#ifndef __DDR_HWIO_TEST_H__
#define __DDR_HWIO_TEST_H__
/*
===========================================================================
*/
/**
  @file ddr_hwio_test.h
  @brief Auto-generated HWIO interface include file.

  Reference chip release:
    SM8250 (Kona) [kona_v1.0_p3q2r17.8_MTO]
 
  This file contains HWIO register definitions for the following modules:
    SECURITY_CONTROL_CORE
    TCSR_TCSR_REGS
    AOSS_CC_AOSS_CC_REG
    CABO_BROADCAST_CABO_GLOBAL
    DPC_REG_DPCC_PHY_GDSCR
    DPC_REG_DPCC_MC_GDSCR
    DPCC_REG_DPCC
    DPCC_REG_DPCC_DPCC_DPCC_REG
    MCCC_MCCC_MSTR
    SHRM_CSR_SHRM_CSR


  Generation parameters: 
  { u'filename': u'ddr_hwio_test.h',
    u'module-filter-exclude': { },
    u'module-filter-include': { },
    u'modules': [ u'SECURITY_CONTROL_CORE',
                  u'TCSR_TCSR_REGS',
                  u'AOSS_CC_AOSS_CC_REG',
                  u'CABO_BROADCAST_CABO_GLOBAL',
                  u'CABO_BROADCAST_CABO_SHKE',
                  u'MC_BROADCAST_MC5_SHKE
                  u'DPC_REG_DPCC_PHY_GDSCR',
                  u'DPC_REG_DPCC_MC_GDSCR',
                  u'DPCC_REG_DPCC',
                  u'DPCC_REG_DPCC_DPCC_DPCC_REG'],
    u'output-fvals': True,
    u'output-offsets': True}
*/
/*
  ===========================================================================

  Copyright (c) 2019 Qualcomm Technologies, Inc.
  All Rights Reserved.
  Confidential and Proprietary - Qualcomm Technologies, Inc.

  Export of this technology or software is regulated by the U.S. Government.
  Diversion contrary to U.S. law prohibited.

  All ideas, data and information contained in or disclosed by
  this document are confidential and proprietary information of
  Qualcomm Technologies, Inc. and all rights therein are expressly reserved.
  By accepting this material the recipient agrees that this material
  and the information contained therein are held in confidence and in
  trust and will not be used, copied, reproduced in whole or in part,
  nor its contents revealed in any manner to others without the express
  written permission of Qualcomm Technologies, Inc.

  ===========================================================================

  $Header: //components/rel/boot.xf/3.2/QcomPkg/SocPkg/8250/Library/DDRTargetLib/ddr_hwio.h#5 $
  $DateTime: 2019/05/02 14:55:57 $
  $Author: pwbldsvc $

  ===========================================================================
*/
#include "msmhwiobase.h"
/*----------------------------------------------------------------------------
 * MODULE: SECURITY_CONTROL_CORE
 *--------------------------------------------------------------------------*/

#define SECURITY_CONTROL_CORE_REG_BASE                                                          (SECURITY_CONTROL_BASE      + 0x00000000)
#define SECURITY_CONTROL_CORE_REG_BASE_SIZE                                                     0x7000
#define SECURITY_CONTROL_CORE_REG_BASE_USED                                                     0x6400
#define SECURITY_CONTROL_CORE_REG_BASE_OFFS                                                     0x00000000

#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_ADDR(n)                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000000 + 0x4 * (n))
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_OFFS(n)                                                 (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000000 + 0x4 * (n))
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_MAXn                                                            71
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_ADDR(n), HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_RMSK)
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_ADDR(n), mask)
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_CRI_CM_PRIVATE_BMSK                                     0xffffffff
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_CRI_CM_PRIVATE_SHFT                                            0x0

#define HWIO_QFPROM_RAW_LCM_ROW_LSB_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000120)
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_OFFS                                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000120)
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_RMSK                                                        0xffffffff
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_LCM_ROW_LSB_ADDR)
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_LCM_ROW_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_LCM_ROW_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_LCM_ROW_LSB_ADDR,m,v,HWIO_QFPROM_RAW_LCM_ROW_LSB_IN)
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_DISABLE_LCM_BMSK                                            0x80000000
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_DISABLE_LCM_SHFT                                                  0x1f
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_DISABLE_LCM_STATE_TRANSITION_BMSK                           0x40000000
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_DISABLE_LCM_STATE_TRANSITION_SHFT                                 0x1e
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_DISABLE_SECURE_PHK_BMSK                                     0x20000000
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_DISABLE_SECURE_PHK_SHFT                                           0x1d
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_RSVD_BMSK                                                   0x1fffffe0
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_RSVD_SHFT                                                          0x5
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_QC_EXTERNAL_BMSK                                                  0x10
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_QC_EXTERNAL_SHFT                                                   0x4
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_QC_INTERNAL_BMSK                                                   0x8
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_QC_INTERNAL_SHFT                                                   0x3
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_QC_FEAT_CONFIG_BMSK                                                0x4
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_QC_FEAT_CONFIG_SHFT                                                0x2
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_HW_TEST_BMSK                                                       0x2
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_HW_TEST_SHFT                                                       0x1
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_SOC_PERSO_BMSK                                                     0x1
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_SOC_PERSO_SHFT                                                     0x0

#define HWIO_QFPROM_RAW_LCM_ROW_MSB_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000124)
#define HWIO_QFPROM_RAW_LCM_ROW_MSB_OFFS                                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000124)
#define HWIO_QFPROM_RAW_LCM_ROW_MSB_RMSK                                                        0xffffffff
#define HWIO_QFPROM_RAW_LCM_ROW_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_LCM_ROW_MSB_ADDR)
#define HWIO_QFPROM_RAW_LCM_ROW_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_LCM_ROW_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_LCM_ROW_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_LCM_ROW_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_LCM_ROW_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_LCM_ROW_MSB_ADDR,m,v,HWIO_QFPROM_RAW_LCM_ROW_MSB_IN)
#define HWIO_QFPROM_RAW_LCM_ROW_MSB_RSVD_BMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_LCM_ROW_MSB_RSVD_SHFT                                                          0x0

#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000128 + 0x8 * (n))
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_OFFS(n)                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000128 + 0x8 * (n))
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_MAXn                                                    1
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_RSVD_BMSK                                      0xffffffff
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_RSVD_SHFT                                             0x0

#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000012c + 0x8 * (n))
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_OFFS(n)                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000012c + 0x8 * (n))
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_MAXn                                                    1
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_RSVD_BMSK                                      0xffffffff
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_RSVD_SHFT                                             0x0

#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n)                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000138 + 0x8 * (n))
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_OFFS(n)                                 (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000138 + 0x8 * (n))
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_RMSK                                    0xffffffff
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_MAXn                                             3
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_BMSK                          0xffffffff
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_SHFT                                 0x0

#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n)                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000013c + 0x8 * (n))
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_OFFS(n)                                 (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000013c + 0x8 * (n))
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RMSK                                    0xffffffff
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_MAXn                                             3
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RSVD1_BMSK                              0x80000000
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RSVD1_SHFT                                    0x1f
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_FEC_VALUE_BMSK                          0x7f000000
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_FEC_VALUE_SHFT                                0x18
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_BMSK                            0xffffff
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_SHFT                                 0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000158)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_OFFS                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000158)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_RMSK                                            0x7fffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_BMSK                    0x40000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_SHFT                          0x1e
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_BMSK                              0x20000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_SHFT                                    0x1d
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_ENABLE_FVAL                              0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_DISABLE_FVAL                             0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_BMSK                       0x1fe00000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_SHFT                             0x15
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_BMSK                        0x180000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_SHFT                            0x13
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_DEFAULT_FVAL                     0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_ENUM_1024_FVAL                   0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_ENUM_2048_FVAL                   0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_ENUM_2560_FVAL                   0x3
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_BMSK                      0x40000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_SHFT                         0x12
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_BMSK                      0x20000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_SHFT                         0x11
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_BMSK                               0x10000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_SHFT                                  0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_ENABLE_FVAL                            0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_DISABLE_FVAL                           0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_BMSK                               0x8000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_SHFT                                  0xf
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_ENABLE_FVAL                           0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_DISABLE_FVAL                          0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_BMSK                               0x4000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_SHFT                                  0xe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_ENABLE_FVAL                           0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_DISABLE_FVAL                          0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_BMSK                                     0x2000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_SHFT                                        0xd
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_ENABLE_FVAL                                 0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_DISABLE_FVAL                                0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_BMSK                                   0x1000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_SHFT                                      0xc
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_ENABLE_FVAL                               0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_DISABLE_FVAL                              0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_BMSK                          0x800
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_SHFT                            0xb
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK                  0x400
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT                    0xa
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_ENABLE_FVAL             0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_DISABLE_FVAL            0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_BMSK                                   0x200
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_SHFT                                     0x9
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_ENABLE_FVAL                              0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_DISABLE_FVAL                             0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_BMSK                                   0x100
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_SHFT                                     0x8
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_ENABLE_FVAL                              0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_DISABLE_FVAL                             0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_BMSK                                       0x80
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_SHFT                                        0x7
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_ENABLE_FVAL                                 0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_DISABLE_FVAL                                0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_BMSK                             0x40
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_SHFT                              0x6
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_ENABLE_FVAL                       0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_DISABLE_FVAL                      0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EFUSE_CAM_SBI_ENABLE_IF_BMSK                          0x20
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EFUSE_CAM_SBI_ENABLE_IF_SHFT                           0x5
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_BMSK                                    0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_SHFT                                     0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_USB_PORT0_FVAL                           0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_USB_PORT1_FVAL                           0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_BMSK                                      0x8
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_SHFT                                      0x3
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_BMSK                            0x7
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_SHFT                            0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_ENABLE_PATCHING_FVAL            0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_DISABLE_PATCHING_FVAL           0x1

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000015c)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_OFFS                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000015c)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_RMSK                                            0xe7fffff7
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_BMSK                          0x80000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_SHFT                                0x1f
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_ICE_ENGINE_USES_SW_KEY_FVAL          0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_ICE_ENGINE_USES_HW_KEY_FVAL          0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_BMSK                          0x40000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_SHFT                                0x1e
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_ICE_ENGINE_USES_SW_KEY_FVAL          0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_ICE_ENGINE_USES_HW_KEY_FVAL          0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_BMSK                                0x20000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_SHFT                                      0x1d
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_DISABLE_FVAL                               0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_BMSK                                 0x4000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_SHFT                                      0x1a
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_DISABLE_FVAL                               0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK              0x2000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT                   0x19
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_ENABLE_FVAL             0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_DISABLE_FVAL            0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_BMSK                  0x1000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_SHFT                       0x18
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_DISABLE_FVAL                0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_BMSK                  0x800000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_SHFT                      0x17
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_BMSK                            0x400000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_SHFT                                0x16
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_BMSK                       0x200000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_SHFT                           0x15
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_BMSK                                    0x100000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_SHFT                                        0x14
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_BMSK                                0x80000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_SHFT                                   0x13
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_ENABLE_FVAL                             0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_DISABLE_FVAL                            0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_BMSK                             0x7c000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_SHFT                                 0xe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_BMSK                          0x2000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_SHFT                             0xd
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_ENABLE_FVAL                      0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_DISABLE_FVAL                     0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_BMSK                             0x1000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_SHFT                                0xc
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_HANA_FEAT_SET_FVAL                  0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_HANAQ_FEAT_SET_FVAL                 0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_BMSK                                      0x800
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_SHFT                                        0xb
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_EFUSE_Q6SS_HVX_HALF_BMSK                             0x400
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_EFUSE_Q6SS_HVX_HALF_SHFT                               0xa
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_BMSK                                    0x200
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_SHFT                                      0x9
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_ENABLE_FVAL                               0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_DISABLE_FVAL                              0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_BMSK                                     0x1e0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_SHFT                                       0x5
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_BMSK                           0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_SHFT                            0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_BMSK                                    0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_SHFT                                    0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_ENABLE_FVAL                             0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_DISABLE_FVAL                            0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_BMSK                                    0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_SHFT                                    0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_ENABLE_FVAL                             0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_DISABLE_FVAL                            0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_BMSK                                    0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_SHFT                                    0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_ENABLE_FVAL                             0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_DISABLE_FVAL                            0x1

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000160)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_OFFS                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000160)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_BMSK                 0xffffc000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_SHFT                        0xe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_DISABLE_FVAL                0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_BMSK                       0x3c00
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_SHFT                          0xa
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_BMSK                     0x3ff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_SHFT                       0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_DISABLE_FVAL               0x1

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000164)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_OFFS                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000164)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_BMSK                        0xc0000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_SHFT                              0x1e
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_BMSK              0x20000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_SHFT                    0x1d
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_ENABLE_FVAL              0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_DISABLE_FVAL             0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_BMSK                  0x10000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_SHFT                        0x1c
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_MOBILE_FVAL                  0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_AUTOMOTIVE_FVAL              0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_BMSK                        0x8000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_SHFT                             0x1b
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_MOBILE_FVAL                       0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_AUTOMOTIVE_FVAL                   0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_BMSK                                0x4000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_SHFT                                     0x1a
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_ENABLE_FVAL                               0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_DISABLE_FVAL                              0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_BMSK                      0x2000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_SHFT                           0x19
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_BMSK                                 0x1000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_SHFT                                      0x18
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_DISABLE_FVAL                               0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_BMSK                   0xffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_SHFT                        0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_DISABLE_FVAL                0x1

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000168)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_OFFS                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000168)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_RMSK                                            0xfbffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_BMSK             0x80000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_SHFT                   0x1f
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_FUSE_CORTEX_M3_DISABLE_BMSK                     0x40000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_FUSE_CORTEX_M3_DISABLE_SHFT                           0x1e
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_Q_CONFIG_FUSE_BMSK                              0x20000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_Q_CONFIG_FUSE_SHFT                                    0x1d
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_I_MC5_FUSE_BMSK                                 0x10000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_I_MC5_FUSE_SHFT                                       0x1c
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_I_MC4_FUSE_BMSK                                  0x8000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_I_MC4_FUSE_SHFT                                       0x1b
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_BMSK               0x2000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_SHFT                    0x19
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_ENABLE_FVAL              0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_DISABLE_FVAL             0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_BMSK               0x1000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_SHFT                    0x18
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_ENABLE_FVAL              0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_DISABLE_FVAL             0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_BMSK                0x800000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_SHFT                    0x17
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_ENABLE_FVAL              0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_DISABLE_FVAL             0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_BMSK                0x400000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_SHFT                    0x16
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_ENABLE_FVAL              0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_DISABLE_FVAL             0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_BMSK                0x200000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_SHFT                    0x15
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_ENABLE_FVAL              0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_DISABLE_FVAL             0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_BMSK                 0x100000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_SHFT                     0x14
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_ENABLE_FVAL               0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_DISABLE_FVAL              0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_BMSK                         0x80000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_SHFT                            0x13
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_ENABLE_FVAL                      0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_DISABLE_FVAL                     0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_BMSK                         0x40000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_SHFT                            0x12
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_ENABLE_FVAL                      0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_DISABLE_FVAL                     0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_BMSK                    0x20000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_SHFT                       0x11
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_DISABLE_FVAL                0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_BMSK                    0x10000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_SHFT                       0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_DISABLE_FVAL                0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_BMSK                     0x8000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_SHFT                        0xf
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_DISABLE_FVAL                0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_BMSK                     0x4000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_SHFT                        0xe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_DISABLE_FVAL                0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_BMSK                    0x2000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_SHFT                       0xd
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_BMSK                    0x1000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_SHFT                       0xc
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                  0x800
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                    0xb
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL             0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL            0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK                   0x400
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT                     0xa
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_ENABLE_FVAL              0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_DISABLE_FVAL             0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_BMSK                        0x200
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_SHFT                          0x9
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_BMSK                        0x100
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_SHFT                          0x8
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_BMSK                         0x80
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_SHFT                          0x7
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_BMSK                         0x40
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_SHFT                          0x6
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_BMSK                        0x20
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_SHFT                         0x5
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_ENABLE_FVAL                  0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_DISABLE_FVAL                 0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_BMSK                        0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_SHFT                         0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_ENABLE_FVAL                  0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_DISABLE_FVAL                 0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK                      0x8
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT                      0x3
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL               0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL              0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK                       0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT                       0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_BMSK                                   0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_SHFT                                   0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_ENABLE_FVAL                            0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_DISABLE_FVAL                           0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_BMSK                                       0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_SHFT                                       0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_DISABLE_FVAL                               0x1

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000016c)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_OFFS                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000016c)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_BMSK                       0xff000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_SHFT                             0x18
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_APSS_KRYO_PP_DISABLE_BMSK                         0x800000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_APSS_KRYO_PP_DISABLE_SHFT                             0x17
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_BMSK                          0x400000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_SHFT                              0x16
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_BMSK                     0x200000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_SHFT                         0x15
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_BMSK                           0x1f8000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_SHFT                                0xf
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_BMSK                         0x4000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_SHFT                            0xe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_BMSK                        0x3fc0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_SHFT                           0x6
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_BMSK                   0x20
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_SHFT                    0x5
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_BMSK                   0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_SHFT                    0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_BMSK                    0x8
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_SHFT                    0x3
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_BMSK                    0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_SHFT                    0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_BMSK                    0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_SHFT                    0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_BMSK                    0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_SHFT                    0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000170)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_OFFS                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000170)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_RMSK                                            0x7fffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_SYS_CFG_GOLDPLUS_PLL_LVAL_BMSK                  0x7f800000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_SYS_CFG_GOLDPLUS_PLL_LVAL_SHFT                        0x17
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_6_BMSK                       0x400000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_6_SHFT                           0x16
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_5_BMSK                       0x200000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_5_SHFT                           0x15
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_4_BMSK                       0x100000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_4_SHFT                           0x14
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_3_BMSK                        0x80000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_3_SHFT                           0x13
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_2_BMSK                        0x40000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_2_SHFT                           0x12
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_1_BMSK                        0x20000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_1_SHFT                           0x11
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_0_BMSK                        0x10000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_0_SHFT                           0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_BMSK                          0xffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_SHFT                             0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000174)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_OFFS                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000174)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_RSVD_BMSK                                       0xfffffffe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_RSVD_SHFT                                              0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_DISABLE_SEC_BOOT_GPIO_BMSK                             0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_DISABLE_SEC_BOOT_GPIO_SHFT                             0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000178)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_OFFS                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000178)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_RSVD_BMSK                                       0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_RSVD_SHFT                                              0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000017c)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_OFFS                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000017c)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_RSVD_BMSK                                       0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_RSVD_SHFT                                              0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000180)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_OFFS                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000180)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_RSVD_BMSK                                       0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_RSVD_SHFT                                              0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000184)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_OFFS                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000184)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_RSVD_BMSK                                       0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_RSVD_SHFT                                              0x0

#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000188)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000188)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_IN)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_RSVD0_BMSK                                             0xfffffff0
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_RSVD0_SHFT                                                    0x4
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ROOT_CERT_ACTIVATION_LIST_BMSK                                0xf
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ROOT_CERT_ACTIVATION_LIST_SHFT                                0x0

#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000018c)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000018c)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_IN)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_RSVD1_BMSK                                             0xfffffffe
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_RSVD1_SHFT                                                    0x1
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_CURRENT_UIE_KEY_SEL_BMSK                                      0x1
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_CURRENT_UIE_KEY_SEL_SHFT                                      0x0

#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000190)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000190)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_IN)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_RSVD0_BMSK                                             0xfffffff0
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_RSVD0_SHFT                                                    0x4
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ROOT_CERT_REVOCATION_LIST_BMSK                                0xf
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ROOT_CERT_REVOCATION_LIST_SHFT                                0x0

#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000194)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000194)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_IN)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_RSVD0_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_RSVD0_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000198)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000198)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW0_LSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_RSVD0_BMSK                                                 0xe0000000
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_RSVD0_SHFT                                                       0x1d
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_MACCHIATO_EN_BMSK                                          0x10000000
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_MACCHIATO_EN_SHFT                                                0x1c
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_FEATURE_ID_BMSK                                             0xff00000
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_FEATURE_ID_SHFT                                                  0x14
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_JTAG_ID_BMSK                                                  0xfffff
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_JTAG_ID_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000019c)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000019c)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW0_MSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_PTE_DATA1_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_PTE_DATA1_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001a0)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001a0)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW1_LSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_PTE_DATA0_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_PTE_DATA0_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001a4)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001a4)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW1_MSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_PTE_DATA1_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_PTE_DATA1_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001a8)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001a8)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_PTE_DATA0_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_PTE_DATA0_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001ac)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001ac)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_PTE_DATA1_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_PTE_DATA1_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001b0)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001b0)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW3_LSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_PTE_DATA0_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_PTE_DATA0_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001b4)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001b4)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW3_MSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_PTE_DATA1_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_PTE_DATA1_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001b8)
#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001b8)
#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW4_LSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW4_LSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_PTE_DATA0_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_PTE_DATA0_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001bc)
#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001bc)
#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW4_MSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW4_MSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_PTE_DATA1_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_PTE_DATA1_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001c0)
#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001c0)
#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW5_LSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW5_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW5_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW5_LSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_PTE_DATA0_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_PTE_DATA0_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001c4)
#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001c4)
#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW5_MSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW5_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW5_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW5_MSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_PTE_DATA1_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_PTE_DATA1_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_RD_PERM_LSB_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001c8)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OFFS                                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001c8)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_RMSK                                                        0xffffffff
#define HWIO_QFPROM_RAW_RD_PERM_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_RD_PERM_LSB_ADDR)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_RD_PERM_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_RD_PERM_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_RD_PERM_LSB_ADDR,m,v,HWIO_QFPROM_RAW_RD_PERM_LSB_IN)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG31_BMSK                                        0x80000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG31_SHFT                                              0x1f
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG31_ALLOW_READ_FVAL                                    0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG31_DISABLE_READ_FVAL                                  0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG30_BMSK                                        0x40000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG30_SHFT                                              0x1e
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG30_ALLOW_READ_FVAL                                    0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG30_DISABLE_READ_FVAL                                  0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG29_BMSK                                        0x20000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG29_SHFT                                              0x1d
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG29_ALLOW_READ_FVAL                                    0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG29_DISABLE_READ_FVAL                                  0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG28_BMSK                                        0x10000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG28_SHFT                                              0x1c
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG28_ALLOW_READ_FVAL                                    0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG28_DISABLE_READ_FVAL                                  0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_USER_DATA_KEY_BMSK                                           0x8000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_USER_DATA_KEY_SHFT                                                0x1b
#define HWIO_QFPROM_RAW_RD_PERM_LSB_USER_DATA_KEY_ALLOW_READ_FVAL                                      0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_USER_DATA_KEY_DISABLE_READ_FVAL                                    0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_IMAGE_ENCR_KEY1_BMSK                                         0x4000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_IMAGE_ENCR_KEY1_SHFT                                              0x1a
#define HWIO_QFPROM_RAW_RD_PERM_LSB_IMAGE_ENCR_KEY1_ALLOW_READ_FVAL                                    0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_IMAGE_ENCR_KEY1_DISABLE_READ_FVAL                                  0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_BOOT_ROM_PATCH_BMSK                                          0x2000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_BOOT_ROM_PATCH_SHFT                                               0x19
#define HWIO_QFPROM_RAW_RD_PERM_LSB_BOOT_ROM_PATCH_ALLOW_READ_FVAL                                     0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_BOOT_ROM_PATCH_DISABLE_READ_FVAL                                   0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_SEC_KEY_DERIVATION_KEY_BMSK                                  0x1000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_SEC_KEY_DERIVATION_KEY_SHFT                                       0x18
#define HWIO_QFPROM_RAW_RD_PERM_LSB_SEC_KEY_DERIVATION_KEY_ALLOW_READ_FVAL                             0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_SEC_KEY_DERIVATION_KEY_DISABLE_READ_FVAL                           0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SEC_BOOT_BMSK                                             0x800000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SEC_BOOT_SHFT                                                 0x17
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SEC_BOOT_ALLOW_READ_FVAL                                       0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SEC_BOOT_DISABLE_READ_FVAL                                     0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_IMAGE_ENCR_KEY_BMSK                                       0x400000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_IMAGE_ENCR_KEY_SHFT                                           0x16
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_IMAGE_ENCR_KEY_ALLOW_READ_FVAL                                 0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_IMAGE_ENCR_KEY_DISABLE_READ_FVAL                               0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG21_BMSK                                           0x200000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG21_SHFT                                               0x15
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG21_ALLOW_READ_FVAL                                     0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG21_DISABLE_READ_FVAL                                   0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG20_BMSK                                           0x100000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG20_SHFT                                               0x14
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG20_ALLOW_READ_FVAL                                     0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG20_DISABLE_READ_FVAL                                   0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_MEM_CONFIG_BMSK                                                0x80000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_MEM_CONFIG_SHFT                                                   0x13
#define HWIO_QFPROM_RAW_RD_PERM_LSB_MEM_CONFIG_ALLOW_READ_FVAL                                         0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_MEM_CONFIG_DISABLE_READ_FVAL                                       0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CALIB_BMSK                                                     0x40000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CALIB_SHFT                                                        0x12
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CALIB_ALLOW_READ_FVAL                                              0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CALIB_DISABLE_READ_FVAL                                            0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PK_HASH0_BMSK                                                  0x20000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PK_HASH0_SHFT                                                     0x11
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PK_HASH0_ALLOW_READ_FVAL                                           0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PK_HASH0_DISABLE_READ_FVAL                                         0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_5_BMSK                                           0x10000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_5_SHFT                                              0x10
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_5_ALLOW_READ_FVAL                                    0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_5_DISABLE_READ_FVAL                                  0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_4_BMSK                                            0x8000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_4_SHFT                                               0xf
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_4_ALLOW_READ_FVAL                                    0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_4_DISABLE_READ_FVAL                                  0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_3_BMSK                                            0x4000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_3_SHFT                                               0xe
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_3_ALLOW_READ_FVAL                                    0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_3_DISABLE_READ_FVAL                                  0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_2_BMSK                                            0x2000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_2_SHFT                                               0xd
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_2_ALLOW_READ_FVAL                                    0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_2_DISABLE_READ_FVAL                                  0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_1_BMSK                                            0x1000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_1_SHFT                                               0xc
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_1_ALLOW_READ_FVAL                                    0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_1_DISABLE_READ_FVAL                                  0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_FEAT_CONFIG_BMSK                                                 0x800
#define HWIO_QFPROM_RAW_RD_PERM_LSB_FEAT_CONFIG_SHFT                                                   0xb
#define HWIO_QFPROM_RAW_RD_PERM_LSB_FEAT_CONFIG_ALLOW_READ_FVAL                                        0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_FEAT_CONFIG_DISABLE_READ_FVAL                                      0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_CONFIG_BMSK                                                  0x400
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_CONFIG_SHFT                                                    0xa
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_CONFIG_ALLOW_READ_FVAL                                         0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_CONFIG_DISABLE_READ_FVAL                                       0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_FEC_EN_BMSK                                                      0x200
#define HWIO_QFPROM_RAW_RD_PERM_LSB_FEC_EN_SHFT                                                        0x9
#define HWIO_QFPROM_RAW_RD_PERM_LSB_FEC_EN_ALLOW_READ_FVAL                                             0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_FEC_EN_DISABLE_READ_FVAL                                           0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_WR_PERM_BMSK                                                     0x100
#define HWIO_QFPROM_RAW_RD_PERM_LSB_WR_PERM_SHFT                                                       0x8
#define HWIO_QFPROM_RAW_RD_PERM_LSB_WR_PERM_ALLOW_READ_FVAL                                            0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_WR_PERM_DISABLE_READ_FVAL                                          0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_RD_PERM_BMSK                                                      0x80
#define HWIO_QFPROM_RAW_RD_PERM_LSB_RD_PERM_SHFT                                                       0x7
#define HWIO_QFPROM_RAW_RD_PERM_LSB_RD_PERM_ALLOW_READ_FVAL                                            0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_RD_PERM_DISABLE_READ_FVAL                                          0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PTE_BMSK                                                          0x40
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PTE_SHFT                                                           0x6
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PTE_ALLOW_READ_FVAL                                                0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PTE_DISABLE_READ_FVAL                                              0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_MRC_2_0_BMSK                                                      0x20
#define HWIO_QFPROM_RAW_RD_PERM_LSB_MRC_2_0_SHFT                                                       0x5
#define HWIO_QFPROM_RAW_RD_PERM_LSB_MRC_2_0_ALLOW_READ_FVAL                                            0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_MRC_2_0_DISABLE_READ_FVAL                                          0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CM_FEAT_CONFIG_BMSK                                               0x10
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CM_FEAT_CONFIG_SHFT                                                0x4
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CM_FEAT_CONFIG_ALLOW_READ_FVAL                                     0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CM_FEAT_CONFIG_DISABLE_READ_FVAL                                   0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PRI_KEY_DERIVATION_KEY_BMSK                                        0x8
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PRI_KEY_DERIVATION_KEY_SHFT                                        0x3
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PRI_KEY_DERIVATION_KEY_ALLOW_READ_FVAL                             0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PRI_KEY_DERIVATION_KEY_DISABLE_READ_FVAL                           0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_BOOT_PATCH_HASH_BMSK                                               0x4
#define HWIO_QFPROM_RAW_RD_PERM_LSB_BOOT_PATCH_HASH_SHFT                                               0x2
#define HWIO_QFPROM_RAW_RD_PERM_LSB_BOOT_PATCH_HASH_ALLOW_READ_FVAL                                    0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_BOOT_PATCH_HASH_DISABLE_READ_FVAL                                  0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_LCM_BMSK                                                           0x2
#define HWIO_QFPROM_RAW_RD_PERM_LSB_LCM_SHFT                                                           0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_LCM_ALLOW_READ_FVAL                                                0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_LCM_DISABLE_READ_FVAL                                              0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CRI_CM_PRIVATE_BMSK                                                0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CRI_CM_PRIVATE_SHFT                                                0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CRI_CM_PRIVATE_ALLOW_READ_FVAL                                     0x0
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CRI_CM_PRIVATE_DISABLE_READ_FVAL                                   0x1

#define HWIO_QFPROM_RAW_RD_PERM_MSB_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001cc)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_OFFS                                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001cc)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_RMSK                                                        0xffffffff
#define HWIO_QFPROM_RAW_RD_PERM_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_RD_PERM_MSB_ADDR)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_RD_PERM_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_RD_PERM_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_RD_PERM_MSB_ADDR,m,v,HWIO_QFPROM_RAW_RD_PERM_MSB_IN)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_RSVD0_BMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_RD_PERM_MSB_RSVD0_SHFT                                                         0x0

#define HWIO_QFPROM_RAW_WR_PERM_LSB_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001d0)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OFFS                                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001d0)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_RMSK                                                        0xffffffff
#define HWIO_QFPROM_RAW_WR_PERM_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_WR_PERM_LSB_ADDR)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_WR_PERM_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_WR_PERM_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_WR_PERM_LSB_ADDR,m,v,HWIO_QFPROM_RAW_WR_PERM_LSB_IN)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG31_BMSK                                        0x80000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG31_SHFT                                              0x1f
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG31_ALLOW_WRITE_FVAL                                   0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG31_DISABLE_WRITE_FVAL                                 0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG30_BMSK                                        0x40000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG30_SHFT                                              0x1e
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG30_ALLOW_WRITE_FVAL                                   0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG30_DISABLE_WRITE_FVAL                                 0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG29_BMSK                                        0x20000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG29_SHFT                                              0x1d
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG29_ALLOW_WRITE_FVAL                                   0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG29_DISABLE_WRITE_FVAL                                 0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG28_BMSK                                        0x10000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG28_SHFT                                              0x1c
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG28_ALLOW_WRITE_FVAL                                   0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG28_DISABLE_WRITE_FVAL                                 0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_USER_DATA_KEY_BMSK                                           0x8000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_USER_DATA_KEY_SHFT                                                0x1b
#define HWIO_QFPROM_RAW_WR_PERM_LSB_USER_DATA_KEY_ALLOW_WRITE_FVAL                                     0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_USER_DATA_KEY_DISABLE_WRITE_FVAL                                   0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_IMAGE_ENCR_KEY1_BMSK                                         0x4000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_IMAGE_ENCR_KEY1_SHFT                                              0x1a
#define HWIO_QFPROM_RAW_WR_PERM_LSB_IMAGE_ENCR_KEY1_ALLOW_WRITE_FVAL                                   0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_IMAGE_ENCR_KEY1_DISABLE_WRITE_FVAL                                 0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_BOOT_ROM_PATCH_BMSK                                          0x2000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_BOOT_ROM_PATCH_SHFT                                               0x19
#define HWIO_QFPROM_RAW_WR_PERM_LSB_BOOT_ROM_PATCH_ALLOW_WRITE_FVAL                                    0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_BOOT_ROM_PATCH_DISABLE_WRITE_FVAL                                  0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_BMSK                                  0x1000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_SHFT                                       0x18
#define HWIO_QFPROM_RAW_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_ALLOW_WRITE_FVAL                            0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_DISABLE_WRITE_FVAL                          0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SEC_BOOT_BMSK                                             0x800000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SEC_BOOT_SHFT                                                 0x17
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SEC_BOOT_ALLOW_WRITE_FVAL                                      0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SEC_BOOT_DISABLE_WRITE_FVAL                                    0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_IMAGE_ENCR_KEY_BMSK                                       0x400000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_IMAGE_ENCR_KEY_SHFT                                           0x16
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_IMAGE_ENCR_KEY_ALLOW_WRITE_FVAL                                0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_IMAGE_ENCR_KEY_DISABLE_WRITE_FVAL                              0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG21_BMSK                                           0x200000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG21_SHFT                                               0x15
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG21_ALLOW_WRITE_FVAL                                    0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG21_DISABLE_WRITE_FVAL                                  0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG20_BMSK                                           0x100000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG20_SHFT                                               0x14
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG20_ALLOW_WRITE_FVAL                                    0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG20_DISABLE_WRITE_FVAL                                  0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_MEM_CONFIG_BMSK                                                0x80000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_MEM_CONFIG_SHFT                                                   0x13
#define HWIO_QFPROM_RAW_WR_PERM_LSB_MEM_CONFIG_ALLOW_WRITE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_MEM_CONFIG_DISABLE_WRITE_FVAL                                      0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CALIB_BMSK                                                     0x40000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CALIB_SHFT                                                        0x12
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CALIB_ALLOW_WRITE_FVAL                                             0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CALIB_DISABLE_WRITE_FVAL                                           0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PK_HASH0_BMSK                                                  0x20000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PK_HASH0_SHFT                                                     0x11
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PK_HASH0_ALLOW_WRITE_FVAL                                          0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PK_HASH0_DISABLE_WRITE_FVAL                                        0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_5_BMSK                                           0x10000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_5_SHFT                                              0x10
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_5_ALLOW_WRITE_FVAL                                   0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_5_DISABLE_WRITE_FVAL                                 0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_4_BMSK                                            0x8000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_4_SHFT                                               0xf
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_4_ALLOW_WRITE_FVAL                                   0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_4_DISABLE_WRITE_FVAL                                 0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_3_BMSK                                            0x4000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_3_SHFT                                               0xe
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_3_ALLOW_WRITE_FVAL                                   0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_3_DISABLE_WRITE_FVAL                                 0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_2_BMSK                                            0x2000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_2_SHFT                                               0xd
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_2_ALLOW_WRITE_FVAL                                   0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_2_DISABLE_WRITE_FVAL                                 0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_1_BMSK                                            0x1000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_1_SHFT                                               0xc
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_1_ALLOW_WRITE_FVAL                                   0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_1_DISABLE_WRITE_FVAL                                 0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_FEAT_CONFIG_BMSK                                                 0x800
#define HWIO_QFPROM_RAW_WR_PERM_LSB_FEAT_CONFIG_SHFT                                                   0xb
#define HWIO_QFPROM_RAW_WR_PERM_LSB_FEAT_CONFIG_ALLOW_WRITE_FVAL                                       0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_FEAT_CONFIG_DISABLE_WRITE_FVAL                                     0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_CONFIG_BMSK                                                  0x400
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_CONFIG_SHFT                                                    0xa
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_CONFIG_ALLOW_WRITE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_CONFIG_DISABLE_WRITE_FVAL                                      0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_FEC_EN_BMSK                                                      0x200
#define HWIO_QFPROM_RAW_WR_PERM_LSB_FEC_EN_SHFT                                                        0x9
#define HWIO_QFPROM_RAW_WR_PERM_LSB_FEC_EN_ALLOW_WRITE_FVAL                                            0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_FEC_EN_DISABLE_WRITE_FVAL                                          0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_WR_PERM_BMSK                                                     0x100
#define HWIO_QFPROM_RAW_WR_PERM_LSB_WR_PERM_SHFT                                                       0x8
#define HWIO_QFPROM_RAW_WR_PERM_LSB_WR_PERM_ALLOW_WRITE_FVAL                                           0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_WR_PERM_DISABLE_WRITE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_RD_PERM_BMSK                                                      0x80
#define HWIO_QFPROM_RAW_WR_PERM_LSB_RD_PERM_SHFT                                                       0x7
#define HWIO_QFPROM_RAW_WR_PERM_LSB_RD_PERM_ALLOW_WRITE_FVAL                                           0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_RD_PERM_DISABLE_WRITE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PTE_BMSK                                                          0x40
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PTE_SHFT                                                           0x6
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PTE_ALLOW_WRITE_FVAL                                               0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PTE_DISABLE_WRITE_FVAL                                             0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_MRC_2_0_BMSK                                                      0x20
#define HWIO_QFPROM_RAW_WR_PERM_LSB_MRC_2_0_SHFT                                                       0x5
#define HWIO_QFPROM_RAW_WR_PERM_LSB_MRC_2_0_ALLOW_WRITE_FVAL                                           0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_MRC_2_0_DISABLE_WRITE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CM_FEAT_CONFIG_BMSK                                               0x10
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CM_FEAT_CONFIG_SHFT                                                0x4
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CM_FEAT_CONFIG_ALLOW_WRITE_FVAL                                    0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CM_FEAT_CONFIG_DISABLE_WRITE_FVAL                                  0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PRI_KEY_DERIVATION_KEY_BMSK                                        0x8
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PRI_KEY_DERIVATION_KEY_SHFT                                        0x3
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PRI_KEY_DERIVATION_KEY_ALLOW_WRITE_FVAL                            0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PRI_KEY_DERIVATION_KEY_DISABLE_WRITE_FVAL                          0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_BOOT_PATCH_HASH_BMSK                                               0x4
#define HWIO_QFPROM_RAW_WR_PERM_LSB_BOOT_PATCH_HASH_SHFT                                               0x2
#define HWIO_QFPROM_RAW_WR_PERM_LSB_BOOT_PATCH_HASH_ALLOW_WRITE_FVAL                                   0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_BOOT_PATCH_HASH_DISABLE_WRITE_FVAL                                 0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_LCM_BMSK                                                           0x2
#define HWIO_QFPROM_RAW_WR_PERM_LSB_LCM_SHFT                                                           0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_LCM_ALLOW_WRITE_FVAL                                               0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_LCM_DISABLE_WRITE_FVAL                                             0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CRI_CM_PRIVATE_BMSK                                                0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CRI_CM_PRIVATE_SHFT                                                0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CRI_CM_PRIVATE_ALLOW_WRITE_FVAL                                    0x0
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CRI_CM_PRIVATE_DISABLE_WRITE_FVAL                                  0x1

#define HWIO_QFPROM_RAW_WR_PERM_MSB_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001d4)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_OFFS                                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001d4)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_RMSK                                                        0xffffffff
#define HWIO_QFPROM_RAW_WR_PERM_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_WR_PERM_MSB_ADDR)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_WR_PERM_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_WR_PERM_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_WR_PERM_MSB_ADDR,m,v,HWIO_QFPROM_RAW_WR_PERM_MSB_IN)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_RSVD0_BMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_WR_PERM_MSB_RSVD0_SHFT                                                         0x0

#define HWIO_QFPROM_RAW_FEC_EN_LSB_ADDR                                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001d8)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_OFFS                                                         (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001d8)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_RMSK                                                         0xffffffff
#define HWIO_QFPROM_RAW_FEC_EN_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEC_EN_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEC_EN_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEC_EN_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEC_EN_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEC_EN_LSB_IN)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION31_FEC_EN_BMSK                                         0x80000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION31_FEC_EN_SHFT                                               0x1f
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION31_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION31_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION30_FEC_EN_BMSK                                         0x40000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION30_FEC_EN_SHFT                                               0x1e
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION30_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION30_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION29_FEC_EN_BMSK                                         0x20000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION29_FEC_EN_SHFT                                               0x1d
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION29_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION29_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION28_FEC_EN_BMSK                                         0x10000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION28_FEC_EN_SHFT                                               0x1c
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION28_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION28_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION27_FEC_EN_BMSK                                          0x8000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION27_FEC_EN_SHFT                                               0x1b
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION27_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION27_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION26_FEC_EN_BMSK                                          0x4000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION26_FEC_EN_SHFT                                               0x1a
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION26_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION26_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION25_FEC_EN_BMSK                                          0x2000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION25_FEC_EN_SHFT                                               0x19
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION25_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION25_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION24_FEC_EN_BMSK                                          0x1000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION24_FEC_EN_SHFT                                               0x18
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION24_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION24_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION23_FEC_EN_BMSK                                           0x800000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION23_FEC_EN_SHFT                                               0x17
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION23_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION23_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION22_FEC_EN_BMSK                                           0x400000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION22_FEC_EN_SHFT                                               0x16
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION22_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION22_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION21_FEC_EN_BMSK                                           0x200000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION21_FEC_EN_SHFT                                               0x15
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION21_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION21_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION20_FEC_EN_BMSK                                           0x100000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION20_FEC_EN_SHFT                                               0x14
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION20_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION20_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION19_FEC_EN_BMSK                                            0x80000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION19_FEC_EN_SHFT                                               0x13
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION19_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION19_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION18_FEC_EN_BMSK                                            0x40000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION18_FEC_EN_SHFT                                               0x12
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION18_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION18_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION17_FEC_EN_BMSK                                            0x20000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION17_FEC_EN_SHFT                                               0x11
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION17_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION17_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION16_FEC_EN_BMSK                                            0x10000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION16_FEC_EN_SHFT                                               0x10
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION16_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION16_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION15_FEC_EN_BMSK                                             0x8000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION15_FEC_EN_SHFT                                                0xf
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION15_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION15_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION14_FEC_EN_BMSK                                             0x4000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION14_FEC_EN_SHFT                                                0xe
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION14_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION14_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION13_FEC_EN_BMSK                                             0x2000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION13_FEC_EN_SHFT                                                0xd
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION13_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION13_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION12_FEC_EN_BMSK                                             0x1000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION12_FEC_EN_SHFT                                                0xc
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION12_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION12_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION11_FEC_EN_BMSK                                              0x800
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION11_FEC_EN_SHFT                                                0xb
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION11_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION11_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION10_FEC_EN_BMSK                                              0x400
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION10_FEC_EN_SHFT                                                0xa
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION10_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION10_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION9_FEC_EN_BMSK                                               0x200
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION9_FEC_EN_SHFT                                                 0x9
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION9_FEC_EN_DISABLE_FVAL                                         0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION9_FEC_EN_ENABLE_FVAL                                          0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION8_FEC_EN_BMSK                                               0x100
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION8_FEC_EN_SHFT                                                 0x8
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION8_FEC_EN_DISABLE_FVAL                                         0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION8_FEC_EN_ENABLE_FVAL                                          0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION7_FEC_EN_BMSK                                                0x80
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION7_FEC_EN_SHFT                                                 0x7
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION7_FEC_EN_DISABLE_FVAL                                         0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION7_FEC_EN_ENABLE_FVAL                                          0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION6_FEC_EN_BMSK                                                0x40
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION6_FEC_EN_SHFT                                                 0x6
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION6_FEC_EN_DISABLE_FVAL                                         0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION6_FEC_EN_ENABLE_FVAL                                          0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION5_FEC_EN_BMSK                                                0x20
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION5_FEC_EN_SHFT                                                 0x5
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION5_FEC_EN_DISABLE_FVAL                                         0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION5_FEC_EN_ENABLE_FVAL                                          0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION4_FEC_EN_BMSK                                                0x10
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION4_FEC_EN_SHFT                                                 0x4
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION4_FEC_EN_DISABLE_FVAL                                         0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION4_FEC_EN_ENABLE_FVAL                                          0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION3_FEC_EN_BMSK                                                 0x8
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION3_FEC_EN_SHFT                                                 0x3
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION3_FEC_EN_DISABLE_FVAL                                         0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION3_FEC_EN_ENABLE_FVAL                                          0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION2_FEC_EN_BMSK                                                 0x4
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION2_FEC_EN_SHFT                                                 0x2
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION2_FEC_EN_DISABLE_FVAL                                         0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION2_FEC_EN_ENABLE_FVAL                                          0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION1_FEC_EN_BMSK                                                 0x2
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION1_FEC_EN_SHFT                                                 0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION1_FEC_EN_DISABLE_FVAL                                         0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION1_FEC_EN_ENABLE_FVAL                                          0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION0_FEC_EN_BMSK                                                 0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION0_FEC_EN_SHFT                                                 0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION0_FEC_EN_DISABLE_FVAL                                         0x0
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION0_FEC_EN_ENABLE_FVAL                                          0x1

#define HWIO_QFPROM_RAW_FEC_EN_MSB_ADDR                                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001dc)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_OFFS                                                         (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001dc)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_RMSK                                                         0xffffffff
#define HWIO_QFPROM_RAW_FEC_EN_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEC_EN_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEC_EN_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEC_EN_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEC_EN_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEC_EN_MSB_IN)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_RSVD0_BMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_FEC_EN_MSB_RSVD0_SHFT                                                          0x0

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001e0)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001e0)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                    0x80000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                          0x1f
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_BMSK                     0x40000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_SHFT                           0x1e
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_BMSK                              0x20000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_SHFT                                    0x1d
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_ENABLE_FVAL                              0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_DISABLE_FVAL                             0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_BMSK                           0x10000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_SHFT                                 0x1c
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_ENABLE_FVAL                           0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_DISABLE_FVAL                          0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SP_DISABLE_BMSK                                      0x8000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SP_DISABLE_SHFT                                           0x1b
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SP_DISABLE_ENABLE_FVAL                                     0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SP_DISABLE_DISABLE_FVAL                                    0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_BMSK                                     0x4000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_SHFT                                          0x1a
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_ENABLE_FVAL                                    0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_DISABLE_FVAL                                   0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_DISABLE_IN_ROM_BMSK                            0x2000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_DISABLE_IN_ROM_SHFT                                 0x19
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_BMSK                 0x1000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_SHFT                      0x18
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_DISABLE_FVAL               0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_ENABLE_FVAL                0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_BMSK                0x800000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_SHFT                    0x17
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_DISABLE_FVAL             0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_ENABLE_FVAL              0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_BMSK                                   0x400000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_SHFT                                       0x16
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_ENABLE_FVAL                                 0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_DISABLE_FVAL                                0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_BMSK                            0x200000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_SHFT                                0x15
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_USE_OEM_ID_FVAL                      0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_USE_SERIAL_NUM_FVAL                  0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_BMSK                             0x100000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_SHFT                                 0x14
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_ENABLE_FVAL                           0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_DISABLE_FVAL                          0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_IMAGE_ENCRYPTION_ENABLE_BMSK                           0x80000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_IMAGE_ENCRYPTION_ENABLE_SHFT                              0x13
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ROOT_CERT_TOTAL_NUM_BMSK                               0x60000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ROOT_CERT_TOTAL_NUM_SHFT                                  0x11
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_USB_TYPE_C_DISABLE_BMSK                            0x10000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_USB_TYPE_C_DISABLE_SHFT                               0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_LOG_DISABLE_BMSK                                    0x8000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_LOG_DISABLE_SHFT                                       0xf
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_WDOG_EN_BMSK                                            0x4000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_WDOG_EN_SHFT                                               0xe
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_WDOG_EN_USE_GPIO_FVAL                                      0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_WDOG_EN_IGNORE_GPIO_ENABLE_WDOG_FVAL                       0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_BMSK               0x2000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_SHFT                  0xd
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_DISABLE_EDL_RESET_FVAL        0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_ENABLE_EDL_RESET_FVAL        0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_FUSE_PROG_DISABLE_BMSK                               0x1000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_FUSE_PROG_DISABLE_SHFT                                  0xc
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SPI_CLK_BOOT_FREQ_BMSK                                   0x800
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SPI_CLK_BOOT_FREQ_SHFT                                     0xb
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_BMSK                           0x400
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_SHFT                             0xa
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_SD_USB_FVAL                      0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_QSPI_SD_USB_FVAL                 0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_BMSK                                           0x3e0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SHFT                                             0x5
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_DEFAULT_FVAL                                     0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SD_UFS_EDL_FVAL                                  0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SD_EDL_FVAL                                      0x2
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_USB_EDL_FVAL                                     0x3
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_QSPI_EDL_FVAL                                    0x4
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SPI_EDL_FVAL                                     0x5
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_UGSG4_SD_USB_EDL_FVAL                            0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SDCC_MCLK_BOOT_FREQ_BMSK                                  0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SDCC_MCLK_BOOT_FREQ_SHFT                                   0x4
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SDCC_MCLK_BOOT_FREQ_ENUM_19_2_MHZ_FVAL                     0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SDCC_MCLK_BOOT_FREQ_ENUM_25_MHZ_FVAL                       0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_BMSK                                0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_SHFT                                0x3
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_USE_FORCE_USB_BOOT_GPIO_TO_FORCE_BOOT_FROM_USB_FVAL        0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_NOT_USE_FORCE_USB_BOOT_PIN_FVAL        0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_BMSK                                   0x4
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_SHFT                                   0x2
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_USE_FORCE_USB_BOOT_GPIO_TO_FORCE_BOOT_FROM_USB_FVAL        0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_NOT_USE_FORCE_USB_BOOT_PIN_FVAL        0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_BMSK                                          0x2
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_SHFT                                          0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_TIMEOUT_DISABLED_FVAL                         0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_TIMEOUT_ENABLED_90S_FVAL                      0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_BMSK                                       0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_SHFT                                       0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_DOWNLOADER_ENABLED_FVAL                    0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_DOWNLOADER_DISABLED_FVAL                   0x1

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001e4)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001e4)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_RSVD1_BMSK                                          0xffffc000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_RSVD1_SHFT                                                 0xe
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_BMSK                         0x2000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_SHFT                            0xd
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_BMSK                         0x1000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_SHFT                            0xc
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_BMSK                          0x800
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_SHFT                            0xb
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_BMSK                          0x400
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_SHFT                            0xa
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_BMSK                          0x200
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_SHFT                            0x9
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_BMSK                           0x100
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_SHFT                             0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_ENABLE_FVAL                      0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_DISABLE_FVAL                     0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_BMSK                                   0x80
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_SHFT                                    0x7
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_ENABLE_FVAL                             0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_DISABLE_FVAL                            0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_BMSK                                   0x40
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_SHFT                                    0x6
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_ENABLE_FVAL                             0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_DISABLE_FVAL                            0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_BMSK                              0x20
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_SHFT                               0x5
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_ENABLE_FVAL                        0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_DISABLE_FVAL                       0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_BMSK                              0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_SHFT                               0x4
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_ENABLE_FVAL                        0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_DISABLE_FVAL                       0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_BMSK                               0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_SHFT                               0x3
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_ENABLE_FVAL                        0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_DISABLE_FVAL                       0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_BMSK                               0x4
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_SHFT                               0x2
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_ENABLE_FVAL                        0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_DISABLE_FVAL                       0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_BMSK                              0x2
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_SHFT                              0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_ENABLE_FVAL                       0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_DISABLE_FVAL                      0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_BMSK                              0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_SHFT                              0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_ENABLE_FVAL                       0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_DISABLE_FVAL                      0x1

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001e8)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001e8)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_DISABLE_RSA_BMSK                                    0x80000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_DISABLE_RSA_SHFT                                          0x1f
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_EKU_ENFORCEMENT_EN_BMSK                             0x40000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_EKU_ENFORCEMENT_EN_SHFT                                   0x1e
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD2_BMSK                                          0x3fff0000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD2_SHFT                                                0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_BMSK                                 0x8000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_SHFT                                    0xf
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_NOT_SECURE_FVAL                         0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_SECURE_FVAL                             0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_BMSK                                 0x4000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_SHFT                                    0xe
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_NOT_SECURE_FVAL                         0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_SECURE_FVAL                             0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_BMSK                                 0x2000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_SHFT                                    0xd
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_NOT_SECURE_FVAL                         0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_SECURE_FVAL                             0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_BMSK                                 0x1000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_SHFT                                    0xc
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_NOT_SECURE_FVAL                         0x0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_SECURE_FVAL                             0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD3_BMSK                                               0x800
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD3_SHFT                                                 0xb
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPU_IAR_ENABLED_BMSK                                     0x400
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPU_IAR_ENABLED_SHFT                                       0xa
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_BMSK                                               0x300
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_SHFT                                                 0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_OVERRIDE_BMSK                           0x80
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_OVERRIDE_SHFT                            0x7
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_FIPS_OVERRIDE_BMSK                                     0x40
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_FIPS_OVERRIDE_SHFT                                      0x6
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_MODEM_CRYPTO_FIPS_ENABLE_BMSK                             0x20
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_MODEM_CRYPTO_FIPS_ENABLE_SHFT                              0x5
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_ENABLE_BMSK                             0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_ENABLE_SHFT                              0x4
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_FIPS_ENABLE_BMSK                                        0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_FIPS_ENABLE_SHFT                                        0x3
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_NVM_AR_CONFIG_BMSK                                      0x6
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_NVM_AR_CONFIG_SHFT                                      0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD0_BMSK                                                 0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD0_SHFT                                                 0x0

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001ec)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001ec)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OEM_PRODUCT_ID_BMSK                                 0xffff0000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OEM_PRODUCT_ID_SHFT                                       0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OEM_HW_ID_BMSK                                          0xffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OEM_HW_ID_SHFT                                             0x0

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001f0)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001f0)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PERIPH_VID_BMSK                                     0xffff0000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PERIPH_VID_SHFT                                           0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PERIPH_PID_BMSK                                         0xffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PERIPH_PID_SHFT                                            0x0

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001f4)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001f4)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_RSVD0_BMSK                                          0xffffff00
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_RSVD0_SHFT                                                 0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ANTI_ROLLBACK_FEATURE_EN_BMSK                             0xff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ANTI_ROLLBACK_FEATURE_EN_SHFT                              0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001f8)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001f8)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_RMSK                                               0x7fffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_BMSK                       0x40000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_SHFT                             0x1e
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_ENABLE_FVAL                       0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_DISABLE_FVAL                      0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_BMSK                                 0x20000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_SHFT                                       0x1d
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_ENABLE_FVAL                                 0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_DISABLE_FVAL                                0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_BMSK                          0x1fe00000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_SHFT                                0x15
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_BMSK                           0x180000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_SHFT                               0x13
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_DEFAULT_FVAL                        0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_ENUM_1024_FVAL                      0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_ENUM_2048_FVAL                      0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_ENUM_2560_FVAL                      0x3
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_BMSK                         0x40000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_SHFT                            0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_ENABLE_FVAL                      0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_DISABLE_FVAL                     0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_BMSK                         0x20000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_SHFT                            0x11
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_ENABLE_FVAL                      0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_DISABLE_FVAL                     0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_BMSK                                  0x10000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_SHFT                                     0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_ENABLE_FVAL                               0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_DISABLE_FVAL                              0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_BMSK                                  0x8000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_SHFT                                     0xf
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_ENABLE_FVAL                              0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_DISABLE_FVAL                             0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_BMSK                                  0x4000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_SHFT                                     0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_ENABLE_FVAL                              0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_DISABLE_FVAL                             0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_BMSK                                        0x2000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_SHFT                                           0xd
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_ENABLE_FVAL                                    0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_DISABLE_FVAL                                   0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_BMSK                                      0x1000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_SHFT                                         0xc
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_ENABLE_FVAL                                  0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_DISABLE_FVAL                                 0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_BMSK                             0x800
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_SHFT                               0xb
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_ENABLE_FVAL                        0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_DISABLE_FVAL                       0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK                     0x400
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT                       0xa
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_BMSK                                      0x200
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_SHFT                                        0x9
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_ENABLE_FVAL                                 0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_DISABLE_FVAL                                0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_BMSK                                      0x100
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_SHFT                                        0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_ENABLE_FVAL                                 0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_DISABLE_FVAL                                0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_BMSK                                          0x80
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_SHFT                                           0x7
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_ENABLE_FVAL                                    0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_DISABLE_FVAL                                   0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_BMSK                                0x40
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_SHFT                                 0x6
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_ENABLE_FVAL                          0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_DISABLE_FVAL                         0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EFUSE_CAM_SBI_ENABLE_IF_BMSK                             0x20
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EFUSE_CAM_SBI_ENABLE_IF_SHFT                              0x5
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_BMSK                                       0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_SHFT                                        0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_USB_PORT0_FVAL                              0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_USB_PORT1_FVAL                              0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_BMSK                                         0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_SHFT                                         0x3
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_BMSK                               0x7
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_SHFT                               0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_ENABLE_PATCHING_FVAL               0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_DISABLE_PATCHING_FVAL              0x1

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001fc)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001fc)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_RMSK                                               0xe7fffff7
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_BMSK                             0x80000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_SHFT                                   0x1f
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_ICE_ENGINE_USES_SW_KEY_FVAL             0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_ICE_ENGINE_USES_HW_KEY_FVAL             0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_BMSK                             0x40000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_SHFT                                   0x1e
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_ICE_ENGINE_USES_SW_KEY_FVAL             0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_ICE_ENGINE_USES_HW_KEY_FVAL             0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_BMSK                                   0x20000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_SHFT                                         0x1d
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_ENABLE_FVAL                                   0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_DISABLE_FVAL                                  0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_BMSK                                    0x4000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_SHFT                                         0x1a
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_ENABLE_FVAL                                   0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_DISABLE_FVAL                                  0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK                 0x2000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT                      0x19
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_BMSK                     0x1000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_SHFT                          0x18
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_BMSK                     0x800000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_SHFT                         0x17
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_BMSK                               0x400000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_SHFT                                   0x16
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_BMSK                          0x200000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_SHFT                              0x15
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_ENABLE_FVAL                        0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_DISABLE_FVAL                       0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_BMSK                                       0x100000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_SHFT                                           0x14
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_BMSK                                   0x80000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_SHFT                                      0x13
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_DISABLE_FVAL                               0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_BMSK                                0x7c000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_SHFT                                    0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_BMSK                             0x2000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_SHFT                                0xd
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_ENABLE_FVAL                         0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_DISABLE_FVAL                        0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_BMSK                                0x1000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_SHFT                                   0xc
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_HANA_FEAT_SET_FVAL                     0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_HANAQ_FEAT_SET_FVAL                    0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_BMSK                                         0x800
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_SHFT                                           0xb
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_EFUSE_Q6SS_HVX_HALF_BMSK                                0x400
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_EFUSE_Q6SS_HVX_HALF_SHFT                                  0xa
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_BMSK                                       0x200
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_SHFT                                         0x9
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_ENABLE_FVAL                                  0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_DISABLE_FVAL                                 0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_BMSK                                        0x1e0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_SHFT                                          0x5
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_BMSK                              0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_SHFT                               0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_ENABLE_FVAL                        0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_DISABLE_FVAL                       0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_BMSK                                       0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_SHFT                                       0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_DISABLE_FVAL                               0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_BMSK                                       0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_SHFT                                       0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_DISABLE_FVAL                               0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_BMSK                                       0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_SHFT                                       0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_DISABLE_FVAL                               0x1

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000200)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000200)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_BMSK                    0xffffc000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_SHFT                           0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_BMSK                          0x3c00
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_SHFT                             0xa
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_ENABLE_FVAL                      0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_DISABLE_FVAL                     0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_BMSK                        0x3ff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_SHFT                          0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_DISABLE_FVAL                  0x1

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000204)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000204)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_BMSK                           0xc0000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_SHFT                                 0x1e
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_BMSK                 0x20000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_SHFT                       0x1d
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_DISABLE_FVAL                0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_BMSK                     0x10000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_SHFT                           0x1c
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_MOBILE_FVAL                     0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_AUTOMOTIVE_FVAL                 0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_BMSK                           0x8000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_SHFT                                0x1b
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_MOBILE_FVAL                          0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_AUTOMOTIVE_FVAL                      0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_BMSK                                   0x4000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_SHFT                                        0x1a
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_ENABLE_FVAL                                  0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_DISABLE_FVAL                                 0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_BMSK                         0x2000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_SHFT                              0x19
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_ENABLE_FVAL                        0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_DISABLE_FVAL                       0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_BMSK                                    0x1000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_SHFT                                         0x18
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_ENABLE_FVAL                                   0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_DISABLE_FVAL                                  0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_BMSK                      0xffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_SHFT                           0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_DISABLE_FVAL                   0x1

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000208)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000208)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_RMSK                                               0xfbffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_BMSK                0x80000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_SHFT                      0x1f
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_FUSE_CORTEX_M3_DISABLE_BMSK                        0x40000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_FUSE_CORTEX_M3_DISABLE_SHFT                              0x1e
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_Q_CONFIG_FUSE_BMSK                                 0x20000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_Q_CONFIG_FUSE_SHFT                                       0x1d
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_I_MC5_FUSE_BMSK                                    0x10000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_I_MC5_FUSE_SHFT                                          0x1c
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_I_MC4_FUSE_BMSK                                     0x8000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_I_MC4_FUSE_SHFT                                          0x1b
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_BMSK                  0x2000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_SHFT                       0x19
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_DISABLE_FVAL                0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_BMSK                  0x1000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_SHFT                       0x18
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_DISABLE_FVAL                0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_BMSK                   0x800000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_SHFT                       0x17
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_DISABLE_FVAL                0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_BMSK                   0x400000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_SHFT                       0x16
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_DISABLE_FVAL                0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_BMSK                   0x200000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_SHFT                       0x15
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_DISABLE_FVAL                0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_BMSK                    0x100000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_SHFT                        0x14
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_ENABLE_FVAL                  0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_DISABLE_FVAL                 0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_BMSK                            0x80000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_SHFT                               0x13
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_ENABLE_FVAL                         0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_DISABLE_FVAL                        0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_BMSK                            0x40000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_SHFT                               0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_ENABLE_FVAL                         0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_DISABLE_FVAL                        0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_BMSK                       0x20000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_SHFT                          0x11
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_BMSK                       0x10000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_SHFT                          0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_BMSK                        0x8000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_SHFT                           0xf
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_BMSK                        0x4000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_SHFT                           0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_BMSK                       0x2000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_SHFT                          0xd
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_BMSK                       0x1000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_SHFT                          0xc
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                     0x800
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                       0xb
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK                      0x400
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT                        0xa
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_DISABLE_FVAL                0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_BMSK                           0x200
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_SHFT                             0x9
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_ENABLE_FVAL                      0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_DISABLE_FVAL                     0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_BMSK                           0x100
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_SHFT                             0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_ENABLE_FVAL                      0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_DISABLE_FVAL                     0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_BMSK                            0x80
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_SHFT                             0x7
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_ENABLE_FVAL                      0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_DISABLE_FVAL                     0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_BMSK                            0x40
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_SHFT                             0x6
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_ENABLE_FVAL                      0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_DISABLE_FVAL                     0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_BMSK                           0x20
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_SHFT                            0x5
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_BMSK                           0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_SHFT                            0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK                         0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT                         0x3
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL                  0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL                 0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK                          0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT                          0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_BMSK                                      0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_SHFT                                      0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_ENABLE_FVAL                               0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_DISABLE_FVAL                              0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_BMSK                                          0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_SHFT                                          0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_ENABLE_FVAL                                   0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_DISABLE_FVAL                                  0x1

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000020c)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000020c)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_BMSK                          0xff000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_SHFT                                0x18
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_APSS_KRYO_PP_DISABLE_BMSK                            0x800000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_APSS_KRYO_PP_DISABLE_SHFT                                0x17
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_BMSK                             0x400000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_SHFT                                 0x16
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_BMSK                        0x200000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_SHFT                            0x15
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_BMSK                              0x1f8000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_SHFT                                   0xf
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_BMSK                            0x4000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_SHFT                               0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_BMSK                           0x3fc0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_SHFT                              0x6
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_BMSK                      0x20
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_SHFT                       0x5
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_BMSK                      0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_SHFT                       0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_BMSK                       0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_SHFT                       0x3
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_BMSK                       0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_SHFT                       0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_BMSK                       0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_SHFT                       0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_BMSK                       0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_SHFT                       0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000210)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000210)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_RMSK                                               0x7fffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_SYS_CFG_GOLDPLUS_PLL_LVAL_BMSK                     0x7f800000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_SYS_CFG_GOLDPLUS_PLL_LVAL_SHFT                           0x17
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_6_BMSK                          0x400000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_6_SHFT                              0x16
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_5_BMSK                          0x200000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_5_SHFT                              0x15
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_4_BMSK                          0x100000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_4_SHFT                              0x14
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_3_BMSK                           0x80000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_3_SHFT                              0x13
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_2_BMSK                           0x40000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_2_SHFT                              0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_1_BMSK                           0x20000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_1_SHFT                              0x11
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_0_BMSK                           0x10000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_0_SHFT                              0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_BMSK                             0xffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_SHFT                                0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000214)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000214)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_RSVD_BMSK                                          0xfffffffe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_RSVD_SHFT                                                 0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_DISABLE_SEC_BOOT_GPIO_BMSK                                0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_DISABLE_SEC_BOOT_GPIO_SHFT                                0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000218)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000218)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_RSVD_BMSK                                          0xfffffffe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_RSVD_SHFT                                                 0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_LEGACY_MBNV6_OVERRIDE_BMSK                                0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_LEGACY_MBNV6_OVERRIDE_SHFT                                0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000021c)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000021c)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_RSVD_BMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_RSVD_SHFT                                                 0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000220)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000220)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_RSVD_BMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_RSVD_SHFT                                                 0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000224)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000224)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_RSVD_BMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_RSVD_SHFT                                                 0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000228)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000228)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_TAP_GEN_SPARE_INSTR_DISABLE_13_0_BMSK              0xfffc0000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_TAP_GEN_SPARE_INSTR_DISABLE_13_0_SHFT                    0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_TAP_INSTR_DISABLE_BMSK                                0x3ffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_TAP_INSTR_DISABLE_SHFT                                    0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000022c)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000022c)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_SEC_TAP_ACCESS_DISABLE_BMSK                        0xfffc0000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_SEC_TAP_ACCESS_DISABLE_SHFT                              0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_TAP_GEN_SPARE_INSTR_DISABLE_31_14_BMSK                0x3ffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_TAP_GEN_SPARE_INSTR_DISABLE_31_14_SHFT                    0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000230)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000230)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_MODEM_PBL_PATCH_VERSION_BMSK                       0xfe000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_MODEM_PBL_PATCH_VERSION_SHFT                             0x19
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_APPS_PBL_PATCH_VERSION_BMSK                         0x1fc0000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_APPS_PBL_PATCH_VERSION_SHFT                              0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_APPS_PBL_BOOT_SPEED_BMSK                              0x30000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_APPS_PBL_BOOT_SPEED_SHFT                                 0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_APPS_PBL_BOOT_SPEED_ENUM_600_MHZ_FVAL                     0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_APPS_PBL_BOOT_SPEED_XO_FVAL                               0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_APPS_PBL_BOOT_SPEED_ENUM_1200_MHZ_FVAL                    0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_APPS_PBL_BOOT_SPEED_NA_FVAL                               0x3
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_MODEM_PBL_BOOT_BMSK                                    0x8000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_MODEM_PBL_BOOT_SHFT                                       0xf
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_RSVD1_56_14_BMSK                                       0x4000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_RSVD1_56_14_SHFT                                          0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_APPS_BOOT_FROM_ROM_BMSK                                0x2000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_APPS_BOOT_FROM_ROM_SHFT                                   0xd
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ENABLE_DEVICE_IN_TEST_MODE_BMSK                        0x1000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ENABLE_DEVICE_IN_TEST_MODE_SHFT                           0xc
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_QTI_ROOT_SIG_FORMAT_SEL_BMSK                            0x800
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_QTI_ROOT_SIG_FORMAT_SEL_SHFT                              0xb
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_CE_BAM_DISABLE_BMSK                                     0x400
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_CE_BAM_DISABLE_SHFT                                       0xa
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_CE_BAM_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_CE_BAM_DISABLE_DISABLE_FVAL                               0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_BMSK                 0x200
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_SHFT                   0x9
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ARM_CE_DISABLE_USAGE_BMSK                               0x100
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ARM_CE_DISABLE_USAGE_SHFT                                 0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_BOOT_ROM_CFG_BMSK                                        0xff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_BOOT_ROM_CFG_SHFT                                         0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000234)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000234)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_APPS_BOOT_TRIGGER_DISABLE_BMSK                     0x80000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_APPS_BOOT_TRIGGER_DISABLE_SHFT                           0x1f
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_APPS_BOOT_TRIGGER_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_APPS_BOOT_TRIGGER_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_PBL_QSEE_BOOT_FLOW_DISABLE_BMSK                    0x40000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_PBL_QSEE_BOOT_FLOW_DISABLE_SHFT                          0x1e
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_XBL_SEC_AUTH_DISABLE_BMSK                          0x20000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_XBL_SEC_AUTH_DISABLE_SHFT                                0x1d
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_MSM_PKG_TYPE_BMSK                                  0x10000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_MSM_PKG_TYPE_SHFT                                        0x1c
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_SPSS_CONFIG_MODE_BMSK                               0xc000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_SPSS_CONFIG_MODE_SHFT                                    0x1a
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_PERIPH_DRV_STRENGTH_SETTING_BMSK                    0x3800000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_PERIPH_DRV_STRENGTH_SETTING_SHFT                         0x17
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_RSVD3_56_54_BMSK                                     0x400000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_RSVD3_56_54_SHFT                                         0x16
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_BMSK                                      0x3c0000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_SHFT                                          0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_TSMC_FVAL                                      0x0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_GLOBAL_FOUNDRIES_FVAL                          0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_SAMSUNG_FVAL                                   0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_IBM_FVAL                                       0x3
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_UMC_FVAL                                       0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_SMIC_FVAL                                      0x5
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_PLL_CFG_BMSK                                          0x3fff0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_PLL_CFG_SHFT                                              0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_APPS_PBL_PLL_CTRL_BMSK                                    0xf
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_APPS_PBL_PLL_CTRL_SHFT                                    0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000238)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000238)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_XBL0_BMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_XBL0_SHFT                                                  0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000023c)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000023c)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_XBL1_BMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_XBL1_SHFT                                                  0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000240)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000240)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_PIL_SUBSYSTEM_31_0_BMSK                             0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_PIL_SUBSYSTEM_31_0_SHFT                                    0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000244)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000244)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_XBL_SEC_BMSK                                        0xfe000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_XBL_SEC_SHFT                                              0x19
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_AOP_BMSK                                             0x1fe0000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_AOP_SHFT                                                  0x11
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_TZ_BMSK                                                0x1ffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_TZ_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000248)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000248)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_XBL_CONFIG_1_0_BMSK                                 0xc0000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_XBL_CONFIG_1_0_SHFT                                       0x1e
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_TQS_HASH_ACTIVE_BMSK                                0x3e000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_TQS_HASH_ACTIVE_SHFT                                      0x19
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_BMSK                            0x1000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_SHFT                                 0x18
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_RPMB_KEY_NOT_PROVISIONED_FVAL         0x0
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_RPMB_KEY_PROVISIONED_FVAL             0x1
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_PIL_SUBSYSTEM_47_32_BMSK                              0xffff00
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_PIL_SUBSYSTEM_47_32_SHFT                                   0x8
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_SAFESWITCH_BMSK                                           0xff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_SAFESWITCH_SHFT                                            0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000024c)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000024c)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_XBL_CONFIG_5_2_BMSK                                 0xf0000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_XBL_CONFIG_5_2_SHFT                                       0x1c
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_DEVICE_CFG_BMSK                                      0xffe0000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_DEVICE_CFG_SHFT                                           0x11
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_DEBUG_POLICY_BMSK                                      0x1f000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_DEBUG_POLICY_SHFT                                          0xc
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_HYPERVISOR_BMSK                                          0xfff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_HYPERVISOR_SHFT                                            0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000250)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000250)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_MSS_BMSK                                            0xffff0000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_MSS_SHFT                                                  0x10
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_MISC_BMSK                                               0xffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_MISC_SHFT                                                  0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000254)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000254)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_SIMLOCK_BMSK                                        0x80000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_SIMLOCK_SHFT                                              0x1f
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_RSVD0_BMSK                                          0x7ffffff0
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_RSVD0_SHFT                                                 0x4
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ROOT_CERT_PK_HASH_INDEX_BMSK                               0xf
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ROOT_CERT_PK_HASH_INDEX_SHFT                               0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000258)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000258)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_MISC_BMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_MISC_SHFT                                                  0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000025c)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000025c)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_RSVD0_BMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_RSVD0_SHFT                                                 0x0

#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_ADDR(n)                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000260 + 0x8 * (n))
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_OFFS(n)                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000260 + 0x8 * (n))
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_MAXn                                                           5
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_HASH_DATA0_BMSK                                       0xffffffff
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_HASH_DATA0_SHFT                                              0x0

#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_ADDR(n)                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000264 + 0x8 * (n))
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_OFFS(n)                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000264 + 0x8 * (n))
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_MAXn                                                           5
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_HASH_DATA1_BMSK                                       0xffffffff
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_HASH_DATA1_SHFT                                              0x0

#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000290)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000290)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW0_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW0_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_RSVD2_BMSK                                               0xfe000000
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_RSVD2_SHFT                                                     0x19
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_USB2PHY_RCAL_CODE_BMSK                                    0x1e00000
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_USB2PHY_RCAL_CODE_SHFT                                         0x15
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_RSVD1_BMSK                                                 0x1ff000
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_RSVD1_SHFT                                                      0xc
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_TURING_Q6SS1_LDO_VREF_TRIM_BMSK                               0xf80
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_TURING_Q6SS1_LDO_VREF_TRIM_SHFT                                 0x7
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_TURING_Q6SS1_LDO_ENABLE_NOM_BMSK                               0x40
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_TURING_Q6SS1_LDO_ENABLE_NOM_SHFT                                0x6
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_RSVD_BMSK                                                      0x3f
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_RSVD_SHFT                                                       0x0

#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000294)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000294)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW0_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW0_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW0_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_RSVD_BMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_RSVD_SHFT                                                       0x0

#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000298)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000298)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW1_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW1_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_RSVD_BMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_RSVD_SHFT                                                       0x0

#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000029c)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000029c)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW1_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW1_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_RSVD1_BMSK                                               0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_RSVD1_SHFT                                                     0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_REFGEN_NORTH_BGV_TRIM_BMSK                               0x7f800000
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_REFGEN_NORTH_BGV_TRIM_SHFT                                     0x17
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_REFGEN_SOUTH_BGV_TRIM_BMSK                                 0x7f8000
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_REFGEN_SOUTH_BGV_TRIM_SHFT                                      0xf
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_BANDGAP_TRIM_BMSK                                            0x7f00
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_BANDGAP_TRIM_SHFT                                               0x8
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_RSVD_BMSK                                                      0xff
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_RSVD_SHFT                                                       0x0

#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002a0)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002a0)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW2_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_AOSS_K_13_0_BMSK                                         0xfffc0000
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_AOSS_K_13_0_SHFT                                               0x12
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_AOSS_N1_BMSK                                                0x3ffff
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_AOSS_N1_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002a4)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002a4)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW2_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_RSVD_BMSK                                                0xff000000
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_RSVD_SHFT                                                      0x18
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_AOSS_DCOPCODE_BMSK                                         0x800000
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_AOSS_DCOPCODE_SHFT                                             0x17
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_AOSS_TDOPCODE_BMSK                                         0x700000
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_AOSS_TDOPCODE_SHFT                                             0x14
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_AOSS_P1_BMSK                                                0xffffc
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_AOSS_P1_SHFT                                                    0x2
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_AOSS_K_15_14_BMSK                                               0x3
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_AOSS_K_15_14_SHFT                                               0x0

#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002a8)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002a8)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW3_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW3_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW3_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_TSENS1_BASE1_1_0_BMSK                                    0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_TSENS1_BASE1_1_0_SHFT                                          0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_TSENS0_BASE1_BMSK                                        0x3ff00000
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_TSENS0_BASE1_SHFT                                              0x14
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_TSENS1_BASE0_BMSK                                           0xffc00
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_TSENS1_BASE0_SHFT                                               0xa
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_TSENS0_BASE0_BMSK                                             0x3ff
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_TSENS0_BASE0_SHFT                                               0x0

#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002ac)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002ac)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW3_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW3_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW3_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_TSENS4_OFFSET_3_0_BMSK                                   0xf0000000
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_TSENS4_OFFSET_3_0_SHFT                                         0x1c
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_TSENS3_OFFSET_BMSK                                        0xf800000
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_TSENS3_OFFSET_SHFT                                             0x17
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_TSENS2_OFFSET_BMSK                                         0x7c0000
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_TSENS2_OFFSET_SHFT                                             0x12
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_TSENS1_OFFSET_BMSK                                          0x3e000
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_TSENS1_OFFSET_SHFT                                              0xd
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_TSENS0_OFFSET_BMSK                                           0x1f00
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_TSENS0_OFFSET_SHFT                                              0x8
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_TSENS1_BASE1_9_2_BMSK                                          0xff
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_TSENS1_BASE1_9_2_SHFT                                           0x0

#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002b0)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002b0)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW4_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW4_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_TSENS11_OFFSET_0_BMSK                                    0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_TSENS11_OFFSET_0_SHFT                                          0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_TSENS10_OFFSET_BMSK                                      0x7c000000
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_TSENS10_OFFSET_SHFT                                            0x1a
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_TSENS9_OFFSET_BMSK                                        0x3e00000
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_TSENS9_OFFSET_SHFT                                             0x15
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_TSENS8_OFFSET_BMSK                                         0x1f0000
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_TSENS8_OFFSET_SHFT                                             0x10
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_TSENS7_OFFSET_BMSK                                           0xf800
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_TSENS7_OFFSET_SHFT                                              0xb
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_TSENS6_OFFSET_BMSK                                            0x7c0
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_TSENS6_OFFSET_SHFT                                              0x6
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_TSENS5_OFFSET_BMSK                                             0x3e
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_TSENS5_OFFSET_SHFT                                              0x1
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_TSENS4_OFFSET_4_BMSK                                            0x1
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_TSENS4_OFFSET_4_SHFT                                            0x0

#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002b4)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002b4)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW4_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW4_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_TSENS17_OFFSET_2_0_BMSK                                  0xe0000000
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_TSENS17_OFFSET_2_0_SHFT                                        0x1d
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_TSENS16_OFFSET_BMSK                                      0x1f000000
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_TSENS16_OFFSET_SHFT                                            0x18
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_TSENS15_OFFSET_BMSK                                        0xf80000
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_TSENS15_OFFSET_SHFT                                            0x13
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_TSENS14_OFFSET_BMSK                                         0x7c000
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_TSENS14_OFFSET_SHFT                                             0xe
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_TSENS13_OFFSET_BMSK                                          0x3e00
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_TSENS13_OFFSET_SHFT                                             0x9
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_TSENS12_OFFSET_BMSK                                           0x1f0
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_TSENS12_OFFSET_SHFT                                             0x4
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_TSENS11_OFFSET_4_1_BMSK                                         0xf
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_TSENS11_OFFSET_4_1_SHFT                                         0x0

#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002b8)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002b8)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW5_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW5_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW5_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW5_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_TSENS23_OFFSET_BMSK                                      0xf8000000
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_TSENS23_OFFSET_SHFT                                            0x1b
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_TSENS22_OFFSET_BMSK                                       0x7c00000
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_TSENS22_OFFSET_SHFT                                            0x16
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_TSENS21_OFFSET_BMSK                                        0x3e0000
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_TSENS21_OFFSET_SHFT                                            0x11
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_TSENS20_OFFSET_BMSK                                         0x1f000
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_TSENS20_OFFSET_SHFT                                             0xc
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_TSENS19_OFFSET_BMSK                                           0xf80
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_TSENS19_OFFSET_SHFT                                             0x7
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_TSENS18_OFFSET_BMSK                                            0x7c
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_TSENS18_OFFSET_SHFT                                             0x2
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_TSENS17_OFFSET_4_3_BMSK                                         0x3
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_TSENS17_OFFSET_4_3_SHFT                                         0x0

#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002bc)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002bc)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW5_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW5_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW5_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW5_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_RSVD_BMSK                                                0xffffff00
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_RSVD_SHFT                                                       0x8
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_TSENS_CAL_SEL_BMSK                                             0xe0
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_TSENS_CAL_SEL_SHFT                                              0x5
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_TSENS24_OFFSET_BMSK                                            0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_TSENS24_OFFSET_SHFT                                             0x0

#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002c0)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002c0)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW6_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW6_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW6_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW6_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW6_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_VSENSE_FUSE1_S5_BMSK                                     0xe0000000
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_VSENSE_FUSE1_S5_SHFT                                           0x1d
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_VSENSE_FUSE1_S4_BMSK                                     0x1c000000
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_VSENSE_FUSE1_S4_SHFT                                           0x1a
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_VSENSE_FUSE1_S3_BMSK                                      0x3800000
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_VSENSE_FUSE1_S3_SHFT                                           0x17
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_VSENSE_FUSE1_S2_BMSK                                       0x700000
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_VSENSE_FUSE1_S2_SHFT                                           0x14
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_VSENSE_FUSE1_S1_BMSK                                        0xe0000
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_VSENSE_FUSE1_S1_SHFT                                           0x11
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_VSENSE_FUSE1_S0_BMSK                                        0x1c000
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_VSENSE_FUSE1_S0_SHFT                                            0xe
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_VSENSE_FUSE2_BMSK                                            0x3f00
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_VSENSE_FUSE2_SHFT                                               0x8
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_VSENSE_FUSE1_BMSK                                              0xff
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_VSENSE_FUSE1_SHFT                                               0x0

#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002c4)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002c4)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW6_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW6_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW6_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW6_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW6_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE2_S6_BMSK                                     0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE2_S6_SHFT                                           0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE2_S5_BMSK                                     0x30000000
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE2_S5_SHFT                                           0x1c
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE2_S4_BMSK                                      0xc000000
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE2_S4_SHFT                                           0x1a
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE2_S3_BMSK                                      0x3000000
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE2_S3_SHFT                                           0x18
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE2_S2_BMSK                                       0xc00000
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE2_S2_SHFT                                           0x16
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE2_S1_BMSK                                       0x300000
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE2_S1_SHFT                                           0x14
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE2_S0_BMSK                                        0xc0000
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE2_S0_SHFT                                           0x12
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_RSVD_BMSK                                                   0x3f000
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_RSVD_SHFT                                                       0xc
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE1_S9_BMSK                                          0xe00
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE1_S9_SHFT                                            0x9
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE1_S8_BMSK                                          0x1c0
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE1_S8_SHFT                                            0x6
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE1_S7_BMSK                                           0x38
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE1_S7_SHFT                                            0x3
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE1_S6_BMSK                                            0x7
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_VSENSE_FUSE1_S6_SHFT                                            0x0

#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002c8)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002c8)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW7_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW7_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW7_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW7_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW7_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_RSVD_BMSK                                                0xffffffc0
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_RSVD_SHFT                                                       0x6
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_VSENSE_FUSE2_S9_BMSK                                           0x30
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_VSENSE_FUSE2_S9_SHFT                                            0x4
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_VSENSE_FUSE2_S8_BMSK                                            0xc
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_VSENSE_FUSE2_S8_SHFT                                            0x2
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_VSENSE_FUSE2_S7_BMSK                                            0x3
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_VSENSE_FUSE2_S7_SHFT                                            0x0

#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002cc)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002cc)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW7_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW7_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW7_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW7_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW7_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_RSVD_BMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_RSVD_SHFT                                                       0x0

#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002d0)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002d0)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW8_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW8_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW8_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW8_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW8_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_RSVD_BMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_RSVD_SHFT                                                       0x0

#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002d4)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002d4)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW8_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW8_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW8_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW8_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW8_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_RSVD_BMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_RSVD_SHFT                                                       0x0

#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002d8)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002d8)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW9_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW9_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW9_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW9_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW9_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_RSVD_BMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_RSVD_SHFT                                                       0x0

#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002dc)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_OFFS                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002dc)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW9_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW9_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW9_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW9_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW9_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_RSVD_BMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_RSVD_SHFT                                                       0x0

#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002e0)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002e0)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW10_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW10_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW10_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW10_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW10_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002e4)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002e4)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW10_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW10_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW10_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW10_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW10_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002e8)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002e8)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW11_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW11_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW11_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW11_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW11_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002ec)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002ec)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW11_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW11_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW11_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW11_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW11_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002f0)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002f0)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW12_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW12_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW12_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW12_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW12_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002f4)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002f4)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW12_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW12_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW12_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW12_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW12_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002f8)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002f8)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW13_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW13_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW13_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW13_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW13_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR_MM_MODE_DISABLE_0_BMSK                              0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR_MM_MODE_DISABLE_0_SHFT                                    0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR_SSC_CX_MODE_DISABLE_BMSK                            0x70000000
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR_SSC_CX_MODE_DISABLE_SHFT                                  0x1c
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR_DDR_MODE_DISABLE_BMSK                                0xe000000
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR_DDR_MODE_DISABLE_SHFT                                     0x19
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR_GFX_MODE_DISABLE_BMSK                                0x1c00000
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR_GFX_MODE_DISABLE_SHFT                                     0x16
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR_CX_MODE_DISABLE_BMSK                                  0x380000
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR_CX_MODE_DISABLE_SHFT                                      0x13
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR_LOCAL_RC_BMSK                                          0x70000
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR_LOCAL_RC_SHFT                                             0x10
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR_GLOBAL_RC_BMSK                                          0xe000
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR_GLOBAL_RC_SHFT                                             0xd
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_AON_AGING_BMSK                                              0x1fe0
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_AON_AGING_SHFT                                                 0x5
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_AON_TARG_VOLT_BMSK                                            0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_AON_TARG_VOLT_SHFT                                             0x0

#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002fc)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002fc)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW13_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW13_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW13_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW13_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW13_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_RSVD_BMSK                                               0xfffffffc
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_RSVD_SHFT                                                      0x2
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_MM_MODE_DISABLE_2_1_BMSK                                   0x3
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_MM_MODE_DISABLE_2_1_SHFT                                   0x0

#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000300)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000300)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW14_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW14_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW14_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW14_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW14_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_CPR0_TARG_VOLT_OFFSET_NOM_BMSK                          0xf0000000
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_CPR0_TARG_VOLT_OFFSET_NOM_SHFT                                0x1c
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_CPR0_TARG_VOLT_OFFSET_TUR_BMSK                           0xf000000
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_CPR0_TARG_VOLT_OFFSET_TUR_SHFT                                0x18
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_CPR0_TARG_VOLT_OFFSET_SUT_BMSK                            0xf00000
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_CPR0_TARG_VOLT_OFFSET_SUT_SHFT                                0x14
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_CPR0_TARG_VOLT_SVS3_BMSK                                   0xf8000
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_CPR0_TARG_VOLT_SVS3_SHFT                                       0xf
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_CPR0_TARG_VOLT_SVS_BMSK                                     0x7c00
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_CPR0_TARG_VOLT_SVS_SHFT                                        0xa
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_CPR0_TARG_VOLT_NOM_BMSK                                      0x3e0
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_CPR0_TARG_VOLT_NOM_SHFT                                        0x5
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_CPR0_TARG_VOLT_SUT_BMSK                                       0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_CPR0_TARG_VOLT_SUT_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000304)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000304)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW14_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW14_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW14_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW14_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW14_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_RSVD_BMSK                                               0xfff00000
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_RSVD_SHFT                                                     0x14
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_CPR0_AGING_BMSK                                            0xff000
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_CPR0_AGING_SHFT                                                0xc
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_CPR0_TARG_VOLT_OFFSET_SVS3_BMSK                              0xf00
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_CPR0_TARG_VOLT_OFFSET_SVS3_SHFT                                0x8
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_CPR0_TARG_VOLT_OFFSET_SVS2_BMSK                               0xf0
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_CPR0_TARG_VOLT_OFFSET_SVS2_SHFT                                0x4
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_CPR0_TARG_VOLT_OFFSET_SVS_BMSK                                 0xf
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_CPR0_TARG_VOLT_OFFSET_SVS_SHFT                                 0x0

#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000308)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000308)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW15_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW15_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW15_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW15_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW15_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_CPR1_TARG_VOLT_OFFSET_NOM_BMSK                          0xf0000000
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_CPR1_TARG_VOLT_OFFSET_NOM_SHFT                                0x1c
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_CPR1_TARG_VOLT_OFFSET_TUR_BMSK                           0xf000000
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_CPR1_TARG_VOLT_OFFSET_TUR_SHFT                                0x18
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_CPR1_TARG_VOLT_OFFSET_SUT_BMSK                            0xf00000
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_CPR1_TARG_VOLT_OFFSET_SUT_SHFT                                0x14
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_CPR1_TARG_VOLT_SVS3_BMSK                                   0xf8000
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_CPR1_TARG_VOLT_SVS3_SHFT                                       0xf
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_CPR1_TARG_VOLT_SVS_BMSK                                     0x7c00
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_CPR1_TARG_VOLT_SVS_SHFT                                        0xa
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_CPR1_TARG_VOLT_NOM_BMSK                                      0x3e0
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_CPR1_TARG_VOLT_NOM_SHFT                                        0x5
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_CPR1_TARG_VOLT_SUT_BMSK                                       0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_CPR1_TARG_VOLT_SUT_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000030c)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000030c)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW15_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW15_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW15_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW15_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW15_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_RSVD_BMSK                                               0xfff00000
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_RSVD_SHFT                                                     0x14
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_CPR1_AGING_BMSK                                            0xff000
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_CPR1_AGING_SHFT                                                0xc
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_CPR1_TARG_VOLT_OFFSET_SVS3_BMSK                              0xf00
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_CPR1_TARG_VOLT_OFFSET_SVS3_SHFT                                0x8
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_CPR1_TARG_VOLT_OFFSET_SVS2_BMSK                               0xf0
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_CPR1_TARG_VOLT_OFFSET_SVS2_SHFT                                0x4
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_CPR1_TARG_VOLT_OFFSET_SVS_BMSK                                 0xf
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_CPR1_TARG_VOLT_OFFSET_SVS_SHFT                                 0x0

#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000310)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000310)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW16_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW16_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW16_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW16_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW16_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_CPR3_TARG_VOLT_NOM_1_0_BMSK                             0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_CPR3_TARG_VOLT_NOM_1_0_SHFT                                   0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_CPR3_TARG_VOLT_TUR_BMSK                                 0x3e000000
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_CPR3_TARG_VOLT_TUR_SHFT                                       0x19
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_CPR3_TARG_VOLT_SUT_BMSK                                  0x1f00000
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_CPR3_TARG_VOLT_SUT_SHFT                                       0x14
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_CPR2_TARG_VOLT_SVS3_BMSK                                   0xf8000
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_CPR2_TARG_VOLT_SVS3_SHFT                                       0xf
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_CPR2_TARG_VOLT_SVS_BMSK                                     0x7c00
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_CPR2_TARG_VOLT_SVS_SHFT                                        0xa
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_CPR2_TARG_VOLT_NOM_BMSK                                      0x3e0
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_CPR2_TARG_VOLT_NOM_SHFT                                        0x5
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_CPR2_TARG_VOLT_TUR_BMSK                                       0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_CPR2_TARG_VOLT_TUR_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000314)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000314)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW16_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW16_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW16_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW16_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW16_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_RSVD_BMSK                                               0xff000000
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_RSVD_SHFT                                                     0x18
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_CPR3_TARG_VOLT_OFFSET_SVSP_BMSK                           0xf00000
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_CPR3_TARG_VOLT_OFFSET_SVSP_SHFT                               0x14
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_CPR3_TARG_VOLT_OFFSET_NOM_BMSK                             0xf0000
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_CPR3_TARG_VOLT_OFFSET_NOM_SHFT                                0x10
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_CPR3_TARG_VOLT_OFFSET_TUR_BMSK                              0xf000
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_CPR3_TARG_VOLT_OFFSET_TUR_SHFT                                 0xc
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_CPR3_TARG_VOLT_OFFSET_SUT_BMSK                               0xf00
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_CPR3_TARG_VOLT_OFFSET_SUT_SHFT                                 0x8
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_CPR3_TARG_VOLT_SVSP_BMSK                                      0xf8
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_CPR3_TARG_VOLT_SVSP_SHFT                                       0x3
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_CPR3_TARG_VOLT_NOM_4_2_BMSK                                    0x7
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_CPR3_TARG_VOLT_NOM_4_2_SHFT                                    0x0

#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000318)
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000318)
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW17_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW17_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW17_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW17_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW17_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_CPR5_TARG_VOLT_OFFSET_TUR_1_0_BMSK                      0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_CPR5_TARG_VOLT_OFFSET_TUR_1_0_SHFT                            0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_CPR5_TARG_VOLT_SVS3_BMSK                                0x3e000000
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_CPR5_TARG_VOLT_SVS3_SHFT                                      0x19
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_CPR5_TARG_VOLT_SVS_BMSK                                  0x1f00000
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_CPR5_TARG_VOLT_SVS_SHFT                                       0x14
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_CPR5_TARG_VOLT_NOM_BMSK                                    0xf8000
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_CPR5_TARG_VOLT_NOM_SHFT                                        0xf
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_CPR5_TARG_VOLT_TUR_BMSK                                     0x7c00
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_CPR5_TARG_VOLT_TUR_SHFT                                        0xa
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_CPR4_TARG_VOLT_NOM_BMSK                                      0x3e0
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_CPR4_TARG_VOLT_NOM_SHFT                                        0x5
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_CPR4_TARG_VOLT_TUR_BMSK                                       0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_CPR4_TARG_VOLT_TUR_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000031c)
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000031c)
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW17_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW17_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW17_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW17_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW17_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_RSVD_BMSK                                               0xfc000000
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_RSVD_SHFT                                                     0x1a
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_CPR5_AGING_BMSK                                          0x3fc0000
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_CPR5_AGING_SHFT                                               0x12
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_SVS3_BMSK                            0x3c000
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_SVS3_SHFT                                0xe
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_SVS2_BMSK                             0x3c00
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_SVS2_SHFT                                0xa
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_SVS_BMSK                               0x3c0
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_SVS_SHFT                                 0x6
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_NOM_BMSK                                0x3c
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_NOM_SHFT                                 0x2
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_TUR_3_2_BMSK                             0x3
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_TUR_3_2_SHFT                             0x0

#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000320)
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000320)
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW18_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW18_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW18_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW18_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW18_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_CPR6_TARG_VOLT_OFFSET_SVSP_BMSK                         0xf0000000
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_CPR6_TARG_VOLT_OFFSET_SVSP_SHFT                               0x1c
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_CPR6_TARG_VOLT_OFFSET_NOM_BMSK                           0xf000000
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_CPR6_TARG_VOLT_OFFSET_NOM_SHFT                                0x18
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_CPR6_TARG_VOLT_OFFSET_TUR_BMSK                            0xf00000
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_CPR6_TARG_VOLT_OFFSET_TUR_SHFT                                0x14
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_CPR6_TARG_VOLT_SVS2_BMSK                                   0xf8000
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_CPR6_TARG_VOLT_SVS2_SHFT                                       0xf
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_CPR6_TARG_VOLT_SVS_BMSK                                     0x7c00
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_CPR6_TARG_VOLT_SVS_SHFT                                        0xa
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_CPR6_TARG_VOLT_NOM_BMSK                                      0x3e0
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_CPR6_TARG_VOLT_NOM_SHFT                                        0x5
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_CPR6_TARG_VOLT_TUR_BMSK                                       0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_CPR6_TARG_VOLT_TUR_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000324)
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000324)
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW18_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW18_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW18_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW18_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW18_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_RSVD_BMSK                                               0xffff0000
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_RSVD_SHFT                                                     0x10
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_CPR6_AGING_BMSK                                             0xff00
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_CPR6_AGING_SHFT                                                0x8
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_CPR6_TARG_VOLT_OFFSET_SVS2_BMSK                               0xf0
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_CPR6_TARG_VOLT_OFFSET_SVS2_SHFT                                0x4
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_CPR6_TARG_VOLT_OFFSET_SVS_BMSK                                 0xf
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_CPR6_TARG_VOLT_OFFSET_SVS_SHFT                                 0x0

#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000328)
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000328)
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW19_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW19_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW19_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW19_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW19_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_CPR7_TARG_VOLT_SVS_3_0_BMSK                             0xf0000000
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_CPR7_TARG_VOLT_SVS_3_0_SHFT                                   0x1c
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_CPR7_TARG_VOLT_NOM_BMSK                                  0xfc00000
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_CPR7_TARG_VOLT_NOM_SHFT                                       0x16
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_CPR7_TARG_VOLT_TUR_BMSK                                   0x3f0000
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_CPR7_TARG_VOLT_TUR_SHFT                                       0x10
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_CPR7_SVS2_ROSEL_BMSK                                        0xf000
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_CPR7_SVS2_ROSEL_SHFT                                           0xc
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_CPR7_SVS_ROSEL_BMSK                                          0xf00
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_CPR7_SVS_ROSEL_SHFT                                            0x8
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_CPR7_NOMINAL_ROSEL_BMSK                                       0xf0
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_CPR7_NOMINAL_ROSEL_SHFT                                        0x4
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_CPR7_TURBO_ROSEL_BMSK                                          0xf
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_CPR7_TURBO_ROSEL_SHFT                                          0x0

#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000032c)
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000032c)
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW19_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW19_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW19_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW19_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW19_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_CPR7_NOMINAL_QUOT_VMIN_BMSK                             0xfff00000
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_CPR7_NOMINAL_QUOT_VMIN_SHFT                                   0x14
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_CPR7_TURBO_QUOT_VMIN_BMSK                                  0xfff00
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_CPR7_TURBO_QUOT_VMIN_SHFT                                      0x8
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_CPR7_TARG_VOLT_SVS2_BMSK                                      0xfc
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_CPR7_TARG_VOLT_SVS2_SHFT                                       0x2
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_CPR7_TARG_VOLT_SVS_5_4_BMSK                                    0x3
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_CPR7_TARG_VOLT_SVS_5_4_SHFT                                    0x0

#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000330)
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000330)
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW20_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW20_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW20_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW20_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW20_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_CPR7_QUOT_OFFSET_TUR_BMSK                               0xff000000
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_CPR7_QUOT_OFFSET_TUR_SHFT                                     0x18
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_CPR7_SVS2_QUOT_VMIN_BMSK                                  0xfff000
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_CPR7_SVS2_QUOT_VMIN_SHFT                                       0xc
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_CPR7_SVS_QUOT_VMIN_BMSK                                      0xfff
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_CPR7_SVS_QUOT_VMIN_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000334)
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000334)
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW20_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW20_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW20_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW20_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW20_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_RSVD_BMSK                                               0xffc00000
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_RSVD_SHFT                                                     0x16
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_CPR7_AGING_BMSK                                           0x3fc000
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_CPR7_AGING_SHFT                                                0xe
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_CPR7_QUOT_OFFSET_SVS_BMSK                                   0x3f80
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_CPR7_QUOT_OFFSET_SVS_SHFT                                      0x7
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_CPR7_QUOT_OFFSET_NOM_BMSK                                     0x7f
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_CPR7_QUOT_OFFSET_NOM_SHFT                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000338)
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000338)
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW21_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW21_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW21_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW21_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW21_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_CPR8_TURBO_QUOT_VMIN_7_0_BMSK                           0xff000000
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_CPR8_TURBO_QUOT_VMIN_7_0_SHFT                                 0x18
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_CPR8_TARG_VOLT_SVS2_BMSK                                  0xfc0000
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_CPR8_TARG_VOLT_SVS2_SHFT                                      0x12
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_CPR8_TARG_VOLT_SVS_BMSK                                    0x3f000
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_CPR8_TARG_VOLT_SVS_SHFT                                        0xc
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_CPR8_TARG_VOLT_NOM_BMSK                                      0xfc0
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_CPR8_TARG_VOLT_NOM_SHFT                                        0x6
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_CPR8_TARG_VOLT_TUR_BMSK                                       0x3f
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_CPR8_TARG_VOLT_TUR_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000033c)
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000033c)
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW21_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW21_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW21_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW21_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW21_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_CPR8_SVS2_QUOT_VMIN_3_0_BMSK                            0xf0000000
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_CPR8_SVS2_QUOT_VMIN_3_0_SHFT                                  0x1c
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_CPR8_SVS_QUOT_VMIN_BMSK                                  0xfff0000
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_CPR8_SVS_QUOT_VMIN_SHFT                                       0x10
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_CPR8_NOMINAL_QUOT_VMIN_BMSK                                 0xfff0
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_CPR8_NOMINAL_QUOT_VMIN_SHFT                                    0x4
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_CPR8_TURBO_QUOT_VMIN_11_8_BMSK                                 0xf
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_CPR8_TURBO_QUOT_VMIN_11_8_SHFT                                 0x0

#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000340)
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000340)
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW22_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW22_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW22_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW22_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW22_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_CPR9_TURBO_ROSEL_1_0_BMSK                               0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_CPR9_TURBO_ROSEL_1_0_SHFT                                     0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_CPR8_QUOT_OFFSET_SVS_BMSK                               0x3f800000
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_CPR8_QUOT_OFFSET_SVS_SHFT                                     0x17
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_CPR8_QUOT_OFFSET_NOM_BMSK                                 0x7f0000
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_CPR8_QUOT_OFFSET_NOM_SHFT                                     0x10
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_CPR8_QUOT_OFFSET_TUR_BMSK                                   0xff00
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_CPR8_QUOT_OFFSET_TUR_SHFT                                      0x8
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_CPR8_SVS2_QUOT_VMIN_11_4_BMSK                                 0xff
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_CPR8_SVS2_QUOT_VMIN_11_4_SHFT                                  0x0

#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000344)
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000344)
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW22_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW22_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW22_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW22_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW22_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_CPR9_TARG_VOLT_SVS_BMSK                                 0xfc000000
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_CPR9_TARG_VOLT_SVS_SHFT                                       0x1a
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_CPR9_TARG_VOLT_NOM_BMSK                                  0x3f00000
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_CPR9_TARG_VOLT_NOM_SHFT                                       0x14
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_CPR9_TARG_VOLT_TUR_BMSK                                    0xfc000
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_CPR9_TARG_VOLT_TUR_SHFT                                        0xe
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_CPR9_SVS2_ROSEL_BMSK                                        0x3c00
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_CPR9_SVS2_ROSEL_SHFT                                           0xa
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_CPR9_SVS_ROSEL_BMSK                                          0x3c0
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_CPR9_SVS_ROSEL_SHFT                                            0x6
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_CPR9_NOMINAL_ROSEL_BMSK                                       0x3c
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_CPR9_NOMINAL_ROSEL_SHFT                                        0x2
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_CPR9_TURBO_ROSEL_3_2_BMSK                                      0x3
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_CPR9_TURBO_ROSEL_3_2_SHFT                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000348)
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000348)
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW23_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW23_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW23_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW23_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW23_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_CPR9_SVS_QUOT_VMIN_1_0_BMSK                             0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_CPR9_SVS_QUOT_VMIN_1_0_SHFT                                   0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_CPR9_NOMINAL_QUOT_VMIN_BMSK                             0x3ffc0000
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_CPR9_NOMINAL_QUOT_VMIN_SHFT                                   0x12
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_CPR9_TURBO_QUOT_VMIN_BMSK                                  0x3ffc0
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_CPR9_TURBO_QUOT_VMIN_SHFT                                      0x6
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_CPR9_TARG_VOLT_SVS2_BMSK                                      0x3f
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_CPR9_TARG_VOLT_SVS2_SHFT                                       0x0

#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000034c)
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000034c)
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW23_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW23_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW23_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW23_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW23_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_CPR9_QUOT_OFFSET_NOM_1_0_BMSK                           0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_CPR9_QUOT_OFFSET_NOM_1_0_SHFT                                 0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_CPR9_QUOT_OFFSET_TUR_BMSK                               0x3fc00000
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_CPR9_QUOT_OFFSET_TUR_SHFT                                     0x16
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_CPR9_SVS2_QUOT_VMIN_BMSK                                  0x3ffc00
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_CPR9_SVS2_QUOT_VMIN_SHFT                                       0xa
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_CPR9_SVS_QUOT_VMIN_11_2_BMSK                                 0x3ff
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_CPR9_SVS_QUOT_VMIN_11_2_SHFT                                   0x0

#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000350)
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000350)
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW24_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW24_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW24_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW24_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW24_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_CPR10_TARG_VOLT_NOM_BMSK                                0xfc000000
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_CPR10_TARG_VOLT_NOM_SHFT                                      0x1a
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_CPR10_TARG_VOLT_TUR_BMSK                                 0x3f00000
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_CPR10_TARG_VOLT_TUR_SHFT                                      0x14
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_CPR9_AGING_BMSK                                            0xff000
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_CPR9_AGING_SHFT                                                0xc
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_CPR9_QUOT_OFFSET_SVS_BMSK                                    0xfe0
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_CPR9_QUOT_OFFSET_SVS_SHFT                                      0x5
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_CPR9_QUOT_OFFSET_NOM_6_2_BMSK                                 0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_CPR9_QUOT_OFFSET_NOM_6_2_SHFT                                  0x0

#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000354)
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000354)
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW24_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW24_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW24_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW24_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW24_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_CPR10_NOMINAL_QUOT_VMIN_7_0_BMSK                        0xff000000
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_CPR10_NOMINAL_QUOT_VMIN_7_0_SHFT                              0x18
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_CPR10_TURBO_QUOT_VMIN_BMSK                                0xfff000
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_CPR10_TURBO_QUOT_VMIN_SHFT                                     0xc
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_CPR10_TARG_VOLT_SVS2_BMSK                                    0xfc0
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_CPR10_TARG_VOLT_SVS2_SHFT                                      0x6
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_CPR10_TARG_VOLT_SVS_BMSK                                      0x3f
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_CPR10_TARG_VOLT_SVS_SHFT                                       0x0

#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000358)
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000358)
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW25_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW25_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW25_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW25_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW25_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_CPR10_QUOT_OFFSET_TUR_3_0_BMSK                          0xf0000000
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_CPR10_QUOT_OFFSET_TUR_3_0_SHFT                                0x1c
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_CPR10_SVS2_QUOT_VMIN_BMSK                                0xfff0000
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_CPR10_SVS2_QUOT_VMIN_SHFT                                     0x10
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_CPR10_SVS_QUOT_VMIN_BMSK                                    0xfff0
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_CPR10_SVS_QUOT_VMIN_SHFT                                       0x4
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_CPR10_NOMINAL_QUOT_VMIN_11_8_BMSK                              0xf
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_CPR10_NOMINAL_QUOT_VMIN_11_8_SHFT                              0x0

#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000035c)
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000035c)
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW25_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW25_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW25_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW25_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW25_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_RSVD_BMSK                                               0xfffc0000
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_RSVD_SHFT                                                     0x12
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_CPR10_QUOT_OFFSET_SVS_BMSK                                 0x3f800
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_CPR10_QUOT_OFFSET_SVS_SHFT                                     0xb
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_CPR10_QUOT_OFFSET_NOM_BMSK                                   0x7f0
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_CPR10_QUOT_OFFSET_NOM_SHFT                                     0x4
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_CPR10_QUOT_OFFSET_TUR_7_4_BMSK                                 0xf
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_CPR10_QUOT_OFFSET_TUR_7_4_SHFT                                 0x0

#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000360)
#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000360)
#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW26_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW26_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW26_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW26_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW26_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_CPR_RSVD_31_0_BMSK                                      0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_CPR_RSVD_31_0_SHFT                                             0x0

#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000364)
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000364)
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW26_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW26_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW26_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW26_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW26_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_RSVD_BMSK                                               0xfffc0000
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_RSVD_SHFT                                                     0x12
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_CPR_RSVD_49_32_BMSK                                        0x3ffff
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_CPR_RSVD_49_32_SHFT                                            0x0

#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000368)
#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000368)
#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW27_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW27_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW27_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW27_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW27_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000036c)
#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000036c)
#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW27_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW27_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW27_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW27_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW27_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000370)
#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000370)
#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW28_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW28_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW28_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW28_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW28_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000374)
#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000374)
#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW28_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW28_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW28_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW28_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW28_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000378)
#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000378)
#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW29_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW29_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW29_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW29_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW29_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000037c)
#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000037c)
#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW29_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW29_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW29_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW29_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW29_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000380)
#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000380)
#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW30_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW30_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW30_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW30_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW30_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000384)
#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000384)
#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW30_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW30_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW30_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW30_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW30_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_ADDR(n)                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000388 + 0x8 * (n))
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_OFFS(n)                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000388 + 0x8 * (n))
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_MAXn                                                        70
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_REDUN_DATA_BMSK                                     0xffffffff
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_REDUN_DATA_SHFT                                            0x0

#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_ADDR(n)                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000038c + 0x8 * (n))
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_OFFS(n)                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000038c + 0x8 * (n))
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_MAXn                                                        70
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_REDUN_DATA_BMSK                                     0xffffffff
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_REDUN_DATA_SHFT                                            0x0

#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005c0)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_OFFS                                                 (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005c0)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_ADDR)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_ADDR,m,v,HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_IN)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_QC_SPARE_BMSK                                        0xffffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_QC_SPARE_SHFT                                               0x0

#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005c4)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_OFFS                                                 (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005c4)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_ADDR)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_ADDR,m,v,HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_IN)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_RSVD0_BMSK                                           0x80000000
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_RSVD0_SHFT                                                 0x1f
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_FEC_VALUE_BMSK                                       0x7f000000
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_FEC_VALUE_SHFT                                             0x18
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_QC_SPARE_BMSK                                          0xffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_QC_SPARE_SHFT                                               0x0

#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005c8)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_OFFS                                                 (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005c8)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_ADDR)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_ADDR,m,v,HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_IN)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_QC_SPARE_BMSK                                        0xffffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_QC_SPARE_SHFT                                               0x0

#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005cc)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_OFFS                                                 (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005cc)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_ADDR)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_ADDR,m,v,HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_IN)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_RSVD0_BMSK                                           0x80000000
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_RSVD0_SHFT                                                 0x1f
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_FEC_VALUE_BMSK                                       0x7f000000
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_FEC_VALUE_SHFT                                             0x18
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_QC_SPARE_BMSK                                          0xffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_QC_SPARE_SHFT                                               0x0

#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n)                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005d0 + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_OFFS(n)                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005d0 + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_RMSK                                        0xffffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_MAXn                                                 1
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_KEY_DATA0_BMSK                              0xffffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_KEY_DATA0_SHFT                                     0x0

#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n)                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005d4 + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_OFFS(n)                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005d4 + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RMSK                                        0xffffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_MAXn                                                 1
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RSVD1_BMSK                                  0x80000000
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RSVD1_SHFT                                        0x1f
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_FEC_VALUE_BMSK                              0x7f000000
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_FEC_VALUE_SHFT                                    0x18
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_KEY_DATA1_BMSK                                0xffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_KEY_DATA1_SHFT                                     0x0

#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005e0)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_OFFS                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005e0)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RMSK                                        0xffffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RSVD0_BMSK                                  0xffff0000
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RSVD0_SHFT                                        0x10
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_KEY_DATA0_BMSK                                  0xffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_KEY_DATA0_SHFT                                     0x0

#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005e4)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_OFFS                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005e4)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RMSK                                        0xffffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD1_BMSK                                  0x80000000
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD1_SHFT                                        0x1f
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_FEC_VALUE_BMSK                              0x7f000000
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_FEC_VALUE_SHFT                                    0x18
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD0_BMSK                                    0xffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD0_SHFT                                         0x0

#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_ADDR(n)                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005e8 + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_OFFS(n)                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005e8 + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_MAXn                                                       1
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT4_BMSK                                    0xff000000
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT4_SHFT                                          0x18
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT3_BMSK                                      0xff0000
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT3_SHFT                                          0x10
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT2_BMSK                                        0xff00
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT2_SHFT                                           0x8
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT1_BMSK                                          0xff
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT1_SHFT                                           0x0

#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_ADDR(n)                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005ec + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_OFFS(n)                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005ec + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_MAXn                                                       1
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_RSVD1_BMSK                                        0x80000000
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_RSVD1_SHFT                                              0x1f
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_FEC_VALUE_BMSK                                    0x7f000000
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_FEC_VALUE_SHFT                                          0x18
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT7_BMSK                                      0xff0000
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT7_SHFT                                          0x10
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT6_BMSK                                        0xff00
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT6_SHFT                                           0x8
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT5_BMSK                                          0xff
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT5_SHFT                                           0x0

#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n)                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005f8 + 0x8 * (n))
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_OFFS(n)                                 (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005f8 + 0x8 * (n))
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_RMSK                                    0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_MAXn                                             3
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_BMSK                          0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_SHFT                                 0x0

#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n)                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005fc + 0x8 * (n))
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_OFFS(n)                                 (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005fc + 0x8 * (n))
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RMSK                                    0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_MAXn                                             3
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RSVD1_BMSK                              0x80000000
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RSVD1_SHFT                                    0x1f
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_FEC_VALUE_BMSK                          0x7f000000
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_FEC_VALUE_SHFT                                0x18
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_BMSK                            0xffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_SHFT                                 0x0

#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000618)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_OFFS                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000618)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_RMSK                                    0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_IN)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_KEY_DATA0_BMSK                          0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_KEY_DATA0_SHFT                                 0x0

#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000061c)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_OFFS                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000061c)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RMSK                                    0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_IN)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD1_BMSK                              0x80000000
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD1_SHFT                                    0x1f
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_FEC_VALUE_BMSK                          0x7f000000
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_FEC_VALUE_SHFT                                0x18
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_BMSK                                0xffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_SHFT                                     0x0

#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_ADDR(n)                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000620 + 0x8 * (n))
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_OFFS(n)                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000620 + 0x8 * (n))
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_MAXn                                                         55
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_PATCH_DATA_BMSK                                      0xffffffff
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_PATCH_DATA_SHFT                                             0x0

#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_ADDR(n)                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000624 + 0x8 * (n))
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_OFFS(n)                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000624 + 0x8 * (n))
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_MAXn                                                         55
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RSVD1_BMSK                                           0x80000000
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RSVD1_SHFT                                                 0x1f
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_FEC_VALUE_BMSK                                       0x7f000000
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_FEC_VALUE_SHFT                                             0x18
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RSVD0_BMSK                                             0xfe0000
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RSVD0_SHFT                                                 0x11
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_PATCH_ADDR_BMSK                                         0x1fffe
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_PATCH_ADDR_SHFT                                             0x1
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_PATCH_EN_BMSK                                               0x1
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_PATCH_EN_SHFT                                               0x0

#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000007e0 + 0x8 * (n))
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_OFFS(n)                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007e0 + 0x8 * (n))
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_MAXn                                                    1
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_KEY_DATA0_BMSK                                 0xffffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_KEY_DATA0_SHFT                                        0x0

#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000007e4 + 0x8 * (n))
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_OFFS(n)                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007e4 + 0x8 * (n))
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_MAXn                                                    1
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_RSVD1_BMSK                                     0x80000000
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_RSVD1_SHFT                                           0x1f
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_FEC_VALUE_BMSK                                 0x7f000000
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_FEC_VALUE_SHFT                                       0x18
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_KEY_DATA1_BMSK                                   0xffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_KEY_DATA1_SHFT                                        0x0

#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x000007f0)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_OFFS                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007f0)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_RSVD0_BMSK                                     0xffff0000
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_RSVD0_SHFT                                           0x10
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_KEY_DATA0_BMSK                                     0xffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_KEY_DATA0_SHFT                                        0x0

#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x000007f4)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_OFFS                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007f4)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD1_BMSK                                     0x80000000
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD1_SHFT                                           0x1f
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_FEC_VALUE_BMSK                                 0x7f000000
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_FEC_VALUE_SHFT                                       0x18
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD0_BMSK                                       0xffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD0_SHFT                                            0x0

#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_ADDR(n)                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x000007f8 + 0x8 * (n))
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_OFFS(n)                                          (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007f8 + 0x8 * (n))
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_MAXn                                                      3
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_USER_DATA_KEY_BMSK                               0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_USER_DATA_KEY_SHFT                                      0x0

#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_ADDR(n)                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x000007fc + 0x8 * (n))
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_OFFS(n)                                          (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007fc + 0x8 * (n))
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_MAXn                                                      3
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_RSVD1_BMSK                                       0x80000000
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_RSVD1_SHFT                                             0x1f
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_FEC_VALUE_BMSK                                   0x7f000000
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_FEC_VALUE_SHFT                                         0x18
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_USER_DATA_KEY_BMSK                                 0xffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_USER_DATA_KEY_SHFT                                      0x0

#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000818)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_OFFS                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000818)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_ADDR)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_IN)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_USER_DATA_KEY_BMSK                               0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_USER_DATA_KEY_SHFT                                      0x0

#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000081c)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_OFFS                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000081c)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_ADDR)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_IN)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_RSVD1_BMSK                                       0x80000000
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_RSVD1_SHFT                                             0x1f
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_FEC_VALUE_BMSK                                   0x7f000000
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_FEC_VALUE_SHFT                                         0x18
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_RSVD0_BMSK                                         0xffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_RSVD0_SHFT                                              0x0

#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_ADDR(n)                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000660 + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_OFFS(n)                                         (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000660 + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_MAXn                                                    31
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_OEM_SPARE_BMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_OEM_SPARE_SHFT                                         0x0

#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_ADDR(n)                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000664 + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_OFFS(n)                                         (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000664 + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_MAXn                                                    31
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_OEM_SPARE_BMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_OEM_SPARE_SHFT                                         0x0

#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_ADDR(n)                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000668 + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_OFFS(n)                                         (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000668 + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_MAXn                                                    31
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_OEM_SPARE_BMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_OEM_SPARE_SHFT                                         0x0

#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_ADDR(n)                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000066c + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_OFFS(n)                                         (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000066c + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_MAXn                                                    31
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_OEM_SPARE_BMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_OEM_SPARE_SHFT                                         0x0

#define HWIO_QFPROM_BLOW_TIMER_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000203c)
#define HWIO_QFPROM_BLOW_TIMER_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000203c)
#define HWIO_QFPROM_BLOW_TIMER_RMSK                                                                  0xfff
#define HWIO_QFPROM_BLOW_TIMER_IN          \
        in_dword(HWIO_QFPROM_BLOW_TIMER_ADDR)
#define HWIO_QFPROM_BLOW_TIMER_INM(m)      \
        in_dword_masked(HWIO_QFPROM_BLOW_TIMER_ADDR, m)
#define HWIO_QFPROM_BLOW_TIMER_OUT(v)      \
        out_dword(HWIO_QFPROM_BLOW_TIMER_ADDR,v)
#define HWIO_QFPROM_BLOW_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_BLOW_TIMER_ADDR,m,v,HWIO_QFPROM_BLOW_TIMER_IN)
#define HWIO_QFPROM_BLOW_TIMER_BLOW_TIMER_BMSK                                                       0xfff
#define HWIO_QFPROM_BLOW_TIMER_BLOW_TIMER_SHFT                                                         0x0

#define HWIO_QFPROM_TEST_CTRL_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002040)
#define HWIO_QFPROM_TEST_CTRL_OFFS                                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002040)
#define HWIO_QFPROM_TEST_CTRL_RMSK                                                                     0xf
#define HWIO_QFPROM_TEST_CTRL_IN          \
        in_dword(HWIO_QFPROM_TEST_CTRL_ADDR)
#define HWIO_QFPROM_TEST_CTRL_INM(m)      \
        in_dword_masked(HWIO_QFPROM_TEST_CTRL_ADDR, m)
#define HWIO_QFPROM_TEST_CTRL_OUT(v)      \
        out_dword(HWIO_QFPROM_TEST_CTRL_ADDR,v)
#define HWIO_QFPROM_TEST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_TEST_CTRL_ADDR,m,v,HWIO_QFPROM_TEST_CTRL_IN)
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_ROM_BMSK                                                         0x8
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_ROM_SHFT                                                         0x3
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_WL_BMSK                                                          0x4
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_WL_SHFT                                                          0x2
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_BL_BMSK                                                          0x2
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_BL_SHFT                                                          0x1
#define HWIO_QFPROM_TEST_CTRL_EN_FUSE_RES_MEAS_BMSK                                                    0x1
#define HWIO_QFPROM_TEST_CTRL_EN_FUSE_RES_MEAS_SHFT                                                    0x0

#define HWIO_QFPROM_ACCEL_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002044)
#define HWIO_QFPROM_ACCEL_OFFS                                                                  (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002044)
#define HWIO_QFPROM_ACCEL_RMSK                                                                       0xfff
#define HWIO_QFPROM_ACCEL_IN          \
        in_dword(HWIO_QFPROM_ACCEL_ADDR)
#define HWIO_QFPROM_ACCEL_INM(m)      \
        in_dword_masked(HWIO_QFPROM_ACCEL_ADDR, m)
#define HWIO_QFPROM_ACCEL_OUT(v)      \
        out_dword(HWIO_QFPROM_ACCEL_ADDR,v)
#define HWIO_QFPROM_ACCEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_ACCEL_ADDR,m,v,HWIO_QFPROM_ACCEL_IN)
#define HWIO_QFPROM_ACCEL_QFPROM_GATELAST_BMSK                                                       0x800
#define HWIO_QFPROM_ACCEL_QFPROM_GATELAST_SHFT                                                         0xb
#define HWIO_QFPROM_ACCEL_QFPROM_TRIPPT_SEL_BMSK                                                     0x700
#define HWIO_QFPROM_ACCEL_QFPROM_TRIPPT_SEL_SHFT                                                       0x8
#define HWIO_QFPROM_ACCEL_QFPROM_ACCEL_BMSK                                                           0xff
#define HWIO_QFPROM_ACCEL_QFPROM_ACCEL_SHFT                                                            0x0

#define HWIO_QFPROM_BLOW_STATUS_ADDR                                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002048)
#define HWIO_QFPROM_BLOW_STATUS_OFFS                                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002048)
#define HWIO_QFPROM_BLOW_STATUS_RMSK                                                                   0x3
#define HWIO_QFPROM_BLOW_STATUS_IN          \
        in_dword(HWIO_QFPROM_BLOW_STATUS_ADDR)
#define HWIO_QFPROM_BLOW_STATUS_INM(m)      \
        in_dword_masked(HWIO_QFPROM_BLOW_STATUS_ADDR, m)
#define HWIO_QFPROM_BLOW_STATUS_QFPROM_WR_ERR_BMSK                                                     0x2
#define HWIO_QFPROM_BLOW_STATUS_QFPROM_WR_ERR_SHFT                                                     0x1
#define HWIO_QFPROM_BLOW_STATUS_QFPROM_WR_ERR_NO_ERROR_FVAL                                            0x0
#define HWIO_QFPROM_BLOW_STATUS_QFPROM_WR_ERR_ERROR_FVAL                                               0x1
#define HWIO_QFPROM_BLOW_STATUS_QFPROM_BUSY_BMSK                                                       0x1
#define HWIO_QFPROM_BLOW_STATUS_QFPROM_BUSY_SHFT                                                       0x0

#define HWIO_QFPROM_ROM_ERROR_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000204c)
#define HWIO_QFPROM_ROM_ERROR_OFFS                                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000204c)
#define HWIO_QFPROM_ROM_ERROR_RMSK                                                                     0x1
#define HWIO_QFPROM_ROM_ERROR_IN          \
        in_dword(HWIO_QFPROM_ROM_ERROR_ADDR)
#define HWIO_QFPROM_ROM_ERROR_INM(m)      \
        in_dword_masked(HWIO_QFPROM_ROM_ERROR_ADDR, m)
#define HWIO_QFPROM_ROM_ERROR_ERROR_BMSK                                                               0x1
#define HWIO_QFPROM_ROM_ERROR_ERROR_SHFT                                                               0x0
#define HWIO_QFPROM_ROM_ERROR_ERROR_NO_ERROR_FVAL                                                      0x0
#define HWIO_QFPROM_ROM_ERROR_ERROR_ERROR_FVAL                                                         0x1

#define HWIO_QFPROM0_MATCH_STATUS_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002050)
#define HWIO_QFPROM0_MATCH_STATUS_OFFS                                                          (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002050)
#define HWIO_QFPROM0_MATCH_STATUS_RMSK                                                          0xffffffff
#define HWIO_QFPROM0_MATCH_STATUS_IN          \
        in_dword(HWIO_QFPROM0_MATCH_STATUS_ADDR)
#define HWIO_QFPROM0_MATCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_QFPROM0_MATCH_STATUS_ADDR, m)
#define HWIO_QFPROM0_MATCH_STATUS_FLAG_BMSK                                                     0xffffffff
#define HWIO_QFPROM0_MATCH_STATUS_FLAG_SHFT                                                            0x0

#define HWIO_QFPROM1_MATCH_STATUS_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002054)
#define HWIO_QFPROM1_MATCH_STATUS_OFFS                                                          (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002054)
#define HWIO_QFPROM1_MATCH_STATUS_RMSK                                                          0xffffffff
#define HWIO_QFPROM1_MATCH_STATUS_IN          \
        in_dword(HWIO_QFPROM1_MATCH_STATUS_ADDR)
#define HWIO_QFPROM1_MATCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_QFPROM1_MATCH_STATUS_ADDR, m)
#define HWIO_QFPROM1_MATCH_STATUS_FLAG_BMSK                                                     0xffffffff
#define HWIO_QFPROM1_MATCH_STATUS_FLAG_SHFT                                                            0x0

#define HWIO_FEC_ESR_ADDR                                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002058)
#define HWIO_FEC_ESR_OFFS                                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002058)
#define HWIO_FEC_ESR_RMSK                                                                           0x2fdf
#define HWIO_FEC_ESR_IN          \
        in_dword(HWIO_FEC_ESR_ADDR)
#define HWIO_FEC_ESR_INM(m)      \
        in_dword_masked(HWIO_FEC_ESR_ADDR, m)
#define HWIO_FEC_ESR_OUT(v)      \
        out_dword(HWIO_FEC_ESR_ADDR,v)
#define HWIO_FEC_ESR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_FEC_ESR_ADDR,m,v,HWIO_FEC_ESR_IN)
#define HWIO_FEC_ESR_CORR_SW_ACC_BMSK                                                               0x2000
#define HWIO_FEC_ESR_CORR_SW_ACC_SHFT                                                                  0xd
#define HWIO_FEC_ESR_CORR_SECURE_CHANNEL_BMSK                                                        0x800
#define HWIO_FEC_ESR_CORR_SECURE_CHANNEL_SHFT                                                          0xb
#define HWIO_FEC_ESR_CORR_BOOT_ROM_BMSK                                                              0x400
#define HWIO_FEC_ESR_CORR_BOOT_ROM_SHFT                                                                0xa
#define HWIO_FEC_ESR_CORR_FUSE_SENSE_BMSK                                                            0x200
#define HWIO_FEC_ESR_CORR_FUSE_SENSE_SHFT                                                              0x9
#define HWIO_FEC_ESR_CORR_MULT_BMSK                                                                  0x100
#define HWIO_FEC_ESR_CORR_MULT_SHFT                                                                    0x8
#define HWIO_FEC_ESR_CORR_SEEN_BMSK                                                                   0x80
#define HWIO_FEC_ESR_CORR_SEEN_SHFT                                                                    0x7
#define HWIO_FEC_ESR_CORR_SEEN_NO_CORRECTION_FVAL                                                      0x0
#define HWIO_FEC_ESR_CORR_SEEN_CORRECTION_FVAL                                                         0x1
#define HWIO_FEC_ESR_ERR_SW_ACC_BMSK                                                                  0x40
#define HWIO_FEC_ESR_ERR_SW_ACC_SHFT                                                                   0x6
#define HWIO_FEC_ESR_ERR_SECURE_CHANNEL_BMSK                                                          0x10
#define HWIO_FEC_ESR_ERR_SECURE_CHANNEL_SHFT                                                           0x4
#define HWIO_FEC_ESR_ERR_BOOT_ROM_BMSK                                                                 0x8
#define HWIO_FEC_ESR_ERR_BOOT_ROM_SHFT                                                                 0x3
#define HWIO_FEC_ESR_ERR_FUSE_SENSE_BMSK                                                               0x4
#define HWIO_FEC_ESR_ERR_FUSE_SENSE_SHFT                                                               0x2
#define HWIO_FEC_ESR_ERR_MULT_BMSK                                                                     0x2
#define HWIO_FEC_ESR_ERR_MULT_SHFT                                                                     0x1
#define HWIO_FEC_ESR_ERR_SEEN_BMSK                                                                     0x1
#define HWIO_FEC_ESR_ERR_SEEN_SHFT                                                                     0x0
#define HWIO_FEC_ESR_ERR_SEEN_NO_ERROR_FVAL                                                            0x0
#define HWIO_FEC_ESR_ERR_SEEN_ERROR_FVAL                                                               0x1

#define HWIO_FEC_EAR_ADDR                                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000205c)
#define HWIO_FEC_EAR_OFFS                                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000205c)
#define HWIO_FEC_EAR_RMSK                                                                       0xffffffff
#define HWIO_FEC_EAR_IN          \
        in_dword(HWIO_FEC_EAR_ADDR)
#define HWIO_FEC_EAR_INM(m)      \
        in_dword_masked(HWIO_FEC_EAR_ADDR, m)
#define HWIO_FEC_EAR_CORR_ADDR_BMSK                                                             0xffff0000
#define HWIO_FEC_EAR_CORR_ADDR_SHFT                                                                   0x10
#define HWIO_FEC_EAR_ERR_ADDR_BMSK                                                                  0xffff
#define HWIO_FEC_EAR_ERR_ADDR_SHFT                                                                     0x0

#define HWIO_QFPROM_BIST_CTRL_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002060)
#define HWIO_QFPROM_BIST_CTRL_OFFS                                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002060)
#define HWIO_QFPROM_BIST_CTRL_RMSK                                                                    0xff
#define HWIO_QFPROM_BIST_CTRL_IN          \
        in_dword(HWIO_QFPROM_BIST_CTRL_ADDR)
#define HWIO_QFPROM_BIST_CTRL_INM(m)      \
        in_dword_masked(HWIO_QFPROM_BIST_CTRL_ADDR, m)
#define HWIO_QFPROM_BIST_CTRL_OUT(v)      \
        out_dword(HWIO_QFPROM_BIST_CTRL_ADDR,v)
#define HWIO_QFPROM_BIST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_BIST_CTRL_ADDR,m,v,HWIO_QFPROM_BIST_CTRL_IN)
#define HWIO_QFPROM_BIST_CTRL_AUTH_REGION_BMSK                                                        0xfc
#define HWIO_QFPROM_BIST_CTRL_AUTH_REGION_SHFT                                                         0x2
#define HWIO_QFPROM_BIST_CTRL_SHA_ENABLE_BMSK                                                          0x2
#define HWIO_QFPROM_BIST_CTRL_SHA_ENABLE_SHFT                                                          0x1
#define HWIO_QFPROM_BIST_CTRL_START_BMSK                                                               0x1
#define HWIO_QFPROM_BIST_CTRL_START_SHFT                                                               0x0

#define HWIO_QFPROM_BIST_ERROR0_ADDR                                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002064)
#define HWIO_QFPROM_BIST_ERROR0_OFFS                                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002064)
#define HWIO_QFPROM_BIST_ERROR0_RMSK                                                            0xffffffff
#define HWIO_QFPROM_BIST_ERROR0_IN          \
        in_dword(HWIO_QFPROM_BIST_ERROR0_ADDR)
#define HWIO_QFPROM_BIST_ERROR0_INM(m)      \
        in_dword_masked(HWIO_QFPROM_BIST_ERROR0_ADDR, m)
#define HWIO_QFPROM_BIST_ERROR0_ERROR_BMSK                                                      0xffffffff
#define HWIO_QFPROM_BIST_ERROR0_ERROR_SHFT                                                             0x0
#define HWIO_QFPROM_BIST_ERROR0_ERROR_NO_ERROR_FVAL                                                    0x0
#define HWIO_QFPROM_BIST_ERROR0_ERROR_ERROR_FVAL                                                       0x1

#define HWIO_QFPROM_BIST_ERROR1_ADDR                                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002068)
#define HWIO_QFPROM_BIST_ERROR1_OFFS                                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002068)
#define HWIO_QFPROM_BIST_ERROR1_RMSK                                                            0xffffffff
#define HWIO_QFPROM_BIST_ERROR1_IN          \
        in_dword(HWIO_QFPROM_BIST_ERROR1_ADDR)
#define HWIO_QFPROM_BIST_ERROR1_INM(m)      \
        in_dword_masked(HWIO_QFPROM_BIST_ERROR1_ADDR, m)
#define HWIO_QFPROM_BIST_ERROR1_ERROR_BMSK                                                      0xffffffff
#define HWIO_QFPROM_BIST_ERROR1_ERROR_SHFT                                                             0x0
#define HWIO_QFPROM_BIST_ERROR1_ERROR_NO_ERROR_FVAL                                                    0x0
#define HWIO_QFPROM_BIST_ERROR1_ERROR_ERROR_FVAL                                                       0x1

#define HWIO_QFPROM_HASH_SIGNATUREn_ADDR(n)                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000206c + 0x4 * (n))
#define HWIO_QFPROM_HASH_SIGNATUREn_OFFS(n)                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000206c + 0x4 * (n))
#define HWIO_QFPROM_HASH_SIGNATUREn_RMSK                                                        0xffffffff
#define HWIO_QFPROM_HASH_SIGNATUREn_MAXn                                                                 7
#define HWIO_QFPROM_HASH_SIGNATUREn_INI(n)        \
        in_dword_masked(HWIO_QFPROM_HASH_SIGNATUREn_ADDR(n), HWIO_QFPROM_HASH_SIGNATUREn_RMSK)
#define HWIO_QFPROM_HASH_SIGNATUREn_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_HASH_SIGNATUREn_ADDR(n), mask)
#define HWIO_QFPROM_HASH_SIGNATUREn_HASH_VALUE_BMSK                                             0xffffffff
#define HWIO_QFPROM_HASH_SIGNATUREn_HASH_VALUE_SHFT                                                    0x0

#define HWIO_HW_KEY_STATUS_ADDR                                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000208c)
#define HWIO_HW_KEY_STATUS_OFFS                                                                 (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000208c)
#define HWIO_HW_KEY_STATUS_RMSK                                                                      0x7ff
#define HWIO_HW_KEY_STATUS_IN          \
        in_dword(HWIO_HW_KEY_STATUS_ADDR)
#define HWIO_HW_KEY_STATUS_INM(m)      \
        in_dword_masked(HWIO_HW_KEY_STATUS_ADDR, m)
#define HWIO_HW_KEY_STATUS_MSA_SECURE_BMSK                                                           0x400
#define HWIO_HW_KEY_STATUS_MSA_SECURE_SHFT                                                             0xa
#define HWIO_HW_KEY_STATUS_MSA_SECURE_MSA_NOT_SECURE_FVAL                                              0x0
#define HWIO_HW_KEY_STATUS_MSA_SECURE_MSA_SECURE_FVAL                                                  0x1
#define HWIO_HW_KEY_STATUS_APPS_SECURE_BMSK                                                          0x200
#define HWIO_HW_KEY_STATUS_APPS_SECURE_SHFT                                                            0x9
#define HWIO_HW_KEY_STATUS_APPS_SECURE_APPS_NOT_SECURE_FVAL                                            0x0
#define HWIO_HW_KEY_STATUS_APPS_SECURE_APPS_SECURE_FVAL                                                0x1
#define HWIO_HW_KEY_STATUS_KDF_AND_HW_KEY_SHIFT_DONE_BMSK                                            0x100
#define HWIO_HW_KEY_STATUS_KDF_AND_HW_KEY_SHIFT_DONE_SHFT                                              0x8
#define HWIO_HW_KEY_STATUS_KDF_AND_HW_KEY_SHIFT_DONE_KDF_AND_HW_KEY_SHIFT_IN_PROGRESS_FVAL             0x0
#define HWIO_HW_KEY_STATUS_KDF_AND_HW_KEY_SHIFT_DONE_KDF_AND_HW_KEY_SHIFT_HAS_COMPLETED_FVAL           0x1
#define HWIO_HW_KEY_STATUS_HW_KEY_SHIFT_DONE_BMSK                                                     0x80
#define HWIO_HW_KEY_STATUS_HW_KEY_SHIFT_DONE_SHFT                                                      0x7
#define HWIO_HW_KEY_STATUS_HW_KEY_SHIFT_DONE_HW_KEY_SHIFT_IN_PROGRESS_FVAL                             0x0
#define HWIO_HW_KEY_STATUS_HW_KEY_SHIFT_DONE_HW_KEY_SHIFT_HAS_COMPLETED_FVAL                           0x1
#define HWIO_HW_KEY_STATUS_FUSE_SENSE_DONE_BMSK                                                       0x40
#define HWIO_HW_KEY_STATUS_FUSE_SENSE_DONE_SHFT                                                        0x6
#define HWIO_HW_KEY_STATUS_FUSE_SENSE_DONE_FUSE_SENSE_IN_PROGRESS_FVAL                                 0x0
#define HWIO_HW_KEY_STATUS_FUSE_SENSE_DONE_FUSE_SENSE_HAS_COMPLETED_FVAL                               0x1
#define HWIO_HW_KEY_STATUS_CRI_CM_BOOT_DONE_BMSK                                                      0x20
#define HWIO_HW_KEY_STATUS_CRI_CM_BOOT_DONE_SHFT                                                       0x5
#define HWIO_HW_KEY_STATUS_CRI_CM_BOOT_DONE_CRI_CM_BOOT_IN_PROGRESS_FVAL                               0x0
#define HWIO_HW_KEY_STATUS_CRI_CM_BOOT_DONE_CRI_CM_BOOT_HAS_COMPLETED_FVAL                             0x1
#define HWIO_HW_KEY_STATUS_KDF_DONE_BMSK                                                              0x10
#define HWIO_HW_KEY_STATUS_KDF_DONE_SHFT                                                               0x4
#define HWIO_HW_KEY_STATUS_KDF_DONE_KDF_OPERATION_IN_PROGRESS_FVAL                                     0x0
#define HWIO_HW_KEY_STATUS_KDF_DONE_KDF_OPERATION_HAS_COMPLETED_FVAL                                   0x1
#define HWIO_HW_KEY_STATUS_MSA_KEYS_BLOCKED_BMSK                                                       0x8
#define HWIO_HW_KEY_STATUS_MSA_KEYS_BLOCKED_SHFT                                                       0x3
#define HWIO_HW_KEY_STATUS_MSA_KEYS_BLOCKED_NOT_BLOCKED_FVAL                                           0x0
#define HWIO_HW_KEY_STATUS_MSA_KEYS_BLOCKED_BLOCKED_FVAL                                               0x1
#define HWIO_HW_KEY_STATUS_APPS_KEYS_BLOCKED_BMSK                                                      0x4
#define HWIO_HW_KEY_STATUS_APPS_KEYS_BLOCKED_SHFT                                                      0x2
#define HWIO_HW_KEY_STATUS_APPS_KEYS_BLOCKED_NOT_BLOCKED_FVAL                                          0x0
#define HWIO_HW_KEY_STATUS_APPS_KEYS_BLOCKED_BLOCKED_FVAL                                              0x1
#define HWIO_HW_KEY_STATUS_SEC_KEY_DERIVATION_KEY_BLOWN_BMSK                                           0x2
#define HWIO_HW_KEY_STATUS_SEC_KEY_DERIVATION_KEY_BLOWN_SHFT                                           0x1
#define HWIO_HW_KEY_STATUS_SEC_KEY_DERIVATION_KEY_BLOWN_NOT_BLOWN_FVAL                                 0x0
#define HWIO_HW_KEY_STATUS_SEC_KEY_DERIVATION_KEY_BLOWN_BLOWN_FVAL                                     0x1
#define HWIO_HW_KEY_STATUS_PRI_KEY_DERIVATION_KEY_BLOWN_BMSK                                           0x1
#define HWIO_HW_KEY_STATUS_PRI_KEY_DERIVATION_KEY_BLOWN_SHFT                                           0x0
#define HWIO_HW_KEY_STATUS_PRI_KEY_DERIVATION_KEY_BLOWN_NOT_BLOWN_FVAL                                 0x0
#define HWIO_HW_KEY_STATUS_PRI_KEY_DERIVATION_KEY_BLOWN_BLOWN_FVAL                                     0x1

#define HWIO_RESET_JDR_STATUS_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002090)
#define HWIO_RESET_JDR_STATUS_OFFS                                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002090)
#define HWIO_RESET_JDR_STATUS_RMSK                                                                     0x3
#define HWIO_RESET_JDR_STATUS_IN          \
        in_dword(HWIO_RESET_JDR_STATUS_ADDR)
#define HWIO_RESET_JDR_STATUS_INM(m)      \
        in_dword_masked(HWIO_RESET_JDR_STATUS_ADDR, m)
#define HWIO_RESET_JDR_STATUS_FORCE_RESET_BMSK                                                         0x2
#define HWIO_RESET_JDR_STATUS_FORCE_RESET_SHFT                                                         0x1
#define HWIO_RESET_JDR_STATUS_DISABLE_SYSTEM_RESET_BMSK                                                0x1
#define HWIO_RESET_JDR_STATUS_DISABLE_SYSTEM_RESET_SHFT                                                0x0

#define HWIO_ATPG_JDR_STATUS_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002094)
#define HWIO_ATPG_JDR_STATUS_OFFS                                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002094)
#define HWIO_ATPG_JDR_STATUS_RMSK                                                                      0x1
#define HWIO_ATPG_JDR_STATUS_IN          \
        in_dword(HWIO_ATPG_JDR_STATUS_ADDR)
#define HWIO_ATPG_JDR_STATUS_INM(m)      \
        in_dword_masked(HWIO_ATPG_JDR_STATUS_ADDR, m)
#define HWIO_ATPG_JDR_STATUS_FUSE_SENSE_ATPG_CTL_BMSK                                                  0x1
#define HWIO_ATPG_JDR_STATUS_FUSE_SENSE_ATPG_CTL_SHFT                                                  0x0

#define HWIO_FEAT_PROV_OUTn_ADDR(n)                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002098 + 0x4 * (n))
#define HWIO_FEAT_PROV_OUTn_OFFS(n)                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002098 + 0x4 * (n))
#define HWIO_FEAT_PROV_OUTn_RMSK                                                                0xffffffff
#define HWIO_FEAT_PROV_OUTn_MAXn                                                                         3
#define HWIO_FEAT_PROV_OUTn_INI(n)        \
        in_dword_masked(HWIO_FEAT_PROV_OUTn_ADDR(n), HWIO_FEAT_PROV_OUTn_RMSK)
#define HWIO_FEAT_PROV_OUTn_INMI(n,mask)    \
        in_dword_masked(HWIO_FEAT_PROV_OUTn_ADDR(n), mask)
#define HWIO_FEAT_PROV_OUTn_FEAT_PROV_OUT_VALUE_BMSK                                            0xffffffff
#define HWIO_FEAT_PROV_OUTn_FEAT_PROV_OUT_VALUE_SHFT                                                   0x0

#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_ADDR(n)                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000020a8 + 0x4 * (n))
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_OFFS(n)                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000020a8 + 0x4 * (n))
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_RMSK                                                  0xffffffff
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_MAXn                                                           3
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_INI(n)        \
        in_dword_masked(HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_ADDR(n), HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_RMSK)
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_INMI(n,mask)    \
        in_dword_masked(HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_ADDR(n), mask)
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_SEC_CTRL_MISC_CONFIG_STATUS_VALUE_BMSK                0xffffffff
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_SEC_CTRL_MISC_CONFIG_STATUS_VALUE_SHFT                       0x0

#define HWIO_DEBUG_FUSE_STATUS_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000020f0)
#define HWIO_DEBUG_FUSE_STATUS_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000020f0)
#define HWIO_DEBUG_FUSE_STATUS_RMSK                                                             0xffffffff
#define HWIO_DEBUG_FUSE_STATUS_IN          \
        in_dword(HWIO_DEBUG_FUSE_STATUS_ADDR)
#define HWIO_DEBUG_FUSE_STATUS_INM(m)      \
        in_dword_masked(HWIO_DEBUG_FUSE_STATUS_ADDR, m)
#define HWIO_DEBUG_FUSE_STATUS_RSVD0_BMSK                                                       0xff000000
#define HWIO_DEBUG_FUSE_STATUS_RSVD0_SHFT                                                             0x18
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC5_DEBUG_BMSK                                            0x800000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC5_DEBUG_SHFT                                                0x17
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC4_DEBUG_BMSK                                            0x400000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC4_DEBUG_SHFT                                                0x16
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC3_DEBUG_BMSK                                            0x200000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC3_DEBUG_SHFT                                                0x15
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC2_DEBUG_BMSK                                            0x100000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC2_DEBUG_SHFT                                                0x14
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC1_DEBUG_BMSK                                             0x80000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC1_DEBUG_SHFT                                                0x13
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC_DEBUG_BMSK                                              0x40000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC_DEBUG_SHFT                                                 0x12
#define HWIO_DEBUG_FUSE_STATUS_APPS_NIDEN_BMSK                                                     0x20000
#define HWIO_DEBUG_FUSE_STATUS_APPS_NIDEN_SHFT                                                        0x11
#define HWIO_DEBUG_FUSE_STATUS_APPS_DBGEN_BMSK                                                     0x10000
#define HWIO_DEBUG_FUSE_STATUS_APPS_DBGEN_SHFT                                                        0x10
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_QSEE_SPNIDEN_BMSK                                            0x8000
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_QSEE_SPNIDEN_SHFT                                               0xf
#define HWIO_DEBUG_FUSE_STATUS_SHARED_QSEE_SPNIDEN_BMSK                                             0x4000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_QSEE_SPNIDEN_SHFT                                                0xe
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_MSS_NIDEN_BMSK                                               0x2000
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_MSS_NIDEN_SHFT                                                  0xd
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MSS_NIDEN_BMSK                                                0x1000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MSS_NIDEN_SHFT                                                   0xc
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_CP_NIDEN_BMSK                                                 0x800
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_CP_NIDEN_SHFT                                                   0xb
#define HWIO_DEBUG_FUSE_STATUS_SHARED_CP_NIDEN_BMSK                                                  0x400
#define HWIO_DEBUG_FUSE_STATUS_SHARED_CP_NIDEN_SHFT                                                    0xa
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_NS_NIDEN_BMSK                                                 0x200
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_NS_NIDEN_SHFT                                                   0x9
#define HWIO_DEBUG_FUSE_STATUS_SHARED_NS_NIDEN_BMSK                                                  0x100
#define HWIO_DEBUG_FUSE_STATUS_SHARED_NS_NIDEN_SHFT                                                    0x8
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_QSEE_SPIDEN_BMSK                                               0x80
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_QSEE_SPIDEN_SHFT                                                0x7
#define HWIO_DEBUG_FUSE_STATUS_SHARED_QSEE_SPIDEN_BMSK                                                0x40
#define HWIO_DEBUG_FUSE_STATUS_SHARED_QSEE_SPIDEN_SHFT                                                 0x6
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_MSS_DBGEN_BMSK                                                 0x20
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_MSS_DBGEN_SHFT                                                  0x5
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MSS_DBGEN_BMSK                                                  0x10
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MSS_DBGEN_SHFT                                                   0x4
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_CP_DBGEN_BMSK                                                   0x8
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_CP_DBGEN_SHFT                                                   0x3
#define HWIO_DEBUG_FUSE_STATUS_SHARED_CP_DBGEN_BMSK                                                    0x4
#define HWIO_DEBUG_FUSE_STATUS_SHARED_CP_DBGEN_SHFT                                                    0x2
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_NS_DBGEN_BMSK                                                   0x2
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_NS_DBGEN_SHFT                                                   0x1
#define HWIO_DEBUG_FUSE_STATUS_SHARED_NS_DBGEN_BMSK                                                    0x1
#define HWIO_DEBUG_FUSE_STATUS_SHARED_NS_DBGEN_SHFT                                                    0x0

#define HWIO_HW_ATTESTATION_CTRL0_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002100)
#define HWIO_HW_ATTESTATION_CTRL0_OFFS                                                          (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002100)
#define HWIO_HW_ATTESTATION_CTRL0_RMSK                                                          0x1fffffff
#define HWIO_HW_ATTESTATION_CTRL0_IN          \
        in_dword(HWIO_HW_ATTESTATION_CTRL0_ADDR)
#define HWIO_HW_ATTESTATION_CTRL0_INM(m)      \
        in_dword_masked(HWIO_HW_ATTESTATION_CTRL0_ADDR, m)
#define HWIO_HW_ATTESTATION_CTRL0_OUT(v)      \
        out_dword(HWIO_HW_ATTESTATION_CTRL0_ADDR,v)
#define HWIO_HW_ATTESTATION_CTRL0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_HW_ATTESTATION_CTRL0_ADDR,m,v,HWIO_HW_ATTESTATION_CTRL0_IN)
#define HWIO_HW_ATTESTATION_CTRL0_REGION_BMSK                                                   0x1f800000
#define HWIO_HW_ATTESTATION_CTRL0_REGION_SHFT                                                         0x17
#define HWIO_HW_ATTESTATION_CTRL0_CONTEXT_STRING_BMSK                                             0x7fff80
#define HWIO_HW_ATTESTATION_CTRL0_CONTEXT_STRING_SHFT                                                  0x7
#define HWIO_HW_ATTESTATION_CTRL0_KEY_SELECT_BMSK                                                     0x78
#define HWIO_HW_ATTESTATION_CTRL0_KEY_SELECT_SHFT                                                      0x3
#define HWIO_HW_ATTESTATION_CTRL0_KEY_SELECT_PKDK_FVAL                                                 0x0
#define HWIO_HW_ATTESTATION_CTRL0_KEY_SELECT_SKDK_FVAL                                                 0x1
#define HWIO_HW_ATTESTATION_CTRL0_KEY_SELECT_RTL_TEST_KEY_FVAL                                         0x2
#define HWIO_HW_ATTESTATION_CTRL0_KEY_SELECT_RTL_COMMERCIAL_KEY_FVAL                                   0x3
#define HWIO_HW_ATTESTATION_CTRL0_OPERATION_BMSK                                                       0x7
#define HWIO_HW_ATTESTATION_CTRL0_OPERATION_SHFT                                                       0x0
#define HWIO_HW_ATTESTATION_CTRL0_OPERATION_DEFAULT_FVAL                                               0x0
#define HWIO_HW_ATTESTATION_CTRL0_OPERATION_KEY_GEN_FVAL                                               0x1
#define HWIO_HW_ATTESTATION_CTRL0_OPERATION_START_FVAL                                                 0x2
#define HWIO_HW_ATTESTATION_CTRL0_OPERATION_UPDATE_FVAL                                                0x3
#define HWIO_HW_ATTESTATION_CTRL0_OPERATION_FINAL_FVAL                                                 0x4

#define HWIO_HW_ATTESTATION_CTRL1_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002104)
#define HWIO_HW_ATTESTATION_CTRL1_OFFS                                                          (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002104)
#define HWIO_HW_ATTESTATION_CTRL1_RMSK                                                          0xffffffff
#define HWIO_HW_ATTESTATION_CTRL1_IN          \
        in_dword(HWIO_HW_ATTESTATION_CTRL1_ADDR)
#define HWIO_HW_ATTESTATION_CTRL1_INM(m)      \
        in_dword_masked(HWIO_HW_ATTESTATION_CTRL1_ADDR, m)
#define HWIO_HW_ATTESTATION_CTRL1_OUT(v)      \
        out_dword(HWIO_HW_ATTESTATION_CTRL1_ADDR,v)
#define HWIO_HW_ATTESTATION_CTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_HW_ATTESTATION_CTRL1_ADDR,m,v,HWIO_HW_ATTESTATION_CTRL1_IN)
#define HWIO_HW_ATTESTATION_CTRL1_NONCE_BMSK                                                    0xffffffff
#define HWIO_HW_ATTESTATION_CTRL1_NONCE_SHFT                                                           0x0

#define HWIO_HW_ATTESTATION_CMD_ADDR                                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002108)
#define HWIO_HW_ATTESTATION_CMD_OFFS                                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002108)
#define HWIO_HW_ATTESTATION_CMD_RMSK                                                                   0x1
#define HWIO_HW_ATTESTATION_CMD_OUT(v)      \
        out_dword(HWIO_HW_ATTESTATION_CMD_ADDR,v)
#define HWIO_HW_ATTESTATION_CMD_OPERATION_COMMAND_BMSK                                                 0x1
#define HWIO_HW_ATTESTATION_CMD_OPERATION_COMMAND_SHFT                                                 0x0

#define HWIO_HW_ATTESTATION_STATUS_ADDR                                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000210c)
#define HWIO_HW_ATTESTATION_STATUS_OFFS                                                         (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000210c)
#define HWIO_HW_ATTESTATION_STATUS_RMSK                                                         0xffffffff
#define HWIO_HW_ATTESTATION_STATUS_IN          \
        in_dword(HWIO_HW_ATTESTATION_STATUS_ADDR)
#define HWIO_HW_ATTESTATION_STATUS_INM(m)      \
        in_dword_masked(HWIO_HW_ATTESTATION_STATUS_ADDR, m)
#define HWIO_HW_ATTESTATION_STATUS_STATUS_BMSK                                                  0xffffffff
#define HWIO_HW_ATTESTATION_STATUS_STATUS_SHFT                                                         0x0
#define HWIO_HW_ATTESTATION_STATUS_STATUS_HW_ATTEST_DERIVED_KEY_READY_FVAL                             0x0
#define HWIO_HW_ATTESTATION_STATUS_STATUS_HW_ATTEST_MAC_VALUE_READY_FVAL                               0x1

#define HWIO_HW_ATTESTATION_ERROR_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002110)
#define HWIO_HW_ATTESTATION_ERROR_OFFS                                                          (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002110)
#define HWIO_HW_ATTESTATION_ERROR_RMSK                                                          0xffffffff
#define HWIO_HW_ATTESTATION_ERROR_IN          \
        in_dword(HWIO_HW_ATTESTATION_ERROR_ADDR)
#define HWIO_HW_ATTESTATION_ERROR_INM(m)      \
        in_dword_masked(HWIO_HW_ATTESTATION_ERROR_ADDR, m)
#define HWIO_HW_ATTESTATION_ERROR_ERROR_BMSK                                                    0xffffffff
#define HWIO_HW_ATTESTATION_ERROR_ERROR_SHFT                                                           0x0
#define HWIO_HW_ATTESTATION_ERROR_ERROR_REGION_OUTSIDE_VALID_RANGE_FVAL                                0x0

#define HWIO_HW_ATTESTATION_RESULTn_ADDR(n)                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002120 + 0x4 * (n))
#define HWIO_HW_ATTESTATION_RESULTn_OFFS(n)                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002120 + 0x4 * (n))
#define HWIO_HW_ATTESTATION_RESULTn_RMSK                                                        0xffffffff
#define HWIO_HW_ATTESTATION_RESULTn_MAXn                                                                 7
#define HWIO_HW_ATTESTATION_RESULTn_INI(n)        \
        in_dword_masked(HWIO_HW_ATTESTATION_RESULTn_ADDR(n), HWIO_HW_ATTESTATION_RESULTn_RMSK)
#define HWIO_HW_ATTESTATION_RESULTn_INMI(n,mask)    \
        in_dword_masked(HWIO_HW_ATTESTATION_RESULTn_ADDR(n), mask)
#define HWIO_HW_ATTESTATION_RESULTn_RESULT_BMSK                                                 0xffffffff
#define HWIO_HW_ATTESTATION_RESULTn_RESULT_SHFT                                                        0x0

#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_ADDR(n)                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004000 + 0x4 * (n))
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_OFFS(n)                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004000 + 0x4 * (n))
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_MAXn                                                           71
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_ADDR(n), HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_RMSK)
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_ADDR(n), mask)
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_CRI_CM_PRIVATE_BMSK                                    0xffffffff
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_CRI_CM_PRIVATE_SHFT                                           0x0

#define HWIO_QFPROM_CORR_LCM_ROW_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004120)
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004120)
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_LCM_ROW_LSB_ADDR)
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_LCM_ROW_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_DISABLE_LCM_BMSK                                           0x80000000
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_DISABLE_LCM_SHFT                                                 0x1f
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_DISABLE_LCM_STATE_TRANSITION_BMSK                          0x40000000
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_DISABLE_LCM_STATE_TRANSITION_SHFT                                0x1e
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_DISABLE_SECURE_PHK_BMSK                                    0x20000000
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_DISABLE_SECURE_PHK_SHFT                                          0x1d
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_RSVD_BMSK                                                  0x1fffffe0
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_RSVD_SHFT                                                         0x5
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_QC_EXTERNAL_BMSK                                                 0x10
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_QC_EXTERNAL_SHFT                                                  0x4
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_QC_INTERNAL_BMSK                                                  0x8
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_QC_INTERNAL_SHFT                                                  0x3
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_QC_FEAT_CONFIG_BMSK                                               0x4
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_QC_FEAT_CONFIG_SHFT                                               0x2
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_HW_TEST_BMSK                                                      0x2
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_HW_TEST_SHFT                                                      0x1
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_SOC_PERSO_BMSK                                                    0x1
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_SOC_PERSO_SHFT                                                    0x0

#define HWIO_QFPROM_CORR_LCM_ROW_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004124)
#define HWIO_QFPROM_CORR_LCM_ROW_MSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004124)
#define HWIO_QFPROM_CORR_LCM_ROW_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_CORR_LCM_ROW_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_LCM_ROW_MSB_ADDR)
#define HWIO_QFPROM_CORR_LCM_ROW_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_LCM_ROW_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_LCM_ROW_MSB_RSVD_BMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_LCM_ROW_MSB_RSVD_SHFT                                                         0x0

#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_ADDR(n)                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004128 + 0x8 * (n))
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_OFFS(n)                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004128 + 0x8 * (n))
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_MAXn                                                   1
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_RSVD_BMSK                                     0xffffffff
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_RSVD_SHFT                                            0x0

#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_ADDR(n)                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000412c + 0x8 * (n))
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_OFFS(n)                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000412c + 0x8 * (n))
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_MAXn                                                   1
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_RSVD_BMSK                                     0xffffffff
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_RSVD_SHFT                                            0x0

#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n)                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004138 + 0x8 * (n))
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_OFFS(n)                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004138 + 0x8 * (n))
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_RMSK                                   0xffffffff
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_MAXn                                            3
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_BMSK                         0xffffffff
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_SHFT                                0x0

#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n)                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000413c + 0x8 * (n))
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_OFFS(n)                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000413c + 0x8 * (n))
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RMSK                                     0xffffff
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_MAXn                                            3
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_BMSK                           0xffffff
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_SHFT                                0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004158)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_OFFS                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004158)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_RMSK                                           0x7fffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_BMSK                   0x40000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_SHFT                         0x1e
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_BMSK                             0x20000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_SHFT                                   0x1d
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_ENABLE_FVAL                             0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_DISABLE_FVAL                            0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_BMSK                      0x1fe00000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_SHFT                            0x15
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_BMSK                       0x180000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_SHFT                           0x13
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_DEFAULT_FVAL                    0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_ENUM_1024_FVAL                  0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_ENUM_2048_FVAL                  0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_ENUM_2560_FVAL                  0x3
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_BMSK                     0x40000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_SHFT                        0x12
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_ENABLE_FVAL                  0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_DISABLE_FVAL                 0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_BMSK                     0x20000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_SHFT                        0x11
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_ENABLE_FVAL                  0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_DISABLE_FVAL                 0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_BMSK                              0x10000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_SHFT                                 0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_ENABLE_FVAL                           0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_DISABLE_FVAL                          0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_BMSK                              0x8000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_SHFT                                 0xf
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_ENABLE_FVAL                          0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_DISABLE_FVAL                         0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_BMSK                              0x4000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_SHFT                                 0xe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_ENABLE_FVAL                          0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_DISABLE_FVAL                         0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_BMSK                                    0x2000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_SHFT                                       0xd
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_DISABLE_FVAL                               0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_BMSK                                  0x1000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_SHFT                                     0xc
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_ENABLE_FVAL                              0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_DISABLE_FVAL                             0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_BMSK                         0x800
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_SHFT                           0xb
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK                 0x400
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT                   0xa
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_ENABLE_FVAL            0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_DISABLE_FVAL           0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_BMSK                                  0x200
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_SHFT                                    0x9
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_ENABLE_FVAL                             0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_DISABLE_FVAL                            0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_BMSK                                  0x100
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_SHFT                                    0x8
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_ENABLE_FVAL                             0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_DISABLE_FVAL                            0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_BMSK                                      0x80
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_SHFT                                       0x7
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_DISABLE_FVAL                               0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_BMSK                            0x40
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_SHFT                             0x6
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_ENABLE_FVAL                      0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_DISABLE_FVAL                     0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EFUSE_CAM_SBI_ENABLE_IF_BMSK                         0x20
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EFUSE_CAM_SBI_ENABLE_IF_SHFT                          0x5
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_BMSK                                   0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_SHFT                                    0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_USB_PORT0_FVAL                          0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_USB_PORT1_FVAL                          0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_BMSK                                     0x8
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_SHFT                                     0x3
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_BMSK                           0x7
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_SHFT                           0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_ENABLE_PATCHING_FVAL           0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_DISABLE_PATCHING_FVAL          0x1

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000415c)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_OFFS                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000415c)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_RMSK                                           0xe7fffff7
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_BMSK                         0x80000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_SHFT                               0x1f
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_ICE_ENGINE_USES_SW_KEY_FVAL         0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_ICE_ENGINE_USES_HW_KEY_FVAL         0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_BMSK                         0x40000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_SHFT                               0x1e
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_ICE_ENGINE_USES_SW_KEY_FVAL         0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_ICE_ENGINE_USES_HW_KEY_FVAL         0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_BMSK                               0x20000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_SHFT                                     0x1d
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_ENABLE_FVAL                               0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_DISABLE_FVAL                              0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_BMSK                                0x4000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_SHFT                                     0x1a
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_ENABLE_FVAL                               0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_DISABLE_FVAL                              0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK             0x2000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT                  0x19
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_ENABLE_FVAL            0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_DISABLE_FVAL           0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_BMSK                 0x1000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_SHFT                      0x18
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_BMSK                 0x800000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_SHFT                     0x17
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_BMSK                           0x400000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_SHFT                               0x16
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_BMSK                      0x200000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_SHFT                          0x15
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_BMSK                                   0x100000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_SHFT                                       0x14
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_BMSK                               0x80000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_SHFT                                  0x13
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_ENABLE_FVAL                            0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_DISABLE_FVAL                           0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_BMSK                            0x7c000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_SHFT                                0xe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_BMSK                         0x2000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_SHFT                            0xd
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_BMSK                            0x1000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_SHFT                               0xc
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_HANA_FEAT_SET_FVAL                 0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_HANAQ_FEAT_SET_FVAL                0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_BMSK                                     0x800
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_SHFT                                       0xb
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_EFUSE_Q6SS_HVX_HALF_BMSK                            0x400
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_EFUSE_Q6SS_HVX_HALF_SHFT                              0xa
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_BMSK                                   0x200
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_SHFT                                     0x9
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_ENABLE_FVAL                              0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_DISABLE_FVAL                             0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_BMSK                                    0x1e0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_SHFT                                      0x5
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_BMSK                          0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_SHFT                           0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_BMSK                                   0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_SHFT                                   0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_ENABLE_FVAL                            0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_DISABLE_FVAL                           0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_BMSK                                   0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_SHFT                                   0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_ENABLE_FVAL                            0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_DISABLE_FVAL                           0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_BMSK                                   0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_SHFT                                   0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_ENABLE_FVAL                            0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_DISABLE_FVAL                           0x1

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004160)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_OFFS                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004160)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_BMSK                0xffffc000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_SHFT                       0xe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_ENABLE_FVAL                0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_DISABLE_FVAL               0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_BMSK                      0x3c00
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_SHFT                         0xa
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_ENABLE_FVAL                  0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_DISABLE_FVAL                 0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_BMSK                    0x3ff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_SHFT                      0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_ENABLE_FVAL               0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_DISABLE_FVAL              0x1

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004164)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_OFFS                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004164)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_BMSK                       0xc0000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_SHFT                             0x1e
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_BMSK             0x20000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_SHFT                   0x1d
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_ENABLE_FVAL             0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_DISABLE_FVAL            0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_BMSK                 0x10000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_SHFT                       0x1c
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_MOBILE_FVAL                 0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_AUTOMOTIVE_FVAL             0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_BMSK                       0x8000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_SHFT                            0x1b
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_MOBILE_FVAL                      0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_AUTOMOTIVE_FVAL                  0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_BMSK                               0x4000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_SHFT                                    0x1a
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_ENABLE_FVAL                              0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_DISABLE_FVAL                             0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_BMSK                     0x2000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_SHFT                          0x19
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_BMSK                                0x1000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_SHFT                                     0x18
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_ENABLE_FVAL                               0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_DISABLE_FVAL                              0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_BMSK                  0xffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_SHFT                       0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_ENABLE_FVAL                0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_DISABLE_FVAL               0x1

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004168)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_OFFS                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004168)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_RMSK                                           0xfbffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_BMSK            0x80000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_SHFT                  0x1f
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_FUSE_CORTEX_M3_DISABLE_BMSK                    0x40000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_FUSE_CORTEX_M3_DISABLE_SHFT                          0x1e
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_Q_CONFIG_FUSE_BMSK                             0x20000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_Q_CONFIG_FUSE_SHFT                                   0x1d
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_I_MC5_FUSE_BMSK                                0x10000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_I_MC5_FUSE_SHFT                                      0x1c
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_I_MC4_FUSE_BMSK                                 0x8000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_I_MC4_FUSE_SHFT                                      0x1b
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_BMSK              0x2000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_SHFT                   0x19
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_ENABLE_FVAL             0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_DISABLE_FVAL            0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_BMSK              0x1000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_SHFT                   0x18
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_ENABLE_FVAL             0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_DISABLE_FVAL            0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_BMSK               0x800000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_SHFT                   0x17
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_ENABLE_FVAL             0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_DISABLE_FVAL            0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_BMSK               0x400000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_SHFT                   0x16
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_ENABLE_FVAL             0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_DISABLE_FVAL            0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_BMSK               0x200000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_SHFT                   0x15
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_ENABLE_FVAL             0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_DISABLE_FVAL            0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_BMSK                0x100000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_SHFT                    0x14
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_ENABLE_FVAL              0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_DISABLE_FVAL             0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_BMSK                        0x80000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_SHFT                           0x13
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_BMSK                        0x40000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_SHFT                           0x12
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_BMSK                   0x20000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_SHFT                      0x11
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_BMSK                   0x10000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_SHFT                      0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_BMSK                    0x8000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_SHFT                       0xf
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_BMSK                    0x4000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_SHFT                       0xe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_BMSK                   0x2000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_SHFT                      0xd
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_ENABLE_FVAL               0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_DISABLE_FVAL              0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_BMSK                   0x1000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_SHFT                      0xc
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_ENABLE_FVAL               0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_DISABLE_FVAL              0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                 0x800
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                   0xb
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL            0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL           0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK                  0x400
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT                    0xa
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_ENABLE_FVAL             0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_DISABLE_FVAL            0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_BMSK                       0x200
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_SHFT                         0x9
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_ENABLE_FVAL                  0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_DISABLE_FVAL                 0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_BMSK                       0x100
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_SHFT                         0x8
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_ENABLE_FVAL                  0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_DISABLE_FVAL                 0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_BMSK                        0x80
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_SHFT                         0x7
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_ENABLE_FVAL                  0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_DISABLE_FVAL                 0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_BMSK                        0x40
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_SHFT                         0x6
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_ENABLE_FVAL                  0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_DISABLE_FVAL                 0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_BMSK                       0x20
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_SHFT                        0x5
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_DISABLE_FVAL                0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_BMSK                       0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_SHFT                        0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_DISABLE_FVAL                0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK                     0x8
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT                     0x3
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL              0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL             0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK                      0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT                      0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_ENABLE_FVAL               0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_DISABLE_FVAL              0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_BMSK                                  0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_SHFT                                  0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_ENABLE_FVAL                           0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_DISABLE_FVAL                          0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_BMSK                                      0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_SHFT                                      0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_ENABLE_FVAL                               0x0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_DISABLE_FVAL                              0x1

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000416c)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_OFFS                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000416c)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_BMSK                      0xff000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_SHFT                            0x18
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_APSS_KRYO_PP_DISABLE_BMSK                        0x800000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_APSS_KRYO_PP_DISABLE_SHFT                            0x17
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_BMSK                         0x400000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_SHFT                             0x16
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_BMSK                    0x200000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_SHFT                        0x15
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_BMSK                          0x1f8000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_SHFT                               0xf
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_BMSK                        0x4000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_SHFT                           0xe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_BMSK                       0x3fc0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_SHFT                          0x6
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_BMSK                  0x20
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_SHFT                   0x5
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_BMSK                  0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_SHFT                   0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_BMSK                   0x8
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_SHFT                   0x3
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_BMSK                   0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_SHFT                   0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_BMSK                   0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_SHFT                   0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_BMSK                   0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_SHFT                   0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004170)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_OFFS                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004170)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_RMSK                                           0x7fffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_SYS_CFG_GOLDPLUS_PLL_LVAL_BMSK                 0x7f800000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_SYS_CFG_GOLDPLUS_PLL_LVAL_SHFT                       0x17
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_6_BMSK                      0x400000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_6_SHFT                          0x16
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_5_BMSK                      0x200000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_5_SHFT                          0x15
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_4_BMSK                      0x100000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_4_SHFT                          0x14
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_3_BMSK                       0x80000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_3_SHFT                          0x13
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_2_BMSK                       0x40000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_2_SHFT                          0x12
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_1_BMSK                       0x20000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_1_SHFT                          0x11
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_0_BMSK                       0x10000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_0_SHFT                          0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_BMSK                         0xffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_SHFT                            0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004174)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_OFFS                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004174)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_RSVD_BMSK                                      0xfffffffe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_RSVD_SHFT                                             0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_DISABLE_SEC_BOOT_GPIO_BMSK                            0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_DISABLE_SEC_BOOT_GPIO_SHFT                            0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004178)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_OFFS                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004178)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_RSVD_BMSK                                      0xfffffffe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_RSVD_SHFT                                             0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_LEGACY_MBNV6_OVERRIDE_BMSK                            0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_LEGACY_MBNV6_OVERRIDE_SHFT                            0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000417c)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_OFFS                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000417c)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_RSVD_BMSK                                      0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_RSVD_SHFT                                             0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004180)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_OFFS                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004180)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_RSVD_BMSK                                      0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_RSVD_SHFT                                             0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004184)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_OFFS                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004184)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_RSVD_BMSK                                      0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_RSVD_SHFT                                             0x0

#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004188)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_OFFS                                                  (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004188)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ADDR)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_RSVD0_BMSK                                            0xfffffff0
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_RSVD0_SHFT                                                   0x4
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ROOT_CERT_ACTIVATION_LIST_BMSK                               0xf
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ROOT_CERT_ACTIVATION_LIST_SHFT                               0x0

#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000418c)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_OFFS                                                  (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000418c)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_ADDR)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_RSVD1_BMSK                                            0xfffffffe
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_RSVD1_SHFT                                                   0x1
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_CURRENT_UIE_KEY_SEL_BMSK                                     0x1
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_CURRENT_UIE_KEY_SEL_SHFT                                     0x0

#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004190)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_OFFS                                                  (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004190)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ADDR)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_RSVD0_BMSK                                            0xfffffff0
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_RSVD0_SHFT                                                   0x4
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ROOT_CERT_REVOCATION_LIST_BMSK                               0xf
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ROOT_CERT_REVOCATION_LIST_SHFT                               0x0

#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004194)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_OFFS                                                  (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004194)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_ADDR)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_RSVD0_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_RSVD0_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004198)
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_OFFS                                                      (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004198)
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW0_LSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_RSVD0_BMSK                                                0xe0000000
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_RSVD0_SHFT                                                      0x1d
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_MACCHIATO_EN_BMSK                                         0x10000000
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_MACCHIATO_EN_SHFT                                               0x1c
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_FEATURE_ID_BMSK                                            0xff00000
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_FEATURE_ID_SHFT                                                 0x14
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_JTAG_ID_BMSK                                                 0xfffff
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_JTAG_ID_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000419c)
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_OFFS                                                      (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000419c)
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW0_MSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_PTE_DATA1_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_PTE_DATA1_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041a0)
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_OFFS                                                      (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041a0)
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW1_LSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_PTE_DATA0_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_PTE_DATA0_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041a4)
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_OFFS                                                      (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041a4)
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW1_MSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_PTE_DATA1_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_PTE_DATA1_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041a8)
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_OFFS                                                      (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041a8)
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW2_LSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_PTE_DATA0_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_PTE_DATA0_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041ac)
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_OFFS                                                      (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041ac)
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW2_MSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_PTE_DATA1_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_PTE_DATA1_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041b0)
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_OFFS                                                      (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041b0)
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW3_LSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_PTE_DATA0_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_PTE_DATA0_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041b4)
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_OFFS                                                      (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041b4)
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW3_MSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_PTE_DATA1_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_PTE_DATA1_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW4_LSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041b8)
#define HWIO_QFPROM_CORR_PTE_ROW4_LSB_OFFS                                                      (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041b8)
#define HWIO_QFPROM_CORR_PTE_ROW4_LSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW4_LSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW4_LSB_PTE_DATA0_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW4_LSB_PTE_DATA0_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW4_MSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041bc)
#define HWIO_QFPROM_CORR_PTE_ROW4_MSB_OFFS                                                      (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041bc)
#define HWIO_QFPROM_CORR_PTE_ROW4_MSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW4_MSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW4_MSB_PTE_DATA1_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW4_MSB_PTE_DATA1_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW5_LSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041c0)
#define HWIO_QFPROM_CORR_PTE_ROW5_LSB_OFFS                                                      (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041c0)
#define HWIO_QFPROM_CORR_PTE_ROW5_LSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW5_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW5_LSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW5_LSB_PTE_DATA0_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW5_LSB_PTE_DATA0_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW5_MSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041c4)
#define HWIO_QFPROM_CORR_PTE_ROW5_MSB_OFFS                                                      (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041c4)
#define HWIO_QFPROM_CORR_PTE_ROW5_MSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW5_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW5_MSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW5_MSB_PTE_DATA1_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW5_MSB_PTE_DATA1_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_RD_PERM_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041c8)
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041c8)
#define HWIO_QFPROM_CORR_RD_PERM_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_CORR_RD_PERM_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_RD_PERM_LSB_ADDR)
#define HWIO_QFPROM_CORR_RD_PERM_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_RD_PERM_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG31_BMSK                                       0x80000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG31_SHFT                                             0x1f
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG31_ALLOW_READ_FVAL                                   0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG31_DISABLE_READ_FVAL                                 0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG30_BMSK                                       0x40000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG30_SHFT                                             0x1e
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG30_ALLOW_READ_FVAL                                   0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG30_DISABLE_READ_FVAL                                 0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG29_BMSK                                       0x20000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG29_SHFT                                             0x1d
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG29_ALLOW_READ_FVAL                                   0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG29_DISABLE_READ_FVAL                                 0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG28_BMSK                                       0x10000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG28_SHFT                                             0x1c
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG28_ALLOW_READ_FVAL                                   0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG28_DISABLE_READ_FVAL                                 0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_USER_DATA_KEY_BMSK                                          0x8000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_USER_DATA_KEY_SHFT                                               0x1b
#define HWIO_QFPROM_CORR_RD_PERM_LSB_USER_DATA_KEY_ALLOW_READ_FVAL                                     0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_USER_DATA_KEY_DISABLE_READ_FVAL                                   0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_IMAGE_ENCR_KEY1_BMSK                                        0x4000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_IMAGE_ENCR_KEY1_SHFT                                             0x1a
#define HWIO_QFPROM_CORR_RD_PERM_LSB_IMAGE_ENCR_KEY1_ALLOW_READ_FVAL                                   0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_IMAGE_ENCR_KEY1_DISABLE_READ_FVAL                                 0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_BOOT_ROM_PATCH_BMSK                                         0x2000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_BOOT_ROM_PATCH_SHFT                                              0x19
#define HWIO_QFPROM_CORR_RD_PERM_LSB_BOOT_ROM_PATCH_ALLOW_READ_FVAL                                    0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_BOOT_ROM_PATCH_DISABLE_READ_FVAL                                  0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_SEC_KEY_DERIVATION_KEY_BMSK                                 0x1000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_SEC_KEY_DERIVATION_KEY_SHFT                                      0x18
#define HWIO_QFPROM_CORR_RD_PERM_LSB_SEC_KEY_DERIVATION_KEY_ALLOW_READ_FVAL                            0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_SEC_KEY_DERIVATION_KEY_DISABLE_READ_FVAL                          0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SEC_BOOT_BMSK                                            0x800000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SEC_BOOT_SHFT                                                0x17
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SEC_BOOT_ALLOW_READ_FVAL                                      0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SEC_BOOT_DISABLE_READ_FVAL                                    0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_IMAGE_ENCR_KEY_BMSK                                      0x400000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_IMAGE_ENCR_KEY_SHFT                                          0x16
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_IMAGE_ENCR_KEY_ALLOW_READ_FVAL                                0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_IMAGE_ENCR_KEY_DISABLE_READ_FVAL                              0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG21_BMSK                                          0x200000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG21_SHFT                                              0x15
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG21_ALLOW_READ_FVAL                                    0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG21_DISABLE_READ_FVAL                                  0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG20_BMSK                                          0x100000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG20_SHFT                                              0x14
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG20_ALLOW_READ_FVAL                                    0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG20_DISABLE_READ_FVAL                                  0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_MEM_CONFIG_BMSK                                               0x80000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_MEM_CONFIG_SHFT                                                  0x13
#define HWIO_QFPROM_CORR_RD_PERM_LSB_MEM_CONFIG_ALLOW_READ_FVAL                                        0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_MEM_CONFIG_DISABLE_READ_FVAL                                      0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CALIB_BMSK                                                    0x40000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CALIB_SHFT                                                       0x12
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CALIB_ALLOW_READ_FVAL                                             0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CALIB_DISABLE_READ_FVAL                                           0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PK_HASH0_BMSK                                                 0x20000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PK_HASH0_SHFT                                                    0x11
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PK_HASH0_ALLOW_READ_FVAL                                          0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PK_HASH0_DISABLE_READ_FVAL                                        0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_5_BMSK                                          0x10000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_5_SHFT                                             0x10
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_5_ALLOW_READ_FVAL                                   0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_5_DISABLE_READ_FVAL                                 0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_4_BMSK                                           0x8000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_4_SHFT                                              0xf
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_4_ALLOW_READ_FVAL                                   0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_4_DISABLE_READ_FVAL                                 0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_3_BMSK                                           0x4000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_3_SHFT                                              0xe
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_3_ALLOW_READ_FVAL                                   0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_3_DISABLE_READ_FVAL                                 0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_2_BMSK                                           0x2000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_2_SHFT                                              0xd
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_2_ALLOW_READ_FVAL                                   0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_2_DISABLE_READ_FVAL                                 0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_1_BMSK                                           0x1000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_1_SHFT                                              0xc
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_1_ALLOW_READ_FVAL                                   0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_1_DISABLE_READ_FVAL                                 0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_FEAT_CONFIG_BMSK                                                0x800
#define HWIO_QFPROM_CORR_RD_PERM_LSB_FEAT_CONFIG_SHFT                                                  0xb
#define HWIO_QFPROM_CORR_RD_PERM_LSB_FEAT_CONFIG_ALLOW_READ_FVAL                                       0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_FEAT_CONFIG_DISABLE_READ_FVAL                                     0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_CONFIG_BMSK                                                 0x400
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_CONFIG_SHFT                                                   0xa
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_CONFIG_ALLOW_READ_FVAL                                        0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_CONFIG_DISABLE_READ_FVAL                                      0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_FEC_EN_BMSK                                                     0x200
#define HWIO_QFPROM_CORR_RD_PERM_LSB_FEC_EN_SHFT                                                       0x9
#define HWIO_QFPROM_CORR_RD_PERM_LSB_FEC_EN_ALLOW_READ_FVAL                                            0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_FEC_EN_DISABLE_READ_FVAL                                          0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_WR_PERM_BMSK                                                    0x100
#define HWIO_QFPROM_CORR_RD_PERM_LSB_WR_PERM_SHFT                                                      0x8
#define HWIO_QFPROM_CORR_RD_PERM_LSB_WR_PERM_ALLOW_READ_FVAL                                           0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_WR_PERM_DISABLE_READ_FVAL                                         0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_RD_PERM_BMSK                                                     0x80
#define HWIO_QFPROM_CORR_RD_PERM_LSB_RD_PERM_SHFT                                                      0x7
#define HWIO_QFPROM_CORR_RD_PERM_LSB_RD_PERM_ALLOW_READ_FVAL                                           0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_RD_PERM_DISABLE_READ_FVAL                                         0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PTE_BMSK                                                         0x40
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PTE_SHFT                                                          0x6
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PTE_ALLOW_READ_FVAL                                               0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PTE_DISABLE_READ_FVAL                                             0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_MRC_2_0_BMSK                                                     0x20
#define HWIO_QFPROM_CORR_RD_PERM_LSB_MRC_2_0_SHFT                                                      0x5
#define HWIO_QFPROM_CORR_RD_PERM_LSB_MRC_2_0_ALLOW_READ_FVAL                                           0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_MRC_2_0_DISABLE_READ_FVAL                                         0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CM_FEAT_CONFIG_BMSK                                              0x10
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CM_FEAT_CONFIG_SHFT                                               0x4
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CM_FEAT_CONFIG_ALLOW_READ_FVAL                                    0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CM_FEAT_CONFIG_DISABLE_READ_FVAL                                  0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PRI_KEY_DERIVATION_KEY_BMSK                                       0x8
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PRI_KEY_DERIVATION_KEY_SHFT                                       0x3
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PRI_KEY_DERIVATION_KEY_ALLOW_READ_FVAL                            0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PRI_KEY_DERIVATION_KEY_DISABLE_READ_FVAL                          0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_BOOT_PATCH_HASH_BMSK                                              0x4
#define HWIO_QFPROM_CORR_RD_PERM_LSB_BOOT_PATCH_HASH_SHFT                                              0x2
#define HWIO_QFPROM_CORR_RD_PERM_LSB_BOOT_PATCH_HASH_ALLOW_READ_FVAL                                   0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_BOOT_PATCH_HASH_DISABLE_READ_FVAL                                 0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_LCM_BMSK                                                          0x2
#define HWIO_QFPROM_CORR_RD_PERM_LSB_LCM_SHFT                                                          0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_LCM_ALLOW_READ_FVAL                                               0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_LCM_DISABLE_READ_FVAL                                             0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CRI_CM_PRIVATE_BMSK                                               0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CRI_CM_PRIVATE_SHFT                                               0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CRI_CM_PRIVATE_ALLOW_READ_FVAL                                    0x0
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CRI_CM_PRIVATE_DISABLE_READ_FVAL                                  0x1

#define HWIO_QFPROM_CORR_RD_PERM_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041cc)
#define HWIO_QFPROM_CORR_RD_PERM_MSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041cc)
#define HWIO_QFPROM_CORR_RD_PERM_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_CORR_RD_PERM_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_RD_PERM_MSB_ADDR)
#define HWIO_QFPROM_CORR_RD_PERM_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_RD_PERM_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_RD_PERM_MSB_RSVD0_BMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_RD_PERM_MSB_RSVD0_SHFT                                                        0x0

#define HWIO_QFPROM_CORR_WR_PERM_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041d0)
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041d0)
#define HWIO_QFPROM_CORR_WR_PERM_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_CORR_WR_PERM_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_WR_PERM_LSB_ADDR)
#define HWIO_QFPROM_CORR_WR_PERM_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_WR_PERM_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG31_BMSK                                       0x80000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG31_SHFT                                             0x1f
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG31_ALLOW_WRITE_FVAL                                  0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG31_DISABLE_WRITE_FVAL                                0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG30_BMSK                                       0x40000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG30_SHFT                                             0x1e
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG30_ALLOW_WRITE_FVAL                                  0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG30_DISABLE_WRITE_FVAL                                0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG29_BMSK                                       0x20000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG29_SHFT                                             0x1d
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG29_ALLOW_WRITE_FVAL                                  0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG29_DISABLE_WRITE_FVAL                                0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG28_BMSK                                       0x10000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG28_SHFT                                             0x1c
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG28_ALLOW_WRITE_FVAL                                  0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG28_DISABLE_WRITE_FVAL                                0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_USER_DATA_KEY_BMSK                                          0x8000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_USER_DATA_KEY_SHFT                                               0x1b
#define HWIO_QFPROM_CORR_WR_PERM_LSB_USER_DATA_KEY_ALLOW_WRITE_FVAL                                    0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_USER_DATA_KEY_DISABLE_WRITE_FVAL                                  0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_IMAGE_ENCR_KEY1_BMSK                                        0x4000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_IMAGE_ENCR_KEY1_SHFT                                             0x1a
#define HWIO_QFPROM_CORR_WR_PERM_LSB_IMAGE_ENCR_KEY1_ALLOW_WRITE_FVAL                                  0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_IMAGE_ENCR_KEY1_DISABLE_WRITE_FVAL                                0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_BOOT_ROM_PATCH_BMSK                                         0x2000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_BOOT_ROM_PATCH_SHFT                                              0x19
#define HWIO_QFPROM_CORR_WR_PERM_LSB_BOOT_ROM_PATCH_ALLOW_WRITE_FVAL                                   0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_BOOT_ROM_PATCH_DISABLE_WRITE_FVAL                                 0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_BMSK                                 0x1000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_SHFT                                      0x18
#define HWIO_QFPROM_CORR_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_ALLOW_WRITE_FVAL                           0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_DISABLE_WRITE_FVAL                         0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SEC_BOOT_BMSK                                            0x800000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SEC_BOOT_SHFT                                                0x17
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SEC_BOOT_ALLOW_WRITE_FVAL                                     0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SEC_BOOT_DISABLE_WRITE_FVAL                                   0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_IMAGE_ENCR_KEY_BMSK                                      0x400000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_IMAGE_ENCR_KEY_SHFT                                          0x16
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_IMAGE_ENCR_KEY_ALLOW_WRITE_FVAL                               0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_IMAGE_ENCR_KEY_DISABLE_WRITE_FVAL                             0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG21_BMSK                                          0x200000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG21_SHFT                                              0x15
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG21_ALLOW_WRITE_FVAL                                   0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG21_DISABLE_WRITE_FVAL                                 0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG20_BMSK                                          0x100000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG20_SHFT                                              0x14
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG20_ALLOW_WRITE_FVAL                                   0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG20_DISABLE_WRITE_FVAL                                 0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_MEM_CONFIG_BMSK                                               0x80000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_MEM_CONFIG_SHFT                                                  0x13
#define HWIO_QFPROM_CORR_WR_PERM_LSB_MEM_CONFIG_ALLOW_WRITE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_MEM_CONFIG_DISABLE_WRITE_FVAL                                     0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CALIB_BMSK                                                    0x40000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CALIB_SHFT                                                       0x12
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CALIB_ALLOW_WRITE_FVAL                                            0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CALIB_DISABLE_WRITE_FVAL                                          0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PK_HASH0_BMSK                                                 0x20000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PK_HASH0_SHFT                                                    0x11
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PK_HASH0_ALLOW_WRITE_FVAL                                         0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PK_HASH0_DISABLE_WRITE_FVAL                                       0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_5_BMSK                                          0x10000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_5_SHFT                                             0x10
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_5_ALLOW_WRITE_FVAL                                  0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_5_DISABLE_WRITE_FVAL                                0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_4_BMSK                                           0x8000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_4_SHFT                                              0xf
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_4_ALLOW_WRITE_FVAL                                  0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_4_DISABLE_WRITE_FVAL                                0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_3_BMSK                                           0x4000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_3_SHFT                                              0xe
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_3_ALLOW_WRITE_FVAL                                  0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_3_DISABLE_WRITE_FVAL                                0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_2_BMSK                                           0x2000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_2_SHFT                                              0xd
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_2_ALLOW_WRITE_FVAL                                  0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_2_DISABLE_WRITE_FVAL                                0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_1_BMSK                                           0x1000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_1_SHFT                                              0xc
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_1_ALLOW_WRITE_FVAL                                  0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_1_DISABLE_WRITE_FVAL                                0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_CONFIG_BMSK                                                 0x800
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_CONFIG_SHFT                                                   0xb
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_CONFIG_ALLOW_WRITE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_CONFIG_DISABLE_WRITE_FVAL                                     0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_FEAT_CONFIG_BMSK                                                0x400
#define HWIO_QFPROM_CORR_WR_PERM_LSB_FEAT_CONFIG_SHFT                                                  0xa
#define HWIO_QFPROM_CORR_WR_PERM_LSB_FEAT_CONFIG_ALLOW_WRITE_FVAL                                      0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_FEAT_CONFIG_DISABLE_WRITE_FVAL                                    0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_FEC_EN_BMSK                                                     0x200
#define HWIO_QFPROM_CORR_WR_PERM_LSB_FEC_EN_SHFT                                                       0x9
#define HWIO_QFPROM_CORR_WR_PERM_LSB_FEC_EN_ALLOW_WRITE_FVAL                                           0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_FEC_EN_DISABLE_WRITE_FVAL                                         0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_WR_PERM_BMSK                                                    0x100
#define HWIO_QFPROM_CORR_WR_PERM_LSB_WR_PERM_SHFT                                                      0x8
#define HWIO_QFPROM_CORR_WR_PERM_LSB_WR_PERM_ALLOW_WRITE_FVAL                                          0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_WR_PERM_DISABLE_WRITE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_RD_PERM_BMSK                                                     0x80
#define HWIO_QFPROM_CORR_WR_PERM_LSB_RD_PERM_SHFT                                                      0x7
#define HWIO_QFPROM_CORR_WR_PERM_LSB_RD_PERM_ALLOW_WRITE_FVAL                                          0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_RD_PERM_DISABLE_WRITE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PTE_BMSK                                                         0x40
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PTE_SHFT                                                          0x6
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PTE_ALLOW_WRITE_FVAL                                              0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PTE_DISABLE_WRITE_FVAL                                            0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_MRC_2_0_BMSK                                                     0x20
#define HWIO_QFPROM_CORR_WR_PERM_LSB_MRC_2_0_SHFT                                                      0x5
#define HWIO_QFPROM_CORR_WR_PERM_LSB_MRC_2_0_ALLOW_WRITE_FVAL                                          0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_MRC_2_0_DISABLE_WRITE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CM_FEAT_CONFIG_BMSK                                              0x10
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CM_FEAT_CONFIG_SHFT                                               0x4
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CM_FEAT_CONFIG_ALLOW_WRITE_FVAL                                   0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CM_FEAT_CONFIG_DISABLE_WRITE_FVAL                                 0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PRI_KEY_DERIVATION_KEY_BMSK                                       0x8
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PRI_KEY_DERIVATION_KEY_SHFT                                       0x3
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PRI_KEY_DERIVATION_KEY_ALLOW_WRITE_FVAL                           0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PRI_KEY_DERIVATION_KEY_DISABLE_WRITE_FVAL                         0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_BOOT_PATCH_HASH_BMSK                                              0x4
#define HWIO_QFPROM_CORR_WR_PERM_LSB_BOOT_PATCH_HASH_SHFT                                              0x2
#define HWIO_QFPROM_CORR_WR_PERM_LSB_BOOT_PATCH_HASH_ALLOW_WRITE_FVAL                                  0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_BOOT_PATCH_HASH_DISABLE_WRITE_FVAL                                0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_LCM_BMSK                                                          0x2
#define HWIO_QFPROM_CORR_WR_PERM_LSB_LCM_SHFT                                                          0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_LCM_ALLOW_WRITE_FVAL                                              0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_LCM_DISABLE_WRITE_FVAL                                            0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CRI_CM_PRIVATE_BMSK                                               0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CRI_CM_PRIVATE_SHFT                                               0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CRI_CM_PRIVATE_ALLOW_WRITE_FVAL                                   0x0
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CRI_CM_PRIVATE_DISABLE_WRITE_FVAL                                 0x1

#define HWIO_QFPROM_CORR_WR_PERM_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041d4)
#define HWIO_QFPROM_CORR_WR_PERM_MSB_OFFS                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041d4)
#define HWIO_QFPROM_CORR_WR_PERM_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_CORR_WR_PERM_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_WR_PERM_MSB_ADDR)
#define HWIO_QFPROM_CORR_WR_PERM_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_WR_PERM_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_WR_PERM_MSB_RSVD0_BMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_WR_PERM_MSB_RSVD0_SHFT                                                        0x0

#define HWIO_QFPROM_CORR_FEC_EN_LSB_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041d8)
#define HWIO_QFPROM_CORR_FEC_EN_LSB_OFFS                                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041d8)
#define HWIO_QFPROM_CORR_FEC_EN_LSB_RMSK                                                        0xffffffff
#define HWIO_QFPROM_CORR_FEC_EN_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEC_EN_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEC_EN_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEC_EN_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION31_FEC_EN_BMSK                                        0x80000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION31_FEC_EN_SHFT                                              0x1f
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION31_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION31_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION30_FEC_EN_BMSK                                        0x40000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION30_FEC_EN_SHFT                                              0x1e
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION30_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION30_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION29_FEC_EN_BMSK                                        0x20000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION29_FEC_EN_SHFT                                              0x1d
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION29_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION29_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION28_FEC_EN_BMSK                                        0x10000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION28_FEC_EN_SHFT                                              0x1c
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION28_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION28_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION27_FEC_EN_BMSK                                         0x8000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION27_FEC_EN_SHFT                                              0x1b
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION27_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION27_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION26_FEC_EN_BMSK                                         0x4000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION26_FEC_EN_SHFT                                              0x1a
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION26_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION26_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION25_FEC_EN_BMSK                                         0x2000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION25_FEC_EN_SHFT                                              0x19
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION25_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION25_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION24_FEC_EN_BMSK                                         0x1000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION24_FEC_EN_SHFT                                              0x18
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION24_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION24_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION23_FEC_EN_BMSK                                          0x800000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION23_FEC_EN_SHFT                                              0x17
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION23_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION23_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION22_FEC_EN_BMSK                                          0x400000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION22_FEC_EN_SHFT                                              0x16
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION22_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION22_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION21_FEC_EN_BMSK                                          0x200000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION21_FEC_EN_SHFT                                              0x15
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION21_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION21_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION20_FEC_EN_BMSK                                          0x100000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION20_FEC_EN_SHFT                                              0x14
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION20_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION20_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION19_FEC_EN_BMSK                                           0x80000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION19_FEC_EN_SHFT                                              0x13
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION19_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION19_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION18_FEC_EN_BMSK                                           0x40000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION18_FEC_EN_SHFT                                              0x12
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION18_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION18_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION17_FEC_EN_BMSK                                           0x20000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION17_FEC_EN_SHFT                                              0x11
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION17_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION17_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION16_FEC_EN_BMSK                                           0x10000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION16_FEC_EN_SHFT                                              0x10
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION16_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION16_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION15_FEC_EN_BMSK                                            0x8000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION15_FEC_EN_SHFT                                               0xf
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION15_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION15_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION14_FEC_EN_BMSK                                            0x4000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION14_FEC_EN_SHFT                                               0xe
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION14_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION14_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION13_FEC_EN_BMSK                                            0x2000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION13_FEC_EN_SHFT                                               0xd
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION13_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION13_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION12_FEC_EN_BMSK                                            0x1000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION12_FEC_EN_SHFT                                               0xc
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION12_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION12_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION11_FEC_EN_BMSK                                             0x800
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION11_FEC_EN_SHFT                                               0xb
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION11_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION11_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION10_FEC_EN_BMSK                                             0x400
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION10_FEC_EN_SHFT                                               0xa
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION10_FEC_EN_DISABLE_FVAL                                       0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION10_FEC_EN_ENABLE_FVAL                                        0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION9_FEC_EN_BMSK                                              0x200
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION9_FEC_EN_SHFT                                                0x9
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION9_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION9_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION8_FEC_EN_BMSK                                              0x100
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION8_FEC_EN_SHFT                                                0x8
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION8_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION8_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION7_FEC_EN_BMSK                                               0x80
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION7_FEC_EN_SHFT                                                0x7
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION7_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION7_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION6_FEC_EN_BMSK                                               0x40
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION6_FEC_EN_SHFT                                                0x6
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION6_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION6_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION5_FEC_EN_BMSK                                               0x20
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION5_FEC_EN_SHFT                                                0x5
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION5_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION5_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION4_FEC_EN_BMSK                                               0x10
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION4_FEC_EN_SHFT                                                0x4
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION4_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION4_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION3_FEC_EN_BMSK                                                0x8
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION3_FEC_EN_SHFT                                                0x3
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION3_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION3_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION2_FEC_EN_BMSK                                                0x4
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION2_FEC_EN_SHFT                                                0x2
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION2_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION2_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION1_FEC_EN_BMSK                                                0x2
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION1_FEC_EN_SHFT                                                0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION1_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION1_FEC_EN_ENABLE_FVAL                                         0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION0_FEC_EN_BMSK                                                0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION0_FEC_EN_SHFT                                                0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION0_FEC_EN_DISABLE_FVAL                                        0x0
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION0_FEC_EN_ENABLE_FVAL                                         0x1

#define HWIO_QFPROM_CORR_FEC_EN_MSB_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041dc)
#define HWIO_QFPROM_CORR_FEC_EN_MSB_OFFS                                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041dc)
#define HWIO_QFPROM_CORR_FEC_EN_MSB_RMSK                                                        0xffffffff
#define HWIO_QFPROM_CORR_FEC_EN_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEC_EN_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEC_EN_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEC_EN_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEC_EN_MSB_RSVD0_BMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_FEC_EN_MSB_RSVD0_SHFT                                                         0x0

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041e0)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041e0)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_IN)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                   0x80000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                         0x1f
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_BMSK                    0x40000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_SHFT                          0x1e
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_BMSK                             0x20000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_SHFT                                   0x1d
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_ENABLE_FVAL                             0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_DISABLE_FVAL                            0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_BMSK                          0x10000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_SHFT                                0x1c
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_ENABLE_FVAL                          0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_DISABLE_FVAL                         0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SP_DISABLE_BMSK                                     0x8000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SP_DISABLE_SHFT                                          0x1b
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SP_DISABLE_ENABLE_FVAL                                    0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SP_DISABLE_DISABLE_FVAL                                   0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_BMSK                                    0x4000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_SHFT                                         0x1a
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_ENABLE_FVAL                                   0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_DISABLE_FVAL                                  0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_DISABLE_IN_ROM_BMSK                           0x2000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_DISABLE_IN_ROM_SHFT                                0x19
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_BMSK                0x1000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_SHFT                     0x18
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_DISABLE_FVAL              0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_ENABLE_FVAL               0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_BMSK               0x800000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_SHFT                   0x17
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_DISABLE_FVAL            0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_ENABLE_FVAL             0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_BMSK                                  0x400000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_SHFT                                      0x16
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_DISABLE_FVAL                               0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_BMSK                           0x200000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_SHFT                               0x15
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_USE_OEM_ID_FVAL                     0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_USE_SERIAL_NUM_FVAL                 0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_BMSK                            0x100000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_SHFT                                0x14
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_ENABLE_FVAL                          0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_DISABLE_FVAL                         0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_IMAGE_ENCRYPTION_ENABLE_BMSK                          0x80000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_IMAGE_ENCRYPTION_ENABLE_SHFT                             0x13
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ROOT_CERT_TOTAL_NUM_BMSK                              0x60000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ROOT_CERT_TOTAL_NUM_SHFT                                 0x11
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_USB_TYPE_C_DISABLE_BMSK                           0x10000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_USB_TYPE_C_DISABLE_SHFT                              0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_LOG_DISABLE_BMSK                                   0x8000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_LOG_DISABLE_SHFT                                      0xf
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_WDOG_EN_BMSK                                           0x4000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_WDOG_EN_SHFT                                              0xe
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_WDOG_EN_USE_GPIO_FVAL                                     0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_WDOG_EN_IGNORE_GPIO_ENABLE_WDOG_FVAL                      0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_BMSK              0x2000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_SHFT                 0xd
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_DISABLE_EDL_RESET_FVAL        0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_ENABLE_EDL_RESET_FVAL        0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_FUSE_PROG_DISABLE_BMSK                              0x1000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_FUSE_PROG_DISABLE_SHFT                                 0xc
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SPI_CLK_BOOT_FREQ_BMSK                                  0x800
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SPI_CLK_BOOT_FREQ_SHFT                                    0xb
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_BMSK                          0x400
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_SHFT                            0xa
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_SD_USB_FVAL                     0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_QSPI_SD_USB_FVAL                0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_BMSK                                          0x3e0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SHFT                                            0x5
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_DEFAULT_FVAL                                    0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SD_UFS_EDL_FVAL                                 0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SD_EDL_FVAL                                     0x2
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_USB_EDL_FVAL                                    0x3
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_QSPI_EDL_FVAL                                   0x4
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SPI_EDL_FVAL                                    0x5
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_UGSG4_SD_USB_EDL_FVAL                           0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SDCC_MCLK_BOOT_FREQ_BMSK                                 0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SDCC_MCLK_BOOT_FREQ_SHFT                                  0x4
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SDCC_MCLK_BOOT_FREQ_ENUM_19_2_MHZ_FVAL                    0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SDCC_MCLK_BOOT_FREQ_ENUM_25_MHZ_FVAL                      0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_BMSK                               0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_SHFT                               0x3
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_USE_FORCE_USB_BOOT_GPIO_TO_FORCE_BOOT_FROM_USB_FVAL        0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_NOT_USE_FORCE_USB_BOOT_PIN_FVAL        0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_BMSK                                  0x4
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_SHFT                                  0x2
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_USE_FORCE_USB_BOOT_GPIO_TO_FORCE_BOOT_FROM_USB_FVAL        0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_NOT_USE_FORCE_USB_BOOT_PIN_FVAL        0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_BMSK                                         0x2
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_SHFT                                         0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_TIMEOUT_DISABLED_FVAL                        0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_TIMEOUT_ENABLED_90S_FVAL                     0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_BMSK                                      0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_SHFT                                      0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_DOWNLOADER_ENABLED_FVAL                   0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_DOWNLOADER_DISABLED_FVAL                  0x1

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041e4)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041e4)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_ADDR)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_RSVD1_BMSK                                         0xffffc000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_RSVD1_SHFT                                                0xe
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_BMSK                        0x2000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_SHFT                           0xd
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_BMSK                        0x1000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_SHFT                           0xc
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_BMSK                         0x800
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_SHFT                           0xb
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_BMSK                         0x400
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_SHFT                           0xa
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_BMSK                         0x200
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_SHFT                           0x9
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_BMSK                          0x100
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_SHFT                            0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_BMSK                                  0x80
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_SHFT                                   0x7
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_ENABLE_FVAL                            0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_DISABLE_FVAL                           0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_BMSK                                  0x40
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_SHFT                                   0x6
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_ENABLE_FVAL                            0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_DISABLE_FVAL                           0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_BMSK                             0x20
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_SHFT                              0x5
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_ENABLE_FVAL                       0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_DISABLE_FVAL                      0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_BMSK                             0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_SHFT                              0x4
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_ENABLE_FVAL                       0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_DISABLE_FVAL                      0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_BMSK                              0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_SHFT                              0x3
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_ENABLE_FVAL                       0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_DISABLE_FVAL                      0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_BMSK                              0x4
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_SHFT                              0x2
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_ENABLE_FVAL                       0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_DISABLE_FVAL                      0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_BMSK                             0x2
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_SHFT                             0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_ENABLE_FVAL                      0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_DISABLE_FVAL                     0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_BMSK                             0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_SHFT                             0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_ENABLE_FVAL                      0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_DISABLE_FVAL                     0x1

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041e8)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041e8)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_ADDR)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_DISABLE_RSA_BMSK                                   0x80000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_DISABLE_RSA_SHFT                                         0x1f
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_EKU_ENFORCEMENT_EN_BMSK                            0x40000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_EKU_ENFORCEMENT_EN_SHFT                                  0x1e
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD2_BMSK                                         0x3fff0000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD2_SHFT                                               0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_BMSK                                0x8000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_SHFT                                   0xf
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_NOT_SECURE_FVAL                        0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_SECURE_FVAL                            0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_BMSK                                0x4000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_SHFT                                   0xe
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_NOT_SECURE_FVAL                        0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_SECURE_FVAL                            0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_BMSK                                0x2000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_SHFT                                   0xd
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_NOT_SECURE_FVAL                        0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_SECURE_FVAL                            0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_BMSK                                0x1000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_SHFT                                   0xc
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_NOT_SECURE_FVAL                        0x0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_SECURE_FVAL                            0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD3_BMSK                                              0x800
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD3_SHFT                                                0xb
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPU_IAR_ENABLED_BMSK                                    0x400
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPU_IAR_ENABLED_SHFT                                      0xa
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_BMSK                                              0x300
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_SHFT                                                0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_OVERRIDE_BMSK                          0x80
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_OVERRIDE_SHFT                           0x7
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_FIPS_OVERRIDE_BMSK                                    0x40
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_FIPS_OVERRIDE_SHFT                                     0x6
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_MODEM_CRYPTO_FIPS_ENABLE_BMSK                            0x20
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_MODEM_CRYPTO_FIPS_ENABLE_SHFT                             0x5
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_ENABLE_BMSK                            0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_ENABLE_SHFT                             0x4
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_FIPS_ENABLE_BMSK                                       0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_FIPS_ENABLE_SHFT                                       0x3
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_NVM_AR_CONFIG_BMSK                                     0x6
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_NVM_AR_CONFIG_SHFT                                     0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD0_BMSK                                                0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD0_SHFT                                                0x0

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041ec)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041ec)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_ADDR)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OEM_PRODUCT_ID_BMSK                                0xffff0000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OEM_PRODUCT_ID_SHFT                                      0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OEM_HW_ID_BMSK                                         0xffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OEM_HW_ID_SHFT                                            0x0

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041f0)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041f0)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_ADDR)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PERIPH_VID_BMSK                                    0xffff0000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PERIPH_VID_SHFT                                          0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PERIPH_PID_BMSK                                        0xffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PERIPH_PID_SHFT                                           0x0

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041f4)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041f4)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ADDR)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_RSVD0_BMSK                                         0xffffff00
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_RSVD0_SHFT                                                0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ANTI_ROLLBACK_FEATURE_EN_BMSK                            0xff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ANTI_ROLLBACK_FEATURE_EN_SHFT                             0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041f8)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041f8)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_RMSK                                              0x7fffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_BMSK                      0x40000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_SHFT                            0x1e
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_ENABLE_FVAL                      0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_DISABLE_FVAL                     0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_BMSK                                0x20000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_SHFT                                      0x1d
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_DISABLE_FVAL                               0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_BMSK                         0x1fe00000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_SHFT                               0x15
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_BMSK                          0x180000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_SHFT                              0x13
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_DEFAULT_FVAL                       0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_ENUM_1024_FVAL                     0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_ENUM_2048_FVAL                     0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_ENUM_2560_FVAL                     0x3
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_BMSK                        0x40000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_SHFT                           0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_BMSK                        0x20000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_SHFT                           0x11
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_BMSK                                 0x10000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_SHFT                                    0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_ENABLE_FVAL                              0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_DISABLE_FVAL                             0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_BMSK                                 0x8000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_SHFT                                    0xf
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_ENABLE_FVAL                             0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_DISABLE_FVAL                            0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_BMSK                                 0x4000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_SHFT                                    0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_ENABLE_FVAL                             0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_DISABLE_FVAL                            0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_BMSK                                       0x2000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_SHFT                                          0xd
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_ENABLE_FVAL                                   0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_DISABLE_FVAL                                  0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_BMSK                                     0x1000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_SHFT                                        0xc
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_ENABLE_FVAL                                 0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_DISABLE_FVAL                                0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_BMSK                            0x800
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_SHFT                              0xb
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_ENABLE_FVAL                       0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_DISABLE_FVAL                      0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK                    0x400
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT                      0xa
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_ENABLE_FVAL               0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_DISABLE_FVAL              0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_BMSK                                     0x200
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_SHFT                                       0x9
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_DISABLE_FVAL                               0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_BMSK                                     0x100
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_SHFT                                       0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_DISABLE_FVAL                               0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_BMSK                                         0x80
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_SHFT                                          0x7
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_ENABLE_FVAL                                   0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_DISABLE_FVAL                                  0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_BMSK                               0x40
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_SHFT                                0x6
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_ENABLE_FVAL                         0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_DISABLE_FVAL                        0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EFUSE_CAM_SBI_ENABLE_IF_BMSK                            0x20
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EFUSE_CAM_SBI_ENABLE_IF_SHFT                             0x5
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_BMSK                                      0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_SHFT                                       0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_USB_PORT0_FVAL                             0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_USB_PORT1_FVAL                             0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_BMSK                                        0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_SHFT                                        0x3
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_BMSK                              0x7
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_SHFT                              0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_ENABLE_PATCHING_FVAL              0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_DISABLE_PATCHING_FVAL             0x1

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041fc)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041fc)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_RMSK                                              0xe7fffff7
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_BMSK                            0x80000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_SHFT                                  0x1f
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_ICE_ENGINE_USES_SW_KEY_FVAL            0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_ICE_ENGINE_USES_HW_KEY_FVAL            0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_BMSK                            0x40000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_SHFT                                  0x1e
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_ICE_ENGINE_USES_SW_KEY_FVAL            0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_ICE_ENGINE_USES_HW_KEY_FVAL            0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_BMSK                                  0x20000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_SHFT                                        0x1d
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_ENABLE_FVAL                                  0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_DISABLE_FVAL                                 0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_BMSK                                   0x4000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_SHFT                                        0x1a
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_ENABLE_FVAL                                  0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_DISABLE_FVAL                                 0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK                0x2000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT                     0x19
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_ENABLE_FVAL               0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_DISABLE_FVAL              0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_BMSK                    0x1000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_SHFT                         0x18
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_BMSK                    0x800000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_SHFT                        0x17
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_BMSK                              0x400000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_SHFT                                  0x16
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_BMSK                         0x200000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_SHFT                             0x15
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_ENABLE_FVAL                       0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_DISABLE_FVAL                      0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_BMSK                                      0x100000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_SHFT                                          0x14
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_BMSK                                  0x80000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_SHFT                                     0x13
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_ENABLE_FVAL                               0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_DISABLE_FVAL                              0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_BMSK                               0x7c000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_SHFT                                   0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_BMSK                            0x2000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_SHFT                               0xd
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_ENABLE_FVAL                        0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_DISABLE_FVAL                       0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_BMSK                               0x1000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_SHFT                                  0xc
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_HANA_FEAT_SET_FVAL                    0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_HANAQ_FEAT_SET_FVAL                   0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_BMSK                                        0x800
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_SHFT                                          0xb
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_EFUSE_Q6SS_HVX_HALF_BMSK                               0x400
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_EFUSE_Q6SS_HVX_HALF_SHFT                                 0xa
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_BMSK                                      0x200
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_SHFT                                        0x9
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_ENABLE_FVAL                                 0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_DISABLE_FVAL                                0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_BMSK                                       0x1e0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_SHFT                                         0x5
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_BMSK                             0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_SHFT                              0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_ENABLE_FVAL                       0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_DISABLE_FVAL                      0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_BMSK                                      0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_SHFT                                      0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_ENABLE_FVAL                               0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_DISABLE_FVAL                              0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_BMSK                                      0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_SHFT                                      0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_ENABLE_FVAL                               0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_DISABLE_FVAL                              0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_BMSK                                      0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_SHFT                                      0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_ENABLE_FVAL                               0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_DISABLE_FVAL                              0x1

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004200)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004200)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_BMSK                   0xffffc000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_SHFT                          0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_BMSK                         0x3c00
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_SHFT                            0xa
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_BMSK                       0x3ff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_SHFT                         0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_ENABLE_FVAL                  0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_DISABLE_FVAL                 0x1

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004204)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004204)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_BMSK                          0xc0000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_SHFT                                0x1e
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_BMSK                0x20000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_SHFT                      0x1d
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_BMSK                    0x10000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_SHFT                          0x1c
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_MOBILE_FVAL                    0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_AUTOMOTIVE_FVAL                0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_BMSK                          0x8000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_SHFT                               0x1b
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_MOBILE_FVAL                         0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_AUTOMOTIVE_FVAL                     0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_BMSK                                  0x4000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_SHFT                                       0x1a
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_ENABLE_FVAL                                 0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_DISABLE_FVAL                                0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_BMSK                        0x2000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_SHFT                             0x19
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_ENABLE_FVAL                       0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_DISABLE_FVAL                      0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_BMSK                                   0x1000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_SHFT                                        0x18
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_ENABLE_FVAL                                  0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_DISABLE_FVAL                                 0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_BMSK                     0xffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_SHFT                          0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_DISABLE_FVAL                  0x1

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004208)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004208)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_RMSK                                              0xfbffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_BMSK               0x80000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_SHFT                     0x1f
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_FUSE_CORTEX_M3_DISABLE_BMSK                       0x40000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_FUSE_CORTEX_M3_DISABLE_SHFT                             0x1e
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_Q_CONFIG_FUSE_BMSK                                0x20000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_Q_CONFIG_FUSE_SHFT                                      0x1d
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_I_MC5_FUSE_BMSK                                   0x10000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_I_MC5_FUSE_SHFT                                         0x1c
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_I_MC4_FUSE_BMSK                                    0x8000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_I_MC4_FUSE_SHFT                                         0x1b
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_BMSK                 0x2000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_SHFT                      0x19
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_BMSK                 0x1000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_SHFT                      0x18
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_BMSK                  0x800000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_SHFT                      0x17
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_BMSK                  0x400000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_SHFT                      0x16
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_BMSK                  0x200000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_SHFT                      0x15
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_BMSK                   0x100000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_SHFT                       0x14
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_DISABLE_FVAL                0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_BMSK                           0x80000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_SHFT                              0x13
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_ENABLE_FVAL                        0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_DISABLE_FVAL                       0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_BMSK                           0x40000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_SHFT                              0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_ENABLE_FVAL                        0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_DISABLE_FVAL                       0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_BMSK                      0x20000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_SHFT                         0x11
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_BMSK                      0x10000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_SHFT                         0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_BMSK                       0x8000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_SHFT                          0xf
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_BMSK                       0x4000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_SHFT                          0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_ENABLE_FVAL                   0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_DISABLE_FVAL                  0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_BMSK                      0x2000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_SHFT                         0xd
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_ENABLE_FVAL                  0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_DISABLE_FVAL                 0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_BMSK                      0x1000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_SHFT                         0xc
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_ENABLE_FVAL                  0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_DISABLE_FVAL                 0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                    0x800
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                      0xb
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL               0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL              0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK                     0x400
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT                       0xa
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_ENABLE_FVAL                0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_DISABLE_FVAL               0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_BMSK                          0x200
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_SHFT                            0x9
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_BMSK                          0x100
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_SHFT                            0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_BMSK                           0x80
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_SHFT                            0x7
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_BMSK                           0x40
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_SHFT                            0x6
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_ENABLE_FVAL                     0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_DISABLE_FVAL                    0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_BMSK                          0x20
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_SHFT                           0x5
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_BMSK                          0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_SHFT                           0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK                        0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT                        0x3
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL                 0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL                0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK                         0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT                         0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_ENABLE_FVAL                  0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_DISABLE_FVAL                 0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_BMSK                                     0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_SHFT                                     0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_ENABLE_FVAL                              0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_DISABLE_FVAL                             0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_BMSK                                         0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_SHFT                                         0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_ENABLE_FVAL                                  0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_DISABLE_FVAL                                 0x1

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000420c)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000420c)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_BMSK                         0xff000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_SHFT                               0x18
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_APSS_KRYO_PP_DISABLE_BMSK                           0x800000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_APSS_KRYO_PP_DISABLE_SHFT                               0x17
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_BMSK                            0x400000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_SHFT                                0x16
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_BMSK                       0x200000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_SHFT                           0x15
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_BMSK                             0x1f8000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_SHFT                                  0xf
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_BMSK                           0x4000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_SHFT                              0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_BMSK                          0x3fc0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_SHFT                             0x6
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_BMSK                     0x20
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_SHFT                      0x5
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_BMSK                     0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_SHFT                      0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_BMSK                      0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_SHFT                      0x3
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_BMSK                      0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_SHFT                      0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_BMSK                      0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_SHFT                      0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_BMSK                      0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_SHFT                      0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004210)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004210)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_RMSK                                              0x7fffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_SYS_CFG_GOLDPLUS_PLL_LVAL_BMSK                    0x7f800000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_SYS_CFG_GOLDPLUS_PLL_LVAL_SHFT                          0x17
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_6_BMSK                         0x400000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_6_SHFT                             0x16
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_5_BMSK                         0x200000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_5_SHFT                             0x15
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_4_BMSK                         0x100000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_4_SHFT                             0x14
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_3_BMSK                          0x80000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_3_SHFT                             0x13
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_2_BMSK                          0x40000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_2_SHFT                             0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_1_BMSK                          0x20000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_1_SHFT                             0x11
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_0_BMSK                          0x10000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_0_SHFT                             0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_BMSK                            0xffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_SHFT                               0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004214)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004214)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_RSVD_BMSK                                         0xfffffffe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_RSVD_SHFT                                                0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_DISABLE_SEC_BOOT_GPIO_BMSK                               0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_DISABLE_SEC_BOOT_GPIO_SHFT                               0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004218)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004218)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_RSVD_BMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_RSVD_SHFT                                                0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000421c)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000421c)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_RSVD_BMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_RSVD_SHFT                                                0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004220)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004220)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_RSVD_BMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_RSVD_SHFT                                                0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004224)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004224)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_RSVD_BMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_RSVD_SHFT                                                0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004228)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004228)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_TAP_GEN_SPARE_INSTR_DISABLE_13_0_BMSK             0xfffc0000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_TAP_GEN_SPARE_INSTR_DISABLE_13_0_SHFT                   0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_TAP_INSTR_DISABLE_BMSK                               0x3ffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_TAP_INSTR_DISABLE_SHFT                                   0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000422c)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000422c)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_SEC_TAP_ACCESS_DISABLE_BMSK                       0xfffc0000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_SEC_TAP_ACCESS_DISABLE_SHFT                             0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_TAP_GEN_SPARE_INSTR_DISABLE_31_14_BMSK               0x3ffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_TAP_GEN_SPARE_INSTR_DISABLE_31_14_SHFT                   0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004230)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004230)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_MODEM_PBL_PATCH_VERSION_BMSK                      0xfe000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_MODEM_PBL_PATCH_VERSION_SHFT                            0x19
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_APPS_PBL_PATCH_VERSION_BMSK                        0x1fc0000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_APPS_PBL_PATCH_VERSION_SHFT                             0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_APPS_PBL_BOOT_SPEED_BMSK                             0x30000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_APPS_PBL_BOOT_SPEED_SHFT                                0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_APPS_PBL_BOOT_SPEED_ENUM_600_MHZ_FVAL                    0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_APPS_PBL_BOOT_SPEED_XO_FVAL                              0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_APPS_PBL_BOOT_SPEED_ENUM_1200_MHZ_FVAL                   0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_APPS_PBL_BOOT_SPEED_NA_FVAL                              0x3
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_MODEM_PBL_BOOT_BMSK                                   0x8000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_MODEM_PBL_BOOT_SHFT                                      0xf
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_RSVD1_56_14_BMSK                                      0x4000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_RSVD1_56_14_SHFT                                         0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_APPS_BOOT_FROM_ROM_BMSK                               0x2000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_APPS_BOOT_FROM_ROM_SHFT                                  0xd
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_ENABLE_DEVICE_IN_TEST_MODE_BMSK                       0x1000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_ENABLE_DEVICE_IN_TEST_MODE_SHFT                          0xc
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_QTI_ROOT_SIG_FORMAT_SEL_BMSK                           0x800
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_QTI_ROOT_SIG_FORMAT_SEL_SHFT                             0xb
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_CE_BAM_DISABLE_BMSK                                    0x400
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_CE_BAM_DISABLE_SHFT                                      0xa
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_CE_BAM_DISABLE_ENABLE_FVAL                               0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_CE_BAM_DISABLE_DISABLE_FVAL                              0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_BMSK                0x200
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_SHFT                  0x9
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_ARM_CE_DISABLE_USAGE_BMSK                              0x100
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_ARM_CE_DISABLE_USAGE_SHFT                                0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_BOOT_ROM_CFG_BMSK                                       0xff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_BOOT_ROM_CFG_SHFT                                        0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004234)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004234)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_APPS_BOOT_TRIGGER_DISABLE_BMSK                    0x80000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_APPS_BOOT_TRIGGER_DISABLE_SHFT                          0x1f
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_APPS_BOOT_TRIGGER_DISABLE_ENABLE_FVAL                    0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_APPS_BOOT_TRIGGER_DISABLE_DISABLE_FVAL                   0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_PBL_QSEE_BOOT_FLOW_DISABLE_BMSK                   0x40000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_PBL_QSEE_BOOT_FLOW_DISABLE_SHFT                         0x1e
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_XBL_SEC_AUTH_DISABLE_BMSK                         0x20000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_XBL_SEC_AUTH_DISABLE_SHFT                               0x1d
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_MSM_PKG_TYPE_BMSK                                 0x10000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_MSM_PKG_TYPE_SHFT                                       0x1c
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_SPSS_CONFIG_MODE_BMSK                              0xc000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_SPSS_CONFIG_MODE_SHFT                                   0x1a
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_PERIPH_DRV_STRENGTH_SETTING_BMSK                   0x3800000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_PERIPH_DRV_STRENGTH_SETTING_SHFT                        0x17
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_RSVD3_56_54_BMSK                                    0x400000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_RSVD3_56_54_SHFT                                        0x16
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_BMSK                                     0x3c0000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_SHFT                                         0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_TSMC_FVAL                                     0x0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_GLOBAL_FOUNDRIES_FVAL                         0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_SAMSUNG_FVAL                                  0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_IBM_FVAL                                      0x3
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_UMC_FVAL                                      0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_SMIC_FVAL                                     0x5
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_PLL_CFG_BMSK                                         0x3fff0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_PLL_CFG_SHFT                                             0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_APPS_PBL_PLL_CTRL_BMSK                                   0xf
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_APPS_PBL_PLL_CTRL_SHFT                                   0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004238)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004238)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_XBL0_BMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_XBL0_SHFT                                                 0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000423c)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000423c)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_XBL1_BMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_XBL1_SHFT                                                 0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004240)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004240)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_PIL_SUBSYSTEM_31_0_BMSK                            0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_PIL_SUBSYSTEM_31_0_SHFT                                   0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004244)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004244)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_XBL_SEC_BMSK                                       0xfe000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_XBL_SEC_SHFT                                             0x19
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_AOP_BMSK                                            0x1fe0000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_AOP_SHFT                                                 0x11
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_TZ_BMSK                                               0x1ffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_TZ_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004248)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004248)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_XBL_CONFIG_1_0_BMSK                                0xc0000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_XBL_CONFIG_1_0_SHFT                                      0x1e
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_TQS_HASH_ACTIVE_BMSK                               0x3e000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_TQS_HASH_ACTIVE_SHFT                                     0x19
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_BMSK                           0x1000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_SHFT                                0x18
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_RPMB_KEY_NOT_PROVISIONED_FVAL        0x0
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_RPMB_KEY_PROVISIONED_FVAL            0x1
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_PIL_SUBSYSTEM_47_32_BMSK                             0xffff00
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_PIL_SUBSYSTEM_47_32_SHFT                                  0x8
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_SAFESWITCH_BMSK                                          0xff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_SAFESWITCH_SHFT                                           0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000424c)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000424c)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_XBL_CONFIG_5_2_BMSK                                0xf0000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_XBL_CONFIG_5_2_SHFT                                      0x1c
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_DEVICE_CFG_BMSK                                     0xffe0000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_DEVICE_CFG_SHFT                                          0x11
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_DEBUG_POLICY_BMSK                                     0x1f000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_DEBUG_POLICY_SHFT                                         0xc
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_HYPERVISOR_BMSK                                         0xfff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_HYPERVISOR_SHFT                                           0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004250)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004250)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_MSS_BMSK                                           0xffff0000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_MSS_SHFT                                                 0x10
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_MISC_BMSK                                              0xffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_MISC_SHFT                                                 0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004254)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004254)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_SIMLOCK_BMSK                                       0x80000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_SIMLOCK_SHFT                                             0x1f
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_RSVD0_BMSK                                         0x7ffffff0
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_RSVD0_SHFT                                                0x4
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ROOT_CERT_PK_HASH_INDEX_BMSK                              0xf
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ROOT_CERT_PK_HASH_INDEX_SHFT                              0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004258)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004258)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_MISC_BMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_MISC_SHFT                                                 0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000425c)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_OFFS                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000425c)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_RSVD0_BMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_RSVD0_SHFT                                                0x0

#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_ADDR(n)                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004260 + 0x8 * (n))
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_OFFS(n)                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004260 + 0x8 * (n))
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_MAXn                                                          5
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_HASH_DATA0_BMSK                                      0xffffffff
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_HASH_DATA0_SHFT                                             0x0

#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_ADDR(n)                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004264 + 0x8 * (n))
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_OFFS(n)                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004264 + 0x8 * (n))
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_MAXn                                                          5
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_HASH_DATA1_BMSK                                      0xffffffff
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_HASH_DATA1_SHFT                                             0x0

#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004290)
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004290)
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW0_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_RSVD2_BMSK                                              0xfe000000
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_RSVD2_SHFT                                                    0x19
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_USB2PHY_RCAL_CODE_BMSK                                   0x1e00000
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_USB2PHY_RCAL_CODE_SHFT                                        0x15
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_RSVD1_BMSK                                                0x1ff000
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_RSVD1_SHFT                                                     0xc
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_TURING_Q6SS1_LDO_VREF_TRIM_BMSK                              0xf80
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_TURING_Q6SS1_LDO_VREF_TRIM_SHFT                                0x7
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_TURING_Q6SS1_LDO_ENABLE_NOM_BMSK                              0x40
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_TURING_Q6SS1_LDO_ENABLE_NOM_SHFT                               0x6
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_RSVD_BMSK                                                     0x3f
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004294)
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004294)
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW0_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004298)
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004298)
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW1_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000429c)
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000429c)
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW1_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_RSVD1_BMSK                                              0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_RSVD1_SHFT                                                    0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_REFGEN_NORTH_BGV_TRIM_BMSK                              0x7f800000
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_REFGEN_NORTH_BGV_TRIM_SHFT                                    0x17
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_REFGEN_SOUTH_BGV_TRIM_BMSK                                0x7f8000
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_REFGEN_SOUTH_BGV_TRIM_SHFT                                     0xf
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_BANDGAP_TRIM_BMSK                                           0x7f00
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_BANDGAP_TRIM_SHFT                                              0x8
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_RSVD_BMSK                                                     0xff
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042a0)
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042a0)
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW2_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_AOSS_K_13_0_BMSK                                        0xfffc0000
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_AOSS_K_13_0_SHFT                                              0x12
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_AOSS_N1_BMSK                                               0x3ffff
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_AOSS_N1_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042a4)
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042a4)
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW2_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_RSVD_BMSK                                               0xff000000
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_RSVD_SHFT                                                     0x18
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_AOSS_DCOPCODE_BMSK                                        0x800000
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_AOSS_DCOPCODE_SHFT                                            0x17
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_AOSS_TDOPCODE_BMSK                                        0x700000
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_AOSS_TDOPCODE_SHFT                                            0x14
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_AOSS_P1_BMSK                                               0xffffc
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_AOSS_P1_SHFT                                                   0x2
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_AOSS_K_15_14_BMSK                                              0x3
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_AOSS_K_15_14_SHFT                                              0x0

#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042a8)
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042a8)
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW3_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_TSENS1_BASE1_1_0_BMSK                                   0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_TSENS1_BASE1_1_0_SHFT                                         0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_TSENS0_BASE1_BMSK                                       0x3ff00000
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_TSENS0_BASE1_SHFT                                             0x14
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_TSENS1_BASE0_BMSK                                          0xffc00
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_TSENS1_BASE0_SHFT                                              0xa
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_TSENS0_BASE0_BMSK                                            0x3ff
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_TSENS0_BASE0_SHFT                                              0x0

#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042ac)
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042ac)
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW3_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_TSENS4_OFFSET_3_0_BMSK                                  0xf0000000
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_TSENS4_OFFSET_3_0_SHFT                                        0x1c
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_TSENS3_OFFSET_BMSK                                       0xf800000
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_TSENS3_OFFSET_SHFT                                            0x17
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_TSENS2_OFFSET_BMSK                                        0x7c0000
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_TSENS2_OFFSET_SHFT                                            0x12
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_TSENS1_OFFSET_BMSK                                         0x3e000
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_TSENS1_OFFSET_SHFT                                             0xd
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_TSENS0_OFFSET_BMSK                                          0x1f00
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_TSENS0_OFFSET_SHFT                                             0x8
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_TSENS1_BASE1_9_2_BMSK                                         0xff
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_TSENS1_BASE1_9_2_SHFT                                          0x0

#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042b0)
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042b0)
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW4_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_TSENS11_OFFSET_0_BMSK                                   0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_TSENS11_OFFSET_0_SHFT                                         0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_TSENS10_OFFSET_BMSK                                     0x7c000000
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_TSENS10_OFFSET_SHFT                                           0x1a
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_TSENS9_OFFSET_BMSK                                       0x3e00000
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_TSENS9_OFFSET_SHFT                                            0x15
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_TSENS8_OFFSET_BMSK                                        0x1f0000
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_TSENS8_OFFSET_SHFT                                            0x10
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_TSENS7_OFFSET_BMSK                                          0xf800
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_TSENS7_OFFSET_SHFT                                             0xb
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_TSENS6_OFFSET_BMSK                                           0x7c0
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_TSENS6_OFFSET_SHFT                                             0x6
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_TSENS5_OFFSET_BMSK                                            0x3e
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_TSENS5_OFFSET_SHFT                                             0x1
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_TSENS4_OFFSET_4_BMSK                                           0x1
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_TSENS4_OFFSET_4_SHFT                                           0x0

#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042b4)
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042b4)
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW4_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_TSENS17_OFFSET_2_0_BMSK                                 0xe0000000
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_TSENS17_OFFSET_2_0_SHFT                                       0x1d
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_TSENS16_OFFSET_BMSK                                     0x1f000000
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_TSENS16_OFFSET_SHFT                                           0x18
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_TSENS15_OFFSET_BMSK                                       0xf80000
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_TSENS15_OFFSET_SHFT                                           0x13
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_TSENS14_OFFSET_BMSK                                        0x7c000
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_TSENS14_OFFSET_SHFT                                            0xe
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_TSENS13_OFFSET_BMSK                                         0x3e00
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_TSENS13_OFFSET_SHFT                                            0x9
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_TSENS12_OFFSET_BMSK                                          0x1f0
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_TSENS12_OFFSET_SHFT                                            0x4
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_TSENS11_OFFSET_4_1_BMSK                                        0xf
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_TSENS11_OFFSET_4_1_SHFT                                        0x0

#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042b8)
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042b8)
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW5_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_TSENS23_OFFSET_BMSK                                     0xf8000000
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_TSENS23_OFFSET_SHFT                                           0x1b
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_TSENS22_OFFSET_BMSK                                      0x7c00000
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_TSENS22_OFFSET_SHFT                                           0x16
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_TSENS21_OFFSET_BMSK                                       0x3e0000
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_TSENS21_OFFSET_SHFT                                           0x11
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_TSENS20_OFFSET_BMSK                                        0x1f000
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_TSENS20_OFFSET_SHFT                                            0xc
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_TSENS19_OFFSET_BMSK                                          0xf80
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_TSENS19_OFFSET_SHFT                                            0x7
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_TSENS18_OFFSET_BMSK                                           0x7c
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_TSENS18_OFFSET_SHFT                                            0x2
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_TSENS17_OFFSET_4_3_BMSK                                        0x3
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_TSENS17_OFFSET_4_3_SHFT                                        0x0

#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042bc)
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042bc)
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW5_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_RSVD_BMSK                                               0xffffff00
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_RSVD_SHFT                                                      0x8
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_TSENS_CAL_SEL_BMSK                                            0xe0
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_TSENS_CAL_SEL_SHFT                                             0x5
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_TSENS24_OFFSET_BMSK                                           0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_TSENS24_OFFSET_SHFT                                            0x0

#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042c0)
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042c0)
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW6_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW6_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_VSENSE_FUSE1_S5_BMSK                                    0xe0000000
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_VSENSE_FUSE1_S5_SHFT                                          0x1d
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_VSENSE_FUSE1_S4_BMSK                                    0x1c000000
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_VSENSE_FUSE1_S4_SHFT                                          0x1a
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_VSENSE_FUSE1_S3_BMSK                                     0x3800000
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_VSENSE_FUSE1_S3_SHFT                                          0x17
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_VSENSE_FUSE1_S2_BMSK                                      0x700000
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_VSENSE_FUSE1_S2_SHFT                                          0x14
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_VSENSE_FUSE1_S1_BMSK                                       0xe0000
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_VSENSE_FUSE1_S1_SHFT                                          0x11
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_VSENSE_FUSE1_S0_BMSK                                       0x1c000
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_VSENSE_FUSE1_S0_SHFT                                           0xe
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_VSENSE_FUSE2_BMSK                                           0x3f00
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_VSENSE_FUSE2_SHFT                                              0x8
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_VSENSE_FUSE1_BMSK                                             0xff
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_VSENSE_FUSE1_SHFT                                              0x0

#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042c4)
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042c4)
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW6_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW6_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE2_S6_BMSK                                    0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE2_S6_SHFT                                          0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE2_S5_BMSK                                    0x30000000
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE2_S5_SHFT                                          0x1c
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE2_S4_BMSK                                     0xc000000
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE2_S4_SHFT                                          0x1a
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE2_S3_BMSK                                     0x3000000
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE2_S3_SHFT                                          0x18
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE2_S2_BMSK                                      0xc00000
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE2_S2_SHFT                                          0x16
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE2_S1_BMSK                                      0x300000
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE2_S1_SHFT                                          0x14
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE2_S0_BMSK                                       0xc0000
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE2_S0_SHFT                                          0x12
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_RSVD_BMSK                                                  0x3f000
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_RSVD_SHFT                                                      0xc
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE1_S9_BMSK                                         0xe00
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE1_S9_SHFT                                           0x9
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE1_S8_BMSK                                         0x1c0
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE1_S8_SHFT                                           0x6
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE1_S7_BMSK                                          0x38
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE1_S7_SHFT                                           0x3
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE1_S6_BMSK                                           0x7
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_VSENSE_FUSE1_S6_SHFT                                           0x0

#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042c8)
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042c8)
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW7_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW7_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_RSVD_BMSK                                               0xffffffc0
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_RSVD_SHFT                                                      0x6
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_VSENSE_FUSE2_S9_BMSK                                          0x30
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_VSENSE_FUSE2_S9_SHFT                                           0x4
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_VSENSE_FUSE2_S8_BMSK                                           0xc
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_VSENSE_FUSE2_S8_SHFT                                           0x2
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_VSENSE_FUSE2_S7_BMSK                                           0x3
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_VSENSE_FUSE2_S7_SHFT                                           0x0

#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042cc)
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042cc)
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW7_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW7_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042d0)
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042d0)
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW8_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW8_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042d4)
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042d4)
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW8_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW8_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042d8)
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042d8)
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW9_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW9_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042dc)
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042dc)
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW9_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW9_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042e0)
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042e0)
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW10_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW10_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042e4)
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042e4)
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW10_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW10_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042e8)
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042e8)
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW11_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW11_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042ec)
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042ec)
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW11_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW11_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042f0)
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042f0)
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW12_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW12_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042f4)
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042f4)
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW12_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW12_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042f8)
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042f8)
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW13_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW13_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR_MM_MODE_DISABLE_0_BMSK                             0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR_MM_MODE_DISABLE_0_SHFT                                   0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR_SSC_CX_MODE_DISABLE_BMSK                           0x70000000
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR_SSC_CX_MODE_DISABLE_SHFT                                 0x1c
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR_DDR_MODE_DISABLE_BMSK                               0xe000000
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR_DDR_MODE_DISABLE_SHFT                                    0x19
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR_GFX_MODE_DISABLE_BMSK                               0x1c00000
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR_GFX_MODE_DISABLE_SHFT                                    0x16
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR_CX_MODE_DISABLE_BMSK                                 0x380000
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR_CX_MODE_DISABLE_SHFT                                     0x13
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR_LOCAL_RC_BMSK                                         0x70000
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR_LOCAL_RC_SHFT                                            0x10
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR_GLOBAL_RC_BMSK                                         0xe000
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR_GLOBAL_RC_SHFT                                            0xd
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_AON_AGING_BMSK                                             0x1fe0
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_AON_AGING_SHFT                                                0x5
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_AON_TARG_VOLT_BMSK                                           0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_AON_TARG_VOLT_SHFT                                            0x0

#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042fc)
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042fc)
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW13_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW13_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_RSVD_BMSK                                              0xfffffffc
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_RSVD_SHFT                                                     0x2
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_MM_MODE_DISABLE_2_1_BMSK                                  0x3
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_MM_MODE_DISABLE_2_1_SHFT                                  0x0

#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004300)
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004300)
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW14_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW14_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_CPR0_TARG_VOLT_OFFSET_NOM_BMSK                         0xf0000000
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_CPR0_TARG_VOLT_OFFSET_NOM_SHFT                               0x1c
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_CPR0_TARG_VOLT_OFFSET_TUR_BMSK                          0xf000000
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_CPR0_TARG_VOLT_OFFSET_TUR_SHFT                               0x18
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_CPR0_TARG_VOLT_OFFSET_SUT_BMSK                           0xf00000
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_CPR0_TARG_VOLT_OFFSET_SUT_SHFT                               0x14
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_CPR0_TARG_VOLT_SVS3_BMSK                                  0xf8000
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_CPR0_TARG_VOLT_SVS3_SHFT                                      0xf
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_CPR0_TARG_VOLT_SVS_BMSK                                    0x7c00
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_CPR0_TARG_VOLT_SVS_SHFT                                       0xa
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_CPR0_TARG_VOLT_NOM_BMSK                                     0x3e0
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_CPR0_TARG_VOLT_NOM_SHFT                                       0x5
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_CPR0_TARG_VOLT_SUT_BMSK                                      0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_CPR0_TARG_VOLT_SUT_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004304)
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004304)
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW14_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW14_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_RSVD_BMSK                                              0xfff00000
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_RSVD_SHFT                                                    0x14
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_CPR0_AGING_BMSK                                           0xff000
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_CPR0_AGING_SHFT                                               0xc
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_CPR0_TARG_VOLT_OFFSET_SVS3_BMSK                             0xf00
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_CPR0_TARG_VOLT_OFFSET_SVS3_SHFT                               0x8
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_CPR0_TARG_VOLT_OFFSET_SVS2_BMSK                              0xf0
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_CPR0_TARG_VOLT_OFFSET_SVS2_SHFT                               0x4
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_CPR0_TARG_VOLT_OFFSET_SVS_BMSK                                0xf
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_CPR0_TARG_VOLT_OFFSET_SVS_SHFT                                0x0

#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004308)
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004308)
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW15_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW15_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_CPR1_TARG_VOLT_OFFSET_NOM_BMSK                         0xf0000000
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_CPR1_TARG_VOLT_OFFSET_NOM_SHFT                               0x1c
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_CPR1_TARG_VOLT_OFFSET_TUR_BMSK                          0xf000000
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_CPR1_TARG_VOLT_OFFSET_TUR_SHFT                               0x18
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_CPR1_TARG_VOLT_OFFSET_SUT_BMSK                           0xf00000
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_CPR1_TARG_VOLT_OFFSET_SUT_SHFT                               0x14
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_CPR1_TARG_VOLT_SVS3_BMSK                                  0xf8000
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_CPR1_TARG_VOLT_SVS3_SHFT                                      0xf
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_CPR1_TARG_VOLT_SVS_BMSK                                    0x7c00
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_CPR1_TARG_VOLT_SVS_SHFT                                       0xa
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_CPR1_TARG_VOLT_NOM_BMSK                                     0x3e0
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_CPR1_TARG_VOLT_NOM_SHFT                                       0x5
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_CPR1_TARG_VOLT_SUT_BMSK                                      0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_CPR1_TARG_VOLT_SUT_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000430c)
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000430c)
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW15_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW15_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_RSVD_BMSK                                              0xfff00000
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_RSVD_SHFT                                                    0x14
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_CPR1_AGING_BMSK                                           0xff000
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_CPR1_AGING_SHFT                                               0xc
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_CPR1_TARG_VOLT_OFFSET_SVS3_BMSK                             0xf00
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_CPR1_TARG_VOLT_OFFSET_SVS3_SHFT                               0x8
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_CPR1_TARG_VOLT_OFFSET_SVS2_BMSK                              0xf0
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_CPR1_TARG_VOLT_OFFSET_SVS2_SHFT                               0x4
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_CPR1_TARG_VOLT_OFFSET_SVS_BMSK                                0xf
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_CPR1_TARG_VOLT_OFFSET_SVS_SHFT                                0x0

#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004310)
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004310)
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW16_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW16_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_CPR3_TARG_VOLT_NOM_1_0_BMSK                            0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_CPR3_TARG_VOLT_NOM_1_0_SHFT                                  0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_CPR3_TARG_VOLT_TUR_BMSK                                0x3e000000
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_CPR3_TARG_VOLT_TUR_SHFT                                      0x19
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_CPR3_TARG_VOLT_SUT_BMSK                                 0x1f00000
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_CPR3_TARG_VOLT_SUT_SHFT                                      0x14
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_CPR2_TARG_VOLT_SVS3_BMSK                                  0xf8000
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_CPR2_TARG_VOLT_SVS3_SHFT                                      0xf
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_CPR2_TARG_VOLT_SVS_BMSK                                    0x7c00
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_CPR2_TARG_VOLT_SVS_SHFT                                       0xa
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_CPR2_TARG_VOLT_NOM_BMSK                                     0x3e0
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_CPR2_TARG_VOLT_NOM_SHFT                                       0x5
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_CPR2_TARG_VOLT_TUR_BMSK                                      0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_CPR2_TARG_VOLT_TUR_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004314)
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004314)
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW16_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW16_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_RSVD_BMSK                                              0xff000000
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_RSVD_SHFT                                                    0x18
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_CPR3_TARG_VOLT_OFFSET_SVSP_BMSK                          0xf00000
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_CPR3_TARG_VOLT_OFFSET_SVSP_SHFT                              0x14
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_CPR3_TARG_VOLT_OFFSET_NOM_BMSK                            0xf0000
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_CPR3_TARG_VOLT_OFFSET_NOM_SHFT                               0x10
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_CPR3_TARG_VOLT_OFFSET_TUR_BMSK                             0xf000
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_CPR3_TARG_VOLT_OFFSET_TUR_SHFT                                0xc
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_CPR3_TARG_VOLT_OFFSET_SUT_BMSK                              0xf00
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_CPR3_TARG_VOLT_OFFSET_SUT_SHFT                                0x8
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_CPR3_TARG_VOLT_SVSP_BMSK                                     0xf8
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_CPR3_TARG_VOLT_SVSP_SHFT                                      0x3
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_CPR3_TARG_VOLT_NOM_4_2_BMSK                                   0x7
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_CPR3_TARG_VOLT_NOM_4_2_SHFT                                   0x0

#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004318)
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004318)
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW17_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW17_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_CPR5_TARG_VOLT_OFFSET_TUR_1_0_BMSK                     0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_CPR5_TARG_VOLT_OFFSET_TUR_1_0_SHFT                           0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_CPR5_TARG_VOLT_SVS3_BMSK                               0x3e000000
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_CPR5_TARG_VOLT_SVS3_SHFT                                     0x19
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_CPR5_TARG_VOLT_SVS_BMSK                                 0x1f00000
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_CPR5_TARG_VOLT_SVS_SHFT                                      0x14
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_CPR5_TARG_VOLT_NOM_BMSK                                   0xf8000
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_CPR5_TARG_VOLT_NOM_SHFT                                       0xf
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_CPR5_TARG_VOLT_TUR_BMSK                                    0x7c00
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_CPR5_TARG_VOLT_TUR_SHFT                                       0xa
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_CPR4_TARG_VOLT_NOM_BMSK                                     0x3e0
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_CPR4_TARG_VOLT_NOM_SHFT                                       0x5
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_CPR4_TARG_VOLT_TUR_BMSK                                      0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_CPR4_TARG_VOLT_TUR_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000431c)
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000431c)
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW17_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW17_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_RSVD_BMSK                                              0xfc000000
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_RSVD_SHFT                                                    0x1a
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_CPR5_AGING_BMSK                                         0x3fc0000
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_CPR5_AGING_SHFT                                              0x12
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_SVS3_BMSK                           0x3c000
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_SVS3_SHFT                               0xe
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_SVS2_BMSK                            0x3c00
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_SVS2_SHFT                               0xa
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_SVS_BMSK                              0x3c0
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_SVS_SHFT                                0x6
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_NOM_BMSK                               0x3c
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_NOM_SHFT                                0x2
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_TUR_3_2_BMSK                            0x3
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_CPR5_TARG_VOLT_OFFSET_TUR_3_2_SHFT                            0x0

#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004320)
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004320)
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW18_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW18_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_CPR6_TARG_VOLT_OFFSET_SVSP_BMSK                        0xf0000000
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_CPR6_TARG_VOLT_OFFSET_SVSP_SHFT                              0x1c
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_CPR6_TARG_VOLT_OFFSET_NOM_BMSK                          0xf000000
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_CPR6_TARG_VOLT_OFFSET_NOM_SHFT                               0x18
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_CPR6_TARG_VOLT_OFFSET_TUR_BMSK                           0xf00000
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_CPR6_TARG_VOLT_OFFSET_TUR_SHFT                               0x14
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_CPR6_TARG_VOLT_SVS2_BMSK                                  0xf8000
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_CPR6_TARG_VOLT_SVS2_SHFT                                      0xf
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_CPR6_TARG_VOLT_SVS_BMSK                                    0x7c00
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_CPR6_TARG_VOLT_SVS_SHFT                                       0xa
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_CPR6_TARG_VOLT_NOM_BMSK                                     0x3e0
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_CPR6_TARG_VOLT_NOM_SHFT                                       0x5
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_CPR6_TARG_VOLT_TUR_BMSK                                      0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_CPR6_TARG_VOLT_TUR_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004324)
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004324)
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW18_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW18_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_RSVD_BMSK                                              0xffff0000
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_RSVD_SHFT                                                    0x10
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_CPR6_AGING_BMSK                                            0xff00
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_CPR6_AGING_SHFT                                               0x8
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_CPR6_TARG_VOLT_OFFSET_SVS2_BMSK                              0xf0
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_CPR6_TARG_VOLT_OFFSET_SVS2_SHFT                               0x4
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_CPR6_TARG_VOLT_OFFSET_SVS_BMSK                                0xf
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_CPR6_TARG_VOLT_OFFSET_SVS_SHFT                                0x0

#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004328)
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004328)
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW19_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW19_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_CPR7_TARG_VOLT_SVS_3_0_BMSK                            0xf0000000
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_CPR7_TARG_VOLT_SVS_3_0_SHFT                                  0x1c
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_CPR7_TARG_VOLT_NOM_BMSK                                 0xfc00000
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_CPR7_TARG_VOLT_NOM_SHFT                                      0x16
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_CPR7_TARG_VOLT_TUR_BMSK                                  0x3f0000
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_CPR7_TARG_VOLT_TUR_SHFT                                      0x10
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_CPR7_SVS2_ROSEL_BMSK                                       0xf000
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_CPR7_SVS2_ROSEL_SHFT                                          0xc
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_CPR7_SVS_ROSEL_BMSK                                         0xf00
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_CPR7_SVS_ROSEL_SHFT                                           0x8
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_CPR7_NOMINAL_ROSEL_BMSK                                      0xf0
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_CPR7_NOMINAL_ROSEL_SHFT                                       0x4
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_CPR7_TURBO_ROSEL_BMSK                                         0xf
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_CPR7_TURBO_ROSEL_SHFT                                         0x0

#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000432c)
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000432c)
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW19_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW19_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_CPR7_NOMINAL_QUOT_VMIN_BMSK                            0xfff00000
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_CPR7_NOMINAL_QUOT_VMIN_SHFT                                  0x14
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_CPR7_TURBO_QUOT_VMIN_BMSK                                 0xfff00
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_CPR7_TURBO_QUOT_VMIN_SHFT                                     0x8
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_CPR7_TARG_VOLT_SVS2_BMSK                                     0xfc
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_CPR7_TARG_VOLT_SVS2_SHFT                                      0x2
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_CPR7_TARG_VOLT_SVS_5_4_BMSK                                   0x3
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_CPR7_TARG_VOLT_SVS_5_4_SHFT                                   0x0

#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004330)
#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004330)
#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW20_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW20_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_CPR7_QUOT_OFFSET_TUR_BMSK                              0xff000000
#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_CPR7_QUOT_OFFSET_TUR_SHFT                                    0x18
#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_CPR7_SVS2_QUOT_VMIN_BMSK                                 0xfff000
#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_CPR7_SVS2_QUOT_VMIN_SHFT                                      0xc
#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_CPR7_SVS_QUOT_VMIN_BMSK                                     0xfff
#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_CPR7_SVS_QUOT_VMIN_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004334)
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004334)
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW20_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW20_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_RSVD_BMSK                                              0xffc00000
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_RSVD_SHFT                                                    0x16
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_CPR7_AGING_BMSK                                          0x3fc000
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_CPR7_AGING_SHFT                                               0xe
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_CPR7_QUOT_OFFSET_SVS_BMSK                                  0x3f80
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_CPR7_QUOT_OFFSET_SVS_SHFT                                     0x7
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_CPR7_QUOT_OFFSET_NOM_BMSK                                    0x7f
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_CPR7_QUOT_OFFSET_NOM_SHFT                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004338)
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004338)
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW21_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW21_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_CPR8_TURBO_QUOT_VMIN_7_0_BMSK                          0xff000000
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_CPR8_TURBO_QUOT_VMIN_7_0_SHFT                                0x18
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_CPR8_TARG_VOLT_SVS2_BMSK                                 0xfc0000
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_CPR8_TARG_VOLT_SVS2_SHFT                                     0x12
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_CPR8_TARG_VOLT_SVS_BMSK                                   0x3f000
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_CPR8_TARG_VOLT_SVS_SHFT                                       0xc
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_CPR8_TARG_VOLT_NOM_BMSK                                     0xfc0
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_CPR8_TARG_VOLT_NOM_SHFT                                       0x6
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_CPR8_TARG_VOLT_TUR_BMSK                                      0x3f
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_CPR8_TARG_VOLT_TUR_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000433c)
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000433c)
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW21_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW21_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_CPR8_SVS2_QUOT_VMIN_3_0_BMSK                           0xf0000000
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_CPR8_SVS2_QUOT_VMIN_3_0_SHFT                                 0x1c
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_CPR8_SVS_QUOT_VMIN_BMSK                                 0xfff0000
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_CPR8_SVS_QUOT_VMIN_SHFT                                      0x10
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_CPR8_NOMINAL_QUOT_VMIN_BMSK                                0xfff0
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_CPR8_NOMINAL_QUOT_VMIN_SHFT                                   0x4
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_CPR8_TURBO_QUOT_VMIN_11_8_BMSK                                0xf
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_CPR8_TURBO_QUOT_VMIN_11_8_SHFT                                0x0

#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004340)
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004340)
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW22_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW22_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_CPR9_TURBO_ROSEL_1_0_BMSK                              0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_CPR9_TURBO_ROSEL_1_0_SHFT                                    0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_CPR8_QUOT_OFFSET_SVS_BMSK                              0x3f800000
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_CPR8_QUOT_OFFSET_SVS_SHFT                                    0x17
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_CPR8_QUOT_OFFSET_NOM_BMSK                                0x7f0000
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_CPR8_QUOT_OFFSET_NOM_SHFT                                    0x10
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_CPR8_QUOT_OFFSET_TUR_BMSK                                  0xff00
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_CPR8_QUOT_OFFSET_TUR_SHFT                                     0x8
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_CPR8_SVS2_QUOT_VMIN_11_4_BMSK                                0xff
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_CPR8_SVS2_QUOT_VMIN_11_4_SHFT                                 0x0

#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004344)
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004344)
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW22_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW22_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_CPR9_TARG_VOLT_SVS_BMSK                                0xfc000000
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_CPR9_TARG_VOLT_SVS_SHFT                                      0x1a
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_CPR9_TARG_VOLT_NOM_BMSK                                 0x3f00000
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_CPR9_TARG_VOLT_NOM_SHFT                                      0x14
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_CPR9_TARG_VOLT_TUR_BMSK                                   0xfc000
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_CPR9_TARG_VOLT_TUR_SHFT                                       0xe
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_CPR9_SVS2_ROSEL_BMSK                                       0x3c00
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_CPR9_SVS2_ROSEL_SHFT                                          0xa
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_CPR9_SVS_ROSEL_BMSK                                         0x3c0
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_CPR9_SVS_ROSEL_SHFT                                           0x6
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_CPR9_NOMINAL_ROSEL_BMSK                                      0x3c
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_CPR9_NOMINAL_ROSEL_SHFT                                       0x2
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_CPR9_TURBO_ROSEL_3_2_BMSK                                     0x3
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_CPR9_TURBO_ROSEL_3_2_SHFT                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004348)
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004348)
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW23_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW23_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_CPR9_SVS_QUOT_VMIN_1_0_BMSK                            0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_CPR9_SVS_QUOT_VMIN_1_0_SHFT                                  0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_CPR9_NOMINAL_QUOT_VMIN_BMSK                            0x3ffc0000
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_CPR9_NOMINAL_QUOT_VMIN_SHFT                                  0x12
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_CPR9_TURBO_QUOT_VMIN_BMSK                                 0x3ffc0
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_CPR9_TURBO_QUOT_VMIN_SHFT                                     0x6
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_CPR9_TARG_VOLT_SVS2_BMSK                                     0x3f
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_CPR9_TARG_VOLT_SVS2_SHFT                                      0x0

#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000434c)
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000434c)
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW23_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW23_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_CPR9_QUOT_OFFSET_NOM_1_0_BMSK                          0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_CPR9_QUOT_OFFSET_NOM_1_0_SHFT                                0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_CPR9_QUOT_OFFSET_TUR_BMSK                              0x3fc00000
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_CPR9_QUOT_OFFSET_TUR_SHFT                                    0x16
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_CPR9_SVS2_QUOT_VMIN_BMSK                                 0x3ffc00
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_CPR9_SVS2_QUOT_VMIN_SHFT                                      0xa
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_CPR9_SVS_QUOT_VMIN_11_2_BMSK                                0x3ff
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_CPR9_SVS_QUOT_VMIN_11_2_SHFT                                  0x0

#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004350)
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004350)
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW24_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW24_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_CPR10_TARG_VOLT_NOM_BMSK                               0xfc000000
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_CPR10_TARG_VOLT_NOM_SHFT                                     0x1a
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_CPR10_TARG_VOLT_TUR_BMSK                                0x3f00000
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_CPR10_TARG_VOLT_TUR_SHFT                                     0x14
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_CPR9_AGING_BMSK                                           0xff000
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_CPR9_AGING_SHFT                                               0xc
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_CPR9_QUOT_OFFSET_SVS_BMSK                                   0xfe0
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_CPR9_QUOT_OFFSET_SVS_SHFT                                     0x5
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_CPR9_QUOT_OFFSET_NOM_6_2_BMSK                                0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_CPR9_QUOT_OFFSET_NOM_6_2_SHFT                                 0x0

#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004354)
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004354)
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW24_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW24_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_CPR10_NOMINAL_QUOT_VMIN_7_0_BMSK                       0xff000000
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_CPR10_NOMINAL_QUOT_VMIN_7_0_SHFT                             0x18
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_CPR10_TURBO_QUOT_VMIN_BMSK                               0xfff000
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_CPR10_TURBO_QUOT_VMIN_SHFT                                    0xc
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_CPR10_TARG_VOLT_SVS2_BMSK                                   0xfc0
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_CPR10_TARG_VOLT_SVS2_SHFT                                     0x6
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_CPR10_TARG_VOLT_SVS_BMSK                                     0x3f
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_CPR10_TARG_VOLT_SVS_SHFT                                      0x0

#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004358)
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004358)
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW25_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW25_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_CPR10_QUOT_OFFSET_TUR_3_0_BMSK                         0xf0000000
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_CPR10_QUOT_OFFSET_TUR_3_0_SHFT                               0x1c
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_CPR10_SVS2_QUOT_VMIN_BMSK                               0xfff0000
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_CPR10_SVS2_QUOT_VMIN_SHFT                                    0x10
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_CPR10_SVS_QUOT_VMIN_BMSK                                   0xfff0
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_CPR10_SVS_QUOT_VMIN_SHFT                                      0x4
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_CPR10_NOMINAL_QUOT_VMIN_11_8_BMSK                             0xf
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_CPR10_NOMINAL_QUOT_VMIN_11_8_SHFT                             0x0

#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000435c)
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000435c)
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW25_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW25_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_RSVD_BMSK                                              0xfffc0000
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_RSVD_SHFT                                                    0x12
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_CPR10_QUOT_OFFSET_SVS_BMSK                                0x3f800
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_CPR10_QUOT_OFFSET_SVS_SHFT                                    0xb
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_CPR10_QUOT_OFFSET_NOM_BMSK                                  0x7f0
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_CPR10_QUOT_OFFSET_NOM_SHFT                                    0x4
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_CPR10_QUOT_OFFSET_TUR_7_4_BMSK                                0xf
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_CPR10_QUOT_OFFSET_TUR_7_4_SHFT                                0x0

#define HWIO_QFPROM_CORR_CALIB_ROW26_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004360)
#define HWIO_QFPROM_CORR_CALIB_ROW26_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004360)
#define HWIO_QFPROM_CORR_CALIB_ROW26_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW26_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW26_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW26_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW26_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW26_LSB_CPR_RSVD_31_0_BMSK                                     0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW26_LSB_CPR_RSVD_31_0_SHFT                                            0x0

#define HWIO_QFPROM_CORR_CALIB_ROW26_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004364)
#define HWIO_QFPROM_CORR_CALIB_ROW26_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004364)
#define HWIO_QFPROM_CORR_CALIB_ROW26_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW26_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW26_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW26_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW26_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW26_MSB_RSVD_BMSK                                              0xfffc0000
#define HWIO_QFPROM_CORR_CALIB_ROW26_MSB_RSVD_SHFT                                                    0x12
#define HWIO_QFPROM_CORR_CALIB_ROW26_MSB_CPR_RSVD_49_32_BMSK                                       0x3ffff
#define HWIO_QFPROM_CORR_CALIB_ROW26_MSB_CPR_RSVD_49_32_SHFT                                           0x0

#define HWIO_QFPROM_CORR_CALIB_ROW27_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004368)
#define HWIO_QFPROM_CORR_CALIB_ROW27_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004368)
#define HWIO_QFPROM_CORR_CALIB_ROW27_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW27_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW27_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW27_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW27_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW27_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW27_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW27_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000436c)
#define HWIO_QFPROM_CORR_CALIB_ROW27_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000436c)
#define HWIO_QFPROM_CORR_CALIB_ROW27_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW27_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW27_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW27_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW27_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW27_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW27_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW28_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004370)
#define HWIO_QFPROM_CORR_CALIB_ROW28_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004370)
#define HWIO_QFPROM_CORR_CALIB_ROW28_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW28_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW28_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW28_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW28_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW28_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW28_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW28_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004374)
#define HWIO_QFPROM_CORR_CALIB_ROW28_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004374)
#define HWIO_QFPROM_CORR_CALIB_ROW28_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW28_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW28_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW28_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW28_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW28_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW28_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW29_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004378)
#define HWIO_QFPROM_CORR_CALIB_ROW29_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004378)
#define HWIO_QFPROM_CORR_CALIB_ROW29_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW29_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW29_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW29_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW29_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW29_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW29_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW29_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000437c)
#define HWIO_QFPROM_CORR_CALIB_ROW29_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000437c)
#define HWIO_QFPROM_CORR_CALIB_ROW29_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW29_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW29_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW29_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW29_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW29_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW29_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW30_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004380)
#define HWIO_QFPROM_CORR_CALIB_ROW30_LSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004380)
#define HWIO_QFPROM_CORR_CALIB_ROW30_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW30_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW30_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW30_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW30_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW30_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW30_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW30_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004384)
#define HWIO_QFPROM_CORR_CALIB_ROW30_MSB_OFFS                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004384)
#define HWIO_QFPROM_CORR_CALIB_ROW30_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW30_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW30_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW30_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW30_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW30_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW30_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_ADDR(n)                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004388 + 0x8 * (n))
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_OFFS(n)                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004388 + 0x8 * (n))
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_MAXn                                                       70
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_REDUN_DATA_BMSK                                    0xffffffff
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_REDUN_DATA_SHFT                                           0x0

#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_ADDR(n)                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000438c + 0x8 * (n))
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_OFFS(n)                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000438c + 0x8 * (n))
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_MAXn                                                       70
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_REDUN_DATA_BMSK                                    0xffffffff
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_REDUN_DATA_SHFT                                           0x0

#define HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045c0)
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045c0)
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_ADDR)
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_QC_SPARE_BMSK                                       0xffffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_QC_SPARE_SHFT                                              0x0

#define HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045c4)
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045c4)
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_RMSK                                                  0xffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_ADDR)
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_QC_SPARE_BMSK                                         0xffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_QC_SPARE_SHFT                                              0x0

#define HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045c8)
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045c8)
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_ADDR)
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_QC_SPARE_BMSK                                       0xffffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_QC_SPARE_SHFT                                              0x0

#define HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045cc)
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_OFFS                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045cc)
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_RMSK                                                  0xffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_ADDR)
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_QC_SPARE_BMSK                                         0xffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_QC_SPARE_SHFT                                              0x0

#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n)                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045d0 + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_OFFS(n)                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045d0 + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_RMSK                                       0xffffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_MAXn                                                1
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_KEY_DATA0_BMSK                             0xffffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_KEY_DATA0_SHFT                                    0x0

#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n)                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045d4 + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_OFFS(n)                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045d4 + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RMSK                                         0xffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_MAXn                                                1
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_KEY_DATA1_BMSK                               0xffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_KEY_DATA1_SHFT                                    0x0

#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045e0)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_OFFS                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045e0)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RMSK                                       0xffffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RSVD0_BMSK                                 0xffff0000
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RSVD0_SHFT                                       0x10
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_KEY_DATA0_BMSK                                 0xffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_KEY_DATA0_SHFT                                    0x0

#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045e4)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_OFFS                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045e4)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RMSK                                         0xffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD0_BMSK                                   0xffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD0_SHFT                                        0x0

#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_ADDR(n)                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045e8 + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_OFFS(n)                                          (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045e8 + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_MAXn                                                      1
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT4_BMSK                                   0xff000000
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT4_SHFT                                         0x18
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT3_BMSK                                     0xff0000
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT3_SHFT                                         0x10
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT2_BMSK                                       0xff00
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT2_SHFT                                          0x8
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT1_BMSK                                         0xff
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT1_SHFT                                          0x0

#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_ADDR(n)                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045ec + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_OFFS(n)                                          (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045ec + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_RMSK                                               0xffffff
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_MAXn                                                      1
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT7_BMSK                                     0xff0000
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT7_SHFT                                         0x10
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT6_BMSK                                       0xff00
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT6_SHFT                                          0x8
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT5_BMSK                                         0xff
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT5_SHFT                                          0x0

#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n)                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045f8 + 0x8 * (n))
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_OFFS(n)                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045f8 + 0x8 * (n))
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_RMSK                                   0xffffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_MAXn                                            3
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_BMSK                         0xffffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_SHFT                                0x0

#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n)                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045fc + 0x8 * (n))
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_OFFS(n)                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045fc + 0x8 * (n))
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RMSK                                     0xffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_MAXn                                            3
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_BMSK                           0xffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_SHFT                                0x0

#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004618)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_OFFS                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004618)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_RMSK                                   0xffffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_KEY_DATA0_BMSK                         0xffffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_KEY_DATA0_SHFT                                0x0

#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000461c)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_OFFS                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000461c)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RMSK                                     0xffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_BMSK                               0xffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_SHFT                                    0x0

#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_ADDR(n)                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004620 + 0x8 * (n))
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_OFFS(n)                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004620 + 0x8 * (n))
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_MAXn                                                        55
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_PATCH_DATA_BMSK                                     0xffffffff
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_PATCH_DATA_SHFT                                            0x0

#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_ADDR(n)                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004624 + 0x8 * (n))
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_OFFS(n)                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004624 + 0x8 * (n))
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_RMSK                                                  0xffffff
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_MAXn                                                        55
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_RSVD0_BMSK                                            0xfe0000
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_RSVD0_SHFT                                                0x11
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_PATCH_ADDR_BMSK                                        0x1fffe
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_PATCH_ADDR_SHFT                                            0x1
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_PATCH_EN_BMSK                                              0x1
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_PATCH_EN_SHFT                                              0x0

#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n)                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000047e0 + 0x8 * (n))
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_OFFS(n)                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047e0 + 0x8 * (n))
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_MAXn                                                   1
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_KEY_DATA0_BMSK                                0xffffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_KEY_DATA0_SHFT                                       0x0

#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n)                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000047e4 + 0x8 * (n))
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_OFFS(n)                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047e4 + 0x8 * (n))
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_RMSK                                            0xffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_MAXn                                                   1
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_KEY_DATA1_BMSK                                  0xffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_KEY_DATA1_SHFT                                       0x0

#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x000047f0)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_OFFS                                          (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047f0)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_RSVD0_BMSK                                    0xffff0000
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_RSVD0_SHFT                                          0x10
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_KEY_DATA0_BMSK                                    0xffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_KEY_DATA0_SHFT                                       0x0

#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x000047f4)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_OFFS                                          (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047f4)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_RMSK                                            0xffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD0_BMSK                                      0xffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD0_SHFT                                           0x0

#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_ADDR(n)                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x000047f8 + 0x8 * (n))
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_OFFS(n)                                         (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047f8 + 0x8 * (n))
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_MAXn                                                     3
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_USER_DATA_KEY_BMSK                              0xffffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_USER_DATA_KEY_SHFT                                     0x0

#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_ADDR(n)                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x000047fc + 0x8 * (n))
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_OFFS(n)                                         (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047fc + 0x8 * (n))
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_RMSK                                              0xffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_MAXn                                                     3
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_USER_DATA_KEY_BMSK                                0xffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_USER_DATA_KEY_SHFT                                     0x0

#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004818)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_OFFS                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004818)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_ADDR)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_USER_DATA_KEY_BMSK                              0xffffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_USER_DATA_KEY_SHFT                                     0x0

#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000481c)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_OFFS                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000481c)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_RMSK                                              0xffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_ADDR)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_RSVD0_BMSK                                        0xffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_RSVD0_SHFT                                             0x0

#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004660 + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_OFFS(n)                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004660 + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_MAXn                                                   31
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_OEM_SPARE_BMSK                                 0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_OEM_SPARE_SHFT                                        0x0

#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004664 + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_OFFS(n)                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004664 + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_MAXn                                                   31
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_OEM_SPARE_BMSK                                 0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_OEM_SPARE_SHFT                                        0x0

#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004668 + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_OFFS(n)                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004668 + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_MAXn                                                   31
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_OEM_SPARE_BMSK                                 0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_OEM_SPARE_SHFT                                        0x0

#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000466c + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_OFFS(n)                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000466c + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_MAXn                                                   31
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_OEM_SPARE_BMSK                                 0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_OEM_SPARE_SHFT                                        0x0

#define HWIO_SEC_CTRL_HW_VERSION_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006000)
#define HWIO_SEC_CTRL_HW_VERSION_OFFS                                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006000)
#define HWIO_SEC_CTRL_HW_VERSION_RMSK                                                           0xffffffff
#define HWIO_SEC_CTRL_HW_VERSION_IN          \
        in_dword(HWIO_SEC_CTRL_HW_VERSION_ADDR)
#define HWIO_SEC_CTRL_HW_VERSION_INM(m)      \
        in_dword_masked(HWIO_SEC_CTRL_HW_VERSION_ADDR, m)
#define HWIO_SEC_CTRL_HW_VERSION_MAJOR_BMSK                                                     0xf0000000
#define HWIO_SEC_CTRL_HW_VERSION_MAJOR_SHFT                                                           0x1c
#define HWIO_SEC_CTRL_HW_VERSION_MINOR_BMSK                                                      0xfff0000
#define HWIO_SEC_CTRL_HW_VERSION_MINOR_SHFT                                                           0x10
#define HWIO_SEC_CTRL_HW_VERSION_STEP_BMSK                                                          0xffff
#define HWIO_SEC_CTRL_HW_VERSION_STEP_SHFT                                                             0x0

#define HWIO_FEATURE_CONFIG0_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006004)
#define HWIO_FEATURE_CONFIG0_OFFS                                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006004)
#define HWIO_FEATURE_CONFIG0_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG0_IN          \
        in_dword(HWIO_FEATURE_CONFIG0_ADDR)
#define HWIO_FEATURE_CONFIG0_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG0_ADDR, m)
#define HWIO_FEATURE_CONFIG0_RSVD1_BMSK                                                         0x80000000
#define HWIO_FEATURE_CONFIG0_RSVD1_SHFT                                                               0x1f
#define HWIO_FEATURE_CONFIG0_TURING_Q6SS_HVX_DISABLE_BMSK                                       0x40000000
#define HWIO_FEATURE_CONFIG0_TURING_Q6SS_HVX_DISABLE_SHFT                                             0x1e
#define HWIO_FEATURE_CONFIG0_TURING_Q6SS_HVX_DISABLE_ENABLE_FVAL                                       0x0
#define HWIO_FEATURE_CONFIG0_TURING_Q6SS_HVX_DISABLE_DISABLE_FVAL                                      0x1
#define HWIO_FEATURE_CONFIG0_QC_SP_DISABLE_BMSK                                                 0x20000000
#define HWIO_FEATURE_CONFIG0_QC_SP_DISABLE_SHFT                                                       0x1d
#define HWIO_FEATURE_CONFIG0_QC_SP_DISABLE_ENABLE_FVAL                                                 0x0
#define HWIO_FEATURE_CONFIG0_QC_SP_DISABLE_DISABLE_FVAL                                                0x1
#define HWIO_FEATURE_CONFIG0_GFX3D_FREQ_LIMIT_VAL_BMSK                                          0x1fe00000
#define HWIO_FEATURE_CONFIG0_GFX3D_FREQ_LIMIT_VAL_SHFT                                                0x15
#define HWIO_FEATURE_CONFIG0_MDSS_RESOLUTION_LIMIT_BMSK                                           0x180000
#define HWIO_FEATURE_CONFIG0_MDSS_RESOLUTION_LIMIT_SHFT                                               0x13
#define HWIO_FEATURE_CONFIG0_MDSS_RESOLUTION_LIMIT_DEFAULT_FVAL                                        0x0
#define HWIO_FEATURE_CONFIG0_MDSS_RESOLUTION_LIMIT_ENUM_1024_FVAL                                      0x1
#define HWIO_FEATURE_CONFIG0_MDSS_RESOLUTION_LIMIT_ENUM_2048_FVAL                                      0x2
#define HWIO_FEATURE_CONFIG0_MDSS_RESOLUTION_LIMIT_ENUM_2560_FVAL                                      0x3
#define HWIO_FEATURE_CONFIG0_IRIS_HEVC_ENCODE_DISABLE_BMSK                                         0x40000
#define HWIO_FEATURE_CONFIG0_IRIS_HEVC_ENCODE_DISABLE_SHFT                                            0x12
#define HWIO_FEATURE_CONFIG0_IRIS_HEVC_ENCODE_DISABLE_ENABLE_FVAL                                      0x0
#define HWIO_FEATURE_CONFIG0_IRIS_HEVC_ENCODE_DISABLE_DISABLE_FVAL                                     0x1
#define HWIO_FEATURE_CONFIG0_IRIS_HEVC_DECODE_DISABLE_BMSK                                         0x20000
#define HWIO_FEATURE_CONFIG0_IRIS_HEVC_DECODE_DISABLE_SHFT                                            0x11
#define HWIO_FEATURE_CONFIG0_IRIS_HEVC_DECODE_DISABLE_ENABLE_FVAL                                      0x0
#define HWIO_FEATURE_CONFIG0_IRIS_HEVC_DECODE_DISABLE_DISABLE_FVAL                                     0x1
#define HWIO_FEATURE_CONFIG0_IRIS_4K_DISABLE_BMSK                                                  0x10000
#define HWIO_FEATURE_CONFIG0_IRIS_4K_DISABLE_SHFT                                                     0x10
#define HWIO_FEATURE_CONFIG0_IRIS_4K_DISABLE_ENABLE_FVAL                                               0x0
#define HWIO_FEATURE_CONFIG0_IRIS_4K_DISABLE_DISABLE_FVAL                                              0x1
#define HWIO_FEATURE_CONFIG0_IRIS_CVP_DISABLE_BMSK                                                  0x8000
#define HWIO_FEATURE_CONFIG0_IRIS_CVP_DISABLE_SHFT                                                     0xf
#define HWIO_FEATURE_CONFIG0_IRIS_CVP_DISABLE_ENABLE_FVAL                                              0x0
#define HWIO_FEATURE_CONFIG0_IRIS_CVP_DISABLE_DISABLE_FVAL                                             0x1
#define HWIO_FEATURE_CONFIG0_IRIS_DISABLE_VPX_BMSK                                                  0x4000
#define HWIO_FEATURE_CONFIG0_IRIS_DISABLE_VPX_SHFT                                                     0xe
#define HWIO_FEATURE_CONFIG0_IRIS_DISABLE_VPX_ENABLE_FVAL                                              0x0
#define HWIO_FEATURE_CONFIG0_IRIS_DISABLE_VPX_DISABLE_FVAL                                             0x1
#define HWIO_FEATURE_CONFIG0_DP_DISABLE_BMSK                                                        0x2000
#define HWIO_FEATURE_CONFIG0_DP_DISABLE_SHFT                                                           0xd
#define HWIO_FEATURE_CONFIG0_DP_DISABLE_ENABLE_FVAL                                                    0x0
#define HWIO_FEATURE_CONFIG0_DP_DISABLE_DISABLE_FVAL                                                   0x1
#define HWIO_FEATURE_CONFIG0_HDCP_DISABLE_BMSK                                                      0x1000
#define HWIO_FEATURE_CONFIG0_HDCP_DISABLE_SHFT                                                         0xc
#define HWIO_FEATURE_CONFIG0_HDCP_DISABLE_ENABLE_FVAL                                                  0x0
#define HWIO_FEATURE_CONFIG0_HDCP_DISABLE_DISABLE_FVAL                                                 0x1
#define HWIO_FEATURE_CONFIG0_MDP_APICAL_LTC_DISABLE_BMSK                                             0x800
#define HWIO_FEATURE_CONFIG0_MDP_APICAL_LTC_DISABLE_SHFT                                               0xb
#define HWIO_FEATURE_CONFIG0_MDP_APICAL_LTC_DISABLE_ENABLE_FVAL                                        0x0
#define HWIO_FEATURE_CONFIG0_MDP_APICAL_LTC_DISABLE_DISABLE_FVAL                                       0x1
#define HWIO_FEATURE_CONFIG0_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK                                     0x400
#define HWIO_FEATURE_CONFIG0_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT                                       0xa
#define HWIO_FEATURE_CONFIG0_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_FEATURE_CONFIG0_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_DISABLE_FVAL                               0x1
#define HWIO_FEATURE_CONFIG0_DSI_1_DISABLE_BMSK                                                      0x200
#define HWIO_FEATURE_CONFIG0_DSI_1_DISABLE_SHFT                                                        0x9
#define HWIO_FEATURE_CONFIG0_DSI_1_DISABLE_ENABLE_FVAL                                                 0x0
#define HWIO_FEATURE_CONFIG0_DSI_1_DISABLE_DISABLE_FVAL                                                0x1
#define HWIO_FEATURE_CONFIG0_DSI_0_DISABLE_BMSK                                                      0x100
#define HWIO_FEATURE_CONFIG0_DSI_0_DISABLE_SHFT                                                        0x8
#define HWIO_FEATURE_CONFIG0_DSI_0_DISABLE_ENABLE_FVAL                                                 0x0
#define HWIO_FEATURE_CONFIG0_DSI_0_DISABLE_DISABLE_FVAL                                                0x1
#define HWIO_FEATURE_CONFIG0_FD_DISABLE_BMSK                                                          0x80
#define HWIO_FEATURE_CONFIG0_FD_DISABLE_SHFT                                                           0x7
#define HWIO_FEATURE_CONFIG0_FD_DISABLE_ENABLE_FVAL                                                    0x0
#define HWIO_FEATURE_CONFIG0_FD_DISABLE_DISABLE_FVAL                                                   0x1
#define HWIO_FEATURE_CONFIG0_CSID_DPCM_14_DISABLE_BMSK                                                0x40
#define HWIO_FEATURE_CONFIG0_CSID_DPCM_14_DISABLE_SHFT                                                 0x6
#define HWIO_FEATURE_CONFIG0_CSID_DPCM_14_DISABLE_ENABLE_FVAL                                          0x0
#define HWIO_FEATURE_CONFIG0_CSID_DPCM_14_DISABLE_DISABLE_FVAL                                         0x1
#define HWIO_FEATURE_CONFIG0_EFUSE_CAM_SBI_ENABLE_IF_BMSK                                             0x20
#define HWIO_FEATURE_CONFIG0_EFUSE_CAM_SBI_ENABLE_IF_SHFT                                              0x5
#define HWIO_FEATURE_CONFIG0_EUD_PORT1_SEL_BMSK                                                       0x10
#define HWIO_FEATURE_CONFIG0_EUD_PORT1_SEL_SHFT                                                        0x4
#define HWIO_FEATURE_CONFIG0_EUD_PORT1_SEL_USB_PORT0_FVAL                                              0x0
#define HWIO_FEATURE_CONFIG0_EUD_PORT1_SEL_USB_PORT1_FVAL                                              0x1
#define HWIO_FEATURE_CONFIG0_EUD_IGNR_CSR_BMSK                                                         0x8
#define HWIO_FEATURE_CONFIG0_EUD_IGNR_CSR_SHFT                                                         0x3
#define HWIO_FEATURE_CONFIG0_BOOT_ROM_PATCH_DISABLE_BMSK                                               0x7
#define HWIO_FEATURE_CONFIG0_BOOT_ROM_PATCH_DISABLE_SHFT                                               0x0
#define HWIO_FEATURE_CONFIG0_BOOT_ROM_PATCH_DISABLE_ENABLE_PATCHING_FVAL                               0x0
#define HWIO_FEATURE_CONFIG0_BOOT_ROM_PATCH_DISABLE_DISABLE_PATCHING_FVAL                              0x1

#define HWIO_FEATURE_CONFIG1_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006008)
#define HWIO_FEATURE_CONFIG1_OFFS                                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006008)
#define HWIO_FEATURE_CONFIG1_RMSK                                                               0xe7fffff7
#define HWIO_FEATURE_CONFIG1_IN          \
        in_dword(HWIO_FEATURE_CONFIG1_ADDR)
#define HWIO_FEATURE_CONFIG1_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG1_ADDR, m)
#define HWIO_FEATURE_CONFIG1_ICE_FORCE_HW_KEY1_BMSK                                             0x80000000
#define HWIO_FEATURE_CONFIG1_ICE_FORCE_HW_KEY1_SHFT                                                   0x1f
#define HWIO_FEATURE_CONFIG1_ICE_FORCE_HW_KEY1_ICE_ENGINE_USES_SW_KEY_FVAL                             0x0
#define HWIO_FEATURE_CONFIG1_ICE_FORCE_HW_KEY1_ICE_ENGINE_USES_HW_KEY_FVAL                             0x1
#define HWIO_FEATURE_CONFIG1_ICE_FORCE_HW_KEY0_BMSK                                             0x40000000
#define HWIO_FEATURE_CONFIG1_ICE_FORCE_HW_KEY0_SHFT                                                   0x1e
#define HWIO_FEATURE_CONFIG1_ICE_FORCE_HW_KEY0_ICE_ENGINE_USES_SW_KEY_FVAL                             0x0
#define HWIO_FEATURE_CONFIG1_ICE_FORCE_HW_KEY0_ICE_ENGINE_USES_HW_KEY_FVAL                             0x1
#define HWIO_FEATURE_CONFIG1_ICE_DISABLE_BMSK                                                   0x20000000
#define HWIO_FEATURE_CONFIG1_ICE_DISABLE_SHFT                                                         0x1d
#define HWIO_FEATURE_CONFIG1_ICE_DISABLE_ENABLE_FVAL                                                   0x0
#define HWIO_FEATURE_CONFIG1_ICE_DISABLE_DISABLE_FVAL                                                  0x1
#define HWIO_FEATURE_CONFIG1_SSC_DISABLE_BMSK                                                    0x4000000
#define HWIO_FEATURE_CONFIG1_SSC_DISABLE_SHFT                                                         0x1a
#define HWIO_FEATURE_CONFIG1_SSC_DISABLE_ENABLE_FVAL                                                   0x0
#define HWIO_FEATURE_CONFIG1_SSC_DISABLE_DISABLE_FVAL                                                  0x1
#define HWIO_FEATURE_CONFIG1_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK                                 0x2000000
#define HWIO_FEATURE_CONFIG1_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT                                      0x19
#define HWIO_FEATURE_CONFIG1_SSC_ISLAND_MODE_Q6_CLK_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_FEATURE_CONFIG1_SSC_ISLAND_MODE_Q6_CLK_DISABLE_DISABLE_FVAL                               0x1
#define HWIO_FEATURE_CONFIG1_SSC_SW_ISLAND_MODE_DISABLE_BMSK                                     0x1000000
#define HWIO_FEATURE_CONFIG1_SSC_SW_ISLAND_MODE_DISABLE_SHFT                                          0x18
#define HWIO_FEATURE_CONFIG1_SSC_SW_ISLAND_MODE_DISABLE_ENABLE_FVAL                                    0x0
#define HWIO_FEATURE_CONFIG1_SSC_SW_ISLAND_MODE_DISABLE_DISABLE_FVAL                                   0x1
#define HWIO_FEATURE_CONFIG1_TCSR_SW_OVERRIDE_SOC_HW_VER_BMSK                                     0x800000
#define HWIO_FEATURE_CONFIG1_TCSR_SW_OVERRIDE_SOC_HW_VER_SHFT                                         0x17
#define HWIO_FEATURE_CONFIG1_APS_RESET_DISABLE_BMSK                                               0x400000
#define HWIO_FEATURE_CONFIG1_APS_RESET_DISABLE_SHFT                                                   0x16
#define HWIO_FEATURE_CONFIG1_IRIS_MULTIPIPE_DISABLE_BMSK                                          0x200000
#define HWIO_FEATURE_CONFIG1_IRIS_MULTIPIPE_DISABLE_SHFT                                              0x15
#define HWIO_FEATURE_CONFIG1_IRIS_MULTIPIPE_DISABLE_ENABLE_FVAL                                        0x0
#define HWIO_FEATURE_CONFIG1_IRIS_MULTIPIPE_DISABLE_DISABLE_FVAL                                       0x1
#define HWIO_FEATURE_CONFIG1_DOLBY_BIT_BMSK                                                       0x100000
#define HWIO_FEATURE_CONFIG1_DOLBY_BIT_SHFT                                                           0x14
#define HWIO_FEATURE_CONFIG1_QC_UDK_DISABLE_BMSK                                                   0x80000
#define HWIO_FEATURE_CONFIG1_QC_UDK_DISABLE_SHFT                                                      0x13
#define HWIO_FEATURE_CONFIG1_QC_UDK_DISABLE_ENABLE_FVAL                                                0x0
#define HWIO_FEATURE_CONFIG1_QC_UDK_DISABLE_DISABLE_FVAL                                               0x1
#define HWIO_FEATURE_CONFIG1_STACKED_MEMORY_ID_BMSK                                                0x7c000
#define HWIO_FEATURE_CONFIG1_STACKED_MEMORY_ID_SHFT                                                    0xe
#define HWIO_FEATURE_CONFIG1_PRNG_TESTMODE_DISABLE_BMSK                                             0x2000
#define HWIO_FEATURE_CONFIG1_PRNG_TESTMODE_DISABLE_SHFT                                                0xd
#define HWIO_FEATURE_CONFIG1_PRNG_TESTMODE_DISABLE_ENABLE_FVAL                                         0x0
#define HWIO_FEATURE_CONFIG1_PRNG_TESTMODE_DISABLE_DISABLE_FVAL                                        0x1
#define HWIO_FEATURE_CONFIG1_MDSS_Q_CONFIG_FUSE_BMSK                                                0x1000
#define HWIO_FEATURE_CONFIG1_MDSS_Q_CONFIG_FUSE_SHFT                                                   0xc
#define HWIO_FEATURE_CONFIG1_MDSS_Q_CONFIG_FUSE_HANA_FEAT_SET_FVAL                                     0x0
#define HWIO_FEATURE_CONFIG1_MDSS_Q_CONFIG_FUSE_HANAQ_FEAT_SET_FVAL                                    0x1
#define HWIO_FEATURE_CONFIG1_MOCHA_PART_BMSK                                                         0x800
#define HWIO_FEATURE_CONFIG1_MOCHA_PART_SHFT                                                           0xb
#define HWIO_FEATURE_CONFIG1_EFUSE_Q6SS_HVX_HALF_BMSK                                                0x400
#define HWIO_FEATURE_CONFIG1_EFUSE_Q6SS_HVX_HALF_SHFT                                                  0xa
#define HWIO_FEATURE_CONFIG1_SMMU_DISABLE_BMSK                                                       0x200
#define HWIO_FEATURE_CONFIG1_SMMU_DISABLE_SHFT                                                         0x9
#define HWIO_FEATURE_CONFIG1_SMMU_DISABLE_ENABLE_FVAL                                                  0x0
#define HWIO_FEATURE_CONFIG1_SMMU_DISABLE_DISABLE_FVAL                                                 0x1
#define HWIO_FEATURE_CONFIG1_VENDOR_LOCK_BMSK                                                        0x1e0
#define HWIO_FEATURE_CONFIG1_VENDOR_LOCK_SHFT                                                          0x5
#define HWIO_FEATURE_CONFIG1_CM_FEAT_CONFIG_DISABLE_BMSK                                              0x10
#define HWIO_FEATURE_CONFIG1_CM_FEAT_CONFIG_DISABLE_SHFT                                               0x4
#define HWIO_FEATURE_CONFIG1_CM_FEAT_CONFIG_DISABLE_ENABLE_FVAL                                        0x0
#define HWIO_FEATURE_CONFIG1_CM_FEAT_CONFIG_DISABLE_DISABLE_FVAL                                       0x1
#define HWIO_FEATURE_CONFIG1_PCIE_2_DISABLE_BMSK                                                       0x4
#define HWIO_FEATURE_CONFIG1_PCIE_2_DISABLE_SHFT                                                       0x2
#define HWIO_FEATURE_CONFIG1_PCIE_2_DISABLE_ENABLE_FVAL                                                0x0
#define HWIO_FEATURE_CONFIG1_PCIE_2_DISABLE_DISABLE_FVAL                                               0x1
#define HWIO_FEATURE_CONFIG1_PCIE_1_DISABLE_BMSK                                                       0x2
#define HWIO_FEATURE_CONFIG1_PCIE_1_DISABLE_SHFT                                                       0x1
#define HWIO_FEATURE_CONFIG1_PCIE_1_DISABLE_ENABLE_FVAL                                                0x0
#define HWIO_FEATURE_CONFIG1_PCIE_1_DISABLE_DISABLE_FVAL                                               0x1
#define HWIO_FEATURE_CONFIG1_PCIE_0_DISABLE_BMSK                                                       0x1
#define HWIO_FEATURE_CONFIG1_PCIE_0_DISABLE_SHFT                                                       0x0
#define HWIO_FEATURE_CONFIG1_PCIE_0_DISABLE_ENABLE_FVAL                                                0x0
#define HWIO_FEATURE_CONFIG1_PCIE_0_DISABLE_DISABLE_FVAL                                               0x1

#define HWIO_FEATURE_CONFIG2_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000600c)
#define HWIO_FEATURE_CONFIG2_OFFS                                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000600c)
#define HWIO_FEATURE_CONFIG2_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG2_IN          \
        in_dword(HWIO_FEATURE_CONFIG2_ADDR)
#define HWIO_FEATURE_CONFIG2_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG2_ADDR, m)
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_HARD_BMSK                                    0xffffc000
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_HARD_SHFT                                           0xe
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_HARD_ENABLE_FVAL                                    0x0
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_HARD_DISABLE_FVAL                                   0x1
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_IU_BMSK                                          0x3c00
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_IU_SHFT                                             0xa
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_IU_ENABLE_FVAL                                      0x0
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_IU_DISABLE_FVAL                                     0x1
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_SPARE_BMSK                                        0x3ff
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_SPARE_SHFT                                          0x0
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_SPARE_ENABLE_FVAL                                   0x0
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_SPARE_DISABLE_FVAL                                  0x1

#define HWIO_FEATURE_CONFIG3_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006010)
#define HWIO_FEATURE_CONFIG3_OFFS                                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006010)
#define HWIO_FEATURE_CONFIG3_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG3_IN          \
        in_dword(HWIO_FEATURE_CONFIG3_ADDR)
#define HWIO_FEATURE_CONFIG3_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG3_ADDR, m)
#define HWIO_FEATURE_CONFIG3_APSS_PDXWRPNTRDELAY_BMSK                                           0xc0000000
#define HWIO_FEATURE_CONFIG3_APSS_PDXWRPNTRDELAY_SHFT                                                 0x1e
#define HWIO_FEATURE_CONFIG3_SEC_CTRL_GCC_NPU_FUSE_DISABLE_BMSK                                 0x20000000
#define HWIO_FEATURE_CONFIG3_SEC_CTRL_GCC_NPU_FUSE_DISABLE_SHFT                                       0x1d
#define HWIO_FEATURE_CONFIG3_SEC_CTRL_GCC_NPU_FUSE_DISABLE_ENABLE_FVAL                                 0x0
#define HWIO_FEATURE_CONFIG3_SEC_CTRL_GCC_NPU_FUSE_DISABLE_DISABLE_FVAL                                0x1
#define HWIO_FEATURE_CONFIG3_AUTOMOTIVE_BIT_FUNCTIONAL_BMSK                                     0x10000000
#define HWIO_FEATURE_CONFIG3_AUTOMOTIVE_BIT_FUNCTIONAL_SHFT                                           0x1c
#define HWIO_FEATURE_CONFIG3_AUTOMOTIVE_BIT_FUNCTIONAL_MOBILE_FVAL                                     0x0
#define HWIO_FEATURE_CONFIG3_AUTOMOTIVE_BIT_FUNCTIONAL_AUTOMOTIVE_FVAL                                 0x1
#define HWIO_FEATURE_CONFIG3_AUTOMOTIVE_BIT_POWER_BMSK                                           0x8000000
#define HWIO_FEATURE_CONFIG3_AUTOMOTIVE_BIT_POWER_SHFT                                                0x1b
#define HWIO_FEATURE_CONFIG3_AUTOMOTIVE_BIT_POWER_MOBILE_FVAL                                          0x0
#define HWIO_FEATURE_CONFIG3_AUTOMOTIVE_BIT_POWER_AUTOMOTIVE_FVAL                                      0x1
#define HWIO_FEATURE_CONFIG3_EMAC_DISABLE_BMSK                                                   0x4000000
#define HWIO_FEATURE_CONFIG3_EMAC_DISABLE_SHFT                                                        0x1a
#define HWIO_FEATURE_CONFIG3_EMAC_DISABLE_ENABLE_FVAL                                                  0x0
#define HWIO_FEATURE_CONFIG3_EMAC_DISABLE_DISABLE_FVAL                                                 0x1
#define HWIO_FEATURE_CONFIG3_MODEM_TCM_BOOT_DISABLE_BMSK                                         0x2000000
#define HWIO_FEATURE_CONFIG3_MODEM_TCM_BOOT_DISABLE_SHFT                                              0x19
#define HWIO_FEATURE_CONFIG3_MODEM_TCM_BOOT_DISABLE_ENABLE_FVAL                                        0x0
#define HWIO_FEATURE_CONFIG3_MODEM_TCM_BOOT_DISABLE_DISABLE_FVAL                                       0x1
#define HWIO_FEATURE_CONFIG3_NAV_DISABLE_BMSK                                                    0x1000000
#define HWIO_FEATURE_CONFIG3_NAV_DISABLE_SHFT                                                         0x18
#define HWIO_FEATURE_CONFIG3_NAV_DISABLE_ENABLE_FVAL                                                   0x0
#define HWIO_FEATURE_CONFIG3_NAV_DISABLE_DISABLE_FVAL                                                  0x1
#define HWIO_FEATURE_CONFIG3_MODEM_FEATURE_DISABLE_SOFT_BMSK                                      0xffffff
#define HWIO_FEATURE_CONFIG3_MODEM_FEATURE_DISABLE_SOFT_SHFT                                           0x0
#define HWIO_FEATURE_CONFIG3_MODEM_FEATURE_DISABLE_SOFT_ENABLE_FVAL                                    0x0
#define HWIO_FEATURE_CONFIG3_MODEM_FEATURE_DISABLE_SOFT_DISABLE_FVAL                                   0x1

#define HWIO_FEATURE_CONFIG4_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006014)
#define HWIO_FEATURE_CONFIG4_OFFS                                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006014)
#define HWIO_FEATURE_CONFIG4_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG4_IN          \
        in_dword(HWIO_FEATURE_CONFIG4_ADDR)
#define HWIO_FEATURE_CONFIG4_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG4_ADDR, m)
#define HWIO_FEATURE_CONFIG4_P2S_ACCU_RED_DEC_END_VAL_FUSE0_BMSK                                0x80000000
#define HWIO_FEATURE_CONFIG4_P2S_ACCU_RED_DEC_END_VAL_FUSE0_SHFT                                      0x1f
#define HWIO_FEATURE_CONFIG4_FUSE_CORTEX_M3_DISABLE_BMSK                                        0x40000000
#define HWIO_FEATURE_CONFIG4_FUSE_CORTEX_M3_DISABLE_SHFT                                              0x1e
#define HWIO_FEATURE_CONFIG4_Q_CONFIG_FUSE_BMSK                                                 0x20000000
#define HWIO_FEATURE_CONFIG4_Q_CONFIG_FUSE_SHFT                                                       0x1d
#define HWIO_FEATURE_CONFIG4_I_MC5_FUSE_BMSK                                                    0x10000000
#define HWIO_FEATURE_CONFIG4_I_MC5_FUSE_SHFT                                                          0x1c
#define HWIO_FEATURE_CONFIG4_I_MC4_FUSE_BMSK                                                     0x8000000
#define HWIO_FEATURE_CONFIG4_I_MC4_FUSE_SHFT                                                          0x1b
#define HWIO_FEATURE_CONFIG4_RSVD_BMSK                                                           0x4000000
#define HWIO_FEATURE_CONFIG4_RSVD_SHFT                                                                0x1a
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC5_DEBUG_DISABLE_BMSK                                  0x2000000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC5_DEBUG_DISABLE_SHFT                                       0x19
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC5_DEBUG_DISABLE_ENABLE_FVAL                                 0x0
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC5_DEBUG_DISABLE_DISABLE_FVAL                                0x1
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC4_DEBUG_DISABLE_BMSK                                  0x1000000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC4_DEBUG_DISABLE_SHFT                                       0x18
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC4_DEBUG_DISABLE_ENABLE_FVAL                                 0x0
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC4_DEBUG_DISABLE_DISABLE_FVAL                                0x1
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC3_DEBUG_DISABLE_BMSK                                   0x800000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC3_DEBUG_DISABLE_SHFT                                       0x17
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC3_DEBUG_DISABLE_ENABLE_FVAL                                 0x0
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC3_DEBUG_DISABLE_DISABLE_FVAL                                0x1
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC2_DEBUG_DISABLE_BMSK                                   0x400000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC2_DEBUG_DISABLE_SHFT                                       0x16
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC2_DEBUG_DISABLE_ENABLE_FVAL                                 0x0
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC2_DEBUG_DISABLE_DISABLE_FVAL                                0x1
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC1_DEBUG_DISABLE_BMSK                                   0x200000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC1_DEBUG_DISABLE_SHFT                                       0x15
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC1_DEBUG_DISABLE_ENABLE_FVAL                                 0x0
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC1_DEBUG_DISABLE_DISABLE_FVAL                                0x1
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC_DEBUG_DISABLE_BMSK                                    0x100000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC_DEBUG_DISABLE_SHFT                                        0x14
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC_DEBUG_DISABLE_ENABLE_FVAL                                  0x0
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC_DEBUG_DISABLE_DISABLE_FVAL                                 0x1
#define HWIO_FEATURE_CONFIG4_QC_APPS_NIDEN_DISABLE_BMSK                                            0x80000
#define HWIO_FEATURE_CONFIG4_QC_APPS_NIDEN_DISABLE_SHFT                                               0x13
#define HWIO_FEATURE_CONFIG4_QC_APPS_NIDEN_DISABLE_ENABLE_FVAL                                         0x0
#define HWIO_FEATURE_CONFIG4_QC_APPS_NIDEN_DISABLE_DISABLE_FVAL                                        0x1
#define HWIO_FEATURE_CONFIG4_QC_APPS_DBGEN_DISABLE_BMSK                                            0x40000
#define HWIO_FEATURE_CONFIG4_QC_APPS_DBGEN_DISABLE_SHFT                                               0x12
#define HWIO_FEATURE_CONFIG4_QC_APPS_DBGEN_DISABLE_ENABLE_FVAL                                         0x0
#define HWIO_FEATURE_CONFIG4_QC_APPS_DBGEN_DISABLE_DISABLE_FVAL                                        0x1
#define HWIO_FEATURE_CONFIG4_QC_SHARED_NS_NIDEN_DISABLE_BMSK                                       0x20000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_NS_NIDEN_DISABLE_SHFT                                          0x11
#define HWIO_FEATURE_CONFIG4_QC_SHARED_NS_NIDEN_DISABLE_ENABLE_FVAL                                    0x0
#define HWIO_FEATURE_CONFIG4_QC_SHARED_NS_NIDEN_DISABLE_DISABLE_FVAL                                   0x1
#define HWIO_FEATURE_CONFIG4_QC_SHARED_NS_DBGEN_DISABLE_BMSK                                       0x10000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_NS_DBGEN_DISABLE_SHFT                                          0x10
#define HWIO_FEATURE_CONFIG4_QC_SHARED_NS_DBGEN_DISABLE_ENABLE_FVAL                                    0x0
#define HWIO_FEATURE_CONFIG4_QC_SHARED_NS_DBGEN_DISABLE_DISABLE_FVAL                                   0x1
#define HWIO_FEATURE_CONFIG4_QC_SHARED_CP_NIDEN_DISABLE_BMSK                                        0x8000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_CP_NIDEN_DISABLE_SHFT                                           0xf
#define HWIO_FEATURE_CONFIG4_QC_SHARED_CP_NIDEN_DISABLE_ENABLE_FVAL                                    0x0
#define HWIO_FEATURE_CONFIG4_QC_SHARED_CP_NIDEN_DISABLE_DISABLE_FVAL                                   0x1
#define HWIO_FEATURE_CONFIG4_QC_SHARED_CP_DBGEN_DISABLE_BMSK                                        0x4000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_CP_DBGEN_DISABLE_SHFT                                           0xe
#define HWIO_FEATURE_CONFIG4_QC_SHARED_CP_DBGEN_DISABLE_ENABLE_FVAL                                    0x0
#define HWIO_FEATURE_CONFIG4_QC_SHARED_CP_DBGEN_DISABLE_DISABLE_FVAL                                   0x1
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MSS_NIDEN_DISABLE_BMSK                                       0x2000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MSS_NIDEN_DISABLE_SHFT                                          0xd
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MSS_NIDEN_DISABLE_ENABLE_FVAL                                   0x0
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MSS_NIDEN_DISABLE_DISABLE_FVAL                                  0x1
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MSS_DBGEN_DISABLE_BMSK                                       0x1000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MSS_DBGEN_DISABLE_SHFT                                          0xc
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MSS_DBGEN_DISABLE_ENABLE_FVAL                                   0x0
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MSS_DBGEN_DISABLE_DISABLE_FVAL                                  0x1
#define HWIO_FEATURE_CONFIG4_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                                     0x800
#define HWIO_FEATURE_CONFIG4_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                                       0xb
#define HWIO_FEATURE_CONFIG4_QC_SHARED_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL                                0x0
#define HWIO_FEATURE_CONFIG4_QC_SHARED_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL                               0x1
#define HWIO_FEATURE_CONFIG4_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK                                      0x400
#define HWIO_FEATURE_CONFIG4_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT                                        0xa
#define HWIO_FEATURE_CONFIG4_QC_SHARED_QSEE_SPIDEN_DISABLE_ENABLE_FVAL                                 0x0
#define HWIO_FEATURE_CONFIG4_QC_SHARED_QSEE_SPIDEN_DISABLE_DISABLE_FVAL                                0x1
#define HWIO_FEATURE_CONFIG4_PRIVATE_NS_NIDEN_DISABLE_BMSK                                           0x200
#define HWIO_FEATURE_CONFIG4_PRIVATE_NS_NIDEN_DISABLE_SHFT                                             0x9
#define HWIO_FEATURE_CONFIG4_PRIVATE_NS_NIDEN_DISABLE_ENABLE_FVAL                                      0x0
#define HWIO_FEATURE_CONFIG4_PRIVATE_NS_NIDEN_DISABLE_DISABLE_FVAL                                     0x1
#define HWIO_FEATURE_CONFIG4_PRIVATE_NS_DBGEN_DISABLE_BMSK                                           0x100
#define HWIO_FEATURE_CONFIG4_PRIVATE_NS_DBGEN_DISABLE_SHFT                                             0x8
#define HWIO_FEATURE_CONFIG4_PRIVATE_NS_DBGEN_DISABLE_ENABLE_FVAL                                      0x0
#define HWIO_FEATURE_CONFIG4_PRIVATE_NS_DBGEN_DISABLE_DISABLE_FVAL                                     0x1
#define HWIO_FEATURE_CONFIG4_PRIVATE_CP_NIDEN_DISABLE_BMSK                                            0x80
#define HWIO_FEATURE_CONFIG4_PRIVATE_CP_NIDEN_DISABLE_SHFT                                             0x7
#define HWIO_FEATURE_CONFIG4_PRIVATE_CP_NIDEN_DISABLE_ENABLE_FVAL                                      0x0
#define HWIO_FEATURE_CONFIG4_PRIVATE_CP_NIDEN_DISABLE_DISABLE_FVAL                                     0x1
#define HWIO_FEATURE_CONFIG4_PRIVATE_CP_DBGEN_DISABLE_BMSK                                            0x40
#define HWIO_FEATURE_CONFIG4_PRIVATE_CP_DBGEN_DISABLE_SHFT                                             0x6
#define HWIO_FEATURE_CONFIG4_PRIVATE_CP_DBGEN_DISABLE_ENABLE_FVAL                                      0x0
#define HWIO_FEATURE_CONFIG4_PRIVATE_CP_DBGEN_DISABLE_DISABLE_FVAL                                     0x1
#define HWIO_FEATURE_CONFIG4_PRIVATE_MSS_NIDEN_DISABLE_BMSK                                           0x20
#define HWIO_FEATURE_CONFIG4_PRIVATE_MSS_NIDEN_DISABLE_SHFT                                            0x5
#define HWIO_FEATURE_CONFIG4_PRIVATE_MSS_NIDEN_DISABLE_ENABLE_FVAL                                     0x0
#define HWIO_FEATURE_CONFIG4_PRIVATE_MSS_NIDEN_DISABLE_DISABLE_FVAL                                    0x1
#define HWIO_FEATURE_CONFIG4_PRIVATE_MSS_DBGEN_DISABLE_BMSK                                           0x10
#define HWIO_FEATURE_CONFIG4_PRIVATE_MSS_DBGEN_DISABLE_SHFT                                            0x4
#define HWIO_FEATURE_CONFIG4_PRIVATE_MSS_DBGEN_DISABLE_ENABLE_FVAL                                     0x0
#define HWIO_FEATURE_CONFIG4_PRIVATE_MSS_DBGEN_DISABLE_DISABLE_FVAL                                    0x1
#define HWIO_FEATURE_CONFIG4_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK                                         0x8
#define HWIO_FEATURE_CONFIG4_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT                                         0x3
#define HWIO_FEATURE_CONFIG4_PRIVATE_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL                                  0x0
#define HWIO_FEATURE_CONFIG4_PRIVATE_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL                                 0x1
#define HWIO_FEATURE_CONFIG4_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK                                          0x4
#define HWIO_FEATURE_CONFIG4_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT                                          0x2
#define HWIO_FEATURE_CONFIG4_PRIVATE_QSEE_SPIDEN_DISABLE_ENABLE_FVAL                                   0x0
#define HWIO_FEATURE_CONFIG4_PRIVATE_QSEE_SPIDEN_DISABLE_DISABLE_FVAL                                  0x1
#define HWIO_FEATURE_CONFIG4_SM_BIST_DISABLE_BMSK                                                      0x2
#define HWIO_FEATURE_CONFIG4_SM_BIST_DISABLE_SHFT                                                      0x1
#define HWIO_FEATURE_CONFIG4_SM_BIST_DISABLE_ENABLE_FVAL                                               0x0
#define HWIO_FEATURE_CONFIG4_SM_BIST_DISABLE_DISABLE_FVAL                                              0x1
#define HWIO_FEATURE_CONFIG4_TIC_DISABLE_BMSK                                                          0x1
#define HWIO_FEATURE_CONFIG4_TIC_DISABLE_SHFT                                                          0x0
#define HWIO_FEATURE_CONFIG4_TIC_DISABLE_ENABLE_FVAL                                                   0x0
#define HWIO_FEATURE_CONFIG4_TIC_DISABLE_DISABLE_FVAL                                                  0x1

#define HWIO_FEATURE_CONFIG5_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006018)
#define HWIO_FEATURE_CONFIG5_OFFS                                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006018)
#define HWIO_FEATURE_CONFIG5_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG5_IN          \
        in_dword(HWIO_FEATURE_CONFIG5_ADDR)
#define HWIO_FEATURE_CONFIG5_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG5_ADDR, m)
#define HWIO_FEATURE_CONFIG5_SYS_CFG_APC1PLL_LVAL_BMSK                                          0xff000000
#define HWIO_FEATURE_CONFIG5_SYS_CFG_APC1PLL_LVAL_SHFT                                                0x18
#define HWIO_FEATURE_CONFIG5_APSS_KRYO_PP_DISABLE_BMSK                                            0x800000
#define HWIO_FEATURE_CONFIG5_APSS_KRYO_PP_DISABLE_SHFT                                                0x17
#define HWIO_FEATURE_CONFIG5_SYS_CFG_L3_SIZE_RED_BMSK                                             0x400000
#define HWIO_FEATURE_CONFIG5_SYS_CFG_L3_SIZE_RED_SHFT                                                 0x16
#define HWIO_FEATURE_CONFIG5_AUTO_CCI_RCG_CFG_DISABLE_BMSK                                        0x200000
#define HWIO_FEATURE_CONFIG5_AUTO_CCI_RCG_CFG_DISABLE_SHFT                                            0x15
#define HWIO_FEATURE_CONFIG5_APPS_BOOT_FSM_FUSE_BMSK                                              0x1f8000
#define HWIO_FEATURE_CONFIG5_APPS_BOOT_FSM_FUSE_SHFT                                                   0xf
#define HWIO_FEATURE_CONFIG5_SYS_APCSCFGAPMBOOTONMX_BMSK                                            0x4000
#define HWIO_FEATURE_CONFIG5_SYS_APCSCFGAPMBOOTONMX_SHFT                                               0xe
#define HWIO_FEATURE_CONFIG5_SYS_APCCCFGCPUPRESENT_N_BMSK                                           0x3fc0
#define HWIO_FEATURE_CONFIG5_SYS_APCCCFGCPUPRESENT_N_SHFT                                              0x6
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE6_BMSK                                      0x20
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE6_SHFT                                       0x5
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE5_BMSK                                      0x10
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE5_SHFT                                       0x4
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE4_BMSK                                       0x8
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE4_SHFT                                       0x3
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE3_BMSK                                       0x4
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE3_SHFT                                       0x2
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE2_BMSK                                       0x2
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE2_SHFT                                       0x1
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE1_BMSK                                       0x1
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE1_SHFT                                       0x0

#define HWIO_FEATURE_CONFIG6_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000601c)
#define HWIO_FEATURE_CONFIG6_OFFS                                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000601c)
#define HWIO_FEATURE_CONFIG6_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG6_IN          \
        in_dword(HWIO_FEATURE_CONFIG6_ADDR)
#define HWIO_FEATURE_CONFIG6_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG6_ADDR, m)
#define HWIO_FEATURE_CONFIG6_RSVD1_BMSK                                                         0x80000000
#define HWIO_FEATURE_CONFIG6_RSVD1_SHFT                                                               0x1f
#define HWIO_FEATURE_CONFIG6_SYS_CFG_GOLDPLUS_PLL_LVAL_BMSK                                     0x7f800000
#define HWIO_FEATURE_CONFIG6_SYS_CFG_GOLDPLUS_PLL_LVAL_SHFT                                           0x17
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_6_BMSK                                          0x400000
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_6_SHFT                                              0x16
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_5_BMSK                                          0x200000
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_5_SHFT                                              0x15
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_4_BMSK                                          0x100000
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_4_SHFT                                              0x14
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_3_BMSK                                           0x80000
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_3_SHFT                                              0x13
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_2_BMSK                                           0x40000
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_2_SHFT                                              0x12
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_1_BMSK                                           0x20000
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_1_SHFT                                              0x11
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_0_BMSK                                           0x10000
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_0_SHFT                                              0x10
#define HWIO_FEATURE_CONFIG6_TURING_Q6SS_PLL_L_MAX_BMSK                                             0xffff
#define HWIO_FEATURE_CONFIG6_TURING_Q6SS_PLL_L_MAX_SHFT                                                0x0

#define HWIO_FEATURE_CONFIG7_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006020)
#define HWIO_FEATURE_CONFIG7_OFFS                                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006020)
#define HWIO_FEATURE_CONFIG7_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG7_IN          \
        in_dword(HWIO_FEATURE_CONFIG7_ADDR)
#define HWIO_FEATURE_CONFIG7_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG7_ADDR, m)
#define HWIO_FEATURE_CONFIG7_RSVD_BMSK                                                          0xfffffffe
#define HWIO_FEATURE_CONFIG7_RSVD_SHFT                                                                 0x1
#define HWIO_FEATURE_CONFIG7_DISABLE_SEC_BOOT_GPIO_BMSK                                                0x1
#define HWIO_FEATURE_CONFIG7_DISABLE_SEC_BOOT_GPIO_SHFT                                                0x0

#define HWIO_FEATURE_CONFIG8_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006024)
#define HWIO_FEATURE_CONFIG8_OFFS                                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006024)
#define HWIO_FEATURE_CONFIG8_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG8_IN          \
        in_dword(HWIO_FEATURE_CONFIG8_ADDR)
#define HWIO_FEATURE_CONFIG8_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG8_ADDR, m)
#define HWIO_FEATURE_CONFIG8_RSVD_BMSK                                                          0xfffffffe
#define HWIO_FEATURE_CONFIG8_RSVD_SHFT                                                                 0x1
#define HWIO_FEATURE_CONFIG8_LEGACY_MBNV6_OVERRIDE_BMSK                                                0x1
#define HWIO_FEATURE_CONFIG8_LEGACY_MBNV6_OVERRIDE_SHFT                                                0x0

#define HWIO_FEATURE_CONFIG9_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006028)
#define HWIO_FEATURE_CONFIG9_OFFS                                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006028)
#define HWIO_FEATURE_CONFIG9_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG9_IN          \
        in_dword(HWIO_FEATURE_CONFIG9_ADDR)
#define HWIO_FEATURE_CONFIG9_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG9_ADDR, m)
#define HWIO_FEATURE_CONFIG9_RSVD_BMSK                                                          0xffffffff
#define HWIO_FEATURE_CONFIG9_RSVD_SHFT                                                                 0x0

#define HWIO_FEATURE_CONFIG10_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000602c)
#define HWIO_FEATURE_CONFIG10_OFFS                                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000602c)
#define HWIO_FEATURE_CONFIG10_RMSK                                                              0xffffffff
#define HWIO_FEATURE_CONFIG10_IN          \
        in_dword(HWIO_FEATURE_CONFIG10_ADDR)
#define HWIO_FEATURE_CONFIG10_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG10_ADDR, m)
#define HWIO_FEATURE_CONFIG10_RSVD1_BMSK                                                        0xffffffff
#define HWIO_FEATURE_CONFIG10_RSVD1_SHFT                                                               0x0

#define HWIO_FEATURE_CONFIG11_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006030)
#define HWIO_FEATURE_CONFIG11_OFFS                                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006030)
#define HWIO_FEATURE_CONFIG11_RMSK                                                              0xffffffff
#define HWIO_FEATURE_CONFIG11_IN          \
        in_dword(HWIO_FEATURE_CONFIG11_ADDR)
#define HWIO_FEATURE_CONFIG11_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG11_ADDR, m)
#define HWIO_FEATURE_CONFIG11_RSVD1_BMSK                                                        0xffffffff
#define HWIO_FEATURE_CONFIG11_RSVD1_SHFT                                                               0x0

#define HWIO_FEATURE_CONFIG12_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006034)
#define HWIO_FEATURE_CONFIG12_OFFS                                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006034)
#define HWIO_FEATURE_CONFIG12_RMSK                                                              0xffffffff
#define HWIO_FEATURE_CONFIG12_IN          \
        in_dword(HWIO_FEATURE_CONFIG12_ADDR)
#define HWIO_FEATURE_CONFIG12_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG12_ADDR, m)
#define HWIO_FEATURE_CONFIG12_TAP_GEN_SPARE_INSTR_DISABLE_13_0_BMSK                             0xfffc0000
#define HWIO_FEATURE_CONFIG12_TAP_GEN_SPARE_INSTR_DISABLE_13_0_SHFT                                   0x12
#define HWIO_FEATURE_CONFIG12_TAP_INSTR_DISABLE_BMSK                                               0x3ffff
#define HWIO_FEATURE_CONFIG12_TAP_INSTR_DISABLE_SHFT                                                   0x0

#define HWIO_FEATURE_CONFIG13_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006038)
#define HWIO_FEATURE_CONFIG13_OFFS                                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006038)
#define HWIO_FEATURE_CONFIG13_RMSK                                                              0xffffffff
#define HWIO_FEATURE_CONFIG13_IN          \
        in_dword(HWIO_FEATURE_CONFIG13_ADDR)
#define HWIO_FEATURE_CONFIG13_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG13_ADDR, m)
#define HWIO_FEATURE_CONFIG13_SEC_TAP_ACCESS_DISABLE_BMSK                                       0xfffc0000
#define HWIO_FEATURE_CONFIG13_SEC_TAP_ACCESS_DISABLE_SHFT                                             0x12
#define HWIO_FEATURE_CONFIG13_TAP_GEN_SPARE_INSTR_DISABLE_31_14_BMSK                               0x3ffff
#define HWIO_FEATURE_CONFIG13_TAP_GEN_SPARE_INSTR_DISABLE_31_14_SHFT                                   0x0

#define HWIO_FEATURE_CONFIG14_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000603c)
#define HWIO_FEATURE_CONFIG14_OFFS                                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000603c)
#define HWIO_FEATURE_CONFIG14_RMSK                                                              0xffffffff
#define HWIO_FEATURE_CONFIG14_IN          \
        in_dword(HWIO_FEATURE_CONFIG14_ADDR)
#define HWIO_FEATURE_CONFIG14_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG14_ADDR, m)
#define HWIO_FEATURE_CONFIG14_MODEM_PBL_PATCH_VERSION_BMSK                                      0xfe000000
#define HWIO_FEATURE_CONFIG14_MODEM_PBL_PATCH_VERSION_SHFT                                            0x19
#define HWIO_FEATURE_CONFIG14_APPS_PBL_PATCH_VERSION_BMSK                                        0x1fc0000
#define HWIO_FEATURE_CONFIG14_APPS_PBL_PATCH_VERSION_SHFT                                             0x12
#define HWIO_FEATURE_CONFIG14_APPS_PBL_BOOT_SPEED_BMSK                                             0x30000
#define HWIO_FEATURE_CONFIG14_APPS_PBL_BOOT_SPEED_SHFT                                                0x10
#define HWIO_FEATURE_CONFIG14_APPS_PBL_BOOT_SPEED_ENUM_600_MHZ_FVAL                                    0x0
#define HWIO_FEATURE_CONFIG14_APPS_PBL_BOOT_SPEED_XO_FVAL                                              0x1
#define HWIO_FEATURE_CONFIG14_APPS_PBL_BOOT_SPEED_ENUM_1200_MHZ_FVAL                                   0x2
#define HWIO_FEATURE_CONFIG14_APPS_PBL_BOOT_SPEED_NA_FVAL                                              0x3
#define HWIO_FEATURE_CONFIG14_MODEM_PBL_BOOT_BMSK                                                   0x8000
#define HWIO_FEATURE_CONFIG14_MODEM_PBL_BOOT_SHFT                                                      0xf
#define HWIO_FEATURE_CONFIG14_RSVD1_56_14_BMSK                                                      0x4000
#define HWIO_FEATURE_CONFIG14_RSVD1_56_14_SHFT                                                         0xe
#define HWIO_FEATURE_CONFIG14_APPS_BOOT_FROM_ROM_BMSK                                               0x2000
#define HWIO_FEATURE_CONFIG14_APPS_BOOT_FROM_ROM_SHFT                                                  0xd
#define HWIO_FEATURE_CONFIG14_ENABLE_DEVICE_IN_TEST_MODE_BMSK                                       0x1000
#define HWIO_FEATURE_CONFIG14_ENABLE_DEVICE_IN_TEST_MODE_SHFT                                          0xc
#define HWIO_FEATURE_CONFIG14_QTI_ROOT_SIG_FORMAT_SEL_BMSK                                           0x800
#define HWIO_FEATURE_CONFIG14_QTI_ROOT_SIG_FORMAT_SEL_SHFT                                             0xb
#define HWIO_FEATURE_CONFIG14_CE_BAM_DISABLE_BMSK                                                    0x400
#define HWIO_FEATURE_CONFIG14_CE_BAM_DISABLE_SHFT                                                      0xa
#define HWIO_FEATURE_CONFIG14_CE_BAM_DISABLE_ENABLE_FVAL                                               0x0
#define HWIO_FEATURE_CONFIG14_CE_BAM_DISABLE_DISABLE_FVAL                                              0x1
#define HWIO_FEATURE_CONFIG14_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_BMSK                                0x200
#define HWIO_FEATURE_CONFIG14_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_SHFT                                  0x9
#define HWIO_FEATURE_CONFIG14_ARM_CE_DISABLE_USAGE_BMSK                                              0x100
#define HWIO_FEATURE_CONFIG14_ARM_CE_DISABLE_USAGE_SHFT                                                0x8
#define HWIO_FEATURE_CONFIG14_BOOT_ROM_CFG_BMSK                                                       0xff
#define HWIO_FEATURE_CONFIG14_BOOT_ROM_CFG_SHFT                                                        0x0

#define HWIO_FEATURE_CONFIG15_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006040)
#define HWIO_FEATURE_CONFIG15_OFFS                                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006040)
#define HWIO_FEATURE_CONFIG15_RMSK                                                              0xffffffff
#define HWIO_FEATURE_CONFIG15_IN          \
        in_dword(HWIO_FEATURE_CONFIG15_ADDR)
#define HWIO_FEATURE_CONFIG15_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG15_ADDR, m)
#define HWIO_FEATURE_CONFIG15_APPS_BOOT_TRIGGER_DISABLE_BMSK                                    0x80000000
#define HWIO_FEATURE_CONFIG15_APPS_BOOT_TRIGGER_DISABLE_SHFT                                          0x1f
#define HWIO_FEATURE_CONFIG15_APPS_BOOT_TRIGGER_DISABLE_ENABLE_FVAL                                    0x0
#define HWIO_FEATURE_CONFIG15_APPS_BOOT_TRIGGER_DISABLE_DISABLE_FVAL                                   0x1
#define HWIO_FEATURE_CONFIG15_PBL_QSEE_BOOT_FLOW_DISABLE_BMSK                                   0x40000000
#define HWIO_FEATURE_CONFIG15_PBL_QSEE_BOOT_FLOW_DISABLE_SHFT                                         0x1e
#define HWIO_FEATURE_CONFIG15_XBL_SEC_AUTH_DISABLE_BMSK                                         0x20000000
#define HWIO_FEATURE_CONFIG15_XBL_SEC_AUTH_DISABLE_SHFT                                               0x1d
#define HWIO_FEATURE_CONFIG15_MSM_PKG_TYPE_BMSK                                                 0x10000000
#define HWIO_FEATURE_CONFIG15_MSM_PKG_TYPE_SHFT                                                       0x1c
#define HWIO_FEATURE_CONFIG15_SPSS_CONFIG_MODE_BMSK                                              0xc000000
#define HWIO_FEATURE_CONFIG15_SPSS_CONFIG_MODE_SHFT                                                   0x1a
#define HWIO_FEATURE_CONFIG15_PERIPH_DRV_STRENGTH_SETTING_BMSK                                   0x3800000
#define HWIO_FEATURE_CONFIG15_PERIPH_DRV_STRENGTH_SETTING_SHFT                                        0x17
#define HWIO_FEATURE_CONFIG15_RSVD3_56_54_BMSK                                                    0x400000
#define HWIO_FEATURE_CONFIG15_RSVD3_56_54_SHFT                                                        0x16
#define HWIO_FEATURE_CONFIG15_FOUNDRY_ID_BMSK                                                     0x3c0000
#define HWIO_FEATURE_CONFIG15_FOUNDRY_ID_SHFT                                                         0x12
#define HWIO_FEATURE_CONFIG15_FOUNDRY_ID_TSMC_FVAL                                                     0x0
#define HWIO_FEATURE_CONFIG15_FOUNDRY_ID_GLOBAL_FOUNDRIES_FVAL                                         0x1
#define HWIO_FEATURE_CONFIG15_FOUNDRY_ID_SAMSUNG_FVAL                                                  0x2
#define HWIO_FEATURE_CONFIG15_FOUNDRY_ID_IBM_FVAL                                                      0x3
#define HWIO_FEATURE_CONFIG15_FOUNDRY_ID_UMC_FVAL                                                      0x4
#define HWIO_FEATURE_CONFIG15_FOUNDRY_ID_SMIC_FVAL                                                     0x5
#define HWIO_FEATURE_CONFIG15_PLL_CFG_BMSK                                                         0x3fff0
#define HWIO_FEATURE_CONFIG15_PLL_CFG_SHFT                                                             0x4
#define HWIO_FEATURE_CONFIG15_APPS_PBL_PLL_CTRL_BMSK                                                   0xf
#define HWIO_FEATURE_CONFIG15_APPS_PBL_PLL_CTRL_SHFT                                                   0x0

#define HWIO_OEM_CONFIG0_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006044)
#define HWIO_OEM_CONFIG0_OFFS                                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006044)
#define HWIO_OEM_CONFIG0_RMSK                                                                   0xffffffff
#define HWIO_OEM_CONFIG0_IN          \
        in_dword(HWIO_OEM_CONFIG0_ADDR)
#define HWIO_OEM_CONFIG0_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG0_ADDR, m)
#define HWIO_OEM_CONFIG0_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                                       0x80000000
#define HWIO_OEM_CONFIG0_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                                             0x1f
#define HWIO_OEM_CONFIG0_SHARED_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL                                       0x0
#define HWIO_OEM_CONFIG0_SHARED_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL                                      0x1
#define HWIO_OEM_CONFIG0_SHARED_QSEE_SPIDEN_DISABLE_BMSK                                        0x40000000
#define HWIO_OEM_CONFIG0_SHARED_QSEE_SPIDEN_DISABLE_SHFT                                              0x1e
#define HWIO_OEM_CONFIG0_SHARED_QSEE_SPIDEN_DISABLE_ENABLE_FVAL                                        0x0
#define HWIO_OEM_CONFIG0_SHARED_QSEE_SPIDEN_DISABLE_DISABLE_FVAL                                       0x1
#define HWIO_OEM_CONFIG0_ALL_DEBUG_DISABLE_BMSK                                                 0x20000000
#define HWIO_OEM_CONFIG0_ALL_DEBUG_DISABLE_SHFT                                                       0x1d
#define HWIO_OEM_CONFIG0_ALL_DEBUG_DISABLE_ENABLE_FVAL                                                 0x0
#define HWIO_OEM_CONFIG0_ALL_DEBUG_DISABLE_DISABLE_FVAL                                                0x1
#define HWIO_OEM_CONFIG0_DEBUG_POLICY_DISABLE_BMSK                                              0x10000000
#define HWIO_OEM_CONFIG0_DEBUG_POLICY_DISABLE_SHFT                                                    0x1c
#define HWIO_OEM_CONFIG0_DEBUG_POLICY_DISABLE_ENABLE_FVAL                                              0x0
#define HWIO_OEM_CONFIG0_DEBUG_POLICY_DISABLE_DISABLE_FVAL                                             0x1
#define HWIO_OEM_CONFIG0_SP_DISABLE_BMSK                                                         0x8000000
#define HWIO_OEM_CONFIG0_SP_DISABLE_SHFT                                                              0x1b
#define HWIO_OEM_CONFIG0_SP_DISABLE_ENABLE_FVAL                                                        0x0
#define HWIO_OEM_CONFIG0_SP_DISABLE_DISABLE_FVAL                                                       0x1
#define HWIO_OEM_CONFIG0_UDK_DISABLE_BMSK                                                        0x4000000
#define HWIO_OEM_CONFIG0_UDK_DISABLE_SHFT                                                             0x1a
#define HWIO_OEM_CONFIG0_UDK_DISABLE_ENABLE_FVAL                                                       0x0
#define HWIO_OEM_CONFIG0_UDK_DISABLE_DISABLE_FVAL                                                      0x1
#define HWIO_OEM_CONFIG0_DEBUG_DISABLE_IN_ROM_BMSK                                               0x2000000
#define HWIO_OEM_CONFIG0_DEBUG_DISABLE_IN_ROM_SHFT                                                    0x19
#define HWIO_OEM_CONFIG0_MSS_HASH_INTEGRITY_CHECK_ENABLE_BMSK                                    0x1000000
#define HWIO_OEM_CONFIG0_MSS_HASH_INTEGRITY_CHECK_ENABLE_SHFT                                         0x18
#define HWIO_OEM_CONFIG0_MSS_HASH_INTEGRITY_CHECK_ENABLE_DISABLE_FVAL                                  0x0
#define HWIO_OEM_CONFIG0_MSS_HASH_INTEGRITY_CHECK_ENABLE_ENABLE_FVAL                                   0x1
#define HWIO_OEM_CONFIG0_APPS_HASH_INTEGRITY_CHECK_DISABLE_BMSK                                   0x800000
#define HWIO_OEM_CONFIG0_APPS_HASH_INTEGRITY_CHECK_DISABLE_SHFT                                       0x17
#define HWIO_OEM_CONFIG0_APPS_HASH_INTEGRITY_CHECK_DISABLE_DISABLE_FVAL                                0x0
#define HWIO_OEM_CONFIG0_APPS_HASH_INTEGRITY_CHECK_DISABLE_ENABLE_FVAL                                 0x1
#define HWIO_OEM_CONFIG0_USB_SS_DISABLE_BMSK                                                      0x400000
#define HWIO_OEM_CONFIG0_USB_SS_DISABLE_SHFT                                                          0x16
#define HWIO_OEM_CONFIG0_USB_SS_DISABLE_ENABLE_FVAL                                                    0x0
#define HWIO_OEM_CONFIG0_USB_SS_DISABLE_DISABLE_FVAL                                                   0x1
#define HWIO_OEM_CONFIG0_SW_ROT_USE_SERIAL_NUM_BMSK                                               0x200000
#define HWIO_OEM_CONFIG0_SW_ROT_USE_SERIAL_NUM_SHFT                                                   0x15
#define HWIO_OEM_CONFIG0_SW_ROT_USE_SERIAL_NUM_USE_OEM_ID_FVAL                                         0x0
#define HWIO_OEM_CONFIG0_SW_ROT_USE_SERIAL_NUM_USE_SERIAL_NUM_FVAL                                     0x1
#define HWIO_OEM_CONFIG0_DISABLE_ROT_TRANSFER_BMSK                                                0x100000
#define HWIO_OEM_CONFIG0_DISABLE_ROT_TRANSFER_SHFT                                                    0x14
#define HWIO_OEM_CONFIG0_DISABLE_ROT_TRANSFER_ENABLE_FVAL                                              0x0
#define HWIO_OEM_CONFIG0_DISABLE_ROT_TRANSFER_DISABLE_FVAL                                             0x1
#define HWIO_OEM_CONFIG0_IMAGE_ENCRYPTION_ENABLE_BMSK                                              0x80000
#define HWIO_OEM_CONFIG0_IMAGE_ENCRYPTION_ENABLE_SHFT                                                 0x13
#define HWIO_OEM_CONFIG0_ROOT_CERT_TOTAL_NUM_BMSK                                                  0x60000
#define HWIO_OEM_CONFIG0_ROOT_CERT_TOTAL_NUM_SHFT                                                     0x11
#define HWIO_OEM_CONFIG0_PBL_USB_TYPE_C_DISABLE_BMSK                                               0x10000
#define HWIO_OEM_CONFIG0_PBL_USB_TYPE_C_DISABLE_SHFT                                                  0x10
#define HWIO_OEM_CONFIG0_PBL_LOG_DISABLE_BMSK                                                       0x8000
#define HWIO_OEM_CONFIG0_PBL_LOG_DISABLE_SHFT                                                          0xf
#define HWIO_OEM_CONFIG0_WDOG_EN_BMSK                                                               0x4000
#define HWIO_OEM_CONFIG0_WDOG_EN_SHFT                                                                  0xe
#define HWIO_OEM_CONFIG0_WDOG_EN_USE_GPIO_FVAL                                                         0x0
#define HWIO_OEM_CONFIG0_WDOG_EN_IGNORE_GPIO_ENABLE_WDOG_FVAL                                          0x1
#define HWIO_OEM_CONFIG0_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_BMSK                                  0x2000
#define HWIO_OEM_CONFIG0_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_SHFT                                     0xd
#define HWIO_OEM_CONFIG0_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_DISABLE_EDL_RESET_FVAL                   0x0
#define HWIO_OEM_CONFIG0_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_ENABLE_EDL_RESET_FVAL                    0x1
#define HWIO_OEM_CONFIG0_SW_FUSE_PROG_DISABLE_BMSK                                                  0x1000
#define HWIO_OEM_CONFIG0_SW_FUSE_PROG_DISABLE_SHFT                                                     0xc
#define HWIO_OEM_CONFIG0_SPI_CLK_BOOT_FREQ_BMSK                                                      0x800
#define HWIO_OEM_CONFIG0_SPI_CLK_BOOT_FREQ_SHFT                                                        0xb
#define HWIO_OEM_CONFIG0_PBL_QSPI_BOOT_EDL_ENABLED_BMSK                                              0x400
#define HWIO_OEM_CONFIG0_PBL_QSPI_BOOT_EDL_ENABLED_SHFT                                                0xa
#define HWIO_OEM_CONFIG0_PBL_QSPI_BOOT_EDL_ENABLED_SD_USB_FVAL                                         0x0
#define HWIO_OEM_CONFIG0_PBL_QSPI_BOOT_EDL_ENABLED_QSPI_SD_USB_FVAL                                    0x1
#define HWIO_OEM_CONFIG0_FAST_BOOT_BMSK                                                              0x3e0
#define HWIO_OEM_CONFIG0_FAST_BOOT_SHFT                                                                0x5
#define HWIO_OEM_CONFIG0_FAST_BOOT_DEFAULT_FVAL                                                        0x0
#define HWIO_OEM_CONFIG0_FAST_BOOT_SD_UFS_EDL_FVAL                                                     0x1
#define HWIO_OEM_CONFIG0_FAST_BOOT_SD_EDL_FVAL                                                         0x2
#define HWIO_OEM_CONFIG0_FAST_BOOT_USB_EDL_FVAL                                                        0x3
#define HWIO_OEM_CONFIG0_FAST_BOOT_QSPI_EDL_FVAL                                                       0x4
#define HWIO_OEM_CONFIG0_FAST_BOOT_SPI_EDL_FVAL                                                        0x5
#define HWIO_OEM_CONFIG0_FAST_BOOT_UGSG4_SD_USB_EDL_FVAL                                               0x8
#define HWIO_OEM_CONFIG0_SDCC_MCLK_BOOT_FREQ_BMSK                                                     0x10
#define HWIO_OEM_CONFIG0_SDCC_MCLK_BOOT_FREQ_SHFT                                                      0x4
#define HWIO_OEM_CONFIG0_SDCC_MCLK_BOOT_FREQ_ENUM_19_2_MHZ_FVAL                                        0x0
#define HWIO_OEM_CONFIG0_SDCC_MCLK_BOOT_FREQ_ENUM_25_MHZ_FVAL                                          0x1
#define HWIO_OEM_CONFIG0_FORCE_USB_BOOT_DISABLE_BMSK                                                   0x8
#define HWIO_OEM_CONFIG0_FORCE_USB_BOOT_DISABLE_SHFT                                                   0x3
#define HWIO_OEM_CONFIG0_FORCE_USB_BOOT_DISABLE_USE_FORCE_USB_BOOT_GPIO_TO_FORCE_BOOT_FROM_USB_FVAL        0x0
#define HWIO_OEM_CONFIG0_FORCE_USB_BOOT_DISABLE_NOT_USE_FORCE_USB_BOOT_PIN_FVAL                        0x1
#define HWIO_OEM_CONFIG0_FORCE_DLOAD_DISABLE_BMSK                                                      0x4
#define HWIO_OEM_CONFIG0_FORCE_DLOAD_DISABLE_SHFT                                                      0x2
#define HWIO_OEM_CONFIG0_FORCE_DLOAD_DISABLE_USE_FORCE_USB_BOOT_GPIO_TO_FORCE_BOOT_FROM_USB_FVAL        0x0
#define HWIO_OEM_CONFIG0_FORCE_DLOAD_DISABLE_NOT_USE_FORCE_USB_BOOT_PIN_FVAL                           0x1
#define HWIO_OEM_CONFIG0_ENUM_TIMEOUT_BMSK                                                             0x2
#define HWIO_OEM_CONFIG0_ENUM_TIMEOUT_SHFT                                                             0x1
#define HWIO_OEM_CONFIG0_ENUM_TIMEOUT_TIMEOUT_DISABLED_FVAL                                            0x0
#define HWIO_OEM_CONFIG0_ENUM_TIMEOUT_TIMEOUT_ENABLED_90S_FVAL                                         0x1
#define HWIO_OEM_CONFIG0_E_DLOAD_DISABLE_BMSK                                                          0x1
#define HWIO_OEM_CONFIG0_E_DLOAD_DISABLE_SHFT                                                          0x0
#define HWIO_OEM_CONFIG0_E_DLOAD_DISABLE_DOWNLOADER_ENABLED_FVAL                                       0x0
#define HWIO_OEM_CONFIG0_E_DLOAD_DISABLE_DOWNLOADER_DISABLED_FVAL                                      0x1

#define HWIO_OEM_CONFIG1_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006048)
#define HWIO_OEM_CONFIG1_OFFS                                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006048)
#define HWIO_OEM_CONFIG1_RMSK                                                                   0xffffffff
#define HWIO_OEM_CONFIG1_IN          \
        in_dword(HWIO_OEM_CONFIG1_ADDR)
#define HWIO_OEM_CONFIG1_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG1_ADDR, m)
#define HWIO_OEM_CONFIG1_RSVD1_BMSK                                                             0xffffc000
#define HWIO_OEM_CONFIG1_RSVD1_SHFT                                                                    0xe
#define HWIO_OEM_CONFIG1_SHARED_MISC5_DEBUG_DISABLE_BMSK                                            0x2000
#define HWIO_OEM_CONFIG1_SHARED_MISC5_DEBUG_DISABLE_SHFT                                               0xd
#define HWIO_OEM_CONFIG1_SHARED_MISC5_DEBUG_DISABLE_ENABLE_FVAL                                        0x0
#define HWIO_OEM_CONFIG1_SHARED_MISC5_DEBUG_DISABLE_DISABLE_FVAL                                       0x1
#define HWIO_OEM_CONFIG1_SHARED_MISC4_DEBUG_DISABLE_BMSK                                            0x1000
#define HWIO_OEM_CONFIG1_SHARED_MISC4_DEBUG_DISABLE_SHFT                                               0xc
#define HWIO_OEM_CONFIG1_SHARED_MISC4_DEBUG_DISABLE_ENABLE_FVAL                                        0x0
#define HWIO_OEM_CONFIG1_SHARED_MISC4_DEBUG_DISABLE_DISABLE_FVAL                                       0x1
#define HWIO_OEM_CONFIG1_SHARED_MISC3_DEBUG_DISABLE_BMSK                                             0x800
#define HWIO_OEM_CONFIG1_SHARED_MISC3_DEBUG_DISABLE_SHFT                                               0xb
#define HWIO_OEM_CONFIG1_SHARED_MISC3_DEBUG_DISABLE_ENABLE_FVAL                                        0x0
#define HWIO_OEM_CONFIG1_SHARED_MISC3_DEBUG_DISABLE_DISABLE_FVAL                                       0x1
#define HWIO_OEM_CONFIG1_SHARED_MISC2_DEBUG_DISABLE_BMSK                                             0x400
#define HWIO_OEM_CONFIG1_SHARED_MISC2_DEBUG_DISABLE_SHFT                                               0xa
#define HWIO_OEM_CONFIG1_SHARED_MISC2_DEBUG_DISABLE_ENABLE_FVAL                                        0x0
#define HWIO_OEM_CONFIG1_SHARED_MISC2_DEBUG_DISABLE_DISABLE_FVAL                                       0x1
#define HWIO_OEM_CONFIG1_SHARED_MISC1_DEBUG_DISABLE_BMSK                                             0x200
#define HWIO_OEM_CONFIG1_SHARED_MISC1_DEBUG_DISABLE_SHFT                                               0x9
#define HWIO_OEM_CONFIG1_SHARED_MISC1_DEBUG_DISABLE_ENABLE_FVAL                                        0x0
#define HWIO_OEM_CONFIG1_SHARED_MISC1_DEBUG_DISABLE_DISABLE_FVAL                                       0x1
#define HWIO_OEM_CONFIG1_SHARED_MISC_DEBUG_DISABLE_BMSK                                              0x100
#define HWIO_OEM_CONFIG1_SHARED_MISC_DEBUG_DISABLE_SHFT                                                0x8
#define HWIO_OEM_CONFIG1_SHARED_MISC_DEBUG_DISABLE_ENABLE_FVAL                                         0x0
#define HWIO_OEM_CONFIG1_SHARED_MISC_DEBUG_DISABLE_DISABLE_FVAL                                        0x1
#define HWIO_OEM_CONFIG1_APPS_NIDEN_DISABLE_BMSK                                                      0x80
#define HWIO_OEM_CONFIG1_APPS_NIDEN_DISABLE_SHFT                                                       0x7
#define HWIO_OEM_CONFIG1_APPS_NIDEN_DISABLE_ENABLE_FVAL                                                0x0
#define HWIO_OEM_CONFIG1_APPS_NIDEN_DISABLE_DISABLE_FVAL                                               0x1
#define HWIO_OEM_CONFIG1_APPS_DBGEN_DISABLE_BMSK                                                      0x40
#define HWIO_OEM_CONFIG1_APPS_DBGEN_DISABLE_SHFT                                                       0x6
#define HWIO_OEM_CONFIG1_APPS_DBGEN_DISABLE_ENABLE_FVAL                                                0x0
#define HWIO_OEM_CONFIG1_APPS_DBGEN_DISABLE_DISABLE_FVAL                                               0x1
#define HWIO_OEM_CONFIG1_SHARED_NS_NIDEN_DISABLE_BMSK                                                 0x20
#define HWIO_OEM_CONFIG1_SHARED_NS_NIDEN_DISABLE_SHFT                                                  0x5
#define HWIO_OEM_CONFIG1_SHARED_NS_NIDEN_DISABLE_ENABLE_FVAL                                           0x0
#define HWIO_OEM_CONFIG1_SHARED_NS_NIDEN_DISABLE_DISABLE_FVAL                                          0x1
#define HWIO_OEM_CONFIG1_SHARED_NS_DBGEN_DISABLE_BMSK                                                 0x10
#define HWIO_OEM_CONFIG1_SHARED_NS_DBGEN_DISABLE_SHFT                                                  0x4
#define HWIO_OEM_CONFIG1_SHARED_NS_DBGEN_DISABLE_ENABLE_FVAL                                           0x0
#define HWIO_OEM_CONFIG1_SHARED_NS_DBGEN_DISABLE_DISABLE_FVAL                                          0x1
#define HWIO_OEM_CONFIG1_SHARED_CP_NIDEN_DISABLE_BMSK                                                  0x8
#define HWIO_OEM_CONFIG1_SHARED_CP_NIDEN_DISABLE_SHFT                                                  0x3
#define HWIO_OEM_CONFIG1_SHARED_CP_NIDEN_DISABLE_ENABLE_FVAL                                           0x0
#define HWIO_OEM_CONFIG1_SHARED_CP_NIDEN_DISABLE_DISABLE_FVAL                                          0x1
#define HWIO_OEM_CONFIG1_SHARED_CP_DBGEN_DISABLE_BMSK                                                  0x4
#define HWIO_OEM_CONFIG1_SHARED_CP_DBGEN_DISABLE_SHFT                                                  0x2
#define HWIO_OEM_CONFIG1_SHARED_CP_DBGEN_DISABLE_ENABLE_FVAL                                           0x0
#define HWIO_OEM_CONFIG1_SHARED_CP_DBGEN_DISABLE_DISABLE_FVAL                                          0x1
#define HWIO_OEM_CONFIG1_SHARED_MSS_NIDEN_DISABLE_BMSK                                                 0x2
#define HWIO_OEM_CONFIG1_SHARED_MSS_NIDEN_DISABLE_SHFT                                                 0x1
#define HWIO_OEM_CONFIG1_SHARED_MSS_NIDEN_DISABLE_ENABLE_FVAL                                          0x0
#define HWIO_OEM_CONFIG1_SHARED_MSS_NIDEN_DISABLE_DISABLE_FVAL                                         0x1
#define HWIO_OEM_CONFIG1_SHARED_MSS_DBGEN_DISABLE_BMSK                                                 0x1
#define HWIO_OEM_CONFIG1_SHARED_MSS_DBGEN_DISABLE_SHFT                                                 0x0
#define HWIO_OEM_CONFIG1_SHARED_MSS_DBGEN_DISABLE_ENABLE_FVAL                                          0x0
#define HWIO_OEM_CONFIG1_SHARED_MSS_DBGEN_DISABLE_DISABLE_FVAL                                         0x1

#define HWIO_OEM_CONFIG2_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000604c)
#define HWIO_OEM_CONFIG2_OFFS                                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000604c)
#define HWIO_OEM_CONFIG2_RMSK                                                                   0xffffffff
#define HWIO_OEM_CONFIG2_IN          \
        in_dword(HWIO_OEM_CONFIG2_ADDR)
#define HWIO_OEM_CONFIG2_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG2_ADDR, m)
#define HWIO_OEM_CONFIG2_DISABLE_RSA_BMSK                                                       0x80000000
#define HWIO_OEM_CONFIG2_DISABLE_RSA_SHFT                                                             0x1f
#define HWIO_OEM_CONFIG2_EKU_ENFORCEMENT_EN_BMSK                                                0x40000000
#define HWIO_OEM_CONFIG2_EKU_ENFORCEMENT_EN_SHFT                                                      0x1e
#define HWIO_OEM_CONFIG2_RSVD2_BMSK                                                             0x3fff0000
#define HWIO_OEM_CONFIG2_RSVD2_SHFT                                                                   0x10
#define HWIO_OEM_CONFIG2_SPARE_REG31_SECURE_BMSK                                                    0x8000
#define HWIO_OEM_CONFIG2_SPARE_REG31_SECURE_SHFT                                                       0xf
#define HWIO_OEM_CONFIG2_SPARE_REG31_SECURE_NOT_SECURE_FVAL                                            0x0
#define HWIO_OEM_CONFIG2_SPARE_REG31_SECURE_SECURE_FVAL                                                0x1
#define HWIO_OEM_CONFIG2_SPARE_REG30_SECURE_BMSK                                                    0x4000
#define HWIO_OEM_CONFIG2_SPARE_REG30_SECURE_SHFT                                                       0xe
#define HWIO_OEM_CONFIG2_SPARE_REG30_SECURE_NOT_SECURE_FVAL                                            0x0
#define HWIO_OEM_CONFIG2_SPARE_REG30_SECURE_SECURE_FVAL                                                0x1
#define HWIO_OEM_CONFIG2_SPARE_REG29_SECURE_BMSK                                                    0x2000
#define HWIO_OEM_CONFIG2_SPARE_REG29_SECURE_SHFT                                                       0xd
#define HWIO_OEM_CONFIG2_SPARE_REG29_SECURE_NOT_SECURE_FVAL                                            0x0
#define HWIO_OEM_CONFIG2_SPARE_REG29_SECURE_SECURE_FVAL                                                0x1
#define HWIO_OEM_CONFIG2_SPARE_REG28_SECURE_BMSK                                                    0x1000
#define HWIO_OEM_CONFIG2_SPARE_REG28_SECURE_SHFT                                                       0xc
#define HWIO_OEM_CONFIG2_SPARE_REG28_SECURE_NOT_SECURE_FVAL                                            0x0
#define HWIO_OEM_CONFIG2_SPARE_REG28_SECURE_SECURE_FVAL                                                0x1
#define HWIO_OEM_CONFIG2_RSVD3_BMSK                                                                  0x800
#define HWIO_OEM_CONFIG2_RSVD3_SHFT                                                                    0xb
#define HWIO_OEM_CONFIG2_SPU_IAR_ENABLED_BMSK                                                        0x400
#define HWIO_OEM_CONFIG2_SPU_IAR_ENABLED_SHFT                                                          0xa
#define HWIO_OEM_CONFIG2_RSVD1_BMSK                                                                  0x300
#define HWIO_OEM_CONFIG2_RSVD1_SHFT                                                                    0x8
#define HWIO_OEM_CONFIG2_TZ_SW_CRYPTO_FIPS_OVERRIDE_BMSK                                              0x80
#define HWIO_OEM_CONFIG2_TZ_SW_CRYPTO_FIPS_OVERRIDE_SHFT                                               0x7
#define HWIO_OEM_CONFIG2_SP_FIPS_OVERRIDE_BMSK                                                        0x40
#define HWIO_OEM_CONFIG2_SP_FIPS_OVERRIDE_SHFT                                                         0x6
#define HWIO_OEM_CONFIG2_MODEM_CRYPTO_FIPS_ENABLE_BMSK                                                0x20
#define HWIO_OEM_CONFIG2_MODEM_CRYPTO_FIPS_ENABLE_SHFT                                                 0x5
#define HWIO_OEM_CONFIG2_TZ_SW_CRYPTO_FIPS_ENABLE_BMSK                                                0x10
#define HWIO_OEM_CONFIG2_TZ_SW_CRYPTO_FIPS_ENABLE_SHFT                                                 0x4
#define HWIO_OEM_CONFIG2_SP_FIPS_ENABLE_BMSK                                                           0x8
#define HWIO_OEM_CONFIG2_SP_FIPS_ENABLE_SHFT                                                           0x3
#define HWIO_OEM_CONFIG2_SP_NVM_AR_CONFIG_BMSK                                                         0x6
#define HWIO_OEM_CONFIG2_SP_NVM_AR_CONFIG_SHFT                                                         0x1
#define HWIO_OEM_CONFIG2_RSVD0_BMSK                                                                    0x1
#define HWIO_OEM_CONFIG2_RSVD0_SHFT                                                                    0x0

#define HWIO_OEM_CONFIG3_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006050)
#define HWIO_OEM_CONFIG3_OFFS                                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006050)
#define HWIO_OEM_CONFIG3_RMSK                                                                   0xffffffff
#define HWIO_OEM_CONFIG3_IN          \
        in_dword(HWIO_OEM_CONFIG3_ADDR)
#define HWIO_OEM_CONFIG3_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG3_ADDR, m)
#define HWIO_OEM_CONFIG3_OEM_PRODUCT_ID_BMSK                                                    0xffff0000
#define HWIO_OEM_CONFIG3_OEM_PRODUCT_ID_SHFT                                                          0x10
#define HWIO_OEM_CONFIG3_OEM_HW_ID_BMSK                                                             0xffff
#define HWIO_OEM_CONFIG3_OEM_HW_ID_SHFT                                                                0x0

#define HWIO_OEM_CONFIG4_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006054)
#define HWIO_OEM_CONFIG4_OFFS                                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006054)
#define HWIO_OEM_CONFIG4_RMSK                                                                   0xffffffff
#define HWIO_OEM_CONFIG4_IN          \
        in_dword(HWIO_OEM_CONFIG4_ADDR)
#define HWIO_OEM_CONFIG4_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG4_ADDR, m)
#define HWIO_OEM_CONFIG4_PERIPH_VID_BMSK                                                        0xffff0000
#define HWIO_OEM_CONFIG4_PERIPH_VID_SHFT                                                              0x10
#define HWIO_OEM_CONFIG4_PERIPH_PID_BMSK                                                            0xffff
#define HWIO_OEM_CONFIG4_PERIPH_PID_SHFT                                                               0x0

#define HWIO_OEM_CONFIG5_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006058)
#define HWIO_OEM_CONFIG5_OFFS                                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006058)
#define HWIO_OEM_CONFIG5_RMSK                                                                   0xffffffff
#define HWIO_OEM_CONFIG5_IN          \
        in_dword(HWIO_OEM_CONFIG5_ADDR)
#define HWIO_OEM_CONFIG5_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG5_ADDR, m)
#define HWIO_OEM_CONFIG5_RSVD0_BMSK                                                             0xffffff00
#define HWIO_OEM_CONFIG5_RSVD0_SHFT                                                                    0x8
#define HWIO_OEM_CONFIG5_ANTI_ROLLBACK_FEATURE_EN_BMSK                                                0xff
#define HWIO_OEM_CONFIG5_ANTI_ROLLBACK_FEATURE_EN_SHFT                                                 0x0

#define HWIO_BOOT_CONFIG_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006070)
#define HWIO_BOOT_CONFIG_OFFS                                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006070)
#define HWIO_BOOT_CONFIG_RMSK                                                                        0x1ff
#define HWIO_BOOT_CONFIG_IN          \
        in_dword(HWIO_BOOT_CONFIG_ADDR)
#define HWIO_BOOT_CONFIG_INM(m)      \
        in_dword_masked(HWIO_BOOT_CONFIG_ADDR, m)
#define HWIO_BOOT_CONFIG_APPS_PBL_BOOT_SPEED_BMSK                                                    0x180
#define HWIO_BOOT_CONFIG_APPS_PBL_BOOT_SPEED_SHFT                                                      0x7
#define HWIO_BOOT_CONFIG_APPS_PBL_BOOT_SPEED_ENUM_600_MHZ_FVAL                                         0x0
#define HWIO_BOOT_CONFIG_APPS_PBL_BOOT_SPEED_ENUM_300_MHZ_FVAL                                         0x1
#define HWIO_BOOT_CONFIG_APPS_PBL_BOOT_SPEED_CXO_FVAL                                                  0x2
#define HWIO_BOOT_CONFIG_APPS_PBL_BOOT_SPEED_NA_FVAL                                                   0x3
#define HWIO_BOOT_CONFIG_APPS_BOOT_FROM_ROM_BMSK                                                      0x40
#define HWIO_BOOT_CONFIG_APPS_BOOT_FROM_ROM_SHFT                                                       0x6
#define HWIO_BOOT_CONFIG_FAST_BOOT_BMSK                                                               0x3e
#define HWIO_BOOT_CONFIG_FAST_BOOT_SHFT                                                                0x1
#define HWIO_BOOT_CONFIG_FAST_BOOT_DEFAULT_FVAL                                                        0x0
#define HWIO_BOOT_CONFIG_FAST_BOOT_PCIE_FVAL                                                           0x1
#define HWIO_BOOT_CONFIG_FAST_BOOT_USB_FVAL                                                            0x2
#define HWIO_BOOT_CONFIG_FAST_BOOT_EMMC_USB_FVAL                                                       0x3
#define HWIO_BOOT_CONFIG_WDOG_EN_BMSK                                                                  0x1
#define HWIO_BOOT_CONFIG_WDOG_EN_SHFT                                                                  0x0
#define HWIO_BOOT_CONFIG_WDOG_EN_GPIO_CONTROLLED_FVAL                                                  0x0
#define HWIO_BOOT_CONFIG_WDOG_EN_ENABLE_WDOG_FVAL                                                      0x1

#define HWIO_SECURE_BOOTn_ADDR(n)                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006078 + 0x4 * (n))
#define HWIO_SECURE_BOOTn_OFFS(n)                                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006078 + 0x4 * (n))
#define HWIO_SECURE_BOOTn_RMSK                                                                       0x1ff
#define HWIO_SECURE_BOOTn_MAXn                                                                          14
#define HWIO_SECURE_BOOTn_INI(n)        \
        in_dword_masked(HWIO_SECURE_BOOTn_ADDR(n), HWIO_SECURE_BOOTn_RMSK)
#define HWIO_SECURE_BOOTn_INMI(n,mask)    \
        in_dword_masked(HWIO_SECURE_BOOTn_ADDR(n), mask)
#define HWIO_SECURE_BOOTn_FUSE_SRC_BMSK                                                              0x100
#define HWIO_SECURE_BOOTn_FUSE_SRC_SHFT                                                                0x8
#define HWIO_SECURE_BOOTn_FUSE_SRC_QUALCOMM_FVAL                                                       0x0
#define HWIO_SECURE_BOOTn_FUSE_SRC_OEM_FVAL                                                            0x1
#define HWIO_SECURE_BOOTn_RSVD_7_BMSK                                                                 0x80
#define HWIO_SECURE_BOOTn_RSVD_7_SHFT                                                                  0x7
#define HWIO_SECURE_BOOTn_USE_SERIAL_NUM_BMSK                                                         0x40
#define HWIO_SECURE_BOOTn_USE_SERIAL_NUM_SHFT                                                          0x6
#define HWIO_SECURE_BOOTn_USE_SERIAL_NUM_USE_OEM_ID_FVAL                                               0x0
#define HWIO_SECURE_BOOTn_USE_SERIAL_NUM_USE_SERIAL_NUM_FVAL                                           0x1
#define HWIO_SECURE_BOOTn_AUTH_EN_BMSK                                                                0x20
#define HWIO_SECURE_BOOTn_AUTH_EN_SHFT                                                                 0x5
#define HWIO_SECURE_BOOTn_PK_HASH_IN_FUSE_BMSK                                                        0x10
#define HWIO_SECURE_BOOTn_PK_HASH_IN_FUSE_SHFT                                                         0x4
#define HWIO_SECURE_BOOTn_PK_HASH_IN_FUSE_SHA_256_HASH_OF_ROOT_CERTIFICATE_IS_IN_ROM_FVAL              0x0
#define HWIO_SECURE_BOOTn_PK_HASH_IN_FUSE_SHA_256_HASH_OF_ROOT_CERTIFICATE_IS_IN_PK_HASH_FVAL          0x1
#define HWIO_SECURE_BOOTn_ROM_PK_HASH_INDEX_BMSK                                                       0xf
#define HWIO_SECURE_BOOTn_ROM_PK_HASH_INDEX_SHFT                                                       0x0

#define HWIO_QSEE_INV_OVERRIDE_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060c0)
#define HWIO_QSEE_INV_OVERRIDE_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060c0)
#define HWIO_QSEE_INV_OVERRIDE_RMSK                                                             0xffffffff
#define HWIO_QSEE_INV_OVERRIDE_IN          \
        in_dword(HWIO_QSEE_INV_OVERRIDE_ADDR)
#define HWIO_QSEE_INV_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_QSEE_INV_OVERRIDE_ADDR, m)
#define HWIO_QSEE_INV_OVERRIDE_OUT(v)      \
        out_dword(HWIO_QSEE_INV_OVERRIDE_ADDR,v)
#define HWIO_QSEE_INV_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QSEE_INV_OVERRIDE_ADDR,m,v,HWIO_QSEE_INV_OVERRIDE_IN)
#define HWIO_QSEE_INV_OVERRIDE_RSVD_31_1_BMSK                                                   0xfffffffe
#define HWIO_QSEE_INV_OVERRIDE_RSVD_31_1_SHFT                                                          0x1
#define HWIO_QSEE_INV_OVERRIDE_SHARED_QSEE_SPIDEN_DISABLE_BMSK                                         0x1
#define HWIO_QSEE_INV_OVERRIDE_SHARED_QSEE_SPIDEN_DISABLE_SHFT                                         0x0
#define HWIO_QSEE_INV_OVERRIDE_SHARED_QSEE_SPIDEN_DISABLE_FUSE_VALUE_FVAL                              0x0
#define HWIO_QSEE_INV_OVERRIDE_SHARED_QSEE_SPIDEN_DISABLE_QC_FUSE_VALUE_FVAL                           0x1

#define HWIO_QSEE_NI_OVERRIDE_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060c4)
#define HWIO_QSEE_NI_OVERRIDE_OFFS                                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060c4)
#define HWIO_QSEE_NI_OVERRIDE_RMSK                                                              0xffffffff
#define HWIO_QSEE_NI_OVERRIDE_IN          \
        in_dword(HWIO_QSEE_NI_OVERRIDE_ADDR)
#define HWIO_QSEE_NI_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_QSEE_NI_OVERRIDE_ADDR, m)
#define HWIO_QSEE_NI_OVERRIDE_OUT(v)      \
        out_dword(HWIO_QSEE_NI_OVERRIDE_ADDR,v)
#define HWIO_QSEE_NI_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QSEE_NI_OVERRIDE_ADDR,m,v,HWIO_QSEE_NI_OVERRIDE_IN)
#define HWIO_QSEE_NI_OVERRIDE_RSVD_31_1_BMSK                                                    0xfffffffe
#define HWIO_QSEE_NI_OVERRIDE_RSVD_31_1_SHFT                                                           0x1
#define HWIO_QSEE_NI_OVERRIDE_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                                         0x1
#define HWIO_QSEE_NI_OVERRIDE_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                                         0x0
#define HWIO_QSEE_NI_OVERRIDE_SHARED_QSEE_SPNIDEN_DISABLE_FUSE_VALUE_FVAL                              0x0
#define HWIO_QSEE_NI_OVERRIDE_SHARED_QSEE_SPNIDEN_DISABLE_QC_FUSE_VALUE_FVAL                           0x1

#define HWIO_MSS_INV_OVERRIDE_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060c8)
#define HWIO_MSS_INV_OVERRIDE_OFFS                                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060c8)
#define HWIO_MSS_INV_OVERRIDE_RMSK                                                              0xffffffff
#define HWIO_MSS_INV_OVERRIDE_IN          \
        in_dword(HWIO_MSS_INV_OVERRIDE_ADDR)
#define HWIO_MSS_INV_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_MSS_INV_OVERRIDE_ADDR, m)
#define HWIO_MSS_INV_OVERRIDE_OUT(v)      \
        out_dword(HWIO_MSS_INV_OVERRIDE_ADDR,v)
#define HWIO_MSS_INV_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MSS_INV_OVERRIDE_ADDR,m,v,HWIO_MSS_INV_OVERRIDE_IN)
#define HWIO_MSS_INV_OVERRIDE_RSVD_31_1_BMSK                                                    0xfffffffe
#define HWIO_MSS_INV_OVERRIDE_RSVD_31_1_SHFT                                                           0x1
#define HWIO_MSS_INV_OVERRIDE_SHARED_MSS_DBGEN_DISABLE_BMSK                                            0x1
#define HWIO_MSS_INV_OVERRIDE_SHARED_MSS_DBGEN_DISABLE_SHFT                                            0x0
#define HWIO_MSS_INV_OVERRIDE_SHARED_MSS_DBGEN_DISABLE_FUSE_VALUE_FVAL                                 0x0
#define HWIO_MSS_INV_OVERRIDE_SHARED_MSS_DBGEN_DISABLE_QC_FUSE_VALUE_FVAL                              0x1

#define HWIO_MSS_NI_OVERRIDE_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060cc)
#define HWIO_MSS_NI_OVERRIDE_OFFS                                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060cc)
#define HWIO_MSS_NI_OVERRIDE_RMSK                                                               0xffffffff
#define HWIO_MSS_NI_OVERRIDE_IN          \
        in_dword(HWIO_MSS_NI_OVERRIDE_ADDR)
#define HWIO_MSS_NI_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_MSS_NI_OVERRIDE_ADDR, m)
#define HWIO_MSS_NI_OVERRIDE_OUT(v)      \
        out_dword(HWIO_MSS_NI_OVERRIDE_ADDR,v)
#define HWIO_MSS_NI_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MSS_NI_OVERRIDE_ADDR,m,v,HWIO_MSS_NI_OVERRIDE_IN)
#define HWIO_MSS_NI_OVERRIDE_RSVD_31_1_BMSK                                                     0xfffffffe
#define HWIO_MSS_NI_OVERRIDE_RSVD_31_1_SHFT                                                            0x1
#define HWIO_MSS_NI_OVERRIDE_SHARED_MSS_NIDEN_DISABLE_BMSK                                             0x1
#define HWIO_MSS_NI_OVERRIDE_SHARED_MSS_NIDEN_DISABLE_SHFT                                             0x0
#define HWIO_MSS_NI_OVERRIDE_SHARED_MSS_NIDEN_DISABLE_FUSE_VALUE_FVAL                                  0x0
#define HWIO_MSS_NI_OVERRIDE_SHARED_MSS_NIDEN_DISABLE_QC_FUSE_VALUE_FVAL                               0x1

#define HWIO_CP_INV_OVERRIDE_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060d0)
#define HWIO_CP_INV_OVERRIDE_OFFS                                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060d0)
#define HWIO_CP_INV_OVERRIDE_RMSK                                                               0xffffffff
#define HWIO_CP_INV_OVERRIDE_IN          \
        in_dword(HWIO_CP_INV_OVERRIDE_ADDR)
#define HWIO_CP_INV_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_CP_INV_OVERRIDE_ADDR, m)
#define HWIO_CP_INV_OVERRIDE_OUT(v)      \
        out_dword(HWIO_CP_INV_OVERRIDE_ADDR,v)
#define HWIO_CP_INV_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CP_INV_OVERRIDE_ADDR,m,v,HWIO_CP_INV_OVERRIDE_IN)
#define HWIO_CP_INV_OVERRIDE_RSVD_31_1_BMSK                                                     0xfffffffe
#define HWIO_CP_INV_OVERRIDE_RSVD_31_1_SHFT                                                            0x1
#define HWIO_CP_INV_OVERRIDE_SHARED_CP_DBGEN_DISABLE_BMSK                                              0x1
#define HWIO_CP_INV_OVERRIDE_SHARED_CP_DBGEN_DISABLE_SHFT                                              0x0
#define HWIO_CP_INV_OVERRIDE_SHARED_CP_DBGEN_DISABLE_FUSE_VALUE_FVAL                                   0x0
#define HWIO_CP_INV_OVERRIDE_SHARED_CP_DBGEN_DISABLE_QC_FUSE_VALUE_FVAL                                0x1

#define HWIO_CP_NI_OVERRIDE_ADDR                                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060d4)
#define HWIO_CP_NI_OVERRIDE_OFFS                                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060d4)
#define HWIO_CP_NI_OVERRIDE_RMSK                                                                0xffffffff
#define HWIO_CP_NI_OVERRIDE_IN          \
        in_dword(HWIO_CP_NI_OVERRIDE_ADDR)
#define HWIO_CP_NI_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_CP_NI_OVERRIDE_ADDR, m)
#define HWIO_CP_NI_OVERRIDE_OUT(v)      \
        out_dword(HWIO_CP_NI_OVERRIDE_ADDR,v)
#define HWIO_CP_NI_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CP_NI_OVERRIDE_ADDR,m,v,HWIO_CP_NI_OVERRIDE_IN)
#define HWIO_CP_NI_OVERRIDE_RSVD_31_1_BMSK                                                      0xfffffffe
#define HWIO_CP_NI_OVERRIDE_RSVD_31_1_SHFT                                                             0x1
#define HWIO_CP_NI_OVERRIDE_SHARED_CP_NIDEN_DISABLE_BMSK                                               0x1
#define HWIO_CP_NI_OVERRIDE_SHARED_CP_NIDEN_DISABLE_SHFT                                               0x0
#define HWIO_CP_NI_OVERRIDE_SHARED_CP_NIDEN_DISABLE_FUSE_VALUE_FVAL                                    0x0
#define HWIO_CP_NI_OVERRIDE_SHARED_CP_NIDEN_DISABLE_QC_FUSE_VALUE_FVAL                                 0x1

#define HWIO_NS_INV_OVERRIDE_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060d8)
#define HWIO_NS_INV_OVERRIDE_OFFS                                                               (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060d8)
#define HWIO_NS_INV_OVERRIDE_RMSK                                                               0xffffffff
#define HWIO_NS_INV_OVERRIDE_IN          \
        in_dword(HWIO_NS_INV_OVERRIDE_ADDR)
#define HWIO_NS_INV_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_NS_INV_OVERRIDE_ADDR, m)
#define HWIO_NS_INV_OVERRIDE_OUT(v)      \
        out_dword(HWIO_NS_INV_OVERRIDE_ADDR,v)
#define HWIO_NS_INV_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_NS_INV_OVERRIDE_ADDR,m,v,HWIO_NS_INV_OVERRIDE_IN)
#define HWIO_NS_INV_OVERRIDE_RSVD_31_5_BMSK                                                     0xffffffe0
#define HWIO_NS_INV_OVERRIDE_RSVD_31_5_SHFT                                                            0x5
#define HWIO_NS_INV_OVERRIDE_APPS_DBGEN_DISABLE_BMSK                                                  0x10
#define HWIO_NS_INV_OVERRIDE_APPS_DBGEN_DISABLE_SHFT                                                   0x4
#define HWIO_NS_INV_OVERRIDE_APPS_DBGEN_DISABLE_FUSE_VALUE_FVAL                                        0x0
#define HWIO_NS_INV_OVERRIDE_APPS_DBGEN_DISABLE_QC_FUSE_VALUE_FVAL                                     0x1
#define HWIO_NS_INV_OVERRIDE_RSVD_3_1_BMSK                                                             0xe
#define HWIO_NS_INV_OVERRIDE_RSVD_3_1_SHFT                                                             0x1
#define HWIO_NS_INV_OVERRIDE_SHARED_NS_DBGEN_DISABLE_BMSK                                              0x1
#define HWIO_NS_INV_OVERRIDE_SHARED_NS_DBGEN_DISABLE_SHFT                                              0x0
#define HWIO_NS_INV_OVERRIDE_SHARED_NS_DBGEN_DISABLE_FUSE_VALUE_FVAL                                   0x0
#define HWIO_NS_INV_OVERRIDE_SHARED_NS_DBGEN_DISABLE_QC_FUSE_VALUE_FVAL                                0x1

#define HWIO_NS_NI_OVERRIDE_ADDR                                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060dc)
#define HWIO_NS_NI_OVERRIDE_OFFS                                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060dc)
#define HWIO_NS_NI_OVERRIDE_RMSK                                                                0xffffffff
#define HWIO_NS_NI_OVERRIDE_IN          \
        in_dword(HWIO_NS_NI_OVERRIDE_ADDR)
#define HWIO_NS_NI_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_NS_NI_OVERRIDE_ADDR, m)
#define HWIO_NS_NI_OVERRIDE_OUT(v)      \
        out_dword(HWIO_NS_NI_OVERRIDE_ADDR,v)
#define HWIO_NS_NI_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_NS_NI_OVERRIDE_ADDR,m,v,HWIO_NS_NI_OVERRIDE_IN)
#define HWIO_NS_NI_OVERRIDE_RSVD_31_5_BMSK                                                      0xffffffe0
#define HWIO_NS_NI_OVERRIDE_RSVD_31_5_SHFT                                                             0x5
#define HWIO_NS_NI_OVERRIDE_APPS_NIDEN_DISABLE_BMSK                                                   0x10
#define HWIO_NS_NI_OVERRIDE_APPS_NIDEN_DISABLE_SHFT                                                    0x4
#define HWIO_NS_NI_OVERRIDE_APPS_NIDEN_DISABLE_FUSE_VALUE_FVAL                                         0x0
#define HWIO_NS_NI_OVERRIDE_APPS_NIDEN_DISABLE_QC_FUSE_VALUE_FVAL                                      0x1
#define HWIO_NS_NI_OVERRIDE_RSVD_3_1_BMSK                                                              0xe
#define HWIO_NS_NI_OVERRIDE_RSVD_3_1_SHFT                                                              0x1
#define HWIO_NS_NI_OVERRIDE_SHARED_NS_NIDEN_DISABLE_BMSK                                               0x1
#define HWIO_NS_NI_OVERRIDE_SHARED_NS_NIDEN_DISABLE_SHFT                                               0x0
#define HWIO_NS_NI_OVERRIDE_SHARED_NS_NIDEN_DISABLE_FUSE_VALUE_FVAL                                    0x0
#define HWIO_NS_NI_OVERRIDE_SHARED_NS_NIDEN_DISABLE_QC_FUSE_VALUE_FVAL                                 0x1

#define HWIO_MISC_DEBUG_OVERRIDE_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060e0)
#define HWIO_MISC_DEBUG_OVERRIDE_OFFS                                                           (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060e0)
#define HWIO_MISC_DEBUG_OVERRIDE_RMSK                                                           0xffffffff
#define HWIO_MISC_DEBUG_OVERRIDE_IN          \
        in_dword(HWIO_MISC_DEBUG_OVERRIDE_ADDR)
#define HWIO_MISC_DEBUG_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_MISC_DEBUG_OVERRIDE_ADDR, m)
#define HWIO_MISC_DEBUG_OVERRIDE_OUT(v)      \
        out_dword(HWIO_MISC_DEBUG_OVERRIDE_ADDR,v)
#define HWIO_MISC_DEBUG_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MISC_DEBUG_OVERRIDE_ADDR,m,v,HWIO_MISC_DEBUG_OVERRIDE_IN)
#define HWIO_MISC_DEBUG_OVERRIDE_RSVD_31_6_BMSK                                                 0xffffffc0
#define HWIO_MISC_DEBUG_OVERRIDE_RSVD_31_6_SHFT                                                        0x6
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC5_DEBUG_DISABLE_BMSK                                      0x20
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC5_DEBUG_DISABLE_SHFT                                       0x5
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC5_DEBUG_DISABLE_FUSE_VALUE_FVAL                            0x0
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC5_DEBUG_DISABLE_ZERO_FVAL                                  0x1
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC4_DEBUG_DISABLE_BMSK                                      0x10
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC4_DEBUG_DISABLE_SHFT                                       0x4
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC4_DEBUG_DISABLE_FUSE_VALUE_FVAL                            0x0
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC4_DEBUG_DISABLE_ZERO_FVAL                                  0x1
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC3_DEBUG_DISABLE_BMSK                                       0x8
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC3_DEBUG_DISABLE_SHFT                                       0x3
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC3_DEBUG_DISABLE_FUSE_VALUE_FVAL                            0x0
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC3_DEBUG_DISABLE_ZERO_FVAL                                  0x1
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC2_DEBUG_DISABLE_BMSK                                       0x4
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC2_DEBUG_DISABLE_SHFT                                       0x2
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC2_DEBUG_DISABLE_FUSE_VALUE_FVAL                            0x0
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC2_DEBUG_DISABLE_ZERO_FVAL                                  0x1
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC1_DEBUG_DISABLE_BMSK                                       0x2
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC1_DEBUG_DISABLE_SHFT                                       0x1
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC1_DEBUG_DISABLE_FUSE_VALUE_FVAL                            0x0
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC1_DEBUG_DISABLE_ZERO_FVAL                                  0x1
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC_DEBUG_DISABLE_BMSK                                        0x1
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC_DEBUG_DISABLE_SHFT                                        0x0
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC_DEBUG_DISABLE_FUSE_VALUE_FVAL                             0x0
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC_DEBUG_DISABLE_QC_FUSE_VALUE_FVAL                          0x1

#define HWIO_CAPT_SEC_GPIO_ADDR                                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006100)
#define HWIO_CAPT_SEC_GPIO_OFFS                                                                 (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006100)
#define HWIO_CAPT_SEC_GPIO_RMSK                                                                     0x1fff
#define HWIO_CAPT_SEC_GPIO_IN          \
        in_dword(HWIO_CAPT_SEC_GPIO_ADDR)
#define HWIO_CAPT_SEC_GPIO_INM(m)      \
        in_dword_masked(HWIO_CAPT_SEC_GPIO_ADDR, m)
#define HWIO_CAPT_SEC_GPIO_OUT(v)      \
        out_dword(HWIO_CAPT_SEC_GPIO_ADDR,v)
#define HWIO_CAPT_SEC_GPIO_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CAPT_SEC_GPIO_ADDR,m,v,HWIO_CAPT_SEC_GPIO_IN)
#define HWIO_CAPT_SEC_GPIO_FORCE_USB_BOOT_GPIO_BMSK                                                 0x1000
#define HWIO_CAPT_SEC_GPIO_FORCE_USB_BOOT_GPIO_SHFT                                                    0xc
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_AP_AUTH_EN_BMSK                                          0x800
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_AP_AUTH_EN_SHFT                                            0xb
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_AP_PK_HASH_IN_FUSE_BMSK                                  0x400
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_AP_PK_HASH_IN_FUSE_SHFT                                    0xa
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_ALL_USE_SERIAL_NUM_BMSK                                  0x200
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_ALL_USE_SERIAL_NUM_SHFT                                    0x9
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_PK_HASH_INDEX_SRC_BMSK                                   0x100
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_PK_HASH_INDEX_SRC_SHFT                                     0x8
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_APPS_PBL_BOOT_SPEED_BMSK                                  0xc0
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_APPS_PBL_BOOT_SPEED_SHFT                                   0x6
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_APPS_BOOT_FROM_ROM_BMSK                                   0x20
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_APPS_BOOT_FROM_ROM_SHFT                                    0x5
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_FAST_BOOT_BMSK                                            0x1e
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_FAST_BOOT_SHFT                                             0x1
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_WDOG_DISABLE_BMSK                                          0x1
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_WDOG_DISABLE_SHFT                                          0x0

#define HWIO_APP_PROC_CFG_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006110)
#define HWIO_APP_PROC_CFG_OFFS                                                                  (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006110)
#define HWIO_APP_PROC_CFG_RMSK                                                                     0xfffff
#define HWIO_APP_PROC_CFG_IN          \
        in_dword(HWIO_APP_PROC_CFG_ADDR)
#define HWIO_APP_PROC_CFG_INM(m)      \
        in_dword_masked(HWIO_APP_PROC_CFG_ADDR, m)
#define HWIO_APP_PROC_CFG_OUT(v)      \
        out_dword(HWIO_APP_PROC_CFG_ADDR,v)
#define HWIO_APP_PROC_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_APP_PROC_CFG_ADDR,m,v,HWIO_APP_PROC_CFG_IN)
#define HWIO_APP_PROC_CFG_SPARE0_BMSK                                                              0xc0000
#define HWIO_APP_PROC_CFG_SPARE0_SHFT                                                                 0x12
#define HWIO_APP_PROC_CFG_SPARE1_BMSK                                                              0x30000
#define HWIO_APP_PROC_CFG_SPARE1_SHFT                                                                 0x10
#define HWIO_APP_PROC_CFG_APPS_CFG_MISC2_BMSK                                                       0xf000
#define HWIO_APP_PROC_CFG_APPS_CFG_MISC2_SHFT                                                          0xc
#define HWIO_APP_PROC_CFG_APPS_CFG_MISC1_BMSK                                                        0xf00
#define HWIO_APP_PROC_CFG_APPS_CFG_MISC1_SHFT                                                          0x8
#define HWIO_APP_PROC_CFG_APPS_CFG_MISC0_BMSK                                                         0xc0
#define HWIO_APP_PROC_CFG_APPS_CFG_MISC0_SHFT                                                          0x6
#define HWIO_APP_PROC_CFG_APPS_CP15_DISABLE_BMSK                                                      0x20
#define HWIO_APP_PROC_CFG_APPS_CP15_DISABLE_SHFT                                                       0x5
#define HWIO_APP_PROC_CFG_APPS_CFG_NMFI_BMSK                                                          0x10
#define HWIO_APP_PROC_CFG_APPS_CFG_NMFI_SHFT                                                           0x4
#define HWIO_APP_PROC_CFG_APPS_CFG_NMFI_NORMAL_FVAL                                                    0x0
#define HWIO_APP_PROC_CFG_APPS_CFG_NMFI_DISABLE_FVAL                                                   0x1
#define HWIO_APP_PROC_CFG_SHARED_QSEE_SPNIDEN_BMSK                                                     0x8
#define HWIO_APP_PROC_CFG_SHARED_QSEE_SPNIDEN_SHFT                                                     0x3
#define HWIO_APP_PROC_CFG_SHARED_CP_NIDEN_BMSK                                                         0x4
#define HWIO_APP_PROC_CFG_SHARED_CP_NIDEN_SHFT                                                         0x2
#define HWIO_APP_PROC_CFG_SHARED_NS_NIDEN_BMSK                                                         0x2
#define HWIO_APP_PROC_CFG_SHARED_NS_NIDEN_SHFT                                                         0x1
#define HWIO_APP_PROC_CFG_APPS_NIDEN_BMSK                                                              0x1
#define HWIO_APP_PROC_CFG_APPS_NIDEN_SHFT                                                              0x0

#define HWIO_MSS_PROC_CFG_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006114)
#define HWIO_MSS_PROC_CFG_OFFS                                                                  (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006114)
#define HWIO_MSS_PROC_CFG_RMSK                                                                         0x1
#define HWIO_MSS_PROC_CFG_IN          \
        in_dword(HWIO_MSS_PROC_CFG_ADDR)
#define HWIO_MSS_PROC_CFG_INM(m)      \
        in_dword_masked(HWIO_MSS_PROC_CFG_ADDR, m)
#define HWIO_MSS_PROC_CFG_OUT(v)      \
        out_dword(HWIO_MSS_PROC_CFG_ADDR,v)
#define HWIO_MSS_PROC_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MSS_PROC_CFG_ADDR,m,v,HWIO_MSS_PROC_CFG_IN)
#define HWIO_MSS_PROC_CFG_SHARED_MSS_NIDEN_BMSK                                                        0x1
#define HWIO_MSS_PROC_CFG_SHARED_MSS_NIDEN_SHFT                                                        0x0

#define HWIO_QFPROM_CLK_CTL_ADDR                                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006118)
#define HWIO_QFPROM_CLK_CTL_OFFS                                                                (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006118)
#define HWIO_QFPROM_CLK_CTL_RMSK                                                                       0x1
#define HWIO_QFPROM_CLK_CTL_IN          \
        in_dword(HWIO_QFPROM_CLK_CTL_ADDR)
#define HWIO_QFPROM_CLK_CTL_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CLK_CTL_ADDR, m)
#define HWIO_QFPROM_CLK_CTL_OUT(v)      \
        out_dword(HWIO_QFPROM_CLK_CTL_ADDR,v)
#define HWIO_QFPROM_CLK_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_CLK_CTL_ADDR,m,v,HWIO_QFPROM_CLK_CTL_IN)
#define HWIO_QFPROM_CLK_CTL_CLK_HALT_BMSK                                                              0x1
#define HWIO_QFPROM_CLK_CTL_CLK_HALT_SHFT                                                              0x0
#define HWIO_QFPROM_CLK_CTL_CLK_HALT_CLK_ENABLED_FVAL                                                  0x0
#define HWIO_QFPROM_CLK_CTL_CLK_HALT_CLK_DISABLED_FVAL                                                 0x1

#define HWIO_JTAG_ID_ADDR                                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006130)
#define HWIO_JTAG_ID_OFFS                                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006130)
#define HWIO_JTAG_ID_RMSK                                                                       0xffffffff
#define HWIO_JTAG_ID_IN          \
        in_dword(HWIO_JTAG_ID_ADDR)
#define HWIO_JTAG_ID_INM(m)      \
        in_dword_masked(HWIO_JTAG_ID_ADDR, m)
#define HWIO_JTAG_ID_JTAG_ID_BMSK                                                               0xffffffff
#define HWIO_JTAG_ID_JTAG_ID_SHFT                                                                      0x0

#define HWIO_SERIAL_NUM_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006134)
#define HWIO_SERIAL_NUM_OFFS                                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006134)
#define HWIO_SERIAL_NUM_RMSK                                                                    0xffffffff
#define HWIO_SERIAL_NUM_IN          \
        in_dword(HWIO_SERIAL_NUM_ADDR)
#define HWIO_SERIAL_NUM_INM(m)      \
        in_dword_masked(HWIO_SERIAL_NUM_ADDR, m)
#define HWIO_SERIAL_NUM_SERIAL_NUM_BMSK                                                         0xffffffff
#define HWIO_SERIAL_NUM_SERIAL_NUM_SHFT                                                                0x0

#define HWIO_OEM_ID_ADDR                                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006138)
#define HWIO_OEM_ID_OFFS                                                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006138)
#define HWIO_OEM_ID_RMSK                                                                        0xffffffff
#define HWIO_OEM_ID_IN          \
        in_dword(HWIO_OEM_ID_ADDR)
#define HWIO_OEM_ID_INM(m)      \
        in_dword_masked(HWIO_OEM_ID_ADDR, m)
#define HWIO_OEM_ID_OEM_ID_BMSK                                                                 0xffff0000
#define HWIO_OEM_ID_OEM_ID_SHFT                                                                       0x10
#define HWIO_OEM_ID_OEM_PRODUCT_ID_BMSK                                                             0xffff
#define HWIO_OEM_ID_OEM_PRODUCT_ID_SHFT                                                                0x0

#define HWIO_TEST_BUS_SEL_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000613c)
#define HWIO_TEST_BUS_SEL_OFFS                                                                  (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000613c)
#define HWIO_TEST_BUS_SEL_RMSK                                                                         0x7
#define HWIO_TEST_BUS_SEL_IN          \
        in_dword(HWIO_TEST_BUS_SEL_ADDR)
#define HWIO_TEST_BUS_SEL_INM(m)      \
        in_dword_masked(HWIO_TEST_BUS_SEL_ADDR, m)
#define HWIO_TEST_BUS_SEL_OUT(v)      \
        out_dword(HWIO_TEST_BUS_SEL_ADDR,v)
#define HWIO_TEST_BUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TEST_BUS_SEL_ADDR,m,v,HWIO_TEST_BUS_SEL_IN)
#define HWIO_TEST_BUS_SEL_TEST_EN_BMSK                                                                 0x4
#define HWIO_TEST_BUS_SEL_TEST_EN_SHFT                                                                 0x2
#define HWIO_TEST_BUS_SEL_TEST_EN_DEBUG_DISABLED_FVAL                                                  0x0
#define HWIO_TEST_BUS_SEL_TEST_EN_DEBUG_ENABLED_FVAL                                                   0x1
#define HWIO_TEST_BUS_SEL_TEST_SELECT_BMSK                                                             0x3
#define HWIO_TEST_BUS_SEL_TEST_SELECT_SHFT                                                             0x0
#define HWIO_TEST_BUS_SEL_TEST_SELECT_FUSE_SENSE_FVAL                                                  0x0
#define HWIO_TEST_BUS_SEL_TEST_SELECT_QFPROM_ARBITER_FVAL                                              0x1
#define HWIO_TEST_BUS_SEL_TEST_SELECT_SW_FVAL                                                          0x2
#define HWIO_TEST_BUS_SEL_TEST_SELECT_ACC_FVAL                                                         0x3

#define HWIO_SPDM_DYN_SECURE_MODE_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006140)
#define HWIO_SPDM_DYN_SECURE_MODE_OFFS                                                          (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006140)
#define HWIO_SPDM_DYN_SECURE_MODE_RMSK                                                                 0x1
#define HWIO_SPDM_DYN_SECURE_MODE_IN          \
        in_dword(HWIO_SPDM_DYN_SECURE_MODE_ADDR)
#define HWIO_SPDM_DYN_SECURE_MODE_INM(m)      \
        in_dword_masked(HWIO_SPDM_DYN_SECURE_MODE_ADDR, m)
#define HWIO_SPDM_DYN_SECURE_MODE_OUT(v)      \
        out_dword(HWIO_SPDM_DYN_SECURE_MODE_ADDR,v)
#define HWIO_SPDM_DYN_SECURE_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SPDM_DYN_SECURE_MODE_ADDR,m,v,HWIO_SPDM_DYN_SECURE_MODE_IN)
#define HWIO_SPDM_DYN_SECURE_MODE_SECURE_MODE_BMSK                                                     0x1
#define HWIO_SPDM_DYN_SECURE_MODE_SECURE_MODE_SHFT                                                     0x0
#define HWIO_SPDM_DYN_SECURE_MODE_SECURE_MODE_DISABLE_FVAL                                             0x0
#define HWIO_SPDM_DYN_SECURE_MODE_SECURE_MODE_ENABLE_FVAL                                              0x1

#define HWIO_CHIP_ID_ADDR                                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006144)
#define HWIO_CHIP_ID_OFFS                                                                       (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006144)
#define HWIO_CHIP_ID_RMSK                                                                           0xffff
#define HWIO_CHIP_ID_IN          \
        in_dword(HWIO_CHIP_ID_ADDR)
#define HWIO_CHIP_ID_INM(m)      \
        in_dword_masked(HWIO_CHIP_ID_ADDR, m)
#define HWIO_CHIP_ID_CHIP_ID_BMSK                                                                   0xffff
#define HWIO_CHIP_ID_CHIP_ID_SHFT                                                                      0x0

#define HWIO_OEM_IMAGE_ENCR_KEYn_ADDR(n)                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006150 + 0x4 * (n))
#define HWIO_OEM_IMAGE_ENCR_KEYn_OFFS(n)                                                        (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006150 + 0x4 * (n))
#define HWIO_OEM_IMAGE_ENCR_KEYn_RMSK                                                           0xffffffff
#define HWIO_OEM_IMAGE_ENCR_KEYn_MAXn                                                                    3
#define HWIO_OEM_IMAGE_ENCR_KEYn_INI(n)        \
        in_dword_masked(HWIO_OEM_IMAGE_ENCR_KEYn_ADDR(n), HWIO_OEM_IMAGE_ENCR_KEYn_RMSK)
#define HWIO_OEM_IMAGE_ENCR_KEYn_INMI(n,mask)    \
        in_dword_masked(HWIO_OEM_IMAGE_ENCR_KEYn_ADDR(n), mask)
#define HWIO_OEM_IMAGE_ENCR_KEYn_KEY_DATA0_BMSK                                                 0xffffffff
#define HWIO_OEM_IMAGE_ENCR_KEYn_KEY_DATA0_SHFT                                                        0x0

#define HWIO_IMAGE_ENCR_KEY1_0_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006160)
#define HWIO_IMAGE_ENCR_KEY1_0_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006160)
#define HWIO_IMAGE_ENCR_KEY1_0_RMSK                                                             0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_0_IN          \
        in_dword(HWIO_IMAGE_ENCR_KEY1_0_ADDR)
#define HWIO_IMAGE_ENCR_KEY1_0_INM(m)      \
        in_dword_masked(HWIO_IMAGE_ENCR_KEY1_0_ADDR, m)
#define HWIO_IMAGE_ENCR_KEY1_0_KEY_DATA0_BMSK                                                   0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_0_KEY_DATA0_SHFT                                                          0x0

#define HWIO_IMAGE_ENCR_KEY1_1_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006164)
#define HWIO_IMAGE_ENCR_KEY1_1_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006164)
#define HWIO_IMAGE_ENCR_KEY1_1_RMSK                                                             0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_1_IN          \
        in_dword(HWIO_IMAGE_ENCR_KEY1_1_ADDR)
#define HWIO_IMAGE_ENCR_KEY1_1_INM(m)      \
        in_dword_masked(HWIO_IMAGE_ENCR_KEY1_1_ADDR, m)
#define HWIO_IMAGE_ENCR_KEY1_1_KEY_DATA0_BMSK                                                   0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_1_KEY_DATA0_SHFT                                                          0x0

#define HWIO_IMAGE_ENCR_KEY1_2_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006168)
#define HWIO_IMAGE_ENCR_KEY1_2_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006168)
#define HWIO_IMAGE_ENCR_KEY1_2_RMSK                                                             0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_2_IN          \
        in_dword(HWIO_IMAGE_ENCR_KEY1_2_ADDR)
#define HWIO_IMAGE_ENCR_KEY1_2_INM(m)      \
        in_dword_masked(HWIO_IMAGE_ENCR_KEY1_2_ADDR, m)
#define HWIO_IMAGE_ENCR_KEY1_2_KEY_DATA0_BMSK                                                   0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_2_KEY_DATA0_SHFT                                                          0x0

#define HWIO_IMAGE_ENCR_KEY1_3_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000616c)
#define HWIO_IMAGE_ENCR_KEY1_3_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000616c)
#define HWIO_IMAGE_ENCR_KEY1_3_RMSK                                                             0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_3_IN          \
        in_dword(HWIO_IMAGE_ENCR_KEY1_3_ADDR)
#define HWIO_IMAGE_ENCR_KEY1_3_INM(m)      \
        in_dword_masked(HWIO_IMAGE_ENCR_KEY1_3_ADDR, m)
#define HWIO_IMAGE_ENCR_KEY1_3_KEY_DATA0_BMSK                                                   0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_3_KEY_DATA0_SHFT                                                          0x0

#define HWIO_PK_HASH0_0_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006190)
#define HWIO_PK_HASH0_0_OFFS                                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006190)
#define HWIO_PK_HASH0_0_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_0_IN          \
        in_dword(HWIO_PK_HASH0_0_ADDR)
#define HWIO_PK_HASH0_0_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_0_ADDR, m)
#define HWIO_PK_HASH0_0_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_0_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_1_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006194)
#define HWIO_PK_HASH0_1_OFFS                                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006194)
#define HWIO_PK_HASH0_1_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_1_IN          \
        in_dword(HWIO_PK_HASH0_1_ADDR)
#define HWIO_PK_HASH0_1_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_1_ADDR, m)
#define HWIO_PK_HASH0_1_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_1_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_2_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006198)
#define HWIO_PK_HASH0_2_OFFS                                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006198)
#define HWIO_PK_HASH0_2_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_2_IN          \
        in_dword(HWIO_PK_HASH0_2_ADDR)
#define HWIO_PK_HASH0_2_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_2_ADDR, m)
#define HWIO_PK_HASH0_2_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_2_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_3_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000619c)
#define HWIO_PK_HASH0_3_OFFS                                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000619c)
#define HWIO_PK_HASH0_3_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_3_IN          \
        in_dword(HWIO_PK_HASH0_3_ADDR)
#define HWIO_PK_HASH0_3_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_3_ADDR, m)
#define HWIO_PK_HASH0_3_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_3_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_4_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061a0)
#define HWIO_PK_HASH0_4_OFFS                                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061a0)
#define HWIO_PK_HASH0_4_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_4_IN          \
        in_dword(HWIO_PK_HASH0_4_ADDR)
#define HWIO_PK_HASH0_4_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_4_ADDR, m)
#define HWIO_PK_HASH0_4_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_4_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_5_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061a4)
#define HWIO_PK_HASH0_5_OFFS                                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061a4)
#define HWIO_PK_HASH0_5_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_5_IN          \
        in_dword(HWIO_PK_HASH0_5_ADDR)
#define HWIO_PK_HASH0_5_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_5_ADDR, m)
#define HWIO_PK_HASH0_5_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_5_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_6_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061a8)
#define HWIO_PK_HASH0_6_OFFS                                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061a8)
#define HWIO_PK_HASH0_6_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_6_IN          \
        in_dword(HWIO_PK_HASH0_6_ADDR)
#define HWIO_PK_HASH0_6_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_6_ADDR, m)
#define HWIO_PK_HASH0_6_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_6_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_7_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061ac)
#define HWIO_PK_HASH0_7_OFFS                                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061ac)
#define HWIO_PK_HASH0_7_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_7_IN          \
        in_dword(HWIO_PK_HASH0_7_ADDR)
#define HWIO_PK_HASH0_7_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_7_ADDR, m)
#define HWIO_PK_HASH0_7_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_7_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_8_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061b0)
#define HWIO_PK_HASH0_8_OFFS                                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061b0)
#define HWIO_PK_HASH0_8_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_8_IN          \
        in_dword(HWIO_PK_HASH0_8_ADDR)
#define HWIO_PK_HASH0_8_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_8_ADDR, m)
#define HWIO_PK_HASH0_8_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_8_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_9_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061b4)
#define HWIO_PK_HASH0_9_OFFS                                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061b4)
#define HWIO_PK_HASH0_9_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_9_IN          \
        in_dword(HWIO_PK_HASH0_9_ADDR)
#define HWIO_PK_HASH0_9_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_9_ADDR, m)
#define HWIO_PK_HASH0_9_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_9_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_10_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061b8)
#define HWIO_PK_HASH0_10_OFFS                                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061b8)
#define HWIO_PK_HASH0_10_RMSK                                                                   0xffffffff
#define HWIO_PK_HASH0_10_IN          \
        in_dword(HWIO_PK_HASH0_10_ADDR)
#define HWIO_PK_HASH0_10_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_10_ADDR, m)
#define HWIO_PK_HASH0_10_HASH_DATA0_BMSK                                                        0xffffffff
#define HWIO_PK_HASH0_10_HASH_DATA0_SHFT                                                               0x0

#define HWIO_PK_HASH0_11_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061bc)
#define HWIO_PK_HASH0_11_OFFS                                                                   (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061bc)
#define HWIO_PK_HASH0_11_RMSK                                                                   0xffffffff
#define HWIO_PK_HASH0_11_IN          \
        in_dword(HWIO_PK_HASH0_11_ADDR)
#define HWIO_PK_HASH0_11_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_11_ADDR, m)
#define HWIO_PK_HASH0_11_HASH_DATA0_BMSK                                                        0xffffffff
#define HWIO_PK_HASH0_11_HASH_DATA0_SHFT                                                               0x0

#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061f0)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061f0)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_RMSK                                              0xffffffff
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_IN          \
        in_dword(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_INM(m)      \
        in_dword_masked(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR, m)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_OUT(v)      \
        out_dword(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR,v)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR,m,v,HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_IN)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION31_STICKY_BIT_BMSK                          0x80000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION31_STICKY_BIT_SHFT                                0x1f
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION31_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION31_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION30_STICKY_BIT_BMSK                          0x40000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION30_STICKY_BIT_SHFT                                0x1e
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION30_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION30_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION29_STICKY_BIT_BMSK                          0x20000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION29_STICKY_BIT_SHFT                                0x1d
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION29_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION29_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION28_STICKY_BIT_BMSK                          0x10000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION28_STICKY_BIT_SHFT                                0x1c
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION28_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION28_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION27_STICKY_BIT_BMSK                           0x8000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION27_STICKY_BIT_SHFT                                0x1b
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION27_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION27_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION26_STICKY_BIT_BMSK                           0x4000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION26_STICKY_BIT_SHFT                                0x1a
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION26_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION26_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION25_STICKY_BIT_BMSK                           0x2000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION25_STICKY_BIT_SHFT                                0x19
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION25_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION25_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION24_STICKY_BIT_BMSK                           0x1000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION24_STICKY_BIT_SHFT                                0x18
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION24_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION24_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION23_STICKY_BIT_BMSK                            0x800000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION23_STICKY_BIT_SHFT                                0x17
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION23_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION23_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION22_STICKY_BIT_BMSK                            0x400000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION22_STICKY_BIT_SHFT                                0x16
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION22_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION22_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION21_STICKY_BIT_BMSK                            0x200000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION21_STICKY_BIT_SHFT                                0x15
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION21_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION21_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION20_STICKY_BIT_BMSK                            0x100000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION20_STICKY_BIT_SHFT                                0x14
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION20_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION20_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION19_STICKY_BIT_BMSK                             0x80000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION19_STICKY_BIT_SHFT                                0x13
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION19_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION19_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION18_STICKY_BIT_BMSK                             0x40000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION18_STICKY_BIT_SHFT                                0x12
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION18_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION18_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION17_STICKY_BIT_BMSK                             0x20000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION17_STICKY_BIT_SHFT                                0x11
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION17_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION17_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION16_STICKY_BIT_BMSK                             0x10000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION16_STICKY_BIT_SHFT                                0x10
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION16_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION16_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION15_STICKY_BIT_BMSK                              0x8000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION15_STICKY_BIT_SHFT                                 0xf
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION15_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION15_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION14_STICKY_BIT_BMSK                              0x4000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION14_STICKY_BIT_SHFT                                 0xe
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION14_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION14_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION13_STICKY_BIT_BMSK                              0x2000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION13_STICKY_BIT_SHFT                                 0xd
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION13_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION13_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION12_STICKY_BIT_BMSK                              0x1000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION12_STICKY_BIT_SHFT                                 0xc
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION12_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION12_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION11_STICKY_BIT_BMSK                               0x800
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION11_STICKY_BIT_SHFT                                 0xb
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION11_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION11_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION10_STICKY_BIT_BMSK                               0x400
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION10_STICKY_BIT_SHFT                                 0xa
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION10_STICKY_BIT_ALLOW_WRITE_FVAL                     0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION10_STICKY_BIT_DISABLE_WRITE_FVAL                   0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION9_STICKY_BIT_BMSK                                0x200
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION9_STICKY_BIT_SHFT                                  0x9
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION9_STICKY_BIT_ALLOW_WRITE_FVAL                      0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION9_STICKY_BIT_DISABLE_WRITE_FVAL                    0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION8_STICKY_BIT_BMSK                                0x100
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION8_STICKY_BIT_SHFT                                  0x8
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION8_STICKY_BIT_ALLOW_WRITE_FVAL                      0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION8_STICKY_BIT_DISABLE_WRITE_FVAL                    0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION7_STICKY_BIT_BMSK                                 0x80
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION7_STICKY_BIT_SHFT                                  0x7
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION7_STICKY_BIT_ALLOW_WRITE_FVAL                      0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION7_STICKY_BIT_DISABLE_WRITE_FVAL                    0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION6_STICKY_BIT_BMSK                                 0x40
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION6_STICKY_BIT_SHFT                                  0x6
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION6_STICKY_BIT_ALLOW_WRITE_FVAL                      0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION6_STICKY_BIT_DISABLE_WRITE_FVAL                    0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION5_STICKY_BIT_BMSK                                 0x20
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION5_STICKY_BIT_SHFT                                  0x5
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION5_STICKY_BIT_ALLOW_WRITE_FVAL                      0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION5_STICKY_BIT_DISABLE_WRITE_FVAL                    0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION4_STICKY_BIT_BMSK                                 0x10
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION4_STICKY_BIT_SHFT                                  0x4
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION4_STICKY_BIT_ALLOW_WRITE_FVAL                      0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION4_STICKY_BIT_DISABLE_WRITE_FVAL                    0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION3_STICKY_BIT_BMSK                                  0x8
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION3_STICKY_BIT_SHFT                                  0x3
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION3_STICKY_BIT_ALLOW_WRITE_FVAL                      0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION3_STICKY_BIT_DISABLE_WRITE_FVAL                    0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION2_STICKY_BIT_BMSK                                  0x4
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION2_STICKY_BIT_SHFT                                  0x2
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION2_STICKY_BIT_ALLOW_WRITE_FVAL                      0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION2_STICKY_BIT_DISABLE_WRITE_FVAL                    0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION1_STICKY_BIT_BMSK                                  0x2
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION1_STICKY_BIT_SHFT                                  0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION1_STICKY_BIT_ALLOW_WRITE_FVAL                      0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION1_STICKY_BIT_DISABLE_WRITE_FVAL                    0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION0_STICKY_BIT_BMSK                                  0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION0_STICKY_BIT_SHFT                                  0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION0_STICKY_BIT_ALLOW_WRITE_FVAL                      0x0
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION0_STICKY_BIT_DISABLE_WRITE_FVAL                    0x1

#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061f4)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_OFFS                                              (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061f4)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_RMSK                                              0xffffffff
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_IN          \
        in_dword(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_INM(m)      \
        in_dword_masked(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR, m)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_OUT(v)      \
        out_dword(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR,v)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR,m,v,HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_IN)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_RSVD0_BMSK                                        0xffffffff
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_RSVD0_SHFT                                               0x0

#define HWIO_ANTI_ROLLBACK_1_0_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006200)
#define HWIO_ANTI_ROLLBACK_1_0_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006200)
#define HWIO_ANTI_ROLLBACK_1_0_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_1_0_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_1_0_ADDR)
#define HWIO_ANTI_ROLLBACK_1_0_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_1_0_ADDR, m)
#define HWIO_ANTI_ROLLBACK_1_0_XBL0_BMSK                                                        0xffffffff
#define HWIO_ANTI_ROLLBACK_1_0_XBL0_SHFT                                                               0x0

#define HWIO_ANTI_ROLLBACK_1_1_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006204)
#define HWIO_ANTI_ROLLBACK_1_1_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006204)
#define HWIO_ANTI_ROLLBACK_1_1_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_1_1_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_1_1_ADDR)
#define HWIO_ANTI_ROLLBACK_1_1_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_1_1_ADDR, m)
#define HWIO_ANTI_ROLLBACK_1_1_XBL1_BMSK                                                        0xffffffff
#define HWIO_ANTI_ROLLBACK_1_1_XBL1_SHFT                                                               0x0

#define HWIO_ANTI_ROLLBACK_2_0_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006208)
#define HWIO_ANTI_ROLLBACK_2_0_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006208)
#define HWIO_ANTI_ROLLBACK_2_0_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_2_0_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_2_0_ADDR)
#define HWIO_ANTI_ROLLBACK_2_0_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_2_0_ADDR, m)
#define HWIO_ANTI_ROLLBACK_2_0_PIL_SUBSYSTEM_31_0_BMSK                                          0xffffffff
#define HWIO_ANTI_ROLLBACK_2_0_PIL_SUBSYSTEM_31_0_SHFT                                                 0x0

#define HWIO_ANTI_ROLLBACK_2_1_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000620c)
#define HWIO_ANTI_ROLLBACK_2_1_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000620c)
#define HWIO_ANTI_ROLLBACK_2_1_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_2_1_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_2_1_ADDR)
#define HWIO_ANTI_ROLLBACK_2_1_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_2_1_ADDR, m)
#define HWIO_ANTI_ROLLBACK_2_1_XBL_SEC_BMSK                                                     0xfe000000
#define HWIO_ANTI_ROLLBACK_2_1_XBL_SEC_SHFT                                                           0x19
#define HWIO_ANTI_ROLLBACK_2_1_AOP_BMSK                                                          0x1fe0000
#define HWIO_ANTI_ROLLBACK_2_1_AOP_SHFT                                                               0x11
#define HWIO_ANTI_ROLLBACK_2_1_TZ_BMSK                                                             0x1ffff
#define HWIO_ANTI_ROLLBACK_2_1_TZ_SHFT                                                                 0x0

#define HWIO_ANTI_ROLLBACK_3_0_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006210)
#define HWIO_ANTI_ROLLBACK_3_0_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006210)
#define HWIO_ANTI_ROLLBACK_3_0_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_3_0_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_3_0_ADDR)
#define HWIO_ANTI_ROLLBACK_3_0_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_3_0_ADDR, m)
#define HWIO_ANTI_ROLLBACK_3_0_RSVD1_BMSK                                                       0xc0000000
#define HWIO_ANTI_ROLLBACK_3_0_RSVD1_SHFT                                                             0x1e
#define HWIO_ANTI_ROLLBACK_3_0_TQS_HASH_ACTIVE_BMSK                                             0x3e000000
#define HWIO_ANTI_ROLLBACK_3_0_TQS_HASH_ACTIVE_SHFT                                                   0x19
#define HWIO_ANTI_ROLLBACK_3_0_RPMB_KEY_PROVISIONED_BMSK                                         0x1000000
#define HWIO_ANTI_ROLLBACK_3_0_RPMB_KEY_PROVISIONED_SHFT                                              0x18
#define HWIO_ANTI_ROLLBACK_3_0_RPMB_KEY_PROVISIONED_RPMB_KEY_NOT_PROVISIONED_FVAL                      0x0
#define HWIO_ANTI_ROLLBACK_3_0_RPMB_KEY_PROVISIONED_RPMB_KEY_PROVISIONED_FVAL                          0x1
#define HWIO_ANTI_ROLLBACK_3_0_PIL_SUBSYSTEM_47_32_BMSK                                           0xffff00
#define HWIO_ANTI_ROLLBACK_3_0_PIL_SUBSYSTEM_47_32_SHFT                                                0x8
#define HWIO_ANTI_ROLLBACK_3_0_SAFESWITCH_BMSK                                                        0xff
#define HWIO_ANTI_ROLLBACK_3_0_SAFESWITCH_SHFT                                                         0x0

#define HWIO_ANTI_ROLLBACK_3_1_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006214)
#define HWIO_ANTI_ROLLBACK_3_1_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006214)
#define HWIO_ANTI_ROLLBACK_3_1_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_3_1_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_3_1_ADDR)
#define HWIO_ANTI_ROLLBACK_3_1_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_3_1_ADDR, m)
#define HWIO_ANTI_ROLLBACK_3_1_RSVD1_BMSK                                                       0xf0000000
#define HWIO_ANTI_ROLLBACK_3_1_RSVD1_SHFT                                                             0x1c
#define HWIO_ANTI_ROLLBACK_3_1_DEVICE_CFG_BMSK                                                   0xffe0000
#define HWIO_ANTI_ROLLBACK_3_1_DEVICE_CFG_SHFT                                                        0x11
#define HWIO_ANTI_ROLLBACK_3_1_DEBUG_POLICY_BMSK                                                   0x1f000
#define HWIO_ANTI_ROLLBACK_3_1_DEBUG_POLICY_SHFT                                                       0xc
#define HWIO_ANTI_ROLLBACK_3_1_HYPERVISOR_BMSK                                                       0xfff
#define HWIO_ANTI_ROLLBACK_3_1_HYPERVISOR_SHFT                                                         0x0

#define HWIO_ANTI_ROLLBACK_4_0_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006218)
#define HWIO_ANTI_ROLLBACK_4_0_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006218)
#define HWIO_ANTI_ROLLBACK_4_0_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_4_0_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_4_0_ADDR)
#define HWIO_ANTI_ROLLBACK_4_0_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_4_0_ADDR, m)
#define HWIO_ANTI_ROLLBACK_4_0_MSS_BMSK                                                         0xffff0000
#define HWIO_ANTI_ROLLBACK_4_0_MSS_SHFT                                                               0x10
#define HWIO_ANTI_ROLLBACK_4_0_MISC_BMSK                                                            0xffff
#define HWIO_ANTI_ROLLBACK_4_0_MISC_SHFT                                                               0x0

#define HWIO_ANTI_ROLLBACK_4_1_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000621c)
#define HWIO_ANTI_ROLLBACK_4_1_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000621c)
#define HWIO_ANTI_ROLLBACK_4_1_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_4_1_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_4_1_ADDR)
#define HWIO_ANTI_ROLLBACK_4_1_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_4_1_ADDR, m)
#define HWIO_ANTI_ROLLBACK_4_1_SIMLOCK_BMSK                                                     0x80000000
#define HWIO_ANTI_ROLLBACK_4_1_SIMLOCK_SHFT                                                           0x1f
#define HWIO_ANTI_ROLLBACK_4_1_RSVD0_BMSK                                                       0x7ffffff0
#define HWIO_ANTI_ROLLBACK_4_1_RSVD0_SHFT                                                              0x4
#define HWIO_ANTI_ROLLBACK_4_1_ROOT_CERT_PK_HASH_INDEX_BMSK                                            0xf
#define HWIO_ANTI_ROLLBACK_4_1_ROOT_CERT_PK_HASH_INDEX_SHFT                                            0x0

#define HWIO_ANTI_ROLLBACK_5_0_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006220)
#define HWIO_ANTI_ROLLBACK_5_0_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006220)
#define HWIO_ANTI_ROLLBACK_5_0_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_5_0_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_5_0_ADDR)
#define HWIO_ANTI_ROLLBACK_5_0_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_5_0_ADDR, m)
#define HWIO_ANTI_ROLLBACK_5_0_MISC_BMSK                                                        0xffffffff
#define HWIO_ANTI_ROLLBACK_5_0_MISC_SHFT                                                               0x0

#define HWIO_ANTI_ROLLBACK_5_1_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006224)
#define HWIO_ANTI_ROLLBACK_5_1_OFFS                                                             (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006224)
#define HWIO_ANTI_ROLLBACK_5_1_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_5_1_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_5_1_ADDR)
#define HWIO_ANTI_ROLLBACK_5_1_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_5_1_ADDR, m)
#define HWIO_ANTI_ROLLBACK_5_1_MISC_BMSK                                                        0xffffffff
#define HWIO_ANTI_ROLLBACK_5_1_MISC_SHFT                                                               0x0

#define HWIO_MRC_2_0_0_ADDR                                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006250)
#define HWIO_MRC_2_0_0_OFFS                                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006250)
#define HWIO_MRC_2_0_0_RMSK                                                                     0xffffffff
#define HWIO_MRC_2_0_0_IN          \
        in_dword(HWIO_MRC_2_0_0_ADDR)
#define HWIO_MRC_2_0_0_INM(m)      \
        in_dword_masked(HWIO_MRC_2_0_0_ADDR, m)
#define HWIO_MRC_2_0_0_RSVD0_BMSK                                                               0xfffffff0
#define HWIO_MRC_2_0_0_RSVD0_SHFT                                                                      0x4
#define HWIO_MRC_2_0_0_ROOT_CERT_ACTIVATION_LIST_BMSK                                                  0xf
#define HWIO_MRC_2_0_0_ROOT_CERT_ACTIVATION_LIST_SHFT                                                  0x0

#define HWIO_MRC_2_0_1_ADDR                                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006254)
#define HWIO_MRC_2_0_1_OFFS                                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006254)
#define HWIO_MRC_2_0_1_RMSK                                                                     0xffffffff
#define HWIO_MRC_2_0_1_IN          \
        in_dword(HWIO_MRC_2_0_1_ADDR)
#define HWIO_MRC_2_0_1_INM(m)      \
        in_dword_masked(HWIO_MRC_2_0_1_ADDR, m)
#define HWIO_MRC_2_0_1_RSVD1_BMSK                                                               0xfffffffe
#define HWIO_MRC_2_0_1_RSVD1_SHFT                                                                      0x1
#define HWIO_MRC_2_0_1_CURRENT_UIE_KEY_SEL_BMSK                                                        0x1
#define HWIO_MRC_2_0_1_CURRENT_UIE_KEY_SEL_SHFT                                                        0x0

#define HWIO_MRC_2_0_2_ADDR                                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006258)
#define HWIO_MRC_2_0_2_OFFS                                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006258)
#define HWIO_MRC_2_0_2_RMSK                                                                     0xffffffff
#define HWIO_MRC_2_0_2_IN          \
        in_dword(HWIO_MRC_2_0_2_ADDR)
#define HWIO_MRC_2_0_2_INM(m)      \
        in_dword_masked(HWIO_MRC_2_0_2_ADDR, m)
#define HWIO_MRC_2_0_2_RSVD0_BMSK                                                               0xfffffff0
#define HWIO_MRC_2_0_2_RSVD0_SHFT                                                                      0x4
#define HWIO_MRC_2_0_2_ROOT_CERT_REVOCATION_LIST_BMSK                                                  0xf
#define HWIO_MRC_2_0_2_ROOT_CERT_REVOCATION_LIST_SHFT                                                  0x0

#define HWIO_MRC_2_0_3_ADDR                                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000625c)
#define HWIO_MRC_2_0_3_OFFS                                                                     (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000625c)
#define HWIO_MRC_2_0_3_RMSK                                                                     0xffffffff
#define HWIO_MRC_2_0_3_IN          \
        in_dword(HWIO_MRC_2_0_3_ADDR)
#define HWIO_MRC_2_0_3_INM(m)      \
        in_dword_masked(HWIO_MRC_2_0_3_ADDR, m)
#define HWIO_MRC_2_0_3_RSVD0_BMSK                                                               0xffffffff
#define HWIO_MRC_2_0_3_RSVD0_SHFT                                                                      0x0

#define HWIO_CRYPTO_LIB_VERSION_ADDR                                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006300)
#define HWIO_CRYPTO_LIB_VERSION_OFFS                                                            (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006300)
#define HWIO_CRYPTO_LIB_VERSION_RMSK                                                            0xffffffff
#define HWIO_CRYPTO_LIB_VERSION_IN          \
        in_dword(HWIO_CRYPTO_LIB_VERSION_ADDR)
#define HWIO_CRYPTO_LIB_VERSION_INM(m)      \
        in_dword_masked(HWIO_CRYPTO_LIB_VERSION_ADDR, m)
#define HWIO_CRYPTO_LIB_VERSION_VERSION_BMSK                                                    0xffffffff
#define HWIO_CRYPTO_LIB_VERSION_VERSION_SHFT                                                           0x0

#define HWIO_LCM_0_ADDR                                                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006304)
#define HWIO_LCM_0_OFFS                                                                         (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006304)
#define HWIO_LCM_0_RMSK                                                                         0xffffffff
#define HWIO_LCM_0_IN          \
        in_dword(HWIO_LCM_0_ADDR)
#define HWIO_LCM_0_INM(m)      \
        in_dword_masked(HWIO_LCM_0_ADDR, m)
#define HWIO_LCM_0_DISABLE_LCM_BMSK                                                             0x80000000
#define HWIO_LCM_0_DISABLE_LCM_SHFT                                                                   0x1f
#define HWIO_LCM_0_DISABLE_LCM_STATE_TRANSITION_BMSK                                            0x40000000
#define HWIO_LCM_0_DISABLE_LCM_STATE_TRANSITION_SHFT                                                  0x1e
#define HWIO_LCM_0_DISABLE_SECURE_PHK_BMSK                                                      0x20000000
#define HWIO_LCM_0_DISABLE_SECURE_PHK_SHFT                                                            0x1d
#define HWIO_LCM_0_RSVD_BMSK                                                                    0x1fffff00
#define HWIO_LCM_0_RSVD_SHFT                                                                           0x8
#define HWIO_LCM_0_DEBUG_STATE_BMSK                                                                   0x80
#define HWIO_LCM_0_DEBUG_STATE_SHFT                                                                    0x7
#define HWIO_LCM_0_ILLEGAL_STATE_BMSK                                                                 0x40
#define HWIO_LCM_0_ILLEGAL_STATE_SHFT                                                                  0x6
#define HWIO_LCM_0_QC_EXTERNAL_BMSK                                                                   0x20
#define HWIO_LCM_0_QC_EXTERNAL_SHFT                                                                    0x5
#define HWIO_LCM_0_QC_INTERNAL_BMSK                                                                   0x10
#define HWIO_LCM_0_QC_INTERNAL_SHFT                                                                    0x4
#define HWIO_LCM_0_QC_FEAT_CONFIG_BMSK                                                                 0x8
#define HWIO_LCM_0_QC_FEAT_CONFIG_SHFT                                                                 0x3
#define HWIO_LCM_0_HW_TEST_BMSK                                                                        0x4
#define HWIO_LCM_0_HW_TEST_SHFT                                                                        0x2
#define HWIO_LCM_0_SOC_PERSO_BMSK                                                                      0x2
#define HWIO_LCM_0_SOC_PERSO_SHFT                                                                      0x1
#define HWIO_LCM_0_BLANK_BMSK                                                                          0x1
#define HWIO_LCM_0_BLANK_SHFT                                                                          0x0

#define HWIO_LCM_1_ADDR                                                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006308)
#define HWIO_LCM_1_OFFS                                                                         (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006308)
#define HWIO_LCM_1_RMSK                                                                         0xffffffff
#define HWIO_LCM_1_IN          \
        in_dword(HWIO_LCM_1_ADDR)
#define HWIO_LCM_1_INM(m)      \
        in_dword_masked(HWIO_LCM_1_ADDR, m)
#define HWIO_LCM_1_LCM_DATA1_BMSK                                                               0xffffffff
#define HWIO_LCM_1_LCM_DATA1_SHFT                                                                      0x0

#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006400)
#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_OFFS                                                    (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006400)
#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_RMSK                                                    0xffffffff
#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_IN          \
        in_dword(HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDR)
#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_INM(m)      \
        in_dword_masked(HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDR, m)
#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_OUT(v)      \
        out_dword(HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDR,v)
#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDR,m,v,HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_IN)
#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDRESS_BMSK                                            0xffffffff
#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDRESS_SHFT                                                   0x0

/*----------------------------------------------------------------------------
 * MODULE: TCSR_TCSR_REGS
 *--------------------------------------------------------------------------*/

#define TCSR_TCSR_REGS_REG_BASE                                                                                         (CORE_TOP_CSR_BASE      + 0x000c0000)
#define TCSR_TCSR_REGS_REG_BASE_SIZE                                                                                    0x30000
#define TCSR_TCSR_REGS_REG_BASE_USED                                                                                    0x2e014
#define TCSR_TCSR_REGS_REG_BASE_OFFS                                                                                    0x000c0000

#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x0000d000)
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_OFFS                                                                          (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d000)
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_RMSK                                                                                 0x7
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_IN          \
        in_dword(HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_ADDR)
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_ADDR, m)
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDMMCX_READ_BMSK                                                     0x4
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDMMCX_READ_SHFT                                                     0x2
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDGFX_READ_BMSK                                                      0x2
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDGFX_READ_SHFT                                                      0x1
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDCX_READ_BMSK                                                       0x1
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDCX_READ_SHFT                                                       0x0

#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x00022000)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_OFFS                                                                (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022000)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_RMSK                                                                      0xff
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_ADDR)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_IN)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_DBGOVR_COMPILER_MEM_ACC_SEL_0_BMSK                                        0xff
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_DBGOVR_COMPILER_MEM_ACC_SEL_0_SHFT                                         0x0

#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00022004)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_OFFS                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022004)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_RMSK                                                                  0xffffffff
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_ADDR)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_IN)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_DBGOVR_CUSTOM_MEM_ACC_SEL_0_BMSK                                      0xffffffff
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_DBGOVR_CUSTOM_MEM_ACC_SEL_0_SHFT                                             0x0

#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00022008)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_OFFS                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022008)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_RMSK                                                                        0xff
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_ADDR)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_IN)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_DBGOVR_CUSTOM_MEM_ACC_SEL_1_BMSK                                            0xff
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_DBGOVR_CUSTOM_MEM_ACC_SEL_1_SHFT                                             0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00022010)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022010)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_7_BMSK                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_7_SHFT                                     0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00022014)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022014)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_6_BMSK                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_6_SHFT                                     0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00022018)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022018)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_5_BMSK                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_5_SHFT                                     0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002201c)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002201c)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_4_BMSK                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_4_SHFT                                     0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00022020)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022020)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_3_BMSK                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_3_SHFT                                     0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00022024)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022024)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_2_BMSK                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_2_SHFT                                     0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00022028)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022028)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_1_BMSK                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_1_SHFT                                     0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002202c)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002202c)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_0_BMSK                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_0_SHFT                                     0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022030)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_OFFS                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022030)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022034)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_OFFS                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022034)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022038)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_OFFS                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022038)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0002203c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_OFFS                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002203c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022040)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_OFFS                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022040)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022044)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_OFFS                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022044)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022048)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_OFFS                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022048)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0002204c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_OFFS                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002204c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022050)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_OFFS                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022050)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022054)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022054)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022058)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022058)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0002205c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002205c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022060)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022060)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022064)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022064)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022068)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022068)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0002206c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002206c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022070)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022070)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022074)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022074)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022078)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022078)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0002207c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002207c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022080)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022080)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022084)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022084)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022088)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022088)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0002208c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002208c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022090)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022090)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022094)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022094)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022098)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022098)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0002209c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002209c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220a0)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x000220a0)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220a4)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x000220a4)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220a8)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x000220a8)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220ac)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x000220ac)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220b0)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x000220b0)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220b4)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x000220b4)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220b8)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x000220b8)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220bc)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x000220bc)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220c0)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x000220c0)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220c4)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x000220c4)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220c8)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x000220c8)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220cc)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x000220cc)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_SHFT                               0x0

#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000d004)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_OFFS                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d004)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_RMSK                                                                 0xffffffff
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_FUSE_COMPILER_MEM_ACC_0_READ_BMSK                                    0xffffffff
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_FUSE_COMPILER_MEM_ACC_0_READ_SHFT                                           0x0

#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000d008)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_OFFS                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d008)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_RMSK                                                                 0xffffffff
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_FUSE_COMPILER_MEM_ACC_1_READ_BMSK                                    0xffffffff
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_FUSE_COMPILER_MEM_ACC_1_READ_SHFT                                           0x0

#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000d00c)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_OFFS                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d00c)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_RMSK                                                                     0xffff
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_FUSE_COMPILER_MEM_ACC_2_READ_BMSK                                        0xffff
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_FUSE_COMPILER_MEM_ACC_2_READ_SHFT                                           0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d010)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d010)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d014)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d014)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d018)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d018)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d01c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d01c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d020)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d020)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d024)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d024)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d028)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d028)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d02c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d02c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d030)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d030)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d034)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d034)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d038)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d038)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d03c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d03c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d040)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d040)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d044)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d044)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d048)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d048)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d04c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d04c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d050)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d050)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d054)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d054)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d058)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d058)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d05c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d05c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d060)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d060)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d064)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d064)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d068)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d068)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d06c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d06c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d070)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d070)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d074)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d074)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d078)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d078)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d07c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d07c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d080)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d080)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d084)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d084)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d088)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d088)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d08c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d08c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d090)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d090)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d094)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d094)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d098)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d098)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d09c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d09c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d0a0)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d0a0)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d0a4)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d0a4)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d0a8)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d0a8)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d0ac)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000d0ac)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_SHFT                                     0x0

#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022800)
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_OFFS                                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022800)
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_RMSK                                                                            0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_IN          \
        in_dword(HWIO_TCSR_MBIST_DBG_STATUS0_REG_ADDR)
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_MBIST_DBG_STATUS0_REG_ADDR, m)
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_MBIST_DBG_STATUS0_BMSK                                                          0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_MBIST_DBG_STATUS0_SHFT                                                                 0x0

#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022804)
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_OFFS                                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022804)
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_RMSK                                                                            0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_IN          \
        in_dword(HWIO_TCSR_MBIST_DBG_STATUS1_REG_ADDR)
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_MBIST_DBG_STATUS1_REG_ADDR, m)
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_MBIST_DBG_STATUS1_BMSK                                                          0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_MBIST_DBG_STATUS1_SHFT                                                                 0x0

#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022808)
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_OFFS                                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00022808)
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_RMSK                                                                            0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_IN          \
        in_dword(HWIO_TCSR_MBIST_DBG_STATUS2_REG_ADDR)
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_MBIST_DBG_STATUS2_REG_ADDR, m)
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_MBIST_DBG_STATUS2_BMSK                                                          0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_MBIST_DBG_STATUS2_SHFT                                                                 0x0

#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0002280c)
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_OFFS                                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002280c)
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_RMSK                                                                            0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_IN          \
        in_dword(HWIO_TCSR_MBIST_DBG_STATUS3_REG_ADDR)
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_MBIST_DBG_STATUS3_REG_ADDR, m)
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_MBIST_DBG_STATUS3_BMSK                                                          0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_MBIST_DBG_STATUS3_SHFT                                                                 0x0

#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_ADDR                                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x00000800)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_OFFS                                                                             (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00000800)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_RMSK                                                                                    0x1
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_IN          \
        in_dword(HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_ADDR)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_ADDR, m)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_OUT(v)      \
        out_dword(HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_ADDR,v)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_ADDR,m,v,HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_IN)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_TIMEOUT_SLAVE_GLB_EN_BMSK                                                               0x1
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_TIMEOUT_SLAVE_GLB_EN_SHFT                                                               0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_ADDR                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x00021010)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_OFFS                                                                    (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00021010)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_RMSK                                                                        0xffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_BMSK                                                 0xffc0
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_SHFT                                                    0x6
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_BMSK                                                    0x3f
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_SHFT                                                     0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_ADDR                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x00021014)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_OFFS                                                                    (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00021014)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_RMSK                                                                        0xffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_BMSK                                                 0xffc0
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_SHFT                                                    0x6
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_BMSK                                                    0x3f
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_SHFT                                                     0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_ADDR                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x00021018)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_OFFS                                                                    (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00021018)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_RMSK                                                                      0x7fffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_BMSK                                               0x7fff00
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_SHFT                                                    0x8
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_BMSK                                                    0xff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_SHFT                                                     0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x0002101c)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_OFFS                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002101c)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_RMSK                                                                      0xffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                        0xffc0
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                           0x6
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                           0x3f
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                            0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00021020)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_OFFS                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00021020)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_RMSK                                                                      0xffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                        0xffc0
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                           0x6
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                           0x3f
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                            0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00021024)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_OFFS                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00021024)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_RMSK                                                                    0x7fffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                      0x7fff00
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                           0x8
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                           0xff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                            0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00021028)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_OFFS                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00021028)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_RMSK                                                                      0xffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                        0xffc0
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                           0x6
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                           0x3f
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                            0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x0002102c)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_OFFS                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002102c)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_RMSK                                                                      0xffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                        0xffc0
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                           0x6
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                           0x3f
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                            0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00021030)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_OFFS                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00021030)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_RMSK                                                                    0x7fffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                      0x7fff00
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                           0x8
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                           0xff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                            0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_ADDR                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0000b000)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_OFFS                                                                   (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000b000)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_RMSK                                                                       0xffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_BMSK                                                0xffc0
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_SHFT                                                   0x6
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_BMSK                                                   0x3f
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_SHFT                                                    0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_ADDR                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0000b004)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_OFFS                                                                   (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000b004)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_RMSK                                                                       0xffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_BMSK                                                0xffc0
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_SHFT                                                   0x6
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_BMSK                                                   0x3f
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_SHFT                                                    0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_ADDR                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0000b008)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_OFFS                                                                   (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000b008)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_RMSK                                                                     0x7fffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_BMSK                                              0x7fff00
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_SHFT                                                   0x8
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_BMSK                                                   0xff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_SHFT                                                    0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b00c)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_OFFS                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000b00c)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_RMSK                                                                     0xffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                       0xffc0
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                          0x6
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                          0x3f
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b010)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_OFFS                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000b010)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_RMSK                                                                     0xffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                       0xffc0
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                          0x6
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                          0x3f
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b014)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_OFFS                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000b014)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_RMSK                                                                   0x7fffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                     0x7fff00
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                          0x8
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                          0xff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b018)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_OFFS                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000b018)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_RMSK                                                                     0xffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                       0xffc0
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                          0x6
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                          0x3f
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b01c)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_OFFS                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000b01c)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_RMSK                                                                     0xffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                       0xffc0
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                          0x6
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                          0x3f
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b020)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_OFFS                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000b020)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_RMSK                                                                   0x7fffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                     0x7fff00
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                          0x8
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                          0xff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x00029004)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_OFFS                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029004)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_RMSK                                                                     0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_BMSK                                              0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_SHFT                                                 0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_BMSK                                                 0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_SHFT                                                  0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x00029008)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_OFFS                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029008)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_RMSK                                                                     0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_BMSK                                              0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_SHFT                                                 0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_BMSK                                                 0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_SHFT                                                  0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0002900c)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_OFFS                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002900c)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_RMSK                                                                   0x7fffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_BMSK                                            0x7fff00
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_SHFT                                                 0x8
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_BMSK                                                 0xff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_SHFT                                                  0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029010)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029010)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029014)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029014)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029018)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029018)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_RMSK                                                                 0x7fffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                   0x7fff00
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0002901c)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002901c)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029020)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029020)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029024)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029024)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_RMSK                                                                 0x7fffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                   0x7fff00
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029028)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029028)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0002902c)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002902c)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029030)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029030)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_RMSK                                                                 0x7fffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                   0x7fff00
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029034)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029034)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029038)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029038)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0002903c)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002903c)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_RMSK                                                                 0x7fffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                   0x7fff00
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029040)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029040)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029044)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029044)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029048)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029048)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_RMSK                                                                 0x7fffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                   0x7fff00
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0002904c)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002904c)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029050)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029050)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029054)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029054)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_RMSK                                                                 0x7fffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                   0x7fff00
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0002b004)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_OFFS                                                                (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b004)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_RMSK                                                                    0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_BMSK                                             0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_SHFT                                                0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_BMSK                                                0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_SHFT                                                 0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0002b008)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_OFFS                                                                (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b008)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_RMSK                                                                    0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_BMSK                                             0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_SHFT                                                0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_BMSK                                                0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_SHFT                                                 0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0002b00c)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_OFFS                                                                (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b00c)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_RMSK                                                                  0x7fffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_BMSK                                           0x7fff00
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_SHFT                                                0x8
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_BMSK                                                0xff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_SHFT                                                 0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b010)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b010)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b014)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b014)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b018)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b018)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_RMSK                                                                0x7fffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0x7fff00
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b01c)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b01c)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b020)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b020)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b024)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b024)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_RMSK                                                                0x7fffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0x7fff00
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b028)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b028)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b02c)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b02c)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b030)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b030)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_RMSK                                                                0x7fffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0x7fff00
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b034)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b034)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b038)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b038)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b03c)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b03c)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_RMSK                                                                0x7fffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0x7fff00
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b040)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b040)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b044)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b044)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b048)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b048)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_RMSK                                                                0x7fffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0x7fff00
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b04c)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b04c)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b050)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b050)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b054)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b054)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_RMSK                                                                0x7fffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0x7fff00
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0002d000)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_OFFS                                                                (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002d000)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_RMSK                                                                    0xffff
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_BMSK                                             0xffc0
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_SHFT                                                0x6
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_BMSK                                                0x3f
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_SHFT                                                 0x0

#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0002d004)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_OFFS                                                                (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002d004)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_RMSK                                                                    0xffff
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_BMSK                                             0xffc0
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_SHFT                                                0x6
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_BMSK                                                0x3f
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_SHFT                                                 0x0

#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0002d008)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_OFFS                                                                (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002d008)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_RMSK                                                                  0x7fffff
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_BMSK                                           0x7fff00
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_SHFT                                                0x8
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_BMSK                                                0xff
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_SHFT                                                 0x0

#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002d00c)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002d00c)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002d010)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002d010)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002d014)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002d014)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_RMSK                                                                0x7fffff
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0x7fff00
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_ADDR                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0002e000)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_OFFS                                                                   (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002e000)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_RMSK                                                                       0xffff
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_BMSK                                                0xffc0
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_SHFT                                                   0x6
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_BMSK                                                   0x3f
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_SHFT                                                    0x0

#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_ADDR                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0002e004)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_OFFS                                                                   (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002e004)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_RMSK                                                                       0xffff
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_BMSK                                                0xffc0
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_SHFT                                                   0x6
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_BMSK                                                   0x3f
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_SHFT                                                    0x0

#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_ADDR                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0002e008)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_OFFS                                                                   (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002e008)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_RMSK                                                                     0x7fffff
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_BMSK                                              0x7fff00
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_SHFT                                                   0x8
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_BMSK                                                   0xff
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_SHFT                                                    0x0

#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0002e00c)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_OFFS                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002e00c)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_RMSK                                                                     0xffff
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                       0xffc0
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                          0x6
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                          0x3f
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0002e010)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_OFFS                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002e010)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_RMSK                                                                     0xffff
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                       0xffc0
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                          0x6
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                          0x3f
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0002e014)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_OFFS                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002e014)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_RMSK                                                                   0x7fffff
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                     0x7fff00
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                          0x8
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                          0xff
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x00029060)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_OFFS                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029060)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_RMSK                                                                   0xffffff
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_I_SSC_QUPV3_0_GSI_INTR_BMSK                                            0xffff00
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_I_SSC_QUPV3_0_GSI_INTR_SHFT                                                 0x8
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_I_SSC_QUPV3_0_SE_INTR_BMSK                                                 0xff
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_I_SSC_QUPV3_0_SE_INTR_SHFT                                                  0x0

#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029064)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029064)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_RMSK                                                                 0xffffff
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_I_SSC_QUPV3_0_GSI_INTR_ENABLE_BMSK                                   0xffff00
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_I_SSC_QUPV3_0_GSI_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_I_SSC_QUPV3_0_SE_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_I_SSC_QUPV3_0_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029068)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029068)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_RMSK                                                                 0xffffff
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_IN          \
        in_dword(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR,v)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR,m,v,HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_IN)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_I_SSC_QUPV3_0_GSI_INTR_ENABLE_BMSK                                   0xffff00
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_I_SSC_QUPV3_0_GSI_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_I_SSC_QUPV3_0_SE_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_I_SSC_QUPV3_0_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0002b060)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_OFFS                                                                (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b060)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_RMSK                                                                  0xffffff
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_I_SSC_QUPV3_0_GSI_INTR_BMSK                                           0xffff00
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_I_SSC_QUPV3_0_GSI_INTR_SHFT                                                0x8
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_I_SSC_QUPV3_0_SE_INTR_BMSK                                                0xff
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_I_SSC_QUPV3_0_SE_INTR_SHFT                                                 0x0

#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b064)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b064)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_RMSK                                                                0xffffff
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_I_SSC_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0xffff00
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_I_SSC_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_I_SSC_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_I_SSC_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b068)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b068)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_RMSK                                                                0xffffff
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_IN          \
        in_dword(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR,v)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR,m,v,HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_IN)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_I_SSC_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0xffff00
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_I_SSC_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_I_SSC_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_I_SSC_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00004000)
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_OFFS                                                                        (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00004000)
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_RMSK                                                                        0xffffffff
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SEC_INTR_BMSK                           0x80000000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SEC_INTR_SHFT                                 0x1f
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_BOOT_ROM_XPU_SEC_INTR_BMSK                                                  0x40000000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_BOOT_ROM_XPU_SEC_INTR_SHFT                                                        0x1e
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SEC_INTR_BMSK                               0x20000000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SEC_INTR_SHFT                                     0x1d
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_LLCC3_XPU_SEC_INTR_BMSK                                                     0x10000000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_LLCC3_XPU_SEC_INTR_SHFT                                                           0x1c
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_LLCC2_XPU_SEC_INTR_BMSK                                                      0x8000000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_LLCC2_XPU_SEC_INTR_SHFT                                                           0x1b
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_LLCC1_XPU_SEC_INTR_BMSK                                                      0x4000000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_LLCC1_XPU_SEC_INTR_SHFT                                                           0x1a
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_LLCC0_XPU_SEC_INTR_BMSK                                                      0x2000000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_LLCC0_XPU_SEC_INTR_SHFT                                                           0x19
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_UFS_XPU_SEC_INTR_BMSK                                                        0x1000000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_UFS_XPU_SEC_INTR_SHFT                                                             0x18
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_SEC_INTR_BMSK                                        0x800000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_SEC_INTR_SHFT                                            0x17
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SSC_SDC_XPU_SEC_INTR_BMSK                                                     0x400000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SSC_SDC_XPU_SEC_INTR_SHFT                                                         0x16
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_GCC_XPU_SEC_INTR_BMSK                                                         0x200000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_GCC_XPU_SEC_INTR_SHFT                                                             0x15
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_AOP_MPU_XPU_SEC_INTR_BMSK                                                     0x100000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_AOP_MPU_XPU_SEC_INTR_SHFT                                                         0x14
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QM_XPU_SEC_INTR_BMSK                                                           0x80000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QM_XPU_SEC_INTR_SHFT                                                              0x13
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QNM_SNOC_XPU_SEC_INTR_BMSK                                                     0x40000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QNM_SNOC_XPU_SEC_INTR_SHFT                                                        0x12
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QHS_CNOC_XPU_SEC_INTR_BMSK                                                     0x20000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QHS_CNOC_XPU_SEC_INTR_SHFT                                                        0x11
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QHM_AOSS_XPU_SEC_INTR_BMSK                                                     0x10000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QHM_AOSS_XPU_SEC_INTR_SHFT                                                        0x10
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SP_XPU_SEC_INTR_BMSK                                                            0x8000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SP_XPU_SEC_INTR_SHFT                                                               0xf
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_PIMEM_MPU_XPU_SEC_INTR_BMSK                                                     0x4000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_PIMEM_MPU_XPU_SEC_INTR_SHFT                                                        0xe
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_PIMEM_APU_XPU_SEC_INTR_BMSK                                                     0x2000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_PIMEM_APU_XPU_SEC_INTR_SHFT                                                        0xd
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SSC_Q6_XPU_SEC_INTR_BMSK                                                        0x1000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SSC_Q6_XPU_SEC_INTR_SHFT                                                           0xc
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SSC_XPU_SEC_INTR_BMSK                                                            0x800
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SSC_XPU_SEC_INTR_SHFT                                                              0xb
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SSC_QUP_XPU_SEC_INTR_BMSK                                                        0x400
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SSC_QUP_XPU_SEC_INTR_SHFT                                                          0xa
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SEC_CTRL_XPU_SEC_INTR_BMSK                                                       0x200
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SEC_CTRL_XPU_SEC_INTR_SHFT                                                         0x9
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_DCC_XPU_SEC_INTR_BMSK                                                            0x100
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_DCC_XPU_SEC_INTR_SHFT                                                              0x8
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_OCIMEM_RPU_XPU_SEC_INTR_BMSK                                                      0x80
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_OCIMEM_RPU_XPU_SEC_INTR_SHFT                                                       0x7
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_CRYPTO0_XPU_SEC_INTR_BMSK                                                         0x40
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_CRYPTO0_XPU_SEC_INTR_SHFT                                                          0x6
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_TCSR_MUTEX_XPU_SEC_INTR_BMSK                                                      0x20
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_TCSR_MUTEX_XPU_SEC_INTR_SHFT                                                       0x5
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QUPV3_1_XPU_SEC_INTR_BMSK                                                         0x10
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QUPV3_1_XPU_SEC_INTR_SHFT                                                          0x4
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_TCSR_REGS_XPU_SEC_INTR_BMSK                                                        0x8
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_TCSR_REGS_XPU_SEC_INTR_SHFT                                                        0x3
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QUPV3_0_XPU_SEC_INTR_BMSK                                                          0x4
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QUPV3_0_XPU_SEC_INTR_SHFT                                                          0x2
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_AOSS_MPU_XPU_SEC_INTR_BMSK                                                         0x2
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_AOSS_MPU_XPU_SEC_INTR_SHFT                                                         0x1
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_PMIC_ARB_XPU_SEC_INTR_BMSK                                                         0x1
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_PMIC_ARB_XPU_SEC_INTR_SHFT                                                         0x0

#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00004004)
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_OFFS                                                                        (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00004004)
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RMSK                                                                          0xffffff
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RESERVE_55_XPU_SEC_INTR_BMSK                                                  0x800000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RESERVE_55_XPU_SEC_INTR_SHFT                                                      0x17
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_4_SEC_INTR_BMSK                                                     0x400000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_4_SEC_INTR_SHFT                                                         0x16
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_3_SEC_INTR_BMSK                                                     0x200000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_3_SEC_INTR_SHFT                                                         0x15
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_2_SEC_INTR_BMSK                                                     0x100000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_2_SEC_INTR_SHFT                                                         0x14
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_1_SEC_INTR_BMSK                                                      0x80000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_1_SEC_INTR_SHFT                                                         0x13
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_0_SEC_INTR_BMSK                                                      0x40000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_0_SEC_INTR_SHFT                                                         0x12
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_QSPI_XPU_SEC_INTR_BMSK                                                         0x20000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_QSPI_XPU_SEC_INTR_SHFT                                                            0x11
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_IPC_ROUTER_XPU_SEC_INTR_BMSK                                                   0x10000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_IPC_ROUTER_XPU_SEC_INTR_SHFT                                                      0x10
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_TLMM_NORTH_XPU_SEC_INTR_BMSK                                                    0x8000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_TLMM_NORTH_XPU_SEC_INTR_SHFT                                                       0xf
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RESERVE_46_XPU_SEC_INTR_BMSK                                                    0x4000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RESERVE_46_XPU_SEC_INTR_SHFT                                                       0xe
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_DDRSS_SHRM_XPU_SEC_INTR_BMSK                                                    0x2000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_DDRSS_SHRM_XPU_SEC_INTR_SHFT                                                       0xd
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_QUPV3_2_XPU_SEC_INTR_BMSK                                                       0x1000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_QUPV3_2_XPU_SEC_INTR_SHFT                                                          0xc
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_IPA_XPU_SEC_INTR_BMSK                                                            0x800
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_IPA_XPU_SEC_INTR_SHFT                                                              0xb
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RESERVE_42_XPU_SEC_INTR_BMSK                                                     0x400
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RESERVE_42_XPU_SEC_INTR_SHFT                                                       0xa
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_TLMM_SOUTH_XPU_SEC_INTR_BMSK                                                     0x200
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_TLMM_SOUTH_XPU_SEC_INTR_SHFT                                                       0x9
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_TLMM_WEST_XPU_SEC_INTR_BMSK                                                      0x100
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_TLMM_WEST_XPU_SEC_INTR_SHFT                                                        0x8
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_MDSS_XPU_SEC_INTR_BMSK                                                            0x80
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_MDSS_XPU_SEC_INTR_SHFT                                                             0x7
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_UFS_CARD_ICE_XPU_SEC_INTR_BMSK                                                    0x40
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_UFS_CARD_ICE_XPU_SEC_INTR_SHFT                                                     0x6
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_TITAN_XPU_SEC_INTR_BMSK                                                           0x20
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_TITAN_XPU_SEC_INTR_SHFT                                                            0x5
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_SPDM_XPU_SEC_INTR_BMSK                                                            0x10
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_SPDM_XPU_SEC_INTR_SHFT                                                             0x4
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RESERVE_35_XPU_SEC_INTR_BMSK                                                       0x8
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RESERVE_35_XPU_SEC_INTR_SHFT                                                       0x3
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_QNM_AGGRE2_XPU_SEC_INTR_BMSK                                                       0x4
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_QNM_AGGRE2_XPU_SEC_INTR_SHFT                                                       0x2
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_QNM_AGGRE1_XPU_SEC_INTR_BMSK                                                       0x2
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_QNM_AGGRE1_XPU_SEC_INTR_SHFT                                                       0x1
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_OCIMEM_XPU3_XPU_SEC_INTR_BMSK                                                      0x1
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_OCIMEM_XPU3_XPU_SEC_INTR_SHFT                                                      0x0

#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_ADDR                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x00004040)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_OFFS                                                                      (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00004040)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_RMSK                                                                      0xffffffff
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SEC_INTR_ENABLE_BMSK                  0x80000000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SEC_INTR_ENABLE_SHFT                        0x1f
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_BOOT_ROM_XPU_SEC_INTR_ENABLE_BMSK                                         0x40000000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_BOOT_ROM_XPU_SEC_INTR_ENABLE_SHFT                                               0x1e
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SEC_INTR_ENABLE_BMSK                      0x20000000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SEC_INTR_ENABLE_SHFT                            0x1d
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_LLCC3_XPU_SEC_INTR_ENABLE_BMSK                                            0x10000000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_LLCC3_XPU_SEC_INTR_ENABLE_SHFT                                                  0x1c
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_LLCC2_XPU_SEC_INTR_ENABLE_BMSK                                             0x8000000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_LLCC2_XPU_SEC_INTR_ENABLE_SHFT                                                  0x1b
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_LLCC1_XPU_SEC_INTR_ENABLE_BMSK                                             0x4000000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_LLCC1_XPU_SEC_INTR_ENABLE_SHFT                                                  0x1a
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_LLCC0_XPU_SEC_INTR_ENABLE_BMSK                                             0x2000000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_LLCC0_XPU_SEC_INTR_ENABLE_SHFT                                                  0x19
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_UFS_XPU_SEC_INTR_ENABLE_BMSK                                               0x1000000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_UFS_XPU_SEC_INTR_ENABLE_SHFT                                                    0x18
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_SEC_INTR_ENABLE_BMSK                               0x800000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_SEC_INTR_ENABLE_SHFT                                   0x17
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_XPU_SEC_INTR_ENABLE_BMSK                                            0x400000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_XPU_SEC_INTR_ENABLE_SHFT                                                0x16
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_GCC_XPU_SEC_INTR_ENABLE_BMSK                                                0x200000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_GCC_XPU_SEC_INTR_ENABLE_SHFT                                                    0x15
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_AOP_MPU_XPU_SEC_INTR_ENABLE_BMSK                                            0x100000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_AOP_MPU_XPU_SEC_INTR_ENABLE_SHFT                                                0x14
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QM_XPU_SEC_INTR_ENABLE_BMSK                                                  0x80000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QM_XPU_SEC_INTR_ENABLE_SHFT                                                     0x13
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QNM_SNOC_XPU_SEC_INTR_ENABLE_BMSK                                            0x40000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QNM_SNOC_XPU_SEC_INTR_ENABLE_SHFT                                               0x12
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QHS_CNOC_XPU_SEC_INTR_ENABLE_BMSK                                            0x20000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QHS_CNOC_XPU_SEC_INTR_ENABLE_SHFT                                               0x11
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QHM_AOSS_XPU_SEC_INTR_ENABLE_BMSK                                            0x10000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QHM_AOSS_XPU_SEC_INTR_ENABLE_SHFT                                               0x10
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SP_XPU_SEC_INTR_ENABLE_BMSK                                                   0x8000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SP_XPU_SEC_INTR_ENABLE_SHFT                                                      0xf
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_PIMEM_MPU_XPU_SEC_INTR_ENABLE_BMSK                                            0x4000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_PIMEM_MPU_XPU_SEC_INTR_ENABLE_SHFT                                               0xe
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_PIMEM_APU_XPU_SEC_INTR_ENABLE_BMSK                                            0x2000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_PIMEM_APU_XPU_SEC_INTR_ENABLE_SHFT                                               0xd
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SSC_Q6_XPU_SEC_INTR_ENABLE_BMSK                                               0x1000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SSC_Q6_XPU_SEC_INTR_ENABLE_SHFT                                                  0xc
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SSC_XPU_SEC_INTR_ENABLE_BMSK                                                   0x800
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SSC_XPU_SEC_INTR_ENABLE_SHFT                                                     0xb
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SSC_QUP_XPU_SEC_INTR_ENABLE_BMSK                                               0x400
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SSC_QUP_XPU_SEC_INTR_ENABLE_SHFT                                                 0xa
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SEC_CTRL_XPU_SEC_INTR_ENABLE_BMSK                                              0x200
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SEC_CTRL_XPU_SEC_INTR_ENABLE_SHFT                                                0x9
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_DCC_XPU_SEC_INTR_ENABLE_BMSK                                                   0x100
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_DCC_XPU_SEC_INTR_ENABLE_SHFT                                                     0x8
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_OCIMEM_RPU_XPU_SEC_INTR_ENABLE_BMSK                                             0x80
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_OCIMEM_RPU_XPU_SEC_INTR_ENABLE_SHFT                                              0x7
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_XPU_SEC_INTR_ENABLE_BMSK                                                0x40
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_XPU_SEC_INTR_ENABLE_SHFT                                                 0x6
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_TCSR_MUTEX_XPU_SEC_INTR_ENABLE_BMSK                                             0x20
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_TCSR_MUTEX_XPU_SEC_INTR_ENABLE_SHFT                                              0x5
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_XPU_SEC_INTR_ENABLE_BMSK                                                0x10
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_XPU_SEC_INTR_ENABLE_SHFT                                                 0x4
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_TCSR_REGS_XPU_SEC_INTR_ENABLE_BMSK                                               0x8
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_TCSR_REGS_XPU_SEC_INTR_ENABLE_SHFT                                               0x3
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_XPU_SEC_INTR_ENABLE_BMSK                                                 0x4
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_XPU_SEC_INTR_ENABLE_SHFT                                                 0x2
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_AOSS_MPU_XPU_SEC_INTR_ENABLE_BMSK                                                0x2
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_AOSS_MPU_XPU_SEC_INTR_ENABLE_SHFT                                                0x1
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_PMIC_ARB_XPU_SEC_INTR_ENABLE_BMSK                                                0x1
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_PMIC_ARB_XPU_SEC_INTR_ENABLE_SHFT                                                0x0

#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_ADDR                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x00004044)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_OFFS                                                                      (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00004044)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RMSK                                                                        0xffffff
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RESERVE_55_XPU_SEC_INTR_ENABLE_BMSK                                         0x800000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RESERVE_55_XPU_SEC_INTR_ENABLE_SHFT                                             0x17
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_4_SEC_INTR_ENABLE_BMSK                                            0x400000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_4_SEC_INTR_ENABLE_SHFT                                                0x16
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_3_SEC_INTR_ENABLE_BMSK                                            0x200000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_3_SEC_INTR_ENABLE_SHFT                                                0x15
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_2_SEC_INTR_ENABLE_BMSK                                            0x100000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_2_SEC_INTR_ENABLE_SHFT                                                0x14
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_1_SEC_INTR_ENABLE_BMSK                                             0x80000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_1_SEC_INTR_ENABLE_SHFT                                                0x13
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_0_SEC_INTR_ENABLE_BMSK                                             0x40000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_0_SEC_INTR_ENABLE_SHFT                                                0x12
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_QSPI_XPU_SEC_INTR_ENABLE_BMSK                                                0x20000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_QSPI_XPU_SEC_INTR_ENABLE_SHFT                                                   0x11
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_IPC_ROUTER_XPU_SEC_INTR_ENABLE_BMSK                                          0x10000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_IPC_ROUTER_XPU_SEC_INTR_ENABLE_SHFT                                             0x10
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_TLMM_NORTH_XPU_SEC_INTR_ENABLE_BMSK                                           0x8000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_TLMM_NORTH_XPU_SEC_INTR_ENABLE_SHFT                                              0xf
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RESERVE_46_XPU_SEC_INTR_ENABLE_BMSK                                           0x4000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RESERVE_46_XPU_SEC_INTR_ENABLE_SHFT                                              0xe
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_DDRSS_SHRM_XPU_SEC_INTR_ENABLE_BMSK                                           0x2000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_DDRSS_SHRM_XPU_SEC_INTR_ENABLE_SHFT                                              0xd
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_QUPV3_2_XPU_SEC_INTR_ENABLE_BMSK                                              0x1000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_QUPV3_2_XPU_SEC_INTR_ENABLE_SHFT                                                 0xc
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_IPA_XPU_SEC_INTR_ENABLE_BMSK                                                   0x800
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_IPA_XPU_SEC_INTR_ENABLE_SHFT                                                     0xb
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RESERVE_42_XPU_SEC_INTR_ENABLE_BMSK                                            0x400
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RESERVE_42_XPU_SEC_INTR_ENABLE_SHFT                                              0xa
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_TLMM_SOUTH_XPU_SEC_INTR_ENABLE_BMSK                                            0x200
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_TLMM_SOUTH_XPU_SEC_INTR_ENABLE_SHFT                                              0x9
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_TLMM_WEST_XPU_SEC_INTR_ENABLE_BMSK                                             0x100
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_TLMM_WEST_XPU_SEC_INTR_ENABLE_SHFT                                               0x8
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_MDSS_XPU_SEC_INTR_ENABLE_BMSK                                                   0x80
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_MDSS_XPU_SEC_INTR_ENABLE_SHFT                                                    0x7
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_UFS_CARD_ICE_XPU_SEC_INTR_ENABLE_BMSK                                           0x40
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_UFS_CARD_ICE_XPU_SEC_INTR_ENABLE_SHFT                                            0x6
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_TITAN_XPU_SEC_INTR_ENABLE_BMSK                                                  0x20
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_TITAN_XPU_SEC_INTR_ENABLE_SHFT                                                   0x5
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_SPDM_XPU_SEC_INTR_ENABLE_BMSK                                                   0x10
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_SPDM_XPU_SEC_INTR_ENABLE_SHFT                                                    0x4
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RESERVE_35_XPU_SEC_INTR_ENABLE_BMSK                                              0x8
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RESERVE_35_XPU_SEC_INTR_ENABLE_SHFT                                              0x3
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_QNM_AGGRE2_XPU_SEC_INTR_ENABLE_BMSK                                              0x4
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_QNM_AGGRE2_XPU_SEC_INTR_ENABLE_SHFT                                              0x2
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_QNM_AGGRE1_XPU_SEC_INTR_ENABLE_BMSK                                              0x2
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_QNM_AGGRE1_XPU_SEC_INTR_ENABLE_SHFT                                              0x1
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_OCIMEM_XPU3_XPU_SEC_INTR_ENABLE_BMSK                                             0x1
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_OCIMEM_XPU3_XPU_SEC_INTR_ENABLE_SHFT                                             0x0

#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_ADDR                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x00002000)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_OFFS                                                                    (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00002000)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_RMSK                                                                    0xffffffff
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR_BMSK                   0x80000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR_SHFT                         0x1f
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_BOOT_ROM_XPU_NON_SEC_INTR_BMSK                                          0x40000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_BOOT_ROM_XPU_NON_SEC_INTR_SHFT                                                0x1e
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR_BMSK                       0x20000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR_SHFT                             0x1d
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_LLCC3_XPU_NON_SEC_INTR_BMSK                                             0x10000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_LLCC3_XPU_NON_SEC_INTR_SHFT                                                   0x1c
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_LLCC2_XPU_NON_SEC_INTR_BMSK                                              0x8000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_LLCC2_XPU_NON_SEC_INTR_SHFT                                                   0x1b
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_LLCC1_XPU_NON_SEC_INTR_BMSK                                              0x4000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_LLCC1_XPU_NON_SEC_INTR_SHFT                                                   0x1a
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_LLCC0_XPU_NON_SEC_INTR_BMSK                                              0x2000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_LLCC0_XPU_NON_SEC_INTR_SHFT                                                   0x19
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_UFS_XPU_NON_SEC_INTR_BMSK                                                0x1000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_UFS_XPU_NON_SEC_INTR_SHFT                                                     0x18
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_NON_SEC_INTR_BMSK                                0x800000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_NON_SEC_INTR_SHFT                                    0x17
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SSC_SDC_XPU_NON_SEC_INTR_BMSK                                             0x400000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SSC_SDC_XPU_NON_SEC_INTR_SHFT                                                 0x16
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_GCC_XPU_NON_SEC_INTR_BMSK                                                 0x200000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_GCC_XPU_NON_SEC_INTR_SHFT                                                     0x15
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_AOP_MPU_XPU_NON_SEC_INTR_BMSK                                             0x100000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_AOP_MPU_XPU_NON_SEC_INTR_SHFT                                                 0x14
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QM_XPU_NON_SEC_INTR_BMSK                                                   0x80000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QM_XPU_NON_SEC_INTR_SHFT                                                      0x13
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QNM_SNOC_XPU_NON_SEC_INTR_BMSK                                             0x40000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QNM_SNOC_XPU_NON_SEC_INTR_SHFT                                                0x12
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QHS_CNOC_XPU_NON_SEC_INTR_BMSK                                             0x20000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QHS_CNOC_XPU_NON_SEC_INTR_SHFT                                                0x11
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QHM_AOSS_XPU_NON_SEC_INTR_BMSK                                             0x10000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QHM_AOSS_XPU_NON_SEC_INTR_SHFT                                                0x10
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SP_XPU_NON_SEC_INTR_BMSK                                                    0x8000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SP_XPU_NON_SEC_INTR_SHFT                                                       0xf
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_PIMEM_MPU_XPU_NON_SEC_INTR_BMSK                                             0x4000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_PIMEM_MPU_XPU_NON_SEC_INTR_SHFT                                                0xe
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_PIMEM_APU_XPU_NON_SEC_INTR_BMSK                                             0x2000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_PIMEM_APU_XPU_NON_SEC_INTR_SHFT                                                0xd
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SSC_Q6_XPU_NON_SEC_INTR_BMSK                                                0x1000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SSC_Q6_XPU_NON_SEC_INTR_SHFT                                                   0xc
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SSC_XPU_NON_SEC_INTR_BMSK                                                    0x800
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SSC_XPU_NON_SEC_INTR_SHFT                                                      0xb
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SSC_QUP_XPU_NON_SEC_INTR_BMSK                                                0x400
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SSC_QUP_XPU_NON_SEC_INTR_SHFT                                                  0xa
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SEC_CTRL_XPU_NON_SEC_INTR_BMSK                                               0x200
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SEC_CTRL_XPU_NON_SEC_INTR_SHFT                                                 0x9
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_DCC_XPU_NON_SEC_INTR_BMSK                                                    0x100
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_DCC_XPU_NON_SEC_INTR_SHFT                                                      0x8
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_OCIMEM_RPU_XPU_NON_SEC_INTR_BMSK                                              0x80
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_OCIMEM_RPU_XPU_NON_SEC_INTR_SHFT                                               0x7
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_CRYPTO0_XPU_NON_SEC_INTR_BMSK                                                 0x40
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_CRYPTO0_XPU_NON_SEC_INTR_SHFT                                                  0x6
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_TCSR_MUTEX_XPU_NON_SEC_INTR_BMSK                                              0x20
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_TCSR_MUTEX_XPU_NON_SEC_INTR_SHFT                                               0x5
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QUPV3_1_XPU_NON_SEC_INTR_BMSK                                                 0x10
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QUPV3_1_XPU_NON_SEC_INTR_SHFT                                                  0x4
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_TCSR_REGS_XPU_NON_SEC_INTR_BMSK                                                0x8
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_TCSR_REGS_XPU_NON_SEC_INTR_SHFT                                                0x3
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QUPV3_0_XPU_NON_SEC_INTR_BMSK                                                  0x4
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QUPV3_0_XPU_NON_SEC_INTR_SHFT                                                  0x2
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_AOSS_MPU_XPU_NON_SEC_INTR_BMSK                                                 0x2
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_AOSS_MPU_XPU_NON_SEC_INTR_SHFT                                                 0x1
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_PMIC_ARB_XPU_NON_SEC_INTR_BMSK                                                 0x1
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_PMIC_ARB_XPU_NON_SEC_INTR_SHFT                                                 0x0

#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_ADDR                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x00002004)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_OFFS                                                                    (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00002004)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RMSK                                                                      0xffffff
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RESERVE_55_XPU_NON_SEC_INTR_BMSK                                          0x800000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RESERVE_55_XPU_NON_SEC_INTR_SHFT                                              0x17
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_4_NON_SEC_INTR_BMSK                                             0x400000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_4_NON_SEC_INTR_SHFT                                                 0x16
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_3_NON_SEC_INTR_BMSK                                             0x200000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_3_NON_SEC_INTR_SHFT                                                 0x15
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_2_NON_SEC_INTR_BMSK                                             0x100000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_2_NON_SEC_INTR_SHFT                                                 0x14
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_1_NON_SEC_INTR_BMSK                                              0x80000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_1_NON_SEC_INTR_SHFT                                                 0x13
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_0_NON_SEC_INTR_BMSK                                              0x40000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_0_NON_SEC_INTR_SHFT                                                 0x12
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_QSPI_XPU_NON_SEC_INTR_BMSK                                                 0x20000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_QSPI_XPU_NON_SEC_INTR_SHFT                                                    0x11
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_IPC_ROUTER_XPU_NON_SEC_INTR_BMSK                                           0x10000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_IPC_ROUTER_XPU_NON_SEC_INTR_SHFT                                              0x10
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_TLMM_NORTH_XPU_NON_SEC_INTR_BMSK                                            0x8000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_TLMM_NORTH_XPU_NON_SEC_INTR_SHFT                                               0xf
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RESERVE_46_XPU_NON_SEC_INTR_BMSK                                            0x4000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RESERVE_46_XPU_NON_SEC_INTR_SHFT                                               0xe
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_DDRSS_SHRM_XPU_NON_SEC_INTR_BMSK                                            0x2000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_DDRSS_SHRM_XPU_NON_SEC_INTR_SHFT                                               0xd
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_QUPV3_2_XPU_NON_SEC_INTR_BMSK                                               0x1000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_QUPV3_2_XPU_NON_SEC_INTR_SHFT                                                  0xc
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_IPA_XPU_NON_SEC_INTR_BMSK                                                    0x800
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_IPA_XPU_NON_SEC_INTR_SHFT                                                      0xb
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RESERVE_42_XPU_NON_SEC_INTR_BMSK                                             0x400
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RESERVE_42_XPU_NON_SEC_INTR_SHFT                                               0xa
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_TLMM_SOUTH_XPU_NON_SEC_INTR_BMSK                                             0x200
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_TLMM_SOUTH_XPU_NON_SEC_INTR_SHFT                                               0x9
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_TLMM_WEST_XPU_NON_SEC_INTR_BMSK                                              0x100
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_TLMM_WEST_XPU_NON_SEC_INTR_SHFT                                                0x8
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_MDSS_XPU_NON_SEC_INTR_BMSK                                                    0x80
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_MDSS_XPU_NON_SEC_INTR_SHFT                                                     0x7
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_UFS_CARD_ICE_XPU_NON_SEC_INTR_BMSK                                            0x40
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_UFS_CARD_ICE_XPU_NON_SEC_INTR_SHFT                                             0x6
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_TITAN_XPU_NON_SEC_INTR_BMSK                                                   0x20
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_TITAN_XPU_NON_SEC_INTR_SHFT                                                    0x5
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_SPDM_XPU_NON_SEC_INTR_BMSK                                                    0x10
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_SPDM_XPU_NON_SEC_INTR_SHFT                                                     0x4
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RESERVE_35_XPU_NON_SEC_INTR_BMSK                                               0x8
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RESERVE_35_XPU_NON_SEC_INTR_SHFT                                               0x3
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_QNM_AGGRE2_XPU_NON_SEC_INTR_BMSK                                               0x4
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_QNM_AGGRE2_XPU_NON_SEC_INTR_SHFT                                               0x2
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_QNM_AGGRE1_XPU_NON_SEC_INTR_BMSK                                               0x2
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_QNM_AGGRE1_XPU_NON_SEC_INTR_SHFT                                               0x1
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_OCIMEM_XPU3_XPU_NON_SEC_INTR_BMSK                                              0x1
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_OCIMEM_XPU3_XPU_NON_SEC_INTR_SHFT                                              0x0

#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00002040)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_OFFS                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00002040)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_RMSK                                                                  0xffffffff
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR_ENABLE_BMSK          0x80000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR_ENABLE_SHFT                0x1f
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_BOOT_ROM_XPU_NON_SEC_INTR_ENABLE_BMSK                                 0x40000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_BOOT_ROM_XPU_NON_SEC_INTR_ENABLE_SHFT                                       0x1e
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR_ENABLE_BMSK              0x20000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR_ENABLE_SHFT                    0x1d
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_LLCC3_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x10000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_LLCC3_XPU_NON_SEC_INTR_ENABLE_SHFT                                          0x1c
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_LLCC2_XPU_NON_SEC_INTR_ENABLE_BMSK                                     0x8000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_LLCC2_XPU_NON_SEC_INTR_ENABLE_SHFT                                          0x1b
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_LLCC1_XPU_NON_SEC_INTR_ENABLE_BMSK                                     0x4000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_LLCC1_XPU_NON_SEC_INTR_ENABLE_SHFT                                          0x1a
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_LLCC0_XPU_NON_SEC_INTR_ENABLE_BMSK                                     0x2000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_LLCC0_XPU_NON_SEC_INTR_ENABLE_SHFT                                          0x19
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_UFS_XPU_NON_SEC_INTR_ENABLE_BMSK                                       0x1000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_UFS_XPU_NON_SEC_INTR_ENABLE_SHFT                                            0x18
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_NON_SEC_INTR_ENABLE_BMSK                       0x800000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_NON_SEC_INTR_ENABLE_SHFT                           0x17
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x400000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_XPU_NON_SEC_INTR_ENABLE_SHFT                                        0x16
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_GCC_XPU_NON_SEC_INTR_ENABLE_BMSK                                        0x200000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_GCC_XPU_NON_SEC_INTR_ENABLE_SHFT                                            0x15
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_AOP_MPU_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x100000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_AOP_MPU_XPU_NON_SEC_INTR_ENABLE_SHFT                                        0x14
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QM_XPU_NON_SEC_INTR_ENABLE_BMSK                                          0x80000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QM_XPU_NON_SEC_INTR_ENABLE_SHFT                                             0x13
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QNM_SNOC_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x40000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QNM_SNOC_XPU_NON_SEC_INTR_ENABLE_SHFT                                       0x12
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QHS_CNOC_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x20000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QHS_CNOC_XPU_NON_SEC_INTR_ENABLE_SHFT                                       0x11
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QHM_AOSS_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x10000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QHM_AOSS_XPU_NON_SEC_INTR_ENABLE_SHFT                                       0x10
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SP_XPU_NON_SEC_INTR_ENABLE_BMSK                                           0x8000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SP_XPU_NON_SEC_INTR_ENABLE_SHFT                                              0xf
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_PIMEM_MPU_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x4000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_PIMEM_MPU_XPU_NON_SEC_INTR_ENABLE_SHFT                                       0xe
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_PIMEM_APU_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x2000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_PIMEM_APU_XPU_NON_SEC_INTR_ENABLE_SHFT                                       0xd
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_Q6_XPU_NON_SEC_INTR_ENABLE_BMSK                                       0x1000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_Q6_XPU_NON_SEC_INTR_ENABLE_SHFT                                          0xc
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_XPU_NON_SEC_INTR_ENABLE_BMSK                                           0x800
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_XPU_NON_SEC_INTR_ENABLE_SHFT                                             0xb
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_QUP_XPU_NON_SEC_INTR_ENABLE_BMSK                                       0x400
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_QUP_XPU_NON_SEC_INTR_ENABLE_SHFT                                         0xa
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SEC_CTRL_XPU_NON_SEC_INTR_ENABLE_BMSK                                      0x200
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SEC_CTRL_XPU_NON_SEC_INTR_ENABLE_SHFT                                        0x9
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_DCC_XPU_NON_SEC_INTR_ENABLE_BMSK                                           0x100
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_DCC_XPU_NON_SEC_INTR_ENABLE_SHFT                                             0x8
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_OCIMEM_RPU_XPU_NON_SEC_INTR_ENABLE_BMSK                                     0x80
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_OCIMEM_RPU_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0x7
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_XPU_NON_SEC_INTR_ENABLE_BMSK                                        0x40
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_XPU_NON_SEC_INTR_ENABLE_SHFT                                         0x6
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_TCSR_MUTEX_XPU_NON_SEC_INTR_ENABLE_BMSK                                     0x20
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_TCSR_MUTEX_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0x5
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_XPU_NON_SEC_INTR_ENABLE_BMSK                                        0x10
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_XPU_NON_SEC_INTR_ENABLE_SHFT                                         0x4
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_TCSR_REGS_XPU_NON_SEC_INTR_ENABLE_BMSK                                       0x8
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_TCSR_REGS_XPU_NON_SEC_INTR_ENABLE_SHFT                                       0x3
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_XPU_NON_SEC_INTR_ENABLE_BMSK                                         0x4
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_XPU_NON_SEC_INTR_ENABLE_SHFT                                         0x2
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_AOSS_MPU_XPU_NON_SEC_INTR_ENABLE_BMSK                                        0x2
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_AOSS_MPU_XPU_NON_SEC_INTR_ENABLE_SHFT                                        0x1
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_PMIC_ARB_XPU_NON_SEC_INTR_ENABLE_BMSK                                        0x1
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_PMIC_ARB_XPU_NON_SEC_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00002044)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_OFFS                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00002044)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RMSK                                                                    0xffffff
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RESERVE_55_XPU_NON_SEC_INTR_ENABLE_BMSK                                 0x800000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RESERVE_55_XPU_NON_SEC_INTR_ENABLE_SHFT                                     0x17
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_4_NON_SEC_INTR_ENABLE_BMSK                                    0x400000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_4_NON_SEC_INTR_ENABLE_SHFT                                        0x16
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_3_NON_SEC_INTR_ENABLE_BMSK                                    0x200000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_3_NON_SEC_INTR_ENABLE_SHFT                                        0x15
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_2_NON_SEC_INTR_ENABLE_BMSK                                    0x100000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_2_NON_SEC_INTR_ENABLE_SHFT                                        0x14
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_1_NON_SEC_INTR_ENABLE_BMSK                                     0x80000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_1_NON_SEC_INTR_ENABLE_SHFT                                        0x13
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_0_NON_SEC_INTR_ENABLE_BMSK                                     0x40000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_0_NON_SEC_INTR_ENABLE_SHFT                                        0x12
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_QSPI_XPU_NON_SEC_INTR_ENABLE_BMSK                                        0x20000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_QSPI_XPU_NON_SEC_INTR_ENABLE_SHFT                                           0x11
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_IPC_ROUTER_XPU_NON_SEC_INTR_ENABLE_BMSK                                  0x10000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_IPC_ROUTER_XPU_NON_SEC_INTR_ENABLE_SHFT                                     0x10
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_TLMM_NORTH_XPU_NON_SEC_INTR_ENABLE_BMSK                                   0x8000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_TLMM_NORTH_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0xf
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RESERVE_46_XPU_NON_SEC_INTR_ENABLE_BMSK                                   0x4000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RESERVE_46_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0xe
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_DDRSS_SHRM_XPU_NON_SEC_INTR_ENABLE_BMSK                                   0x2000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_DDRSS_SHRM_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0xd
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_QUPV3_2_XPU_NON_SEC_INTR_ENABLE_BMSK                                      0x1000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_QUPV3_2_XPU_NON_SEC_INTR_ENABLE_SHFT                                         0xc
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_IPA_XPU_NON_SEC_INTR_ENABLE_BMSK                                           0x800
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_IPA_XPU_NON_SEC_INTR_ENABLE_SHFT                                             0xb
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RESERVE_42_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x400
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RESERVE_42_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0xa
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_TLMM_SOUTH_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x200
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_TLMM_SOUTH_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0x9
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_TLMM_WEST_XPU_NON_SEC_INTR_ENABLE_BMSK                                     0x100
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_TLMM_WEST_XPU_NON_SEC_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_MDSS_XPU_NON_SEC_INTR_ENABLE_BMSK                                           0x80
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_MDSS_XPU_NON_SEC_INTR_ENABLE_SHFT                                            0x7
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_UFS_CARD_ICE_XPU_NON_SEC_INTR_ENABLE_BMSK                                   0x40
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_UFS_CARD_ICE_XPU_NON_SEC_INTR_ENABLE_SHFT                                    0x6
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_TITAN_XPU_NON_SEC_INTR_ENABLE_BMSK                                          0x20
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_TITAN_XPU_NON_SEC_INTR_ENABLE_SHFT                                           0x5
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_SPDM_XPU_NON_SEC_INTR_ENABLE_BMSK                                           0x10
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_SPDM_XPU_NON_SEC_INTR_ENABLE_SHFT                                            0x4
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RESERVE_35_XPU_NON_SEC_INTR_ENABLE_BMSK                                      0x8
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RESERVE_35_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0x3
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_QNM_AGGRE2_XPU_NON_SEC_INTR_ENABLE_BMSK                                      0x4
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_QNM_AGGRE2_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0x2
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_QNM_AGGRE1_XPU_NON_SEC_INTR_ENABLE_BMSK                                      0x2
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_QNM_AGGRE1_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0x1
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_OCIMEM_XPU3_XPU_NON_SEC_INTR_ENABLE_BMSK                                     0x1
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_OCIMEM_XPU3_XPU_NON_SEC_INTR_ENABLE_SHFT                                     0x0

#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00006000)
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_OFFS                                                                        (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00006000)
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_RMSK                                                                        0xffffffff
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_MSA_INTR_BMSK                           0x80000000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_MSA_INTR_SHFT                                 0x1f
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_BOOT_ROM_XPU_MSA_INTR_BMSK                                                  0x40000000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_BOOT_ROM_XPU_MSA_INTR_SHFT                                                        0x1e
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_MSA_INTR_BMSK                               0x20000000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_MSA_INTR_SHFT                                     0x1d
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_LLCC3_XPU_MSA_INTR_BMSK                                                     0x10000000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_LLCC3_XPU_MSA_INTR_SHFT                                                           0x1c
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_LLCC2_XPU_MSA_INTR_BMSK                                                      0x8000000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_LLCC2_XPU_MSA_INTR_SHFT                                                           0x1b
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_LLCC1_XPU_MSA_INTR_BMSK                                                      0x4000000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_LLCC1_XPU_MSA_INTR_SHFT                                                           0x1a
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_LLCC0_XPU_MSA_INTR_BMSK                                                      0x2000000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_LLCC0_XPU_MSA_INTR_SHFT                                                           0x19
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_UFS_XPU_MSA_INTR_BMSK                                                        0x1000000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_UFS_XPU_MSA_INTR_SHFT                                                             0x18
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_MSA_INTR_BMSK                                        0x800000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_MSA_INTR_SHFT                                            0x17
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SSC_SDC_XPU_MSA_INTR_BMSK                                                     0x400000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SSC_SDC_XPU_MSA_INTR_SHFT                                                         0x16
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_GCC_XPU_MSA_INTR_BMSK                                                         0x200000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_GCC_XPU_MSA_INTR_SHFT                                                             0x15
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_AOP_MPU_XPU_MSA_INTR_BMSK                                                     0x100000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_AOP_MPU_XPU_MSA_INTR_SHFT                                                         0x14
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QM_XPU_MSA_INTR_BMSK                                                           0x80000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QM_XPU_MSA_INTR_SHFT                                                              0x13
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QNM_SNOC_XPU_MSA_INTR_BMSK                                                     0x40000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QNM_SNOC_XPU_MSA_INTR_SHFT                                                        0x12
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QHS_CNOC_XPU_MSA_INTR_BMSK                                                     0x20000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QHS_CNOC_XPU_MSA_INTR_SHFT                                                        0x11
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QHM_AOSS_XPU_MSA_INTR_BMSK                                                     0x10000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QHM_AOSS_XPU_MSA_INTR_SHFT                                                        0x10
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SP_XPU_MSA_INTR_BMSK                                                            0x8000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SP_XPU_MSA_INTR_SHFT                                                               0xf
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_PIMEM_MPU_XPU_MSA_INTR_BMSK                                                     0x4000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_PIMEM_MPU_XPU_MSA_INTR_SHFT                                                        0xe
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_PIMEM_APU_XPU_MSA_INTR_BMSK                                                     0x2000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_PIMEM_APU_XPU_MSA_INTR_SHFT                                                        0xd
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SSC_Q6_XPU_MSA_INTR_BMSK                                                        0x1000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SSC_Q6_XPU_MSA_INTR_SHFT                                                           0xc
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SSC_XPU_MSA_INTR_BMSK                                                            0x800
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SSC_XPU_MSA_INTR_SHFT                                                              0xb
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SSC_QUP_XPU_MSA_INTR_BMSK                                                        0x400
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SSC_QUP_XPU_MSA_INTR_SHFT                                                          0xa
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SEC_CTRL_XPU_MSA_INTR_BMSK                                                       0x200
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SEC_CTRL_XPU_MSA_INTR_SHFT                                                         0x9
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_DCC_XPU_MSA_INTR_BMSK                                                            0x100
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_DCC_XPU_MSA_INTR_SHFT                                                              0x8
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_OCIMEM_RPU_XPU_MSA_INTR_BMSK                                                      0x80
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_OCIMEM_RPU_XPU_MSA_INTR_SHFT                                                       0x7
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_CRYPTO0_XPU_MSA_INTR_BMSK                                                         0x40
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_CRYPTO0_XPU_MSA_INTR_SHFT                                                          0x6
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_TCSR_MUTEX_XPU_MSA_INTR_BMSK                                                      0x20
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_TCSR_MUTEX_XPU_MSA_INTR_SHFT                                                       0x5
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QUPV3_1_XPU_MSA_INTR_BMSK                                                         0x10
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QUPV3_1_XPU_MSA_INTR_SHFT                                                          0x4
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_TCSR_REGS_XPU_MSA_INTR_BMSK                                                        0x8
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_TCSR_REGS_XPU_MSA_INTR_SHFT                                                        0x3
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QUPV3_0_XPU_MSA_INTR_BMSK                                                          0x4
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QUPV3_0_XPU_MSA_INTR_SHFT                                                          0x2
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_AOSS_MPU_XPU_MSA_INTR_BMSK                                                         0x2
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_AOSS_MPU_XPU_MSA_INTR_SHFT                                                         0x1
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_PMIC_ARB_XPU_MSA_INTR_BMSK                                                         0x1
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_PMIC_ARB_XPU_MSA_INTR_SHFT                                                         0x0

#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00006004)
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_OFFS                                                                        (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00006004)
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RMSK                                                                          0xffffff
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RESERVE_55_XPU_MSA_INTR_BMSK                                                  0x800000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RESERVE_55_XPU_MSA_INTR_SHFT                                                      0x17
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_4_MSA_INTR_BMSK                                                     0x400000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_4_MSA_INTR_SHFT                                                         0x16
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_3_MSA_INTR_BMSK                                                     0x200000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_3_MSA_INTR_SHFT                                                         0x15
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_2_MSA_INTR_BMSK                                                     0x100000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_2_MSA_INTR_SHFT                                                         0x14
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_1_MSA_INTR_BMSK                                                      0x80000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_1_MSA_INTR_SHFT                                                         0x13
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_0_MSA_INTR_BMSK                                                      0x40000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_0_MSA_INTR_SHFT                                                         0x12
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_QSPI_XPU_MSA_INTR_BMSK                                                         0x20000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_QSPI_XPU_MSA_INTR_SHFT                                                            0x11
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_IPC_ROUTER_XPU_MSA_INTR_BMSK                                                   0x10000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_IPC_ROUTER_XPU_MSA_INTR_SHFT                                                      0x10
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_TLMM_NORTH_XPU_MSA_INTR_BMSK                                                    0x8000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_TLMM_NORTH_XPU_MSA_INTR_SHFT                                                       0xf
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RESERVE_46_XPU_MSA_INTR_BMSK                                                    0x4000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RESERVE_46_XPU_MSA_INTR_SHFT                                                       0xe
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_DDRSS_SHRM_XPU_MSA_INTR_BMSK                                                    0x2000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_DDRSS_SHRM_XPU_MSA_INTR_SHFT                                                       0xd
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_QUPV3_2_XPU_MSA_INTR_BMSK                                                       0x1000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_QUPV3_2_XPU_MSA_INTR_SHFT                                                          0xc
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_IPA_XPU_MSA_INTR_BMSK                                                            0x800
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_IPA_XPU_MSA_INTR_SHFT                                                              0xb
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RESERVE_42_XPU_MSA_INTR_BMSK                                                     0x400
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RESERVE_42_XPU_MSA_INTR_SHFT                                                       0xa
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_TLMM_SOUTH_XPU_MSA_INTR_BMSK                                                     0x200
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_TLMM_SOUTH_XPU_MSA_INTR_SHFT                                                       0x9
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_TLMM_WEST_XPU_MSA_INTR_BMSK                                                      0x100
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_TLMM_WEST_XPU_MSA_INTR_SHFT                                                        0x8
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_MDSS_XPU_MSA_INTR_BMSK                                                            0x80
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_MDSS_XPU_MSA_INTR_SHFT                                                             0x7
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_UFS_CARD_ICE_XPU_MSA_INTR_BMSK                                                    0x40
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_UFS_CARD_ICE_XPU_MSA_INTR_SHFT                                                     0x6
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_TITAN_XPU_MSA_INTR_BMSK                                                           0x20
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_TITAN_XPU_MSA_INTR_SHFT                                                            0x5
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_SPDM_XPU_MSA_INTR_BMSK                                                            0x10
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_SPDM_XPU_MSA_INTR_SHFT                                                             0x4
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RESERVE_35_XPU_MSA_INTR_BMSK                                                       0x8
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RESERVE_35_XPU_MSA_INTR_SHFT                                                       0x3
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_QNM_AGGRE2_XPU_MSA_INTR_BMSK                                                       0x4
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_QNM_AGGRE2_XPU_MSA_INTR_SHFT                                                       0x2
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_QNM_AGGRE1_XPU_MSA_INTR_BMSK                                                       0x2
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_QNM_AGGRE1_XPU_MSA_INTR_SHFT                                                       0x1
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_OCIMEM_XPU3_XPU_MSA_INTR_BMSK                                                      0x1
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_OCIMEM_XPU3_XPU_MSA_INTR_SHFT                                                      0x0

#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_ADDR                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x00006040)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_OFFS                                                                      (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00006040)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_RMSK                                                                      0xffffffff
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_MSA_INTR_ENABLE_BMSK                  0x80000000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_MSA_INTR_ENABLE_SHFT                        0x1f
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_BOOT_ROM_XPU_MSA_INTR_ENABLE_BMSK                                         0x40000000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_BOOT_ROM_XPU_MSA_INTR_ENABLE_SHFT                                               0x1e
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_MSA_INTR_ENABLE_BMSK                      0x20000000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_MSA_INTR_ENABLE_SHFT                            0x1d
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_LLCC3_XPU_MSA_INTR_ENABLE_BMSK                                            0x10000000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_LLCC3_XPU_MSA_INTR_ENABLE_SHFT                                                  0x1c
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_LLCC2_XPU_MSA_INTR_ENABLE_BMSK                                             0x8000000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_LLCC2_XPU_MSA_INTR_ENABLE_SHFT                                                  0x1b
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_LLCC1_XPU_MSA_INTR_ENABLE_BMSK                                             0x4000000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_LLCC1_XPU_MSA_INTR_ENABLE_SHFT                                                  0x1a
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_LLCC0_XPU_MSA_INTR_ENABLE_BMSK                                             0x2000000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_LLCC0_XPU_MSA_INTR_ENABLE_SHFT                                                  0x19
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_UFS_XPU_MSA_INTR_ENABLE_BMSK                                               0x1000000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_UFS_XPU_MSA_INTR_ENABLE_SHFT                                                    0x18
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_MSA_INTR_ENABLE_BMSK                               0x800000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_MSA_INTR_ENABLE_SHFT                                   0x17
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SSC_SDC_XPU_MSA_INTR_ENABLE_BMSK                                            0x400000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SSC_SDC_XPU_MSA_INTR_ENABLE_SHFT                                                0x16
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_GCC_XPU_MSA_INTR_ENABLE_BMSK                                                0x200000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_GCC_XPU_MSA_INTR_ENABLE_SHFT                                                    0x15
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_AOP_MPU_XPU_MSA_INTR_ENABLE_BMSK                                            0x100000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_AOP_MPU_XPU_MSA_INTR_ENABLE_SHFT                                                0x14
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QM_XPU_MSA_INTR_ENABLE_BMSK                                                  0x80000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QM_XPU_MSA_INTR_ENABLE_SHFT                                                     0x13
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QNM_SNOC_XPU_MSA_INTR_ENABLE_BMSK                                            0x40000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QNM_SNOC_XPU_MSA_INTR_ENABLE_SHFT                                               0x12
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QHS_CNOC_XPU_MSA_INTR_ENABLE_BMSK                                            0x20000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QHS_CNOC_XPU_MSA_INTR_ENABLE_SHFT                                               0x11
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QHM_AOSS_XPU_MSA_INTR_ENABLE_BMSK                                            0x10000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QHM_AOSS_XPU_MSA_INTR_ENABLE_SHFT                                               0x10
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SP_XPU_MSA_INTR_ENABLE_BMSK                                                   0x8000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SP_XPU_MSA_INTR_ENABLE_SHFT                                                      0xf
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_PIMEM_MPU_XPU_MSA_INTR_ENABLE_BMSK                                            0x4000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_PIMEM_MPU_XPU_MSA_INTR_ENABLE_SHFT                                               0xe
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_PIMEM_APU_XPU_MSA_INTR_ENABLE_BMSK                                            0x2000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_PIMEM_APU_XPU_MSA_INTR_ENABLE_SHFT                                               0xd
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SSC_Q6_XPU_MSA_INTR_ENABLE_BMSK                                               0x1000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SSC_Q6_XPU_MSA_INTR_ENABLE_SHFT                                                  0xc
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SSC_XPU_MSA_INTR_ENABLE_BMSK                                                   0x800
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SSC_XPU_MSA_INTR_ENABLE_SHFT                                                     0xb
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SSC_QUP_XPU_MSA_INTR_ENABLE_BMSK                                               0x400
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SSC_QUP_XPU_MSA_INTR_ENABLE_SHFT                                                 0xa
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SEC_CTRL_XPU_MSA_INTR_ENABLE_BMSK                                              0x200
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SEC_CTRL_XPU_MSA_INTR_ENABLE_SHFT                                                0x9
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_DCC_XPU_MSA_INTR_ENABLE_BMSK                                                   0x100
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_DCC_XPU_MSA_INTR_ENABLE_SHFT                                                     0x8
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_OCIMEM_RPU_XPU_MSA_INTR_ENABLE_BMSK                                             0x80
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_OCIMEM_RPU_XPU_MSA_INTR_ENABLE_SHFT                                              0x7
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_CRYPTO0_XPU_MSA_INTR_ENABLE_BMSK                                                0x40
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_CRYPTO0_XPU_MSA_INTR_ENABLE_SHFT                                                 0x6
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_TCSR_MUTEX_XPU_MSA_INTR_ENABLE_BMSK                                             0x20
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_TCSR_MUTEX_XPU_MSA_INTR_ENABLE_SHFT                                              0x5
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QUPV3_1_XPU_MSA_INTR_ENABLE_BMSK                                                0x10
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QUPV3_1_XPU_MSA_INTR_ENABLE_SHFT                                                 0x4
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_TCSR_REGS_XPU_MSA_INTR_ENABLE_BMSK                                               0x8
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_TCSR_REGS_XPU_MSA_INTR_ENABLE_SHFT                                               0x3
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QUPV3_0_XPU_MSA_INTR_ENABLE_BMSK                                                 0x4
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QUPV3_0_XPU_MSA_INTR_ENABLE_SHFT                                                 0x2
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_AOSS_MPU_XPU_MSA_INTR_ENABLE_BMSK                                                0x2
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_AOSS_MPU_XPU_MSA_INTR_ENABLE_SHFT                                                0x1
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_PMIC_ARB_XPU_MSA_INTR_ENABLE_BMSK                                                0x1
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_PMIC_ARB_XPU_MSA_INTR_ENABLE_SHFT                                                0x0

#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_ADDR                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x00006044)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_OFFS                                                                      (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00006044)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RMSK                                                                        0xffffff
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RESERVE_55_XPU_MSA_INTR_ENABLE_BMSK                                         0x800000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RESERVE_55_XPU_MSA_INTR_ENABLE_SHFT                                             0x17
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_4_MSA_INTR_ENABLE_BMSK                                            0x400000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_4_MSA_INTR_ENABLE_SHFT                                                0x16
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_3_MSA_INTR_ENABLE_BMSK                                            0x200000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_3_MSA_INTR_ENABLE_SHFT                                                0x15
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_2_MSA_INTR_ENABLE_BMSK                                            0x100000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_2_MSA_INTR_ENABLE_SHFT                                                0x14
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_1_MSA_INTR_ENABLE_BMSK                                             0x80000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_1_MSA_INTR_ENABLE_SHFT                                                0x13
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_0_MSA_INTR_ENABLE_BMSK                                             0x40000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_0_MSA_INTR_ENABLE_SHFT                                                0x12
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_QSPI_XPU_MSA_INTR_ENABLE_BMSK                                                0x20000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_QSPI_XPU_MSA_INTR_ENABLE_SHFT                                                   0x11
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_IPC_ROUTER_XPU_MSA_INTR_ENABLE_BMSK                                          0x10000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_IPC_ROUTER_XPU_MSA_INTR_ENABLE_SHFT                                             0x10
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_TLMM_NORTH_XPU_MSA_INTR_ENABLE_BMSK                                           0x8000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_TLMM_NORTH_XPU_MSA_INTR_ENABLE_SHFT                                              0xf
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RESERVE_46_XPU_MSA_INTR_ENABLE_BMSK                                           0x4000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RESERVE_46_XPU_MSA_INTR_ENABLE_SHFT                                              0xe
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_DDRSS_SHRM_XPU_MSA_INTR_ENABLE_BMSK                                           0x2000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_DDRSS_SHRM_XPU_MSA_INTR_ENABLE_SHFT                                              0xd
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_QUPV3_2_XPU_MSA_INTR_ENABLE_BMSK                                              0x1000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_QUPV3_2_XPU_MSA_INTR_ENABLE_SHFT                                                 0xc
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_IPA_XPU_MSA_INTR_ENABLE_BMSK                                                   0x800
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_IPA_XPU_MSA_INTR_ENABLE_SHFT                                                     0xb
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RESERVE_42_XPU_MSA_INTR_ENABLE_BMSK                                            0x400
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RESERVE_42_XPU_MSA_INTR_ENABLE_SHFT                                              0xa
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_TLMM_SOUTH_XPU_MSA_INTR_ENABLE_BMSK                                            0x200
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_TLMM_SOUTH_XPU_MSA_INTR_ENABLE_SHFT                                              0x9
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_TLMM_WEST_XPU_MSA_INTR_ENABLE_BMSK                                             0x100
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_TLMM_WEST_XPU_MSA_INTR_ENABLE_SHFT                                               0x8
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_MDSS_XPU_MSA_INTR_ENABLE_BMSK                                                   0x80
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_MDSS_XPU_MSA_INTR_ENABLE_SHFT                                                    0x7
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_UFS_CARD_ICE_XPU_MSA_INTR_ENABLE_BMSK                                           0x40
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_UFS_CARD_ICE_XPU_MSA_INTR_ENABLE_SHFT                                            0x6
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_TITAN_XPU_MSA_INTR_ENABLE_BMSK                                                  0x20
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_TITAN_XPU_MSA_INTR_ENABLE_SHFT                                                   0x5
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_SPDM_XPU_MSA_INTR_ENABLE_BMSK                                                   0x10
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_SPDM_XPU_MSA_INTR_ENABLE_SHFT                                                    0x4
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RESERVE_35_XPU_MSA_INTR_ENABLE_BMSK                                              0x8
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RESERVE_35_XPU_MSA_INTR_ENABLE_SHFT                                              0x3
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_QNM_AGGRE2_XPU_MSA_INTR_ENABLE_BMSK                                              0x4
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_QNM_AGGRE2_XPU_MSA_INTR_ENABLE_SHFT                                              0x2
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_QNM_AGGRE1_XPU_MSA_INTR_ENABLE_BMSK                                              0x2
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_QNM_AGGRE1_XPU_MSA_INTR_ENABLE_SHFT                                              0x1
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_OCIMEM_XPU3_XPU_MSA_INTR_ENABLE_BMSK                                             0x1
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_OCIMEM_XPU3_XPU_MSA_INTR_ENABLE_SHFT                                             0x0

#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_ADDR                                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00021000)
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_OFFS                                                                         (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00021000)
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_RMSK                                                                         0xffffffff
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SP_INTR_BMSK                             0x80000000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SP_INTR_SHFT                                   0x1f
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_BOOT_ROM_XPU_SP_INTR_BMSK                                                    0x40000000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_BOOT_ROM_XPU_SP_INTR_SHFT                                                          0x1e
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SP_INTR_BMSK                                 0x20000000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SP_INTR_SHFT                                       0x1d
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_LLCC3_XPU_SP_INTR_BMSK                                                       0x10000000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_LLCC3_XPU_SP_INTR_SHFT                                                             0x1c
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_LLCC2_XPU_SP_INTR_BMSK                                                        0x8000000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_LLCC2_XPU_SP_INTR_SHFT                                                             0x1b
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_LLCC1_XPU_SP_INTR_BMSK                                                        0x4000000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_LLCC1_XPU_SP_INTR_SHFT                                                             0x1a
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_LLCC0_XPU_SP_INTR_BMSK                                                        0x2000000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_LLCC0_XPU_SP_INTR_SHFT                                                             0x19
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_UFS_XPU_SP_INTR_BMSK                                                          0x1000000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_UFS_XPU_SP_INTR_SHFT                                                               0x18
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_SP_INTR_BMSK                                          0x800000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_SP_INTR_SHFT                                              0x17
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SSC_SDC_XPU_SP_INTR_BMSK                                                       0x400000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SSC_SDC_XPU_SP_INTR_SHFT                                                           0x16
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_GCC_XPU_SP_INTR_BMSK                                                           0x200000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_GCC_XPU_SP_INTR_SHFT                                                               0x15
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_AOP_MPU_XPU_SP_INTR_BMSK                                                       0x100000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_AOP_MPU_XPU_SP_INTR_SHFT                                                           0x14
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QM_XPU_SP_INTR_BMSK                                                             0x80000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QM_XPU_SP_INTR_SHFT                                                                0x13
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QNM_SNOC_XPU_SP_INTR_BMSK                                                       0x40000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QNM_SNOC_XPU_SP_INTR_SHFT                                                          0x12
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QHS_CNOC_XPU_SP_INTR_BMSK                                                       0x20000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QHS_CNOC_XPU_SP_INTR_SHFT                                                          0x11
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QHM_AOSS_XPU_SP_INTR_BMSK                                                       0x10000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QHM_AOSS_XPU_SP_INTR_SHFT                                                          0x10
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SP_XPU_SP_INTR_BMSK                                                              0x8000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SP_XPU_SP_INTR_SHFT                                                                 0xf
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_PIMEM_MPU_XPU_SP_INTR_BMSK                                                       0x4000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_PIMEM_MPU_XPU_SP_INTR_SHFT                                                          0xe
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_PIMEM_APU_XPU_SP_INTR_BMSK                                                       0x2000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_PIMEM_APU_XPU_SP_INTR_SHFT                                                          0xd
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SSC_Q6_XPU_SP_INTR_BMSK                                                          0x1000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SSC_Q6_XPU_SP_INTR_SHFT                                                             0xc
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SSC_XPU_SP_INTR_BMSK                                                              0x800
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SSC_XPU_SP_INTR_SHFT                                                                0xb
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SSC_QUP_XPU_SP_INTR_BMSK                                                          0x400
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SSC_QUP_XPU_SP_INTR_SHFT                                                            0xa
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SEC_CTRL_XPU_SP_INTR_BMSK                                                         0x200
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SEC_CTRL_XPU_SP_INTR_SHFT                                                           0x9
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_DCC_XPU_SP_INTR_BMSK                                                              0x100
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_DCC_XPU_SP_INTR_SHFT                                                                0x8
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_OCIMEM_RPU_XPU_SP_INTR_BMSK                                                        0x80
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_OCIMEM_RPU_XPU_SP_INTR_SHFT                                                         0x7
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_CRYPTO0_XPU_SP_INTR_BMSK                                                           0x40
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_CRYPTO0_XPU_SP_INTR_SHFT                                                            0x6
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_TCSR_MUTEX_XPU_SP_INTR_BMSK                                                        0x20
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_TCSR_MUTEX_XPU_SP_INTR_SHFT                                                         0x5
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QUPV3_1_XPU_SP_INTR_BMSK                                                           0x10
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QUPV3_1_XPU_SP_INTR_SHFT                                                            0x4
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_TCSR_REGS_XPU_SP_INTR_BMSK                                                          0x8
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_TCSR_REGS_XPU_SP_INTR_SHFT                                                          0x3
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QUPV3_0_XPU_SP_INTR_BMSK                                                            0x4
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QUPV3_0_XPU_SP_INTR_SHFT                                                            0x2
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_AOSS_MPU_XPU_SP_INTR_BMSK                                                           0x2
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_AOSS_MPU_XPU_SP_INTR_SHFT                                                           0x1
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_PMIC_ARB_XPU_SP_INTR_BMSK                                                           0x1
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_PMIC_ARB_XPU_SP_INTR_SHFT                                                           0x0

#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_ADDR                                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00021004)
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_OFFS                                                                         (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00021004)
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RMSK                                                                           0xffffff
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RESERVE_55_XPU_SP_INTR_BMSK                                                    0x800000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RESERVE_55_XPU_SP_INTR_SHFT                                                        0x17
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_4_SP_INTR_BMSK                                                       0x400000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_4_SP_INTR_SHFT                                                           0x16
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_3_SP_INTR_BMSK                                                       0x200000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_3_SP_INTR_SHFT                                                           0x15
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_2_SP_INTR_BMSK                                                       0x100000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_2_SP_INTR_SHFT                                                           0x14
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_1_SP_INTR_BMSK                                                        0x80000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_1_SP_INTR_SHFT                                                           0x13
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_0_SP_INTR_BMSK                                                        0x40000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_0_SP_INTR_SHFT                                                           0x12
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_QSPI_XPU_SP_INTR_BMSK                                                           0x20000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_QSPI_XPU_SP_INTR_SHFT                                                              0x11
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_IPC_ROUTER_XPU_SP_INTR_BMSK                                                     0x10000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_IPC_ROUTER_XPU_SP_INTR_SHFT                                                        0x10
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_TLMM_NORTH_XPU_SP_INTR_BMSK                                                      0x8000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_TLMM_NORTH_XPU_SP_INTR_SHFT                                                         0xf
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RESERVE_46_XPU_SP_INTR_BMSK                                                      0x4000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RESERVE_46_XPU_SP_INTR_SHFT                                                         0xe
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_DDRSS_SHRM_XPU_SP_INTR_BMSK                                                      0x2000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_DDRSS_SHRM_XPU_SP_INTR_SHFT                                                         0xd
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_QUPV3_2_XPU_SP_INTR_BMSK                                                         0x1000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_QUPV3_2_XPU_SP_INTR_SHFT                                                            0xc
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_IPA_XPU_SP_INTR_BMSK                                                              0x800
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_IPA_XPU_SP_INTR_SHFT                                                                0xb
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RESERVE_42_XPU_SP_INTR_BMSK                                                       0x400
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RESERVE_42_XPU_SP_INTR_SHFT                                                         0xa
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_TLMM_SOUTH_XPU_SP_INTR_BMSK                                                       0x200
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_TLMM_SOUTH_XPU_SP_INTR_SHFT                                                         0x9
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_TLMM_WEST_XPU_SP_INTR_BMSK                                                        0x100
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_TLMM_WEST_XPU_SP_INTR_SHFT                                                          0x8
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_MDSS_XPU_SP_INTR_BMSK                                                              0x80
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_MDSS_XPU_SP_INTR_SHFT                                                               0x7
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_UFS_CARD_ICE_XPU_SP_INTR_BMSK                                                      0x40
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_UFS_CARD_ICE_XPU_SP_INTR_SHFT                                                       0x6
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_TITAN_XPU_SP_INTR_BMSK                                                             0x20
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_TITAN_XPU_SP_INTR_SHFT                                                              0x5
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_SPDM_XPU_SP_INTR_BMSK                                                              0x10
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_SPDM_XPU_SP_INTR_SHFT                                                               0x4
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RESERVE_35_XPU_SP_INTR_BMSK                                                         0x8
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RESERVE_35_XPU_SP_INTR_SHFT                                                         0x3
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_QNM_AGGRE2_XPU_SP_INTR_BMSK                                                         0x4
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_QNM_AGGRE2_XPU_SP_INTR_SHFT                                                         0x2
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_QNM_AGGRE1_XPU_SP_INTR_BMSK                                                         0x2
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_QNM_AGGRE1_XPU_SP_INTR_SHFT                                                         0x1
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_OCIMEM_XPU3_XPU_SP_INTR_BMSK                                                        0x1
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_OCIMEM_XPU3_XPU_SP_INTR_SHFT                                                        0x0

#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_ADDR                                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x00021008)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_OFFS                                                                       (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00021008)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_RMSK                                                                       0xffffffff
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SP_INTR_ENABLE_BMSK                    0x80000000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SP_INTR_ENABLE_SHFT                          0x1f
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_BOOT_ROM_XPU_SP_INTR_ENABLE_BMSK                                           0x40000000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_BOOT_ROM_XPU_SP_INTR_ENABLE_SHFT                                                 0x1e
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SP_INTR_ENABLE_BMSK                        0x20000000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SP_INTR_ENABLE_SHFT                              0x1d
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_LLCC3_XPU_SP_INTR_ENABLE_BMSK                                              0x10000000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_LLCC3_XPU_SP_INTR_ENABLE_SHFT                                                    0x1c
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_LLCC2_XPU_SP_INTR_ENABLE_BMSK                                               0x8000000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_LLCC2_XPU_SP_INTR_ENABLE_SHFT                                                    0x1b
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_LLCC1_XPU_SP_INTR_ENABLE_BMSK                                               0x4000000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_LLCC1_XPU_SP_INTR_ENABLE_SHFT                                                    0x1a
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_LLCC0_XPU_SP_INTR_ENABLE_BMSK                                               0x2000000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_LLCC0_XPU_SP_INTR_ENABLE_SHFT                                                    0x19
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_UFS_XPU_SP_INTR_ENABLE_BMSK                                                 0x1000000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_UFS_XPU_SP_INTR_ENABLE_SHFT                                                      0x18
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_SP_INTR_ENABLE_BMSK                                 0x800000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_SP_INTR_ENABLE_SHFT                                     0x17
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SSC_SDC_XPU_SP_INTR_ENABLE_BMSK                                              0x400000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SSC_SDC_XPU_SP_INTR_ENABLE_SHFT                                                  0x16
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_GCC_XPU_SP_INTR_ENABLE_BMSK                                                  0x200000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_GCC_XPU_SP_INTR_ENABLE_SHFT                                                      0x15
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_AOP_MPU_XPU_SP_INTR_ENABLE_BMSK                                              0x100000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_AOP_MPU_XPU_SP_INTR_ENABLE_SHFT                                                  0x14
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QM_XPU_SP_INTR_ENABLE_BMSK                                                    0x80000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QM_XPU_SP_INTR_ENABLE_SHFT                                                       0x13
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QNM_SNOC_XPU_SP_INTR_ENABLE_BMSK                                              0x40000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QNM_SNOC_XPU_SP_INTR_ENABLE_SHFT                                                 0x12
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QHS_CNOC_XPU_SP_INTR_ENABLE_BMSK                                              0x20000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QHS_CNOC_XPU_SP_INTR_ENABLE_SHFT                                                 0x11
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QHM_AOSS_XPU_SP_INTR_ENABLE_BMSK                                              0x10000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QHM_AOSS_XPU_SP_INTR_ENABLE_SHFT                                                 0x10
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SP_XPU_SP_INTR_ENABLE_BMSK                                                     0x8000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SP_XPU_SP_INTR_ENABLE_SHFT                                                        0xf
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_PIMEM_MPU_XPU_SP_INTR_ENABLE_BMSK                                              0x4000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_PIMEM_MPU_XPU_SP_INTR_ENABLE_SHFT                                                 0xe
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_PIMEM_APU_XPU_SP_INTR_ENABLE_BMSK                                              0x2000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_PIMEM_APU_XPU_SP_INTR_ENABLE_SHFT                                                 0xd
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SSC_Q6_XPU_SP_INTR_ENABLE_BMSK                                                 0x1000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SSC_Q6_XPU_SP_INTR_ENABLE_SHFT                                                    0xc
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SSC_XPU_SP_INTR_ENABLE_BMSK                                                     0x800
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SSC_XPU_SP_INTR_ENABLE_SHFT                                                       0xb
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SSC_QUP_XPU_SP_INTR_ENABLE_BMSK                                                 0x400
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SSC_QUP_XPU_SP_INTR_ENABLE_SHFT                                                   0xa
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SEC_CTRL_XPU_SP_INTR_ENABLE_BMSK                                                0x200
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SEC_CTRL_XPU_SP_INTR_ENABLE_SHFT                                                  0x9
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_DCC_XPU_SP_INTR_ENABLE_BMSK                                                     0x100
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_DCC_XPU_SP_INTR_ENABLE_SHFT                                                       0x8
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_OCIMEM_RPU_XPU_SP_INTR_ENABLE_BMSK                                               0x80
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_OCIMEM_RPU_XPU_SP_INTR_ENABLE_SHFT                                                0x7
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_CRYPTO0_XPU_SP_INTR_ENABLE_BMSK                                                  0x40
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_CRYPTO0_XPU_SP_INTR_ENABLE_SHFT                                                   0x6
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_TCSR_MUTEX_XPU_SP_INTR_ENABLE_BMSK                                               0x20
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_TCSR_MUTEX_XPU_SP_INTR_ENABLE_SHFT                                                0x5
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QUPV3_1_XPU_SP_INTR_ENABLE_BMSK                                                  0x10
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QUPV3_1_XPU_SP_INTR_ENABLE_SHFT                                                   0x4
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_TCSR_REGS_XPU_SP_INTR_ENABLE_BMSK                                                 0x8
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_TCSR_REGS_XPU_SP_INTR_ENABLE_SHFT                                                 0x3
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QUPV3_0_XPU_SP_INTR_ENABLE_BMSK                                                   0x4
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QUPV3_0_XPU_SP_INTR_ENABLE_SHFT                                                   0x2
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_AOSS_MPU_XPU_SP_INTR_ENABLE_BMSK                                                  0x2
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_AOSS_MPU_XPU_SP_INTR_ENABLE_SHFT                                                  0x1
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_PMIC_ARB_XPU_SP_INTR_ENABLE_BMSK                                                  0x1
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_PMIC_ARB_XPU_SP_INTR_ENABLE_SHFT                                                  0x0

#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_ADDR                                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x0002100c)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_OFFS                                                                       (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002100c)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RMSK                                                                         0xffffff
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RESERVE_55_XPU_SP_INTR_ENABLE_BMSK                                           0x800000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RESERVE_55_XPU_SP_INTR_ENABLE_SHFT                                               0x17
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_4_SP_INTR_ENABLE_BMSK                                              0x400000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_4_SP_INTR_ENABLE_SHFT                                                  0x16
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_3_SP_INTR_ENABLE_BMSK                                              0x200000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_3_SP_INTR_ENABLE_SHFT                                                  0x15
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_2_SP_INTR_ENABLE_BMSK                                              0x100000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_2_SP_INTR_ENABLE_SHFT                                                  0x14
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_1_SP_INTR_ENABLE_BMSK                                               0x80000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_1_SP_INTR_ENABLE_SHFT                                                  0x13
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_0_SP_INTR_ENABLE_BMSK                                               0x40000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_0_SP_INTR_ENABLE_SHFT                                                  0x12
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_QSPI_XPU_SP_INTR_ENABLE_BMSK                                                  0x20000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_QSPI_XPU_SP_INTR_ENABLE_SHFT                                                     0x11
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_IPC_ROUTER_XPU_SP_INTR_ENABLE_BMSK                                            0x10000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_IPC_ROUTER_XPU_SP_INTR_ENABLE_SHFT                                               0x10
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_TLMM_NORTH_XPU_SP_INTR_ENABLE_BMSK                                             0x8000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_TLMM_NORTH_XPU_SP_INTR_ENABLE_SHFT                                                0xf
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RESERVE_46_XPU_SP_INTR_ENABLE_BMSK                                             0x4000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RESERVE_46_XPU_SP_INTR_ENABLE_SHFT                                                0xe
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_DDRSS_SHRM_XPU_SP_INTR_ENABLE_BMSK                                             0x2000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_DDRSS_SHRM_XPU_SP_INTR_ENABLE_SHFT                                                0xd
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_QUPV3_2_XPU_SP_INTR_ENABLE_BMSK                                                0x1000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_QUPV3_2_XPU_SP_INTR_ENABLE_SHFT                                                   0xc
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_IPA_XPU_SP_INTR_ENABLE_BMSK                                                     0x800
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_IPA_XPU_SP_INTR_ENABLE_SHFT                                                       0xb
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RESERVE_42_XPU_SP_INTR_ENABLE_BMSK                                              0x400
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RESERVE_42_XPU_SP_INTR_ENABLE_SHFT                                                0xa
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_TLMM_SOUTH_XPU_SP_INTR_ENABLE_BMSK                                              0x200
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_TLMM_SOUTH_XPU_SP_INTR_ENABLE_SHFT                                                0x9
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_TLMM_WEST_XPU_SP_INTR_ENABLE_BMSK                                               0x100
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_TLMM_WEST_XPU_SP_INTR_ENABLE_SHFT                                                 0x8
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_MDSS_XPU_SP_INTR_ENABLE_BMSK                                                     0x80
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_MDSS_XPU_SP_INTR_ENABLE_SHFT                                                      0x7
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_UFS_CARD_ICE_XPU_SP_INTR_ENABLE_BMSK                                             0x40
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_UFS_CARD_ICE_XPU_SP_INTR_ENABLE_SHFT                                              0x6
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_TITAN_XPU_SP_INTR_ENABLE_BMSK                                                    0x20
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_TITAN_XPU_SP_INTR_ENABLE_SHFT                                                     0x5
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_SPDM_XPU_SP_INTR_ENABLE_BMSK                                                     0x10
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_SPDM_XPU_SP_INTR_ENABLE_SHFT                                                      0x4
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RESERVE_35_XPU_SP_INTR_ENABLE_BMSK                                                0x8
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RESERVE_35_XPU_SP_INTR_ENABLE_SHFT                                                0x3
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_QNM_AGGRE2_XPU_SP_INTR_ENABLE_BMSK                                                0x4
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_QNM_AGGRE2_XPU_SP_INTR_ENABLE_SHFT                                                0x2
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_QNM_AGGRE1_XPU_SP_INTR_ENABLE_BMSK                                                0x2
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_QNM_AGGRE1_XPU_SP_INTR_ENABLE_SHFT                                                0x1
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_OCIMEM_XPU3_XPU_SP_INTR_ENABLE_BMSK                                               0x1
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_OCIMEM_XPU3_XPU_SP_INTR_ENABLE_SHFT                                               0x0

#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00002010)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00002010)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_RMSK                                                              0x3ffff
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_RESERVE_17_VMIDMT_NSGIRPT_BMSK                                    0x20000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_RESERVE_17_VMIDMT_NSGIRPT_SHFT                                       0x11
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_RESERVE_16_VMIDMT_NSGIRPT_BMSK                                    0x10000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_RESERVE_16_VMIDMT_NSGIRPT_SHFT                                       0x10
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_RESERVE_15_VMIDMT_NSGIRPT_BMSK                                     0x8000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_RESERVE_15_VMIDMT_NSGIRPT_SHFT                                        0xf
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_LPASS_2_VMIDMT_NSGIRPT_BMSK                                        0x4000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_LPASS_2_VMIDMT_NSGIRPT_SHFT                                           0xe
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QSPI_VMIDMT_NSGIRPT_BMSK                                           0x2000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QSPI_VMIDMT_NSGIRPT_SHFT                                              0xd
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_SPDM_VMIDMT_NSGIRPT_BMSK                                           0x1000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_SPDM_VMIDMT_NSGIRPT_SHFT                                              0xc
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QDSS_DAP_VMIDMT_NSGIRPT_BMSK                                        0x800
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QDSS_DAP_VMIDMT_NSGIRPT_SHFT                                          0xb
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QDSS_TRACE_VMIDMT_NSGIRPT_BMSK                                      0x400
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QDSS_TRACE_VMIDMT_NSGIRPT_SHFT                                        0xa
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_IPA_VMIDMT_NSGIRPT_BMSK                                             0x200
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_IPA_VMIDMT_NSGIRPT_SHFT                                               0x9
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_LPASS_1_VMIDMT_NSGIRPT_BMSK                                         0x100
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_LPASS_1_VMIDMT_NSGIRPT_SHFT                                           0x8
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_LPASS_0_VMIDMT_NSGIRPT_BMSK                                          0x80
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_LPASS_0_VMIDMT_NSGIRPT_SHFT                                           0x7
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_SSC_VMIDMT_NSGIRPT_BMSK                                              0x40
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_SSC_VMIDMT_NSGIRPT_SHFT                                               0x6
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QUPV3_2_VMIDMT_NSGIRPT_BMSK                                          0x20
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QUPV3_2_VMIDMT_NSGIRPT_SHFT                                           0x5
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QUPV3_1_VMIDMT_NSGIRPT_BMSK                                          0x10
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QUPV3_1_VMIDMT_NSGIRPT_SHFT                                           0x4
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_SSC_SDC_VMIDMT_NSGIRPT_BMSK                                           0x8
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_SSC_SDC_VMIDMT_NSGIRPT_SHFT                                           0x3
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QUPV3_0_VMIDMT_NSGIRPT_BMSK                                           0x4
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QUPV3_0_VMIDMT_NSGIRPT_SHFT                                           0x2
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_AOP_VMIDMT_NSGIRPT_BMSK                                               0x2
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_AOP_VMIDMT_NSGIRPT_SHFT                                               0x1
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_CRYPTO0_VMIDMT_NSGIRPT_BMSK                                           0x1
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_CRYPTO0_VMIDMT_NSGIRPT_SHFT                                           0x0

#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00002050)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_OFFS                                                         (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00002050)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_RMSK                                                            0x3ffff
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_17_VMIDMT_NSGIRPT_ENABLE_BMSK                           0x20000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_17_VMIDMT_NSGIRPT_ENABLE_SHFT                              0x11
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_16_VMIDMT_NSGIRPT_ENABLE_BMSK                           0x10000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_16_VMIDMT_NSGIRPT_ENABLE_SHFT                              0x10
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_15_VMIDMT_NSGIRPT_ENABLE_BMSK                            0x8000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_15_VMIDMT_NSGIRPT_ENABLE_SHFT                               0xf
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_2_VMIDMT_NSGIRPT_ENABLE_BMSK                               0x4000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_2_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0xe
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QSPI_VMIDMT_NSGIRPT_ENABLE_BMSK                                  0x2000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QSPI_VMIDMT_NSGIRPT_ENABLE_SHFT                                     0xd
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_SPDM_VMIDMT_NSGIRPT_ENABLE_BMSK                                  0x1000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_SPDM_VMIDMT_NSGIRPT_ENABLE_SHFT                                     0xc
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QDSS_DAP_VMIDMT_NSGIRPT_ENABLE_BMSK                               0x800
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QDSS_DAP_VMIDMT_NSGIRPT_ENABLE_SHFT                                 0xb
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QDSS_TRACE_VMIDMT_NSGIRPT_ENABLE_BMSK                             0x400
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QDSS_TRACE_VMIDMT_NSGIRPT_ENABLE_SHFT                               0xa
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_IPA_VMIDMT_NSGIRPT_ENABLE_BMSK                                    0x200
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_IPA_VMIDMT_NSGIRPT_ENABLE_SHFT                                      0x9
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_1_VMIDMT_NSGIRPT_ENABLE_BMSK                                0x100
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_1_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0x8
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_0_VMIDMT_NSGIRPT_ENABLE_BMSK                                 0x80
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_0_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0x7
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_VMIDMT_NSGIRPT_ENABLE_BMSK                                     0x40
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_VMIDMT_NSGIRPT_ENABLE_SHFT                                      0x6
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_2_VMIDMT_NSGIRPT_ENABLE_BMSK                                 0x20
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_2_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0x5
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_VMIDMT_NSGIRPT_ENABLE_BMSK                                 0x10
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0x4
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_VMIDMT_NSGIRPT_ENABLE_BMSK                                  0x8
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0x3
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_VMIDMT_NSGIRPT_ENABLE_BMSK                                  0x4
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0x2
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_AOP_VMIDMT_NSGIRPT_ENABLE_BMSK                                      0x2
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_AOP_VMIDMT_NSGIRPT_ENABLE_SHFT                                      0x1
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_VMIDMT_NSGIRPT_ENABLE_BMSK                                  0x1
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0x0

#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00003000)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00003000)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_RMSK                                                                 0x3ffff
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_RESERVE_17_VMIDMT_NSGCFGIRPT_BMSK                                    0x20000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_RESERVE_17_VMIDMT_NSGCFGIRPT_SHFT                                       0x11
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_RESERVE_16_VMIDMT_NSGCFGIRPT_BMSK                                    0x10000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_RESERVE_16_VMIDMT_NSGCFGIRPT_SHFT                                       0x10
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_RESERVE_15_VMIDMT_NSGCFGIRPT_BMSK                                     0x8000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_RESERVE_15_VMIDMT_NSGCFGIRPT_SHFT                                        0xf
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_LPASS_2_VMIDMT_NSGCFGIRPT_BMSK                                        0x4000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_LPASS_2_VMIDMT_NSGCFGIRPT_SHFT                                           0xe
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QSPI_VMIDMT_NSGCFGIRPT_BMSK                                           0x2000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QSPI_VMIDMT_NSGCFGIRPT_SHFT                                              0xd
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_SPDM_VMIDMT_NSGCFGIRPT_BMSK                                           0x1000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_SPDM_VMIDMT_NSGCFGIRPT_SHFT                                              0xc
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QDSS_DAP_VMIDMT_NSGCFGIRPT_BMSK                                        0x800
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QDSS_DAP_VMIDMT_NSGCFGIRPT_SHFT                                          0xb
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QDSS_TRACE_VMIDMT_NSGCFGIRPT_BMSK                                      0x400
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QDSS_TRACE_VMIDMT_NSGCFGIRPT_SHFT                                        0xa
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_IPA_VMIDMT_NSGCFGIRPT_BMSK                                             0x200
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_IPA_VMIDMT_NSGCFGIRPT_SHFT                                               0x9
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_LPASS_1_VMIDMT_NSGCFGIRPT_BMSK                                         0x100
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_LPASS_1_VMIDMT_NSGCFGIRPT_SHFT                                           0x8
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_LPASS_0_VMIDMT_NSGCFGIRPT_BMSK                                          0x80
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_LPASS_0_VMIDMT_NSGCFGIRPT_SHFT                                           0x7
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_SSC_VMIDMT_NSGCFGIRPT_BMSK                                              0x40
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_SSC_VMIDMT_NSGCFGIRPT_SHFT                                               0x6
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QUPV3_2_VMIDMT_NSGCFGIRPT_BMSK                                          0x20
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QUPV3_2_VMIDMT_NSGCFGIRPT_SHFT                                           0x5
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QUPV3_1_VMIDMT_NSGCFGIRPT_BMSK                                          0x10
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QUPV3_1_VMIDMT_NSGCFGIRPT_SHFT                                           0x4
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_SSC_SDC_VMIDMT_NSGCFGIRPT_BMSK                                           0x8
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_SSC_SDC_VMIDMT_NSGCFGIRPT_SHFT                                           0x3
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QUPV3_0_VMIDMT_NSGCFGIRPT_BMSK                                           0x4
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QUPV3_0_VMIDMT_NSGCFGIRPT_SHFT                                           0x2
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_AOP_VMIDMT_NSGCFGIRPT_BMSK                                               0x2
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_AOP_VMIDMT_NSGCFGIRPT_SHFT                                               0x1
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_CRYPTO0_VMIDMT_NSGCFGIRPT_BMSK                                           0x1
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_CRYPTO0_VMIDMT_NSGCFGIRPT_SHFT                                           0x0

#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00003040)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_OFFS                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00003040)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_RMSK                                                               0x3ffff
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_17_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                           0x20000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_17_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                              0x11
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_16_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                           0x10000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_16_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                              0x10
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_15_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                            0x8000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_15_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                               0xf
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_2_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                               0x4000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_2_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0xe
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QSPI_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                  0x2000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QSPI_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                     0xd
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_SPDM_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                  0x1000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_SPDM_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                     0xc
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QDSS_DAP_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                               0x800
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QDSS_DAP_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                 0xb
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QDSS_TRACE_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                             0x400
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QDSS_TRACE_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                               0xa
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_IPA_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                    0x200
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_IPA_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                      0x9
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_1_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                0x100
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_1_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0x8
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_0_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                 0x80
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_0_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0x7
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                     0x40
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                      0x6
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_2_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                 0x20
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_2_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0x5
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                 0x10
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0x4
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                  0x8
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0x3
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                  0x4
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0x2
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_AOP_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                      0x2
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_AOP_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                      0x1
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                  0x1
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0x0

#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00004010)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_OFFS                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00004010)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_RMSK                                                                  0x3ffff
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_RESERVE_17_VMIDMT_GIRPT_BMSK                                          0x20000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_RESERVE_17_VMIDMT_GIRPT_SHFT                                             0x11
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_RESERVE_16_VMIDMT_GIRPT_BMSK                                          0x10000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_RESERVE_16_VMIDMT_GIRPT_SHFT                                             0x10
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_RESERVE_15_VMIDMT_GIRPT_BMSK                                           0x8000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_RESERVE_15_VMIDMT_GIRPT_SHFT                                              0xf
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_LPASS_2_VMIDMT_GIRPT_BMSK                                              0x4000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_LPASS_2_VMIDMT_GIRPT_SHFT                                                 0xe
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QSPI_VMIDMT_GIRPT_BMSK                                                 0x2000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QSPI_VMIDMT_GIRPT_SHFT                                                    0xd
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_SPDM_VMIDMT_GIRPT_BMSK                                                 0x1000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_SPDM_VMIDMT_GIRPT_SHFT                                                    0xc
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QDSS_DAP_VMIDMT_GIRPT_BMSK                                              0x800
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QDSS_DAP_VMIDMT_GIRPT_SHFT                                                0xb
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QDSS_TRACE_VMIDMT_GIRPT_BMSK                                            0x400
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QDSS_TRACE_VMIDMT_GIRPT_SHFT                                              0xa
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_IPA_VMIDMT_GIRPT_BMSK                                                   0x200
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_IPA_VMIDMT_GIRPT_SHFT                                                     0x9
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_LPASS_1_VMIDMT_GIRPT_BMSK                                               0x100
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_LPASS_1_VMIDMT_GIRPT_SHFT                                                 0x8
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_LPASS_0_VMIDMT_GIRPT_BMSK                                                0x80
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_LPASS_0_VMIDMT_GIRPT_SHFT                                                 0x7
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_SSC_VMIDMT_GIRPT_BMSK                                                    0x40
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_SSC_VMIDMT_GIRPT_SHFT                                                     0x6
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QUPV3_2_VMIDMT_GIRPT_BMSK                                                0x20
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QUPV3_2_VMIDMT_GIRPT_SHFT                                                 0x5
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QUPV3_1_VMIDMT_GIRPT_BMSK                                                0x10
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QUPV3_1_VMIDMT_GIRPT_SHFT                                                 0x4
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_SSC_SDC_VMIDMT_GIRPT_BMSK                                                 0x8
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_SSC_SDC_VMIDMT_GIRPT_SHFT                                                 0x3
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QUPV3_0_VMIDMT_GIRPT_BMSK                                                 0x4
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QUPV3_0_VMIDMT_GIRPT_SHFT                                                 0x2
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_AOP_VMIDMT_GIRPT_BMSK                                                     0x2
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_AOP_VMIDMT_GIRPT_SHFT                                                     0x1
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_CRYPTO0_VMIDMT_GIRPT_BMSK                                                 0x1
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_CRYPTO0_VMIDMT_GIRPT_SHFT                                                 0x0

#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_ADDR                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x00004050)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_OFFS                                                             (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00004050)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_RMSK                                                                0x3ffff
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_RESERVE_17_VMIDMT_GIRPT_ENABLE_BMSK                                 0x20000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_RESERVE_17_VMIDMT_GIRPT_ENABLE_SHFT                                    0x11
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_RESERVE_16_VMIDMT_GIRPT_ENABLE_BMSK                                 0x10000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_RESERVE_16_VMIDMT_GIRPT_ENABLE_SHFT                                    0x10
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_RESERVE_15_VMIDMT_GIRPT_ENABLE_BMSK                                  0x8000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_RESERVE_15_VMIDMT_GIRPT_ENABLE_SHFT                                     0xf
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_LPASS_2_VMIDMT_GIRPT_ENABLE_BMSK                                     0x4000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_LPASS_2_VMIDMT_GIRPT_ENABLE_SHFT                                        0xe
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QSPI_VMIDMT_GIRPT_ENABLE_BMSK                                        0x2000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QSPI_VMIDMT_GIRPT_ENABLE_SHFT                                           0xd
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_SPDM_VMIDMT_GIRPT_ENABLE_BMSK                                        0x1000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_SPDM_VMIDMT_GIRPT_ENABLE_SHFT                                           0xc
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QDSS_DAP_VMIDMT_GIRPT_ENABLE_BMSK                                     0x800
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QDSS_DAP_VMIDMT_GIRPT_ENABLE_SHFT                                       0xb
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QDSS_TRACE_VMIDMT_GIRPT_ENABLE_BMSK                                   0x400
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QDSS_TRACE_VMIDMT_GIRPT_ENABLE_SHFT                                     0xa
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_IPA_VMIDMT_GIRPT_ENABLE_BMSK                                          0x200
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_IPA_VMIDMT_GIRPT_ENABLE_SHFT                                            0x9
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_LPASS_1_VMIDMT_GIRPT_ENABLE_BMSK                                      0x100
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_LPASS_1_VMIDMT_GIRPT_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_LPASS_0_VMIDMT_GIRPT_ENABLE_BMSK                                       0x80
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_LPASS_0_VMIDMT_GIRPT_ENABLE_SHFT                                        0x7
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_SSC_VMIDMT_GIRPT_ENABLE_BMSK                                           0x40
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_SSC_VMIDMT_GIRPT_ENABLE_SHFT                                            0x6
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QUPV3_2_VMIDMT_GIRPT_ENABLE_BMSK                                       0x20
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QUPV3_2_VMIDMT_GIRPT_ENABLE_SHFT                                        0x5
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_VMIDMT_GIRPT_ENABLE_BMSK                                       0x10
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_VMIDMT_GIRPT_ENABLE_SHFT                                        0x4
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_VMIDMT_GIRPT_ENABLE_BMSK                                        0x8
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_VMIDMT_GIRPT_ENABLE_SHFT                                        0x3
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_VMIDMT_GIRPT_ENABLE_BMSK                                        0x4
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_VMIDMT_GIRPT_ENABLE_SHFT                                        0x2
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_AOP_VMIDMT_GIRPT_ENABLE_BMSK                                            0x2
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_AOP_VMIDMT_GIRPT_ENABLE_SHFT                                            0x1
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_VMIDMT_GIRPT_ENABLE_BMSK                                        0x1
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_VMIDMT_GIRPT_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00005000)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_OFFS                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00005000)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_RMSK                                                                     0x3ffff
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_RESERVE_17_VMIDMT_GCFGIRPT_BMSK                                          0x20000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_RESERVE_17_VMIDMT_GCFGIRPT_SHFT                                             0x11
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_RESERVE_16_VMIDMT_GCFGIRPT_BMSK                                          0x10000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_RESERVE_16_VMIDMT_GCFGIRPT_SHFT                                             0x10
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_RESERVE_15_VMIDMT_GCFGIRPT_BMSK                                           0x8000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_RESERVE_15_VMIDMT_GCFGIRPT_SHFT                                              0xf
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_LPASS_2_VMIDMT_GCFGIRPT_BMSK                                              0x4000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_LPASS_2_VMIDMT_GCFGIRPT_SHFT                                                 0xe
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QSPI_VMIDMT_GCFGIRPT_BMSK                                                 0x2000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QSPI_VMIDMT_GCFGIRPT_SHFT                                                    0xd
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_SPDM_VMIDMT_GCFGIRPT_BMSK                                                 0x1000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_SPDM_VMIDMT_GCFGIRPT_SHFT                                                    0xc
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QDSS_DAP_VMIDMT_GCFGIRPT_BMSK                                              0x800
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QDSS_DAP_VMIDMT_GCFGIRPT_SHFT                                                0xb
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QDSS_TRACE_VMIDMT_GCFGIRPT_BMSK                                            0x400
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QDSS_TRACE_VMIDMT_GCFGIRPT_SHFT                                              0xa
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_IPA_VMIDMT_GCFGIRPT_BMSK                                                   0x200
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_IPA_VMIDMT_GCFGIRPT_SHFT                                                     0x9
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_LPASS_1_VMIDMT_GCFGIRPT_BMSK                                               0x100
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_LPASS_1_VMIDMT_GCFGIRPT_SHFT                                                 0x8
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_LPASS_0_VMIDMT_GCFGIRPT_BMSK                                                0x80
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_LPASS_0_VMIDMT_GCFGIRPT_SHFT                                                 0x7
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_SSC_VMIDMT_GCFGIRPT_BMSK                                                    0x40
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_SSC_VMIDMT_GCFGIRPT_SHFT                                                     0x6
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QUPV3_2_VMIDMT_GCFGIRPT_BMSK                                                0x20
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QUPV3_2_VMIDMT_GCFGIRPT_SHFT                                                 0x5
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QUPV3_1_VMIDMT_GCFGIRPT_BMSK                                                0x10
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QUPV3_1_VMIDMT_GCFGIRPT_SHFT                                                 0x4
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_SSC_SDC_VMIDMT_GCFGIRPT_BMSK                                                 0x8
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_SSC_SDC_VMIDMT_GCFGIRPT_SHFT                                                 0x3
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QUPV3_0_VMIDMT_GCFGIRPT_BMSK                                                 0x4
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QUPV3_0_VMIDMT_GCFGIRPT_SHFT                                                 0x2
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_AOP_VMIDMT_GCFGIRPT_BMSK                                                     0x2
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_AOP_VMIDMT_GCFGIRPT_SHFT                                                     0x1
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_CRYPTO0_VMIDMT_GCFGIRPT_BMSK                                                 0x1
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_CRYPTO0_VMIDMT_GCFGIRPT_SHFT                                                 0x0

#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x00005040)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_OFFS                                                                (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00005040)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_RMSK                                                                   0x3ffff
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_RESERVE_17_VMIDMT_GCFGIRPT_ENABLE_BMSK                                 0x20000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_RESERVE_17_VMIDMT_GCFGIRPT_ENABLE_SHFT                                    0x11
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_RESERVE_16_VMIDMT_GCFGIRPT_ENABLE_BMSK                                 0x10000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_RESERVE_16_VMIDMT_GCFGIRPT_ENABLE_SHFT                                    0x10
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_RESERVE_15_VMIDMT_GCFGIRPT_ENABLE_BMSK                                  0x8000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_RESERVE_15_VMIDMT_GCFGIRPT_ENABLE_SHFT                                     0xf
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_LPASS_2_VMIDMT_GCFGIRPT_ENABLE_BMSK                                     0x4000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_LPASS_2_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0xe
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QSPI_VMIDMT_GCFGIRPT_ENABLE_BMSK                                        0x2000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QSPI_VMIDMT_GCFGIRPT_ENABLE_SHFT                                           0xd
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_SPDM_VMIDMT_GCFGIRPT_ENABLE_BMSK                                        0x1000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_SPDM_VMIDMT_GCFGIRPT_ENABLE_SHFT                                           0xc
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QDSS_DAP_VMIDMT_GCFGIRPT_ENABLE_BMSK                                     0x800
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QDSS_DAP_VMIDMT_GCFGIRPT_ENABLE_SHFT                                       0xb
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QDSS_TRACE_VMIDMT_GCFGIRPT_ENABLE_BMSK                                   0x400
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QDSS_TRACE_VMIDMT_GCFGIRPT_ENABLE_SHFT                                     0xa
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_IPA_VMIDMT_GCFGIRPT_ENABLE_BMSK                                          0x200
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_IPA_VMIDMT_GCFGIRPT_ENABLE_SHFT                                            0x9
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_LPASS_1_VMIDMT_GCFGIRPT_ENABLE_BMSK                                      0x100
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_LPASS_1_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_LPASS_0_VMIDMT_GCFGIRPT_ENABLE_BMSK                                       0x80
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_LPASS_0_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0x7
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_SSC_VMIDMT_GCFGIRPT_ENABLE_BMSK                                           0x40
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_SSC_VMIDMT_GCFGIRPT_ENABLE_SHFT                                            0x6
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QUPV3_2_VMIDMT_GCFGIRPT_ENABLE_BMSK                                       0x20
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QUPV3_2_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0x5
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_VMIDMT_GCFGIRPT_ENABLE_BMSK                                       0x10
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0x4
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_VMIDMT_GCFGIRPT_ENABLE_BMSK                                        0x8
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0x3
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_VMIDMT_GCFGIRPT_ENABLE_BMSK                                        0x4
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0x2
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_AOP_VMIDMT_GCFGIRPT_ENABLE_BMSK                                            0x2
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_AOP_VMIDMT_GCFGIRPT_ENABLE_SHFT                                            0x1
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_VMIDMT_GCFGIRPT_ENABLE_BMSK                                        0x1
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_ADDR                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x00008020)
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_OFFS                                                                    (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00008020)
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RMSK                                                                    0xffffffff
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_BMSK                                      0x80000000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_SHFT                                            0x1f
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_BMSK                                      0x40000000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_SHFT                                            0x1e
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_BMSK                                      0x20000000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_SHFT                                            0x1d
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_BMSK                                      0x10000000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_SHFT                                            0x1c
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_BMSK                                       0x8000000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_SHFT                                            0x1b
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_BMSK                                       0x4000000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_SHFT                                            0x1a
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_BMSK                                       0x2000000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_SHFT                                            0x19
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_BMSK                                       0x1000000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_SHFT                                            0x18
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_BMSK                                           0x800000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_SHFT                                               0x17
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_BMSK                                           0x400000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_SHFT                                               0x16
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_BMSK                                           0x200000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_SHFT                                               0x15
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_BMSK                                        0x100000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_SHFT                                            0x14
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_BMSK                                           0x80000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_SHFT                                              0x13
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_BMSK                                           0x40000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_SHFT                                              0x12
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_BMSK                                         0x20000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_SHFT                                            0x11
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_BMSK                                         0x10000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_SHFT                                            0x10
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_BMSK                                          0x8000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_SHFT                                             0xf
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_BMSK                                          0x4000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_SHFT                                             0xe
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_BMSK                                          0x2000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_SHFT                                             0xd
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_BMSK                                          0x1000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_SHFT                                             0xc
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_BMSK                                           0x800
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_SHFT                                             0xb
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_BMSK                                           0x400
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_SHFT                                             0xa
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_BMSK                                            0x200
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_SHFT                                              0x9
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_BMSK                                            0x100
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_SHFT                                              0x8
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_BMSK                                             0x80
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_SHFT                                              0x7
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_BMSK                                             0x40
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_SHFT                                              0x6
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_BMSK                                             0x20
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_SHFT                                              0x5
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_BMSK                                             0x10
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_SHFT                                              0x4
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_BMSK                                              0x8
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_SHFT                                              0x3
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_BMSK                                                0x4
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_SHFT                                                0x2
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_BMSK                                                0x2
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_SHFT                                                0x1
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_BMSK                                                  0x1
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_SHFT                                                  0x0

#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00027000)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00027000)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RMSK                                                              0xffffffff
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x80000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x1f
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x40000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x1e
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x20000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x1d
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x10000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x1c
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x8000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x1b
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x4000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x1a
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x2000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x19
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x1000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x18
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_BMSK                              0x800000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_SHFT                                  0x17
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                              0x400000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                                  0x16
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                              0x200000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                  0x15
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x100000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x14
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                              0x80000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                                 0x13
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                              0x40000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                 0x12
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x20000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x11
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x10000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x10
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x8000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0xf
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x4000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0xe
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x2000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0xd
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x1000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0xc
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x800
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0xb
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x400
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0xa
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x200
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                 0x9
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x100
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                 0x8
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x80
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                 0x7
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x40
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                 0x6
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x20
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                 0x5
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x10
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                 0x4
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                 0x8
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                 0x3
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_ENABLE_BMSK                                   0x4
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_ENABLE_SHFT                                   0x2
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_ENABLE_BMSK                                   0x2
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_ENABLE_SHFT                                   0x1
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                     0x1
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                     0x0

#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_ADDR                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x00028000)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_OFFS                                                             (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00028000)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RMSK                                                             0xffffffff
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x80000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x1f
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x40000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x1e
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x20000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x1d
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x10000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x1c
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x8000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x1b
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x4000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x1a
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x2000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x19
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x1000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x18
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_BMSK                             0x800000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_SHFT                                 0x17
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                             0x400000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                                 0x16
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                             0x200000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                 0x15
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x100000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x14
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                             0x80000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                                0x13
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                             0x40000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                0x12
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x20000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x11
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x10000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x10
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x8000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0xf
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x4000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0xe
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x2000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0xd
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x1000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0xc
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x800
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0xb
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x400
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0xa
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x200
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0x9
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x100
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0x8
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x80
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0x7
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x40
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0x6
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x20
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0x5
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x10
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0x4
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x8
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0x3
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_ENABLE_BMSK                                  0x4
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_ENABLE_SHFT                                  0x2
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_ENABLE_BMSK                                  0x2
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_ENABLE_SHFT                                  0x1
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                    0x1
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                    0x0

#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00029000)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_OFFS                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00029000)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RMSK                                                            0xffffffff
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                       0x80000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x1f
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                       0x40000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x1e
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                       0x20000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x1d
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                       0x10000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x1c
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x8000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x1b
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x4000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x1a
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x2000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x19
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x1000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x18
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_BMSK                            0x800000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_SHFT                                0x17
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                            0x400000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                                0x16
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                            0x200000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                0x15
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x100000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x14
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                            0x80000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                               0x13
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                            0x40000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                               0x12
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x20000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x11
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x10000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x10
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x8000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0xf
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x4000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0xe
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x2000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0xd
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x1000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0xc
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x800
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0xb
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x400
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0xa
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x200
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x9
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x100
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x8
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x80
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x7
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x40
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x6
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x20
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x5
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x10
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x4
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x8
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x3
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_ENABLE_BMSK                                 0x4
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_ENABLE_SHFT                                 0x2
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_ENABLE_BMSK                                 0x2
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_ENABLE_SHFT                                 0x1
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                   0x1
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                   0x0

#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0002b000)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002b000)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RMSK                                                           0xffffffff
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                      0x80000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x1f
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                      0x40000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x1e
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                      0x20000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x1d
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                      0x10000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x1c
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                       0x8000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x1b
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                       0x4000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x1a
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                       0x2000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x19
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                       0x1000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x18
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_BMSK                           0x800000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_SHFT                               0x17
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                           0x400000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                               0x16
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                           0x200000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                               0x15
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x100000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x14
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                           0x80000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                              0x13
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                           0x40000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                              0x12
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x20000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x11
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x10000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x10
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x8000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0xf
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x4000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0xe
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x2000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0xd
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x1000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0xc
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x800
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0xb
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x400
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0xa
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x200
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x9
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x100
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x8
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x80
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x7
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x40
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x6
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x20
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x5
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x10
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x4
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x8
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x3
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_ENABLE_BMSK                                0x4
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_ENABLE_SHFT                                0x2
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_ENABLE_BMSK                                0x2
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_ENABLE_SHFT                                0x1
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                  0x1
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                  0x0

#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002d060)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_OFFS                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002d060)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_RMSK                                                                    0xff
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_I_TOP_IBI_I3C_INTR_BMSK                                                 0xff
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_I_TOP_IBI_I3C_INTR_SHFT                                                  0x0

#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0002d064)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_OFFS                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002d064)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_RMSK                                                                  0xff
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_I_TOP_IBI_I3C_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_I_TOP_IBI_I3C_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_SOC_HW_VERSION_ADDR                                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x00008000)
#define HWIO_TCSR_SOC_HW_VERSION_OFFS                                                                                   (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00008000)
#define HWIO_TCSR_SOC_HW_VERSION_RMSK                                                                                   0xffffffff
#define HWIO_TCSR_SOC_HW_VERSION_IN          \
        in_dword(HWIO_TCSR_SOC_HW_VERSION_ADDR)
#define HWIO_TCSR_SOC_HW_VERSION_INM(m)      \
        in_dword_masked(HWIO_TCSR_SOC_HW_VERSION_ADDR, m)
#define HWIO_TCSR_SOC_HW_VERSION_FAMILY_NUMBER_BMSK                                                                     0xf0000000
#define HWIO_TCSR_SOC_HW_VERSION_FAMILY_NUMBER_SHFT                                                                           0x1c
#define HWIO_TCSR_SOC_HW_VERSION_DEVICE_NUMBER_BMSK                                                                      0xfff0000
#define HWIO_TCSR_SOC_HW_VERSION_DEVICE_NUMBER_SHFT                                                                           0x10
#define HWIO_TCSR_SOC_HW_VERSION_MAJOR_VERSION_BMSK                                                                         0xff00
#define HWIO_TCSR_SOC_HW_VERSION_MAJOR_VERSION_SHFT                                                                            0x8
#define HWIO_TCSR_SOC_HW_VERSION_MINOR_VERSION_BMSK                                                                           0xff
#define HWIO_TCSR_SOC_HW_VERSION_MINOR_VERSION_SHFT                                                                            0x0

#define HWIO_TCSR_SOC_EMULATION_TYPE_ADDR                                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00008004)
#define HWIO_TCSR_SOC_EMULATION_TYPE_OFFS                                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00008004)
#define HWIO_TCSR_SOC_EMULATION_TYPE_RMSK                                                                                      0x3
#define HWIO_TCSR_SOC_EMULATION_TYPE_IN          \
        in_dword(HWIO_TCSR_SOC_EMULATION_TYPE_ADDR)
#define HWIO_TCSR_SOC_EMULATION_TYPE_INM(m)      \
        in_dword_masked(HWIO_TCSR_SOC_EMULATION_TYPE_ADDR, m)
#define HWIO_TCSR_SOC_EMULATION_TYPE_SOC_EMULATION_TYPE_BMSK                                                                   0x3
#define HWIO_TCSR_SOC_EMULATION_TYPE_SOC_EMULATION_TYPE_SHFT                                                                   0x0
#define HWIO_TCSR_SOC_EMULATION_TYPE_SOC_EMULATION_TYPE_SILICON_FVAL                                                           0x0
#define HWIO_TCSR_SOC_EMULATION_TYPE_SOC_EMULATION_TYPE_RUMI_FVAL                                                              0x1
#define HWIO_TCSR_SOC_EMULATION_TYPE_SOC_EMULATION_TYPE_VELOCE_FVAL                                                            0x2
#define HWIO_TCSR_SOC_EMULATION_TYPE_SOC_EMULATION_TYPE_VIRTIO_FVAL                                                            0x3

#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x00008008)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_OFFS                                                                          (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00008008)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_RMSK                                                                          0xffffffff
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_IN          \
        in_dword(HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_ADDR)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_INM(m)      \
        in_dword_masked(HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_ADDR, m)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_OUT(v)      \
        out_dword(HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_ADDR,v)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_ADDR,m,v,HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_IN)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_FAMILY_NUMBER_BMSK                                                   0xf0000000
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_FAMILY_NUMBER_SHFT                                                         0x1c
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_DEVICE_NUMBER_BMSK                                                    0xfff0000
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_DEVICE_NUMBER_SHFT                                                         0x10
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_MAJOR_VERSION_BMSK                                                       0xff00
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_MAJOR_VERSION_SHFT                                                          0x8
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_MINOR_VERSION_BMSK                                                         0xff
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_MINOR_VERSION_SHFT                                                          0x0

#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00008070)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_OFFS                                                                        (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00008070)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_RMSK                                                                        0xffffffff
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_IN          \
        in_dword(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_ADDR)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_ADDR, m)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_SRAM_REDUNDANCY_CRC_ERR_BMSK                                                0xffffffff
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_SRAM_REDUNDANCY_CRC_ERR_SHFT                                                       0x0

#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00008074)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_OFFS                                                                        (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00008074)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_RMSK                                                                        0xffffffff
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_IN          \
        in_dword(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_ADDR)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_ADDR, m)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_SRAM_REDUNDANCY_CRC_ERR_BMSK                                                0xffffffff
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_SRAM_REDUNDANCY_CRC_ERR_SHFT                                                       0x0

#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00008078)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_OFFS                                                                        (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00008078)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_RMSK                                                                        0xffffffff
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_IN          \
        in_dword(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_ADDR)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_ADDR, m)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_SRAM_REDUNDANCY_CRC_ERR_BMSK                                                0xffffffff
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_SRAM_REDUNDANCY_CRC_ERR_SHFT                                                       0x0

#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x0000807c)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_OFFS                                                                        (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000807c)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_RMSK                                                                        0xffffffff
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_IN          \
        in_dword(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_ADDR)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_INM(m)      \
        in_dword_masked(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_ADDR, m)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_SRAM_REDUNDANCY_CRC_ERR_BMSK                                                0xffffffff
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_SRAM_REDUNDANCY_CRC_ERR_SHFT                                                       0x0

#define HWIO_TCSR_TCSR_CLK_EN_ADDR                                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0000907c)
#define HWIO_TCSR_TCSR_CLK_EN_OFFS                                                                                      (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000907c)
#define HWIO_TCSR_TCSR_CLK_EN_RMSK                                                                                             0x1
#define HWIO_TCSR_TCSR_CLK_EN_IN          \
        in_dword(HWIO_TCSR_TCSR_CLK_EN_ADDR)
#define HWIO_TCSR_TCSR_CLK_EN_INM(m)      \
        in_dword_masked(HWIO_TCSR_TCSR_CLK_EN_ADDR, m)
#define HWIO_TCSR_TCSR_CLK_EN_OUT(v)      \
        out_dword(HWIO_TCSR_TCSR_CLK_EN_ADDR,v)
#define HWIO_TCSR_TCSR_CLK_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TCSR_CLK_EN_ADDR,m,v,HWIO_TCSR_TCSR_CLK_EN_IN)
#define HWIO_TCSR_TCSR_CLK_EN_TCSR_CLK_EN_BMSK                                                                                 0x1
#define HWIO_TCSR_TCSR_CLK_EN_TCSR_CLK_EN_SHFT                                                                                 0x0

#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_ADDR                                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x0000a100)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_OFFS                                                                             (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000a100)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_RMSK                                                                                    0x1
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_IN          \
        in_dword(HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_ADDR)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_INM(m)      \
        in_dword_masked(HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_ADDR, m)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_OUT(v)      \
        out_dword(HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_ADDR,v)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_ADDR,m,v,HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_IN)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_TCSR_IPA_WARMBOOT_EN_BMSK                                                               0x1
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_TCSR_IPA_WARMBOOT_EN_SHFT                                                               0x0

#define HWIO_TCSR_SYS_POWER_CTRL_ADDR                                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0000a000)
#define HWIO_TCSR_SYS_POWER_CTRL_OFFS                                                                                   (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000a000)
#define HWIO_TCSR_SYS_POWER_CTRL_RMSK                                                                                       0xffff
#define HWIO_TCSR_SYS_POWER_CTRL_IN          \
        in_dword(HWIO_TCSR_SYS_POWER_CTRL_ADDR)
#define HWIO_TCSR_SYS_POWER_CTRL_INM(m)      \
        in_dword_masked(HWIO_TCSR_SYS_POWER_CTRL_ADDR, m)
#define HWIO_TCSR_SYS_POWER_CTRL_OUT(v)      \
        out_dword(HWIO_TCSR_SYS_POWER_CTRL_ADDR,v)
#define HWIO_TCSR_SYS_POWER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SYS_POWER_CTRL_ADDR,m,v,HWIO_TCSR_SYS_POWER_CTRL_IN)
#define HWIO_TCSR_SYS_POWER_CTRL_SYS_POWER_CTRL_BMSK                                                                        0xffff
#define HWIO_TCSR_SYS_POWER_CTRL_SYS_POWER_CTRL_SHFT                                                                           0x0

#define HWIO_TCSR_USB_CORE_ID_ADDR                                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0000a004)
#define HWIO_TCSR_USB_CORE_ID_OFFS                                                                                      (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000a004)
#define HWIO_TCSR_USB_CORE_ID_RMSK                                                                                             0x3
#define HWIO_TCSR_USB_CORE_ID_IN          \
        in_dword(HWIO_TCSR_USB_CORE_ID_ADDR)
#define HWIO_TCSR_USB_CORE_ID_INM(m)      \
        in_dword_masked(HWIO_TCSR_USB_CORE_ID_ADDR, m)
#define HWIO_TCSR_USB_CORE_ID_OUT(v)      \
        out_dword(HWIO_TCSR_USB_CORE_ID_ADDR,v)
#define HWIO_TCSR_USB_CORE_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_USB_CORE_ID_ADDR,m,v,HWIO_TCSR_USB_CORE_ID_IN)
#define HWIO_TCSR_USB_CORE_ID_USB_CORE_ID_BMSK                                                                                 0x3
#define HWIO_TCSR_USB_CORE_ID_USB_CORE_ID_SHFT                                                                                 0x0

#define HWIO_TCSR_SPARE0_REG0_ADDR                                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0000a044)
#define HWIO_TCSR_SPARE0_REG0_OFFS                                                                                      (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000a044)
#define HWIO_TCSR_SPARE0_REG0_RMSK                                                                                      0xffffffff
#define HWIO_TCSR_SPARE0_REG0_IN          \
        in_dword(HWIO_TCSR_SPARE0_REG0_ADDR)
#define HWIO_TCSR_SPARE0_REG0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPARE0_REG0_ADDR, m)
#define HWIO_TCSR_SPARE0_REG0_OUT(v)      \
        out_dword(HWIO_TCSR_SPARE0_REG0_ADDR,v)
#define HWIO_TCSR_SPARE0_REG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPARE0_REG0_ADDR,m,v,HWIO_TCSR_SPARE0_REG0_IN)
#define HWIO_TCSR_SPARE0_REG0_SPARE0_REG0_BMSK                                                                          0xffffffff
#define HWIO_TCSR_SPARE0_REG0_SPARE0_REG0_SHFT                                                                                 0x0

#define HWIO_TCSR_SPARE0_REG1_ADDR                                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0000a048)
#define HWIO_TCSR_SPARE0_REG1_OFFS                                                                                      (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000a048)
#define HWIO_TCSR_SPARE0_REG1_RMSK                                                                                      0xffffffff
#define HWIO_TCSR_SPARE0_REG1_IN          \
        in_dword(HWIO_TCSR_SPARE0_REG1_ADDR)
#define HWIO_TCSR_SPARE0_REG1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPARE0_REG1_ADDR, m)
#define HWIO_TCSR_SPARE0_REG1_OUT(v)      \
        out_dword(HWIO_TCSR_SPARE0_REG1_ADDR,v)
#define HWIO_TCSR_SPARE0_REG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPARE0_REG1_ADDR,m,v,HWIO_TCSR_SPARE0_REG1_IN)
#define HWIO_TCSR_SPARE0_REG1_SPARE0_REG1_BMSK                                                                          0xffffffff
#define HWIO_TCSR_SPARE0_REG1_SPARE0_REG1_SHFT                                                                                 0x0

#define HWIO_TCSR_SPARE1_REG0_ADDR                                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0000a04c)
#define HWIO_TCSR_SPARE1_REG0_OFFS                                                                                      (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000a04c)
#define HWIO_TCSR_SPARE1_REG0_RMSK                                                                                      0xffffffff
#define HWIO_TCSR_SPARE1_REG0_IN          \
        in_dword(HWIO_TCSR_SPARE1_REG0_ADDR)
#define HWIO_TCSR_SPARE1_REG0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPARE1_REG0_ADDR, m)
#define HWIO_TCSR_SPARE1_REG0_OUT(v)      \
        out_dword(HWIO_TCSR_SPARE1_REG0_ADDR,v)
#define HWIO_TCSR_SPARE1_REG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPARE1_REG0_ADDR,m,v,HWIO_TCSR_SPARE1_REG0_IN)
#define HWIO_TCSR_SPARE1_REG0_SPARE1_REG0_BMSK                                                                          0xffffffff
#define HWIO_TCSR_SPARE1_REG0_SPARE1_REG0_SHFT                                                                                 0x0

#define HWIO_TCSR_SPARE1_REG1_ADDR                                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0000a050)
#define HWIO_TCSR_SPARE1_REG1_OFFS                                                                                      (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000a050)
#define HWIO_TCSR_SPARE1_REG1_RMSK                                                                                      0xffffffff
#define HWIO_TCSR_SPARE1_REG1_IN          \
        in_dword(HWIO_TCSR_SPARE1_REG1_ADDR)
#define HWIO_TCSR_SPARE1_REG1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPARE1_REG1_ADDR, m)
#define HWIO_TCSR_SPARE1_REG1_OUT(v)      \
        out_dword(HWIO_TCSR_SPARE1_REG1_ADDR,v)
#define HWIO_TCSR_SPARE1_REG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPARE1_REG1_ADDR,m,v,HWIO_TCSR_SPARE1_REG1_IN)
#define HWIO_TCSR_SPARE1_REG1_SPARE1_REG1_BMSK                                                                          0xffffffff
#define HWIO_TCSR_SPARE1_REG1_SPARE1_REG1_SHFT                                                                                 0x0

#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_ADDR                                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x00001010)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_OFFS                                                                                (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00001010)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_RMSK                                                                                    0xffff
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_IN          \
        in_dword(HWIO_TCSR_SPDM_CNT_CLK_CTRL_ADDR)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPDM_CNT_CLK_CTRL_ADDR, m)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_OUT(v)      \
        out_dword(HWIO_TCSR_SPDM_CNT_CLK_CTRL_ADDR,v)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPDM_CNT_CLK_CTRL_ADDR,m,v,HWIO_TCSR_SPDM_CNT_CLK_CTRL_IN)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_SPDM_CNT_CLK_MUX_SEL_BMSK                                                               0xffff
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_SPDM_CNT_CLK_MUX_SEL_SHFT                                                                  0x0

#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_ADDR                                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x00001018)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_OFFS                                                                                (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00001018)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_RMSK                                                                                0xffffffff
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_IN          \
        in_dword(HWIO_TCSR_SPDM_WRP_CTI_CTL0_ADDR)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPDM_WRP_CTI_CTL0_ADDR, m)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_OUT(v)      \
        out_dword(HWIO_TCSR_SPDM_WRP_CTI_CTL0_ADDR,v)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPDM_WRP_CTI_CTL0_ADDR,m,v,HWIO_TCSR_SPDM_WRP_CTI_CTL0_IN)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_SPDM_WRP_CTI_CTL0_BMSK                                                              0xffffffff
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_SPDM_WRP_CTI_CTL0_SHFT                                                                     0x0

#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_ADDR                                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0000101c)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_OFFS                                                                                (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000101c)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_RMSK                                                                                0xffffffff
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_IN          \
        in_dword(HWIO_TCSR_SPDM_WRP_CTI_CTL1_ADDR)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPDM_WRP_CTI_CTL1_ADDR, m)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_OUT(v)      \
        out_dword(HWIO_TCSR_SPDM_WRP_CTI_CTL1_ADDR,v)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPDM_WRP_CTI_CTL1_ADDR,m,v,HWIO_TCSR_SPDM_WRP_CTI_CTL1_IN)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_SPDM_WRP_CTI_CTL1_BMSK                                                              0xffffffff
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_SPDM_WRP_CTI_CTL1_SHFT                                                                     0x0

#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00016000)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_OFFS                                                                        (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00016000)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_RMSK                                                                               0x3
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_IN          \
        in_dword(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_ADDR)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_ADDR, m)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_OUT(v)      \
        out_dword(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_ADDR,v)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_ADDR,m,v,HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_IN)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_TEST_EN_1_BMSK                                                                     0x2
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_TEST_EN_1_SHFT                                                                     0x1
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_TEST_DATA_1_BMSK                                                                   0x1
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_TEST_DATA_1_SHFT                                                                   0x0

#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00016004)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_OFFS                                                                        (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00016004)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_RMSK                                                                               0x3
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_IN          \
        in_dword(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_ADDR)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_ADDR, m)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_OUT(v)      \
        out_dword(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_ADDR,v)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_ADDR,m,v,HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_IN)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_TEST_EN_0_BMSK                                                                     0x2
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_TEST_EN_0_SHFT                                                                     0x1
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_TEST_DATA_0_BMSK                                                                   0x1
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_TEST_DATA_0_SHFT                                                                   0x0

#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_ADDR                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x00017000)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_OFFS                                                                      (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00017000)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_RMSK                                                                             0x3
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_IN          \
        in_dword(HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_ADDR)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_INM(m)      \
        in_dword_masked(HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_ADDR, m)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_OUT(v)      \
        out_dword(HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_ADDR,v)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_ADDR,m,v,HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_IN)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_QDSS_NS_ENABLE_BACKPRESSURE_BMSK                                                 0x2
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_QDSS_NS_ENABLE_BACKPRESSURE_SHFT                                                 0x1
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_QDSS_NS_ENABLE_EVENT_IFACE_BMSK                                                  0x1
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_QDSS_NS_ENABLE_EVENT_IFACE_SHFT                                                  0x0

#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_ADDR                                                                     (TCSR_TCSR_REGS_REG_BASE      + 0x00017004)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_OFFS                                                                     (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00017004)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_RMSK                                                                            0x3
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_IN          \
        in_dword(HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_ADDR)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_INM(m)      \
        in_dword_masked(HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_ADDR, m)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_OUT(v)      \
        out_dword(HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_ADDR,v)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_ADDR,m,v,HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_IN)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_QDSS_SEC_ENABLE_BACKPRESSURE_BMSK                                               0x2
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_QDSS_SEC_ENABLE_BACKPRESSURE_SHFT                                               0x1
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_QDSS_SEC_ENABLE_EVENT_IFACE_BMSK                                                0x1
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_QDSS_SEC_ENABLE_EVENT_IFACE_SHFT                                                0x0

#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_ADDR                                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00017008)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_OFFS                                                                         (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00017008)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_RMSK                                                                                0x1
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_IN          \
        in_dword(HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_ADDR)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_INM(m)      \
        in_dword_masked(HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_ADDR, m)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_OUT(v)      \
        out_dword(HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_ADDR,v)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_ADDR,m,v,HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_IN)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_QDSS_NS_ETR_TRACE_BMSK                                                              0x1
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_QDSS_NS_ETR_TRACE_SHFT                                                              0x0

#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x00011000)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_OFFS                                                                (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00011000)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_RMSK                                                                       0x1
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_IN          \
        in_dword(HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_ADDR)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_INM(m)      \
        in_dword_masked(HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_ADDR, m)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_OUT(v)      \
        out_dword(HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_ADDR,v)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_ADDR,m,v,HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_IN)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_VSENSE_CONTROLLER_ENABLE_REGISTER_BMSK                                     0x1
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_VSENSE_CONTROLLER_ENABLE_REGISTER_SHFT                                     0x0

#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00012000)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_OFFS                                                                        (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00012000)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_RMSK                                                                        0xffffffff
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_IN          \
        in_dword(HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_ADDR)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_INM(m)      \
        in_dword_masked(HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_ADDR, m)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_OUT(v)      \
        out_dword(HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_ADDR,v)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_ADDR,m,v,HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_IN)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_TCSR_RESET_DEBUG_SW_ENTRY_BMSK                                              0xffffffff
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_TCSR_RESET_DEBUG_SW_ENTRY_SHFT                                                     0x0

#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00013000)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_OFFS                                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00013000)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_RMSK                                                                            0xffffffff
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_IN          \
        in_dword(HWIO_TCSR_TCSR_BOOT_MISC_DETECT_ADDR)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_INM(m)      \
        in_dword_masked(HWIO_TCSR_TCSR_BOOT_MISC_DETECT_ADDR, m)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_OUT(v)      \
        out_dword(HWIO_TCSR_TCSR_BOOT_MISC_DETECT_ADDR,v)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TCSR_BOOT_MISC_DETECT_ADDR,m,v,HWIO_TCSR_TCSR_BOOT_MISC_DETECT_IN)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_TCSR_BOOT_MISC_DETECT_BMSK                                                      0xffffffff
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_TCSR_BOOT_MISC_DETECT_SHFT                                                             0x0

#define HWIO_TCSR_TZ_WONCE_n_ADDR(n)                                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x00014000 + 0x4 * (n))
#define HWIO_TCSR_TZ_WONCE_n_OFFS(n)                                                                                    (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00014000 + 0x4 * (n))
#define HWIO_TCSR_TZ_WONCE_n_RMSK                                                                                       0xffffffff
#define HWIO_TCSR_TZ_WONCE_n_MAXn                                                                                               15
#define HWIO_TCSR_TZ_WONCE_n_INI(n)        \
        in_dword_masked(HWIO_TCSR_TZ_WONCE_n_ADDR(n), HWIO_TCSR_TZ_WONCE_n_RMSK)
#define HWIO_TCSR_TZ_WONCE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_TCSR_TZ_WONCE_n_ADDR(n), mask)
#define HWIO_TCSR_TZ_WONCE_n_OUTI(n,val)    \
        out_dword(HWIO_TCSR_TZ_WONCE_n_ADDR(n),val)
#define HWIO_TCSR_TZ_WONCE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_TCSR_TZ_WONCE_n_ADDR(n),mask,val,HWIO_TCSR_TZ_WONCE_n_INI(n))
#define HWIO_TCSR_TZ_WONCE_n_TZ_WONCE_ADDRESS_BMSK                                                                      0xffffffff
#define HWIO_TCSR_TZ_WONCE_n_TZ_WONCE_ADDRESS_SHFT                                                                             0x0

#define HWIO_TCSR_QREFS_RPT_CONFIG_ADDR                                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x00015000)
#define HWIO_TCSR_QREFS_RPT_CONFIG_OFFS                                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00015000)
#define HWIO_TCSR_QREFS_RPT_CONFIG_RMSK                                                                                     0xffff
#define HWIO_TCSR_QREFS_RPT_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_RPT_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_RPT_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_RPT_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_RPT_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_RPT_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_RPT_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_RPT_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_RPT_CONFIG_IN)
#define HWIO_TCSR_QREFS_RPT_CONFIG_QREFS_RPT_CONFIG_BUS_SELECT_BMSK                                                         0xffff
#define HWIO_TCSR_QREFS_RPT_CONFIG_QREFS_RPT_CONFIG_BUS_SELECT_SHFT                                                            0x0

#define HWIO_TCSR_QREFS_TXVBG_CONFIG_ADDR                                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00015004)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_OFFS                                                                               (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00015004)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_RMSK                                                                                   0xffff
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_TXVBG_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_TXVBG_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_TXVBG_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_TXVBG_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_TXVBG_CONFIG_IN)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_QREFS_TXVBG_CONFIG_BMSK                                                                0xffff
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_QREFS_TXVBG_CONFIG_SHFT                                                                   0x0

#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_ADDR                                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x00015008)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_OFFS                                                                             (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00015008)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_RMSK                                                                                   0xff
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO_RX3_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RX3_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO_RX3_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO_RX3_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO_RX3_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_QREFS_CXO_RX3_CONFIG_BMSK                                                              0xff
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_QREFS_CXO_RX3_CONFIG_SHFT                                                               0x0

#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_ADDR                                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x0001500c)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_OFFS                                                                             (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001500c)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_RMSK                                                                                   0xff
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO_RX2_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RX2_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO_RX2_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO_RX2_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO_RX2_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_QREFS_CXO_RX2_CONFIG_BMSK                                                              0xff
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_QREFS_CXO_RX2_CONFIG_SHFT                                                               0x0

#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00015010)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_OFFS                                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00015010)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_RMSK                                                                                  0xff
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_QREFS_CXO_RPT2_CONFIG_BMSK                                                            0xff
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_QREFS_CXO_RPT2_CONFIG_SHFT                                                             0x0

#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00015018)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_OFFS                                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00015018)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_RMSK                                                                                  0xff
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_QREFS_CXO2_RX0_CONFIG_BMSK                                                            0xff
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_QREFS_CXO2_RX0_CONFIG_SHFT                                                             0x0

#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_ADDR                                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0001501c)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_OFFS                                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001501c)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_RMSK                                                                                 0xff
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_QREFS_CXO2_RPT1_CONFIG_BMSK                                                          0xff
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_QREFS_CXO2_RPT1_CONFIG_SHFT                                                           0x0

#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_ADDR                                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00015020)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_OFFS                                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00015020)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_RMSK                                                                                 0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_QREFS_CXO2_RPT0_CONFIG_BMSK                                                          0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_QREFS_CXO2_RPT0_CONFIG_SHFT                                                           0x0

#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_ADDR                                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00015024)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_OFFS                                                                         (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00015024)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_RMSK                                                                             0xffff
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_QREFS_CXO2_TXVBG0_CONFIG_BMSK                                                    0xffff
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_QREFS_CXO2_TXVBG0_CONFIG_SHFT                                                       0x0

#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0001502c)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_OFFS                                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001502c)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_RMSK                                                                                  0xff
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_QREFS_CXO_RPT3_CONFIG_BMSK                                                            0xff
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_QREFS_CXO_RPT3_CONFIG_SHFT                                                             0x0

#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x00015030)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_OFFS                                                                          (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00015030)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_RMSK                                                                                0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_QREFS_CXO2_RPT0A_CONFIG_BMSK                                                        0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_QREFS_CXO2_RPT0A_CONFIG_SHFT                                                         0x0

#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x00015034)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_OFFS                                                                          (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00015034)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_RMSK                                                                                0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_QREFS_CXO2_RPT0B_CONFIG_BMSK                                                        0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_QREFS_CXO2_RPT0B_CONFIG_SHFT                                                         0x0

#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_ADDR                                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x00015038)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_OFFS                                                                             (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00015038)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_RMSK                                                                                   0xff
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO_RX1_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RX1_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO_RX1_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO_RX1_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO_RX1_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_QREFS_CXO_RX1_CONFIG_BMSK                                                              0xff
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_QREFS_CXO_RX1_CONFIG_SHFT                                                               0x0

#define HWIO_TCSR_QZIP_CTL_ST_ADDR                                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0000c000)
#define HWIO_TCSR_QZIP_CTL_ST_OFFS                                                                                      (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000c000)
#define HWIO_TCSR_QZIP_CTL_ST_RMSK                                                                                            0xff
#define HWIO_TCSR_QZIP_CTL_ST_IN          \
        in_dword(HWIO_TCSR_QZIP_CTL_ST_ADDR)
#define HWIO_TCSR_QZIP_CTL_ST_INM(m)      \
        in_dword_masked(HWIO_TCSR_QZIP_CTL_ST_ADDR, m)
#define HWIO_TCSR_QZIP_CTL_ST_OUT(v)      \
        out_dword(HWIO_TCSR_QZIP_CTL_ST_ADDR,v)
#define HWIO_TCSR_QZIP_CTL_ST_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QZIP_CTL_ST_ADDR,m,v,HWIO_TCSR_QZIP_CTL_ST_IN)
#define HWIO_TCSR_QZIP_CTL_ST_QZIP_CTL_ST_BMSK                                                                                0xff
#define HWIO_TCSR_QZIP_CTL_ST_QZIP_CTL_ST_SHFT                                                                                 0x0

#define HWIO_TCSR_TIC_CNOC_NS_ADDR                                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0000c004)
#define HWIO_TCSR_TIC_CNOC_NS_OFFS                                                                                      (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000c004)
#define HWIO_TCSR_TIC_CNOC_NS_RMSK                                                                                             0x1
#define HWIO_TCSR_TIC_CNOC_NS_IN          \
        in_dword(HWIO_TCSR_TIC_CNOC_NS_ADDR)
#define HWIO_TCSR_TIC_CNOC_NS_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIC_CNOC_NS_ADDR, m)
#define HWIO_TCSR_TIC_CNOC_NS_OUT(v)      \
        out_dword(HWIO_TCSR_TIC_CNOC_NS_ADDR,v)
#define HWIO_TCSR_TIC_CNOC_NS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIC_CNOC_NS_ADDR,m,v,HWIO_TCSR_TIC_CNOC_NS_IN)
#define HWIO_TCSR_TIC_CNOC_NS_TIC_CNOC_NS_BMSK                                                                                 0x1
#define HWIO_TCSR_TIC_CNOC_NS_TIC_CNOC_NS_SHFT                                                                                 0x0

#define HWIO_TCSR_CONN_BOX_SPARE_0_ADDR                                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000e000)
#define HWIO_TCSR_CONN_BOX_SPARE_0_OFFS                                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000e000)
#define HWIO_TCSR_CONN_BOX_SPARE_0_RMSK                                                                                 0xffffffff
#define HWIO_TCSR_CONN_BOX_SPARE_0_IN          \
        in_dword(HWIO_TCSR_CONN_BOX_SPARE_0_ADDR)
#define HWIO_TCSR_CONN_BOX_SPARE_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_CONN_BOX_SPARE_0_ADDR, m)
#define HWIO_TCSR_CONN_BOX_SPARE_0_OUT(v)      \
        out_dword(HWIO_TCSR_CONN_BOX_SPARE_0_ADDR,v)
#define HWIO_TCSR_CONN_BOX_SPARE_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_CONN_BOX_SPARE_0_ADDR,m,v,HWIO_TCSR_CONN_BOX_SPARE_0_IN)
#define HWIO_TCSR_CONN_BOX_SPARE_0_CONN_BOX_SPARE_0_BMSK                                                                0xffffffff
#define HWIO_TCSR_CONN_BOX_SPARE_0_CONN_BOX_SPARE_0_SHFT                                                                       0x0

#define HWIO_TCSR_CONN_BOX_SPARE_1_ADDR                                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000f000)
#define HWIO_TCSR_CONN_BOX_SPARE_1_OFFS                                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0000f000)
#define HWIO_TCSR_CONN_BOX_SPARE_1_RMSK                                                                                 0xffffffff
#define HWIO_TCSR_CONN_BOX_SPARE_1_IN          \
        in_dword(HWIO_TCSR_CONN_BOX_SPARE_1_ADDR)
#define HWIO_TCSR_CONN_BOX_SPARE_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_CONN_BOX_SPARE_1_ADDR, m)
#define HWIO_TCSR_CONN_BOX_SPARE_1_OUT(v)      \
        out_dword(HWIO_TCSR_CONN_BOX_SPARE_1_ADDR,v)
#define HWIO_TCSR_CONN_BOX_SPARE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_CONN_BOX_SPARE_1_ADDR,m,v,HWIO_TCSR_CONN_BOX_SPARE_1_IN)
#define HWIO_TCSR_CONN_BOX_SPARE_1_CONN_BOX_SPARE_1_BMSK                                                                0xffffffff
#define HWIO_TCSR_CONN_BOX_SPARE_1_CONN_BOX_SPARE_1_SHFT                                                                       0x0

#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_ADDR                                                                     (TCSR_TCSR_REGS_REG_BASE      + 0x00018000)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_OFFS                                                                     (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00018000)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_RMSK                                                                     0xffffffff
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_IN          \
        in_dword(HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_ADDR)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_INM(m)      \
        in_dword_masked(HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_ADDR, m)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_OUT(v)      \
        out_dword(HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_ADDR,v)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_ADDR,m,v,HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_IN)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_CFG_BITS_SHFT_BMSK                                                       0xffffffff
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_CFG_BITS_SHFT_SHFT                                                              0x0

#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00019000)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_OFFS                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00019000)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_RMSK                                                                  0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_IN          \
        in_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_ADDR)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_ADDR, m)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_OUT(v)      \
        out_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_ADDR,v)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_ADDR,m,v,HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_IN)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_USER_COMPUTE_SIGNALING_WRITE_STATUS_BMSK                              0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_USER_COMPUTE_SIGNALING_WRITE_STATUS_SHFT                                     0x0

#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00019004)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_OFFS                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00019004)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_RMSK                                                                  0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_IN          \
        in_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_ADDR)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_ADDR, m)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_OUT(v)      \
        out_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_ADDR,v)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_ADDR,m,v,HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_IN)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_USER_COMPUTE_SIGNALING_WRITE_STATUS_BMSK                              0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_USER_COMPUTE_SIGNALING_WRITE_STATUS_SHFT                                     0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0001a000)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001a000)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_RMSK                                                           0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_ADDR)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_0_STATUS_USER_BMSK                                   0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_0_STATUS_USER_SHFT                                          0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0001a400)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_OFFS                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001a400)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_RMSK                                                            0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_0_CLEAR_USER_BMSK                                     0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_0_CLEAR_USER_SHFT                                            0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_ADDR                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x0001a800)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_OFFS                                                             (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001a800)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_RMSK                                                             0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_ADDR)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_ADDR,m,v,HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_IN)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_0_MASK_USER_BMSK                                       0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_0_MASK_USER_SHFT                                              0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0001b000)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001b000)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_RMSK                                                           0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_ADDR)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_1_STATUS_USER_BMSK                                   0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_1_STATUS_USER_SHFT                                          0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0001b400)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_OFFS                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001b400)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_RMSK                                                            0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_1_CLEAR_USER_BMSK                                     0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_1_CLEAR_USER_SHFT                                            0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_ADDR                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x0001b800)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_OFFS                                                             (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001b800)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_RMSK                                                             0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_ADDR)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_ADDR,m,v,HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_IN)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_1_MASK_USER_BMSK                                       0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_1_MASK_USER_SHFT                                              0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0001c000)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001c000)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_RMSK                                                           0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_ADDR)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_2_STATUS_USER_BMSK                                   0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_2_STATUS_USER_SHFT                                          0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0001c400)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_OFFS                                                            (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001c400)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_RMSK                                                            0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_2_CLEAR_USER_BMSK                                     0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_2_CLEAR_USER_SHFT                                            0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_ADDR                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x0001c800)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_OFFS                                                             (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001c800)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_RMSK                                                             0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_ADDR)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_ADDR,m,v,HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_IN)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_2_MASK_USER_BMSK                                       0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_2_MASK_USER_SHFT                                              0x0

#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0001d000)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_OFFS                                                                (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001d000)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_RMSK                                                                0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_IN          \
        in_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_ADDR)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_ADDR, m)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_OUT(v)      \
        out_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_ADDR,v)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_ADDR,m,v,HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_IN)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_KERNEL_COMPUTE_SIGNALING_WRITE_STATUS_BMSK                          0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_KERNEL_COMPUTE_SIGNALING_WRITE_STATUS_SHFT                                 0x0

#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0001d004)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_OFFS                                                                (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001d004)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_RMSK                                                                0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_IN          \
        in_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_ADDR)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_ADDR, m)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_OUT(v)      \
        out_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_ADDR,v)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_ADDR,m,v,HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_IN)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_KERNEL_COMPUTE_SIGNALING_WRITE_STATUS_BMSK                          0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_KERNEL_COMPUTE_SIGNALING_WRITE_STATUS_SHFT                                 0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x0001e000)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_OFFS                                                         (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001e000)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_RMSK                                                         0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_0_STATUS_KERNEL_BMSK                               0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_0_STATUS_KERNEL_SHFT                                      0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x0001e400)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_OFFS                                                          (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001e400)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_RMSK                                                          0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_0_CLEAR_KERNEL_BMSK                                 0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_0_CLEAR_KERNEL_SHFT                                        0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0001e800)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001e800)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_RMSK                                                           0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_ADDR)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,m,v,HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_IN)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_0_MASK_KERNEL_BMSK                                   0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_0_MASK_KERNEL_SHFT                                          0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x0001f000)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_OFFS                                                         (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001f000)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_RMSK                                                         0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_1_STATUS_KERNEL_BMSK                               0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_1_STATUS_KERNEL_SHFT                                      0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x0001f400)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_OFFS                                                          (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001f400)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_RMSK                                                          0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_1_CLEAR_KERNEL_BMSK                                 0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_1_CLEAR_KERNEL_SHFT                                        0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0001f800)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0001f800)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_RMSK                                                           0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_ADDR)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,m,v,HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_IN)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_1_MASK_KERNEL_BMSK                                   0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_1_MASK_KERNEL_SHFT                                          0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00020000)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_OFFS                                                         (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00020000)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_RMSK                                                         0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_2_STATUS_KERNEL_BMSK                               0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_2_STATUS_KERNEL_SHFT                                      0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x00020400)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_OFFS                                                          (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00020400)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_RMSK                                                          0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_2_CLEAR_KERNEL_BMSK                                 0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_2_CLEAR_KERNEL_SHFT                                        0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00020800)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_OFFS                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00020800)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_RMSK                                                           0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_ADDR)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,m,v,HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_IN)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_2_MASK_KERNEL_BMSK                                   0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_2_MASK_KERNEL_SHFT                                          0x0

#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_ADDR                                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00023000)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_OFFS                                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00023000)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_RMSK                                                                                  0x3
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_IN          \
        in_dword(HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_ADDR)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_INM(m)      \
        in_dword_masked(HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_ADDR, m)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_OUT(v)      \
        out_dword(HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_ADDR,v)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_ADDR,m,v,HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_IN)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_A1NOC_SP_BYPASS_CHECK_TYPE_BMSK                                                       0x2
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_A1NOC_SP_BYPASS_CHECK_TYPE_SHFT                                                       0x1
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_A1NOC_MSA_BYPASS_CHECK_TYPE_BMSK                                                      0x1
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_A1NOC_MSA_BYPASS_CHECK_TYPE_SHFT                                                      0x0

#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_ADDR                                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00023004)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_OFFS                                                                           (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00023004)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_RMSK                                                                                  0x3
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_IN          \
        in_dword(HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_ADDR)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_INM(m)      \
        in_dword_masked(HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_ADDR, m)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_OUT(v)      \
        out_dword(HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_ADDR,v)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_ADDR,m,v,HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_IN)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_A2NOC_SP_BYPASS_CHECK_TYPE_BMSK                                                       0x2
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_A2NOC_SP_BYPASS_CHECK_TYPE_SHFT                                                       0x1
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_A2NOC_MSA_BYPASS_CHECK_TYPE_BMSK                                                      0x1
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_A2NOC_MSA_BYPASS_CHECK_TYPE_SHFT                                                      0x0

#define HWIO_TCSR_WCSS_TESTBUS_SEL_ADDR                                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x00024000)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_OFFS                                                                                 (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00024000)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_RMSK                                                                                       0xff
#define HWIO_TCSR_WCSS_TESTBUS_SEL_IN          \
        in_dword(HWIO_TCSR_WCSS_TESTBUS_SEL_ADDR)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_WCSS_TESTBUS_SEL_ADDR, m)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_OUT(v)      \
        out_dword(HWIO_TCSR_WCSS_TESTBUS_SEL_ADDR,v)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_WCSS_TESTBUS_SEL_ADDR,m,v,HWIO_TCSR_WCSS_TESTBUS_SEL_IN)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_WCSS_TESTBUS_SEL_BMSK                                                                      0xff
#define HWIO_TCSR_WCSS_TESTBUS_SEL_WCSS_TESTBUS_SEL_SHFT                                                                       0x0

#define HWIO_TCSR_WCSS_AHBBM_CTRL_ADDR                                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00024004)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_OFFS                                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00024004)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_RMSK                                                                                         0x7
#define HWIO_TCSR_WCSS_AHBBM_CTRL_IN          \
        in_dword(HWIO_TCSR_WCSS_AHBBM_CTRL_ADDR)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_INM(m)      \
        in_dword_masked(HWIO_TCSR_WCSS_AHBBM_CTRL_ADDR, m)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_OUT(v)      \
        out_dword(HWIO_TCSR_WCSS_AHBBM_CTRL_ADDR,v)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_WCSS_AHBBM_CTRL_ADDR,m,v,HWIO_TCSR_WCSS_AHBBM_CTRL_IN)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_SOFT_RESET_BMSK                                                                        0x4
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_SOFT_RESET_SHFT                                                                        0x2
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_CLKGATE_DISABLE_BMSK                                                                   0x2
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_CLKGATE_DISABLE_SHFT                                                                   0x1
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_ROOT_CLK_ENABLE_BMSK                                                                   0x1
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_ROOT_CLK_ENABLE_SHFT                                                                   0x0

#define HWIO_TCSR_APSS_SPARE_REG0_ADDR                                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00025014)
#define HWIO_TCSR_APSS_SPARE_REG0_OFFS                                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00025014)
#define HWIO_TCSR_APSS_SPARE_REG0_RMSK                                                                                  0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG0_IN          \
        in_dword(HWIO_TCSR_APSS_SPARE_REG0_ADDR)
#define HWIO_TCSR_APSS_SPARE_REG0_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG0_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG0_OUT(v)      \
        out_dword(HWIO_TCSR_APSS_SPARE_REG0_ADDR,v)
#define HWIO_TCSR_APSS_SPARE_REG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_APSS_SPARE_REG0_ADDR,m,v,HWIO_TCSR_APSS_SPARE_REG0_IN)
#define HWIO_TCSR_APSS_SPARE_REG0_SPARE_REG0_BMSK                                                                       0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG0_SPARE_REG0_SHFT                                                                              0x0

#define HWIO_TCSR_APSS_SPARE_REG1_ADDR                                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00025018)
#define HWIO_TCSR_APSS_SPARE_REG1_OFFS                                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00025018)
#define HWIO_TCSR_APSS_SPARE_REG1_RMSK                                                                                  0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG1_IN          \
        in_dword(HWIO_TCSR_APSS_SPARE_REG1_ADDR)
#define HWIO_TCSR_APSS_SPARE_REG1_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG1_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG1_OUT(v)      \
        out_dword(HWIO_TCSR_APSS_SPARE_REG1_ADDR,v)
#define HWIO_TCSR_APSS_SPARE_REG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_APSS_SPARE_REG1_ADDR,m,v,HWIO_TCSR_APSS_SPARE_REG1_IN)
#define HWIO_TCSR_APSS_SPARE_REG1_SPARE_REG1_BMSK                                                                       0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG1_SPARE_REG1_SHFT                                                                              0x0

#define HWIO_TCSR_APSS_SPARE_REG2_ADDR                                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x0002501c)
#define HWIO_TCSR_APSS_SPARE_REG2_OFFS                                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002501c)
#define HWIO_TCSR_APSS_SPARE_REG2_RMSK                                                                                  0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG2_IN          \
        in_dword(HWIO_TCSR_APSS_SPARE_REG2_ADDR)
#define HWIO_TCSR_APSS_SPARE_REG2_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG2_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG2_OUT(v)      \
        out_dword(HWIO_TCSR_APSS_SPARE_REG2_ADDR,v)
#define HWIO_TCSR_APSS_SPARE_REG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_APSS_SPARE_REG2_ADDR,m,v,HWIO_TCSR_APSS_SPARE_REG2_IN)
#define HWIO_TCSR_APSS_SPARE_REG2_SPARE_REG2_BMSK                                                                       0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG2_SPARE_REG2_SHFT                                                                              0x0

#define HWIO_TCSR_APSS_SPARE_REG3_ADDR                                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00025020)
#define HWIO_TCSR_APSS_SPARE_REG3_OFFS                                                                                  (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00025020)
#define HWIO_TCSR_APSS_SPARE_REG3_RMSK                                                                                  0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG3_IN          \
        in_dword(HWIO_TCSR_APSS_SPARE_REG3_ADDR)
#define HWIO_TCSR_APSS_SPARE_REG3_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG3_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG3_OUT(v)      \
        out_dword(HWIO_TCSR_APSS_SPARE_REG3_ADDR,v)
#define HWIO_TCSR_APSS_SPARE_REG3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_APSS_SPARE_REG3_ADDR,m,v,HWIO_TCSR_APSS_SPARE_REG3_IN)
#define HWIO_TCSR_APSS_SPARE_REG3_SPARE_REG3_BMSK                                                                       0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG3_SPARE_REG3_SHFT                                                                              0x0

#define HWIO_TCSR_APSS_SPARE_REG_RD_0_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00025024)
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_OFFS                                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00025024)
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_RMSK                                                                              0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_IN          \
        in_dword(HWIO_TCSR_APSS_SPARE_REG_RD_0_ADDR)
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG_RD_0_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_SPARE_REG_RD_0_BMSK                                                               0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_SPARE_REG_RD_0_SHFT                                                                      0x0

#define HWIO_TCSR_APSS_SPARE_REG_RD_1_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00025028)
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_OFFS                                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00025028)
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_RMSK                                                                              0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_IN          \
        in_dword(HWIO_TCSR_APSS_SPARE_REG_RD_1_ADDR)
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG_RD_1_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_SPARE_REG_RD_1_BMSK                                                               0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_SPARE_REG_RD_1_SHFT                                                                      0x0

#define HWIO_TCSR_APSS_SPARE_REG_RD_2_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002502c)
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_OFFS                                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002502c)
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_RMSK                                                                              0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_IN          \
        in_dword(HWIO_TCSR_APSS_SPARE_REG_RD_2_ADDR)
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG_RD_2_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_SPARE_REG_RD_2_BMSK                                                               0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_SPARE_REG_RD_2_SHFT                                                                      0x0

#define HWIO_TCSR_APSS_SPARE_REG_RD_3_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00025030)
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_OFFS                                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00025030)
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_RMSK                                                                              0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_IN          \
        in_dword(HWIO_TCSR_APSS_SPARE_REG_RD_3_ADDR)
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG_RD_3_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_SPARE_REG_RD_3_BMSK                                                               0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_SPARE_REG_RD_3_SHFT                                                                      0x0

#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x00013100)
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_OFFS                                                                          (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00013100)
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_RMSK                                                                          0xffffffff
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_IN          \
        in_dword(HWIO_TCSR_BOOT_IMEM_START_ADDRESS_ADDR)
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_INM(m)      \
        in_dword_masked(HWIO_TCSR_BOOT_IMEM_START_ADDRESS_ADDR, m)
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_BOOT_IMEM_START_ADDRESS_BMSK                                                  0xffffffff
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_BOOT_IMEM_START_ADDRESS_SHFT                                                         0x0

#define HWIO_TCSR_BOOT_IMEM_SIZE_ADDR                                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x00013200)
#define HWIO_TCSR_BOOT_IMEM_SIZE_OFFS                                                                                   (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00013200)
#define HWIO_TCSR_BOOT_IMEM_SIZE_RMSK                                                                                   0xffffffff
#define HWIO_TCSR_BOOT_IMEM_SIZE_IN          \
        in_dword(HWIO_TCSR_BOOT_IMEM_SIZE_ADDR)
#define HWIO_TCSR_BOOT_IMEM_SIZE_INM(m)      \
        in_dword_masked(HWIO_TCSR_BOOT_IMEM_SIZE_ADDR, m)
#define HWIO_TCSR_BOOT_IMEM_SIZE_BOOT_IMEM_SIZE_BMSK                                                                    0xffffffff
#define HWIO_TCSR_BOOT_IMEM_SIZE_BOOT_IMEM_SIZE_SHFT                                                                           0x0

#define HWIO_TCSR_BOOT_IMEM_DISABLE_ADDR                                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x00013300)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_OFFS                                                                                (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00013300)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_RMSK                                                                                       0x1
#define HWIO_TCSR_BOOT_IMEM_DISABLE_IN          \
        in_dword(HWIO_TCSR_BOOT_IMEM_DISABLE_ADDR)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_BOOT_IMEM_DISABLE_ADDR, m)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_OUT(v)      \
        out_dword(HWIO_TCSR_BOOT_IMEM_DISABLE_ADDR,v)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_BOOT_IMEM_DISABLE_ADDR,m,v,HWIO_TCSR_BOOT_IMEM_DISABLE_IN)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_BOOT_IMEM_DISABLE_BMSK                                                                     0x1
#define HWIO_TCSR_BOOT_IMEM_DISABLE_BOOT_IMEM_DISABLE_SHFT                                                                     0x0

#define HWIO_TCSR_BIAS_REF_LS_EN_ADDR                                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x00026000)
#define HWIO_TCSR_BIAS_REF_LS_EN_OFFS                                                                                   (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x00026000)
#define HWIO_TCSR_BIAS_REF_LS_EN_RMSK                                                                                         0x3f
#define HWIO_TCSR_BIAS_REF_LS_EN_IN          \
        in_dword(HWIO_TCSR_BIAS_REF_LS_EN_ADDR)
#define HWIO_TCSR_BIAS_REF_LS_EN_INM(m)      \
        in_dword_masked(HWIO_TCSR_BIAS_REF_LS_EN_ADDR, m)
#define HWIO_TCSR_BIAS_REF_LS_EN_OUT(v)      \
        out_dword(HWIO_TCSR_BIAS_REF_LS_EN_ADDR,v)
#define HWIO_TCSR_BIAS_REF_LS_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_BIAS_REF_LS_EN_ADDR,m,v,HWIO_TCSR_BIAS_REF_LS_EN_IN)
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_3_AUXBUF_EN_BMSK                                                                 0x20
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_3_AUXBUF_EN_SHFT                                                                  0x5
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_3_ATEST_EN_BMSK                                                                  0x10
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_3_ATEST_EN_SHFT                                                                   0x4
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_2_AUXBUF_EN_BMSK                                                                  0x8
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_2_AUXBUF_EN_SHFT                                                                  0x3
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_2_ATEST_EN_BMSK                                                                   0x4
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_2_ATEST_EN_SHFT                                                                   0x2
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_1_AUXBUF_EN_BMSK                                                                  0x2
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_1_AUXBUF_EN_SHFT                                                                  0x1
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_1_ATEST_EN_BMSK                                                                   0x1
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_1_ATEST_EN_SHFT                                                                   0x0

#define HWIO_TCSR_REFGEN_QLINK_ENABLE_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002c000)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_OFFS                                                                              (TCSR_TCSR_REGS_REG_BASE_OFFS + 0x0002c000)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_RMSK                                                                                     0x1
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_IN          \
        in_dword(HWIO_TCSR_REFGEN_QLINK_ENABLE_ADDR)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_REFGEN_QLINK_ENABLE_ADDR, m)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_REFGEN_QLINK_ENABLE_ADDR,v)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_REFGEN_QLINK_ENABLE_ADDR,m,v,HWIO_TCSR_REFGEN_QLINK_ENABLE_IN)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_REFGEN_QLINK_ENABLE_BMSK                                                                 0x1
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_REFGEN_QLINK_ENABLE_SHFT                                                                 0x0

/*----------------------------------------------------------------------------
 * MODULE: AOSS_CC_AOSS_CC_REG
 *--------------------------------------------------------------------------*/

#define AOSS_CC_AOSS_CC_REG_REG_BASE                                                      (AOSS_BASE      + 0x012a0000)
#define AOSS_CC_AOSS_CC_REG_REG_BASE_SIZE                                                 0x60000
#define AOSS_CC_AOSS_CC_REG_REG_BASE_USED                                                 0x51000
#define AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS                                                 0x012a0000

#define HWIO_AOSS_CC_PLL0_MODE_ADDR                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000000)
#define HWIO_AOSS_CC_PLL0_MODE_OFFS                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_AOSS_CC_PLL0_MODE_RMSK                                                       0xffffffff
#define HWIO_AOSS_CC_PLL0_MODE_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_MODE_ADDR)
#define HWIO_AOSS_CC_PLL0_MODE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_MODE_ADDR, m)
#define HWIO_AOSS_CC_PLL0_MODE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_MODE_ADDR,v)
#define HWIO_AOSS_CC_PLL0_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_MODE_ADDR,m,v,HWIO_AOSS_CC_PLL0_MODE_IN)
#define HWIO_AOSS_CC_PLL0_MODE_PLL_LOCK_DET_BMSK                                          0x80000000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_LOCK_DET_SHFT                                                0x1f
#define HWIO_AOSS_CC_PLL0_MODE_PLL_ACTIVE_FLAG_BMSK                                       0x40000000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_ACTIVE_FLAG_SHFT                                             0x1e
#define HWIO_AOSS_CC_PLL0_MODE_PLL_ACK_LATCH_BMSK                                         0x20000000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_ACK_LATCH_SHFT                                               0x1d
#define HWIO_AOSS_CC_PLL0_MODE_PLL_LOCK_DET_FINE_BMSK                                     0x10000000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_LOCK_DET_FINE_SHFT                                           0x1c
#define HWIO_AOSS_CC_PLL0_MODE_PCAL_DONE_BMSK                                              0x8000000
#define HWIO_AOSS_CC_PLL0_MODE_PCAL_DONE_SHFT                                                   0x1b
#define HWIO_AOSS_CC_PLL0_MODE_PCAL_DONE_PROCESS_CALIBRATION_NOT_DONE_FVAL                       0x0
#define HWIO_AOSS_CC_PLL0_MODE_PCAL_DONE_PROCESS_CALIBRATION_DONE_FVAL                           0x1
#define HWIO_AOSS_CC_PLL0_MODE_RESERVE_BITS26_25_BMSK                                      0x6000000
#define HWIO_AOSS_CC_PLL0_MODE_RESERVE_BITS26_25_SHFT                                           0x19
#define HWIO_AOSS_CC_PLL0_MODE_FSM_LEGACY_MODE_BMSK                                        0x1000000
#define HWIO_AOSS_CC_PLL0_MODE_FSM_LEGACY_MODE_SHFT                                             0x18
#define HWIO_AOSS_CC_PLL0_MODE_FSM_LEGACY_MODE_DISABLE_VOTE_FSM_LEGACY_MODE_FVAL                 0x0
#define HWIO_AOSS_CC_PLL0_MODE_FSM_LEGACY_MODE_ENABLE_VOTE_FSM_LEGACY_MODE_FVAL                  0x1
#define HWIO_AOSS_CC_PLL0_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_BMSK                              0x800000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_SHFT                                  0x17
#define HWIO_AOSS_CC_PLL0_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_NO_BYPASS_FVAL                         0x0
#define HWIO_AOSS_CC_PLL0_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_BYPASS_FVAL                            0x1
#define HWIO_AOSS_CC_PLL0_MODE_PLL_UPDATE_BMSK                                              0x400000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_UPDATE_SHFT                                                  0x16
#define HWIO_AOSS_CC_PLL0_MODE_PLL_UPDATE_NO_UPDATE_FVAL                                         0x0
#define HWIO_AOSS_CC_PLL0_MODE_PLL_UPDATE_UPDATE_FVAL                                            0x1
#define HWIO_AOSS_CC_PLL0_MODE_PLL_VOTE_FSM_RESET_BMSK                                      0x200000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_VOTE_FSM_RESET_SHFT                                          0x15
#define HWIO_AOSS_CC_PLL0_MODE_PLL_VOTE_FSM_RESET_NO_RESET_FVAL                                  0x0
#define HWIO_AOSS_CC_PLL0_MODE_PLL_VOTE_FSM_RESET_RESET_FVAL                                     0x1
#define HWIO_AOSS_CC_PLL0_MODE_PLL_VOTE_FSM_ENA_BMSK                                        0x100000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_VOTE_FSM_ENA_SHFT                                            0x14
#define HWIO_AOSS_CC_PLL0_MODE_PLL_VOTE_FSM_ENA_DISABLE_FVAL                                     0x0
#define HWIO_AOSS_CC_PLL0_MODE_PLL_VOTE_FSM_ENA_ENABLE_FVAL                                      0x1
#define HWIO_AOSS_CC_PLL0_MODE_PLL_BIAS_COUNT_BMSK                                           0xfc000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_BIAS_COUNT_SHFT                                               0xe
#define HWIO_AOSS_CC_PLL0_MODE_PLL_LOCK_COUNT_BMSK                                            0x3f00
#define HWIO_AOSS_CC_PLL0_MODE_PLL_LOCK_COUNT_SHFT                                               0x8
#define HWIO_AOSS_CC_PLL0_MODE_RESERVE_BIT7_BMSK                                                0x80
#define HWIO_AOSS_CC_PLL0_MODE_RESERVE_BIT7_SHFT                                                 0x7
#define HWIO_AOSS_CC_PLL0_MODE_OUT_TEST_HW_CTL_BMSK                                             0x40
#define HWIO_AOSS_CC_PLL0_MODE_OUT_TEST_HW_CTL_SHFT                                              0x6
#define HWIO_AOSS_CC_PLL0_MODE_OUT_TEST_HW_CTL_SW_CONTROL_FVAL                                   0x0
#define HWIO_AOSS_CC_PLL0_MODE_OUT_TEST_HW_CTL_HW_CONTROL_FVAL                                   0x1
#define HWIO_AOSS_CC_PLL0_MODE_OUT_ODD_HW_CTL_BMSK                                              0x20
#define HWIO_AOSS_CC_PLL0_MODE_OUT_ODD_HW_CTL_SHFT                                               0x5
#define HWIO_AOSS_CC_PLL0_MODE_OUT_ODD_HW_CTL_SW_CONTROL_FVAL                                    0x0
#define HWIO_AOSS_CC_PLL0_MODE_OUT_ODD_HW_CTL_HW_CONTROL_FVAL                                    0x1
#define HWIO_AOSS_CC_PLL0_MODE_OUT_EVEN_HW_CTL_BMSK                                             0x10
#define HWIO_AOSS_CC_PLL0_MODE_OUT_EVEN_HW_CTL_SHFT                                              0x4
#define HWIO_AOSS_CC_PLL0_MODE_OUT_EVEN_HW_CTL_SW_CONTROL_FVAL                                   0x0
#define HWIO_AOSS_CC_PLL0_MODE_OUT_EVEN_HW_CTL_HW_CONTROL_FVAL                                   0x1
#define HWIO_AOSS_CC_PLL0_MODE_OUT_MAIN_HW_CTL_BMSK                                              0x8
#define HWIO_AOSS_CC_PLL0_MODE_OUT_MAIN_HW_CTL_SHFT                                              0x3
#define HWIO_AOSS_CC_PLL0_MODE_OUT_MAIN_HW_CTL_SW_CONTROL_FVAL                                   0x0
#define HWIO_AOSS_CC_PLL0_MODE_OUT_MAIN_HW_CTL_HW_CONTROL_FVAL                                   0x1
#define HWIO_AOSS_CC_PLL0_MODE_PLL_RESET_N_BMSK                                                  0x4
#define HWIO_AOSS_CC_PLL0_MODE_PLL_RESET_N_SHFT                                                  0x2
#define HWIO_AOSS_CC_PLL0_MODE_PLL_RESET_N_RESET_FVAL                                            0x0
#define HWIO_AOSS_CC_PLL0_MODE_PLL_RESET_N_NO_RESET_FVAL                                         0x1
#define HWIO_AOSS_CC_PLL0_MODE_RESERVE_BIT1_BMSK                                                 0x2
#define HWIO_AOSS_CC_PLL0_MODE_RESERVE_BIT1_SHFT                                                 0x1
#define HWIO_AOSS_CC_PLL0_MODE_PLL_OUTCTRL_BMSK                                                  0x1
#define HWIO_AOSS_CC_PLL0_MODE_PLL_OUTCTRL_SHFT                                                  0x0
#define HWIO_AOSS_CC_PLL0_MODE_PLL_OUTCTRL_DISABLE_FVAL                                          0x0
#define HWIO_AOSS_CC_PLL0_MODE_PLL_OUTCTRL_ENABLE_FVAL                                           0x1

#define HWIO_AOSS_CC_PLL0_L_VAL_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000004)
#define HWIO_AOSS_CC_PLL0_L_VAL_OFFS                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_AOSS_CC_PLL0_L_VAL_RMSK                                                          0xffff
#define HWIO_AOSS_CC_PLL0_L_VAL_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_L_VAL_ADDR)
#define HWIO_AOSS_CC_PLL0_L_VAL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_L_VAL_ADDR, m)
#define HWIO_AOSS_CC_PLL0_L_VAL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_L_VAL_ADDR,v)
#define HWIO_AOSS_CC_PLL0_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_L_VAL_ADDR,m,v,HWIO_AOSS_CC_PLL0_L_VAL_IN)
#define HWIO_AOSS_CC_PLL0_L_VAL_PLL_L_BMSK                                                    0xffff
#define HWIO_AOSS_CC_PLL0_L_VAL_PLL_L_SHFT                                                       0x0

#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000008)
#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_OFFS                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_RMSK                                                      0xffff
#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_CAL_L_VAL_ADDR)
#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_CAL_L_VAL_ADDR, m)
#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_CAL_L_VAL_ADDR,v)
#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_CAL_L_VAL_ADDR,m,v,HWIO_AOSS_CC_PLL0_CAL_L_VAL_IN)
#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_PLL_CAL_L_BMSK                                            0xffff
#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_PLL_CAL_L_SHFT                                               0x0

#define HWIO_AOSS_CC_PLL0_USER_CTL_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000000c)
#define HWIO_AOSS_CC_PLL0_USER_CTL_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_AOSS_CC_PLL0_USER_CTL_RMSK                                                   0xffffffff
#define HWIO_AOSS_CC_PLL0_USER_CTL_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_USER_CTL_ADDR)
#define HWIO_AOSS_CC_PLL0_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_USER_CTL_ADDR, m)
#define HWIO_AOSS_CC_PLL0_USER_CTL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_USER_CTL_ADDR,v)
#define HWIO_AOSS_CC_PLL0_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_USER_CTL_ADDR,m,v,HWIO_AOSS_CC_PLL0_USER_CTL_IN)
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT31_BMSK                                     0x80000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT31_SHFT                                           0x1f
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT30_BMSK                                     0x40000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT30_SHFT                                           0x1e
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT29_BMSK                                     0x20000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT29_SHFT                                           0x1d
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT28_BMSK                                     0x10000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT28_SHFT                                           0x1c
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT27_BMSK                                      0x8000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT27_SHFT                                           0x1b
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT26_BMSK                                      0x4000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT26_SHFT                                           0x1a
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT25_BMSK                                      0x2000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT25_SHFT                                           0x19
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT24_BMSK                                      0x1000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT24_SHFT                                           0x18
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT23_BMSK                                       0x800000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT23_SHFT                                           0x17
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT22_BMSK                                       0x400000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT22_SHFT                                           0x16
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT21_BMSK                                       0x200000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT21_SHFT                                           0x15
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT20_BMSK                                       0x100000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT20_SHFT                                           0x14
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT19_BMSK                                        0x80000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT19_SHFT                                           0x13
#define HWIO_AOSS_CC_PLL0_USER_CTL_PRE_DIV_RATIO_BMSK                                        0x70000
#define HWIO_AOSS_CC_PLL0_USER_CTL_PRE_DIV_RATIO_SHFT                                           0x10
#define HWIO_AOSS_CC_PLL0_USER_CTL_PRE_DIV_RATIO_DIVIDE_BY_1_FVAL                                0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_PRE_DIV_RATIO_DIVIDE_BY_2_FVAL                                0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_PRE_DIV_RATIO_DIVIDE_BY_4_FVAL                                0x3
#define HWIO_AOSS_CC_PLL0_USER_CTL_POST_DIV_RATIO_ODD_BMSK                                    0xf000
#define HWIO_AOSS_CC_PLL0_USER_CTL_POST_DIV_RATIO_ODD_SHFT                                       0xc
#define HWIO_AOSS_CC_PLL0_USER_CTL_POST_DIV_RATIO_ODD_DIVIDE_BY_1_FVAL                           0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_POST_DIV_RATIO_ODD_DIVIDE_BY_3_FVAL                           0x3
#define HWIO_AOSS_CC_PLL0_USER_CTL_POST_DIV_RATIO_ODD_DIVIDE_BY_5_FVAL                           0x5
#define HWIO_AOSS_CC_PLL0_USER_CTL_POST_DIV_RATIO_ODD_DIVIDE_BY_7_FVAL                           0x7
#define HWIO_AOSS_CC_PLL0_USER_CTL_POST_DIV_RATIO_EVEN_BMSK                                    0xf00
#define HWIO_AOSS_CC_PLL0_USER_CTL_POST_DIV_RATIO_EVEN_SHFT                                      0x8
#define HWIO_AOSS_CC_PLL0_USER_CTL_POST_DIV_RATIO_EVEN_DIVIDE_BY_1_FVAL                          0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_POST_DIV_RATIO_EVEN_DIVIDE_BY_2_FVAL                          0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_POST_DIV_RATIO_EVEN_DIVIDE_BY_4_FVAL                          0x3
#define HWIO_AOSS_CC_PLL0_USER_CTL_POST_DIV_RATIO_EVEN_DIVIDE_BY_8_FVAL                          0x7
#define HWIO_AOSS_CC_PLL0_USER_CTL_OUT_CLK_POLARITY_BMSK                                        0x80
#define HWIO_AOSS_CC_PLL0_USER_CTL_OUT_CLK_POLARITY_SHFT                                         0x7
#define HWIO_AOSS_CC_PLL0_USER_CTL_OUT_CLK_POLARITY_DO_NOT_INVERT_OUTPUT_FVAL                    0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_OUT_CLK_POLARITY_INVERT_OUTPUT_FVAL                           0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT6_BMSK                                            0x40
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT6_SHFT                                             0x6
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT5_BMSK                                            0x20
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT5_SHFT                                             0x5
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_TEST_BMSK                                             0x10
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_TEST_SHFT                                              0x4
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_TEST_DISABLE_FVAL                                      0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_TEST_ENABLE_FVAL                                       0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT3_BMSK                                             0x8
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT3_SHFT                                             0x3
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_ODD_BMSK                                               0x4
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_ODD_SHFT                                               0x2
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_ODD_DISABLE_FVAL                                       0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_ODD_ENABLE_FVAL                                        0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_EVEN_BMSK                                              0x2
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_EVEN_SHFT                                              0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_EVEN_DISABLE_FVAL                                      0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_EVEN_ENABLE_FVAL                                       0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_MAIN_BMSK                                              0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_MAIN_SHFT                                              0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_MAIN_DISABLE_FVAL                                      0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_MAIN_ENABLE_FVAL                                       0x1

#define HWIO_AOSS_CC_PLL0_USER_CTL_U_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000010)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RMSK                                                 0xffffffff
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_USER_CTL_U_ADDR)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_USER_CTL_U_ADDR, m)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_USER_CTL_U_ADDR,v)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_USER_CTL_U_ADDR,m,v,HWIO_AOSS_CC_PLL0_USER_CTL_U_IN)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT63_BMSK                                   0x80000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT63_SHFT                                         0x1f
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT62_BMSK                                   0x40000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT62_SHFT                                         0x1e
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT61_BMSK                                   0x20000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT61_SHFT                                         0x1d
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT60_BMSK                                   0x10000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT60_SHFT                                         0x1c
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT59_BMSK                                    0x8000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT59_SHFT                                         0x1b
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT58_BMSK                                    0x4000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT58_SHFT                                         0x1a
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT57_BMSK                                    0x2000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT57_SHFT                                         0x19
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT56_BMSK                                    0x1000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT56_SHFT                                         0x18
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT55_BMSK                                     0x800000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT55_SHFT                                         0x17
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT54_BMSK                                     0x400000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT54_SHFT                                         0x16
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT53_BMSK                                     0x200000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT53_SHFT                                         0x15
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT52_BMSK                                     0x100000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT52_SHFT                                         0x14
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT51_BMSK                                      0x80000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT51_SHFT                                         0x13
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_LOCK_DETECTOR_SELECTION_BMSK                            0x40000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_LOCK_DETECTOR_SELECTION_SHFT                               0x12
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_LOCK_DETECTOR_SELECTION_LOCK_DETECT_FROM_FLL_FVAL           0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_LOCK_DETECTOR_SELECTION_LOCK_DETECT_FROM_PLL_FVAL           0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_TYPE_2_MODE_SELECTION_BMSK                              0x20000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_TYPE_2_MODE_SELECTION_SHFT                                 0x11
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_BANG_BANG_MODE_SELECTION_BMSK                           0x10000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_BANG_BANG_MODE_SELECTION_SHFT                              0x10
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_FRAC_FORMAT_SEL_BMSK                                     0x8000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_FRAC_FORMAT_SEL_SHFT                                        0xf
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_FRAC_FORMAT_SEL_POWER_OF_TWO_BASED_FRACTIONAL_MULTIPLIER_FVAL        0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_FRAC_FORMAT_SEL_M_OVER_N_BASED_FRACTIONAL_MULTIPLIER_FVAL        0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT46_BMSK                                       0x4000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT46_SHFT                                          0xe
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_REF_CLK_AT_OUT_BMSK                                      0x2000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_REF_CLK_AT_OUT_SHFT                                         0xd
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_REF_CLK_AT_OUT_OUTPUT_IS_THE_REFERENCE_CLOCK_WHEN_NOT_LOCKED_FVAL        0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_REF_CLK_AT_OUT_OUTPUT_IS_ALWAYS_THE_CLOCK_GENERATED_BY_PLL_FVAL        0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_SCALE_FREQ_ON_RESTART_BMSK                               0x1800
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_SCALE_FREQ_ON_RESTART_SHFT                                  0xb
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_SCALE_FREQ_ON_RESTART_NO_SCALING_FVAL                       0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_SCALE_FREQ_ON_RESTART_SCALE_FREQUENCY_DOWNWARD_BY_6_PERCENT_FVAL        0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_SCALE_FREQ_ON_RESTART_SCALE_FREQUENCY_DOWNWARD_BY_12_PERCENT_FVAL        0x2
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_SCALE_FREQ_ON_RESTART_SCALE_FREQUENCY_DOWNWARD_BY_25_PERCENT_FVAL        0x3
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_LATCH_INTERFACE_BYPASS_BMSK                               0x400
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_LATCH_INTERFACE_BYPASS_SHFT                                 0xa
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_LATCH_INTERFACE_BYPASS_DO_NOT_BYPASS_FVAL                   0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_LATCH_INTERFACE_BYPASS_BYPASS_FVAL                          0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_STATUS_REGISTER_BMSK                                      0x3e0
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_STATUS_REGISTER_SHFT                                        0x5
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_WRITE_STATE_EN_BMSK                                        0x10
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_WRITE_STATE_EN_SHFT                                         0x4
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_WRITE_STATE_EN_DISABLE_FVAL                                 0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_WRITE_STATE_EN_ENABLE_FVAL                                  0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_CALIB_CTRL_BMSK                                             0xe
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_CALIB_CTRL_SHFT                                             0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_CALIB_CTRL_ALWAYS_PERFORM_CALIBRATION_FVAL                  0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_CALIB_CTRL_NEVER_PERFORM_CALIBRATION_FVAL                   0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_CALIB_CTRL_AUTOMATIC_FVAL                                   0x2
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_BMSK                                 0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_SHFT                                 0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_USE_BOTH_FINE_AND_COARSE_LOCK_DETECTORS_FVAL        0x0
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_USE_ONLY_THE_FINE_LOCK_DETECTOR_FVAL        0x1

#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000014)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_OFFS                                                (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000014)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RMSK                                                0xffffffff
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_USER_CTL_U1_ADDR)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_USER_CTL_U1_ADDR, m)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_USER_CTL_U1_ADDR,v)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_USER_CTL_U1_ADDR,m,v,HWIO_AOSS_CC_PLL0_USER_CTL_U1_IN)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT95_BMSK                                  0x80000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT95_SHFT                                        0x1f
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT94_BMSK                                  0x40000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT94_SHFT                                        0x1e
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT93_BMSK                                  0x20000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT93_SHFT                                        0x1d
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT92_BMSK                                  0x10000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT92_SHFT                                        0x1c
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT91_BMSK                                   0x8000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT91_SHFT                                        0x1b
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT90_BMSK                                   0x4000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT90_SHFT                                        0x1a
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT89_BMSK                                   0x2000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT89_SHFT                                        0x19
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT88_BMSK                                   0x1000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT88_SHFT                                        0x18
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT87_BMSK                                    0x800000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT87_SHFT                                        0x17
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT86_BMSK                                    0x400000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT86_SHFT                                        0x16
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT85_BMSK                                    0x200000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT85_SHFT                                        0x15
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT84_BMSK                                    0x100000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT84_SHFT                                        0x14
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT83_BMSK                                     0x80000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT83_SHFT                                        0x13
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT82_BMSK                                     0x40000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT82_SHFT                                        0x12
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT81_BMSK                                     0x20000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT81_SHFT                                        0x11
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT80_BMSK                                     0x10000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT80_SHFT                                        0x10
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT79_BMSK                                      0x8000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT79_SHFT                                         0xf
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT78_BMSK                                      0x4000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT78_SHFT                                         0xe
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT77_BMSK                                      0x2000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT77_SHFT                                         0xd
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT76_BMSK                                      0x1000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT76_SHFT                                         0xc
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT75_BMSK                                       0x800
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT75_SHFT                                         0xb
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT74_BMSK                                       0x400
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT74_SHFT                                         0xa
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT73_BMSK                                       0x200
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT73_SHFT                                         0x9
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT72_BMSK                                       0x100
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT72_SHFT                                         0x8
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT71_BMSK                                        0x80
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT71_SHFT                                         0x7
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT70_BMSK                                        0x40
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT70_SHFT                                         0x6
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT69_BMSK                                        0x20
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT69_SHFT                                         0x5
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT68_BMSK                                        0x10
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT68_SHFT                                         0x4
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT67_BMSK                                         0x8
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT67_SHFT                                         0x3
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT66_BMSK                                         0x4
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT66_SHFT                                         0x2
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT65_BMSK                                         0x2
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT65_SHFT                                         0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT64_BMSK                                         0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT64_SHFT                                         0x0

#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000018)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000018)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_RMSK                                                 0xffffffff
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_CONFIG_CTL_ADDR)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_CONFIG_CTL_ADDR, m)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_CONFIG_CTL_ADDR,v)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_CONFIG_CTL_ADDR,m,v,HWIO_AOSS_CC_PLL0_CONFIG_CTL_IN)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FINE_LDC_THRESHOLD_BMSK                              0xfc000000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FINE_LDC_THRESHOLD_SHFT                                    0x1a
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_COARSE_LDC_THRESHOLD_BMSK                             0x3c00000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_COARSE_LDC_THRESHOLD_SHFT                                  0x16
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_BMSK                     0x3c0000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_SHFT                         0x12
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_BMSK                      0x3c000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_SHFT                          0xe
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_BMSK                             0x3800
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_SHFT                                0xb
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_BMSK                            0x700
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_SHFT                              0x8
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_BMSK                                  0xf0
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_SHFT                                   0x4
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FWD_GAIN_KFN_BMSK                                           0xf
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FWD_GAIN_KFN_SHFT                                           0x0

#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_ADDR                                               (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000001c)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_OFFS                                               (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_RMSK                                               0xffffffff
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_ADDR)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_ADDR, m)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_ADDR,v)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_ADDR,m,v,HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_IN)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_BIST_CFG_BMSK                                      0xffff0000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_BIST_CFG_SHFT                                            0x10
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_BMSK                           0xc000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_SHFT                              0xe
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_COARSE_LOCK_DETECT_FVAL           0x0
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_FINE_LOCK_DETECT_FVAL             0x1
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_PLL_LOCK_DETECT_INT_FVAL          0x2
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_RESERVED_FVAL                     0x3
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_OSC_SETTLING_TIME_BMSK                                 0x3000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_OSC_SETTLING_TIME_SHFT                                    0xc
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_OSC_SETTLING_TIME_COUNT_0_IE_DO_NOT_WAIT_FVAL             0x0
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_OSC_SETTLING_TIME_COUNT_10_REFERENCE_CYCLES_FVAL          0x1
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_OSC_SETTLING_TIME_COUNT_25_REFERENCE_CYCLES_FVAL          0x2
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_OSC_SETTLING_TIME_COUNT_50_REFERENCE_CYCLES_FVAL          0x3
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_BMSK                                0xc00
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_SHFT                                  0xa
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_USE_12_STEPS_FVAL                     0x0
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_USE_10_STEPS_FVAL                     0x1
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_USE_8_STEPS_FVAL                      0x2
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_USE_6_STEPS_FVAL                      0x3
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_CASC_CURRENT_CTL_B_BMSK                                 0x380
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_CASC_CURRENT_CTL_B_SHFT                                   0x7
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_BMSK                         0x40
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_SHFT                          0x6
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_MINIMUM_GLITCH_THRESHOLD_IS_NOT_INCREASED_FVAL        0x0
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_MINIMUM_GLITCH_THRESHOLD_IS_INCREASED_BY_4X_FVAL        0x1
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_BMSK                                0x30
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_SHFT                                 0x4
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_MINIMUM_OF_4_FVAL                    0x0
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_MINIMUM_OF_16_FVAL                   0x1
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_MINIMUM_OF_128_FVAL                  0x2
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_MINIMUM_OF_256_FVAL                  0x3
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_LDET_THRESH_SCALE_BMSK                                    0x8
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_LDET_THRESH_SCALE_SHFT                                    0x3
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_DCO_STARTUP_CONFIG_BMSK                                   0x6
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_DCO_STARTUP_CONFIG_SHFT                                   0x1
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_BMSK                              0x1
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_SHFT                              0x0
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_DISABLE_FVAL                      0x0
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_ENABLE_FVAL                       0x1

#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_ADDR                                              (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000020)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_OFFS                                              (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_RMSK                                              0xffffffff
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_ADDR)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_ADDR, m)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_ADDR,v)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_ADDR,m,v,HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_IN)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_THRESHOLD_BMSK                             0xc0000000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_THRESHOLD_SHFT                                   0x1e
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_PCODE_OFFSET_BMSK                                 0x38000000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_PCODE_OFFSET_SHFT                                       0x1b
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_COUNTER_BLANK_BMSK                                 0x4000000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_COUNTER_BLANK_SHFT                                      0x1a
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_RESYNC_EDGE_BMSK                                0x2000000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_RESYNC_EDGE_SHFT                                     0x19
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_RESYNC_SEL_BMSK                                 0x1000000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_RESYNC_SEL_SHFT                                      0x18
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_BMSK                            0xc00000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_SHFT                                0x16
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_LOCK_THRESH_BMSK                                 0x380000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_LOCK_THRESH_SHFT                                     0x13
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_RESERVE_BIT82_BMSK                                   0x40000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_RESERVE_BIT82_SHFT                                      0x12
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_BMSK                              0x30000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_SHFT                                 0x10
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_BMSK                                0xc000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_SHFT                                   0xe
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_EN_BMSK                                        0x2000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_EN_SHFT                                           0xd
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_EN_CALIBRATION_DISABLE_FVAL                       0x0
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_EN_CALIBRATION_ENABLE_FVAL                        0x1
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_BMSK                          0x1800
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_SHFT                             0xb
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BBMODE_INT_GAIN_BMSK                                   0x780
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BBMODE_INT_GAIN_SHFT                                     0x7
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BBMODE_PROP_GAIN_BMSK                                   0x78
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BBMODE_PROP_GAIN_SHFT                                    0x3
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_TDC_SELECTION_BMSK                                       0x4
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_TDC_SELECTION_SHFT                                       0x2
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_RESERVE_BIT65_BMSK                                       0x2
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_RESERVE_BIT65_SHFT                                       0x1
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_FORCE_DSM_ON_BMSK                                        0x1
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_FORCE_DSM_ON_SHFT                                        0x0
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_FORCE_DSM_ON_NOT_FORCED_ENABLED_FVAL                     0x0
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_FORCE_DSM_ON_FORCED_ENABLED_FVAL                         0x1

#define HWIO_AOSS_CC_PLL0_TEST_CTL_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000024)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000024)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_RMSK                                                   0xffffffff
#define HWIO_AOSS_CC_PLL0_TEST_CTL_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_TEST_CTL_ADDR)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_TEST_CTL_ADDR, m)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_TEST_CTL_ADDR,v)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_TEST_CTL_ADDR,m,v,HWIO_AOSS_CC_PLL0_TEST_CTL_IN)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_BMSK                           0xc0000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_SHFT                                 0x1e
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_ADD_0_CYCLES_FVAL                     0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_ADD_1_CYCLES_FVAL                     0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_ADD_2_CYCLES_FVAL                     0x2
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_ADD_4_CYCLES_FVAL                     0x3
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_FIRST_ORDER_DSM_BMSK                            0x20000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_FIRST_ORDER_DSM_SHFT                                  0x1d
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_FIRST_ORDER_DSM_DO_NOT_BYPASS_FVAL                     0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_FIRST_ORDER_DSM_BYPASS_FVAL                            0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_BMSK                       0x18000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_SHFT                             0x1b
#define HWIO_AOSS_CC_PLL0_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_LIMIT_OF_4_FVAL                   0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_LIMIT_OF_16_FVAL                  0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_LIMIT_OF_32_FVAL                  0x2
#define HWIO_AOSS_CC_PLL0_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_LIMIT_OF_128_FVAL                 0x3
#define HWIO_AOSS_CC_PLL0_TEST_CTL_GLITCH_PREVENTION_DIS_BMSK                              0x4000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_GLITCH_PREVENTION_DIS_SHFT                                   0x1a
#define HWIO_AOSS_CC_PLL0_TEST_CTL_GLITCH_PREVENTION_DIS_GLITCH_DETECTOR_IS_ON_FVAL              0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_GLITCH_PREVENTION_DIS_GLITCH_DETECTOR_IS_OFF_FVAL             0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ATEST_ISCALE_BMSK                                       0x3000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ATEST_ISCALE_SHFT                                            0x18
#define HWIO_AOSS_CC_PLL0_TEST_CTL_PLL_TEST_OUT_SEL_BMSK                                    0xf00000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_PLL_TEST_OUT_SEL_SHFT                                        0x14
#define HWIO_AOSS_CC_PLL0_TEST_CTL_PLL_TEST_OUT_SEL_RESET_N_FVAL                                 0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_PLL_TEST_OUT_SEL_DCO_CLOCK_BEFORE_POST_DIVISION_FVAL          0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_PLL_TEST_OUT_SEL_PLLOUT_EVEN_FVAL                             0x2
#define HWIO_AOSS_CC_PLL0_TEST_CTL_PLL_TEST_OUT_SEL_PLLOUT_ODD_FVAL                              0x3
#define HWIO_AOSS_CC_PLL0_TEST_CTL_PLL_TEST_OUT_SEL_NMO_OUTPUT_FVAL                              0x4
#define HWIO_AOSS_CC_PLL0_TEST_CTL_PLL_TEST_OUT_SEL_DIVIDER_OUTPUT_FVAL                          0x5
#define HWIO_AOSS_CC_PLL0_TEST_CTL_PLL_TEST_OUT_SEL_TBD_FVAL                                     0x6
#define HWIO_AOSS_CC_PLL0_TEST_CTL_PLL_TEST_OUT_SEL_REFERENCE_CLOCK_FVAL                         0x7
#define HWIO_AOSS_CC_PLL0_TEST_CTL_RESERVE_BIT19_BMSK                                        0x80000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_RESERVE_BIT19_SHFT                                           0x13
#define HWIO_AOSS_CC_PLL0_TEST_CTL_DIV2_NMO_EN_BMSK                                          0x40000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_DIV2_NMO_EN_SHFT                                             0x12
#define HWIO_AOSS_CC_PLL0_TEST_CTL_DIV2_NMO_EN_DISABLE_FVAL                                      0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_DIV2_NMO_EN_ENABLE_FVAL                                       0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NMO_OSC_SEL_BMSK                                          0x30000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NMO_OSC_SEL_SHFT                                             0x10
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NMO_OSC_SEL_OFF_FVAL                                          0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NMO_OSC_SEL_FREQ_OF_1200MHZ_FVAL                              0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NMO_OSC_SEL_FREQ_OF_900MHZ_FVAL                               0x2
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NMO_OSC_SEL_FREQ_OF_600MHZ_FVAL                               0x3
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NOISE_MAG_BMSK                                             0xe000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NOISE_MAG_SHFT                                                0xd
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NOISE_MAG_OFF_FVAL                                            0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NOISE_MAG_NOISE_OF_34MVRMS_FVAL                               0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NOISE_MAG_NOISE_OF_61MVRMS_FVAL                               0x3
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NOISE_MAG_NOISE_OF_72MVRMS_FVAL                               0x7
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NOISE_GEN_EN_BMSK                                          0x1000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NOISE_GEN_EN_SHFT                                             0xc
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NOISE_GEN_EN_DISABLE_FVAL                                     0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NOISE_GEN_EN_ENABLE_FVAL                                      0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_DISABLE_DCAPS_BMSK                                          0x800
#define HWIO_AOSS_CC_PLL0_TEST_CTL_DISABLE_DCAPS_SHFT                                            0xb
#define HWIO_AOSS_CC_PLL0_TEST_CTL_RESERVE_BIT10_BMSK                                          0x400
#define HWIO_AOSS_CC_PLL0_TEST_CTL_RESERVE_BIT10_SHFT                                            0xa
#define HWIO_AOSS_CC_PLL0_TEST_CTL_RESERVE_BIT9_BMSK                                           0x200
#define HWIO_AOSS_CC_PLL0_TEST_CTL_RESERVE_BIT9_SHFT                                             0x9
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_BMSK                                0x100
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_SHFT                                  0x8
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_DO_NOT_BYPASS_FVAL                    0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_BYPASS_ENABLED_FVAL                   0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VDD_TEST_BMSK                                             0x80
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VDD_TEST_SHFT                                              0x7
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VDD_TEST_DISABLE_FVAL                                      0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VDD_TEST_ENABLE_FVAL                                       0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VREG_TEST_BMSK                                            0x40
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VREG_TEST_SHFT                                             0x6
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VREG_TEST_DISABLE_FVAL                                     0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VREG_TEST_ENABLE_FVAL                                      0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VREF_TEST_BMSK                                            0x20
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VREF_TEST_SHFT                                             0x5
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VREF_TEST_DISABLE_FVAL                                     0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VREF_TEST_ENABLE_FVAL                                      0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VDCO_TEST_BMSK                                            0x10
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VDCO_TEST_SHFT                                             0x4
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VDCO_TEST_DISABLE_FVAL                                     0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VDCO_TEST_ENABLE_FVAL                                      0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_ATEST_BUFFER_BMSK                                      0x8
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_ATEST_BUFFER_SHFT                                      0x3
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_ATEST_BUFFER_ATEST_BUFFER_ENABLED_FVAL                 0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_ATEST_BUFFER_ATEST_BUFFER_DISABLED_FVAL                0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_IVCO_TEST_BMSK                                             0x4
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_IVCO_TEST_SHFT                                             0x2
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_IVCO_TEST_DISABLE_FVAL                                     0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_IVCO_TEST_ENABLE_FVAL                                      0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ATEST1_EN_BMSK                                                0x2
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ATEST1_EN_SHFT                                                0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ATEST1_EN_DISABLE_FVAL                                        0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ATEST1_EN_ENABLE_FVAL                                         0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ATEST0_EN_BMSK                                                0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ATEST0_EN_SHFT                                                0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ATEST0_EN_DISABLE_FVAL                                        0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ATEST0_EN_ENABLE_FVAL                                         0x1

#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000028)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000028)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_RMSK                                                 0xffffffff
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_TEST_CTL_U_ADDR)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_TEST_CTL_U_ADDR, m)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_TEST_CTL_U_ADDR,v)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_TEST_CTL_U_ADDR,m,v,HWIO_AOSS_CC_PLL0_TEST_CTL_U_IN)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_CASC_DAC_FCW_LSBS_BMSK                               0xe0000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_CASC_DAC_FCW_LSBS_SHFT                                     0x1d
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_CASC_DAC_BMSK                               0x10000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_CASC_DAC_SHFT                                     0x1c
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_CASC_DAC_DO_NOT_OVERRIDE_FVAL                      0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_CASC_DAC_OVERRIDE_FVAL                             0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_COMP_COARSE_FCW_BMSK                                  0xe000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_COMP_COARSE_FCW_SHFT                                       0x19
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_BMSK                         0x1800000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_SHFT                              0x17
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_DO_NOT_OVERRIDE_FVAL               0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_OVERRIDE_THE_INPUT_TO_THE_DAC_FVAL        0x2
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_OVERRIDE_THE_INTERNAL_COMPENSATION_CODE_FVAL        0x3
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_FINE_FCW_BMSK                                          0x7e0000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_FINE_FCW_SHFT                                              0x11
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_FINE_FCW_BMSK                                  0x10000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_FINE_FCW_SHFT                                     0x10
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_FINE_FCW_DO_NOT_OVERRIDE_FVAL                      0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_FINE_FCW_OVERRIDE_FVAL                             0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_REG_COARSE_FCW_BMSK                                      0xfe00
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_REG_COARSE_FCW_SHFT                                         0x9
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_BMSK                              0x100
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_SHFT                                0x8
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_DO_NOT_OVERRIDE_FVAL                0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_OVERRIDE_FVAL                       0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_PROCESS_CALIB_WORD_BMSK                                    0xe0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_PROCESS_CALIB_WORD_SHFT                                     0x5
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_CALIB_WORD_BMSK                                   0x10
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_CALIB_WORD_SHFT                                    0x4
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_CALIB_WORD_DO_NOT_OVERRIDE_FVAL                    0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_CALIB_WORD_OVERRIDE_FVAL                           0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_BMSK                                 0x8
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_SHFT                                 0x3
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_ENABLE_FVAL                          0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_DISABLE_FVAL                         0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_DISABLE_LFSR_BMSK                                           0x4
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_DISABLE_LFSR_SHFT                                           0x2
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_DISABLE_LFSR_ENABLE_FVAL                                    0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_DISABLE_LFSR_DISABLE_FVAL                                   0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_SKIP_FINE_TUNE_BMSK                                         0x2
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_SKIP_FINE_TUNE_SHFT                                         0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_SKIP_FINE_TUNE_PERFORM_FINE_TUNING_FVAL                     0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_SKIP_FINE_TUNE_SKIP_FINE_TUNING_FVAL                        0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_SKIP_FAST_LOCK_BMSK                                         0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_SKIP_FAST_LOCK_SHFT                                         0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_SKIP_FAST_LOCK_USE_FAST_LOCKING_FVAL                        0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_SKIP_FAST_LOCK_USE_LINEAR_LOCKING_FVAL                      0x1

#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000002c)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_OFFS                                                (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000002c)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RMSK                                                0xffffffff
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_TEST_CTL_U1_ADDR)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_TEST_CTL_U1_ADDR, m)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_TEST_CTL_U1_ADDR,v)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_TEST_CTL_U1_ADDR,m,v,HWIO_AOSS_CC_PLL0_TEST_CTL_U1_IN)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT95_BMSK                                  0x80000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT95_SHFT                                        0x1f
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT94_BMSK                                  0x40000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT94_SHFT                                        0x1e
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_FLL_COUNT_DISABLE_BMSK                              0x20000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_FLL_COUNT_DISABLE_SHFT                                    0x1d
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_FLL_COUNT_DISABLE_ENABLE_FVAL                              0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_FLL_COUNT_DISABLE_DISABLE_FVAL                             0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_FLL_COUNT_IN_DIV2_BMSK                              0x10000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_FLL_COUNT_IN_DIV2_SHFT                                    0x1c
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_FLL_COUNT_IN_DIV2_DISABLE_FVAL                             0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_FLL_COUNT_IN_DIV2_ENABLE_FVAL                              0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT91_BMSK                                   0x8000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT91_SHFT                                        0x1b
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT90_BMSK                                   0x4000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT90_SHFT                                        0x1a
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT89_BMSK                                   0x2000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT89_SHFT                                        0x19
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT88_BMSK                                   0x1000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT88_SHFT                                        0x18
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT87_BMSK                                    0x800000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT87_SHFT                                        0x17
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_SILENCE_REF_OUTBUF_BMSK                               0x400000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_SILENCE_REF_OUTBUF_SHFT                                   0x16
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_SILENCE_REF_OUTBUF_DONT_TIE_LOW_FVAL                       0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_SILENCE_REF_OUTBUF_TIE_LOW_FVAL                            0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT85_BMSK                                    0x200000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT85_SHFT                                        0x15
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT84_BMSK                                    0x100000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT84_SHFT                                        0x14
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT83_BMSK                                     0x80000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT83_SHFT                                        0x13
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_BMSK                             0x40000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_SHFT                                0x12
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_ENABLE_FVAL                          0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_DISABLE_FVAL                         0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_REF_CLK_SEL_BMSK                                       0x20000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_REF_CLK_SEL_SHFT                                          0x11
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_REF_CLK_SEL_SELECT_CLK_REF_FVAL                            0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_REF_CLK_SEL_SELECT_CLK_AUX_FVAL                            0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_BMSK                         0x10000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_SHFT                            0x10
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_ENABLE_FVAL                      0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_DISABLE_FVAL                     0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DIS_AMP_STARTUP_BMSK                                    0x8000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DIS_AMP_STARTUP_SHFT                                       0xf
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DIS_AMP_STARTUP_ENABLE_FVAL                                0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DIS_AMP_STARTUP_DISABLE_FVAL                               0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_CLAMP_BMSK                                      0x4000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_CLAMP_SHFT                                         0xe
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_CLAMP_ENABLE_FVAL                                  0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_CLAMP_DISABLE_FVAL                                 0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_BMSK                            0x2000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_SHFT                               0xd
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_ENABLE_FVAL                        0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_DISABLE_FVAL                       0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT76_BMSK                                      0x1000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT76_SHFT                                         0xc
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT75_BMSK                                       0x800
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT75_SHFT                                         0xb
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT74_BMSK                                       0x400
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT74_SHFT                                         0xa
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT73_BMSK                                       0x200
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT73_SHFT                                         0x9
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT72_BMSK                                       0x100
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT72_SHFT                                         0x8
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_BMSK                              0x80
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_SHFT                               0x7
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_AFTER_SPLIT_INTO_REGULAR_AND_COMPENSATION_FVAL        0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_BEFORE_THE_SPLIT_FVAL              0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_ENABLE_TRAINING_SEQ_BMSK                                  0x40
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_ENABLE_TRAINING_SEQ_SHFT                                   0x6
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_ENABLE_TRAINING_SEQ_NO_TRAINING_SEQUENCE_FVAL              0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_ENABLE_TRAINING_SEQ_ENABLE_TRAINING_SEQUENCE_FVAL          0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_STATUS_REG_EN_BMSK                                        0x20
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_STATUS_REG_EN_SHFT                                         0x5
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_STATUS_REG_EN_DISABLE_FVAL                                 0x0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_STATUS_REG_EN_ENABLE_FVAL                                  0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT68_BMSK                                        0x10
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT68_SHFT                                         0x4
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT67_BMSK                                         0x8
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT67_SHFT                                         0x3
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT66_BMSK                                         0x4
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT66_SHFT                                         0x2
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_CASC_DAC_FCW_MSBS_BMSK                                     0x3
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_CASC_DAC_FCW_MSBS_SHFT                                     0x0

#define HWIO_AOSS_CC_PLL0_STATUS_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000030)
#define HWIO_AOSS_CC_PLL0_STATUS_OFFS                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_AOSS_CC_PLL0_STATUS_RMSK                                                     0xffffffff
#define HWIO_AOSS_CC_PLL0_STATUS_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_STATUS_ADDR)
#define HWIO_AOSS_CC_PLL0_STATUS_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_STATUS_ADDR, m)
#define HWIO_AOSS_CC_PLL0_STATUS_STATUS_31_0_BMSK                                         0xffffffff
#define HWIO_AOSS_CC_PLL0_STATUS_STATUS_31_0_SHFT                                                0x0

#define HWIO_AOSS_CC_PLL0_FREQ_CTL_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000034)
#define HWIO_AOSS_CC_PLL0_FREQ_CTL_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_AOSS_CC_PLL0_FREQ_CTL_RMSK                                                   0xffffffff
#define HWIO_AOSS_CC_PLL0_FREQ_CTL_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_FREQ_CTL_ADDR)
#define HWIO_AOSS_CC_PLL0_FREQ_CTL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_FREQ_CTL_ADDR, m)
#define HWIO_AOSS_CC_PLL0_FREQ_CTL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_FREQ_CTL_ADDR,v)
#define HWIO_AOSS_CC_PLL0_FREQ_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_FREQ_CTL_ADDR,m,v,HWIO_AOSS_CC_PLL0_FREQ_CTL_IN)
#define HWIO_AOSS_CC_PLL0_FREQ_CTL_FREQUENCY_CTL_WORD_BMSK                                0xffffffff
#define HWIO_AOSS_CC_PLL0_FREQ_CTL_FREQUENCY_CTL_WORD_SHFT                                       0x0

#define HWIO_AOSS_CC_PLL0_OPMODE_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000038)
#define HWIO_AOSS_CC_PLL0_OPMODE_OFFS                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_AOSS_CC_PLL0_OPMODE_RMSK                                                            0x7
#define HWIO_AOSS_CC_PLL0_OPMODE_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_OPMODE_ADDR)
#define HWIO_AOSS_CC_PLL0_OPMODE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_OPMODE_ADDR, m)
#define HWIO_AOSS_CC_PLL0_OPMODE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_OPMODE_ADDR,v)
#define HWIO_AOSS_CC_PLL0_OPMODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_OPMODE_ADDR,m,v,HWIO_AOSS_CC_PLL0_OPMODE_IN)
#define HWIO_AOSS_CC_PLL0_OPMODE_PLL_OPMODE_BMSK                                                 0x7
#define HWIO_AOSS_CC_PLL0_OPMODE_PLL_OPMODE_SHFT                                                 0x0
#define HWIO_AOSS_CC_PLL0_OPMODE_PLL_OPMODE_STANDBY_FVAL                                         0x0
#define HWIO_AOSS_CC_PLL0_OPMODE_PLL_OPMODE_RUN_FVAL                                             0x1
#define HWIO_AOSS_CC_PLL0_OPMODE_PLL_OPMODE_NA_FVAL                                              0x2
#define HWIO_AOSS_CC_PLL0_OPMODE_PLL_OPMODE_FREEZE_FVAL                                          0x3
#define HWIO_AOSS_CC_PLL0_OPMODE_PLL_OPMODE_REALIGN_FVAL                                         0x5

#define HWIO_AOSS_CC_PLL0_STATE_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000003c)
#define HWIO_AOSS_CC_PLL0_STATE_OFFS                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_AOSS_CC_PLL0_STATE_RMSK                                                             0x7
#define HWIO_AOSS_CC_PLL0_STATE_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_STATE_ADDR)
#define HWIO_AOSS_CC_PLL0_STATE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_STATE_ADDR, m)
#define HWIO_AOSS_CC_PLL0_STATE_PLL_STATE_BMSK                                                   0x7
#define HWIO_AOSS_CC_PLL0_STATE_PLL_STATE_SHFT                                                   0x0

#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000040)
#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_OFFS                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_RMSK                                                      0xffff
#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_ALPHA_VAL_ADDR)
#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_ALPHA_VAL_ADDR, m)
#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_ALPHA_VAL_ADDR,v)
#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_ALPHA_VAL_ADDR,m,v,HWIO_AOSS_CC_PLL0_ALPHA_VAL_IN)
#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_PLL_ALPHA_VAL_BMSK                                        0xffff
#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_PLL_ALPHA_VAL_SHFT                                           0x0

#define HWIO_AOSS_CC_PLL0_SPARE_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000044)
#define HWIO_AOSS_CC_PLL0_SPARE_OFFS                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_AOSS_CC_PLL0_SPARE_RMSK                                                            0xff
#define HWIO_AOSS_CC_PLL0_SPARE_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_SPARE_ADDR)
#define HWIO_AOSS_CC_PLL0_SPARE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_SPARE_ADDR, m)
#define HWIO_AOSS_CC_PLL0_SPARE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_SPARE_ADDR,v)
#define HWIO_AOSS_CC_PLL0_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_SPARE_ADDR,m,v,HWIO_AOSS_CC_PLL0_SPARE_IN)
#define HWIO_AOSS_CC_PLL0_SPARE_SPARE_OUTPUTS_BMSK                                              0xf0
#define HWIO_AOSS_CC_PLL0_SPARE_SPARE_OUTPUTS_SHFT                                               0x4
#define HWIO_AOSS_CC_PLL0_SPARE_SPARE_INPUTS_BMSK                                                0xf
#define HWIO_AOSS_CC_PLL0_SPARE_SPARE_INPUTS_SHFT                                                0x0

#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_ADDR                                            (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000048)
#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_OFFS                                            (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_RMSK                                                  0xff
#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_ADDR)
#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_ADDR, m)
#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_ADDR,v)
#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_ADDR,m,v,HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_IN)
#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_BMSK                                  0xff
#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_SHFT                                   0x0

#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_ADDR                                              (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000004c)
#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_OFFS                                              (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_RMSK                                                     0xf
#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_ADDR)
#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_ADDR, m)
#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_ADDR,v)
#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_ADDR,m,v,HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_IN)
#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_SSC_NUM_STEPS_BMSK                                       0xf
#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_SSC_NUM_STEPS_SHFT                                       0x0

#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_ADDR                                            (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000050)
#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_OFFS                                            (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_RMSK                                                   0xf
#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_ADDR)
#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_ADDR, m)
#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_ADDR,v)
#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_ADDR,m,v,HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_IN)
#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_SSC_UPDATE_RATE_BMSK                                   0xf
#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_SSC_UPDATE_RATE_SHFT                                   0x0

#define HWIO_AOSS_CC_PLL1_MODE_ADDR                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001000)
#define HWIO_AOSS_CC_PLL1_MODE_OFFS                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00001000)
#define HWIO_AOSS_CC_PLL1_MODE_RMSK                                                       0xffffffff
#define HWIO_AOSS_CC_PLL1_MODE_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_MODE_ADDR)
#define HWIO_AOSS_CC_PLL1_MODE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_MODE_ADDR, m)
#define HWIO_AOSS_CC_PLL1_MODE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_MODE_ADDR,v)
#define HWIO_AOSS_CC_PLL1_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_MODE_ADDR,m,v,HWIO_AOSS_CC_PLL1_MODE_IN)
#define HWIO_AOSS_CC_PLL1_MODE_PLL_LOCK_DET_BMSK                                          0x80000000
#define HWIO_AOSS_CC_PLL1_MODE_PLL_LOCK_DET_SHFT                                                0x1f
#define HWIO_AOSS_CC_PLL1_MODE_PLL_ACTIVE_FLAG_BMSK                                       0x40000000
#define HWIO_AOSS_CC_PLL1_MODE_PLL_ACTIVE_FLAG_SHFT                                             0x1e
#define HWIO_AOSS_CC_PLL1_MODE_RESERVE_BITS29_22_BMSK                                     0x3fc00000
#define HWIO_AOSS_CC_PLL1_MODE_RESERVE_BITS29_22_SHFT                                           0x16
#define HWIO_AOSS_CC_PLL1_MODE_PLL_VOTE_FSM_RESET_BMSK                                      0x200000
#define HWIO_AOSS_CC_PLL1_MODE_PLL_VOTE_FSM_RESET_SHFT                                          0x15
#define HWIO_AOSS_CC_PLL1_MODE_PLL_VOTE_FSM_RESET_NO_RESET_FVAL                                  0x0
#define HWIO_AOSS_CC_PLL1_MODE_PLL_VOTE_FSM_RESET_RESET_FVAL                                     0x1
#define HWIO_AOSS_CC_PLL1_MODE_PLL_VOTE_FSM_ENA_BMSK                                        0x100000
#define HWIO_AOSS_CC_PLL1_MODE_PLL_VOTE_FSM_ENA_SHFT                                            0x14
#define HWIO_AOSS_CC_PLL1_MODE_PLL_VOTE_FSM_ENA_DISABLE_FVAL                                     0x0
#define HWIO_AOSS_CC_PLL1_MODE_PLL_VOTE_FSM_ENA_ENABLE_FVAL                                      0x1
#define HWIO_AOSS_CC_PLL1_MODE_PLL_BIAS_COUNT_BMSK                                           0xfc000
#define HWIO_AOSS_CC_PLL1_MODE_PLL_BIAS_COUNT_SHFT                                               0xe
#define HWIO_AOSS_CC_PLL1_MODE_PLL_LOCK_COUNT_BMSK                                            0x3f00
#define HWIO_AOSS_CC_PLL1_MODE_PLL_LOCK_COUNT_SHFT                                               0x8
#define HWIO_AOSS_CC_PLL1_MODE_RESERVE_BIT7_BMSK                                                0x80
#define HWIO_AOSS_CC_PLL1_MODE_RESERVE_BIT7_SHFT                                                 0x7
#define HWIO_AOSS_CC_PLL1_MODE_PLL_CLOCK_SELECT_BMSK                                            0x40
#define HWIO_AOSS_CC_PLL1_MODE_PLL_CLOCK_SELECT_SHFT                                             0x6
#define HWIO_AOSS_CC_PLL1_MODE_PLL_CLOCK_SELECT_ROUTE_CLK_XO_TO_THE_OUTPUT_FVAL                  0x0
#define HWIO_AOSS_CC_PLL1_MODE_PLL_CLOCK_SELECT_ROUTE_THE_INTERNALLY_GENERATED_CLOCK_TO_THE_OUTPUT_FVAL        0x1
#define HWIO_AOSS_CC_PLL1_MODE_PLL_REQUESTS_CAL_BMSK                                            0x20
#define HWIO_AOSS_CC_PLL1_MODE_PLL_REQUESTS_CAL_SHFT                                             0x5
#define HWIO_AOSS_CC_PLL1_MODE_PLL_CLK_XO_PRESENT_BMSK                                          0x10
#define HWIO_AOSS_CC_PLL1_MODE_PLL_CLK_XO_PRESENT_SHFT                                           0x4
#define HWIO_AOSS_CC_PLL1_MODE_PLL_IN_CALIBRATION_BMSK                                           0x8
#define HWIO_AOSS_CC_PLL1_MODE_PLL_IN_CALIBRATION_SHFT                                           0x3
#define HWIO_AOSS_CC_PLL1_MODE_PLL_RESET_N_BMSK                                                  0x4
#define HWIO_AOSS_CC_PLL1_MODE_PLL_RESET_N_SHFT                                                  0x2
#define HWIO_AOSS_CC_PLL1_MODE_PLL_RESET_N_RESET_FVAL                                            0x0
#define HWIO_AOSS_CC_PLL1_MODE_PLL_RESET_N_NO_RESET_FVAL                                         0x1
#define HWIO_AOSS_CC_PLL1_MODE_RESERVE_BIT1_BMSK                                                 0x2
#define HWIO_AOSS_CC_PLL1_MODE_RESERVE_BIT1_SHFT                                                 0x1
#define HWIO_AOSS_CC_PLL1_MODE_PLL_OUTCTRL_BMSK                                                  0x1
#define HWIO_AOSS_CC_PLL1_MODE_PLL_OUTCTRL_SHFT                                                  0x0
#define HWIO_AOSS_CC_PLL1_MODE_PLL_OUTCTRL_DISABLE_FVAL                                          0x0
#define HWIO_AOSS_CC_PLL1_MODE_PLL_OUTCTRL_ENABLE_FVAL                                           0x1

#define HWIO_AOSS_CC_PLL1_L_VAL_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001004)
#define HWIO_AOSS_CC_PLL1_L_VAL_OFFS                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00001004)
#define HWIO_AOSS_CC_PLL1_L_VAL_RMSK                                                           0xfff
#define HWIO_AOSS_CC_PLL1_L_VAL_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_L_VAL_ADDR)
#define HWIO_AOSS_CC_PLL1_L_VAL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_L_VAL_ADDR, m)
#define HWIO_AOSS_CC_PLL1_L_VAL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_L_VAL_ADDR,v)
#define HWIO_AOSS_CC_PLL1_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_L_VAL_ADDR,m,v,HWIO_AOSS_CC_PLL1_L_VAL_IN)
#define HWIO_AOSS_CC_PLL1_L_VAL_PLL_L_BMSK                                                     0xfff
#define HWIO_AOSS_CC_PLL1_L_VAL_PLL_L_SHFT                                                       0x0

#define HWIO_AOSS_CC_PLL1_USER_CTL_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001008)
#define HWIO_AOSS_CC_PLL1_USER_CTL_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00001008)
#define HWIO_AOSS_CC_PLL1_USER_CTL_RMSK                                                   0xffffffff
#define HWIO_AOSS_CC_PLL1_USER_CTL_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_USER_CTL_ADDR)
#define HWIO_AOSS_CC_PLL1_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_USER_CTL_ADDR, m)
#define HWIO_AOSS_CC_PLL1_USER_CTL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_USER_CTL_ADDR,v)
#define HWIO_AOSS_CC_PLL1_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_USER_CTL_ADDR,m,v,HWIO_AOSS_CC_PLL1_USER_CTL_IN)
#define HWIO_AOSS_CC_PLL1_USER_CTL_RESERVE_BITS31_17_BMSK                                 0xfffe0000
#define HWIO_AOSS_CC_PLL1_USER_CTL_RESERVE_BITS31_17_SHFT                                       0x11
#define HWIO_AOSS_CC_PLL1_USER_CTL_POST_DIV_RATIO_EVEN_BMSK                                  0x10000
#define HWIO_AOSS_CC_PLL1_USER_CTL_POST_DIV_RATIO_EVEN_SHFT                                     0x10
#define HWIO_AOSS_CC_PLL1_USER_CTL_POST_DIV_RATIO_EVEN_DIVIDE_BY_1_FVAL                          0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_POST_DIV_RATIO_EVEN_DIVIDE_BY_2_FVAL                          0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_RESERVE_BITS15_12_BMSK                                     0xf000
#define HWIO_AOSS_CC_PLL1_USER_CTL_RESERVE_BITS15_12_SHFT                                        0xc
#define HWIO_AOSS_CC_PLL1_USER_CTL_POST_DIV_RATIO_BMSK                                         0xf00
#define HWIO_AOSS_CC_PLL1_USER_CTL_POST_DIV_RATIO_SHFT                                           0x8
#define HWIO_AOSS_CC_PLL1_USER_CTL_POST_DIV_RATIO_DIVIDE_BY_1_FVAL                               0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_POST_DIV_RATIO_DIVIDE_BY_2_FVAL                               0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_OUT_CLK_POLARITY_BMSK                                        0x80
#define HWIO_AOSS_CC_PLL1_USER_CTL_OUT_CLK_POLARITY_SHFT                                         0x7
#define HWIO_AOSS_CC_PLL1_USER_CTL_OUT_CLK_POLARITY_DO_NOT_INVERT_OUTPUT_FVAL                    0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_OUT_CLK_POLARITY_INVERT_OUTPUT_FVAL                           0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_RESERVE_BITS6_5_BMSK                                         0x60
#define HWIO_AOSS_CC_PLL1_USER_CTL_RESERVE_BITS6_5_SHFT                                          0x5
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_TEST_BMSK                                             0x10
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_TEST_SHFT                                              0x4
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_TEST_DISABLE_FVAL                                      0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_TEST_ENABLE_FVAL                                       0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_RESERVE_BITS3_2_BMSK                                          0xc
#define HWIO_AOSS_CC_PLL1_USER_CTL_RESERVE_BITS3_2_SHFT                                          0x2
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_EVEN_BMSK                                              0x2
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_EVEN_SHFT                                              0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_EVEN_DISABLE_FVAL                                      0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_EVEN_ENABLE_FVAL                                       0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_MAIN_BMSK                                              0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_MAIN_SHFT                                              0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_MAIN_DISABLE_FVAL                                      0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_MAIN_ENABLE_FVAL                                       0x1

#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000100c)
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000100c)
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_RMSK                                                 0xffffffff
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_USER_CTL_U_ADDR)
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_USER_CTL_U_ADDR, m)
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_USER_CTL_U_ADDR,v)
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_USER_CTL_U_ADDR,m,v,HWIO_AOSS_CC_PLL1_USER_CTL_U_IN)
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_RESERVE_BITS63_59_BMSK                               0xf8000000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_RESERVE_BITS63_59_SHFT                                     0x1b
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_LOW_LATENCY_CLK_BMSK                           0x4000000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_LOW_LATENCY_CLK_SHFT                                0x1a
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_LOW_LATENCY_CLK_DISABLE_FVAL                         0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_LOW_LATENCY_CLK_ENABLE_FVAL                          0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_STANDBY_CLK_BMSK                               0x2000000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_STANDBY_CLK_SHFT                                    0x19
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_STANDBY_CLK_DISABLE_FVAL                             0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_STANDBY_CLK_ENABLE_FVAL                              0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_SET_MAX_COMP_RATE_BMSK                                0x1000000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_SET_MAX_COMP_RATE_SHFT                                     0x18
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_SET_MAX_COMP_RATE_DISABLE_FVAL                              0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_SET_MAX_COMP_RATE_ENABLE_FVAL                               0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_CONT_CAL_BMSK                                   0x800000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_CONT_CAL_SHFT                                       0x17
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_CONT_CAL_DISABLE_FVAL                                0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_CONT_CAL_ENABLE_FVAL                                 0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_XO_FREQUENCY_SELECT_BMSK                               0x400000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_XO_FREQUENCY_SELECT_SHFT                                   0x16
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_XO_FREQUENCY_SELECT_FREQ_19_2MHZ_FVAL                       0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_XO_FREQUENCY_SELECT_FREQ_32_768KHZ_FVAL                     0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_INTERNAL_CLOCK_SELECTION_BMSK                          0x300000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_INTERNAL_CLOCK_SELECTION_SHFT                              0x14
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_INTERNAL_CLOCK_SELECTION_STARTUP_OSCILLATOR_FVAL            0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_INTERNAL_CLOCK_SELECTION_TDO_OSCILLATOR_FVAL                0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_INTERNAL_CLOCK_SELECTION_DCO_OSCILLATOR_FVAL                0x2
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_INTERNAL_CLOCK_SELECTION_EXTERNAL_REFERENCE_CLOCK_FVAL        0x3
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_RESERVE_BITS51_49_BMSK                                  0xe0000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_RESERVE_BITS51_49_SHFT                                     0x11
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_INITIAL_OUTPUT_CLOCK_MUX_BMSK                           0x18000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_INITIAL_OUTPUT_CLOCK_MUX_SHFT                               0xf
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_INITIAL_OUTPUT_CLOCK_MUX_SELECT_XO_FVAL                     0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_INITIAL_OUTPUT_CLOCK_MUX_SELECT_INTERNAL_CLOCK_FVAL         0x2
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_KEEP_BIAS_ON_IN_STBY_BMSK                                0x4000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_KEEP_BIAS_ON_IN_STBY_SHFT                                   0xe
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_KEEP_BIAS_ON_IN_STBY_BIAS_IS_OFF_IN_STBY_FVAL               0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_KEEP_BIAS_ON_IN_STBY_BIAS_IS_ON_IN_STBY_FVAL                0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_XO_CLK_AT_OUT_BMSK                                       0x2000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_XO_CLK_AT_OUT_SHFT                                          0xd
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_XO_CLK_AT_OUT_OUTPUT_IS_DETERMINATED_BY_PLL_CLOCK_SELECT_FVAL        0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_XO_CLK_AT_OUT_AUTOMATICALLY_SWITCH_FROM_THE_CLOCK_AT_CLK_XO_PASSTHRU_TO_THE_SYNTHESIZED_CLOCK_WHEN_PLL_LOCK_DET_GOES_HIGH_OTHERWISE_IT_WILL_SIMPLY_OUTPUT_CLK_XO_PASSTHRU_FVAL        0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_CALIBRATION_SETTING_BMSK                                 0x1000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_CALIBRATION_SETTING_SHFT                                    0xc
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_CALIBRATION_SETTING_AUTOMATICALLY_RUN_CALIBRATION_IF_NECESSARY_FVAL        0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_CALIBRATION_SETTING_ALWAYS_RUN_CALIBRATION_FVAL             0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_USE_RESTORE_BMSK                                          0x800
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_USE_RESTORE_SHFT                                            0xb
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_USE_RESTORE_DO_NOT_RESTORE_STATE_FVAL                       0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_USE_RESTORE_ATTEMPT_TO_RESTORE_THE_STATE_FVAL               0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_REQUEST_CAL_BMSK                                          0x400
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_REQUEST_CAL_SHFT                                            0xa
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_REQUEST_CAL_WAIT_FVAL                                       0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_REQUEST_CAL_START_CALIBRATION_FVAL                          0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_STATUS_REGISTER_BMSK                                      0x3e0
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_STATUS_REGISTER_SHFT                                        0x5
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_RESERVE_BITS36_35_BMSK                                     0x18
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_RESERVE_BITS36_35_SHFT                                      0x3
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_CAL_SCALING_BMSK                                            0x6
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_CAL_SCALING_SHFT                                            0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_USE_EXTERNAL_CLK_REF_BMSK                                   0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_USE_EXTERNAL_CLK_REF_SHFT                                   0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_USE_EXTERNAL_CLK_REF_CLK_REF_SERVES_AS_CALIBRATION_REFERENCE_FOR_INTERNAL_OSCILLATOR_AND_THE_INTERNAL_OSCILLATOR_SERVED_AS_DFLL_REFERENCE_FVAL        0x0
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_USE_EXTERNAL_CLK_REF_CLK_REF_DIRECTLY_SERVES_AS_DFLL_REFERENCE_BYPASSING_THE_INTERNAL_OSCILLATOR_FVAL        0x1

#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001010)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00001010)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_RMSK                                                 0xffffffff
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_CONFIG_CTL_ADDR)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_CONFIG_CTL_ADDR, m)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_CONFIG_CTL_ADDR,v)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_CONFIG_CTL_ADDR,m,v,HWIO_AOSS_CC_PLL1_CONFIG_CTL_IN)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FINE_LD_UNMASK_TIMER_BMSK                            0xc0000000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FINE_LD_UNMASK_TIMER_SHFT                                  0x1e
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FINE_LD_RELOCK_SAMPLE_SIZE_BMSK                      0x30000000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FINE_LD_RELOCK_SAMPLE_SIZE_SHFT                            0x1c
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FCW_BMSK                                              0xffc0000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FCW_SHFT                                                   0x12
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_OVERRIDE_FCW_BMSK                                       0x20000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_OVERRIDE_FCW_SHFT                                          0x11
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_OVERRIDE_FCW_DO_NOT_OVERRIDE_FVAL                           0x0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_OVERRIDE_FCW_OVERRIDE_FVAL                                  0x1
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FINE_LD_THRESHOLD_BMSK                                  0x1c000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FINE_LD_THRESHOLD_SHFT                                      0xe
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FINE_LD_SAMPLE_SIZE_BMSK                                 0x3f00
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FINE_LD_SAMPLE_SIZE_SHFT                                    0x8
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FWD_GAIN_KFN_SLEW_BMSK                                     0xf0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FWD_GAIN_KFN_SLEW_SHFT                                      0x4
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FWD_GAIN_KFN_BMSK                                           0xf
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FWD_GAIN_KFN_SHFT                                           0x0

#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_ADDR                                               (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001014)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_OFFS                                               (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00001014)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_RMSK                                               0xffffffff
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_ADDR)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_ADDR, m)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_ADDR,v)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_ADDR,m,v,HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_IN)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_THRESHOLD_1_BMSK                          0xfc000000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_THRESHOLD_1_SHFT                                0x1a
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_THRESHOLD_0_BMSK                           0x3f00000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_THRESHOLD_0_SHFT                                0x14
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_RESERVE_BIT51_BMSK                                    0x80000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_RESERVE_BIT51_SHFT                                       0x13
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_SKIP_FIRST_TEMPCOMP_RELOCK_BMSK                       0x40000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_SKIP_FIRST_TEMPCOMP_RELOCK_SHFT                          0x12
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_SKIP_FIRST_TEMPCOMP_RELOCK_DO_NOT_SKIP_FVAL               0x0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_SKIP_FIRST_TEMPCOMP_RELOCK_SKIP_FVAL                      0x1
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_FIRST_TEMPCOMP_RELOCK_NUM_OUT_CYCLES_BMSK             0x30000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_FIRST_TEMPCOMP_RELOCK_NUM_OUT_CYCLES_SHFT                0x10
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_FIRST_TEMPCOMP_RELOCK_NUM_OUT_CYCLES_COUNT_16_CYCLES_FVAL        0x0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_FIRST_TEMPCOMP_RELOCK_NUM_OUT_CYCLES_COUNT_32_CYCLES_FVAL        0x1
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_FIRST_TEMPCOMP_RELOCK_NUM_OUT_CYCLES_COUNT_64_CYCLES_FVAL        0x2
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_FIRST_TEMPCOMP_RELOCK_NUM_OUT_CYCLES_COUNT_128_CYCLES_FVAL        0x3
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_FIRST_TEMPCOMP_RELOCK_BMSK                             0x8000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_FIRST_TEMPCOMP_RELOCK_SHFT                                0xf
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_FIRST_TEMPCOMP_RELOCK_STANDARD_BUT_SLOWER_CORRECTION_FVAL        0x0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_FIRST_TEMPCOMP_RELOCK_COARSE_BUT_QUICK_CORRECTION_FVAL        0x1
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_NUM_OUT_CYCLES_BMSK                           0x7000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_NUM_OUT_CYCLES_SHFT                              0xc
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_NUM_OUT_CYCLES_COUNT_32_CYCLES_FVAL              0x0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_NUM_OUT_CYCLES_COUNT_64_CYCLES_FVAL              0x1
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_NUM_OUT_CYCLES_COUNT_128_CYCLES_FVAL             0x2
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_NUM_OUT_CYCLES_COUNT_256_CYCLES_FVAL             0x3
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_NUM_OUT_CYCLES_COUNT_512_CYCLES_FVAL             0x4
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_NUM_OUT_CYCLES_COUNT_1024_CYCLES_FVAL            0x5
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_NUM_OUT_CYCLES_COUNT_2048_CYCLES_FVAL            0x6
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_NUM_OUT_CYCLES_COUNT_4096_CYCLES_FVAL            0x7
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_CAL_NUM_XO_CYCLES_BMSK                                  0xe00
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_CAL_NUM_XO_CYCLES_SHFT                                    0x9
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_CAL_NUM_XO_CYCLES_COUNT_32_CYCLES_FOR_19_2M_XO_1_CYCLE_FOR_32K_XO_FVAL        0x0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_CAL_NUM_XO_CYCLES_COUNT_64_CYCLES_FOR_19_2M_XO_1_CYCLE_FOR_32K_XO_FVAL        0x1
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_CAL_NUM_XO_CYCLES_COUNT_128_CYCLES_FOR_19_2M_XO_1_CYCLE_FOR_32K_XO_FVAL        0x2
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_CAL_NUM_XO_CYCLES_COUNT_256CYCLES_FOR_19_2M_XO_1_CYCLE_FOR_32K_XO_FVAL        0x3
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_CAL_NUM_XO_CYCLES_COUNT_512_CYCLES_FOR_19_2M_XO_1_CYCLE_FOR_32K_XO_FVAL        0x4
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_CAL_NUM_XO_CYCLES_COUNT_1024_CYCLES_FOR_19_2M_XO_2_CYCLE_FOR_32K_XO_FVAL        0x5
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_CAL_NUM_XO_CYCLES_COUNT_2048_CYCLES_FOR_19_2M_XO_4_CYCLE_FOR_32K_XO_FVAL        0x6
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_CAL_NUM_XO_CYCLES_COUNT_4096_CYCLES_FOR_19_2M_XO_8_CYCLE_FOR_32K_XO_FVAL        0x7
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_GLITCH_DETECTOR_COUNT_LIMIT_BMSK                        0x180
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_GLITCH_DETECTOR_COUNT_LIMIT_SHFT                          0x7
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_GLITCH_DETECTOR_COUNT_LIMIT_LIMIT_OF_4_FVAL               0x0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_GLITCH_DETECTOR_COUNT_LIMIT_LIMIT_OF_16_FVAL              0x1
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_GLITCH_DETECTOR_COUNT_LIMIT_LIMIT_OF_32_FVAL              0x2
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_GLITCH_DETECTOR_COUNT_LIMIT_LIMIT_OF_128_FVAL             0x3
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_GLITCH_PREVENTION_DIS_BMSK                               0x40
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_GLITCH_PREVENTION_DIS_SHFT                                0x6
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_GLITCH_PREVENTION_DIS_GLITCH_DETECTOR_IS_ON_FVAL          0x0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_GLITCH_PREVENTION_DIS_GLITCH_DETECTOR_IS_OFF_FVAL         0x1
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_BMSK                         0x20
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_SHFT                          0x5
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_MINIMUM_GLITCH_THRESHOLD_IS_NOT_INCREASED_FVAL        0x0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_MINIMUM_GLITCH_THRESHOLD_IS_INCREASED_BY_8X_FVAL        0x1
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_BMSK                                0x18
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_SHFT                                 0x3
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_MINIMUM_OF_4_FVAL                    0x0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_MINIMUM_OF_16_FVAL                   0x1
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_MINIMUM_OF_128_FVAL                  0x2
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_MINIMUM_OF_256_FVAL                  0x3
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_RQ_LFSR_DISABLE_BMSK                                 0x4
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_RQ_LFSR_DISABLE_SHFT                                 0x2
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_RQ_LFSR_DISABLE_DO_NOT_DISABLE_FVAL                  0x0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_RQ_LFSR_DISABLE_DISABLE_FVAL                         0x1
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_RQ_BYPASS_BMSK                                       0x2
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_RQ_BYPASS_SHFT                                       0x1
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_RQ_BYPASS_DO_NOT_BYPASS_FVAL                         0x0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_RQ_BYPASS_BYPASS_FVAL                                0x1
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_LFSR_DISABLE_BMSK                                    0x1
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_LFSR_DISABLE_SHFT                                    0x0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_LFSR_DISABLE_DO_NOT_DISABLE_FVAL                     0x0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_LFSR_DISABLE_DISABLE_FVAL                            0x1

#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_ADDR                                              (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001018)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_OFFS                                              (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00001018)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_RMSK                                              0xffffffff
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_ADDR)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_ADDR, m)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_ADDR,v)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_ADDR,m,v,HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_IN)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_RESERVE_BITS95_94_BMSK                            0xc0000000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_RESERVE_BITS95_94_SHFT                                  0x1e
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_6_BMSK                         0x3f000000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_6_SHFT                               0x18
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_5_BMSK                           0xfc0000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_5_SHFT                               0x12
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_4_BMSK                            0x3f000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_4_SHFT                                0xc
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_3_BMSK                              0xfc0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_3_SHFT                                0x6
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_2_BMSK                               0x3f
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_2_SHFT                                0x0

#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_ADDR                                              (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000101c)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_OFFS                                              (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000101c)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_RMSK                                              0xffffffff
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_ADDR)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_ADDR, m)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_ADDR,v)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_ADDR,m,v,HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_IN)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_RESERVE_BITS127_126_BMSK                          0xc0000000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_RESERVE_BITS127_126_SHFT                                0x1e
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_TEMPCOMP_CORRFACTOR_CLAMP_BMSK                    0x3fc00000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_TEMPCOMP_CORRFACTOR_CLAMP_SHFT                          0x16
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_TEMPCOMP_MIN_DIST_OF_SEP_BMSK                       0x3f0000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_TEMPCOMP_MIN_DIST_OF_SEP_SHFT                           0x10
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_TEMPCOMP_K_DEFAULT_BMSK                               0xffff
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_TEMPCOMP_K_DEFAULT_SHFT                                  0x0

#define HWIO_AOSS_CC_PLL1_TEST_CTL_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001020)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00001020)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_RMSK                                                   0xffffffff
#define HWIO_AOSS_CC_PLL1_TEST_CTL_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_TEST_CTL_ADDR)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_TEST_CTL_ADDR, m)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_TEST_CTL_ADDR,v)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_TEST_CTL_ADDR,m,v,HWIO_AOSS_CC_PLL1_TEST_CTL_IN)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_SOSC_ON_BMSK                                     0x80000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_SOSC_ON_SHFT                                           0x1f
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_SOSC_ON_DO_NOT_FORCE_FVAL                               0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_SOSC_ON_FORCE_ON_FVAL                                   0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_KEEP_SOSC_ON_IN_STBY_BMSK                              0x40000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_KEEP_SOSC_ON_IN_STBY_SHFT                                    0x1e
#define HWIO_AOSS_CC_PLL1_TEST_CTL_KEEP_SOSC_ON_IN_STBY_DO_NOT_FORCE_FVAL                        0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_KEEP_SOSC_ON_IN_STBY_FORCE_ON_FVAL                            0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_STAY_IN_FREERUN_BMSK                             0x20000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_STAY_IN_FREERUN_SHFT                                   0x1d
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_STAY_IN_FREERUN_DO_NOT_FORCE_FVAL                       0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_STAY_IN_FREERUN_FORCE_FVAL                              0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_STAY_IN_LOCKED_BMSK                              0x10000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_STAY_IN_LOCKED_SHFT                                    0x1c
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_STAY_IN_LOCKED_DO_NOT_FORCE_FVAL                        0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_STAY_IN_LOCKED_FORCE_FVAL                               0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_FREERUN_BMSK                                 0x8000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_FREERUN_SHFT                                      0x1b
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_FREERUN_DO_NOT_FORCE_FVAL                          0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_FREERUN_FORCE_FVAL                                 0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_LOCKED_BMSK                                  0x4000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_LOCKED_SHFT                                       0x1a
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_LOCKED_DO_NOT_FORCE_FVAL                           0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_LOCKED_FORCE_FVAL                                  0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_TEMPCOMP_BMSK                                0x2000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_TEMPCOMP_SHFT                                     0x19
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_TEMPCOMP_DO_NOT_FORCE_FVAL                         0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_TEMPCOMP_FORCE_FVAL                                0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_CAL_AFTER_FIRST_BMSK                         0x1000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_CAL_AFTER_FIRST_SHFT                              0x18
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_CAL_AFTER_FIRST_DO_NOT_FORCE_FVAL                  0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_CAL_AFTER_FIRST_FORCE_FVAL                         0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FREERUNTIMER_BMSK                                        0xe00000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FREERUNTIMER_SHFT                                            0x15
#define HWIO_AOSS_CC_PLL1_TEST_CTL_LOCKEDTIMER_BMSK                                         0x1c0000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_LOCKEDTIMER_SHFT                                             0x12
#define HWIO_AOSS_CC_PLL1_TEST_CTL_DCOTIMER_BMSK                                             0x38000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_DCOTIMER_SHFT                                                 0xf
#define HWIO_AOSS_CC_PLL1_TEST_CTL_BIASTIMER_BMSK                                             0x7000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_BIASTIMER_SHFT                                                0xc
#define HWIO_AOSS_CC_PLL1_TEST_CTL_TDOTIMER2_BMSK                                              0xe00
#define HWIO_AOSS_CC_PLL1_TEST_CTL_TDOTIMER2_SHFT                                                0x9
#define HWIO_AOSS_CC_PLL1_TEST_CTL_TDOTIMER1_BMSK                                              0x1c0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_TDOTIMER1_SHFT                                                0x6
#define HWIO_AOSS_CC_PLL1_TEST_CTL_TDOTIMER0_BMSK                                               0x38
#define HWIO_AOSS_CC_PLL1_TEST_CTL_TDOTIMER0_SHFT                                                0x3
#define HWIO_AOSS_CC_PLL1_TEST_CTL_TSENSTIMER_BMSK                                               0x7
#define HWIO_AOSS_CC_PLL1_TEST_CTL_TSENSTIMER_SHFT                                               0x0

#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001024)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00001024)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_RMSK                                                 0xffffffff
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_TEST_CTL_U_ADDR)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_TEST_CTL_U_ADDR, m)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_TEST_CTL_U_ADDR,v)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_TEST_CTL_U_ADDR,m,v,HWIO_AOSS_CC_PLL1_TEST_CTL_U_IN)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_TDO_PCAL_TARGET_BMSK                                 0xf0000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_TDO_PCAL_TARGET_SHFT                                       0x1c
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_LD_UNMASK_BMSK                                  0x8000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_LD_UNMASK_SHFT                                       0x1b
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_LD_UNMASK_DO_NOT_FORCE_FVAL                           0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_LD_UNMASK_FORCE_ON_FVAL                               0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_STATUS_SEL_CAL_RAM_ROW_BMSK                           0x7000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_STATUS_SEL_CAL_RAM_ROW_SHFT                                0x18
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_DISABLE_TSENS_IN_STBY_BMSK                             0x800000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_DISABLE_TSENS_IN_STBY_SHFT                                 0x17
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_RESERVE_BITS54_51_BMSK                                 0x780000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_RESERVE_BITS54_51_SHFT                                     0x13
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_BIST_CFG_BMSK                                           0x7ff80
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_BIST_CFG_SHFT                                               0x7
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_ENABLE_TEST_SEQ_BMSK                                       0x40
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_ENABLE_TEST_SEQ_SHFT                                        0x6
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_ENABLE_TEST_SEQ_DISABLE_FVAL                                0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_ENABLE_TEST_SEQ_ENABLE_FVAL                                 0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_STATUS_REG_EN_BMSK                                         0x20
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_STATUS_REG_EN_SHFT                                          0x5
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_STATUS_REG_EN_DISABLE_FVAL                                  0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_STATUS_REG_EN_ENABLE_FVAL                                   0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_BIAS_AND_DCO_ON_BMSK                                 0x10
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_BIAS_AND_DCO_ON_SHFT                                  0x4
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_BIAS_AND_DCO_ON_DO_NOT_FORCE_FVAL                     0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_BIAS_AND_DCO_ON_FORCE_ON_FVAL                         0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_SET_TDO_MODE_BMSK                                           0x8
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_SET_TDO_MODE_SHFT                                           0x3
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_SET_TDO_MODE_REF_MODE_FVAL                                  0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_SET_TDO_MODE_TSENS_MODE_FVAL                                0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TDO_MODE_BMSK                                         0x4
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TDO_MODE_SHFT                                         0x2
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TDO_MODE_DO_NOT_FORCE_FVAL                            0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TDO_MODE_FORCE_ON_FVAL                                0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TDO_ON_BMSK                                           0x2
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TDO_ON_SHFT                                           0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TDO_ON_DO_NOT_FORCE_FVAL                              0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TDO_ON_FORCE_ON_FVAL                                  0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TSENS_ON_BMSK                                         0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TSENS_ON_SHFT                                         0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TSENS_ON_DO_NOT_FORCE_FVAL                            0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TSENS_ON_FORCE_ON_FVAL                                0x1

#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001028)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_OFFS                                                (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00001028)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_RMSK                                                0xffffffff
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_TEST_CTL_U1_ADDR)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_TEST_CTL_U1_ADDR, m)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_TEST_CTL_U1_ADDR,v)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_TEST_CTL_U1_ADDR,m,v,HWIO_AOSS_CC_PLL1_TEST_CTL_U1_IN)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INITIAL_INPUT_MUX_CLK_CAL_BMSK                      0xc0000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INITIAL_INPUT_MUX_CLK_CAL_SHFT                            0x1e
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INITIAL_INPUT_MUX_CLK_CAL_DCO_DIVIDED_BY_2_FVAL            0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INITIAL_INPUT_MUX_CLK_CAL_XO_FVAL                          0x2
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INITIAL_INPUT_MUX_CLK_DIG_BMSK                      0x3e000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INITIAL_INPUT_MUX_CLK_DIG_SHFT                            0x19
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INITIAL_INPUT_MUX_CLK_DIG_EXTERNAL_REFERENCE_FVAL          0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INITIAL_INPUT_MUX_CLK_DIG_STARTUP_CLOCK_FVAL               0x2
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INITIAL_INPUT_MUX_CLK_DIG_DCO_CLOCK_UNDIVIDED_FVAL         0x4
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INITIAL_INPUT_MUX_CLK_DIG_TDO_CLOCK_DIVIDED_DOWN_AS_DFLL_REF_FVAL        0x8
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INITIAL_INPUT_MUX_CLK_DIG_FREERUN_CLOCK_FVAL              0x10
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_ATEST1_VOLT_SEL_BMSK                             0x1800000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_ATEST1_VOLT_SEL_SHFT                                  0x17
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_REG_BIAS_BMSK                                     0x600000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_REG_BIAS_SHFT                                         0x15
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_VREF_SEL_BMSK                                     0x180000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_VREF_SEL_SHFT                                         0x13
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_ENABLEVMUXPROBE_BMSK                               0x40000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_ENABLEVMUXPROBE_SHFT                                  0x12
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_ENABLEVLDOPROBE_BMSK                               0x20000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_ENABLEVLDOPROBE_SHFT                                  0x11
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_CHOPSELECT_BMSK                                    0x10000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_CHOPSELECT_SHFT                                       0x10
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_BIAS_ENABLEATESTSOURCE_BMSK                             0x8000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_BIAS_ENABLEATESTSOURCE_SHFT                                0xf
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_BIAS_ENABLEIOUTATEST_BMSK                               0x4000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_BIAS_ENABLEIOUTATEST_SHFT                                  0xe
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_DISABLE_RESYNC_BMSK                                 0x2000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_DISABLE_RESYNC_SHFT                                    0xd
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_RESISTOR_ADJUST_BMSK                                0x1800
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_RESISTOR_ADJUST_SHFT                                   0xb
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_INCREASE_GAIN_BMSK                                   0x400
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_INCREASE_GAIN_SHFT                                     0xa
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_INCREASE_GAIN_NOMINAL_GAIN_SETTING_FVAL                0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_INCREASE_GAIN_HIGHER_GAIN_SETTING_FVAL                 0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_RESERVE_BIT73_BMSK                                       0x200
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_RESERVE_BIT73_SHFT                                         0x9
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_SELECT_FWD_GAIN_TEMPCOMP_BMSK                            0x100
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_SELECT_FWD_GAIN_TEMPCOMP_SHFT                              0x8
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_SELECT_FWD_GAIN_TEMPCOMP_USE_KFN_SLEW_FOR_LOCK_AND_RELOCK_AND_TEMPCOMP_FVAL        0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_SELECT_FWD_GAIN_TEMPCOMP_USE_KFN_SLEW_FOR_LOCK_AND_RELOCK_BUT_KFN_FOR_TEMPCOMP_FVAL        0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_PCAL_DIV_EN_BMSK                                      0x80
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_PCAL_DIV_EN_SHFT                                       0x7
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_FORCE_BOTH_DCO_ENABLES_TOGETHER_BMSK                      0x40
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_FORCE_BOTH_DCO_ENABLES_TOGETHER_SHFT                       0x6
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_FORCE_DCO_PCAL_VALUE_BMSK                                 0x20
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_FORCE_DCO_PCAL_VALUE_SHFT                                  0x5
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DISABLE_DCO_PCAL_BMSK                                     0x10
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DISABLE_DCO_PCAL_SHFT                                      0x4
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DISABLE_DCO_PCAL_DO_NOT_DISABLE_FVAL                       0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DISABLE_DCO_PCAL_DISABLE_FVAL                              0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_FORCE_TDO_PCAL_VALUE_BMSK                                  0xe
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_FORCE_TDO_PCAL_VALUE_SHFT                                  0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DISABLE_TDO_PCAL_BMSK                                      0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DISABLE_TDO_PCAL_SHFT                                      0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DISABLE_TDO_PCAL_DO_NOT_DISABLE_FVAL                       0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DISABLE_TDO_PCAL_DISABLE_FVAL                              0x1

#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000102c)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_OFFS                                                (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000102c)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_RMSK                                                0xffffffff
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ADDR)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ADDR, m)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ADDR,v)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ADDR,m,v,HWIO_AOSS_CC_PLL1_TEST_CTL_U2_IN)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_PLL_TEST_OUT_SEL_BMSK                               0xf0000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_PLL_TEST_OUT_SEL_SHFT                                     0x1c
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_OVERRIDE_XO_BMSK                                     0x8000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_OVERRIDE_XO_SHFT                                          0x1b
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_OVERRIDE_XO_DO_NOT_OVERRIDE_FVAL                           0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_OVERRIDE_XO_OVERRIDE_FVAL                                  0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NMO_EN_DIV2_BMSK                                     0x4000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NMO_EN_DIV2_SHFT                                          0x1a
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NMO_EN_DIV2_DISABLE_FVAL                                   0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NMO_EN_DIV2_ENABLE_FVAL                                    0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NMO_OSC_SEL_BMSK                                     0x3000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NMO_OSC_SEL_SHFT                                          0x18
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NMO_OSC_SEL_OFF_FVAL                                       0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NMO_OSC_SEL_FREQ_OF_350MHZ_FVAL                            0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NMO_OSC_SEL_FREQ_OF_700MHZ_FVAL                            0x2
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NMO_OSC_SEL_FREQ_OF_1400MHZ_FVAL                           0x3
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NG_NOISE_MAG_BMSK                                     0xe00000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NG_NOISE_MAG_SHFT                                         0x15
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NG_NOISE_MAG_OFF_FVAL                                      0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NG_NOISE_MAG_MAGNITUDE_OF_34MVRMS_FVAL                     0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NG_NOISE_MAG_MAGNITUDE_OF_61MVRMS_FVAL                     0x3
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NG_NOISE_MAG_MAGNITUDE_OF_72MVRMS_FVAL                     0x7
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NG_EN_BMSK                                            0x100000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NG_EN_SHFT                                                0x14
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NG_EN_DISABLE_FVAL                                         0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NG_EN_ENABLE_FVAL                                          0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST1_BUFFER_CHOP_BMSK                                0x80000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST1_BUFFER_CHOP_SHFT                                   0x13
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST1_BUFFER_CHOP_CHOP_ONE_WAY_FVAL                       0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST1_BUFFER_CHOP_CHOP_OTHER_WAY_FVAL                     0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST1_BUFFER_EN_BMSK                                  0x40000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST1_BUFFER_EN_SHFT                                     0x12
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST1_BUFFER_EN_DISABLE_AND_BYPASS_FVAL                   0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST1_BUFFER_EN_ENABLE_FVAL                               0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST_EN_BMSK                                          0x20000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST_EN_SHFT                                             0x11
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST_EN_DISABLE_FVAL                                      0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST_EN_ENABLE_FVAL                                       0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_RESERVE_BITS112_110_BMSK                               0x1c000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_RESERVE_BITS112_110_SHFT                                   0xe
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_SOSC_CAL_THRSHLD_BMSK                                   0x3000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_SOSC_CAL_THRSHLD_SHFT                                      0xc
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_OVERRIDE_SOSC_CAL_DIV_BMSK                               0x800
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_OVERRIDE_SOSC_CAL_DIV_SHFT                                 0xb
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_FREERUN_BMSK                               0x780
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_FREERUN_SHFT                                 0x7
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_FREERUN_DIVIDE_BY_1_FVAL                     0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_FREERUN_DIVIDE_BY_2_FVAL                     0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_FREERUN_DIVIDE_BY_4_FVAL                     0x3
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_FREERUN_DIVIDE_BY_8_FVAL                     0x7
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_FREERUN_DIVIDE_BY_16_FVAL                    0xf
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_SPEEDUP_CLKDIG_TEMPCOMP_BMSK                              0x40
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_SPEEDUP_CLKDIG_TEMPCOMP_SHFT                               0x6
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_SPEEDUP_CLKDIG_TEMPCOMP_MULTIPLY_BY_1_FVAL                 0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_SPEEDUP_CLKDIG_TEMPCOMP_MULTIPLY_BY_2_FVAL                 0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_ACQ_LOCKED_BMSK                             0x38
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_ACQ_LOCKED_SHFT                              0x3
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_ACQ_LOCKED_DIVIDE_BY_32_FVAL                 0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_ACQ_LOCKED_DIVIDE_BY_64_FVAL                 0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_ACQ_LOCKED_DIVIDE_BY_128_FVAL                0x3
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_ACQ_LOCKED_DIVIDE_BY_256_FVAL                0x7
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_SOSC_BMSK                                           0x6
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_SOSC_SHFT                                           0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_SOSC_DIVIDE_BY_1_FVAL                               0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_SOSC_DIVIDE_BY_2_FVAL                               0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_SOSC_DIVIDE_BY_4_FVAL                               0x3
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_TDO_BMSK                                            0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_TDO_SHFT                                            0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_TDO_DIVIDE_BY_1_FVAL                                0x0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_TDO_DIVIDE_BY_2_FVAL                                0x1

#define HWIO_AOSS_CC_PLL1_FREQ_CTL_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001030)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00001030)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_RMSK                                                   0xffffffff
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_FREQ_CTL_ADDR)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_FREQ_CTL_ADDR, m)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_FREQ_CTL_ADDR,v)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_FREQ_CTL_ADDR,m,v,HWIO_AOSS_CC_PLL1_FREQ_CTL_IN)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_FREQUENCY_CTL_WORD_LOWER_BMSK                          0xffffffff
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_FREQUENCY_CTL_WORD_LOWER_SHFT                                 0x0

#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001034)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00001034)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_RMSK                                                 0xffffffff
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_FREQ_CTL_U_ADDR)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_FREQ_CTL_U_ADDR, m)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_FREQ_CTL_U_ADDR,v)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_FREQ_CTL_U_ADDR,m,v,HWIO_AOSS_CC_PLL1_FREQ_CTL_U_IN)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_FREQUENCY_CTL_WORD_UPPER_BMSK                        0xffffffff
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_FREQUENCY_CTL_WORD_UPPER_SHFT                               0x0

#define HWIO_AOSS_CC_PLL1_STATUS_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001038)
#define HWIO_AOSS_CC_PLL1_STATUS_OFFS                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00001038)
#define HWIO_AOSS_CC_PLL1_STATUS_RMSK                                                     0xffffffff
#define HWIO_AOSS_CC_PLL1_STATUS_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_STATUS_ADDR)
#define HWIO_AOSS_CC_PLL1_STATUS_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_STATUS_ADDR, m)
#define HWIO_AOSS_CC_PLL1_STATUS_STATUS_31_0_BMSK                                         0xffffffff
#define HWIO_AOSS_CC_PLL1_STATUS_STATUS_31_0_SHFT                                                0x0

#define HWIO_AOSS_CC_PLL1_STATE_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000103c)
#define HWIO_AOSS_CC_PLL1_STATE_OFFS                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000103c)
#define HWIO_AOSS_CC_PLL1_STATE_RMSK                                                             0x7
#define HWIO_AOSS_CC_PLL1_STATE_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_STATE_ADDR)
#define HWIO_AOSS_CC_PLL1_STATE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_STATE_ADDR, m)
#define HWIO_AOSS_CC_PLL1_STATE_PLL_STATE_BMSK                                                   0x7
#define HWIO_AOSS_CC_PLL1_STATE_PLL_STATE_SHFT                                                   0x0
#define HWIO_AOSS_CC_PLL1_STATE_PLL_STATE_OFF_FVAL                                               0x0
#define HWIO_AOSS_CC_PLL1_STATE_PLL_STATE_STANDBY_FVAL                                           0x1
#define HWIO_AOSS_CC_PLL1_STATE_PLL_STATE_RUN_FVAL                                               0x7

#define HWIO_AOSS_CC_PLL1_OPMODE_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001040)
#define HWIO_AOSS_CC_PLL1_OPMODE_OFFS                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00001040)
#define HWIO_AOSS_CC_PLL1_OPMODE_RMSK                                                            0x7
#define HWIO_AOSS_CC_PLL1_OPMODE_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_OPMODE_ADDR)
#define HWIO_AOSS_CC_PLL1_OPMODE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_OPMODE_ADDR, m)
#define HWIO_AOSS_CC_PLL1_OPMODE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_OPMODE_ADDR,v)
#define HWIO_AOSS_CC_PLL1_OPMODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_OPMODE_ADDR,m,v,HWIO_AOSS_CC_PLL1_OPMODE_IN)
#define HWIO_AOSS_CC_PLL1_OPMODE_PLL_OPMODE_BMSK                                                 0x7
#define HWIO_AOSS_CC_PLL1_OPMODE_PLL_OPMODE_SHFT                                                 0x0
#define HWIO_AOSS_CC_PLL1_OPMODE_PLL_OPMODE_STANDBY_FVAL                                         0x0
#define HWIO_AOSS_CC_PLL1_OPMODE_PLL_OPMODE_RUN_FVAL                                             0x1
#define HWIO_AOSS_CC_PLL1_OPMODE_PLL_OPMODE_NA_FVAL                                              0x2

#define HWIO_AOSS_CC_PLL1_SPARE_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001044)
#define HWIO_AOSS_CC_PLL1_SPARE_OFFS                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00001044)
#define HWIO_AOSS_CC_PLL1_SPARE_RMSK                                                            0xff
#define HWIO_AOSS_CC_PLL1_SPARE_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_SPARE_ADDR)
#define HWIO_AOSS_CC_PLL1_SPARE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_SPARE_ADDR, m)
#define HWIO_AOSS_CC_PLL1_SPARE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_SPARE_ADDR,v)
#define HWIO_AOSS_CC_PLL1_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_SPARE_ADDR,m,v,HWIO_AOSS_CC_PLL1_SPARE_IN)
#define HWIO_AOSS_CC_PLL1_SPARE_SPARE_OUTPUTS_BMSK                                              0xf0
#define HWIO_AOSS_CC_PLL1_SPARE_SPARE_OUTPUTS_SHFT                                               0x4
#define HWIO_AOSS_CC_PLL1_SPARE_SPARE_INPUTS_BMSK                                                0xf
#define HWIO_AOSS_CC_PLL1_SPARE_SPARE_INPUTS_SHFT                                                0x0

#define HWIO_AOSS_CC_AOP_BCR_ADDR                                                         (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002000)
#define HWIO_AOSS_CC_AOP_BCR_OFFS                                                         (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002000)
#define HWIO_AOSS_CC_AOP_BCR_RMSK                                                                0x1
#define HWIO_AOSS_CC_AOP_BCR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_BCR_ADDR)
#define HWIO_AOSS_CC_AOP_BCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_BCR_ADDR, m)
#define HWIO_AOSS_CC_AOP_BCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_BCR_ADDR,v)
#define HWIO_AOSS_CC_AOP_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_BCR_ADDR,m,v,HWIO_AOSS_CC_AOP_BCR_IN)
#define HWIO_AOSS_CC_AOP_BCR_BLK_ARES_BMSK                                                       0x1
#define HWIO_AOSS_CC_AOP_BCR_BLK_ARES_SHFT                                                       0x0
#define HWIO_AOSS_CC_AOP_BCR_BLK_ARES_DISABLE_FVAL                                               0x0
#define HWIO_AOSS_CC_AOP_BCR_BLK_ARES_ENABLE_FVAL                                                0x1

#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_ADDR                                           (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002004)
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_OFFS                                           (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002004)
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_RMSK                                           0x80000005
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_ADDR)
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_ADDR, m)
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_ADDR,v)
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_ADDR,m,v,HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_IN)
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_CLK_OFF_BMSK                                   0x80000000
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_CLK_OFF_SHFT                                         0x1f
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_CLK_ARES_BMSK                                         0x4
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_CLK_ARES_SHFT                                         0x2
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_CLK_ARES_NO_RESET_FVAL                                0x0
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_CLK_ARES_RESET_FVAL                                   0x1
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_CLK_ENABLE_BMSK                                       0x1
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_CLK_ENABLE_SHFT                                       0x0
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_CLK_ENABLE_DISABLE_FVAL                               0x0
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_CLK_ENABLE_ENABLE_FVAL                                0x1

#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_ADDR                                         (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002008)
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_OFFS                                         (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002008)
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_RMSK                                         0x80000004
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_ADDR)
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_ADDR, m)
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_ADDR,v)
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_ADDR,m,v,HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_IN)
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_CLK_OFF_BMSK                                 0x80000000
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_CLK_OFF_SHFT                                       0x1f
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_CLK_ARES_BMSK                                       0x4
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_CLK_ARES_SHFT                                       0x2
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_CLK_ARES_NO_RESET_FVAL                              0x0
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_CLK_ARES_RESET_FVAL                                 0x1

#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_ADDR                                               (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000200c)
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_OFFS                                               (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000200c)
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_RMSK                                               0x80000004
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_ADDR)
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_ADDR, m)
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_ADDR,v)
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_ADDR,m,v,HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_IN)
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_CLK_OFF_BMSK                                       0x80000000
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_CLK_OFF_SHFT                                             0x1f
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_CLK_ARES_BMSK                                             0x4
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_CLK_ARES_SHFT                                             0x2
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_CLK_ARES_NO_RESET_FVAL                                    0x0
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_CLK_ARES_RESET_FVAL                                       0x1

#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002010)
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_OFFS                                                (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002010)
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_RMSK                                                0x80007ff4
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_ADDR)
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_ADDR, m)
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_ADDR,v)
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_ADDR,m,v,HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_IN)
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_CORE_ON_BMSK                                  0x4000
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_CORE_ON_SHFT                                     0xe
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL                       0x0
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL                        0x1
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                0x2000
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                   0xd
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL                     0x0
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL                      0x1
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                               0x1000
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                  0xc
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL                    0x0
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL                     0x1
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_BMSK                                              0xf00
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_SHFT                                                0x8
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_CLOCK0_FVAL                                         0x0
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_CLOCK1_FVAL                                         0x1
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_CLOCK2_FVAL                                         0x2
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_CLOCK3_FVAL                                         0x3
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_CLOCK4_FVAL                                         0x4
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_CLOCK5_FVAL                                         0x5
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_CLOCK6_FVAL                                         0x6
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_CLOCK7_FVAL                                         0x7
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_CLOCK8_FVAL                                         0x8
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_CLOCK9_FVAL                                         0x9
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_CLOCK10_FVAL                                        0xa
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_CLOCK11_FVAL                                        0xb
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_CLOCK12_FVAL                                        0xc
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_CLOCK13_FVAL                                        0xd
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_CLOCK14_FVAL                                        0xe
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_CLOCK15_FVAL                                        0xf
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_BMSK                                                0xf0
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_SHFT                                                 0x4
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_CLOCK0_FVAL                                          0x0
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_CLOCK1_FVAL                                          0x1
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_CLOCK2_FVAL                                          0x2
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_CLOCK3_FVAL                                          0x3
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_CLOCK4_FVAL                                          0x4
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_CLOCK5_FVAL                                          0x5
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_CLOCK6_FVAL                                          0x6
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_CLOCK7_FVAL                                          0x7
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_CLOCK8_FVAL                                          0x8
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_CLOCK9_FVAL                                          0x9
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_CLOCK10_FVAL                                         0xa
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_CLOCK11_FVAL                                         0xb
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_CLOCK12_FVAL                                         0xc
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_CLOCK13_FVAL                                         0xd
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_CLOCK14_FVAL                                         0xe
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_CLOCK15_FVAL                                         0xf
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_CLK_ARES_NO_RESET_FVAL                                     0x0
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_CLK_ARES_RESET_FVAL                                        0x1

#define HWIO_AOSS_CC_BUS_CBCR_ADDR                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002014)
#define HWIO_AOSS_CC_BUS_CBCR_OFFS                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002014)
#define HWIO_AOSS_CC_BUS_CBCR_RMSK                                                        0x80000004
#define HWIO_AOSS_CC_BUS_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_BUS_CBCR_ADDR)
#define HWIO_AOSS_CC_BUS_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_BUS_CBCR_ADDR, m)
#define HWIO_AOSS_CC_BUS_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_BUS_CBCR_ADDR,v)
#define HWIO_AOSS_CC_BUS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_BUS_CBCR_ADDR,m,v,HWIO_AOSS_CC_BUS_CBCR_IN)
#define HWIO_AOSS_CC_BUS_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_AOSS_CC_BUS_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_AOSS_CC_BUS_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_AOSS_CC_BUS_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_AOSS_CC_BUS_CBCR_CLK_ARES_NO_RESET_FVAL                                             0x0
#define HWIO_AOSS_CC_BUS_CBCR_CLK_ARES_RESET_FVAL                                                0x1

#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002018)
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_OFFS                                                (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002018)
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_RMSK                                                0x80007ff5
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_MESSAGE_RAM_CBCR_ADDR)
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_MESSAGE_RAM_CBCR_ADDR, m)
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_MESSAGE_RAM_CBCR_ADDR,v)
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_MESSAGE_RAM_CBCR_ADDR,m,v,HWIO_AOSS_CC_MESSAGE_RAM_CBCR_IN)
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_CORE_ON_BMSK                                  0x4000
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_CORE_ON_SHFT                                     0xe
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL                       0x0
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL                        0x1
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                0x2000
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                   0xd
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL                     0x0
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL                      0x1
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                               0x1000
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                  0xc
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL                    0x0
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL                     0x1
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_BMSK                                              0xf00
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_SHFT                                                0x8
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_CLOCK0_FVAL                                         0x0
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_CLOCK1_FVAL                                         0x1
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_CLOCK2_FVAL                                         0x2
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_CLOCK3_FVAL                                         0x3
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_CLOCK4_FVAL                                         0x4
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_CLOCK5_FVAL                                         0x5
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_CLOCK6_FVAL                                         0x6
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_CLOCK7_FVAL                                         0x7
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_CLOCK8_FVAL                                         0x8
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_CLOCK9_FVAL                                         0x9
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_CLOCK10_FVAL                                        0xa
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_CLOCK11_FVAL                                        0xb
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_CLOCK12_FVAL                                        0xc
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_CLOCK13_FVAL                                        0xd
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_CLOCK14_FVAL                                        0xe
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_CLOCK15_FVAL                                        0xf
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_BMSK                                                0xf0
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_SHFT                                                 0x4
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_CLOCK0_FVAL                                          0x0
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_CLOCK1_FVAL                                          0x1
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_CLOCK2_FVAL                                          0x2
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_CLOCK3_FVAL                                          0x3
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_CLOCK4_FVAL                                          0x4
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_CLOCK5_FVAL                                          0x5
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_CLOCK6_FVAL                                          0x6
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_CLOCK7_FVAL                                          0x7
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_CLOCK8_FVAL                                          0x8
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_CLOCK9_FVAL                                          0x9
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_CLOCK10_FVAL                                         0xa
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_CLOCK11_FVAL                                         0xb
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_CLOCK12_FVAL                                         0xc
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_CLOCK13_FVAL                                         0xd
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_CLOCK14_FVAL                                         0xe
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_CLOCK15_FVAL                                         0xf
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_CLK_ARES_NO_RESET_FVAL                                     0x0
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_CLK_ARES_RESET_FVAL                                        0x1
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_CLK_ENABLE_BMSK                                            0x1
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_CLK_ENABLE_SHFT                                            0x0
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_CLK_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_CLK_ENABLE_ENABLE_FVAL                                     0x1

#define HWIO_AOSS_CC_AOP_RO_CBCR_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000201c)
#define HWIO_AOSS_CC_AOP_RO_CBCR_OFFS                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000201c)
#define HWIO_AOSS_CC_AOP_RO_CBCR_RMSK                                                     0x80000005
#define HWIO_AOSS_CC_AOP_RO_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_RO_CBCR_ADDR)
#define HWIO_AOSS_CC_AOP_RO_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_RO_CBCR_ADDR, m)
#define HWIO_AOSS_CC_AOP_RO_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_RO_CBCR_ADDR,v)
#define HWIO_AOSS_CC_AOP_RO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_RO_CBCR_ADDR,m,v,HWIO_AOSS_CC_AOP_RO_CBCR_IN)
#define HWIO_AOSS_CC_AOP_RO_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_AOSS_CC_AOP_RO_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_AOSS_CC_AOP_RO_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_AOSS_CC_AOP_RO_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_AOSS_CC_AOP_RO_CBCR_CLK_ARES_NO_RESET_FVAL                                          0x0
#define HWIO_AOSS_CC_AOP_RO_CBCR_CLK_ARES_RESET_FVAL                                             0x1
#define HWIO_AOSS_CC_AOP_RO_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_AOSS_CC_AOP_RO_CBCR_CLK_ENABLE_SHFT                                                 0x0
#define HWIO_AOSS_CC_AOP_RO_CBCR_CLK_ENABLE_DISABLE_FVAL                                         0x0
#define HWIO_AOSS_CC_AOP_RO_CBCR_CLK_ENABLE_ENABLE_FVAL                                          0x1

#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_ADDR                                               (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002020)
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_OFFS                                               (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002020)
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_RMSK                                               0x80000005
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_ADDR)
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_ADDR, m)
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_ADDR,v)
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_ADDR,m,v,HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_IN)
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_CLK_OFF_BMSK                                       0x80000000
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_CLK_OFF_SHFT                                             0x1f
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_CLK_ARES_BMSK                                             0x4
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_CLK_ARES_SHFT                                             0x2
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_CLK_ARES_NO_RESET_FVAL                                    0x0
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_CLK_ARES_RESET_FVAL                                       0x1
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_CLK_ENABLE_BMSK                                           0x1
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_CLK_ENABLE_SHFT                                           0x0
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_CLK_ENABLE_DISABLE_FVAL                                   0x0
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_CLK_ENABLE_ENABLE_FVAL                                    0x1

#define HWIO_AOSS_CC_AO_DAP_CBCR_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002024)
#define HWIO_AOSS_CC_AO_DAP_CBCR_OFFS                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002024)
#define HWIO_AOSS_CC_AO_DAP_CBCR_RMSK                                                     0x80000005
#define HWIO_AOSS_CC_AO_DAP_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_AO_DAP_CBCR_ADDR)
#define HWIO_AOSS_CC_AO_DAP_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AO_DAP_CBCR_ADDR, m)
#define HWIO_AOSS_CC_AO_DAP_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AO_DAP_CBCR_ADDR,v)
#define HWIO_AOSS_CC_AO_DAP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AO_DAP_CBCR_ADDR,m,v,HWIO_AOSS_CC_AO_DAP_CBCR_IN)
#define HWIO_AOSS_CC_AO_DAP_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_AOSS_CC_AO_DAP_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_AOSS_CC_AO_DAP_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_AOSS_CC_AO_DAP_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_AOSS_CC_AO_DAP_CBCR_CLK_ARES_NO_RESET_FVAL                                          0x0
#define HWIO_AOSS_CC_AO_DAP_CBCR_CLK_ARES_RESET_FVAL                                             0x1
#define HWIO_AOSS_CC_AO_DAP_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_AOSS_CC_AO_DAP_CBCR_CLK_ENABLE_SHFT                                                 0x0
#define HWIO_AOSS_CC_AO_DAP_CBCR_CLK_ENABLE_DISABLE_FVAL                                         0x0
#define HWIO_AOSS_CC_AO_DAP_CBCR_CLK_ENABLE_ENABLE_FVAL                                          0x1

#define HWIO_AOSS_CC_AOP_DAP_CBCR_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002028)
#define HWIO_AOSS_CC_AOP_DAP_CBCR_OFFS                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002028)
#define HWIO_AOSS_CC_AOP_DAP_CBCR_RMSK                                                    0x80000005
#define HWIO_AOSS_CC_AOP_DAP_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_DAP_CBCR_ADDR)
#define HWIO_AOSS_CC_AOP_DAP_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_DAP_CBCR_ADDR, m)
#define HWIO_AOSS_CC_AOP_DAP_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_DAP_CBCR_ADDR,v)
#define HWIO_AOSS_CC_AOP_DAP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_DAP_CBCR_ADDR,m,v,HWIO_AOSS_CC_AOP_DAP_CBCR_IN)
#define HWIO_AOSS_CC_AOP_DAP_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_AOSS_CC_AOP_DAP_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_AOSS_CC_AOP_DAP_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_AOSS_CC_AOP_DAP_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_AOSS_CC_AOP_DAP_CBCR_CLK_ARES_NO_RESET_FVAL                                         0x0
#define HWIO_AOSS_CC_AOP_DAP_CBCR_CLK_ARES_RESET_FVAL                                            0x1
#define HWIO_AOSS_CC_AOP_DAP_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_AOSS_CC_AOP_DAP_CBCR_CLK_ENABLE_SHFT                                                0x0
#define HWIO_AOSS_CC_AOP_DAP_CBCR_CLK_ENABLE_DISABLE_FVAL                                        0x0
#define HWIO_AOSS_CC_AOP_DAP_CBCR_CLK_ENABLE_ENABLE_FVAL                                         0x1

#define HWIO_AOSS_CC_WCSS_TS_CBCR_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000202c)
#define HWIO_AOSS_CC_WCSS_TS_CBCR_OFFS                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000202c)
#define HWIO_AOSS_CC_WCSS_TS_CBCR_RMSK                                                    0x80000005
#define HWIO_AOSS_CC_WCSS_TS_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_WCSS_TS_CBCR_ADDR)
#define HWIO_AOSS_CC_WCSS_TS_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_WCSS_TS_CBCR_ADDR, m)
#define HWIO_AOSS_CC_WCSS_TS_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_WCSS_TS_CBCR_ADDR,v)
#define HWIO_AOSS_CC_WCSS_TS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_WCSS_TS_CBCR_ADDR,m,v,HWIO_AOSS_CC_WCSS_TS_CBCR_IN)
#define HWIO_AOSS_CC_WCSS_TS_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_AOSS_CC_WCSS_TS_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_AOSS_CC_WCSS_TS_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_AOSS_CC_WCSS_TS_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_AOSS_CC_WCSS_TS_CBCR_CLK_ARES_NO_RESET_FVAL                                         0x0
#define HWIO_AOSS_CC_WCSS_TS_CBCR_CLK_ARES_RESET_FVAL                                            0x1
#define HWIO_AOSS_CC_WCSS_TS_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_AOSS_CC_WCSS_TS_CBCR_CLK_ENABLE_SHFT                                                0x0
#define HWIO_AOSS_CC_WCSS_TS_CBCR_CLK_ENABLE_DISABLE_FVAL                                        0x0
#define HWIO_AOSS_CC_WCSS_TS_CBCR_CLK_ENABLE_ENABLE_FVAL                                         0x1

#define HWIO_AOSS_CC_RO_CBCR_ADDR                                                         (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002030)
#define HWIO_AOSS_CC_RO_CBCR_OFFS                                                         (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002030)
#define HWIO_AOSS_CC_RO_CBCR_RMSK                                                         0x80000005
#define HWIO_AOSS_CC_RO_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_RO_CBCR_ADDR)
#define HWIO_AOSS_CC_RO_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RO_CBCR_ADDR, m)
#define HWIO_AOSS_CC_RO_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RO_CBCR_ADDR,v)
#define HWIO_AOSS_CC_RO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RO_CBCR_ADDR,m,v,HWIO_AOSS_CC_RO_CBCR_IN)
#define HWIO_AOSS_CC_RO_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_AOSS_CC_RO_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_AOSS_CC_RO_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_AOSS_CC_RO_CBCR_CLK_ARES_SHFT                                                       0x2
#define HWIO_AOSS_CC_RO_CBCR_CLK_ARES_NO_RESET_FVAL                                              0x0
#define HWIO_AOSS_CC_RO_CBCR_CLK_ARES_RESET_FVAL                                                 0x1
#define HWIO_AOSS_CC_RO_CBCR_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_AOSS_CC_RO_CBCR_CLK_ENABLE_SHFT                                                     0x0
#define HWIO_AOSS_CC_RO_CBCR_CLK_ENABLE_DISABLE_FVAL                                             0x0
#define HWIO_AOSS_CC_RO_CBCR_CLK_ENABLE_ENABLE_FVAL                                              0x1

#define HWIO_AOSS_CC_EUD_AT_CBCR_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002034)
#define HWIO_AOSS_CC_EUD_AT_CBCR_OFFS                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002034)
#define HWIO_AOSS_CC_EUD_AT_CBCR_RMSK                                                     0x80000005
#define HWIO_AOSS_CC_EUD_AT_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_EUD_AT_CBCR_ADDR)
#define HWIO_AOSS_CC_EUD_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_EUD_AT_CBCR_ADDR, m)
#define HWIO_AOSS_CC_EUD_AT_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_EUD_AT_CBCR_ADDR,v)
#define HWIO_AOSS_CC_EUD_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_EUD_AT_CBCR_ADDR,m,v,HWIO_AOSS_CC_EUD_AT_CBCR_IN)
#define HWIO_AOSS_CC_EUD_AT_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_AOSS_CC_EUD_AT_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_AOSS_CC_EUD_AT_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_AOSS_CC_EUD_AT_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_AOSS_CC_EUD_AT_CBCR_CLK_ARES_NO_RESET_FVAL                                          0x0
#define HWIO_AOSS_CC_EUD_AT_CBCR_CLK_ARES_RESET_FVAL                                             0x1
#define HWIO_AOSS_CC_EUD_AT_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_AOSS_CC_EUD_AT_CBCR_CLK_ENABLE_SHFT                                                 0x0
#define HWIO_AOSS_CC_EUD_AT_CBCR_CLK_ENABLE_DISABLE_FVAL                                         0x0
#define HWIO_AOSS_CC_EUD_AT_CBCR_CLK_ENABLE_ENABLE_FVAL                                          0x1

#define HWIO_AOSS_CC_XO_CBCR_ADDR                                                         (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002038)
#define HWIO_AOSS_CC_XO_CBCR_OFFS                                                         (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002038)
#define HWIO_AOSS_CC_XO_CBCR_RMSK                                                         0x80000005
#define HWIO_AOSS_CC_XO_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_XO_CBCR_ADDR)
#define HWIO_AOSS_CC_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_XO_CBCR_ADDR, m)
#define HWIO_AOSS_CC_XO_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_XO_CBCR_ADDR,v)
#define HWIO_AOSS_CC_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_XO_CBCR_ADDR,m,v,HWIO_AOSS_CC_XO_CBCR_IN)
#define HWIO_AOSS_CC_XO_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_AOSS_CC_XO_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_AOSS_CC_XO_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_AOSS_CC_XO_CBCR_CLK_ARES_SHFT                                                       0x2
#define HWIO_AOSS_CC_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                              0x0
#define HWIO_AOSS_CC_XO_CBCR_CLK_ARES_RESET_FVAL                                                 0x1
#define HWIO_AOSS_CC_XO_CBCR_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_AOSS_CC_XO_CBCR_CLK_ENABLE_SHFT                                                     0x0
#define HWIO_AOSS_CC_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                             0x0
#define HWIO_AOSS_CC_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                              0x1

#define HWIO_AOSS_CC_GDSC_CBCR_ADDR                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000203c)
#define HWIO_AOSS_CC_GDSC_CBCR_OFFS                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000203c)
#define HWIO_AOSS_CC_GDSC_CBCR_RMSK                                                       0x80000005
#define HWIO_AOSS_CC_GDSC_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_GDSC_CBCR_ADDR)
#define HWIO_AOSS_CC_GDSC_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_GDSC_CBCR_ADDR, m)
#define HWIO_AOSS_CC_GDSC_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_GDSC_CBCR_ADDR,v)
#define HWIO_AOSS_CC_GDSC_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_GDSC_CBCR_ADDR,m,v,HWIO_AOSS_CC_GDSC_CBCR_IN)
#define HWIO_AOSS_CC_GDSC_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_AOSS_CC_GDSC_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_AOSS_CC_GDSC_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_AOSS_CC_GDSC_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_AOSS_CC_GDSC_CBCR_CLK_ARES_NO_RESET_FVAL                                            0x0
#define HWIO_AOSS_CC_GDSC_CBCR_CLK_ARES_RESET_FVAL                                               0x1
#define HWIO_AOSS_CC_GDSC_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_AOSS_CC_GDSC_CBCR_CLK_ENABLE_SHFT                                                   0x0
#define HWIO_AOSS_CC_GDSC_CBCR_CLK_ENABLE_DISABLE_FVAL                                           0x0
#define HWIO_AOSS_CC_GDSC_CBCR_CLK_ENABLE_ENABLE_FVAL                                            0x1

#define HWIO_AOSS_CC_TSENS_HW_CBCR_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002040)
#define HWIO_AOSS_CC_TSENS_HW_CBCR_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002040)
#define HWIO_AOSS_CC_TSENS_HW_CBCR_RMSK                                                   0x80000004
#define HWIO_AOSS_CC_TSENS_HW_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_TSENS_HW_CBCR_ADDR)
#define HWIO_AOSS_CC_TSENS_HW_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_TSENS_HW_CBCR_ADDR, m)
#define HWIO_AOSS_CC_TSENS_HW_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_TSENS_HW_CBCR_ADDR,v)
#define HWIO_AOSS_CC_TSENS_HW_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_TSENS_HW_CBCR_ADDR,m,v,HWIO_AOSS_CC_TSENS_HW_CBCR_IN)
#define HWIO_AOSS_CC_TSENS_HW_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_AOSS_CC_TSENS_HW_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_AOSS_CC_TSENS_HW_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_AOSS_CC_TSENS_HW_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_AOSS_CC_TSENS_HW_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_AOSS_CC_TSENS_HW_CBCR_CLK_ARES_RESET_FVAL                                           0x1

#define HWIO_AOSS_CC_PDC_CBCR_ADDR                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002044)
#define HWIO_AOSS_CC_PDC_CBCR_OFFS                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002044)
#define HWIO_AOSS_CC_PDC_CBCR_RMSK                                                        0x80000005
#define HWIO_AOSS_CC_PDC_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_PDC_CBCR_ADDR)
#define HWIO_AOSS_CC_PDC_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PDC_CBCR_ADDR, m)
#define HWIO_AOSS_CC_PDC_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PDC_CBCR_ADDR,v)
#define HWIO_AOSS_CC_PDC_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PDC_CBCR_ADDR,m,v,HWIO_AOSS_CC_PDC_CBCR_IN)
#define HWIO_AOSS_CC_PDC_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_AOSS_CC_PDC_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_AOSS_CC_PDC_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_AOSS_CC_PDC_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_AOSS_CC_PDC_CBCR_CLK_ARES_NO_RESET_FVAL                                             0x0
#define HWIO_AOSS_CC_PDC_CBCR_CLK_ARES_RESET_FVAL                                                0x1
#define HWIO_AOSS_CC_PDC_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_AOSS_CC_PDC_CBCR_CLK_ENABLE_SHFT                                                    0x0
#define HWIO_AOSS_CC_PDC_CBCR_CLK_ENABLE_DISABLE_FVAL                                            0x0
#define HWIO_AOSS_CC_PDC_CBCR_CLK_ENABLE_ENABLE_FVAL                                             0x1

#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_ADDR                                            (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002048)
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_OFFS                                            (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002048)
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_RMSK                                            0x80000005
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_ADDR)
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_ADDR, m)
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_ADDR,v)
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_ADDR,m,v,HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_IN)
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_CLK_OFF_BMSK                                    0x80000000
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_CLK_OFF_SHFT                                          0x1f
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_CLK_ARES_BMSK                                          0x4
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_CLK_ARES_SHFT                                          0x2
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_CLK_ARES_NO_RESET_FVAL                                 0x0
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_CLK_ARES_RESET_FVAL                                    0x1
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_CLK_ENABLE_BMSK                                        0x1
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_CLK_ENABLE_SHFT                                        0x0
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_CLK_ENABLE_DISABLE_FVAL                                0x0
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_CLK_ENABLE_ENABLE_FVAL                                 0x1

#define HWIO_AOSS_CC_AOP_CMD_RCGR_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000204c)
#define HWIO_AOSS_CC_AOP_CMD_RCGR_OFFS                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000204c)
#define HWIO_AOSS_CC_AOP_CMD_RCGR_RMSK                                                    0x80000013
#define HWIO_AOSS_CC_AOP_CMD_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_CMD_RCGR_ADDR)
#define HWIO_AOSS_CC_AOP_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_CMD_RCGR_ADDR, m)
#define HWIO_AOSS_CC_AOP_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_CMD_RCGR_ADDR,v)
#define HWIO_AOSS_CC_AOP_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_CMD_RCGR_ADDR,m,v,HWIO_AOSS_CC_AOP_CMD_RCGR_IN)
#define HWIO_AOSS_CC_AOP_CMD_RCGR_ROOT_OFF_BMSK                                           0x80000000
#define HWIO_AOSS_CC_AOP_CMD_RCGR_ROOT_OFF_SHFT                                                 0x1f
#define HWIO_AOSS_CC_AOP_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                           0x10
#define HWIO_AOSS_CC_AOP_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                            0x4
#define HWIO_AOSS_CC_AOP_CMD_RCGR_ROOT_EN_BMSK                                                   0x2
#define HWIO_AOSS_CC_AOP_CMD_RCGR_ROOT_EN_SHFT                                                   0x1
#define HWIO_AOSS_CC_AOP_CMD_RCGR_ROOT_EN_DISABLE_FVAL                                           0x0
#define HWIO_AOSS_CC_AOP_CMD_RCGR_ROOT_EN_ENABLE_FVAL                                            0x1
#define HWIO_AOSS_CC_AOP_CMD_RCGR_UPDATE_BMSK                                                    0x1
#define HWIO_AOSS_CC_AOP_CMD_RCGR_UPDATE_SHFT                                                    0x0
#define HWIO_AOSS_CC_AOP_CMD_RCGR_UPDATE_DISABLE_FVAL                                            0x0
#define HWIO_AOSS_CC_AOP_CMD_RCGR_UPDATE_ENABLE_FVAL                                             0x1

#define HWIO_AOSS_CC_AOP_CFG_RCGR_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002050)
#define HWIO_AOSS_CC_AOP_CFG_RCGR_OFFS                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002050)
#define HWIO_AOSS_CC_AOP_CFG_RCGR_RMSK                                                      0x11071f
#define HWIO_AOSS_CC_AOP_CFG_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_CFG_RCGR_ADDR)
#define HWIO_AOSS_CC_AOP_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_CFG_RCGR_ADDR, m)
#define HWIO_AOSS_CC_AOP_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_CFG_RCGR_ADDR,v)
#define HWIO_AOSS_CC_AOP_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_CFG_RCGR_ADDR,m,v,HWIO_AOSS_CC_AOP_CFG_RCGR_IN)
#define HWIO_AOSS_CC_AOP_CFG_RCGR_HW_CLK_CONTROL_BMSK                                       0x100000
#define HWIO_AOSS_CC_AOP_CFG_RCGR_HW_CLK_CONTROL_SHFT                                           0x14
#define HWIO_AOSS_CC_AOP_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL                                    0x0
#define HWIO_AOSS_CC_AOP_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL                                     0x1
#define HWIO_AOSS_CC_AOP_CFG_RCGR_RCGLITE_DISABLE_BMSK                                       0x10000
#define HWIO_AOSS_CC_AOP_CFG_RCGR_RCGLITE_DISABLE_SHFT                                          0x10
#define HWIO_AOSS_CC_AOP_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL                           0x0
#define HWIO_AOSS_CC_AOP_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL                          0x1
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_SEL_BMSK                                                 0x700
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_SEL_SHFT                                                   0x8
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_SEL_SRC0_FVAL                                              0x0
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_SEL_SRC1_FVAL                                              0x1
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_SEL_SRC2_FVAL                                              0x2
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_SEL_SRC3_FVAL                                              0x3
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_SEL_SRC4_FVAL                                              0x4
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_SEL_SRC5_FVAL                                              0x5
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_SEL_SRC6_FVAL                                              0x6
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_SEL_SRC7_FVAL                                              0x7
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_SHFT                                                   0x0
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_BYPASS_FVAL                                            0x0
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV1_FVAL                                              0x1
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV1_5_FVAL                                            0x2
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV2_FVAL                                              0x3
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV2_5_FVAL                                            0x4
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV3_FVAL                                              0x5
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV3_5_FVAL                                            0x6
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV4_FVAL                                              0x7
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV4_5_FVAL                                            0x8
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV5_FVAL                                              0x9
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV5_5_FVAL                                            0xa
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV6_FVAL                                              0xb
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV6_5_FVAL                                            0xc
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV7_FVAL                                              0xd
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV7_5_FVAL                                            0xe
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV8_FVAL                                              0xf
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV8_5_FVAL                                           0x10
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV9_FVAL                                             0x11
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV9_5_FVAL                                           0x12
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV10_FVAL                                            0x13
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV10_5_FVAL                                          0x14
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV11_FVAL                                            0x15
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV11_5_FVAL                                          0x16
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV12_FVAL                                            0x17
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV12_5_FVAL                                          0x18
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV13_FVAL                                            0x19
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV13_5_FVAL                                          0x1a
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV14_FVAL                                            0x1b
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV14_5_FVAL                                          0x1c
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV15_FVAL                                            0x1d
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV15_5_FVAL                                          0x1e
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_DIV16_FVAL                                            0x1f

#define HWIO_AOSS_CC_AOP_DIV_CDIVR_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000208c)
#define HWIO_AOSS_CC_AOP_DIV_CDIVR_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000208c)
#define HWIO_AOSS_CC_AOP_DIV_CDIVR_RMSK                                                          0xf
#define HWIO_AOSS_CC_AOP_DIV_CDIVR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_DIV_CDIVR_ADDR)
#define HWIO_AOSS_CC_AOP_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_DIV_CDIVR_ADDR, m)
#define HWIO_AOSS_CC_AOP_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_DIV_CDIVR_ADDR,v)
#define HWIO_AOSS_CC_AOP_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_DIV_CDIVR_ADDR,m,v,HWIO_AOSS_CC_AOP_DIV_CDIVR_IN)
#define HWIO_AOSS_CC_AOP_DIV_CDIVR_CLK_DIV_BMSK                                                  0xf
#define HWIO_AOSS_CC_AOP_DIV_CDIVR_CLK_DIV_SHFT                                                  0x0

#define HWIO_AOSS_CC_RO_CMD_RCGR_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002090)
#define HWIO_AOSS_CC_RO_CMD_RCGR_OFFS                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002090)
#define HWIO_AOSS_CC_RO_CMD_RCGR_RMSK                                                     0x80000013
#define HWIO_AOSS_CC_RO_CMD_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_RO_CMD_RCGR_ADDR)
#define HWIO_AOSS_CC_RO_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RO_CMD_RCGR_ADDR, m)
#define HWIO_AOSS_CC_RO_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RO_CMD_RCGR_ADDR,v)
#define HWIO_AOSS_CC_RO_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RO_CMD_RCGR_ADDR,m,v,HWIO_AOSS_CC_RO_CMD_RCGR_IN)
#define HWIO_AOSS_CC_RO_CMD_RCGR_ROOT_OFF_BMSK                                            0x80000000
#define HWIO_AOSS_CC_RO_CMD_RCGR_ROOT_OFF_SHFT                                                  0x1f
#define HWIO_AOSS_CC_RO_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                            0x10
#define HWIO_AOSS_CC_RO_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                             0x4
#define HWIO_AOSS_CC_RO_CMD_RCGR_ROOT_EN_BMSK                                                    0x2
#define HWIO_AOSS_CC_RO_CMD_RCGR_ROOT_EN_SHFT                                                    0x1
#define HWIO_AOSS_CC_RO_CMD_RCGR_ROOT_EN_DISABLE_FVAL                                            0x0
#define HWIO_AOSS_CC_RO_CMD_RCGR_ROOT_EN_ENABLE_FVAL                                             0x1
#define HWIO_AOSS_CC_RO_CMD_RCGR_UPDATE_BMSK                                                     0x1
#define HWIO_AOSS_CC_RO_CMD_RCGR_UPDATE_SHFT                                                     0x0
#define HWIO_AOSS_CC_RO_CMD_RCGR_UPDATE_DISABLE_FVAL                                             0x0
#define HWIO_AOSS_CC_RO_CMD_RCGR_UPDATE_ENABLE_FVAL                                              0x1

#define HWIO_AOSS_CC_RO_CFG_RCGR_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002094)
#define HWIO_AOSS_CC_RO_CFG_RCGR_OFFS                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002094)
#define HWIO_AOSS_CC_RO_CFG_RCGR_RMSK                                                       0x11071f
#define HWIO_AOSS_CC_RO_CFG_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_RO_CFG_RCGR_ADDR)
#define HWIO_AOSS_CC_RO_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RO_CFG_RCGR_ADDR, m)
#define HWIO_AOSS_CC_RO_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RO_CFG_RCGR_ADDR,v)
#define HWIO_AOSS_CC_RO_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RO_CFG_RCGR_ADDR,m,v,HWIO_AOSS_CC_RO_CFG_RCGR_IN)
#define HWIO_AOSS_CC_RO_CFG_RCGR_HW_CLK_CONTROL_BMSK                                        0x100000
#define HWIO_AOSS_CC_RO_CFG_RCGR_HW_CLK_CONTROL_SHFT                                            0x14
#define HWIO_AOSS_CC_RO_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL                                     0x0
#define HWIO_AOSS_CC_RO_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL                                      0x1
#define HWIO_AOSS_CC_RO_CFG_RCGR_RCGLITE_DISABLE_BMSK                                        0x10000
#define HWIO_AOSS_CC_RO_CFG_RCGR_RCGLITE_DISABLE_SHFT                                           0x10
#define HWIO_AOSS_CC_RO_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL                            0x0
#define HWIO_AOSS_CC_RO_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL                           0x1
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_SEL_BMSK                                                  0x700
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_SEL_SHFT                                                    0x8
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_SEL_SRC0_FVAL                                               0x0
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_SEL_SRC1_FVAL                                               0x1
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_SEL_SRC2_FVAL                                               0x2
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_SEL_SRC3_FVAL                                               0x3
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_SEL_SRC4_FVAL                                               0x4
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_SEL_SRC5_FVAL                                               0x5
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_SEL_SRC6_FVAL                                               0x6
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_SEL_SRC7_FVAL                                               0x7
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_BMSK                                                   0x1f
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_SHFT                                                    0x0
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_BYPASS_FVAL                                             0x0
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV1_FVAL                                               0x1
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV1_5_FVAL                                             0x2
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV2_FVAL                                               0x3
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV2_5_FVAL                                             0x4
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV3_FVAL                                               0x5
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV3_5_FVAL                                             0x6
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV4_FVAL                                               0x7
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV4_5_FVAL                                             0x8
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV5_FVAL                                               0x9
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV5_5_FVAL                                             0xa
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV6_FVAL                                               0xb
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV6_5_FVAL                                             0xc
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV7_FVAL                                               0xd
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV7_5_FVAL                                             0xe
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV8_FVAL                                               0xf
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV8_5_FVAL                                            0x10
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV9_FVAL                                              0x11
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV9_5_FVAL                                            0x12
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV10_FVAL                                             0x13
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV10_5_FVAL                                           0x14
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV11_FVAL                                             0x15
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV11_5_FVAL                                           0x16
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV12_FVAL                                             0x17
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV12_5_FVAL                                           0x18
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV13_FVAL                                             0x19
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV13_5_FVAL                                           0x1a
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV14_FVAL                                             0x1b
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV14_5_FVAL                                           0x1c
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV15_FVAL                                             0x1d
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV15_5_FVAL                                           0x1e
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_DIV16_FVAL                                             0x1f

#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000020d0)
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x000020d0)
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_RMSK                                                 0x80000013
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ADDR)
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ADDR, m)
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ADDR,v)
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ADDR,m,v,HWIO_AOSS_CC_EUD_AT_CMD_RCGR_IN)
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ROOT_OFF_BMSK                                        0x80000000
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ROOT_OFF_SHFT                                              0x1f
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                        0x10
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                         0x4
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ROOT_EN_BMSK                                                0x2
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ROOT_EN_SHFT                                                0x1
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ROOT_EN_DISABLE_FVAL                                        0x0
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ROOT_EN_ENABLE_FVAL                                         0x1
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_UPDATE_BMSK                                                 0x1
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_UPDATE_SHFT                                                 0x0
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_UPDATE_DISABLE_FVAL                                         0x0
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_UPDATE_ENABLE_FVAL                                          0x1

#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000020d4)
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x000020d4)
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_RMSK                                                   0x11071f
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_EUD_AT_CFG_RCGR_ADDR)
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_EUD_AT_CFG_RCGR_ADDR, m)
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_EUD_AT_CFG_RCGR_ADDR,v)
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_EUD_AT_CFG_RCGR_ADDR,m,v,HWIO_AOSS_CC_EUD_AT_CFG_RCGR_IN)
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_HW_CLK_CONTROL_BMSK                                    0x100000
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_HW_CLK_CONTROL_SHFT                                        0x14
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL                                 0x0
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL                                  0x1
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_RCGLITE_DISABLE_BMSK                                    0x10000
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_RCGLITE_DISABLE_SHFT                                       0x10
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL                        0x0
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL                       0x1
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_SEL_BMSK                                              0x700
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_SEL_SHFT                                                0x8
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_SEL_SRC0_FVAL                                           0x0
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_SEL_SRC1_FVAL                                           0x1
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_SEL_SRC2_FVAL                                           0x2
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_SEL_SRC3_FVAL                                           0x3
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_SEL_SRC4_FVAL                                           0x4
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_SEL_SRC5_FVAL                                           0x5
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_SEL_SRC6_FVAL                                           0x6
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_SEL_SRC7_FVAL                                           0x7
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_BMSK                                               0x1f
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_SHFT                                                0x0
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_BYPASS_FVAL                                         0x0
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV1_FVAL                                           0x1
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV1_5_FVAL                                         0x2
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV2_FVAL                                           0x3
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV2_5_FVAL                                         0x4
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV3_FVAL                                           0x5
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV3_5_FVAL                                         0x6
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV4_FVAL                                           0x7
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV4_5_FVAL                                         0x8
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV5_FVAL                                           0x9
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV5_5_FVAL                                         0xa
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV6_FVAL                                           0xb
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV6_5_FVAL                                         0xc
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV7_FVAL                                           0xd
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV7_5_FVAL                                         0xe
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV8_FVAL                                           0xf
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV8_5_FVAL                                        0x10
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV9_FVAL                                          0x11
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV9_5_FVAL                                        0x12
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV10_FVAL                                         0x13
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV10_5_FVAL                                       0x14
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV11_FVAL                                         0x15
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV11_5_FVAL                                       0x16
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV12_FVAL                                         0x17
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV12_5_FVAL                                       0x18
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV13_FVAL                                         0x19
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV13_5_FVAL                                       0x1a
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV14_FVAL                                         0x1b
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV14_5_FVAL                                       0x1c
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV15_FVAL                                         0x1d
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV15_5_FVAL                                       0x1e
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_DIV16_FVAL                                         0x1f

#define HWIO_AOSS_CC_IBI_BCR_ADDR                                                         (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002110)
#define HWIO_AOSS_CC_IBI_BCR_OFFS                                                         (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002110)
#define HWIO_AOSS_CC_IBI_BCR_RMSK                                                                0x1
#define HWIO_AOSS_CC_IBI_BCR_IN          \
        in_dword(HWIO_AOSS_CC_IBI_BCR_ADDR)
#define HWIO_AOSS_CC_IBI_BCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_IBI_BCR_ADDR, m)
#define HWIO_AOSS_CC_IBI_BCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_IBI_BCR_ADDR,v)
#define HWIO_AOSS_CC_IBI_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_IBI_BCR_ADDR,m,v,HWIO_AOSS_CC_IBI_BCR_IN)
#define HWIO_AOSS_CC_IBI_BCR_BLK_ARES_BMSK                                                       0x1
#define HWIO_AOSS_CC_IBI_BCR_BLK_ARES_SHFT                                                       0x0
#define HWIO_AOSS_CC_IBI_BCR_BLK_ARES_DISABLE_FVAL                                               0x0
#define HWIO_AOSS_CC_IBI_BCR_BLK_ARES_ENABLE_FVAL                                                0x1

#define HWIO_AOSS_CC_IBI_CMD_RCGR_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002114)
#define HWIO_AOSS_CC_IBI_CMD_RCGR_OFFS                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002114)
#define HWIO_AOSS_CC_IBI_CMD_RCGR_RMSK                                                    0x80000013
#define HWIO_AOSS_CC_IBI_CMD_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_IBI_CMD_RCGR_ADDR)
#define HWIO_AOSS_CC_IBI_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_IBI_CMD_RCGR_ADDR, m)
#define HWIO_AOSS_CC_IBI_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_IBI_CMD_RCGR_ADDR,v)
#define HWIO_AOSS_CC_IBI_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_IBI_CMD_RCGR_ADDR,m,v,HWIO_AOSS_CC_IBI_CMD_RCGR_IN)
#define HWIO_AOSS_CC_IBI_CMD_RCGR_ROOT_OFF_BMSK                                           0x80000000
#define HWIO_AOSS_CC_IBI_CMD_RCGR_ROOT_OFF_SHFT                                                 0x1f
#define HWIO_AOSS_CC_IBI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                           0x10
#define HWIO_AOSS_CC_IBI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                            0x4
#define HWIO_AOSS_CC_IBI_CMD_RCGR_ROOT_EN_BMSK                                                   0x2
#define HWIO_AOSS_CC_IBI_CMD_RCGR_ROOT_EN_SHFT                                                   0x1
#define HWIO_AOSS_CC_IBI_CMD_RCGR_ROOT_EN_DISABLE_FVAL                                           0x0
#define HWIO_AOSS_CC_IBI_CMD_RCGR_ROOT_EN_ENABLE_FVAL                                            0x1
#define HWIO_AOSS_CC_IBI_CMD_RCGR_UPDATE_BMSK                                                    0x1
#define HWIO_AOSS_CC_IBI_CMD_RCGR_UPDATE_SHFT                                                    0x0
#define HWIO_AOSS_CC_IBI_CMD_RCGR_UPDATE_DISABLE_FVAL                                            0x0
#define HWIO_AOSS_CC_IBI_CMD_RCGR_UPDATE_ENABLE_FVAL                                             0x1

#define HWIO_AOSS_CC_IBI_CFG_RCGR_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002118)
#define HWIO_AOSS_CC_IBI_CFG_RCGR_OFFS                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002118)
#define HWIO_AOSS_CC_IBI_CFG_RCGR_RMSK                                                      0x11071f
#define HWIO_AOSS_CC_IBI_CFG_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_IBI_CFG_RCGR_ADDR)
#define HWIO_AOSS_CC_IBI_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_IBI_CFG_RCGR_ADDR, m)
#define HWIO_AOSS_CC_IBI_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_IBI_CFG_RCGR_ADDR,v)
#define HWIO_AOSS_CC_IBI_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_IBI_CFG_RCGR_ADDR,m,v,HWIO_AOSS_CC_IBI_CFG_RCGR_IN)
#define HWIO_AOSS_CC_IBI_CFG_RCGR_HW_CLK_CONTROL_BMSK                                       0x100000
#define HWIO_AOSS_CC_IBI_CFG_RCGR_HW_CLK_CONTROL_SHFT                                           0x14
#define HWIO_AOSS_CC_IBI_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL                                    0x0
#define HWIO_AOSS_CC_IBI_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL                                     0x1
#define HWIO_AOSS_CC_IBI_CFG_RCGR_RCGLITE_DISABLE_BMSK                                       0x10000
#define HWIO_AOSS_CC_IBI_CFG_RCGR_RCGLITE_DISABLE_SHFT                                          0x10
#define HWIO_AOSS_CC_IBI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL                           0x0
#define HWIO_AOSS_CC_IBI_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL                          0x1
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_SEL_BMSK                                                 0x700
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_SEL_SHFT                                                   0x8
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_SEL_SRC0_FVAL                                              0x0
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_SEL_SRC1_FVAL                                              0x1
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_SEL_SRC2_FVAL                                              0x2
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_SEL_SRC3_FVAL                                              0x3
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_SEL_SRC4_FVAL                                              0x4
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_SEL_SRC5_FVAL                                              0x5
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_SEL_SRC6_FVAL                                              0x6
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_SEL_SRC7_FVAL                                              0x7
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_SHFT                                                   0x0
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_BYPASS_FVAL                                            0x0
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV1_FVAL                                              0x1
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV1_5_FVAL                                            0x2
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV2_FVAL                                              0x3
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV2_5_FVAL                                            0x4
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV3_FVAL                                              0x5
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV3_5_FVAL                                            0x6
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV4_FVAL                                              0x7
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV4_5_FVAL                                            0x8
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV5_FVAL                                              0x9
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV5_5_FVAL                                            0xa
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV6_FVAL                                              0xb
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV6_5_FVAL                                            0xc
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV7_FVAL                                              0xd
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV7_5_FVAL                                            0xe
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV8_FVAL                                              0xf
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV8_5_FVAL                                           0x10
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV9_FVAL                                             0x11
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV9_5_FVAL                                           0x12
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV10_FVAL                                            0x13
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV10_5_FVAL                                          0x14
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV11_FVAL                                            0x15
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV11_5_FVAL                                          0x16
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV12_FVAL                                            0x17
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV12_5_FVAL                                          0x18
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV13_FVAL                                            0x19
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV13_5_FVAL                                          0x1a
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV14_FVAL                                            0x1b
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV14_5_FVAL                                          0x1c
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV15_FVAL                                            0x1d
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV15_5_FVAL                                          0x1e
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_DIV16_FVAL                                            0x1f

#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002154)
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_OFFS                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002154)
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_RMSK                                                  0x80000005
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_IBI_CTRL0_CBCR_ADDR)
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_IBI_CTRL0_CBCR_ADDR, m)
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_IBI_CTRL0_CBCR_ADDR,v)
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_IBI_CTRL0_CBCR_ADDR,m,v,HWIO_AOSS_CC_IBI_CTRL0_CBCR_IN)
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_CLK_ARES_NO_RESET_FVAL                                       0x0
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_CLK_ARES_RESET_FVAL                                          0x1
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_CLK_ENABLE_SHFT                                              0x0
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_CLK_ENABLE_DISABLE_FVAL                                      0x0
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_CLK_ENABLE_ENABLE_FVAL                                       0x1

#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002158)
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_OFFS                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002158)
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_RMSK                                                  0x80000005
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_IBI_CTRL1_CBCR_ADDR)
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_IBI_CTRL1_CBCR_ADDR, m)
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_IBI_CTRL1_CBCR_ADDR,v)
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_IBI_CTRL1_CBCR_ADDR,m,v,HWIO_AOSS_CC_IBI_CTRL1_CBCR_IN)
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_CLK_ARES_NO_RESET_FVAL                                       0x0
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_CLK_ARES_RESET_FVAL                                          0x1
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_CLK_ENABLE_SHFT                                              0x0
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_CLK_ENABLE_DISABLE_FVAL                                      0x0
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_CLK_ENABLE_ENABLE_FVAL                                       0x1

#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000215c)
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_OFFS                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000215c)
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_RMSK                                                  0x80000005
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_IBI_CTRL2_CBCR_ADDR)
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_IBI_CTRL2_CBCR_ADDR, m)
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_IBI_CTRL2_CBCR_ADDR,v)
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_IBI_CTRL2_CBCR_ADDR,m,v,HWIO_AOSS_CC_IBI_CTRL2_CBCR_IN)
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_CLK_ARES_NO_RESET_FVAL                                       0x0
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_CLK_ARES_RESET_FVAL                                          0x1
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_CLK_ENABLE_SHFT                                              0x0
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_CLK_ENABLE_DISABLE_FVAL                                      0x0
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_CLK_ENABLE_ENABLE_FVAL                                       0x1

#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002160)
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_OFFS                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002160)
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_RMSK                                                  0x80000005
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_IBI_CTRL3_CBCR_ADDR)
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_IBI_CTRL3_CBCR_ADDR, m)
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_IBI_CTRL3_CBCR_ADDR,v)
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_IBI_CTRL3_CBCR_ADDR,m,v,HWIO_AOSS_CC_IBI_CTRL3_CBCR_IN)
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_CLK_ARES_NO_RESET_FVAL                                       0x0
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_CLK_ARES_RESET_FVAL                                          0x1
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_CLK_ENABLE_SHFT                                              0x0
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_CLK_ENABLE_DISABLE_FVAL                                      0x0
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_CLK_ENABLE_ENABLE_FVAL                                       0x1

#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000021a8)
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_OFFS                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x000021a8)
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_RMSK                                                  0x80000013
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_SLEEP_CMD_RCGR_ADDR)
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SLEEP_CMD_RCGR_ADDR, m)
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SLEEP_CMD_RCGR_ADDR,v)
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SLEEP_CMD_RCGR_ADDR,m,v,HWIO_AOSS_CC_SLEEP_CMD_RCGR_IN)
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_ROOT_OFF_BMSK                                         0x80000000
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_ROOT_OFF_SHFT                                               0x1f
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                         0x10
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                          0x4
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_ROOT_EN_BMSK                                                 0x2
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_ROOT_EN_SHFT                                                 0x1
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_ROOT_EN_DISABLE_FVAL                                         0x0
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_ROOT_EN_ENABLE_FVAL                                          0x1
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_UPDATE_BMSK                                                  0x1
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_UPDATE_SHFT                                                  0x0
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_UPDATE_DISABLE_FVAL                                          0x0
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_UPDATE_ENABLE_FVAL                                           0x1

#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000021ac)
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_OFFS                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x000021ac)
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_RMSK                                                    0x11071f
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_SLEEP_CFG_RCGR_ADDR)
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SLEEP_CFG_RCGR_ADDR, m)
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SLEEP_CFG_RCGR_ADDR,v)
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SLEEP_CFG_RCGR_ADDR,m,v,HWIO_AOSS_CC_SLEEP_CFG_RCGR_IN)
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_HW_CLK_CONTROL_BMSK                                     0x100000
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_HW_CLK_CONTROL_SHFT                                         0x14
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL                                  0x0
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL                                   0x1
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_RCGLITE_DISABLE_BMSK                                     0x10000
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_RCGLITE_DISABLE_SHFT                                        0x10
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL                         0x0
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL                        0x1
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_SEL_BMSK                                               0x700
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_SEL_SHFT                                                 0x8
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_SEL_SRC0_FVAL                                            0x0
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_SEL_SRC1_FVAL                                            0x1
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_SEL_SRC2_FVAL                                            0x2
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_SEL_SRC3_FVAL                                            0x3
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_SEL_SRC4_FVAL                                            0x4
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_SEL_SRC5_FVAL                                            0x5
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_SEL_SRC6_FVAL                                            0x6
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_SEL_SRC7_FVAL                                            0x7
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_BMSK                                                0x1f
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_SHFT                                                 0x0
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_BYPASS_FVAL                                          0x0
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV1_FVAL                                            0x1
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV1_5_FVAL                                          0x2
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV2_FVAL                                            0x3
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV2_5_FVAL                                          0x4
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV3_FVAL                                            0x5
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV3_5_FVAL                                          0x6
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV4_FVAL                                            0x7
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV4_5_FVAL                                          0x8
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV5_FVAL                                            0x9
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV5_5_FVAL                                          0xa
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV6_FVAL                                            0xb
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV6_5_FVAL                                          0xc
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV7_FVAL                                            0xd
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV7_5_FVAL                                          0xe
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV8_FVAL                                            0xf
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV8_5_FVAL                                         0x10
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV9_FVAL                                           0x11
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV9_5_FVAL                                         0x12
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV10_FVAL                                          0x13
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV10_5_FVAL                                        0x14
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV11_FVAL                                          0x15
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV11_5_FVAL                                        0x16
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV12_FVAL                                          0x17
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV12_5_FVAL                                        0x18
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV13_FVAL                                          0x19
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV13_5_FVAL                                        0x1a
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV14_FVAL                                          0x1b
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV14_5_FVAL                                        0x1c
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV15_FVAL                                          0x1d
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV15_5_FVAL                                        0x1e
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_DIV16_FVAL                                          0x1f

#define HWIO_AOSS_CC_SLEEP_CBCR_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000021e8)
#define HWIO_AOSS_CC_SLEEP_CBCR_OFFS                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x000021e8)
#define HWIO_AOSS_CC_SLEEP_CBCR_RMSK                                                      0x80000005
#define HWIO_AOSS_CC_SLEEP_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SLEEP_CBCR_ADDR)
#define HWIO_AOSS_CC_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SLEEP_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SLEEP_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SLEEP_CBCR_ADDR,m,v,HWIO_AOSS_CC_SLEEP_CBCR_IN)
#define HWIO_AOSS_CC_SLEEP_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_AOSS_CC_SLEEP_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_AOSS_CC_SLEEP_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_AOSS_CC_SLEEP_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_AOSS_CC_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL                                           0x0
#define HWIO_AOSS_CC_SLEEP_CBCR_CLK_ARES_RESET_FVAL                                              0x1
#define HWIO_AOSS_CC_SLEEP_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_AOSS_CC_SLEEP_CBCR_CLK_ENABLE_SHFT                                                  0x0
#define HWIO_AOSS_CC_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL                                          0x0
#define HWIO_AOSS_CC_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL                                           0x1

#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002228)
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002228)
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_RMSK                                                 0x80000005
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_PERIPH_SLP_CBCR_ADDR)
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PERIPH_SLP_CBCR_ADDR, m)
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PERIPH_SLP_CBCR_ADDR,v)
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PERIPH_SLP_CBCR_ADDR,m,v,HWIO_AOSS_CC_PERIPH_SLP_CBCR_IN)
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_CLK_OFF_BMSK                                         0x80000000
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_CLK_OFF_SHFT                                               0x1f
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_CLK_ARES_BMSK                                               0x4
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_CLK_ARES_SHFT                                               0x2
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_CLK_ARES_NO_RESET_FVAL                                      0x0
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_CLK_ARES_RESET_FVAL                                         0x1
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_CLK_ENABLE_BMSK                                             0x1
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_CLK_ENABLE_SHFT                                             0x0
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_CLK_ENABLE_DISABLE_FVAL                                     0x0
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_CLK_ENABLE_ENABLE_FVAL                                      0x1

#define HWIO_AOSS_CC_SWAO_BCR_ADDR                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000222c)
#define HWIO_AOSS_CC_SWAO_BCR_OFFS                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000222c)
#define HWIO_AOSS_CC_SWAO_BCR_RMSK                                                               0x1
#define HWIO_AOSS_CC_SWAO_BCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_BCR_ADDR)
#define HWIO_AOSS_CC_SWAO_BCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_BCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_BCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_BCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_BCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_BCR_IN)
#define HWIO_AOSS_CC_SWAO_BCR_BLK_ARES_BMSK                                                      0x1
#define HWIO_AOSS_CC_SWAO_BCR_BLK_ARES_SHFT                                                      0x0
#define HWIO_AOSS_CC_SWAO_BCR_BLK_ARES_DISABLE_FVAL                                              0x0
#define HWIO_AOSS_CC_SWAO_BCR_BLK_ARES_ENABLE_FVAL                                               0x1

#define HWIO_AOSS_CC_SWAO_GDSCR_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002230)
#define HWIO_AOSS_CC_SWAO_GDSCR_OFFS                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002230)
#define HWIO_AOSS_CC_SWAO_GDSCR_RMSK                                                      0xf8ffffff
#define HWIO_AOSS_CC_SWAO_GDSCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_GDSCR_ADDR)
#define HWIO_AOSS_CC_SWAO_GDSCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_GDSCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_GDSCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_GDSCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_GDSCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_GDSCR_IN)
#define HWIO_AOSS_CC_SWAO_GDSCR_PWR_ON_BMSK                                               0x80000000
#define HWIO_AOSS_CC_SWAO_GDSCR_PWR_ON_SHFT                                                     0x1f
#define HWIO_AOSS_CC_SWAO_GDSCR_GDSC_STATE_BMSK                                           0x78000000
#define HWIO_AOSS_CC_SWAO_GDSCR_GDSC_STATE_SHFT                                                 0x1b
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_REST_WAIT_BMSK                                           0xf00000
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_REST_WAIT_SHFT                                               0x14
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_FEW_WAIT_BMSK                                             0xf0000
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_FEW_WAIT_SHFT                                                0x10
#define HWIO_AOSS_CC_SWAO_GDSCR_CLK_DIS_WAIT_BMSK                                             0xf000
#define HWIO_AOSS_CC_SWAO_GDSCR_CLK_DIS_WAIT_SHFT                                                0xc
#define HWIO_AOSS_CC_SWAO_GDSCR_RETAIN_FF_ENABLE_BMSK                                          0x800
#define HWIO_AOSS_CC_SWAO_GDSCR_RETAIN_FF_ENABLE_SHFT                                            0xb
#define HWIO_AOSS_CC_SWAO_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_AOSS_CC_SWAO_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL                                     0x1
#define HWIO_AOSS_CC_SWAO_GDSCR_RESTORE_BMSK                                                   0x400
#define HWIO_AOSS_CC_SWAO_GDSCR_RESTORE_SHFT                                                     0xa
#define HWIO_AOSS_CC_SWAO_GDSCR_RESTORE_DISABLE_FVAL                                             0x0
#define HWIO_AOSS_CC_SWAO_GDSCR_RESTORE_ENABLE_FVAL                                              0x1
#define HWIO_AOSS_CC_SWAO_GDSCR_SAVE_BMSK                                                      0x200
#define HWIO_AOSS_CC_SWAO_GDSCR_SAVE_SHFT                                                        0x9
#define HWIO_AOSS_CC_SWAO_GDSCR_SAVE_DISABLE_FVAL                                                0x0
#define HWIO_AOSS_CC_SWAO_GDSCR_SAVE_ENABLE_FVAL                                                 0x1
#define HWIO_AOSS_CC_SWAO_GDSCR_RETAIN_BMSK                                                    0x100
#define HWIO_AOSS_CC_SWAO_GDSCR_RETAIN_SHFT                                                      0x8
#define HWIO_AOSS_CC_SWAO_GDSCR_RETAIN_DISABLE_FVAL                                              0x0
#define HWIO_AOSS_CC_SWAO_GDSCR_RETAIN_ENABLE_FVAL                                               0x1
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_REST_BMSK                                                    0x80
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_REST_SHFT                                                     0x7
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_REST_DISABLE_FVAL                                             0x0
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_REST_ENABLE_FVAL                                              0x1
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_FEW_BMSK                                                     0x40
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_FEW_SHFT                                                      0x6
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_FEW_DISABLE_FVAL                                              0x0
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_FEW_ENABLE_FVAL                                               0x1
#define HWIO_AOSS_CC_SWAO_GDSCR_CLAMP_IO_BMSK                                                   0x20
#define HWIO_AOSS_CC_SWAO_GDSCR_CLAMP_IO_SHFT                                                    0x5
#define HWIO_AOSS_CC_SWAO_GDSCR_CLAMP_IO_DISABLE_FVAL                                            0x0
#define HWIO_AOSS_CC_SWAO_GDSCR_CLAMP_IO_ENABLE_FVAL                                             0x1
#define HWIO_AOSS_CC_SWAO_GDSCR_CLK_DISABLE_BMSK                                                0x10
#define HWIO_AOSS_CC_SWAO_GDSCR_CLK_DISABLE_SHFT                                                 0x4
#define HWIO_AOSS_CC_SWAO_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL                                 0x0
#define HWIO_AOSS_CC_SWAO_GDSCR_CLK_DISABLE_CLK_DISABLE_FVAL                                     0x1
#define HWIO_AOSS_CC_SWAO_GDSCR_PD_ARES_BMSK                                                     0x8
#define HWIO_AOSS_CC_SWAO_GDSCR_PD_ARES_SHFT                                                     0x3
#define HWIO_AOSS_CC_SWAO_GDSCR_PD_ARES_NO_RESET_FVAL                                            0x0
#define HWIO_AOSS_CC_SWAO_GDSCR_PD_ARES_RESET_FVAL                                               0x1
#define HWIO_AOSS_CC_SWAO_GDSCR_SW_OVERRIDE_BMSK                                                 0x4
#define HWIO_AOSS_CC_SWAO_GDSCR_SW_OVERRIDE_SHFT                                                 0x2
#define HWIO_AOSS_CC_SWAO_GDSCR_SW_OVERRIDE_DISABLE_FVAL                                         0x0
#define HWIO_AOSS_CC_SWAO_GDSCR_SW_OVERRIDE_ENABLE_FVAL                                          0x1
#define HWIO_AOSS_CC_SWAO_GDSCR_HW_CONTROL_BMSK                                                  0x2
#define HWIO_AOSS_CC_SWAO_GDSCR_HW_CONTROL_SHFT                                                  0x1
#define HWIO_AOSS_CC_SWAO_GDSCR_HW_CONTROL_DISABLE_FVAL                                          0x0
#define HWIO_AOSS_CC_SWAO_GDSCR_HW_CONTROL_ENABLE_FVAL                                           0x1
#define HWIO_AOSS_CC_SWAO_GDSCR_SW_COLLAPSE_BMSK                                                 0x1
#define HWIO_AOSS_CC_SWAO_GDSCR_SW_COLLAPSE_SHFT                                                 0x0
#define HWIO_AOSS_CC_SWAO_GDSCR_SW_COLLAPSE_DISABLE_FVAL                                         0x0
#define HWIO_AOSS_CC_SWAO_GDSCR_SW_COLLAPSE_ENABLE_FVAL                                          0x1

#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002234)
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_OFFS                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002234)
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_RMSK                                                  0xffffffff
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_CFG_GDSCR_ADDR)
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_CFG_GDSCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_CFG_GDSCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_CFG_GDSCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_CFG_GDSCR_IN)
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_SPARE_CTRL_IN_BMSK                               0xf0000000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_SPARE_CTRL_IN_SHFT                                     0x1c
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK                               0xc000000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT                                    0x1a
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK                                0x2000000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT                                     0x19
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PWR_UP_START_BMSK                                 0x1000000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PWR_UP_START_SHFT                                      0x18
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK                          0xf00000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT                              0x14
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                             0x80000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                                0x13
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK                                 0x40000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT                                    0x12
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK                                 0x20000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT                                    0x11
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK                              0x10000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT                                 0x10
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                             0x8000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                                0xf
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                            0x7800
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                               0xb
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK                                    0x400
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT                                      0xa
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                             0x200
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                               0x9
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                             0x100
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                               0x8
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                                 0x80
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                                  0x7
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                        0x60
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                         0x5
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                                  0x10
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                                   0x4
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                            0x8
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                            0x3
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                          0x4
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                          0x2
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                              0x2
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                              0x1
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                           0x1
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                           0x0

#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002238)
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002238)
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_RMSK                                                    0x1ffff
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_CFG2_GDSCR_ADDR)
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_CFG2_GDSCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_CFG2_GDSCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_CFG2_GDSCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_CFG2_GDSCR_IN)
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK                                  0x10000
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT                                     0x10
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK                                      0xf000
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT                                         0xc
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                               0xf00
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                                 0x8
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                                  0xf0
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                                   0x4
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                                    0xf
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                                    0x0

#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_ADDR                                            (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000223c)
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_OFFS                                            (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000223c)
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_RMSK                                            0x80000005
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_ADDR)
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_IN)
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_CLK_OFF_BMSK                                    0x80000000
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_CLK_OFF_SHFT                                          0x1f
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_CLK_ARES_BMSK                                          0x4
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_CLK_ARES_SHFT                                          0x2
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_CLK_ARES_NO_RESET_FVAL                                 0x0
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_CLK_ARES_RESET_FVAL                                    0x1
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_CLK_ENABLE_BMSK                                        0x1
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_CLK_ENABLE_SHFT                                        0x0
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_CLK_ENABLE_DISABLE_FVAL                                0x0
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_CLK_ENABLE_ENABLE_FVAL                                 0x1

#define HWIO_AOSS_CC_SWAO_CBCR_ADDR                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002240)
#define HWIO_AOSS_CC_SWAO_CBCR_OFFS                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002240)
#define HWIO_AOSS_CC_SWAO_CBCR_RMSK                                                       0x80000005
#define HWIO_AOSS_CC_SWAO_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_CBCR_ADDR)
#define HWIO_AOSS_CC_SWAO_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_CBCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_CBCR_IN)
#define HWIO_AOSS_CC_SWAO_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_AOSS_CC_SWAO_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_AOSS_CC_SWAO_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_AOSS_CC_SWAO_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_AOSS_CC_SWAO_CBCR_CLK_ARES_NO_RESET_FVAL                                            0x0
#define HWIO_AOSS_CC_SWAO_CBCR_CLK_ARES_RESET_FVAL                                               0x1
#define HWIO_AOSS_CC_SWAO_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_AOSS_CC_SWAO_CBCR_CLK_ENABLE_SHFT                                                   0x0
#define HWIO_AOSS_CC_SWAO_CBCR_CLK_ENABLE_DISABLE_FVAL                                           0x0
#define HWIO_AOSS_CC_SWAO_CBCR_CLK_ENABLE_ENABLE_FVAL                                            0x1

#define HWIO_AOSS_CC_SWAO_AO_CBCR_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002244)
#define HWIO_AOSS_CC_SWAO_AO_CBCR_OFFS                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002244)
#define HWIO_AOSS_CC_SWAO_AO_CBCR_RMSK                                                    0x80000005
#define HWIO_AOSS_CC_SWAO_AO_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_AO_CBCR_ADDR)
#define HWIO_AOSS_CC_SWAO_AO_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_AO_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_AO_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_AO_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_AO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_AO_CBCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_AO_CBCR_IN)
#define HWIO_AOSS_CC_SWAO_AO_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_AOSS_CC_SWAO_AO_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_AOSS_CC_SWAO_AO_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_AOSS_CC_SWAO_AO_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_AOSS_CC_SWAO_AO_CBCR_CLK_ARES_NO_RESET_FVAL                                         0x0
#define HWIO_AOSS_CC_SWAO_AO_CBCR_CLK_ARES_RESET_FVAL                                            0x1
#define HWIO_AOSS_CC_SWAO_AO_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_AOSS_CC_SWAO_AO_CBCR_CLK_ENABLE_SHFT                                                0x0
#define HWIO_AOSS_CC_SWAO_AO_CBCR_CLK_ENABLE_DISABLE_FVAL                                        0x0
#define HWIO_AOSS_CC_SWAO_AO_CBCR_CLK_ENABLE_ENABLE_FVAL                                         0x1

#define HWIO_AOSS_CC_SWAO_MEM_CBCR_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002248)
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002248)
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_RMSK                                                   0x80007ff5
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_MEM_CBCR_ADDR)
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_MEM_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_MEM_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_MEM_CBCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_MEM_CBCR_IN)
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_CORE_ON_BMSK                                     0x4000
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_CORE_ON_SHFT                                        0xe
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL                          0x0
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL                           0x1
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                   0x2000
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                      0xd
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL                        0x0
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL                         0x1
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                  0x1000
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                     0xc
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL                       0x0
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL                        0x1
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_BMSK                                                 0xf00
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_SHFT                                                   0x8
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_CLOCK0_FVAL                                            0x0
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_CLOCK1_FVAL                                            0x1
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_CLOCK2_FVAL                                            0x2
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_CLOCK3_FVAL                                            0x3
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_CLOCK4_FVAL                                            0x4
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_CLOCK5_FVAL                                            0x5
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_CLOCK6_FVAL                                            0x6
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_CLOCK7_FVAL                                            0x7
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_CLOCK8_FVAL                                            0x8
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_CLOCK9_FVAL                                            0x9
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_CLOCK10_FVAL                                           0xa
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_CLOCK11_FVAL                                           0xb
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_CLOCK12_FVAL                                           0xc
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_CLOCK13_FVAL                                           0xd
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_CLOCK14_FVAL                                           0xe
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_CLOCK15_FVAL                                           0xf
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_BMSK                                                   0xf0
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_SHFT                                                    0x4
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_CLOCK0_FVAL                                             0x0
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_CLOCK1_FVAL                                             0x1
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_CLOCK2_FVAL                                             0x2
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_CLOCK3_FVAL                                             0x3
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_CLOCK4_FVAL                                             0x4
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_CLOCK5_FVAL                                             0x5
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_CLOCK6_FVAL                                             0x6
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_CLOCK7_FVAL                                             0x7
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_CLOCK8_FVAL                                             0x8
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_CLOCK9_FVAL                                             0x9
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_CLOCK10_FVAL                                            0xa
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_CLOCK11_FVAL                                            0xb
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_CLOCK12_FVAL                                            0xc
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_CLOCK13_FVAL                                            0xd
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_CLOCK14_FVAL                                            0xe
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_CLOCK15_FVAL                                            0xf
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_AOSS_CC_SWAO_TS_CBCR_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000224c)
#define HWIO_AOSS_CC_SWAO_TS_CBCR_OFFS                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000224c)
#define HWIO_AOSS_CC_SWAO_TS_CBCR_RMSK                                                    0x80000005
#define HWIO_AOSS_CC_SWAO_TS_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_TS_CBCR_ADDR)
#define HWIO_AOSS_CC_SWAO_TS_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_TS_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_TS_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_TS_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_TS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_TS_CBCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_TS_CBCR_IN)
#define HWIO_AOSS_CC_SWAO_TS_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_AOSS_CC_SWAO_TS_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_AOSS_CC_SWAO_TS_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_AOSS_CC_SWAO_TS_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_AOSS_CC_SWAO_TS_CBCR_CLK_ARES_NO_RESET_FVAL                                         0x0
#define HWIO_AOSS_CC_SWAO_TS_CBCR_CLK_ARES_RESET_FVAL                                            0x1
#define HWIO_AOSS_CC_SWAO_TS_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_AOSS_CC_SWAO_TS_CBCR_CLK_ENABLE_SHFT                                                0x0
#define HWIO_AOSS_CC_SWAO_TS_CBCR_CLK_ENABLE_DISABLE_FVAL                                        0x0
#define HWIO_AOSS_CC_SWAO_TS_CBCR_CLK_ENABLE_ENABLE_FVAL                                         0x1

#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002250)
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002250)
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_RMSK                                                 0x80000005
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_TS_AO_CBCR_ADDR)
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_TS_AO_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_TS_AO_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_TS_AO_CBCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_TS_AO_CBCR_IN)
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_CLK_OFF_BMSK                                         0x80000000
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_CLK_OFF_SHFT                                               0x1f
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_CLK_ARES_BMSK                                               0x4
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_CLK_ARES_SHFT                                               0x2
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_CLK_ARES_NO_RESET_FVAL                                      0x0
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_CLK_ARES_RESET_FVAL                                         0x1
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_CLK_ENABLE_BMSK                                             0x1
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_CLK_ENABLE_SHFT                                             0x0
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_CLK_ENABLE_DISABLE_FVAL                                     0x0
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_CLK_ENABLE_ENABLE_FVAL                                      0x1

#define HWIO_AOSS_CC_SWAO_BUS_CBCR_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002254)
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002254)
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_RMSK                                                   0x80000005
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_BUS_CBCR_ADDR)
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_BUS_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_BUS_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_BUS_CBCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_BUS_CBCR_IN)
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_AOSS_CC_SWAO_CMD_RCGR_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002258)
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002258)
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_RMSK                                                   0x80000013
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_CMD_RCGR_ADDR)
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_CMD_RCGR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_CMD_RCGR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_CMD_RCGR_ADDR,m,v,HWIO_AOSS_CC_SWAO_CMD_RCGR_IN)
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_ROOT_OFF_BMSK                                          0x80000000
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_ROOT_OFF_SHFT                                                0x1f
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                          0x10
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                           0x4
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_ROOT_EN_BMSK                                                  0x2
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_ROOT_EN_SHFT                                                  0x1
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_ROOT_EN_DISABLE_FVAL                                          0x0
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_ROOT_EN_ENABLE_FVAL                                           0x1
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_UPDATE_BMSK                                                   0x1
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_UPDATE_SHFT                                                   0x0
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_UPDATE_DISABLE_FVAL                                           0x0
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_UPDATE_ENABLE_FVAL                                            0x1

#define HWIO_AOSS_CC_SWAO_CFG_RCGR_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000225c)
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000225c)
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_RMSK                                                     0x11071f
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_CFG_RCGR_ADDR)
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_CFG_RCGR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_CFG_RCGR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_CFG_RCGR_ADDR,m,v,HWIO_AOSS_CC_SWAO_CFG_RCGR_IN)
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_HW_CLK_CONTROL_BMSK                                      0x100000
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_HW_CLK_CONTROL_SHFT                                          0x14
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL                                   0x0
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL                                    0x1
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_RCGLITE_DISABLE_BMSK                                      0x10000
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_RCGLITE_DISABLE_SHFT                                         0x10
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL                          0x0
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL                         0x1
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_SEL_BMSK                                                0x700
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_SEL_SHFT                                                  0x8
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_SEL_SRC0_FVAL                                             0x0
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_SEL_SRC1_FVAL                                             0x1
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_SEL_SRC2_FVAL                                             0x2
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_SEL_SRC3_FVAL                                             0x3
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_SEL_SRC4_FVAL                                             0x4
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_SEL_SRC5_FVAL                                             0x5
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_SEL_SRC6_FVAL                                             0x6
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_SEL_SRC7_FVAL                                             0x7
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_SHFT                                                  0x0
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_BYPASS_FVAL                                           0x0
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV1_FVAL                                             0x1
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV1_5_FVAL                                           0x2
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV2_FVAL                                             0x3
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV2_5_FVAL                                           0x4
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV3_FVAL                                             0x5
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV3_5_FVAL                                           0x6
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV4_FVAL                                             0x7
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV4_5_FVAL                                           0x8
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV5_FVAL                                             0x9
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV5_5_FVAL                                           0xa
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV6_FVAL                                             0xb
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV6_5_FVAL                                           0xc
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV7_FVAL                                             0xd
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV7_5_FVAL                                           0xe
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV8_FVAL                                             0xf
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV8_5_FVAL                                          0x10
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV9_FVAL                                            0x11
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV9_5_FVAL                                          0x12
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV10_FVAL                                           0x13
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV10_5_FVAL                                         0x14
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV11_FVAL                                           0x15
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV11_5_FVAL                                         0x16
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV12_FVAL                                           0x17
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV12_5_FVAL                                         0x18
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV13_FVAL                                           0x19
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV13_5_FVAL                                         0x1a
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV14_FVAL                                           0x1b
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV14_5_FVAL                                         0x1c
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV15_FVAL                                           0x1d
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV15_5_FVAL                                         0x1e
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_DIV16_FVAL                                           0x1f

#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002298)
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_OFFS                                                (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002298)
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_RMSK                                                0x80000013
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ADDR)
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ADDR,m,v,HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_IN)
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ROOT_OFF_BMSK                                       0x80000000
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ROOT_OFF_SHFT                                             0x1f
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                       0x10
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                        0x4
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ROOT_EN_BMSK                                               0x2
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ROOT_EN_SHFT                                               0x1
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ROOT_EN_DISABLE_FVAL                                       0x0
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ROOT_EN_ENABLE_FVAL                                        0x1
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_UPDATE_BMSK                                                0x1
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_UPDATE_SHFT                                                0x0
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_UPDATE_DISABLE_FVAL                                        0x0
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_UPDATE_ENABLE_FVAL                                         0x1

#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000229c)
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_OFFS                                                (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000229c)
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_RMSK                                                  0x11071f
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_ADDR)
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_ADDR,m,v,HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_IN)
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_HW_CLK_CONTROL_BMSK                                   0x100000
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_HW_CLK_CONTROL_SHFT                                       0x14
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL                                0x0
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL                                 0x1
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_RCGLITE_DISABLE_BMSK                                   0x10000
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_RCGLITE_DISABLE_SHFT                                      0x10
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL                       0x0
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL                      0x1
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_SEL_BMSK                                             0x700
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_SEL_SHFT                                               0x8
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_SEL_SRC0_FVAL                                          0x0
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_SEL_SRC1_FVAL                                          0x1
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_SEL_SRC2_FVAL                                          0x2
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_SEL_SRC3_FVAL                                          0x3
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_SEL_SRC4_FVAL                                          0x4
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_SEL_SRC5_FVAL                                          0x5
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_SEL_SRC6_FVAL                                          0x6
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_SEL_SRC7_FVAL                                          0x7
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_BMSK                                              0x1f
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_SHFT                                               0x0
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_BYPASS_FVAL                                        0x0
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV1_FVAL                                          0x1
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV1_5_FVAL                                        0x2
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV2_FVAL                                          0x3
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV2_5_FVAL                                        0x4
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV3_FVAL                                          0x5
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV3_5_FVAL                                        0x6
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV4_FVAL                                          0x7
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV4_5_FVAL                                        0x8
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV5_FVAL                                          0x9
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV5_5_FVAL                                        0xa
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV6_FVAL                                          0xb
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV6_5_FVAL                                        0xc
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV7_FVAL                                          0xd
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV7_5_FVAL                                        0xe
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV8_FVAL                                          0xf
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV8_5_FVAL                                       0x10
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV9_FVAL                                         0x11
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV9_5_FVAL                                       0x12
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV10_FVAL                                        0x13
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV10_5_FVAL                                      0x14
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV11_FVAL                                        0x15
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV11_5_FVAL                                      0x16
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV12_FVAL                                        0x17
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV12_5_FVAL                                      0x18
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV13_FVAL                                        0x19
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV13_5_FVAL                                      0x1a
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV14_FVAL                                        0x1b
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV14_5_FVAL                                      0x1c
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV15_FVAL                                        0x1d
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV15_5_FVAL                                      0x1e
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_DIV16_FVAL                                        0x1f

#define HWIO_AOSS_CC_SPMI_BCR_ADDR                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000022d8)
#define HWIO_AOSS_CC_SPMI_BCR_OFFS                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x000022d8)
#define HWIO_AOSS_CC_SPMI_BCR_RMSK                                                               0x1
#define HWIO_AOSS_CC_SPMI_BCR_IN          \
        in_dword(HWIO_AOSS_CC_SPMI_BCR_ADDR)
#define HWIO_AOSS_CC_SPMI_BCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPMI_BCR_ADDR, m)
#define HWIO_AOSS_CC_SPMI_BCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPMI_BCR_ADDR,v)
#define HWIO_AOSS_CC_SPMI_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPMI_BCR_ADDR,m,v,HWIO_AOSS_CC_SPMI_BCR_IN)
#define HWIO_AOSS_CC_SPMI_BCR_BLK_ARES_BMSK                                                      0x1
#define HWIO_AOSS_CC_SPMI_BCR_BLK_ARES_SHFT                                                      0x0
#define HWIO_AOSS_CC_SPMI_BCR_BLK_ARES_DISABLE_FVAL                                              0x0
#define HWIO_AOSS_CC_SPMI_BCR_BLK_ARES_ENABLE_FVAL                                               0x1

#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_ADDR                                               (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000022dc)
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_OFFS                                               (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x000022dc)
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_RMSK                                               0x80000005
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_ADDR)
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_ADDR,m,v,HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_IN)
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_CLK_OFF_BMSK                                       0x80000000
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_CLK_OFF_SHFT                                             0x1f
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_CLK_ARES_BMSK                                             0x4
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_CLK_ARES_SHFT                                             0x2
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_CLK_ARES_NO_RESET_FVAL                                    0x0
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_CLK_ARES_RESET_FVAL                                       0x1
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_CLK_ENABLE_BMSK                                           0x1
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_CLK_ENABLE_SHFT                                           0x0
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_CLK_ENABLE_DISABLE_FVAL                                   0x0
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_CLK_ENABLE_ENABLE_FVAL                                    0x1

#define HWIO_AOSS_CC_SPMI_SER_CBCR_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000022e0)
#define HWIO_AOSS_CC_SPMI_SER_CBCR_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x000022e0)
#define HWIO_AOSS_CC_SPMI_SER_CBCR_RMSK                                                   0x80000005
#define HWIO_AOSS_CC_SPMI_SER_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SPMI_SER_CBCR_ADDR)
#define HWIO_AOSS_CC_SPMI_SER_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPMI_SER_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SPMI_SER_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPMI_SER_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SPMI_SER_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPMI_SER_CBCR_ADDR,m,v,HWIO_AOSS_CC_SPMI_SER_CBCR_IN)
#define HWIO_AOSS_CC_SPMI_SER_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_AOSS_CC_SPMI_SER_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_AOSS_CC_SPMI_SER_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_AOSS_CC_SPMI_SER_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_AOSS_CC_SPMI_SER_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_AOSS_CC_SPMI_SER_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_AOSS_CC_SPMI_SER_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_AOSS_CC_SPMI_SER_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_AOSS_CC_SPMI_SER_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_AOSS_CC_SPMI_SER_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_ADDR                                               (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000022e4)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_OFFS                                               (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x000022e4)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_RMSK                                               0x80000005
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_ADDR)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_ADDR,m,v,HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_IN)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_CLK_OFF_BMSK                                       0x80000000
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_CLK_OFF_SHFT                                             0x1f
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_CLK_ARES_BMSK                                             0x4
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_CLK_ARES_SHFT                                             0x2
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_CLK_ARES_NO_RESET_FVAL                                    0x0
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_CLK_ARES_RESET_FVAL                                       0x1
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_CLK_ENABLE_BMSK                                           0x1
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_CLK_ENABLE_SHFT                                           0x0
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_CLK_ENABLE_DISABLE_FVAL                                   0x0
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_CLK_ENABLE_ENABLE_FVAL                                    0x1

#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ADDR                                           (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000022e8)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_OFFS                                           (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x000022e8)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_RMSK                                           0x80000013
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ADDR)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ADDR, m)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ADDR,v)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ADDR,m,v,HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_IN)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ROOT_OFF_BMSK                                  0x80000000
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ROOT_OFF_SHFT                                        0x1f
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                  0x10
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                   0x4
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ROOT_EN_BMSK                                          0x2
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ROOT_EN_SHFT                                          0x1
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ROOT_EN_DISABLE_FVAL                                  0x0
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ROOT_EN_ENABLE_FVAL                                   0x1
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_UPDATE_BMSK                                           0x1
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_UPDATE_SHFT                                           0x0
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_UPDATE_DISABLE_FVAL                                   0x0
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_UPDATE_ENABLE_FVAL                                    0x1

#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_ADDR                                           (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000022ec)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_OFFS                                           (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x000022ec)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_RMSK                                             0x11071f
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_ADDR)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_ADDR, m)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_ADDR,v)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_ADDR,m,v,HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_IN)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_HW_CLK_CONTROL_BMSK                              0x100000
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_HW_CLK_CONTROL_SHFT                                  0x14
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_HW_CLK_CONTROL_DISABLE_FVAL                           0x0
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_HW_CLK_CONTROL_ENABLE_FVAL                            0x1
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_RCGLITE_DISABLE_BMSK                              0x10000
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_RCGLITE_DISABLE_SHFT                                 0x10
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_ENABLED_FVAL                  0x0
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_RCGLITE_DISABLE_RCGLITE_DISABLED_FVAL                 0x1
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_SEL_BMSK                                        0x700
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_SEL_SHFT                                          0x8
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_SEL_SRC0_FVAL                                     0x0
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_SEL_SRC1_FVAL                                     0x1
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_SEL_SRC2_FVAL                                     0x2
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_SEL_SRC3_FVAL                                     0x3
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_SEL_SRC4_FVAL                                     0x4
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_SEL_SRC5_FVAL                                     0x5
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_SEL_SRC6_FVAL                                     0x6
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_SEL_SRC7_FVAL                                     0x7
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_BMSK                                         0x1f
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_SHFT                                          0x0
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_BYPASS_FVAL                                   0x0
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV1_FVAL                                     0x1
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV1_5_FVAL                                   0x2
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV2_FVAL                                     0x3
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV2_5_FVAL                                   0x4
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV3_FVAL                                     0x5
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV3_5_FVAL                                   0x6
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV4_FVAL                                     0x7
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV4_5_FVAL                                   0x8
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV5_FVAL                                     0x9
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV5_5_FVAL                                   0xa
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV6_FVAL                                     0xb
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV6_5_FVAL                                   0xc
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV7_FVAL                                     0xd
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV7_5_FVAL                                   0xe
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV8_FVAL                                     0xf
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV8_5_FVAL                                  0x10
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV9_FVAL                                    0x11
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV9_5_FVAL                                  0x12
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV10_FVAL                                   0x13
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV10_5_FVAL                                 0x14
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV11_FVAL                                   0x15
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV11_5_FVAL                                 0x16
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV12_FVAL                                   0x17
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV12_5_FVAL                                 0x18
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV13_FVAL                                   0x19
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV13_5_FVAL                                 0x1a
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV14_FVAL                                   0x1b
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV14_5_FVAL                                 0x1c
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV15_FVAL                                   0x1d
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV15_5_FVAL                                 0x1e
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_DIV16_FVAL                                   0x1f

#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002328)
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002328)
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_RMSK                                                        0x1
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_IN          \
        in_dword(HWIO_AOSS_CC_GLOBAL_CNTR_BCR_ADDR)
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_GLOBAL_CNTR_BCR_ADDR, m)
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_GLOBAL_CNTR_BCR_ADDR,v)
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_GLOBAL_CNTR_BCR_ADDR,m,v,HWIO_AOSS_CC_GLOBAL_CNTR_BCR_IN)
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_BLK_ARES_BMSK                                               0x1
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_BLK_ARES_SHFT                                               0x0
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_BLK_ARES_DISABLE_FVAL                                       0x0
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_BLK_ARES_ENABLE_FVAL                                        0x1

#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002340)
#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002340)
#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_RMSK                                                        0x3
#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_IN          \
        in_dword(HWIO_AOSS_CC_DEBUG_DIV_CDIVR_ADDR)
#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_DEBUG_DIV_CDIVR_ADDR, m)
#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_DEBUG_DIV_CDIVR_ADDR,v)
#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_DEBUG_DIV_CDIVR_ADDR,m,v,HWIO_AOSS_CC_DEBUG_DIV_CDIVR_IN)
#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_CLK_DIV_BMSK                                                0x3
#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_CLK_DIV_SHFT                                                0x0

#define HWIO_AOSS_CC_DEBUG_CBCR_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002344)
#define HWIO_AOSS_CC_DEBUG_CBCR_OFFS                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002344)
#define HWIO_AOSS_CC_DEBUG_CBCR_RMSK                                                      0x80000005
#define HWIO_AOSS_CC_DEBUG_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_DEBUG_CBCR_ADDR)
#define HWIO_AOSS_CC_DEBUG_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_DEBUG_CBCR_ADDR, m)
#define HWIO_AOSS_CC_DEBUG_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_DEBUG_CBCR_ADDR,v)
#define HWIO_AOSS_CC_DEBUG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_DEBUG_CBCR_ADDR,m,v,HWIO_AOSS_CC_DEBUG_CBCR_IN)
#define HWIO_AOSS_CC_DEBUG_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_AOSS_CC_DEBUG_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_AOSS_CC_DEBUG_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_AOSS_CC_DEBUG_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_AOSS_CC_DEBUG_CBCR_CLK_ARES_NO_RESET_FVAL                                           0x0
#define HWIO_AOSS_CC_DEBUG_CBCR_CLK_ARES_RESET_FVAL                                              0x1
#define HWIO_AOSS_CC_DEBUG_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_AOSS_CC_DEBUG_CBCR_CLK_ENABLE_SHFT                                                  0x0
#define HWIO_AOSS_CC_DEBUG_CBCR_CLK_ENABLE_DISABLE_FVAL                                          0x0
#define HWIO_AOSS_CC_DEBUG_CBCR_CLK_ENABLE_ENABLE_FVAL                                           0x1

#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_ADDR                                              (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000234c)
#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_OFFS                                              (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000234c)
#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_RMSK                                                     0x3
#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_IN          \
        in_dword(HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_ADDR)
#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_ADDR, m)
#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_ADDR,v)
#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_ADDR,m,v,HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_IN)
#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_CLK_DIV_BMSK                                             0x3
#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_CLK_DIV_SHFT                                             0x0

#define HWIO_AOSS_CC_PLL_TEST_CBCR_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002350)
#define HWIO_AOSS_CC_PLL_TEST_CBCR_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002350)
#define HWIO_AOSS_CC_PLL_TEST_CBCR_RMSK                                                   0x80000005
#define HWIO_AOSS_CC_PLL_TEST_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_PLL_TEST_CBCR_ADDR)
#define HWIO_AOSS_CC_PLL_TEST_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL_TEST_CBCR_ADDR, m)
#define HWIO_AOSS_CC_PLL_TEST_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL_TEST_CBCR_ADDR,v)
#define HWIO_AOSS_CC_PLL_TEST_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL_TEST_CBCR_ADDR,m,v,HWIO_AOSS_CC_PLL_TEST_CBCR_IN)
#define HWIO_AOSS_CC_PLL_TEST_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_AOSS_CC_PLL_TEST_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_AOSS_CC_PLL_TEST_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_AOSS_CC_PLL_TEST_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_AOSS_CC_PLL_TEST_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_AOSS_CC_PLL_TEST_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_AOSS_CC_PLL_TEST_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_AOSS_CC_PLL_TEST_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_AOSS_CC_PLL_TEST_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_AOSS_CC_PLL_TEST_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002354)
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_OFFS                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002354)
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_RMSK                                                         0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_IN          \
        in_dword(HWIO_AOSS_CC_RPMH_ACCEL_BCR_ADDR)
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RPMH_ACCEL_BCR_ADDR, m)
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RPMH_ACCEL_BCR_ADDR,v)
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RPMH_ACCEL_BCR_ADDR,m,v,HWIO_AOSS_CC_RPMH_ACCEL_BCR_IN)
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_BLK_ARES_BMSK                                                0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_BLK_ARES_SHFT                                                0x0
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_BLK_ARES_DISABLE_FVAL                                        0x0
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_BLK_ARES_ENABLE_FVAL                                         0x1

#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002358)
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_OFFS                                                (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002358)
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RMSK                                                0xf8ffffff
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_IN          \
        in_dword(HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_ADDR)
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_ADDR, m)
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_ADDR,v)
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_ADDR,m,v,HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_IN)
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_PWR_ON_BMSK                                         0x80000000
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_PWR_ON_SHFT                                               0x1f
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_GDSC_STATE_BMSK                                     0x78000000
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_GDSC_STATE_SHFT                                           0x1b
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_REST_WAIT_BMSK                                     0xf00000
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_REST_WAIT_SHFT                                         0x14
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_FEW_WAIT_BMSK                                       0xf0000
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_FEW_WAIT_SHFT                                          0x10
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_CLK_DIS_WAIT_BMSK                                       0xf000
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_CLK_DIS_WAIT_SHFT                                          0xc
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RETAIN_FF_ENABLE_BMSK                                    0x800
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RETAIN_FF_ENABLE_SHFT                                      0xb
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL                              0x0
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL                               0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RESTORE_BMSK                                             0x400
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RESTORE_SHFT                                               0xa
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RESTORE_DISABLE_FVAL                                       0x0
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RESTORE_ENABLE_FVAL                                        0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SAVE_BMSK                                                0x200
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SAVE_SHFT                                                  0x9
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SAVE_DISABLE_FVAL                                          0x0
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SAVE_ENABLE_FVAL                                           0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RETAIN_BMSK                                              0x100
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RETAIN_SHFT                                                0x8
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RETAIN_DISABLE_FVAL                                        0x0
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RETAIN_ENABLE_FVAL                                         0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_REST_BMSK                                              0x80
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_REST_SHFT                                               0x7
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_REST_DISABLE_FVAL                                       0x0
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_REST_ENABLE_FVAL                                        0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_FEW_BMSK                                               0x40
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_FEW_SHFT                                                0x6
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_FEW_DISABLE_FVAL                                        0x0
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_FEW_ENABLE_FVAL                                         0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_CLAMP_IO_BMSK                                             0x20
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_CLAMP_IO_SHFT                                              0x5
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_CLAMP_IO_DISABLE_FVAL                                      0x0
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_CLAMP_IO_ENABLE_FVAL                                       0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_CLK_DISABLE_BMSK                                          0x10
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_CLK_DISABLE_SHFT                                           0x4
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL                           0x0
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_CLK_DISABLE_CLK_DISABLE_FVAL                               0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_PD_ARES_BMSK                                               0x8
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_PD_ARES_SHFT                                               0x3
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_PD_ARES_NO_RESET_FVAL                                      0x0
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_PD_ARES_RESET_FVAL                                         0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SW_OVERRIDE_BMSK                                           0x4
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SW_OVERRIDE_SHFT                                           0x2
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SW_OVERRIDE_DISABLE_FVAL                                   0x0
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SW_OVERRIDE_ENABLE_FVAL                                    0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_HW_CONTROL_BMSK                                            0x2
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_HW_CONTROL_SHFT                                            0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_HW_CONTROL_DISABLE_FVAL                                    0x0
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_HW_CONTROL_ENABLE_FVAL                                     0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SW_COLLAPSE_BMSK                                           0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SW_COLLAPSE_SHFT                                           0x0
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SW_COLLAPSE_DISABLE_FVAL                                   0x0
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SW_COLLAPSE_ENABLE_FVAL                                    0x1

#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_ADDR                                            (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000235c)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_OFFS                                            (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000235c)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_RMSK                                            0xffffffff
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_IN          \
        in_dword(HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_ADDR)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_ADDR, m)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_ADDR,v)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_ADDR,m,v,HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_IN)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_SPARE_CTRL_IN_BMSK                         0xf0000000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_SPARE_CTRL_IN_SHFT                               0x1c
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK                         0xc000000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT                              0x1a
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK                          0x2000000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT                               0x19
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PWR_UP_START_BMSK                           0x1000000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PWR_UP_START_SHFT                                0x18
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK                    0xf00000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT                        0x14
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                       0x80000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                          0x13
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK                           0x40000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT                              0x12
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK                           0x20000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT                              0x11
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK                        0x10000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT                           0x10
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                       0x8000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                          0xf
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                      0x7800
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                         0xb
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK                              0x400
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT                                0xa
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                       0x200
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                         0x9
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                       0x100
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                         0x8
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                           0x80
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                            0x7
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                  0x60
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                   0x5
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                            0x10
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                             0x4
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                      0x8
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                      0x3
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                    0x4
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                    0x2
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                        0x2
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                        0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                     0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                     0x0

#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_ADDR                                           (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002360)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_OFFS                                           (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002360)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_RMSK                                              0x1ffff
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_IN          \
        in_dword(HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_ADDR)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_ADDR, m)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_ADDR,v)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_ADDR,m,v,HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_IN)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK                            0x10000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT                               0x10
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK                                0xf000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT                                   0xc
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                         0xf00
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                           0x8
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                            0xf0
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                             0x4
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                              0xf
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                              0x0

#define HWIO_AOSS_CC_RPMH_CBCR_ADDR                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002364)
#define HWIO_AOSS_CC_RPMH_CBCR_OFFS                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00002364)
#define HWIO_AOSS_CC_RPMH_CBCR_RMSK                                                       0x80000005
#define HWIO_AOSS_CC_RPMH_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_RPMH_CBCR_ADDR)
#define HWIO_AOSS_CC_RPMH_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RPMH_CBCR_ADDR, m)
#define HWIO_AOSS_CC_RPMH_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RPMH_CBCR_ADDR,v)
#define HWIO_AOSS_CC_RPMH_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RPMH_CBCR_ADDR,m,v,HWIO_AOSS_CC_RPMH_CBCR_IN)
#define HWIO_AOSS_CC_RPMH_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_AOSS_CC_RPMH_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_AOSS_CC_RPMH_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_AOSS_CC_RPMH_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_AOSS_CC_RPMH_CBCR_CLK_ARES_NO_RESET_FVAL                                            0x0
#define HWIO_AOSS_CC_RPMH_CBCR_CLK_ARES_RESET_FVAL                                               0x1
#define HWIO_AOSS_CC_RPMH_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_AOSS_CC_RPMH_CBCR_CLK_ENABLE_SHFT                                                   0x0
#define HWIO_AOSS_CC_RPMH_CBCR_CLK_ENABLE_DISABLE_FVAL                                           0x0
#define HWIO_AOSS_CC_RPMH_CBCR_CLK_ENABLE_ENABLE_FVAL                                            0x1

#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_ADDR                                           (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000023a4)
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_OFFS                                           (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x000023a4)
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_RMSK                                           0x80000005
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_ADDR)
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_ADDR, m)
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_ADDR,v)
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_ADDR,m,v,HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_IN)
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_CLK_OFF_BMSK                                   0x80000000
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_CLK_OFF_SHFT                                         0x1f
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_CLK_ARES_BMSK                                         0x4
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_CLK_ARES_SHFT                                         0x2
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_CLK_ARES_NO_RESET_FVAL                                0x0
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_CLK_ARES_RESET_FVAL                                   0x1
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_CLK_ENABLE_BMSK                                       0x1
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_CLK_ENABLE_SHFT                                       0x0
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_CLK_ENABLE_DISABLE_FVAL                               0x0
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_CLK_ENABLE_ENABLE_FVAL                                0x1

#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003004)
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_OFFS                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00003004)
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_RMSK                                                        0xff
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_IN          \
        in_dword(HWIO_AOSS_CC_DEBUG_MUX_MUXR_ADDR)
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_DEBUG_MUX_MUXR_ADDR, m)
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_DEBUG_MUX_MUXR_ADDR,v)
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_DEBUG_MUX_MUXR_ADDR,m,v,HWIO_AOSS_CC_DEBUG_MUX_MUXR_IN)
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_BMSK                                                0xff
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_SHFT                                                 0x0
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_AOP_PROC_FREERUN_CLK_FVAL                    0x1
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_AOP_PROC_RISCV_AHB_CLK_FVAL                  0x2
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_AOP_PROC_AHB_CLK_FVAL                        0x3
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_AOP_BUS_AHB_CLK_FVAL                         0x4
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_IBI_CTRL0_CLK_FVAL                           0x5
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_IBI_CTRL1_CLK_FVAL                           0x6
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_IBI_CTRL2_CLK_FVAL                           0x7
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_IBI_CTRL3_CLK_FVAL                           0x8
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_BUS_CLK_FVAL                                 0x9
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_MESSAGE_RAM_CLK_FVAL                         0xa
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_AOP_RO_CLK_FVAL                              0xb
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_PWR_MUX_CTRL_CLK_FVAL                        0xc
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_AO_DAP_CLK_FVAL                              0xd
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_AOP_DAP_CLK_FVAL                             0xe
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_WCSS_TS_CLK_FVAL                             0xf
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_RO_CLK_FVAL                                 0x10
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_EUD_AT_CLK_FVAL                             0x11
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_XO_CLK_FVAL                                 0x12
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_GDSC_CLK_FVAL                               0x13
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_TSENS_HW_CLK_FVAL                           0x14
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_PDC_CLK_FVAL                                0x15
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_PDC_GLOBAL_CNTR_CLK_FVAL                    0x16
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_SLEEP_CLK_FVAL                              0x17
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_PERIPH_SLP_CLK_FVAL                         0x18
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_SWAO_RPMH_DEBUG_CLK_FVAL                    0x1a
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_SWAO_CLK_FVAL                               0x1b
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_SWAO_AO_CLK_FVAL                            0x1c
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_SWAO_MEM_CLK_FVAL                           0x1d
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_SWAO_TS_CLK_FVAL                            0x1e
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_SWAO_TS_AO_CLK_FVAL                         0x1f
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_SWAO_BUS_CLK_FVAL                           0x20
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_SPMI_CFG_AHB_CLK_FVAL                       0x21
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_SPMI_SER_CLK_FVAL                           0x22
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_SPMI_AOD_SER_CLK_FVAL                       0x23
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_WCSS_DBG_CLK_FVAL                                   0x24
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_SSC_DBG_CLK_FVAL                                    0x25
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_RPMH_CLK_FVAL                               0x26
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_AOSS_CC_RPMH_GLOBAL_CNTR_CLK_FVAL                   0x27

#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_ADDR                                               (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003008)
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_OFFS                                               (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00003008)
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_RMSK                                                      0x7
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_IN          \
        in_dword(HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_ADDR)
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_ADDR, m)
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_ADDR,v)
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_ADDR,m,v,HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_IN)
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_MUX_SEL_BMSK                                              0x7
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_MUX_SEL_SHFT                                              0x0
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_MUX_SEL_AOSS_CC_PLL0_TEST_FVAL                            0x0
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_MUX_SEL_AOSS_CC_PLL1_TEST_FVAL                            0x1

#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000300c)
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_OFFS                                                (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000300c)
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_RMSK                                                       0x7
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_IN          \
        in_dword(HWIO_AOSS_CC_PLL_RESET_N_MUXR_ADDR)
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL_RESET_N_MUXR_ADDR, m)
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL_RESET_N_MUXR_ADDR,v)
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL_RESET_N_MUXR_ADDR,m,v,HWIO_AOSS_CC_PLL_RESET_N_MUXR_IN)
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_MUX_SEL_BMSK                                               0x7
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_MUX_SEL_SHFT                                               0x0
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_MUX_SEL_AOSS_CC_PLL0_RESET_N_FVAL                          0x0
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_MUX_SEL_AOSS_CC_PLL1_RESET_N_FVAL                          0x1

#define HWIO_AOSS_CC_PLL_STATUS_MUXR_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003010)
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00003010)
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_RMSK                                                        0x7
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_IN          \
        in_dword(HWIO_AOSS_CC_PLL_STATUS_MUXR_ADDR)
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL_STATUS_MUXR_ADDR, m)
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL_STATUS_MUXR_ADDR,v)
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL_STATUS_MUXR_ADDR,m,v,HWIO_AOSS_CC_PLL_STATUS_MUXR_IN)
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_MUX_SEL_BMSK                                                0x7
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_MUX_SEL_SHFT                                                0x0
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_MUX_SEL_ZERO_FVAL                                           0x0
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_MUX_SEL_AOSS_CC_PLL0_STATUS_FVAL                            0x1
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_MUX_SEL_AOSS_CC_PLL1_STATUS_FVAL                            0x2
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_MUX_SEL_RST_CTL_STATUS31_0_FVAL                             0x3
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_MUX_SEL_RST_CTL_STATUS63_32_FVAL                            0x4

#define HWIO_AOSS_CC_PLL_CLK_SEL_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003014)
#define HWIO_AOSS_CC_PLL_CLK_SEL_OFFS                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00003014)
#define HWIO_AOSS_CC_PLL_CLK_SEL_RMSK                                                            0x7
#define HWIO_AOSS_CC_PLL_CLK_SEL_IN          \
        in_dword(HWIO_AOSS_CC_PLL_CLK_SEL_ADDR)
#define HWIO_AOSS_CC_PLL_CLK_SEL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL_CLK_SEL_ADDR, m)
#define HWIO_AOSS_CC_PLL_CLK_SEL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL_CLK_SEL_ADDR,v)
#define HWIO_AOSS_CC_PLL_CLK_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL_CLK_SEL_ADDR,m,v,HWIO_AOSS_CC_PLL_CLK_SEL_IN)
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL1_CLK_REF_SEL_BMSK                                           0x4
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL1_CLK_REF_SEL_SHFT                                           0x2
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL1_CLK_REF_SEL_BI_TCXO_FVAL                                   0x0
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL1_CLK_REF_SEL_SLEEP_CLK_FVAL                                 0x1
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL1_CLK_XO_SEL_BMSK                                            0x2
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL1_CLK_XO_SEL_SHFT                                            0x1
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL1_CLK_XO_SEL_BI_TCXO_FVAL                                    0x0
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL1_CLK_XO_SEL_SLEEP_CLK_FVAL                                  0x1
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL0_CLK_REF_SEL_BMSK                                           0x1
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL0_CLK_REF_SEL_SHFT                                           0x0
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL0_CLK_REF_SEL_BI_TCXO_FVAL                                   0x0
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL0_CLK_REF_SEL_PLUTO_OUTPUT_FVAL                              0x1

#define HWIO_AOSS_CC_CDBGPWRUPREQ_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003018)
#define HWIO_AOSS_CC_CDBGPWRUPREQ_OFFS                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00003018)
#define HWIO_AOSS_CC_CDBGPWRUPREQ_RMSK                                                    0x80000001
#define HWIO_AOSS_CC_CDBGPWRUPREQ_IN          \
        in_dword(HWIO_AOSS_CC_CDBGPWRUPREQ_ADDR)
#define HWIO_AOSS_CC_CDBGPWRUPREQ_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_CDBGPWRUPREQ_ADDR, m)
#define HWIO_AOSS_CC_CDBGPWRUPREQ_OUT(v)      \
        out_dword(HWIO_AOSS_CC_CDBGPWRUPREQ_ADDR,v)
#define HWIO_AOSS_CC_CDBGPWRUPREQ_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_CDBGPWRUPREQ_ADDR,m,v,HWIO_AOSS_CC_CDBGPWRUPREQ_IN)
#define HWIO_AOSS_CC_CDBGPWRUPREQ_STATUS_BMSK                                             0x80000000
#define HWIO_AOSS_CC_CDBGPWRUPREQ_STATUS_SHFT                                                   0x1f
#define HWIO_AOSS_CC_CDBGPWRUPREQ_REQ_BMSK                                                       0x1
#define HWIO_AOSS_CC_CDBGPWRUPREQ_REQ_SHFT                                                       0x0
#define HWIO_AOSS_CC_CDBGPWRUPREQ_REQ_DISABLE_FVAL                                               0x0
#define HWIO_AOSS_CC_CDBGPWRUPREQ_REQ_ENABLE_FVAL                                                0x1

#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ADDR                                              (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050000)
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_OFFS                                              (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00050000)
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_RMSK                                                  0x3fff
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_IN          \
        in_dword(HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ADDR)
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ADDR, m)
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ADDR,v)
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ADDR,m,v,HWIO_AOSS_CC_RESET_DEBUG_ENABLE_IN)
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PCIE_RESET_SEP_EN_BMSK                                0x2000
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PCIE_RESET_SEP_EN_SHFT                                   0xd
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PCIE_RESET_SEP_EN_DISABLE_FVAL                           0x0
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PCIE_RESET_SEP_EN_ENABLE_FVAL                            0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_SW_BASED_PRE_ARES_BMSK                                0x1000
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_SW_BASED_PRE_ARES_SHFT                                   0xc
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_SW_BASED_PRE_ARES_DEASSERT_FVAL                          0x0
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_SW_BASED_PRE_ARES_ASSERT_FVAL                            0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ALLOW_SW_BASED_RST_DBG_EN_BMSK                         0x800
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ALLOW_SW_BASED_RST_DBG_EN_SHFT                           0xb
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ALLOW_SW_BASED_RST_DBG_EN_DISABLE_FVAL                   0x0
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ALLOW_SW_BASED_RST_DBG_EN_ENABLE_FVAL                    0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PRE_SW_SRST_TMR_EN_BMSK                                0x400
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PRE_SW_SRST_TMR_EN_SHFT                                  0xa
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PRE_SW_SRST_TMR_EN_DISABLE_FVAL                          0x0
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PRE_SW_SRST_TMR_EN_ENABLE_FVAL                           0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_EUD_T32_SRST_EN_BMSK                                   0x200
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_EUD_T32_SRST_EN_SHFT                                     0x9
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_EUD_T32_SRST_EN_DISABLE_FVAL                             0x0
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_EUD_T32_SRST_EN_ENABLE_FVAL                              0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_EUD_RESET_SECOND_PASS_EN_BMSK                          0x100
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_EUD_RESET_SECOND_PASS_EN_SHFT                            0x8
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_EUD_RESET_SECOND_PASS_EN_DISABLE_FVAL                    0x0
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_EUD_RESET_SECOND_PASS_EN_ENABLE_FVAL                     0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_DISABLE_APCS_ALT_ARES_BMSK                              0x80
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_DISABLE_APCS_ALT_ARES_SHFT                               0x7
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_DISABLE_APCS_ALT_ARES_ENABLE_FVAL                        0x0
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_DISABLE_APCS_ALT_ARES_DISABLE_FVAL                       0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_SECURE_WDOG_RESET_DEBUG_EN_BMSK                         0x40
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_SECURE_WDOG_RESET_DEBUG_EN_SHFT                          0x6
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_SECURE_WDOG_RESET_DEBUG_EN_DISABLE_FVAL                  0x0
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_SECURE_WDOG_RESET_DEBUG_EN_ENABLE_FVAL                   0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_MSM_TSENSE_RESET_DEBUG_EN_BMSK                          0x20
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_MSM_TSENSE_RESET_DEBUG_EN_SHFT                           0x5
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_MSM_TSENSE_RESET_DEBUG_EN_DISABLE_FVAL                   0x0
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_MSM_TSENSE_RESET_DEBUG_EN_ENABLE_FVAL                    0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PMIC_RESIN_RESET_DEBUG_EN_BMSK                          0x10
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PMIC_RESIN_RESET_DEBUG_EN_SHFT                           0x4
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PMIC_RESIN_RESET_DEBUG_EN_DISABLE_FVAL                   0x0
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PMIC_RESIN_RESET_DEBUG_EN_ENABLE_FVAL                    0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PROC_HALT_EN_BMSK                                        0x8
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PROC_HALT_EN_SHFT                                        0x3
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PROC_HALT_EN_DISABLE_FVAL                                0x0
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PROC_HALT_EN_ENABLE_FVAL                                 0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_AUTO_PS_HOLD_SET_EN_BMSK                                 0x4
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_AUTO_PS_HOLD_SET_EN_SHFT                                 0x2
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_AUTO_PS_HOLD_SET_EN_DISABLE_FVAL                         0x0
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_AUTO_PS_HOLD_SET_EN_ENABLE_FVAL                          0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ACCESS_RESET_FIRST_PASS_EN_BMSK                          0x2
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ACCESS_RESET_FIRST_PASS_EN_SHFT                          0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ACCESS_RESET_FIRST_PASS_EN_DISABLE_FVAL                  0x0
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ACCESS_RESET_FIRST_PASS_EN_ENABLE_FVAL                   0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_DEBUG_RESET_FIRST_PASS_EN_BMSK                           0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_DEBUG_RESET_FIRST_PASS_EN_SHFT                           0x0
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_DEBUG_RESET_FIRST_PASS_EN_DISABLE_FVAL                   0x0
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_DEBUG_RESET_FIRST_PASS_EN_ENABLE_FVAL                    0x1

#define HWIO_AOSS_CC_RESET_FSM_CTRL_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050004)
#define HWIO_AOSS_CC_RESET_FSM_CTRL_OFFS                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00050004)
#define HWIO_AOSS_CC_RESET_FSM_CTRL_RMSK                                                        0x7f
#define HWIO_AOSS_CC_RESET_FSM_CTRL_IN          \
        in_dword(HWIO_AOSS_CC_RESET_FSM_CTRL_ADDR)
#define HWIO_AOSS_CC_RESET_FSM_CTRL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RESET_FSM_CTRL_ADDR, m)
#define HWIO_AOSS_CC_RESET_FSM_CTRL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RESET_FSM_CTRL_ADDR,v)
#define HWIO_AOSS_CC_RESET_FSM_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RESET_FSM_CTRL_ADDR,m,v,HWIO_AOSS_CC_RESET_FSM_CTRL_IN)
#define HWIO_AOSS_CC_RESET_FSM_CTRL_BLOCK_PCIE_ARES_BMSK                                        0x40
#define HWIO_AOSS_CC_RESET_FSM_CTRL_BLOCK_PCIE_ARES_SHFT                                         0x6
#define HWIO_AOSS_CC_RESET_FSM_CTRL_BLOCK_PCIE_ARES_UNBLOCK_FVAL                                 0x0
#define HWIO_AOSS_CC_RESET_FSM_CTRL_BLOCK_PCIE_ARES_BLOCK_FVAL                                   0x1
#define HWIO_AOSS_CC_RESET_FSM_CTRL_PCIE_LINK_TMR_EN_BMSK                                       0x20
#define HWIO_AOSS_CC_RESET_FSM_CTRL_PCIE_LINK_TMR_EN_SHFT                                        0x5
#define HWIO_AOSS_CC_RESET_FSM_CTRL_PCIE_LINK_TMR_EN_DISABLE_FVAL                                0x0
#define HWIO_AOSS_CC_RESET_FSM_CTRL_PCIE_LINK_TMR_EN_ENABLE_FVAL                                 0x1
#define HWIO_AOSS_CC_RESET_FSM_CTRL_WKUP_TMR_EN_BMSK                                            0x10
#define HWIO_AOSS_CC_RESET_FSM_CTRL_WKUP_TMR_EN_SHFT                                             0x4
#define HWIO_AOSS_CC_RESET_FSM_CTRL_WKUP_TMR_EN_DISABLE_FVAL                                     0x0
#define HWIO_AOSS_CC_RESET_FSM_CTRL_WKUP_TMR_EN_ENABLE_FVAL                                      0x1
#define HWIO_AOSS_CC_RESET_FSM_CTRL_NORMAL_WKUP_EN_BMSK                                          0x8
#define HWIO_AOSS_CC_RESET_FSM_CTRL_NORMAL_WKUP_EN_SHFT                                          0x3
#define HWIO_AOSS_CC_RESET_FSM_CTRL_NORMAL_WKUP_EN_DISABLE_FVAL                                  0x0
#define HWIO_AOSS_CC_RESET_FSM_CTRL_NORMAL_WKUP_EN_ENABLE_FVAL                                   0x1
#define HWIO_AOSS_CC_RESET_FSM_CTRL_FIRST_PASS_TMR_EN_BMSK                                       0x4
#define HWIO_AOSS_CC_RESET_FSM_CTRL_FIRST_PASS_TMR_EN_SHFT                                       0x2
#define HWIO_AOSS_CC_RESET_FSM_CTRL_FIRST_PASS_TMR_EN_DISABLE_FVAL                               0x0
#define HWIO_AOSS_CC_RESET_FSM_CTRL_FIRST_PASS_TMR_EN_ENABLE_FVAL                                0x1
#define HWIO_AOSS_CC_RESET_FSM_CTRL_FIRST_PASS_COMPLETE_BMSK                                     0x2
#define HWIO_AOSS_CC_RESET_FSM_CTRL_FIRST_PASS_COMPLETE_SHFT                                     0x1
#define HWIO_AOSS_CC_RESET_FSM_CTRL_FIRST_PASS_COMPLETE_NOT_DONE_FVAL                            0x0
#define HWIO_AOSS_CC_RESET_FSM_CTRL_FIRST_PASS_COMPLETE_DONE_FVAL                                0x1
#define HWIO_AOSS_CC_RESET_FSM_CTRL_BLOCK_RESIN_BMSK                                             0x1
#define HWIO_AOSS_CC_RESET_FSM_CTRL_BLOCK_RESIN_SHFT                                             0x0
#define HWIO_AOSS_CC_RESET_FSM_CTRL_BLOCK_RESIN_UNBLOCK_FVAL                                     0x0
#define HWIO_AOSS_CC_RESET_FSM_CTRL_BLOCK_RESIN_BLOCK_FVAL                                       0x1

#define HWIO_AOSS_CC_WIND_DOWN_TIMER_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050008)
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00050008)
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_RMSK                                                 0xffffffff
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_IN          \
        in_dword(HWIO_AOSS_CC_WIND_DOWN_TIMER_ADDR)
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_WIND_DOWN_TIMER_ADDR, m)
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_OUT(v)      \
        out_dword(HWIO_AOSS_CC_WIND_DOWN_TIMER_ADDR,v)
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_WIND_DOWN_TIMER_ADDR,m,v,HWIO_AOSS_CC_WIND_DOWN_TIMER_IN)
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_RESERVE_BITS31_16_BMSK                               0xffff0000
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_RESERVE_BITS31_16_SHFT                                     0x10
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_TIMER_VAL_BMSK                                           0xffff
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_TIMER_VAL_SHFT                                              0x0

#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_ADDR                                             (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0005000c)
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_OFFS                                             (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0005000c)
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_RMSK                                             0xffffffff
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_IN          \
        in_dword(HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_ADDR)
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_ADDR, m)
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_ADDR,v)
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_ADDR,m,v,HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_IN)
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_RESERVE_BITS31_16_BMSK                           0xffff0000
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_RESERVE_BITS31_16_SHFT                                 0x10
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_TIMER_VAL_BMSK                                       0xffff
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_TIMER_VAL_SHFT                                          0x0

#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_ADDR                                              (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050010)
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_OFFS                                              (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00050010)
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_RMSK                                              0xffffffff
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_IN          \
        in_dword(HWIO_AOSS_CC_STOP_CAPTURE_TIMER_ADDR)
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_STOP_CAPTURE_TIMER_ADDR, m)
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_OUT(v)      \
        out_dword(HWIO_AOSS_CC_STOP_CAPTURE_TIMER_ADDR,v)
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_STOP_CAPTURE_TIMER_ADDR,m,v,HWIO_AOSS_CC_STOP_CAPTURE_TIMER_IN)
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_RESERVE_BITS31_16_BMSK                            0xffff0000
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_RESERVE_BITS31_16_SHFT                                  0x10
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_TIMER_VAL_BMSK                                        0xffff
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_TIMER_VAL_SHFT                                           0x0

#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_ADDR                                         (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050014)
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_OFFS                                         (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00050014)
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_RMSK                                         0xffffffff
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_IN          \
        in_dword(HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_ADDR)
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_ADDR, m)
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_ADDR,v)
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_ADDR,m,v,HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_IN)
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_RESERVE_BITS31_16_BMSK                       0xffff0000
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_RESERVE_BITS31_16_SHFT                             0x10
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_TIMER_VAL_BMSK                                   0xffff
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_TIMER_VAL_SHFT                                      0x0

#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_ADDR                                              (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050018)
#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_OFFS                                              (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00050018)
#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_RMSK                                              0xffffffff
#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_IN          \
        in_dword(HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_ADDR)
#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_ADDR, m)
#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_OUT(v)      \
        out_dword(HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_ADDR,v)
#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_ADDR,m,v,HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_IN)
#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_TIMER_VAL_BMSK                                    0xffffffff
#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_TIMER_VAL_SHFT                                           0x0

#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_ADDR                                             (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0005001c)
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_OFFS                                             (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0005001c)
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_RMSK                                             0xffffffff
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_IN          \
        in_dword(HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_ADDR)
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_ADDR, m)
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_ADDR,v)
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_ADDR,m,v,HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_IN)
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_RESERVE_BITS31_8_BMSK                            0xffffff00
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_RESERVE_BITS31_8_SHFT                                   0x8
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_TIMER_VAL_BMSK                                         0xff
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_TIMER_VAL_SHFT                                          0x0

#define HWIO_AOSS_CC_RESET_STATUS_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050020)
#define HWIO_AOSS_CC_RESET_STATUS_OFFS                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00050020)
#define HWIO_AOSS_CC_RESET_STATUS_RMSK                                                        0x3fff
#define HWIO_AOSS_CC_RESET_STATUS_IN          \
        in_dword(HWIO_AOSS_CC_RESET_STATUS_ADDR)
#define HWIO_AOSS_CC_RESET_STATUS_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RESET_STATUS_ADDR, m)
#define HWIO_AOSS_CC_RESET_STATUS_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RESET_STATUS_ADDR,v)
#define HWIO_AOSS_CC_RESET_STATUS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RESET_STATUS_ADDR,m,v,HWIO_AOSS_CC_RESET_STATUS_IN)
#define HWIO_AOSS_CC_RESET_STATUS_PCIE_MIMO_BASED_RESET_STATUS_BMSK                           0x2000
#define HWIO_AOSS_CC_RESET_STATUS_PCIE_MIMO_BASED_RESET_STATUS_SHFT                              0xd
#define HWIO_AOSS_CC_RESET_STATUS_PERST_TIMEOUT_RESET_STATUS_BMSK                             0x1000
#define HWIO_AOSS_CC_RESET_STATUS_PERST_TIMEOUT_RESET_STATUS_SHFT                                0xc
#define HWIO_AOSS_CC_RESET_STATUS_PERST_RAW_RESET_STATUS_BMSK                                  0x800
#define HWIO_AOSS_CC_RESET_STATUS_PERST_RAW_RESET_STATUS_SHFT                                    0xb
#define HWIO_AOSS_CC_RESET_STATUS_PERST_RESET_STATUS_BMSK                                      0x400
#define HWIO_AOSS_CC_RESET_STATUS_PERST_RESET_STATUS_SHFT                                        0xa
#define HWIO_AOSS_CC_RESET_STATUS_PS_HOLD_STATUS_BMSK                                          0x200
#define HWIO_AOSS_CC_RESET_STATUS_PS_HOLD_STATUS_SHFT                                            0x9
#define HWIO_AOSS_CC_RESET_STATUS_QDSS_SW_SRST_RESET_STATUS_BMSK                               0x100
#define HWIO_AOSS_CC_RESET_STATUS_QDSS_SW_SRST_RESET_STATUS_SHFT                                 0x8
#define HWIO_AOSS_CC_RESET_STATUS_EUD_SRST_RESET_STATUS_BMSK                                    0x80
#define HWIO_AOSS_CC_RESET_STATUS_EUD_SRST_RESET_STATUS_SHFT                                     0x7
#define HWIO_AOSS_CC_RESET_STATUS_PMIC_ABNORMAL_RESIN_RESET_STATUS_BMSK                         0x40
#define HWIO_AOSS_CC_RESET_STATUS_PMIC_ABNORMAL_RESIN_RESET_STATUS_SHFT                          0x6
#define HWIO_AOSS_CC_RESET_STATUS_MSM_TSENSE1_RESET_STATUS_BMSK                                 0x20
#define HWIO_AOSS_CC_RESET_STATUS_MSM_TSENSE1_RESET_STATUS_SHFT                                  0x5
#define HWIO_AOSS_CC_RESET_STATUS_PROC_HALT_CTI_STATUS_BMSK                                     0x10
#define HWIO_AOSS_CC_RESET_STATUS_PROC_HALT_CTI_STATUS_SHFT                                      0x4
#define HWIO_AOSS_CC_RESET_STATUS_PROC_HALT_CTI_STATUS_NO_HALT_FVAL                              0x0
#define HWIO_AOSS_CC_RESET_STATUS_PROC_HALT_CTI_STATUS_HALT_FVAL                                 0x1
#define HWIO_AOSS_CC_RESET_STATUS_SRST_RESET_STATUS_BMSK                                         0x8
#define HWIO_AOSS_CC_RESET_STATUS_SRST_RESET_STATUS_SHFT                                         0x3
#define HWIO_AOSS_CC_RESET_STATUS_MSM_TSENSE0_RESET_STATUS_BMSK                                  0x4
#define HWIO_AOSS_CC_RESET_STATUS_MSM_TSENSE0_RESET_STATUS_SHFT                                  0x2
#define HWIO_AOSS_CC_RESET_STATUS_PMIC_RESIN_RESET_STATUS_BMSK                                   0x2
#define HWIO_AOSS_CC_RESET_STATUS_PMIC_RESIN_RESET_STATUS_SHFT                                   0x1
#define HWIO_AOSS_CC_RESET_STATUS_SECURE_WDOG_EXPIRE_RESET_STATUS_BMSK                           0x1
#define HWIO_AOSS_CC_RESET_STATUS_SECURE_WDOG_EXPIRE_RESET_STATUS_SHFT                           0x0

#define HWIO_AOSS_CC_RESET_FSM_STATUS_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050024)
#define HWIO_AOSS_CC_RESET_FSM_STATUS_OFFS                                                (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00050024)
#define HWIO_AOSS_CC_RESET_FSM_STATUS_RMSK                                                   0xfffff
#define HWIO_AOSS_CC_RESET_FSM_STATUS_IN          \
        in_dword(HWIO_AOSS_CC_RESET_FSM_STATUS_ADDR)
#define HWIO_AOSS_CC_RESET_FSM_STATUS_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RESET_FSM_STATUS_ADDR, m)
#define HWIO_AOSS_CC_RESET_FSM_STATUS_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RESET_FSM_STATUS_ADDR,v)
#define HWIO_AOSS_CC_RESET_FSM_STATUS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RESET_FSM_STATUS_ADDR,m,v,HWIO_AOSS_CC_RESET_FSM_STATUS_IN)
#define HWIO_AOSS_CC_RESET_FSM_STATUS_PCIE_LINK_DN_REQ_BMSK                                  0x80000
#define HWIO_AOSS_CC_RESET_FSM_STATUS_PCIE_LINK_DN_REQ_SHFT                                     0x13
#define HWIO_AOSS_CC_RESET_FSM_STATUS_PCIE_LINK_DN_ACK_BMSK                                  0x40000
#define HWIO_AOSS_CC_RESET_FSM_STATUS_PCIE_LINK_DN_ACK_SHFT                                     0x12
#define HWIO_AOSS_CC_RESET_FSM_STATUS_BLOCK_PCIE_ARES_BMSK                                   0x20000
#define HWIO_AOSS_CC_RESET_FSM_STATUS_BLOCK_PCIE_ARES_SHFT                                      0x11
#define HWIO_AOSS_CC_RESET_FSM_STATUS_ALLOW_PCIE_ARES_BMSK                                   0x10000
#define HWIO_AOSS_CC_RESET_FSM_STATUS_ALLOW_PCIE_ARES_SHFT                                      0x10
#define HWIO_AOSS_CC_RESET_FSM_STATUS_PCIE_LINK_TMR_LD_BMSK                                   0x8000
#define HWIO_AOSS_CC_RESET_FSM_STATUS_PCIE_LINK_TMR_LD_SHFT                                      0xf
#define HWIO_AOSS_CC_RESET_FSM_STATUS_PCIE_LINK_TMR_EXPIRE_BMSK                               0x4000
#define HWIO_AOSS_CC_RESET_FSM_STATUS_PCIE_LINK_TMR_EXPIRE_SHFT                                  0xe
#define HWIO_AOSS_CC_RESET_FSM_STATUS_DBG_PDC_HANG_STATUS_BMSK                                0x2000
#define HWIO_AOSS_CC_RESET_FSM_STATUS_DBG_PDC_HANG_STATUS_SHFT                                   0xd
#define HWIO_AOSS_CC_RESET_FSM_STATUS_DBG_PDC_TRIGGER_BMSK                                    0x1000
#define HWIO_AOSS_CC_RESET_FSM_STATUS_DBG_PDC_TRIGGER_SHFT                                       0xc
#define HWIO_AOSS_CC_RESET_FSM_STATUS_NORM_WKUP_HANG_STATUS_BMSK                               0x800
#define HWIO_AOSS_CC_RESET_FSM_STATUS_NORM_WKUP_HANG_STATUS_SHFT                                 0xb
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FIRST_PASS_EXPIRE_BMSK                                   0x400
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FIRST_PASS_EXPIRE_SHFT                                     0xa
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FIRST_PASS_TIMER_LD_BMSK                                 0x200
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FIRST_PASS_TIMER_LD_SHFT                                   0x9
#define HWIO_AOSS_CC_RESET_FSM_STATUS_BLOCK_RESIN_ASET_BMSK                                    0x100
#define HWIO_AOSS_CC_RESET_FSM_STATUS_BLOCK_RESIN_ASET_SHFT                                      0x8
#define HWIO_AOSS_CC_RESET_FSM_STATUS_BLOCK_RESIN_ARES_BMSK                                     0x80
#define HWIO_AOSS_CC_RESET_FSM_STATUS_BLOCK_RESIN_ARES_SHFT                                      0x7
#define HWIO_AOSS_CC_RESET_FSM_STATUS_DBG_TIMER_TRIGGER_BMSK                                    0x40
#define HWIO_AOSS_CC_RESET_FSM_STATUS_DBG_TIMER_TRIGGER_SHFT                                     0x6
#define HWIO_AOSS_CC_RESET_FSM_STATUS_RESET_DEBUG_READY_BMSK                                    0x20
#define HWIO_AOSS_CC_RESET_FSM_STATUS_RESET_DEBUG_READY_SHFT                                     0x5
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FIRST_PASS_BMSK                                           0x10
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FIRST_PASS_SHFT                                            0x4
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FSM_STATE_BMSK                                             0xf
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FSM_STATE_SHFT                                             0x0
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FSM_STATE_POR_ST_FVAL                                      0x0
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FSM_STATE_IDLE_ST_FVAL                                     0x1
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FSM_STATE_NORMAL_RESET_ST_FVAL                             0x2
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FSM_STATE_BLOCK_RESIN_ST_FVAL                              0x3
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FSM_STATE_DBG_TIMER_WAIT_ST_FVAL                           0x4
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FSM_STATE_ALLOW_RESIN_FIRST_PASS_ST_FVAL                   0x5
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FSM_STATE_FIRST_PASS_ST_FVAL                               0x6
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FSM_STATE_ALLOW_RESIN_SECOND_PASS_ST_FVAL                  0x7
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FSM_STATE_NORM_WKUP_IN_DBG_ST_FVAL                         0x8
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FSM_STATE_ABNORM_BRINGUP_IN_DBG_ST_FVAL                    0x9
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FSM_STATE_PCIE_LINK_CHK_IN_NORMAL_RST_ST_FVAL              0xa
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FSM_STATE_PCIE_LINK_CHK_IN_DBG_ST_FVAL                     0xb

#define HWIO_AOSS_CC_TIC_MISC_ADDR                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050028)
#define HWIO_AOSS_CC_TIC_MISC_OFFS                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00050028)
#define HWIO_AOSS_CC_TIC_MISC_RMSK                                                               0x3
#define HWIO_AOSS_CC_TIC_MISC_IN          \
        in_dword(HWIO_AOSS_CC_TIC_MISC_ADDR)
#define HWIO_AOSS_CC_TIC_MISC_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_TIC_MISC_ADDR, m)
#define HWIO_AOSS_CC_TIC_MISC_OUT(v)      \
        out_dword(HWIO_AOSS_CC_TIC_MISC_ADDR,v)
#define HWIO_AOSS_CC_TIC_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_TIC_MISC_ADDR,m,v,HWIO_AOSS_CC_TIC_MISC_IN)
#define HWIO_AOSS_CC_TIC_MISC_APCS_SANS_BOOT_PROC_RESET_IN_TIC_BMSK                              0x2
#define HWIO_AOSS_CC_TIC_MISC_APCS_SANS_BOOT_PROC_RESET_IN_TIC_SHFT                              0x1
#define HWIO_AOSS_CC_TIC_MISC_APCS_SANS_BOOT_PROC_RESET_IN_TIC_REMOVE_RESET_FVAL                 0x0
#define HWIO_AOSS_CC_TIC_MISC_APCS_SANS_BOOT_PROC_RESET_IN_TIC_APPLY_RESET_FVAL                  0x1
#define HWIO_AOSS_CC_TIC_MISC_BOOT_PROC_RESET_IN_TIC_BMSK                                        0x1
#define HWIO_AOSS_CC_TIC_MISC_BOOT_PROC_RESET_IN_TIC_SHFT                                        0x0
#define HWIO_AOSS_CC_TIC_MISC_BOOT_PROC_RESET_IN_TIC_REMOVE_RESET_FVAL                           0x0
#define HWIO_AOSS_CC_TIC_MISC_BOOT_PROC_RESET_IN_TIC_APPLY_RESET_FVAL                            0x1

#define HWIO_AOSS_CC_APCS_MISC_ADDR                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00051000)
#define HWIO_AOSS_CC_APCS_MISC_OFFS                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00051000)
#define HWIO_AOSS_CC_APCS_MISC_RMSK                                                              0x1
#define HWIO_AOSS_CC_APCS_MISC_IN          \
        in_dword(HWIO_AOSS_CC_APCS_MISC_ADDR)
#define HWIO_AOSS_CC_APCS_MISC_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_APCS_MISC_ADDR, m)
#define HWIO_AOSS_CC_APCS_MISC_OUT(v)      \
        out_dword(HWIO_AOSS_CC_APCS_MISC_ADDR,v)
#define HWIO_AOSS_CC_APCS_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_APCS_MISC_ADDR,m,v,HWIO_AOSS_CC_APCS_MISC_IN)
#define HWIO_AOSS_CC_APCS_MISC_AOP_RESET_BMSK                                                    0x1
#define HWIO_AOSS_CC_APCS_MISC_AOP_RESET_SHFT                                                    0x0
#define HWIO_AOSS_CC_APCS_MISC_AOP_RESET_REMOVE_RESET_FVAL                                       0x0
#define HWIO_AOSS_CC_APCS_MISC_AOP_RESET_APPLY_RESET_FVAL                                        0x1

#define HWIO_AOSS_CC_APCS_RESET_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0005002c)
#define HWIO_AOSS_CC_APCS_RESET_OFFS                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0005002c)
#define HWIO_AOSS_CC_APCS_RESET_RMSK                                                             0x3
#define HWIO_AOSS_CC_APCS_RESET_IN          \
        in_dword(HWIO_AOSS_CC_APCS_RESET_ADDR)
#define HWIO_AOSS_CC_APCS_RESET_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_APCS_RESET_ADDR, m)
#define HWIO_AOSS_CC_APCS_RESET_OUT(v)      \
        out_dword(HWIO_AOSS_CC_APCS_RESET_ADDR,v)
#define HWIO_AOSS_CC_APCS_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_APCS_RESET_ADDR,m,v,HWIO_AOSS_CC_APCS_RESET_IN)
#define HWIO_AOSS_CC_APCS_RESET_APCS_SANS_BOOT_PROC_RESET_BMSK                                   0x2
#define HWIO_AOSS_CC_APCS_RESET_APCS_SANS_BOOT_PROC_RESET_SHFT                                   0x1
#define HWIO_AOSS_CC_APCS_RESET_APCS_SANS_BOOT_PROC_RESET_REMOVE_RESET_FVAL                      0x0
#define HWIO_AOSS_CC_APCS_RESET_APCS_SANS_BOOT_PROC_RESET_APPLY_RESET_FVAL                       0x1
#define HWIO_AOSS_CC_APCS_RESET_BOOT_PROC_RESET_BMSK                                             0x1
#define HWIO_AOSS_CC_APCS_RESET_BOOT_PROC_RESET_SHFT                                             0x0
#define HWIO_AOSS_CC_APCS_RESET_BOOT_PROC_RESET_REMOVE_RESET_FVAL                                0x0
#define HWIO_AOSS_CC_APCS_RESET_BOOT_PROC_RESET_APPLY_RESET_FVAL                                 0x1

#define HWIO_AOSS_CC_MSS_RESTART_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00010000)
#define HWIO_AOSS_CC_MSS_RESTART_OFFS                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00010000)
#define HWIO_AOSS_CC_MSS_RESTART_RMSK                                                            0x1
#define HWIO_AOSS_CC_MSS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_MSS_RESTART_ADDR)
#define HWIO_AOSS_CC_MSS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_MSS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_MSS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_MSS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_MSS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_MSS_RESTART_ADDR,m,v,HWIO_AOSS_CC_MSS_RESTART_IN)
#define HWIO_AOSS_CC_MSS_RESTART_SS_RESTART_BMSK                                                 0x1
#define HWIO_AOSS_CC_MSS_RESTART_SS_RESTART_SHFT                                                 0x0
#define HWIO_AOSS_CC_MSS_RESTART_SS_RESTART_REMOVE_RESET_FVAL                                    0x0
#define HWIO_AOSS_CC_MSS_RESTART_SS_RESTART_APPLY_RESET_FVAL                                     0x1

#define HWIO_AOSS_CC_CAMSS_RESTART_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00011000)
#define HWIO_AOSS_CC_CAMSS_RESTART_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00011000)
#define HWIO_AOSS_CC_CAMSS_RESTART_RMSK                                                          0x1
#define HWIO_AOSS_CC_CAMSS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_CAMSS_RESTART_ADDR)
#define HWIO_AOSS_CC_CAMSS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_CAMSS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_CAMSS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_CAMSS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_CAMSS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_CAMSS_RESTART_ADDR,m,v,HWIO_AOSS_CC_CAMSS_RESTART_IN)
#define HWIO_AOSS_CC_CAMSS_RESTART_SS_RESTART_BMSK                                               0x1
#define HWIO_AOSS_CC_CAMSS_RESTART_SS_RESTART_SHFT                                               0x0
#define HWIO_AOSS_CC_CAMSS_RESTART_SS_RESTART_REMOVE_RESET_FVAL                                  0x0
#define HWIO_AOSS_CC_CAMSS_RESTART_SS_RESTART_APPLY_RESET_FVAL                                   0x1

#define HWIO_AOSS_CC_VENUS_RESTART_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00012000)
#define HWIO_AOSS_CC_VENUS_RESTART_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00012000)
#define HWIO_AOSS_CC_VENUS_RESTART_RMSK                                                          0x1
#define HWIO_AOSS_CC_VENUS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_VENUS_RESTART_ADDR)
#define HWIO_AOSS_CC_VENUS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_VENUS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_VENUS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_VENUS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_VENUS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_VENUS_RESTART_ADDR,m,v,HWIO_AOSS_CC_VENUS_RESTART_IN)
#define HWIO_AOSS_CC_VENUS_RESTART_SS_RESTART_BMSK                                               0x1
#define HWIO_AOSS_CC_VENUS_RESTART_SS_RESTART_SHFT                                               0x0
#define HWIO_AOSS_CC_VENUS_RESTART_SS_RESTART_REMOVE_RESET_FVAL                                  0x0
#define HWIO_AOSS_CC_VENUS_RESTART_SS_RESTART_APPLY_RESET_FVAL                                   0x1

#define HWIO_AOSS_CC_GPU_RESTART_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00013000)
#define HWIO_AOSS_CC_GPU_RESTART_OFFS                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00013000)
#define HWIO_AOSS_CC_GPU_RESTART_RMSK                                                            0x1
#define HWIO_AOSS_CC_GPU_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_GPU_RESTART_ADDR)
#define HWIO_AOSS_CC_GPU_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_GPU_RESTART_ADDR, m)
#define HWIO_AOSS_CC_GPU_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_GPU_RESTART_ADDR,v)
#define HWIO_AOSS_CC_GPU_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_GPU_RESTART_ADDR,m,v,HWIO_AOSS_CC_GPU_RESTART_IN)
#define HWIO_AOSS_CC_GPU_RESTART_SS_RESTART_BMSK                                                 0x1
#define HWIO_AOSS_CC_GPU_RESTART_SS_RESTART_SHFT                                                 0x0
#define HWIO_AOSS_CC_GPU_RESTART_SS_RESTART_REMOVE_RESET_FVAL                                    0x0
#define HWIO_AOSS_CC_GPU_RESTART_SS_RESTART_APPLY_RESET_FVAL                                     0x1

#define HWIO_AOSS_CC_DISPSS_RESTART_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00014000)
#define HWIO_AOSS_CC_DISPSS_RESTART_OFFS                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00014000)
#define HWIO_AOSS_CC_DISPSS_RESTART_RMSK                                                         0x1
#define HWIO_AOSS_CC_DISPSS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_DISPSS_RESTART_ADDR)
#define HWIO_AOSS_CC_DISPSS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_DISPSS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_DISPSS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_DISPSS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_DISPSS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_DISPSS_RESTART_ADDR,m,v,HWIO_AOSS_CC_DISPSS_RESTART_IN)
#define HWIO_AOSS_CC_DISPSS_RESTART_SS_RESTART_BMSK                                              0x1
#define HWIO_AOSS_CC_DISPSS_RESTART_SS_RESTART_SHFT                                              0x0
#define HWIO_AOSS_CC_DISPSS_RESTART_SS_RESTART_REMOVE_RESET_FVAL                                 0x0
#define HWIO_AOSS_CC_DISPSS_RESTART_SS_RESTART_APPLY_RESET_FVAL                                  0x1

#define HWIO_AOSS_CC_WCSS_RESTART_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00020000)
#define HWIO_AOSS_CC_WCSS_RESTART_OFFS                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00020000)
#define HWIO_AOSS_CC_WCSS_RESTART_RMSK                                                           0x1
#define HWIO_AOSS_CC_WCSS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_WCSS_RESTART_ADDR)
#define HWIO_AOSS_CC_WCSS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_WCSS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_WCSS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_WCSS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_WCSS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_WCSS_RESTART_ADDR,m,v,HWIO_AOSS_CC_WCSS_RESTART_IN)
#define HWIO_AOSS_CC_WCSS_RESTART_SS_RESTART_BMSK                                                0x1
#define HWIO_AOSS_CC_WCSS_RESTART_SS_RESTART_SHFT                                                0x0
#define HWIO_AOSS_CC_WCSS_RESTART_SS_RESTART_REMOVE_RESET_FVAL                                   0x0
#define HWIO_AOSS_CC_WCSS_RESTART_SS_RESTART_APPLY_RESET_FVAL                                    0x1

#define HWIO_AOSS_CC_GSS_RESTART_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00021000)
#define HWIO_AOSS_CC_GSS_RESTART_OFFS                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00021000)
#define HWIO_AOSS_CC_GSS_RESTART_RMSK                                                            0x1
#define HWIO_AOSS_CC_GSS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_GSS_RESTART_ADDR)
#define HWIO_AOSS_CC_GSS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_GSS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_GSS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_GSS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_GSS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_GSS_RESTART_ADDR,m,v,HWIO_AOSS_CC_GSS_RESTART_IN)
#define HWIO_AOSS_CC_GSS_RESTART_SS_RESTART_BMSK                                                 0x1
#define HWIO_AOSS_CC_GSS_RESTART_SS_RESTART_SHFT                                                 0x0
#define HWIO_AOSS_CC_GSS_RESTART_SS_RESTART_REMOVE_RESET_FVAL                                    0x0
#define HWIO_AOSS_CC_GSS_RESTART_SS_RESTART_APPLY_RESET_FVAL                                     0x1

#define HWIO_AOSS_CC_LPASS_RESTART_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00030000)
#define HWIO_AOSS_CC_LPASS_RESTART_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00030000)
#define HWIO_AOSS_CC_LPASS_RESTART_RMSK                                                          0x1
#define HWIO_AOSS_CC_LPASS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_LPASS_RESTART_ADDR)
#define HWIO_AOSS_CC_LPASS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_LPASS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_LPASS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_LPASS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_LPASS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_LPASS_RESTART_ADDR,m,v,HWIO_AOSS_CC_LPASS_RESTART_IN)
#define HWIO_AOSS_CC_LPASS_RESTART_SS_RESTART_BMSK                                               0x1
#define HWIO_AOSS_CC_LPASS_RESTART_SS_RESTART_SHFT                                               0x0
#define HWIO_AOSS_CC_LPASS_RESTART_SS_RESTART_REMOVE_RESET_FVAL                                  0x0
#define HWIO_AOSS_CC_LPASS_RESTART_SS_RESTART_APPLY_RESET_FVAL                                   0x1

#define HWIO_AOSS_CC_NPU_RESTART_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00030004)
#define HWIO_AOSS_CC_NPU_RESTART_OFFS                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00030004)
#define HWIO_AOSS_CC_NPU_RESTART_RMSK                                                            0x1
#define HWIO_AOSS_CC_NPU_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_NPU_RESTART_ADDR)
#define HWIO_AOSS_CC_NPU_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_NPU_RESTART_ADDR, m)
#define HWIO_AOSS_CC_NPU_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_NPU_RESTART_ADDR,v)
#define HWIO_AOSS_CC_NPU_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_NPU_RESTART_ADDR,m,v,HWIO_AOSS_CC_NPU_RESTART_IN)
#define HWIO_AOSS_CC_NPU_RESTART_SS_RESTART_BMSK                                                 0x1
#define HWIO_AOSS_CC_NPU_RESTART_SS_RESTART_SHFT                                                 0x0
#define HWIO_AOSS_CC_NPU_RESTART_SS_RESTART_REMOVE_RESET_FVAL                                    0x0
#define HWIO_AOSS_CC_NPU_RESTART_SS_RESTART_APPLY_RESET_FVAL                                     0x1

#define HWIO_AOSS_CC_SENSORS_RESTART_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00031000)
#define HWIO_AOSS_CC_SENSORS_RESTART_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00031000)
#define HWIO_AOSS_CC_SENSORS_RESTART_RMSK                                                        0x1
#define HWIO_AOSS_CC_SENSORS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_SENSORS_RESTART_ADDR)
#define HWIO_AOSS_CC_SENSORS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SENSORS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_SENSORS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SENSORS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_SENSORS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SENSORS_RESTART_ADDR,m,v,HWIO_AOSS_CC_SENSORS_RESTART_IN)
#define HWIO_AOSS_CC_SENSORS_RESTART_SS_RESTART_BMSK                                             0x1
#define HWIO_AOSS_CC_SENSORS_RESTART_SS_RESTART_SHFT                                             0x0
#define HWIO_AOSS_CC_SENSORS_RESTART_SS_RESTART_REMOVE_RESET_FVAL                                0x0
#define HWIO_AOSS_CC_SENSORS_RESTART_SS_RESTART_APPLY_RESET_FVAL                                 0x1

#define HWIO_AOSS_CC_SPSS_RESTART_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00032000)
#define HWIO_AOSS_CC_SPSS_RESTART_OFFS                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00032000)
#define HWIO_AOSS_CC_SPSS_RESTART_RMSK                                                           0x1
#define HWIO_AOSS_CC_SPSS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_SPSS_RESTART_ADDR)
#define HWIO_AOSS_CC_SPSS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPSS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_SPSS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPSS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_SPSS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPSS_RESTART_ADDR,m,v,HWIO_AOSS_CC_SPSS_RESTART_IN)
#define HWIO_AOSS_CC_SPSS_RESTART_SS_RESTART_BMSK                                                0x1
#define HWIO_AOSS_CC_SPSS_RESTART_SS_RESTART_SHFT                                                0x0
#define HWIO_AOSS_CC_SPSS_RESTART_SS_RESTART_REMOVE_RESET_FVAL                                   0x0
#define HWIO_AOSS_CC_SPSS_RESTART_SS_RESTART_APPLY_RESET_FVAL                                    0x1

#define HWIO_AOSS_CC_COMPUTESS_RESTART_ADDR                                               (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00040000)
#define HWIO_AOSS_CC_COMPUTESS_RESTART_OFFS                                               (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00040000)
#define HWIO_AOSS_CC_COMPUTESS_RESTART_RMSK                                                      0x1
#define HWIO_AOSS_CC_COMPUTESS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_COMPUTESS_RESTART_ADDR)
#define HWIO_AOSS_CC_COMPUTESS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_COMPUTESS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_COMPUTESS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_COMPUTESS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_COMPUTESS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_COMPUTESS_RESTART_ADDR,m,v,HWIO_AOSS_CC_COMPUTESS_RESTART_IN)
#define HWIO_AOSS_CC_COMPUTESS_RESTART_SS_RESTART_BMSK                                           0x1
#define HWIO_AOSS_CC_COMPUTESS_RESTART_SS_RESTART_SHFT                                           0x0
#define HWIO_AOSS_CC_COMPUTESS_RESTART_SS_RESTART_REMOVE_RESET_FVAL                              0x0
#define HWIO_AOSS_CC_COMPUTESS_RESTART_SS_RESTART_APPLY_RESET_FVAL                               0x1

#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_ADDR                                             (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050034)
#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_OFFS                                             (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00050034)
#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_RMSK                                             0xffffffff
#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_IN          \
        in_dword(HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_ADDR)
#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_ADDR, m)
#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_OUT(v)      \
        out_dword(HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_ADDR,v)
#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_ADDR,m,v,HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_IN)
#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_TIMER_VAL_BMSK                                   0xffffffff
#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_TIMER_VAL_SHFT                                          0x0

#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000301c)
#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_OFFS                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000301c)
#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_RMSK                                                        0x1
#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_IN          \
        in_dword(HWIO_AOSS_CC_DEBUG_HW_EVENTS_ADDR)
#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_DEBUG_HW_EVENTS_ADDR, m)
#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_OUT(v)      \
        out_dword(HWIO_AOSS_CC_DEBUG_HW_EVENTS_ADDR,v)
#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_DEBUG_HW_EVENTS_ADDR,m,v,HWIO_AOSS_CC_DEBUG_HW_EVENTS_IN)
#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_MUX_SEL_BMSK                                                0x1
#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_MUX_SEL_SHFT                                                0x0

#define HWIO_AOSS_CC_AOP_MISC_ADDR                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003020)
#define HWIO_AOSS_CC_AOP_MISC_OFFS                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00003020)
#define HWIO_AOSS_CC_AOP_MISC_RMSK                                                               0x1
#define HWIO_AOSS_CC_AOP_MISC_IN          \
        in_dword(HWIO_AOSS_CC_AOP_MISC_ADDR)
#define HWIO_AOSS_CC_AOP_MISC_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_MISC_ADDR, m)
#define HWIO_AOSS_CC_AOP_MISC_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_MISC_ADDR,v)
#define HWIO_AOSS_CC_AOP_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_MISC_ADDR,m,v,HWIO_AOSS_CC_AOP_MISC_IN)
#define HWIO_AOSS_CC_AOP_MISC_AUTO_SCALE_DIS_BMSK                                                0x1
#define HWIO_AOSS_CC_AOP_MISC_AUTO_SCALE_DIS_SHFT                                                0x0
#define HWIO_AOSS_CC_AOP_MISC_AUTO_SCALE_DIS_SCALE_NOT_DISABLE_FVAL                              0x0
#define HWIO_AOSS_CC_AOP_MISC_AUTO_SCALE_DIS_SCALE_DISABLE_FVAL                                  0x1

#define HWIO_AOSS_CC_PLL0_MODE_SEL_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003000)
#define HWIO_AOSS_CC_PLL0_MODE_SEL_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00003000)
#define HWIO_AOSS_CC_PLL0_MODE_SEL_RMSK                                                   0xffffffff
#define HWIO_AOSS_CC_PLL0_MODE_SEL_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_MODE_SEL_ADDR)
#define HWIO_AOSS_CC_PLL0_MODE_SEL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_MODE_SEL_ADDR, m)
#define HWIO_AOSS_CC_PLL0_MODE_SEL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_MODE_SEL_ADDR,v)
#define HWIO_AOSS_CC_PLL0_MODE_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_MODE_SEL_ADDR,m,v,HWIO_AOSS_CC_PLL0_MODE_SEL_IN)
#define HWIO_AOSS_CC_PLL0_MODE_SEL_RESERVE_BITS31_1_BMSK                                  0xfffffffe
#define HWIO_AOSS_CC_PLL0_MODE_SEL_RESERVE_BITS31_1_SHFT                                         0x1
#define HWIO_AOSS_CC_PLL0_MODE_SEL_SELECT_BIT0_BMSK                                              0x1
#define HWIO_AOSS_CC_PLL0_MODE_SEL_SELECT_BIT0_SHFT                                              0x0

#define HWIO_AOSS_CC_PLL1_OUTCTRL_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003024)
#define HWIO_AOSS_CC_PLL1_OUTCTRL_OFFS                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00003024)
#define HWIO_AOSS_CC_PLL1_OUTCTRL_RMSK                                                           0x1
#define HWIO_AOSS_CC_PLL1_OUTCTRL_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_OUTCTRL_ADDR)
#define HWIO_AOSS_CC_PLL1_OUTCTRL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_OUTCTRL_ADDR, m)
#define HWIO_AOSS_CC_PLL1_OUTCTRL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_OUTCTRL_ADDR,v)
#define HWIO_AOSS_CC_PLL1_OUTCTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_OUTCTRL_ADDR,m,v,HWIO_AOSS_CC_PLL1_OUTCTRL_IN)
#define HWIO_AOSS_CC_PLL1_OUTCTRL_SEL_BMSK                                                       0x1
#define HWIO_AOSS_CC_PLL1_OUTCTRL_SEL_SHFT                                                       0x0
#define HWIO_AOSS_CC_PLL1_OUTCTRL_SEL_WITHOUT_LOCKDETECT_FVAL                                    0x0
#define HWIO_AOSS_CC_PLL1_OUTCTRL_SEL_WITH_LOCKDETECT_FVAL                                       0x1

#define HWIO_AOSS_CC_PLL1_MODE_SEL_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003028)
#define HWIO_AOSS_CC_PLL1_MODE_SEL_OFFS                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00003028)
#define HWIO_AOSS_CC_PLL1_MODE_SEL_RMSK                                                   0xffffffff
#define HWIO_AOSS_CC_PLL1_MODE_SEL_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_MODE_SEL_ADDR)
#define HWIO_AOSS_CC_PLL1_MODE_SEL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_MODE_SEL_ADDR, m)
#define HWIO_AOSS_CC_PLL1_MODE_SEL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_MODE_SEL_ADDR,v)
#define HWIO_AOSS_CC_PLL1_MODE_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_MODE_SEL_ADDR,m,v,HWIO_AOSS_CC_PLL1_MODE_SEL_IN)
#define HWIO_AOSS_CC_PLL1_MODE_SEL_RESERVE_BITS31_1_BMSK                                  0xfffffffe
#define HWIO_AOSS_CC_PLL1_MODE_SEL_RESERVE_BITS31_1_SHFT                                         0x1
#define HWIO_AOSS_CC_PLL1_MODE_SEL_SELECT_BIT0_BMSK                                              0x1
#define HWIO_AOSS_CC_PLL1_MODE_SEL_SELECT_BIT0_SHFT                                              0x0

#define HWIO_AOSS_CC_SPARE2_REG_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000302c)
#define HWIO_AOSS_CC_SPARE2_REG_OFFS                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x0000302c)
#define HWIO_AOSS_CC_SPARE2_REG_RMSK                                                      0xffffffff
#define HWIO_AOSS_CC_SPARE2_REG_IN          \
        in_dword(HWIO_AOSS_CC_SPARE2_REG_ADDR)
#define HWIO_AOSS_CC_SPARE2_REG_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPARE2_REG_ADDR, m)
#define HWIO_AOSS_CC_SPARE2_REG_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPARE2_REG_ADDR,v)
#define HWIO_AOSS_CC_SPARE2_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPARE2_REG_ADDR,m,v,HWIO_AOSS_CC_SPARE2_REG_IN)
#define HWIO_AOSS_CC_SPARE2_REG_SPARE2_BITS_BMSK                                          0xffffffff
#define HWIO_AOSS_CC_SPARE2_REG_SPARE2_BITS_SHFT                                                 0x0

#define HWIO_AOSS_CC_CSYSPWRUPREQ_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003030)
#define HWIO_AOSS_CC_CSYSPWRUPREQ_OFFS                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00003030)
#define HWIO_AOSS_CC_CSYSPWRUPREQ_RMSK                                                    0x80000000
#define HWIO_AOSS_CC_CSYSPWRUPREQ_IN          \
        in_dword(HWIO_AOSS_CC_CSYSPWRUPREQ_ADDR)
#define HWIO_AOSS_CC_CSYSPWRUPREQ_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_CSYSPWRUPREQ_ADDR, m)
#define HWIO_AOSS_CC_CSYSPWRUPREQ_STATUS_BMSK                                             0x80000000
#define HWIO_AOSS_CC_CSYSPWRUPREQ_STATUS_SHFT                                                   0x1f

#define HWIO_AOSS_CC_SPARE3_REG_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050038)
#define HWIO_AOSS_CC_SPARE3_REG_OFFS                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00050038)
#define HWIO_AOSS_CC_SPARE3_REG_RMSK                                                      0xffffffff
#define HWIO_AOSS_CC_SPARE3_REG_IN          \
        in_dword(HWIO_AOSS_CC_SPARE3_REG_ADDR)
#define HWIO_AOSS_CC_SPARE3_REG_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPARE3_REG_ADDR, m)
#define HWIO_AOSS_CC_SPARE3_REG_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPARE3_REG_ADDR,v)
#define HWIO_AOSS_CC_SPARE3_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPARE3_REG_ADDR,m,v,HWIO_AOSS_CC_SPARE3_REG_IN)
#define HWIO_AOSS_CC_SPARE3_REG_SPARE2_BITS_BMSK                                          0xffffffff
#define HWIO_AOSS_CC_SPARE3_REG_SPARE2_BITS_SHFT                                                 0x0

#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_ADDR                                            (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050040)
#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_OFFS                                            (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00050040)
#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_RMSK                                            0xffffffff
#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_IN          \
        in_dword(HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_ADDR)
#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_ADDR, m)
#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_ADDR,v)
#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_ADDR,m,v,HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_IN)
#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_TIMER_VAL_BMSK                                  0xffffffff
#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_TIMER_VAL_SHFT                                         0x0

#define HWIO_AOSS_CC_ALT_RESET_ENABLE_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000458)
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_OFFS                                                (AOSS_CC_AOSS_CC_REG_REG_BASE_OFFS + 0x00000458)
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_RMSK                                                       0x3
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_IN          \
        in_dword(HWIO_AOSS_CC_ALT_RESET_ENABLE_ADDR)
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_ALT_RESET_ENABLE_ADDR, m)
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_ALT_RESET_ENABLE_ADDR,v)
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_ALT_RESET_ENABLE_ADDR,m,v,HWIO_AOSS_CC_ALT_RESET_ENABLE_IN)
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_ALLOW_GEMNOC_ALT_ARES_BMSK                                 0x2
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_ALLOW_GEMNOC_ALT_ARES_SHFT                                 0x1
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_ALLOW_GEMNOC_ALT_ARES_DISABLE_FVAL                         0x0
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_ALLOW_GEMNOC_ALT_ARES_ENABLE_FVAL                          0x1
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_ALLOW_BIMC_ALT_ARES_BMSK                                   0x1
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_ALLOW_BIMC_ALT_ARES_SHFT                                   0x0
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_ALLOW_BIMC_ALT_ARES_DISABLE_FVAL                           0x0
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_ALLOW_BIMC_ALT_ARES_ENABLE_FVAL                            0x1

/*----------------------------------------------------------------------------
 * MODULE: CABO_BROADCAST_CABO_GLOBAL
 *--------------------------------------------------------------------------*/

#define CABO_BROADCAST_CABO_GLOBAL_REG_BASE                                                      (DDR_SS_BASE      + 0x00660000)
#define CABO_BROADCAST_CABO_GLOBAL_REG_BASE_SIZE                                                 0x1000
#define CABO_BROADCAST_CABO_GLOBAL_REG_BASE_USED                                                 0x4e0
#define CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS                                                 0x00660000

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_VERSION_ADDR                                          (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000000)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_VERSION_OFFS                                          (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000000)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_VERSION_RMSK                                          0xffffffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_VERSION_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_VERSION_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_VERSION_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_VERSION_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_VERSION_MAJOR_BMSK                                    0xf0000000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_VERSION_MAJOR_SHFT                                          0x1c
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_VERSION_MINOR_BMSK                                     0xfff0000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_VERSION_MINOR_SHFT                                          0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_VERSION_STEP_BMSK                                         0xffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_VERSION_STEP_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CORE_INFO_ADDR                                           (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000004)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CORE_INFO_OFFS                                           (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000004)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CORE_INFO_RMSK                                           0xffffffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CORE_INFO_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_CORE_INFO_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CORE_INFO_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_CORE_INFO_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CORE_INFO_ID_BMSK                                        0xffffffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CORE_INFO_ID_SHFT                                               0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_INFO_ADDR                                             (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000008)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_INFO_OFFS                                             (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000008)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_INFO_RMSK                                             0xffffffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_INFO_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_INFO_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_INFO_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_INFO_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_INFO_MAJOR_BMSK                                       0xff000000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_INFO_MAJOR_SHFT                                             0x18
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_INFO_BRANCH_BMSK                                        0xff0000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_INFO_BRANCH_SHFT                                            0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_INFO_MINOR_BMSK                                           0xff00
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_INFO_MINOR_SHFT                                              0x8
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_INFO_ECO_BMSK                                               0xff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_HW_INFO_ECO_SHFT                                                0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_LOAD_CONFIG_ADDR                                         (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000020)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_LOAD_CONFIG_OFFS                                         (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000020)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_LOAD_CONFIG_RMSK                                                0x1
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_LOAD_CONFIG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_LOAD_CONFIG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_LOAD_CONFIG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_LOAD_CONFIG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_LOAD_CONFIG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_LOAD_CONFIG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_LOAD_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_GLOBAL_LOAD_CONFIG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_GLOBAL_LOAD_CONFIG_IN)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_LOAD_CONFIG_LOAD_CONFIG_BMSK                                    0x1
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_LOAD_CONFIG_LOAD_CONFIG_SHFT                                    0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_0_ADDR                                (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000030)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_0_OFFS                                (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000030)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_0_RMSK                                  0xffff0f
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_0_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_0_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_0_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_0_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_0_ADDR_WIDTH_BMSK                       0xff0000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_0_ADDR_WIDTH_SHFT                           0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_0_DDR_BUS_WIDTH_BMSK                      0xff00
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_0_DDR_BUS_WIDTH_SHFT                         0x8
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_0_AID_WIDTH_BMSK                             0xf
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_0_AID_WIDTH_SHFT                             0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_1_ADDR                                (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000034)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_1_OFFS                                (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000034)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_1_RMSK                                0xffffff00
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_1_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_1_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_1_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_1_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_1_MSI_DATA_WIDTH_BMSK                 0xffff0000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_1_MSI_DATA_WIDTH_SHFT                       0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_1_CORE_DATA_WIDTH_BMSK                    0xff00
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_1_CORE_DATA_WIDTH_SHFT                       0x8

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_2_ADDR                                (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000038)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_2_OFFS                                (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000038)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_2_RMSK                                0xffffffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_2_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_2_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_2_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_2_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_2_ACH_DEPTH_BMSK                      0xff000000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_2_ACH_DEPTH_SHFT                            0x18
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_2_WCH_DEPTH_BMSK                        0xff0000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_2_WCH_DEPTH_SHFT                            0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_2_RCH_DEPTH_BMSK                          0xffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_2_RCH_DEPTH_SHFT                             0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_3_ADDR                                (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x0000003c)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_3_OFFS                                (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x0000003c)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_3_RMSK                                  0xff00ff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_3_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_3_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_3_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_3_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_3_ISU_CQ_DEPTH_BMSK                     0xff0000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_3_ISU_CQ_DEPTH_SHFT                         0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_3_WBUF_DEPTH_BMSK                           0xff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_3_WBUF_DEPTH_SHFT                            0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_4_ADDR                                (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000040)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_4_OFFS                                (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000040)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_4_RMSK                                0xf000ffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_4_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_4_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_4_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_4_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_4_NUM_CBUS_BMSK                       0xf0000000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_4_NUM_CBUS_SHFT                             0x1c
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_4_CBU_WR_CQ_DEPTH_BMSK                    0xff00
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_4_CBU_WR_CQ_DEPTH_SHFT                       0x8
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_4_CBU_RD_CQ_DEPTH_BMSK                      0xff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CONFIGURATION_INFO_4_CBU_RD_CQ_DEPTH_SHFT                       0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_BANK_MAP_CFG_INFO_CBU_m_ADDR(m)                          (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000044 + 0x4 * (m))
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_BANK_MAP_CFG_INFO_CBU_m_OFFS(m)                          (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000044 + 0x4 * (m))
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_BANK_MAP_CFG_INFO_CBU_m_RMSK                                 0xffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_BANK_MAP_CFG_INFO_CBU_m_MAXm                                      0
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_BANK_MAP_CFG_INFO_CBU_m_INI(m)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_BANK_MAP_CFG_INFO_CBU_m_ADDR(m), HWIO_CABO_BROADCAST_CABO_GLOBAL_BANK_MAP_CFG_INFO_CBU_m_RMSK)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_BANK_MAP_CFG_INFO_CBU_m_INMI(m,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_BANK_MAP_CFG_INFO_CBU_m_ADDR(m), mask)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_BANK_MAP_CFG_INFO_CBU_m_BANK_MAP_BMSK                        0xffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_BANK_MAP_CFG_INFO_CBU_m_BANK_MAP_SHFT                           0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_ADDR                                            (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000070)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_OFFS                                            (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000070)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_RMSK                                                 0x31f
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_PEG_CG_EN_BMSK                                       0x200
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_PEG_CG_EN_SHFT                                         0x9
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_CONFIG_CG_EN_BMSK                                    0x100
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_CONFIG_CG_EN_SHFT                                      0x8
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_INTR_CG_EN_BMSK                                       0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_INTR_CG_EN_SHFT                                        0x4
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_RFU_3_1_BMSK                                           0xe
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_RFU_3_1_SHFT                                           0x1
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_RTCG_CG_EN_BMSK                                        0x1
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CLK_CTRL_RTCG_CG_EN_SHFT                                        0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DDR_CLK_PERIOD_CFG_ADDR                                  (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000080)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DDR_CLK_PERIOD_CFG_OFFS                                  (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000080)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DDR_CLK_PERIOD_CFG_RMSK                                     0x1ffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DDR_CLK_PERIOD_CFG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_DDR_CLK_PERIOD_CFG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DDR_CLK_PERIOD_CFG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_DDR_CLK_PERIOD_CFG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DDR_CLK_PERIOD_CFG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_DDR_CLK_PERIOD_CFG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DDR_CLK_PERIOD_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_GLOBAL_DDR_CLK_PERIOD_CFG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_GLOBAL_DDR_CLK_PERIOD_CFG_IN)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DDR_CLK_PERIOD_CFG_DDR_CLK_PERIOD_BMSK                      0x1ffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DDR_CLK_PERIOD_CFG_DDR_CLK_PERIOD_SHFT                          0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_ADDR                                           (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000090)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_OFFS                                           (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000090)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_RMSK                                                 0x3f
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_IN)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_SW_CLK_RATE_VALUE_BMSK                               0x30
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_SW_CLK_RATE_VALUE_SHFT                                0x4
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_RFU_3_1_BMSK                                          0xe
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_RFU_3_1_SHFT                                          0x1
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_SW_CLK_RATE_EN_BMSK                                   0x1
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CC_SW_CFG_SW_CLK_RATE_EN_SHFT                                   0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_ADDR                                      (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x000000a0)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_OFFS                                      (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x000000a0)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_RMSK                                           0xff7
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_IN)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_SYNC_RATE_BMSK                                 0xf00
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_SYNC_RATE_SHFT                                   0x8
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_RFU_7_5_BMSK                                    0xe0
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_RFU_7_5_SHFT                                     0x5
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_OVERRIDE_BMSK                                   0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_OVERRIDE_SHFT                                    0x4
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_INDEX_BMSK                                       0x7
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_CFG_INDEX_SHFT                                       0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_CFG_ADDR                                            (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000100)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_CFG_OFFS                                            (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000100)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_CFG_RMSK                                                   0x1
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_CFG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_CFG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_CFG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_CFG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_CFG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_CFG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_CFG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_CFG_IN)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_CFG_RTCG_EN_BMSK                                           0x1
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_CFG_RTCG_EN_SHFT                                           0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_STABLE_CLK_TIMER_CFG_ADDR                           (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000108)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_STABLE_CLK_TIMER_CFG_OFFS                           (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000108)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_STABLE_CLK_TIMER_CFG_RMSK                                 0xff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_STABLE_CLK_TIMER_CFG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_STABLE_CLK_TIMER_CFG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_STABLE_CLK_TIMER_CFG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_STABLE_CLK_TIMER_CFG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_STABLE_CLK_TIMER_CFG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_STABLE_CLK_TIMER_CFG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_STABLE_CLK_TIMER_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_STABLE_CLK_TIMER_CFG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_STABLE_CLK_TIMER_CFG_IN)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_STABLE_CLK_TIMER_CFG_STABLE_CLK_TIMER_BMSK                0xff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_STABLE_CLK_TIMER_CFG_STABLE_CLK_TIMER_SHFT                 0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_ADDR(n)                            (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000110 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_OFFS(n)                            (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000110 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_RMSK                                 0xffffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_MAXn                                        3
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_RFU_15_12_BMSK                       0xf00000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_RFU_15_12_SHFT                           0x14
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_IDLE_TIMER_OFFSET_BMSK                0xf0000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_IDLE_TIMER_OFFSET_SHFT                   0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_IDLE_TIMER_BMSK                        0xffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_RTCG_IDLE_TIMER_CFG_n_IDLE_TIMER_SHFT                           0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEBUG_CFG_ADDR                                           (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000300)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEBUG_CFG_OFFS                                           (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000300)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEBUG_CFG_RMSK                                           0xffffffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEBUG_CFG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_DEBUG_CFG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEBUG_CFG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_DEBUG_CFG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEBUG_CFG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_DEBUG_CFG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEBUG_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_GLOBAL_DEBUG_CFG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_GLOBAL_DEBUG_CFG_IN)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEBUG_CFG_BLK_SELECT_BMSK                                0xffff0000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEBUG_CFG_BLK_SELECT_SHFT                                      0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEBUG_CFG_SELECT_BMSK                                        0xffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEBUG_CFG_SELECT_SHFT                                           0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SPARE_CFG_ADDR                                           (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x000003b0)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SPARE_CFG_OFFS                                           (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x000003b0)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SPARE_CFG_RMSK                                           0xffffffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SPARE_CFG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_SPARE_CFG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SPARE_CFG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_SPARE_CFG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SPARE_CFG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_SPARE_CFG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SPARE_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_GLOBAL_SPARE_CFG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_GLOBAL_SPARE_CFG_IN)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SPARE_CFG_RFU_31_0_BMSK                                  0xffffffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SPARE_CFG_RFU_31_0_SHFT                                         0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_IDLE_STATUS_ADDR                                         (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000400)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_IDLE_STATUS_OFFS                                         (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000400)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_IDLE_STATUS_RMSK                                         0xc003ffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_IDLE_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_IDLE_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_IDLE_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_IDLE_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_IDLE_STATUS_CLKON_BMSK                                   0x80000000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_IDLE_STATUS_CLKON_SHFT                                         0x1f
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_IDLE_STATUS_IDLE_BMSK                                    0x40000000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_IDLE_STATUS_IDLE_SHFT                                          0x1e
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_IDLE_STATUS_RANK_IDLE_BMSK                                  0x30000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_IDLE_STATUS_RANK_IDLE_SHFT                                     0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_IDLE_STATUS_BANK_IDLE_BMSK                                   0xffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_IDLE_STATUS_BANK_IDLE_SHFT                                      0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEVICE_STATUS_ADDR                                       (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000404)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEVICE_STATUS_OFFS                                       (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000404)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEVICE_STATUS_RMSK                                           0x3333
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEVICE_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_DEVICE_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEVICE_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_DEVICE_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEVICE_STATUS_RANKS_READY_BMSK                               0x3000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEVICE_STATUS_RANKS_READY_SHFT                                  0xc
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEVICE_STATUS_RANKS_IN_SELFRFRSH_BMSK                         0x300
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEVICE_STATUS_RANKS_IN_SELFRFRSH_SHFT                           0x8
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEVICE_STATUS_RANKS_IN_CSPD_BMSK                               0x30
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEVICE_STATUS_RANKS_IN_CSPD_SHFT                                0x4
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEVICE_STATUS_RANKS_IN_PD_BMSK                                  0x3
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_DEVICE_STATUS_RANKS_IN_PD_SHFT                                  0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_ACH_STATUS_ADDR                                      (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000410)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_ACH_STATUS_OFFS                                      (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000410)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_ACH_STATUS_RMSK                                          0x1111
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_ACH_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_ACH_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_ACH_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_ACH_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_ACH_STATUS_ATK_FIFO_FULL_BMSK                            0x1000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_ACH_STATUS_ATK_FIFO_FULL_SHFT                               0xc
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_ACH_STATUS_ATK_FIFO_EMPTY_BMSK                            0x100
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_ACH_STATUS_ATK_FIFO_EMPTY_SHFT                              0x8
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_ACH_STATUS_ACH_FIFO_FULL_BMSK                              0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_ACH_STATUS_ACH_FIFO_FULL_SHFT                               0x4
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_ACH_STATUS_ACH_FIFO_EMPTY_BMSK                              0x1
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_ACH_STATUS_ACH_FIFO_EMPTY_SHFT                              0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_ADDR                                      (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000414)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_OFFS                                      (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000414)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_RMSK                                        0x111111
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_WCMD_ORDER_FIFO_FULL_BMSK                   0x100000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_WCMD_ORDER_FIFO_FULL_SHFT                       0x14
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_WCMD_ORDER_FIFO_EMPTY_BMSK                   0x10000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_WCMD_ORDER_FIFO_EMPTY_SHFT                      0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_WTK_FIFO_FULL_BMSK                            0x1000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_WTK_FIFO_FULL_SHFT                               0xc
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_WTK_FIFO_EMPTY_BMSK                            0x100
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_WTK_FIFO_EMPTY_SHFT                              0x8
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_WCH_FIFO_FULL_BMSK                              0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_WCH_FIFO_FULL_SHFT                               0x4
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_WCH_FIFO_EMPTY_BMSK                              0x1
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WCH_STATUS_WCH_FIFO_EMPTY_SHFT                              0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_RCH_STATUS_ADDR                                      (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000418)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_RCH_STATUS_OFFS                                      (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000418)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_RCH_STATUS_RMSK                                      0xffff0011
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_RCH_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_RCH_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_RCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_RCH_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_RCH_STATUS_RCREDIT_CNTR_BMSK                         0xffff0000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_RCH_STATUS_RCREDIT_CNTR_SHFT                               0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_RCH_STATUS_RCH_FIFO_FULL_BMSK                              0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_RCH_STATUS_RCH_FIFO_FULL_SHFT                               0x4
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_RCH_STATUS_RCH_FIFO_EMPTY_BMSK                              0x1
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_RCH_STATUS_RCH_FIFO_EMPTY_SHFT                              0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS0_ADDR                                  (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000420)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS0_OFFS                                  (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000420)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS0_RMSK                                  0x1f1f3f3f
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS0_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS0_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS0_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS0_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS0_WR_HP_CMDS_IN_USE_BMSK                0x1f000000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS0_WR_HP_CMDS_IN_USE_SHFT                      0x18
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS0_WR_LP_CMDS_IN_USE_BMSK                  0x1f0000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS0_WR_LP_CMDS_IN_USE_SHFT                      0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS0_RD_HP_CMDS_IN_USE_BMSK                    0x3f00
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS0_RD_HP_CMDS_IN_USE_SHFT                       0x8
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS0_RD_LP_CMDS_IN_USE_BMSK                      0x3f
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS0_RD_LP_CMDS_IN_USE_SHFT                       0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS1_ADDR                                  (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000424)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS1_OFFS                                  (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000424)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS1_RMSK                                      0x3f11
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS1_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS1_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS1_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS1_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS1_WR_CMDS_WAITON_DATA_BMSK                  0x3f00
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS1_WR_CMDS_WAITON_DATA_SHFT                     0x8
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS1_CBU_WRQ_FULL_BMSK                           0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS1_CBU_WRQ_FULL_SHFT                            0x4
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS1_CBU_RDQ_FULL_BMSK                            0x1
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_CMDBUF_STATUS1_CBU_RDQ_FULL_SHFT                            0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WRBUF_STATUS_ADDR                                    (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000430)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WRBUF_STATUS_OFFS                                    (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000430)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WRBUF_STATUS_RMSK                                          0x11
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WRBUF_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WRBUF_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WRBUF_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WRBUF_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WRBUF_STATUS_WBUF_FULL_BMSK                                0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WRBUF_STATUS_WBUF_FULL_SHFT                                 0x4
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WRBUF_STATUS_WBUF_EMPTY_BMSK                                0x1
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_ISU_WRBUF_STATUS_WBUF_EMPTY_SHFT                                0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_RDCQ_STATUS_ADDR(m)                                (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000440 + 0x10 * (m))
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_RDCQ_STATUS_OFFS(m)                                (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000440 + 0x10 * (m))
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_RDCQ_STATUS_RMSK                                     0x3f3f3f
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_RDCQ_STATUS_MAXm                                            0
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_RDCQ_STATUS_INI(m)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_RDCQ_STATUS_ADDR(m), HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_RDCQ_STATUS_RMSK)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_RDCQ_STATUS_INMI(m,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_RDCQ_STATUS_ADDR(m), mask)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_RDCQ_STATUS_HP_CMDS_IN_USE_BMSK                      0x3f0000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_RDCQ_STATUS_HP_CMDS_IN_USE_SHFT                          0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_RDCQ_STATUS_MP_CMDS_IN_USE_BMSK                        0x3f00
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_RDCQ_STATUS_MP_CMDS_IN_USE_SHFT                           0x8
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_RDCQ_STATUS_LP_CMDS_IN_USE_BMSK                          0x3f
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_RDCQ_STATUS_LP_CMDS_IN_USE_SHFT                           0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_WRCQ_STATUS_ADDR(m)                                (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x00000448 + 0x10 * (m))
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_WRCQ_STATUS_OFFS(m)                                (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x00000448 + 0x10 * (m))
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_WRCQ_STATUS_RMSK                                     0x3f3f3f
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_WRCQ_STATUS_MAXm                                            0
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_WRCQ_STATUS_INI(m)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_WRCQ_STATUS_ADDR(m), HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_WRCQ_STATUS_RMSK)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_WRCQ_STATUS_INMI(m,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_WRCQ_STATUS_ADDR(m), mask)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_WRCQ_STATUS_HP_CMDS_IN_USE_BMSK                      0x3f0000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_WRCQ_STATUS_HP_CMDS_IN_USE_SHFT                          0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_WRCQ_STATUS_MP_CMDS_IN_USE_BMSK                        0x3f00
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_WRCQ_STATUS_MP_CMDS_IN_USE_SHFT                           0x8
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_WRCQ_STATUS_LP_CMDS_IN_USE_BMSK                          0x3f
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_CBU_m_WRCQ_STATUS_LP_CMDS_IN_USE_SHFT                           0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_ADDR                                          (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x000004a0)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_OFFS                                          (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x000004a0)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_RMSK                                          0x3f311111
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_HKS_CMD_PEND_BMSK                             0x3f000000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_HKS_CMD_PEND_SHFT                                   0x18
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_HKS_RANK_PEND_BMSK                              0x300000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_HKS_RANK_PEND_SHFT                                  0x14
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_RD_BKPR_STATUS_BMSK                              0x10000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_RD_BKPR_STATUS_SHFT                                 0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_PRQ_FULL_BMSK                                     0x1000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_PRQ_FULL_SHFT                                        0xc
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_PRQ_EMPTY_BMSK                                     0x100
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_PRQ_EMPTY_SHFT                                       0x8
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_PWQ_FULL_BMSK                                       0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_PWQ_FULL_SHFT                                        0x4
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_PWQ_EMPTY_BMSK                                       0x1
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_MPE_STATUS_PWQ_EMPTY_SHFT                                       0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_ADDR                                         (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x000004b0)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_OFFS                                         (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x000004b0)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_RMSK                                         0x77003730
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_RANK1_REFRESH_RATE_BMSK                      0x70000000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_RANK1_REFRESH_RATE_SHFT                            0x1c
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_RANK0_REFRESH_RATE_BMSK                       0x7000000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_RANK0_REFRESH_RATE_SHFT                            0x18
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_FSW_SELF_REFRESH_BMSK                            0x3000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_FSW_SELF_REFRESH_SHFT                               0xc
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_WDOG_PRE_ARES_DONE_BMSK                           0x400
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_WDOG_PRE_ARES_DONE_SHFT                             0xa
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_WDOG_SELF_REFRESH_BMSK                            0x300
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_WDOG_SELF_REFRESH_SHFT                              0x8
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_SW_SELF_REFRESH_BMSK                               0x30
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_STATUS_SW_SELF_REFRESH_SHFT                                0x4

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_BANK_UNAVAIL_STATUS_ADDR                            (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x000004b4)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_BANK_UNAVAIL_STATUS_OFFS                            (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x000004b4)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_BANK_UNAVAIL_STATUS_RMSK                                0xffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_BANK_UNAVAIL_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_BANK_UNAVAIL_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_BANK_UNAVAIL_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_BANK_UNAVAIL_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_BANK_UNAVAIL_STATUS_BANK_UNAVAIL_BMSK                   0xffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_BANK_UNAVAIL_STATUS_BANK_UNAVAIL_SHFT                      0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_FSW_STATUS_ADDR                                     (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x000004b8)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_FSW_STATUS_OFFS                                     (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x000004b8)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_FSW_STATUS_RMSK                                     0x1f1fffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_FSW_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_FSW_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_FSW_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_FSW_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_FSW_STATUS_CURR_FSW_ACK_STATE_BMSK                  0x1f000000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_FSW_STATUS_CURR_FSW_ACK_STATE_SHFT                        0x18
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_FSW_STATUS_CURR_FSW_REQ_STATE_BMSK                    0x1f0000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_FSW_STATUS_CURR_FSW_REQ_STATE_SHFT                        0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_FSW_STATUS_TASK_COMPLETE_BMSK                           0xffff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_FSW_STATUS_TASK_COMPLETE_SHFT                              0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_WDOG_STATUS_ADDR                                    (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x000004bc)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_WDOG_STATUS_OFFS                                    (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x000004bc)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_WDOG_STATUS_RMSK                                         0x1f1
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_WDOG_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_WDOG_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_WDOG_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_WDOG_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_WDOG_STATUS_FSM_STATE_BMSK                               0x1f0
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_WDOG_STATUS_FSM_STATE_SHFT                                 0x4
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_WDOG_STATUS_PRE_ARES_DONE_BMSK                             0x1
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_SHKE_WDOG_STATUS_PRE_ARES_DONE_SHFT                             0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_STATUS_ADDR                                          (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x000004d0)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_STATUS_OFFS                                          (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x000004d0)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_STATUS_RMSK                                            0xff003f
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_STATUS_PWRS_STATUS_BMSK                                0xff0000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_STATUS_PWRS_STATUS_SHFT                                    0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_STATUS_TIMESTAMP_VAL_BMSK                                  0x3f
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_STATUS_TIMESTAMP_VAL_SHFT                                   0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_DQS_FIFO_STATUS_ADDR                                 (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x000004d4)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_DQS_FIFO_STATUS_OFFS                                 (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x000004d4)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_DQS_FIFO_STATUS_RMSK                                   0xff00ff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_DQS_FIFO_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_DQS_FIFO_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_DQS_FIFO_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_DQS_FIFO_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_DQS_FIFO_STATUS_DQS_FIFO_FULL_BMSK                     0xff0000
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_DQS_FIFO_STATUS_DQS_FIFO_FULL_SHFT                         0x10
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_DQS_FIFO_STATUS_DQS_FIFO_EMPTY_BMSK                        0xff
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_OSU_DQS_FIFO_STATUS_DQS_FIFO_EMPTY_SHFT                         0x0

#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_STATUS_ADDR                                   (CABO_BROADCAST_CABO_GLOBAL_REG_BASE      + 0x000004e0)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_STATUS_OFFS                                   (CABO_BROADCAST_CABO_GLOBAL_REG_BASE_OFFS + 0x000004e0)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_STATUS_RMSK                                          0x7
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_STATUS_INDEX_IN_USE_BMSK                             0x7
#define HWIO_CABO_BROADCAST_CABO_GLOBAL_QOS_POLICY_STATUS_INDEX_IN_USE_SHFT                             0x0

/*----------------------------------------------------------------------------
 * MODULE: DPCC_REG_DPCC
 *--------------------------------------------------------------------------*/

#define DPCC_REG_DPCC_REG_BASE (DDR_SS_BASE      + 0x00084000)
#define DPCC_REG_DPCC_REG_BASE_SIZE 0x3000
#define DPCC_REG_DPCC_REG_BASE_USED 0x0
#define DPCC_REG_DPCC_REG_BASE_OFFS 0x00084000

/*----------------------------------------------------------------------------
 * MODULE: DPCC_REG_DPCC_DPCC_DPCC_REG
 *--------------------------------------------------------------------------*/

#define DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE                                                   (DDR_SS_BASE      + 0x00084000)
#define DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_SIZE                                              0x3000
#define DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_USED                                              0x2010
#define DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS                                              0x00084000

#define HWIO_DPCC_REG_DPCC_DEBUG_DIV_CDIVR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000004)
#define HWIO_DPCC_REG_DPCC_DEBUG_DIV_CDIVR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000004)
#define HWIO_DPCC_REG_DPCC_DEBUG_DIV_CDIVR_RMSK                                                       0x3
#define HWIO_DPCC_REG_DPCC_DEBUG_DIV_CDIVR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_DEBUG_DIV_CDIVR_ADDR)
#define HWIO_DPCC_REG_DPCC_DEBUG_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_DEBUG_DIV_CDIVR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_DEBUG_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_DEBUG_DIV_CDIVR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_DEBUG_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_DEBUG_DIV_CDIVR_ADDR,m,v,HWIO_DPCC_REG_DPCC_DEBUG_DIV_CDIVR_IN)
#define HWIO_DPCC_REG_DPCC_DEBUG_DIV_CDIVR_CLK_DIV_BMSK                                               0x3
#define HWIO_DPCC_REG_DPCC_DEBUG_DIV_CDIVR_CLK_DIV_SHFT                                               0x0

#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_ADDR                                                     (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000008)
#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_OFFS                                                     (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000008)
#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_RMSK                                                     0x80000005
#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_DEBUG_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_DEBUG_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_DEBUG_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_DEBUG_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_DEBUG_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_CLK_ARES_NO_RESET_FVAL                                          0x0
#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_CLK_ARES_RESET_FVAL                                             0x1
#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_CLK_ENABLE_SHFT                                                 0x0
#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_CLK_ENABLE_DISABLE_FVAL                                         0x0
#define HWIO_DPCC_REG_DPCC_DEBUG_CBCR_CLK_ENABLE_ENABLE_FVAL                                          0x1

#define HWIO_DPCC_REG_DPCC_PLL_TEST_DIV_CDIVR_ADDR                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000010)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_DIV_CDIVR_OFFS                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000010)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_DIV_CDIVR_RMSK                                                    0x3
#define HWIO_DPCC_REG_DPCC_PLL_TEST_DIV_CDIVR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PLL_TEST_DIV_CDIVR_ADDR)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PLL_TEST_DIV_CDIVR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PLL_TEST_DIV_CDIVR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PLL_TEST_DIV_CDIVR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PLL_TEST_DIV_CDIVR_IN)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_DIV_CDIVR_CLK_DIV_BMSK                                            0x3
#define HWIO_DPCC_REG_DPCC_PLL_TEST_DIV_CDIVR_CLK_DIV_SHFT                                            0x0

#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_ADDR                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000014)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_OFFS                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000014)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_RMSK                                                  0x80000005
#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_CLK_ARES_NO_RESET_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_CLK_ARES_RESET_FVAL                                          0x1
#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_CLK_ENABLE_SHFT                                              0x0
#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_CLK_ENABLE_DISABLE_FVAL                                      0x0
#define HWIO_DPCC_REG_DPCC_PLL_TEST_CBCR_CLK_ENABLE_ENABLE_FVAL                                       0x1

#define HWIO_DPCC_REG_DPCC_SHUB_BCR_ADDR                                                       (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000018)
#define HWIO_DPCC_REG_DPCC_SHUB_BCR_OFFS                                                       (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000018)
#define HWIO_DPCC_REG_DPCC_SHUB_BCR_RMSK                                                              0x1
#define HWIO_DPCC_REG_DPCC_SHUB_BCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHUB_BCR_ADDR)
#define HWIO_DPCC_REG_DPCC_SHUB_BCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHUB_BCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHUB_BCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHUB_BCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHUB_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHUB_BCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHUB_BCR_IN)
#define HWIO_DPCC_REG_DPCC_SHUB_BCR_BLK_ARES_BMSK                                                     0x1
#define HWIO_DPCC_REG_DPCC_SHUB_BCR_BLK_ARES_SHFT                                                     0x0
#define HWIO_DPCC_REG_DPCC_SHUB_BCR_BLK_ARES_DISABLE_FVAL                                             0x0
#define HWIO_DPCC_REG_DPCC_SHUB_BCR_BLK_ARES_ENABLE_FVAL                                              0x1

#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_ADDR                                                     (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000001c)
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_OFFS                                                     (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000001c)
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_RMSK                                                     0xf8ffffff
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHUB_GDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHUB_GDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHUB_GDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHUB_GDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHUB_GDSCR_IN)
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_PWR_ON_BMSK                                              0x80000000
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_PWR_ON_SHFT                                                    0x1f
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_GDSC_STATE_BMSK                                          0x78000000
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_GDSC_STATE_SHFT                                                0x1b
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_EN_REST_WAIT_BMSK                                          0xf00000
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_EN_REST_WAIT_SHFT                                              0x14
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_EN_FEW_WAIT_BMSK                                            0xf0000
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_EN_FEW_WAIT_SHFT                                               0x10
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_CLK_DIS_WAIT_BMSK                                            0xf000
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_CLK_DIS_WAIT_SHFT                                               0xc
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_RETAIN_FF_ENABLE_BMSK                                         0x800
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_RETAIN_FF_ENABLE_SHFT                                           0xb
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL                                    0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_RESTORE_BMSK                                                  0x400
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_RESTORE_SHFT                                                    0xa
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_RESTORE_DISABLE_FVAL                                            0x0
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_RESTORE_ENABLE_FVAL                                             0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_SAVE_BMSK                                                     0x200
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_SAVE_SHFT                                                       0x9
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_SAVE_DISABLE_FVAL                                               0x0
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_SAVE_ENABLE_FVAL                                                0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_RETAIN_BMSK                                                   0x100
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_RETAIN_SHFT                                                     0x8
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_RETAIN_DISABLE_FVAL                                             0x0
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_RETAIN_ENABLE_FVAL                                              0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_EN_REST_BMSK                                                   0x80
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_EN_REST_SHFT                                                    0x7
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_EN_REST_DISABLE_FVAL                                            0x0
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_EN_REST_ENABLE_FVAL                                             0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_EN_FEW_BMSK                                                    0x40
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_EN_FEW_SHFT                                                     0x6
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_EN_FEW_DISABLE_FVAL                                             0x0
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_EN_FEW_ENABLE_FVAL                                              0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_CLAMP_IO_BMSK                                                  0x20
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_CLAMP_IO_SHFT                                                   0x5
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_CLAMP_IO_DISABLE_FVAL                                           0x0
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_CLAMP_IO_ENABLE_FVAL                                            0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_CLK_DISABLE_BMSK                                               0x10
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_CLK_DISABLE_SHFT                                                0x4
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL                                0x0
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_CLK_DISABLE_CLK_DISABLE_FVAL                                    0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_PD_ARES_BMSK                                                    0x8
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_PD_ARES_SHFT                                                    0x3
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_PD_ARES_NO_RESET_FVAL                                           0x0
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_PD_ARES_RESET_FVAL                                              0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_SW_OVERRIDE_BMSK                                                0x4
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_SW_OVERRIDE_SHFT                                                0x2
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_SW_OVERRIDE_DISABLE_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_SW_OVERRIDE_ENABLE_FVAL                                         0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_HW_CONTROL_BMSK                                                 0x2
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_HW_CONTROL_SHFT                                                 0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_HW_CONTROL_DISABLE_FVAL                                         0x0
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_HW_CONTROL_ENABLE_FVAL                                          0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_SW_COLLAPSE_BMSK                                                0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_SW_COLLAPSE_SHFT                                                0x0
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_SW_COLLAPSE_DISABLE_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_SHUB_GDSCR_SW_COLLAPSE_ENABLE_FVAL                                         0x1

#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_ADDR                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000020)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_OFFS                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000020)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_RMSK                                                 0xffffffff
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_IN)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_SPARE_CTRL_IN_BMSK                              0xf0000000
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_SPARE_CTRL_IN_SHFT                                    0x1c
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK                              0xc000000
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT                                   0x1a
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK                               0x2000000
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT                                    0x19
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_PWR_UP_START_BMSK                                0x1000000
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_PWR_UP_START_SHFT                                     0x18
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK                         0xf00000
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT                             0x14
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                            0x80000
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                               0x13
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK                                0x40000
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT                                   0x12
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK                                0x20000
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT                                   0x11
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK                             0x10000
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT                                0x10
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                            0x8000
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                               0xf
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                           0x7800
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                              0xb
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK                                   0x400
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT                                     0xa
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                            0x200
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                              0x9
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                            0x100
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                              0x8
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                                0x80
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                                 0x7
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                       0x60
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                        0x5
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                                 0x10
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                                  0x4
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                           0x8
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                           0x3
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                         0x4
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                         0x2
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                             0x2
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                             0x1
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                          0x1
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                          0x0

#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000024)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000024)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_RMSK                                                   0x1ffff
#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_IN)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK                                 0x10000
#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT                                    0x10
#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK                                     0xf000
#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT                                        0xc
#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                              0xf00
#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                                0x8
#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                                 0xf0
#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                                  0x4
#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                                   0xf
#define HWIO_DPCC_REG_DPCC_SHUB_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                                   0x0

#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_ADDR                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000028)
#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_OFFS                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000028)
#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_RMSK                                                  0x80000005
#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_CLK_ARES_RESET_FVAL                                          0x1
#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_CLK_ENABLE_SHFT                                              0x0
#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                      0x0
#define HWIO_DPCC_REG_DPCC_LLCC0_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                       0x1

#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_ADDR                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000002c)
#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_OFFS                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000002c)
#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_RMSK                                                  0x80000005
#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_CLK_ARES_RESET_FVAL                                          0x1
#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_CLK_ENABLE_SHFT                                              0x0
#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                      0x0
#define HWIO_DPCC_REG_DPCC_LLCC1_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                       0x1

#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_ADDR                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000030)
#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_OFFS                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000030)
#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_RMSK                                                  0x80000005
#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_CLK_ARES_RESET_FVAL                                          0x1
#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_CLK_ENABLE_SHFT                                              0x0
#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                      0x0
#define HWIO_DPCC_REG_DPCC_LLCC2_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                       0x1

#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_ADDR                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000034)
#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_OFFS                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000034)
#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_RMSK                                                  0x80000005
#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_CLK_ARES_RESET_FVAL                                          0x1
#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_CLK_ENABLE_SHFT                                              0x0
#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                      0x0
#define HWIO_DPCC_REG_DPCC_LLCC3_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                       0x1

#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_ADDR                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000038)
#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_OFFS                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000038)
#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_RMSK                                                 0x80000005
#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_CLK_OFF_BMSK                                         0x80000000
#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_CLK_OFF_SHFT                                               0x1f
#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_CLK_ARES_BMSK                                               0x4
#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_CLK_ARES_SHFT                                               0x2
#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                      0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_CLK_ARES_RESET_FVAL                                         0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_CLK_ENABLE_BMSK                                             0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_CLK_ENABLE_SHFT                                             0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                      0x1

#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000003c)
#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000003c)
#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_RMSK                                                0x80000005
#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_CLK_ARES_RESET_FVAL                                        0x1
#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_CLK_ENABLE_BMSK                                            0x1
#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_CLK_ENABLE_SHFT                                            0x0
#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_LLCC0_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL                                     0x1

#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000040)
#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000040)
#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_RMSK                                                0x80000005
#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_CLK_ARES_RESET_FVAL                                        0x1
#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_CLK_ENABLE_BMSK                                            0x1
#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_CLK_ENABLE_SHFT                                            0x0
#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_LLCC1_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL                                     0x1

#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000044)
#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000044)
#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_RMSK                                                0x80000005
#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_CLK_ARES_RESET_FVAL                                        0x1
#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_CLK_ENABLE_BMSK                                            0x1
#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_CLK_ENABLE_SHFT                                            0x0
#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_LLCC2_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL                                     0x1

#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000048)
#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000048)
#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_RMSK                                                0x80000005
#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_CLK_ARES_RESET_FVAL                                        0x1
#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_CLK_ENABLE_BMSK                                            0x1
#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_CLK_ENABLE_SHFT                                            0x0
#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_LLCC3_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL                                     0x1

#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_ADDR                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000004c)
#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_OFFS                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000004c)
#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_RMSK                                                 0x80000005
#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_CLK_OFF_BMSK                                         0x80000000
#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_CLK_OFF_SHFT                                               0x1f
#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_CLK_ARES_BMSK                                               0x4
#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_CLK_ARES_SHFT                                               0x2
#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL                                      0x0
#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_CLK_ARES_RESET_FVAL                                         0x1
#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_CLK_ENABLE_BMSK                                             0x1
#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_CLK_ENABLE_SHFT                                             0x0
#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_LAGG_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL                                      0x1

#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_ADDR                                               (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000050)
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_OFFS                                               (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000050)
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_RMSK                                               0x80007ff5
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_CLK_OFF_BMSK                                       0x80000000
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_CLK_OFF_SHFT                                             0x1f
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_FORCE_MEM_CORE_ON_BMSK                                 0x4000
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_FORCE_MEM_CORE_ON_SHFT                                    0xe
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL                      0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL                       0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_FORCE_MEM_PERIPH_ON_BMSK                               0x2000
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                  0xd
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL                    0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL                     0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                              0x1000
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                 0xc
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL                   0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL                    0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_BMSK                                             0xf00
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_SHFT                                               0x8
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_CLOCK0_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_CLOCK1_FVAL                                        0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_CLOCK2_FVAL                                        0x2
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_CLOCK3_FVAL                                        0x3
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_CLOCK4_FVAL                                        0x4
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_CLOCK5_FVAL                                        0x5
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_CLOCK6_FVAL                                        0x6
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_CLOCK7_FVAL                                        0x7
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_CLOCK8_FVAL                                        0x8
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_CLOCK9_FVAL                                        0x9
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_CLOCK10_FVAL                                       0xa
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_CLOCK11_FVAL                                       0xb
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_CLOCK12_FVAL                                       0xc
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_CLOCK13_FVAL                                       0xd
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_CLOCK14_FVAL                                       0xe
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_WAKEUP_CLOCK15_FVAL                                       0xf
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_BMSK                                               0xf0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_SHFT                                                0x4
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_CLOCK0_FVAL                                         0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_CLOCK1_FVAL                                         0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_CLOCK2_FVAL                                         0x2
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_CLOCK3_FVAL                                         0x3
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_CLOCK4_FVAL                                         0x4
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_CLOCK5_FVAL                                         0x5
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_CLOCK6_FVAL                                         0x6
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_CLOCK7_FVAL                                         0x7
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_CLOCK8_FVAL                                         0x8
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_CLOCK9_FVAL                                         0x9
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_CLOCK10_FVAL                                        0xa
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_CLOCK11_FVAL                                        0xb
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_CLOCK12_FVAL                                        0xc
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_CLOCK13_FVAL                                        0xd
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_CLOCK14_FVAL                                        0xe
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_SLEEP_CLOCK15_FVAL                                        0xf
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_CLK_ARES_BMSK                                             0x4
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_CLK_ARES_SHFT                                             0x2
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_CLK_ARES_RESET_FVAL                                       0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_CLK_ENABLE_BMSK                                           0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_CLK_ENABLE_SHFT                                           0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL                                    0x1

#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_ADDR                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000054)
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_OFFS                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000054)
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_RMSK                                              0xfffff37e
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_ADDR)
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_ADDR,m,v,HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_IN)
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                    0xff000000
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                          0x18
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                       0xff0000
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                           0x10
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_RESERVE_BITS15_13_BMSK                                0xe000
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_RESERVE_BITS15_13_SHFT                                   0xd
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                      0x1000
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                         0xc
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_NO_RESET_FVAL                0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_RESET_FVAL                   0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                          0x300
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                            0x8
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_1_FVAL                   0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_2_FVAL                   0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_4_FVAL                   0x2
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_DIV_RATIO_SLP_STG_CLK_DIV_BY_8_FVAL                   0x3
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_FORCE_CLK_ON_BMSK                                       0x40
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_FORCE_CLK_ON_SHFT                                        0x6
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_FORCE_CLK_ON_NO_FORCE_FVAL                               0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_FORCE_CLK_ON_FORCE_ENABLE_FVAL                           0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_RST_SEL_SLP_STG_BMSK                                 0x20
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_RST_SEL_SLP_STG_SHFT                                  0x5
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_HARDWARE_ARES_FVAL         0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_RST_SEL_SLP_STG_SELECT_THE_SW_RST_SLP_STG_BIT_FVAL        0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_RST_SLP_STG_BMSK                                     0x10
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_RST_SLP_STG_SHFT                                      0x4
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_RST_SLP_STG_DE_ASSERTION_OF_THE_RESET_FVAL            0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_RST_SLP_STG_ASSERTION_OF_THE_RESET_FVAL               0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_CTRL_PWR_DOWN_BMSK                                    0x8
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_CTRL_PWR_DOWN_SHFT                                    0x3
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_CTRL_PWR_DOWN_NO_SW_CTRL_FVAL                         0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_CTRL_PWR_DOWN_SW_CTRL_FVAL                            0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                               0x4
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                               0x2
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM_FVAL        0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_CLK_EN_SEL_SLP_STG_SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT_FVAL        0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_CLK_EN_SLP_STG_BMSK                                   0x2
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_CLK_EN_SLP_STG_SHFT                                   0x1
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_DISABLE_FVAL             0x0
#define HWIO_DPCC_REG_DPCC_GEMNOC_SHUB_SREGR_SW_CLK_EN_SLP_STG_SLP_STG_CLOCK_ENABLE_FVAL              0x1

#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_ADDR                                                    (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000058)
#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_OFFS                                                    (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000058)
#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_RMSK                                                    0x80000005
#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_CLK_ARES_NO_RESET_FVAL                                         0x0
#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_CLK_ARES_RESET_FVAL                                            0x1
#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_CLK_ENABLE_SHFT                                                0x0
#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_CLK_ENABLE_DISABLE_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_CMPNOC_CBCR_CLK_ENABLE_ENABLE_FVAL                                         0x1

#define HWIO_DPCC_REG_DPCC_GPU_CBCR_ADDR                                                       (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000005c)
#define HWIO_DPCC_REG_DPCC_GPU_CBCR_OFFS                                                       (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000005c)
#define HWIO_DPCC_REG_DPCC_GPU_CBCR_RMSK                                                       0x80000005
#define HWIO_DPCC_REG_DPCC_GPU_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_GPU_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_GPU_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_GPU_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_GPU_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_GPU_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_GPU_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_GPU_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_GPU_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_GPU_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_DPCC_REG_DPCC_GPU_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_DPCC_REG_DPCC_GPU_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_DPCC_REG_DPCC_GPU_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_DPCC_REG_DPCC_GPU_CBCR_CLK_ARES_NO_RESET_FVAL                                            0x0
#define HWIO_DPCC_REG_DPCC_GPU_CBCR_CLK_ARES_RESET_FVAL                                               0x1
#define HWIO_DPCC_REG_DPCC_GPU_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_DPCC_REG_DPCC_GPU_CBCR_CLK_ENABLE_SHFT                                                   0x0
#define HWIO_DPCC_REG_DPCC_GPU_CBCR_CLK_ENABLE_DISABLE_FVAL                                           0x0
#define HWIO_DPCC_REG_DPCC_GPU_CBCR_CLK_ENABLE_ENABLE_FVAL                                            0x1

#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_ADDR                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000060)
#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_OFFS                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000060)
#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_RMSK                                                   0x80000005
#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_MNOC_HF_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_ADDR                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000064)
#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_OFFS                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000064)
#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_RMSK                                                   0x80000005
#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_MNOC_SF_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_ADDR                                                      (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000068)
#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_OFFS                                                      (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000068)
#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_RMSK                                                      0x80000005
#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SNOC_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SNOC_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SNOC_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SNOC_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_SNOC_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_CLK_ARES_NO_RESET_FVAL                                           0x0
#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_CLK_ARES_RESET_FVAL                                              0x1
#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_CLK_ENABLE_SHFT                                                  0x0
#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_CLK_ENABLE_DISABLE_FVAL                                          0x0
#define HWIO_DPCC_REG_DPCC_SNOC_CBCR_CLK_ENABLE_ENABLE_FVAL                                           0x1

#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_ADDR                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000006c)
#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_OFFS                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000006c)
#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_RMSK                                                   0x80000005
#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_SNOC_GC_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_ADDR                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000070)
#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_OFFS                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000070)
#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_RMSK                                                   0x80000005
#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_SNOC_SF_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_ADDR                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000074)
#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_OFFS                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000074)
#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_RMSK                                                   0x80000005
#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_SYS_TCU_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_ADDR                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000078)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_OFFS                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000078)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_RMSK                                                  0x80000005
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_CLK_ARES_NO_RESET_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_CLK_ARES_RESET_FVAL                                          0x1
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_CLK_ENABLE_SHFT                                              0x0
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_CLK_ENABLE_DISABLE_FVAL                                      0x0
#define HWIO_DPCC_REG_DPCC_SHUB_CFG_CBCR_CLK_ENABLE_ENABLE_FVAL                                       0x1

#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_ADDR                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000007c)
#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_OFFS                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000007c)
#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_RMSK                                                  0x80000005
#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_CLK_ARES_NO_RESET_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_CLK_ARES_RESET_FVAL                                          0x1
#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_CLK_ENABLE_SHFT                                              0x0
#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_CLK_ENABLE_DISABLE_FVAL                                      0x0
#define HWIO_DPCC_REG_DPCC_SHUB_ATB_CBCR_CLK_ENABLE_ENABLE_FVAL                                       0x1

#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_ADDR                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000080)
#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_OFFS                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000080)
#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_RMSK                                                   0x80000005
#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_SHUB_TS_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_ADDR                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000084)
#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_OFFS                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000084)
#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_RMSK                                                   0x80000005
#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_PCIE_SF_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_DPCC_REG_DPCC_MC4_BCR_ADDR                                                        (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000088)
#define HWIO_DPCC_REG_DPCC_MC4_BCR_OFFS                                                        (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000088)
#define HWIO_DPCC_REG_DPCC_MC4_BCR_RMSK                                                               0x1
#define HWIO_DPCC_REG_DPCC_MC4_BCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MC4_BCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MC4_BCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MC4_BCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MC4_BCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MC4_BCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MC4_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MC4_BCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MC4_BCR_IN)
#define HWIO_DPCC_REG_DPCC_MC4_BCR_BLK_ARES_BMSK                                                      0x1
#define HWIO_DPCC_REG_DPCC_MC4_BCR_BLK_ARES_SHFT                                                      0x0
#define HWIO_DPCC_REG_DPCC_MC4_BCR_BLK_ARES_DISABLE_FVAL                                              0x0
#define HWIO_DPCC_REG_DPCC_MC4_BCR_BLK_ARES_ENABLE_FVAL                                               0x1

#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_ADDR                                                      (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000008c)
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_OFFS                                                      (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000008c)
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_RMSK                                                      0xf8ffffff
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MC4_GDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MC4_GDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MC4_GDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MC4_GDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MC4_GDSCR_IN)
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_PWR_ON_BMSK                                               0x80000000
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_PWR_ON_SHFT                                                     0x1f
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_GDSC_STATE_BMSK                                           0x78000000
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_GDSC_STATE_SHFT                                                 0x1b
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_EN_REST_WAIT_BMSK                                           0xf00000
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_EN_REST_WAIT_SHFT                                               0x14
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_EN_FEW_WAIT_BMSK                                             0xf0000
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_EN_FEW_WAIT_SHFT                                                0x10
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_CLK_DIS_WAIT_BMSK                                             0xf000
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_CLK_DIS_WAIT_SHFT                                                0xc
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_RETAIN_FF_ENABLE_BMSK                                          0x800
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_RETAIN_FF_ENABLE_SHFT                                            0xb
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL                                     0x1
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_RESTORE_BMSK                                                   0x400
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_RESTORE_SHFT                                                     0xa
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_RESTORE_DISABLE_FVAL                                             0x0
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_RESTORE_ENABLE_FVAL                                              0x1
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_SAVE_BMSK                                                      0x200
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_SAVE_SHFT                                                        0x9
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_SAVE_DISABLE_FVAL                                                0x0
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_SAVE_ENABLE_FVAL                                                 0x1
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_RETAIN_BMSK                                                    0x100
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_RETAIN_SHFT                                                      0x8
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_RETAIN_DISABLE_FVAL                                              0x0
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_RETAIN_ENABLE_FVAL                                               0x1
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_EN_REST_BMSK                                                    0x80
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_EN_REST_SHFT                                                     0x7
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_EN_REST_DISABLE_FVAL                                             0x0
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_EN_REST_ENABLE_FVAL                                              0x1
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_EN_FEW_BMSK                                                     0x40
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_EN_FEW_SHFT                                                      0x6
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_EN_FEW_DISABLE_FVAL                                              0x0
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_EN_FEW_ENABLE_FVAL                                               0x1
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_CLAMP_IO_BMSK                                                   0x20
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_CLAMP_IO_SHFT                                                    0x5
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_CLAMP_IO_DISABLE_FVAL                                            0x0
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_CLAMP_IO_ENABLE_FVAL                                             0x1
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_CLK_DISABLE_BMSK                                                0x10
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_CLK_DISABLE_SHFT                                                 0x4
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_CLK_DISABLE_CLK_DISABLE_FVAL                                     0x1
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_PD_ARES_BMSK                                                     0x8
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_PD_ARES_SHFT                                                     0x3
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_PD_ARES_NO_RESET_FVAL                                            0x0
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_PD_ARES_RESET_FVAL                                               0x1
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_SW_OVERRIDE_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_SW_OVERRIDE_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_SW_OVERRIDE_DISABLE_FVAL                                         0x0
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_SW_OVERRIDE_ENABLE_FVAL                                          0x1
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_HW_CONTROL_BMSK                                                  0x2
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_HW_CONTROL_SHFT                                                  0x1
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_HW_CONTROL_DISABLE_FVAL                                          0x0
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_HW_CONTROL_ENABLE_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_SW_COLLAPSE_BMSK                                                 0x1
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_SW_COLLAPSE_SHFT                                                 0x0
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_SW_COLLAPSE_DISABLE_FVAL                                         0x0
#define HWIO_DPCC_REG_DPCC_MC4_GDSCR_SW_COLLAPSE_ENABLE_FVAL                                          0x1

#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_ADDR                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000090)
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_OFFS                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000090)
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_RMSK                                                  0xffffffff
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_IN)
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_SPARE_CTRL_IN_BMSK                               0xf0000000
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_SPARE_CTRL_IN_SHFT                                     0x1c
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK                               0xc000000
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT                                    0x1a
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK                                0x2000000
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT                                     0x19
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_PWR_UP_START_BMSK                                 0x1000000
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_PWR_UP_START_SHFT                                      0x18
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK                          0xf00000
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT                              0x14
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                             0x80000
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                                0x13
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK                                 0x40000
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT                                    0x12
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK                                 0x20000
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT                                    0x11
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK                              0x10000
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT                                 0x10
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                             0x8000
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                                0xf
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                            0x7800
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                               0xb
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK                                    0x400
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT                                      0xa
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                             0x200
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                               0x9
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                             0x100
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                               0x8
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                                 0x80
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                                  0x7
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                        0x60
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                         0x5
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                                  0x10
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                                   0x4
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                            0x8
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                            0x3
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                          0x4
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                          0x2
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                              0x2
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                              0x1
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                           0x1
#define HWIO_DPCC_REG_DPCC_MC4_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                           0x0

#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_ADDR                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000094)
#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_OFFS                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000094)
#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_RMSK                                                    0x1ffff
#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_IN)
#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK                                  0x10000
#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT                                     0x10
#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK                                      0xf000
#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT                                         0xc
#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                               0xf00
#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                                 0x8
#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                                  0xf0
#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                                   0x4
#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                                    0xf
#define HWIO_DPCC_REG_DPCC_MC4_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                                    0x0

#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000098)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000098)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_RMSK                                                0x80000005
#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_CLK_ARES_RESET_FVAL                                        0x1
#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_CLK_ENABLE_BMSK                                            0x1
#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_CLK_ENABLE_SHFT                                            0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC4_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                     0x1

#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000009c)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000009c)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_RMSK                                                0x80000005
#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_CLK_ARES_RESET_FVAL                                        0x1
#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_CLK_ENABLE_BMSK                                            0x1
#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_CLK_ENABLE_SHFT                                            0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC4_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                     0x1

#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000a0)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000a0)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_RMSK                                                0x80000005
#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_CLK_ARES_RESET_FVAL                                        0x1
#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_CLK_ENABLE_BMSK                                            0x1
#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_CLK_ENABLE_SHFT                                            0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC4_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                     0x1

#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000a4)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000a4)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_RMSK                                                0x80000005
#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_CLK_ARES_RESET_FVAL                                        0x1
#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_CLK_ENABLE_BMSK                                            0x1
#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_CLK_ENABLE_SHFT                                            0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC4_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                     0x1

#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_ADDR                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000a8)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_OFFS                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000a8)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_RMSK                                             0x80000005
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_CLK_OFF_BMSK                                     0x80000000
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_CLK_OFF_SHFT                                           0x1f
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_CLK_ARES_BMSK                                           0x4
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_CLK_ARES_SHFT                                           0x2
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_CLK_ARES_RESET_FVAL                                     0x1
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_CLK_ENABLE_BMSK                                         0x1
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_CLK_ENABLE_SHFT                                         0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL                                  0x1

#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_ADDR                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000ac)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_OFFS                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000ac)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_RMSK                                             0x80000005
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_CLK_OFF_BMSK                                     0x80000000
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_CLK_OFF_SHFT                                           0x1f
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_CLK_ARES_BMSK                                           0x4
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_CLK_ARES_SHFT                                           0x2
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_CLK_ARES_RESET_FVAL                                     0x1
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_CLK_ENABLE_BMSK                                         0x1
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_CLK_ENABLE_SHFT                                         0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL                                  0x1

#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_ADDR                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000b0)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_OFFS                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000b0)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_RMSK                                             0x80000005
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_CLK_OFF_BMSK                                     0x80000000
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_CLK_OFF_SHFT                                           0x1f
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_CLK_ARES_BMSK                                           0x4
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_CLK_ARES_SHFT                                           0x2
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_CLK_ARES_RESET_FVAL                                     0x1
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_CLK_ENABLE_BMSK                                         0x1
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_CLK_ENABLE_SHFT                                         0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL                                  0x1

#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_ADDR                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000b4)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_OFFS                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000b4)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_RMSK                                             0x80000005
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_CLK_OFF_BMSK                                     0x80000000
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_CLK_OFF_SHFT                                           0x1f
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_CLK_ARES_BMSK                                           0x4
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_CLK_ARES_SHFT                                           0x2
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_CLK_ARES_RESET_FVAL                                     0x1
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_CLK_ENABLE_BMSK                                         0x1
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_CLK_ENABLE_SHFT                                         0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL                                  0x1

#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_ADDR                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000b8)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_OFFS                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000b8)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_RMSK                                              0x80000005
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_CLK_OFF_BMSK                                      0x80000000
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_CLK_OFF_SHFT                                            0x1f
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_CLK_ARES_BMSK                                            0x4
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_CLK_ARES_SHFT                                            0x2
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_CLK_ARES_RESET_FVAL                                      0x1
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_CLK_ENABLE_BMSK                                          0x1
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_CLK_ENABLE_SHFT                                          0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC4_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL                                   0x1

#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_ADDR                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000bc)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_OFFS                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000bc)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_RMSK                                              0x80000005
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_CLK_OFF_BMSK                                      0x80000000
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_CLK_OFF_SHFT                                            0x1f
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_CLK_ARES_BMSK                                            0x4
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_CLK_ARES_SHFT                                            0x2
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_CLK_ARES_RESET_FVAL                                      0x1
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_CLK_ENABLE_BMSK                                          0x1
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_CLK_ENABLE_SHFT                                          0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC4_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL                                   0x1

#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_ADDR                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000c0)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_OFFS                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000c0)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_RMSK                                              0x80000005
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_CLK_OFF_BMSK                                      0x80000000
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_CLK_OFF_SHFT                                            0x1f
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_CLK_ARES_BMSK                                            0x4
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_CLK_ARES_SHFT                                            0x2
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_CLK_ARES_RESET_FVAL                                      0x1
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_CLK_ENABLE_BMSK                                          0x1
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_CLK_ENABLE_SHFT                                          0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC4_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL                                   0x1

#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_ADDR                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000c4)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_OFFS                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000c4)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_RMSK                                              0x80000005
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_CLK_OFF_BMSK                                      0x80000000
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_CLK_OFF_SHFT                                            0x1f
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_CLK_ARES_BMSK                                            0x4
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_CLK_ARES_SHFT                                            0x2
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_CLK_ARES_RESET_FVAL                                      0x1
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_CLK_ENABLE_BMSK                                          0x1
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_CLK_ENABLE_SHFT                                          0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC4_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL                                   0x1

#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_ADDR                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000c8)
#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_OFFS                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000c8)
#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_RMSK                                                   0x80000005
#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_MC4_CFG_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_ADDR                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000cc)
#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_OFFS                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000cc)
#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_RMSK                                                   0x80000005
#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_MC4_ATB_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_DPCC_REG_DPCC_MC5_BCR_ADDR                                                        (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000d0)
#define HWIO_DPCC_REG_DPCC_MC5_BCR_OFFS                                                        (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000d0)
#define HWIO_DPCC_REG_DPCC_MC5_BCR_RMSK                                                               0x1
#define HWIO_DPCC_REG_DPCC_MC5_BCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MC5_BCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MC5_BCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MC5_BCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MC5_BCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MC5_BCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MC5_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MC5_BCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MC5_BCR_IN)
#define HWIO_DPCC_REG_DPCC_MC5_BCR_BLK_ARES_BMSK                                                      0x1
#define HWIO_DPCC_REG_DPCC_MC5_BCR_BLK_ARES_SHFT                                                      0x0
#define HWIO_DPCC_REG_DPCC_MC5_BCR_BLK_ARES_DISABLE_FVAL                                              0x0
#define HWIO_DPCC_REG_DPCC_MC5_BCR_BLK_ARES_ENABLE_FVAL                                               0x1

#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_ADDR                                                      (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000d4)
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_OFFS                                                      (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000d4)
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_RMSK                                                      0xf8ffffff
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MC5_GDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MC5_GDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MC5_GDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MC5_GDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MC5_GDSCR_IN)
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_PWR_ON_BMSK                                               0x80000000
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_PWR_ON_SHFT                                                     0x1f
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_GDSC_STATE_BMSK                                           0x78000000
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_GDSC_STATE_SHFT                                                 0x1b
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_EN_REST_WAIT_BMSK                                           0xf00000
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_EN_REST_WAIT_SHFT                                               0x14
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_EN_FEW_WAIT_BMSK                                             0xf0000
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_EN_FEW_WAIT_SHFT                                                0x10
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_CLK_DIS_WAIT_BMSK                                             0xf000
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_CLK_DIS_WAIT_SHFT                                                0xc
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_RETAIN_FF_ENABLE_BMSK                                          0x800
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_RETAIN_FF_ENABLE_SHFT                                            0xb
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL                                     0x1
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_RESTORE_BMSK                                                   0x400
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_RESTORE_SHFT                                                     0xa
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_RESTORE_DISABLE_FVAL                                             0x0
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_RESTORE_ENABLE_FVAL                                              0x1
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_SAVE_BMSK                                                      0x200
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_SAVE_SHFT                                                        0x9
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_SAVE_DISABLE_FVAL                                                0x0
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_SAVE_ENABLE_FVAL                                                 0x1
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_RETAIN_BMSK                                                    0x100
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_RETAIN_SHFT                                                      0x8
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_RETAIN_DISABLE_FVAL                                              0x0
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_RETAIN_ENABLE_FVAL                                               0x1
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_EN_REST_BMSK                                                    0x80
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_EN_REST_SHFT                                                     0x7
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_EN_REST_DISABLE_FVAL                                             0x0
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_EN_REST_ENABLE_FVAL                                              0x1
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_EN_FEW_BMSK                                                     0x40
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_EN_FEW_SHFT                                                      0x6
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_EN_FEW_DISABLE_FVAL                                              0x0
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_EN_FEW_ENABLE_FVAL                                               0x1
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_CLAMP_IO_BMSK                                                   0x20
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_CLAMP_IO_SHFT                                                    0x5
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_CLAMP_IO_DISABLE_FVAL                                            0x0
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_CLAMP_IO_ENABLE_FVAL                                             0x1
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_CLK_DISABLE_BMSK                                                0x10
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_CLK_DISABLE_SHFT                                                 0x4
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_CLK_DISABLE_CLK_DISABLE_FVAL                                     0x1
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_PD_ARES_BMSK                                                     0x8
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_PD_ARES_SHFT                                                     0x3
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_PD_ARES_NO_RESET_FVAL                                            0x0
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_PD_ARES_RESET_FVAL                                               0x1
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_SW_OVERRIDE_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_SW_OVERRIDE_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_SW_OVERRIDE_DISABLE_FVAL                                         0x0
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_SW_OVERRIDE_ENABLE_FVAL                                          0x1
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_HW_CONTROL_BMSK                                                  0x2
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_HW_CONTROL_SHFT                                                  0x1
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_HW_CONTROL_DISABLE_FVAL                                          0x0
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_HW_CONTROL_ENABLE_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_SW_COLLAPSE_BMSK                                                 0x1
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_SW_COLLAPSE_SHFT                                                 0x0
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_SW_COLLAPSE_DISABLE_FVAL                                         0x0
#define HWIO_DPCC_REG_DPCC_MC5_GDSCR_SW_COLLAPSE_ENABLE_FVAL                                          0x1

#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_ADDR                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000d8)
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_OFFS                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000d8)
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_RMSK                                                  0xffffffff
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_IN)
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_SPARE_CTRL_IN_BMSK                               0xf0000000
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_SPARE_CTRL_IN_SHFT                                     0x1c
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK                               0xc000000
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT                                    0x1a
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK                                0x2000000
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT                                     0x19
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_PWR_UP_START_BMSK                                 0x1000000
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_PWR_UP_START_SHFT                                      0x18
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK                          0xf00000
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT                              0x14
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                             0x80000
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                                0x13
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK                                 0x40000
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT                                    0x12
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK                                 0x20000
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT                                    0x11
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK                              0x10000
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT                                 0x10
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                             0x8000
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                                0xf
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                            0x7800
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                               0xb
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK                                    0x400
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT                                      0xa
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                             0x200
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                               0x9
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                             0x100
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                               0x8
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                                 0x80
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                                  0x7
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                        0x60
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                         0x5
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                                  0x10
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                                   0x4
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                            0x8
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                            0x3
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                          0x4
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                          0x2
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                              0x2
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                              0x1
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                           0x1
#define HWIO_DPCC_REG_DPCC_MC5_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                           0x0

#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_ADDR                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000dc)
#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_OFFS                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000dc)
#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_RMSK                                                    0x1ffff
#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_IN)
#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK                                  0x10000
#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT                                     0x10
#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK                                      0xf000
#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT                                         0xc
#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                               0xf00
#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                                 0x8
#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                                  0xf0
#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                                   0x4
#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                                    0xf
#define HWIO_DPCC_REG_DPCC_MC5_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                                    0x0

#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000e0)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000e0)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_RMSK                                                0x80000005
#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_CLK_ARES_RESET_FVAL                                        0x1
#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_CLK_ENABLE_BMSK                                            0x1
#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_CLK_ENABLE_SHFT                                            0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC5_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                     0x1

#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000e4)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000e4)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_RMSK                                                0x80000005
#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_CLK_ARES_RESET_FVAL                                        0x1
#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_CLK_ENABLE_BMSK                                            0x1
#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_CLK_ENABLE_SHFT                                            0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC5_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                     0x1

#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000e8)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000e8)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_RMSK                                                0x80000005
#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_CLK_ARES_RESET_FVAL                                        0x1
#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_CLK_ENABLE_BMSK                                            0x1
#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_CLK_ENABLE_SHFT                                            0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC5_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                     0x1

#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000ec)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000ec)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_RMSK                                                0x80000005
#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_CLK_ARES_RESET_FVAL                                        0x1
#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_CLK_ENABLE_BMSK                                            0x1
#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_CLK_ENABLE_SHFT                                            0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC5_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                     0x1

#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_ADDR                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000f0)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_OFFS                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000f0)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_RMSK                                             0x80000005
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_CLK_OFF_BMSK                                     0x80000000
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_CLK_OFF_SHFT                                           0x1f
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_CLK_ARES_BMSK                                           0x4
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_CLK_ARES_SHFT                                           0x2
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_CLK_ARES_RESET_FVAL                                     0x1
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_CLK_ENABLE_BMSK                                         0x1
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_CLK_ENABLE_SHFT                                         0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL                                  0x1

#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_ADDR                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000f4)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_OFFS                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000f4)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_RMSK                                             0x80000005
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_CLK_OFF_BMSK                                     0x80000000
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_CLK_OFF_SHFT                                           0x1f
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_CLK_ARES_BMSK                                           0x4
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_CLK_ARES_SHFT                                           0x2
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_CLK_ARES_RESET_FVAL                                     0x1
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_CLK_ENABLE_BMSK                                         0x1
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_CLK_ENABLE_SHFT                                         0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL                                  0x1

#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_ADDR                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000f8)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_OFFS                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000f8)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_RMSK                                             0x80000005
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_CLK_OFF_BMSK                                     0x80000000
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_CLK_OFF_SHFT                                           0x1f
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_CLK_ARES_BMSK                                           0x4
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_CLK_ARES_SHFT                                           0x2
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_CLK_ARES_RESET_FVAL                                     0x1
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_CLK_ENABLE_BMSK                                         0x1
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_CLK_ENABLE_SHFT                                         0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL                                  0x1

#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_ADDR                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x000000fc)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_OFFS                                             (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x000000fc)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_RMSK                                             0x80000005
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_CLK_OFF_BMSK                                     0x80000000
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_CLK_OFF_SHFT                                           0x1f
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_CLK_ARES_BMSK                                           0x4
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_CLK_ARES_SHFT                                           0x2
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_CLK_ARES_RESET_FVAL                                     0x1
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_CLK_ENABLE_BMSK                                         0x1
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_CLK_ENABLE_SHFT                                         0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL                                  0x1

#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_ADDR                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000100)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_OFFS                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000100)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_RMSK                                              0x80000005
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_CLK_OFF_BMSK                                      0x80000000
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_CLK_OFF_SHFT                                            0x1f
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_CLK_ARES_BMSK                                            0x4
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_CLK_ARES_SHFT                                            0x2
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_CLK_ARES_RESET_FVAL                                      0x1
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_CLK_ENABLE_BMSK                                          0x1
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_CLK_ENABLE_SHFT                                          0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_CH0_MC5_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL                                   0x1

#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_ADDR                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000104)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_OFFS                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000104)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_RMSK                                              0x80000005
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_CLK_OFF_BMSK                                      0x80000000
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_CLK_OFF_SHFT                                            0x1f
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_CLK_ARES_BMSK                                            0x4
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_CLK_ARES_SHFT                                            0x2
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_CLK_ARES_RESET_FVAL                                      0x1
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_CLK_ENABLE_BMSK                                          0x1
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_CLK_ENABLE_SHFT                                          0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_CH1_MC5_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL                                   0x1

#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_ADDR                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000108)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_OFFS                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000108)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_RMSK                                              0x80000005
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_CLK_OFF_BMSK                                      0x80000000
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_CLK_OFF_SHFT                                            0x1f
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_CLK_ARES_BMSK                                            0x4
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_CLK_ARES_SHFT                                            0x2
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_CLK_ARES_RESET_FVAL                                      0x1
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_CLK_ENABLE_BMSK                                          0x1
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_CLK_ENABLE_SHFT                                          0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_CH2_MC5_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL                                   0x1

#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_ADDR                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000010c)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_OFFS                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000010c)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_RMSK                                              0x80000005
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_CLK_OFF_BMSK                                      0x80000000
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_CLK_OFF_SHFT                                            0x1f
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_CLK_ARES_BMSK                                            0x4
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_CLK_ARES_SHFT                                            0x2
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_CLK_ARES_NO_RESET_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_CLK_ARES_RESET_FVAL                                      0x1
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_CLK_ENABLE_BMSK                                          0x1
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_CLK_ENABLE_SHFT                                          0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_CLK_ENABLE_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_CH3_MC5_SHUB_CBCR_CLK_ENABLE_ENABLE_FVAL                                   0x1

#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_ADDR                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000110)
#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_OFFS                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000110)
#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_RMSK                                                   0x80000005
#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_MC5_CFG_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_ADDR                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000114)
#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_OFFS                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000114)
#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_RMSK                                                   0x80000005
#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_MC5_ATB_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_DPCC_REG_DPCC_PHY_BCR_ADDR                                                        (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000118)
#define HWIO_DPCC_REG_DPCC_PHY_BCR_OFFS                                                        (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000118)
#define HWIO_DPCC_REG_DPCC_PHY_BCR_RMSK                                                               0x1
#define HWIO_DPCC_REG_DPCC_PHY_BCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PHY_BCR_ADDR)
#define HWIO_DPCC_REG_DPCC_PHY_BCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PHY_BCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PHY_BCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PHY_BCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PHY_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PHY_BCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PHY_BCR_IN)
#define HWIO_DPCC_REG_DPCC_PHY_BCR_BLK_ARES_BMSK                                                      0x1
#define HWIO_DPCC_REG_DPCC_PHY_BCR_BLK_ARES_SHFT                                                      0x0
#define HWIO_DPCC_REG_DPCC_PHY_BCR_BLK_ARES_DISABLE_FVAL                                              0x0
#define HWIO_DPCC_REG_DPCC_PHY_BCR_BLK_ARES_ENABLE_FVAL                                               0x1

#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_ADDR                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000011c)
#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_OFFS                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000011c)
#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_RMSK                                                   0x80000005
#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_PHY0_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000120)
#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000120)
#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_RMSK                                                0x80000005
#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_CLK_ARES_RESET_FVAL                                        0x1
#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_CLK_ENABLE_BMSK                                            0x1
#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_CLK_ENABLE_SHFT                                            0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL                                     0x1

#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_ADDR                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000124)
#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_OFFS                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000124)
#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_RMSK                                                  0x80000005
#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_CLK_ARES_NO_RESET_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_CLK_ARES_RESET_FVAL                                          0x1
#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_CLK_ENABLE_SHFT                                              0x0
#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_CLK_ENABLE_DISABLE_FVAL                                      0x0
#define HWIO_DPCC_REG_DPCC_PHY0_ATB_CBCR_CLK_ENABLE_ENABLE_FVAL                                       0x1

#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_ADDR                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000128)
#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_OFFS                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000128)
#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_RMSK                                                   0x80000005
#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_PHY1_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000012c)
#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000012c)
#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_RMSK                                                0x80000005
#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_CLK_ARES_RESET_FVAL                                        0x1
#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_CLK_ENABLE_BMSK                                            0x1
#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_CLK_ENABLE_SHFT                                            0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL                                     0x1

#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_ADDR                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000130)
#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_OFFS                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000130)
#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_RMSK                                                  0x80000005
#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_CLK_ARES_NO_RESET_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_CLK_ARES_RESET_FVAL                                          0x1
#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_CLK_ENABLE_SHFT                                              0x0
#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_CLK_ENABLE_DISABLE_FVAL                                      0x0
#define HWIO_DPCC_REG_DPCC_PHY1_ATB_CBCR_CLK_ENABLE_ENABLE_FVAL                                       0x1

#define HWIO_DPCC_REG_DPCC_SHRM_BCR_ADDR                                                       (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000134)
#define HWIO_DPCC_REG_DPCC_SHRM_BCR_OFFS                                                       (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000134)
#define HWIO_DPCC_REG_DPCC_SHRM_BCR_RMSK                                                              0x1
#define HWIO_DPCC_REG_DPCC_SHRM_BCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHRM_BCR_ADDR)
#define HWIO_DPCC_REG_DPCC_SHRM_BCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHRM_BCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHRM_BCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHRM_BCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHRM_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHRM_BCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHRM_BCR_IN)
#define HWIO_DPCC_REG_DPCC_SHRM_BCR_BLK_ARES_BMSK                                                     0x1
#define HWIO_DPCC_REG_DPCC_SHRM_BCR_BLK_ARES_SHFT                                                     0x0
#define HWIO_DPCC_REG_DPCC_SHRM_BCR_BLK_ARES_DISABLE_FVAL                                             0x0
#define HWIO_DPCC_REG_DPCC_SHRM_BCR_BLK_ARES_ENABLE_FVAL                                              0x1

#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_ADDR                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000138)
#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_OFFS                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000138)
#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_RMSK                                                   0x80000005
#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_SHRM_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_ADDR                                                      (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000013c)
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_OFFS                                                      (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000013c)
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_RMSK                                                      0x80007ff5
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHRM_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHRM_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHRM_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHRM_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHRM_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_FORCE_MEM_CORE_ON_BMSK                                        0x4000
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_FORCE_MEM_CORE_ON_SHFT                                           0xe
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_FORCE_MEM_CORE_ON_FORCE_DISABLE_FVAL                             0x0
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_FORCE_MEM_CORE_ON_FORCE_ENABLE_FVAL                              0x1
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                      0x2000
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                         0xd
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_FORCE_MEM_PERIPH_ON_FORCE_DISABLE_FVAL                           0x0
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_FORCE_MEM_PERIPH_ON_FORCE_ENABLE_FVAL                            0x1
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                     0x1000
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                        0xc
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_DISABLE_FVAL                          0x0
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_FORCE_MEM_PERIPH_OFF_FORCE_ENABLE_FVAL                           0x1
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_BMSK                                                    0xf00
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_SHFT                                                      0x8
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_CLOCK0_FVAL                                               0x0
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_CLOCK1_FVAL                                               0x1
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_CLOCK2_FVAL                                               0x2
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_CLOCK3_FVAL                                               0x3
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_CLOCK4_FVAL                                               0x4
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_CLOCK5_FVAL                                               0x5
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_CLOCK6_FVAL                                               0x6
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_CLOCK7_FVAL                                               0x7
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_CLOCK8_FVAL                                               0x8
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_CLOCK9_FVAL                                               0x9
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_CLOCK10_FVAL                                              0xa
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_CLOCK11_FVAL                                              0xb
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_CLOCK12_FVAL                                              0xc
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_CLOCK13_FVAL                                              0xd
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_CLOCK14_FVAL                                              0xe
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_WAKEUP_CLOCK15_FVAL                                              0xf
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_BMSK                                                      0xf0
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_SHFT                                                       0x4
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_CLOCK0_FVAL                                                0x0
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_CLOCK1_FVAL                                                0x1
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_CLOCK2_FVAL                                                0x2
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_CLOCK3_FVAL                                                0x3
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_CLOCK4_FVAL                                                0x4
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_CLOCK5_FVAL                                                0x5
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_CLOCK6_FVAL                                                0x6
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_CLOCK7_FVAL                                                0x7
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_CLOCK8_FVAL                                                0x8
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_CLOCK9_FVAL                                                0x9
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_CLOCK10_FVAL                                               0xa
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_CLOCK11_FVAL                                               0xb
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_CLOCK12_FVAL                                               0xc
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_CLOCK13_FVAL                                               0xd
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_CLOCK14_FVAL                                               0xe
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_SLEEP_CLOCK15_FVAL                                               0xf
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_CLK_ARES_NO_RESET_FVAL                                           0x0
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_CLK_ARES_RESET_FVAL                                              0x1
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_CLK_ENABLE_SHFT                                                  0x0
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_CLK_ENABLE_DISABLE_FVAL                                          0x0
#define HWIO_DPCC_REG_DPCC_SHRM_CBCR_CLK_ENABLE_ENABLE_FVAL                                           0x1

#define HWIO_DPCC_REG_DPCC_MCCC_BCR_ADDR                                                       (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000140)
#define HWIO_DPCC_REG_DPCC_MCCC_BCR_OFFS                                                       (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000140)
#define HWIO_DPCC_REG_DPCC_MCCC_BCR_RMSK                                                              0x1
#define HWIO_DPCC_REG_DPCC_MCCC_BCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MCCC_BCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MCCC_BCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MCCC_BCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MCCC_BCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MCCC_BCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MCCC_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MCCC_BCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MCCC_BCR_IN)
#define HWIO_DPCC_REG_DPCC_MCCC_BCR_BLK_ARES_BMSK                                                     0x1
#define HWIO_DPCC_REG_DPCC_MCCC_BCR_BLK_ARES_SHFT                                                     0x0
#define HWIO_DPCC_REG_DPCC_MCCC_BCR_BLK_ARES_DISABLE_FVAL                                             0x0
#define HWIO_DPCC_REG_DPCC_MCCC_BCR_BLK_ARES_ENABLE_FVAL                                              0x1

#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_ADDR                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000144)
#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_OFFS                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000144)
#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_RMSK                                                   0x80000005
#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_MCCC_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_ADDR                                                      (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000148)
#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_OFFS                                                      (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000148)
#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_RMSK                                                      0x80000005
#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MCCC_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MCCC_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MCCC_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MCCC_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_MCCC_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_CLK_ARES_NO_RESET_FVAL                                           0x0
#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_CLK_ARES_RESET_FVAL                                              0x1
#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_CLK_ENABLE_SHFT                                                  0x0
#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_CLK_ENABLE_DISABLE_FVAL                                          0x0
#define HWIO_DPCC_REG_DPCC_MCCC_CBCR_CLK_ENABLE_ENABLE_FVAL                                           0x1

#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_BCR_ADDR                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000014c)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_BCR_OFFS                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000014c)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_BCR_RMSK                                                         0x1
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_BCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_DDRSS_TOP_BCR_ADDR)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_BCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_DDRSS_TOP_BCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_BCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_DDRSS_TOP_BCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_DDRSS_TOP_BCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_DDRSS_TOP_BCR_IN)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_BCR_BLK_ARES_BMSK                                                0x1
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_BCR_BLK_ARES_SHFT                                                0x0
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_BCR_BLK_ARES_DISABLE_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_BCR_BLK_ARES_ENABLE_FVAL                                         0x1

#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_ADDR                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000150)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_OFFS                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000150)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_RMSK                                              0x80000005
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_CLK_OFF_BMSK                                      0x80000000
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_CLK_OFF_SHFT                                            0x1f
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_CLK_ARES_BMSK                                            0x4
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_CLK_ARES_SHFT                                            0x2
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_CLK_ARES_RESET_FVAL                                      0x1
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_CLK_ENABLE_BMSK                                          0x1
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_CLK_ENABLE_SHFT                                          0x0
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                   0x1

#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_ADDR                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000154)
#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_OFFS                                                   (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000154)
#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_RMSK                                                   0x80000005
#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_CLK_ARES_NO_RESET_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_CLK_ARES_RESET_FVAL                                           0x1
#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_CLK_ENABLE_SHFT                                               0x0
#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_CLK_ENABLE_DISABLE_FVAL                                       0x0
#define HWIO_DPCC_REG_DPCC_AHB2PHY_CBCR_CLK_ENABLE_ENABLE_FVAL                                        0x1

#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_ADDR                                                    (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000158)
#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_OFFS                                                    (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000158)
#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_RMSK                                                    0x80000005
#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_CLK_ARES_NO_RESET_FVAL                                         0x0
#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_CLK_ARES_RESET_FVAL                                            0x1
#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_CLK_ENABLE_SHFT                                                0x0
#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_CLK_ENABLE_DISABLE_FVAL                                        0x0
#define HWIO_DPCC_REG_DPCC_TGU_XO_CBCR_CLK_ENABLE_ENABLE_FVAL                                         0x1

#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_ADDR                                           (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000015c)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_OFFS                                           (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000015c)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_RMSK                                           0x80000005
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_CLK_OFF_BMSK                                   0x80000000
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_CLK_OFF_SHFT                                         0x1f
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_CLK_ARES_BMSK                                         0x4
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_CLK_ARES_SHFT                                         0x2
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_CLK_ARES_NO_RESET_FVAL                                0x0
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_CLK_ARES_RESET_FVAL                                   0x1
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_CLK_ENABLE_BMSK                                       0x1
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_CLK_ENABLE_SHFT                                       0x0
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_CLK_ENABLE_DISABLE_FVAL                               0x0
#define HWIO_DPCC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR_CLK_ENABLE_ENABLE_FVAL                                0x1

#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_DIV_CDIVR_ADDR                                            (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000160)
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_DIV_CDIVR_OFFS                                            (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000160)
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_DIV_CDIVR_RMSK                                                   0x3
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_DIV_CDIVR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_DCNOC_CFG_DIV_CDIVR_ADDR)
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_DCNOC_CFG_DIV_CDIVR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_DCNOC_CFG_DIV_CDIVR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_DCNOC_CFG_DIV_CDIVR_ADDR,m,v,HWIO_DPCC_REG_DPCC_DCNOC_CFG_DIV_CDIVR_IN)
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_DIV_CDIVR_CLK_DIV_BMSK                                           0x3
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_DIV_CDIVR_CLK_DIV_SHFT                                           0x0

#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_ADDR                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000164)
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_OFFS                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000164)
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_RMSK                                                 0x80000005
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_ADDR)
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_IN)
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_CLK_OFF_BMSK                                         0x80000000
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_CLK_OFF_SHFT                                               0x1f
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_CLK_ARES_BMSK                                               0x4
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_CLK_ARES_SHFT                                               0x2
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_CLK_ARES_NO_RESET_FVAL                                      0x0
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_CLK_ARES_RESET_FVAL                                         0x1
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_CLK_ENABLE_BMSK                                             0x1
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_CLK_ENABLE_SHFT                                             0x0
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_CLK_ENABLE_DISABLE_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_DCNOC_CFG_CBCR_CLK_ENABLE_ENABLE_FVAL                                      0x1

#define HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_ADDR                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00002000)
#define HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_OFFS                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00002000)
#define HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_RMSK                                                        0x3
#define HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_IN)
#define HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_RETAIN_FF_ENABLE_BMSK                                       0x2
#define HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_RETAIN_FF_ENABLE_SHFT                                       0x1
#define HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL                               0x0
#define HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL                                0x1
#define HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_SW_OVERRIDE_BMSK                                            0x1
#define HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_SW_OVERRIDE_SHFT                                            0x0
#define HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_SW_OVERRIDE_DISABLE_FVAL                                    0x0
#define HWIO_DPCC_REG_DPCC_TZ_SHUB_SGDSCR_SW_OVERRIDE_ENABLE_FVAL                                     0x1

#define HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_ADDR                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00002004)
#define HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_OFFS                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00002004)
#define HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_RMSK                                                         0x3
#define HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_IN)
#define HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_RETAIN_FF_ENABLE_BMSK                                        0x2
#define HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_RETAIN_FF_ENABLE_SHFT                                        0x1
#define HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL                                0x0
#define HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL                                 0x1
#define HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_SW_OVERRIDE_BMSK                                             0x1
#define HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_SW_OVERRIDE_SHFT                                             0x0
#define HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_SW_OVERRIDE_DISABLE_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_TZ_MC5_SGDSCR_SW_OVERRIDE_ENABLE_FVAL                                      0x1

#define HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_ADDR                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00002008)
#define HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_OFFS                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00002008)
#define HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_RMSK                                                         0x3
#define HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_IN)
#define HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_RETAIN_FF_ENABLE_BMSK                                        0x2
#define HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_RETAIN_FF_ENABLE_SHFT                                        0x1
#define HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL                                0x0
#define HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL                                 0x1
#define HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_SW_OVERRIDE_BMSK                                             0x1
#define HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_SW_OVERRIDE_SHFT                                             0x0
#define HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_SW_OVERRIDE_DISABLE_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_TZ_MC4_SGDSCR_SW_OVERRIDE_ENABLE_FVAL                                      0x1

#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_ADDR                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000000)
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_OFFS                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000000)
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_RMSK                                                       0x7f
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_ADDR)
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_ADDR,m,v,HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_IN)
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_BMSK                                               0x7f
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_SHFT                                                0x0
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_LLCC0_XO_CLK_FVAL                              0x0
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_LLCC1_XO_CLK_FVAL                              0x1
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_LLCC2_XO_CLK_FVAL                              0x2
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_LLCC3_XO_CLK_FVAL                              0x3
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_GEMNOC_XO_CLK_FVAL                             0x4
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_LLCC0_SHUB_CLK_FVAL                            0x5
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_LLCC1_SHUB_CLK_FVAL                            0x6
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_LLCC2_SHUB_CLK_FVAL                            0x7
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_LLCC3_SHUB_CLK_FVAL                            0x8
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_LAGG_SHUB_CLK_FVAL                             0x9
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_GEMNOC_SHUB_CLK_FVAL                           0xa
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_GEMNOC_SHUB_SLP_STG_CLK_FVAL                   0xb
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CMPNOC_CLK_FVAL                                0xc
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_GPU_CLK_FVAL                                   0xd
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_MNOC_HF_CLK_FVAL                               0xe
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_MNOC_SF_CLK_FVAL                               0xf
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_SNOC_CLK_FVAL                                 0x10
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_SNOC_GC_CLK_FVAL                              0x11
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_SNOC_SF_CLK_FVAL                              0x12
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_SYS_TCU_CLK_FVAL                              0x13
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_SHUB_CFG_CLK_FVAL                             0x14
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_SHUB_ATB_CLK_FVAL                             0x15
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_SHUB_TS_CLK_FVAL                              0x16
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_PCIE_SF_CLK_FVAL                              0x17
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH0_MC4_XO_CLK_FVAL                           0x18
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH1_MC4_XO_CLK_FVAL                           0x19
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH2_MC4_XO_CLK_FVAL                           0x1a
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH3_MC4_XO_CLK_FVAL                           0x1b
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH0_MC4_SLEEP_CLK_FVAL                        0x1c
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH1_MC4_SLEEP_CLK_FVAL                        0x1d
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH2_MC4_SLEEP_CLK_FVAL                        0x1e
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH3_MC4_SLEEP_CLK_FVAL                        0x1f
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH0_MC4_SHUB_CLK_FVAL                         0x20
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH1_MC4_SHUB_CLK_FVAL                         0x21
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH2_MC4_SHUB_CLK_FVAL                         0x22
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH3_MC4_SHUB_CLK_FVAL                         0x23
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_MC4_CFG_CLK_FVAL                              0x24
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_MC4_ATB_CLK_FVAL                              0x25
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH0_MC5_XO_CLK_FVAL                           0x26
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH1_MC5_XO_CLK_FVAL                           0x27
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH2_MC5_XO_CLK_FVAL                           0x28
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH3_MC5_XO_CLK_FVAL                           0x29
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH0_MC5_SLEEP_CLK_FVAL                        0x2a
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH1_MC5_SLEEP_CLK_FVAL                        0x2b
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH2_MC5_SLEEP_CLK_FVAL                        0x2c
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH3_MC5_SLEEP_CLK_FVAL                        0x2d
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH0_MC5_SHUB_CLK_FVAL                         0x2e
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH1_MC5_SHUB_CLK_FVAL                         0x2f
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH2_MC5_SHUB_CLK_FVAL                         0x30
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_CH3_MC5_SHUB_CLK_FVAL                         0x31
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_MC5_CFG_CLK_FVAL                              0x32
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_MC5_ATB_CLK_FVAL                              0x33
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_PHY0_XO_CLK_FVAL                              0x34
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_PHY0_SLEEP_CLK_FVAL                           0x35
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_PHY0_ATB_CLK_FVAL                             0x36
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_PHY1_XO_CLK_FVAL                              0x37
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_PHY1_SLEEP_CLK_FVAL                           0x38
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_PHY1_ATB_CLK_FVAL                             0x39
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_SHRM_XO_CLK_FVAL                              0x3a
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_SHRM_CLK_FVAL                                 0x3b
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_MCCC_XO_CLK_FVAL                              0x3c
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_MCCC_CLK_FVAL                                 0x3d
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_DDRSS_TOP_XO_CLK_FVAL                         0x3e
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_AHB2PHY_CLK_FVAL                              0x3f
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_TGU_XO_CLK_FVAL                               0x40
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_DDRSS_TOP_SLEEP_CLK_FVAL                      0x41
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DPCC_DCNOC_CFG_CLK_FVAL                            0x42
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_MCCC_DEBUG0_CLK_FVAL                               0x43
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_MCCC_DEBUG1_CLK_FVAL                               0x44
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_MCCC_DEBUG2_CLK_FVAL                               0x45
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_MCCC_DEBUG3_CLK_FVAL                               0x46
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_MCCC_DEBUG4_CLK_FVAL                               0x47
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DDRCC_PLL_TEST0_CLK_FVAL                           0x48
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_DDRCC_PLL_TEST1_CLK_FVAL                           0x49
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_MCCC_PLL_TEST2_CLK_FVAL                            0x4a
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_MCCC_PLL_TEST3_CLK_FVAL                            0x4b
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_MCCC_PLL_TEST4_CLK_FVAL                            0x4c
#define HWIO_DPCC_REG_DPCC_DEBUG_MUX_MUXR_MUX_SEL_MCCC_PLL_TEST5_CLK_FVAL                            0x4d

#define HWIO_DPCC_REG_DPCC_PLL_TEST_MUX_MUXR_ADDR                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000000c)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_MUX_MUXR_OFFS                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000000c)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_MUX_MUXR_RMSK                                                    0x3f
#define HWIO_DPCC_REG_DPCC_PLL_TEST_MUX_MUXR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PLL_TEST_MUX_MUXR_ADDR)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_MUX_MUXR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PLL_TEST_MUX_MUXR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_MUX_MUXR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PLL_TEST_MUX_MUXR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_MUX_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PLL_TEST_MUX_MUXR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PLL_TEST_MUX_MUXR_IN)
#define HWIO_DPCC_REG_DPCC_PLL_TEST_MUX_MUXR_MUX_SEL_BMSK                                            0x3f
#define HWIO_DPCC_REG_DPCC_PLL_TEST_MUX_MUXR_MUX_SEL_SHFT                                             0x0

#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_ADDR                                               (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000200)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_OFFS                                               (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000200)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_RMSK                                               0xffffdfff
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_ADDR)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IN)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_PWR_ON_STATUS_BMSK                                 0x80000000
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_PWR_ON_STATUS_SHFT                                       0x1f
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_RESERVE_30_15_BMSK                                 0x7fff8000
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_RESERVE_30_15_SHFT                                        0xf
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_COLLAPSE_OUT_BMSK                                      0x4000
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_COLLAPSE_OUT_SHFT                                         0xe
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_HALT_ACK_TIMEOUT_BMSK                                  0x1fe0
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_HALT_ACK_TIMEOUT_SHFT                                     0x5
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_GDS_HW_STATE_BMSK                                        0x1e
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_GDS_HW_STATE_SHFT                                         0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_SW_OVERRIDE_BMSK                                          0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_SW_OVERRIDE_SHFT                                          0x0

#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_ADDR                                        (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000204)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_OFFS                                        (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000204)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_RMSK                                        0xffffffff
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_ADDR)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_IN)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_RESERVE_31_21_BMSK                          0xffc00000
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_RESERVE_31_21_SHFT                                0x16
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_ACK_STATUS_BMSK            0x300000
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_ACK_STATUS_SHFT                0x14
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_RESERVE_19_17_BMSK                             0xc0000
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_RESERVE_19_17_SHFT                                0x12
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_UP_ACK_STATUS_BMSK               0x30000
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_UP_ACK_STATUS_SHFT                  0x10
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_RESERVE_15_13_BMSK                              0xc000
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_RESERVE_15_13_SHFT                                 0xe
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_ACK_STATUS_BMSK                  0x3000
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_ACK_STATUS_SHFT                     0xc
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_RESERVE_11_9_BMSK                                0xc00
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_RESERVE_11_9_SHFT                                  0xa
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_HALT1_PWR_UP_ACK_STATUS_BMSK                     0x300
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_HALT1_PWR_UP_ACK_STATUS_SHFT                       0x8
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_RESERVE_7_5_BMSK                                  0xe0
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_RESERVE_7_5_SHFT                                   0x5
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_ACK_STATUS_BMSK                    0x10
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_ACK_STATUS_SHFT                     0x4
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_RESERVE_3_1_BMSK                                   0xe
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_RESERVE_3_1_SHFT                                   0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_HALT2_PWR_UP_ACK_STATUS_BMSK                       0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_STATUS_HALT2_PWR_UP_ACK_STATUS_SHFT                       0x0

#define HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_ADDR                                      (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000208)
#define HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_OFFS                                      (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000208)
#define HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_RMSK                                            0x1f
#define HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_ADDR)
#define HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_IN)
#define HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_DVM_HALT_REQ_BMSK                               0x18
#define HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_DVM_HALT_REQ_SHFT                                0x3
#define HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_GEMNOC_HALT_REQ_BMSK                             0x4
#define HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_GEMNOC_HALT_REQ_SHFT                             0x2
#define HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_DCNOC_HALT_REQ_BMSK                              0x3
#define HWIO_DPCC_REG_DPCC_SHUB_HALT_REQ_GDS_HW_CTRL_DCNOC_HALT_REQ_SHFT                              0x0

#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_STATUS_ADDR                                    (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000020c)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_STATUS_OFFS                                    (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000020c)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_STATUS_RMSK                                           0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_STATUS_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_STATUS_ADDR)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_STATUS_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_STATUS_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_STATUS_STATUS_BMSK                                    0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_STATUS_STATUS_SHFT                                    0x0

#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_MASK_ADDR                                      (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000210)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_MASK_OFFS                                      (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000210)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_MASK_RMSK                                             0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_MASK_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_MASK_ADDR)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_MASK_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_MASK_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_MASK_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_MASK_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_MASK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_MASK_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_MASK_IN)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_MASK_MASK_BMSK                                        0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_MASK_MASK_SHFT                                        0x0

#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_CLEAR_ADDR                                     (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000214)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_CLEAR_OFFS                                     (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000214)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_CLEAR_RMSK                                            0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_CLEAR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_CLEAR_ADDR)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_CLEAR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_CLEAR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_CLEAR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_CLEAR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_CLEAR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_CLEAR_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_CLEAR_IN)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_CLEAR_CLEAR_BMSK                                      0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_IRQ_CLEAR_CLEAR_SHFT                                      0x0

#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_SPARE_ADDR                                         (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000218)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_SPARE_OFFS                                         (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000218)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_SPARE_RMSK                                               0xff
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_SPARE_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_SPARE_ADDR)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_SPARE_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_SPARE_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_SPARE_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_SPARE_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_SPARE_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_SPARE_IN)
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_SPARE_SPARE_BMSK                                         0xff
#define HWIO_DPCC_REG_DPCC_SHUB_GDS_HW_CTRL_SPARE_SPARE_SHFT                                          0x0

#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_CFG_ADDR                                       (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000230)
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_CFG_OFFS                                       (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000230)
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_CFG_RMSK                                             0x37
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_CFG_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_CFG_ADDR)
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_CFG_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_CFG_ADDR, m)
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_CFG_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_CFG_ADDR,v)
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_CFG_ADDR,m,v,HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_CFG_IN)
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_CFG_MC_ACTIVE_SEL_BMSK                               0x30
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_CFG_MC_ACTIVE_SEL_SHFT                                0x4
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_CFG_SHUB_ACTIVE_SEL_BMSK                              0x7
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_CFG_SHUB_ACTIVE_SEL_SHFT                              0x0

#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_STATUS_ADDR                                    (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000234)
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_STATUS_OFFS                                    (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000234)
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_STATUS_RMSK                                          0xf1
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_STATUS_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_STATUS_ADDR)
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_STATUS_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_STATUS_ADDR, m)
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_STATUS_MC_ACTIVE_BMSK                                0xf0
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_STATUS_MC_ACTIVE_SHFT                                 0x4
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_STATUS_SHUB_ACTIVE_BMSK                               0x1
#define HWIO_DPCC_REG_DPCC_FAL_TOL_DDRSS_ACTIVE_STATUS_SHUB_ACTIVE_SHFT                               0x0

#define HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_ADDR                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000250)
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_OFFS                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000250)
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_RMSK                                                        0xf
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_ADDR)
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_ADDR, m)
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_ADDR,v)
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_ADDR,m,v,HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_IN)
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_SW_FREEZEIO_1_SET_BMSK                                      0x8
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_SW_FREEZEIO_1_SET_SHFT                                      0x3
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_SW_FREEZEIO_1_RESET_BMSK                                    0x4
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_SW_FREEZEIO_1_RESET_SHFT                                    0x2
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_SW_FREEZEIO_0_SET_BMSK                                      0x2
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_SW_FREEZEIO_0_SET_SHFT                                      0x1
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_SW_FREEZEIO_0_RESET_BMSK                                    0x1
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_CTRL_SW_FREEZEIO_0_RESET_SHFT                                    0x0

#define HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_ADDR                                               (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000254)
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_OFFS                                               (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000254)
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_RMSK                                                     0x1f
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_ADDR)
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_ADDR, m)
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_MC_PRE_ARES_DONE_BMSK                                    0x10
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_MC_PRE_ARES_DONE_SHFT                                     0x4
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_PHY_FREEZE_IO_1_PREDFT_BMSK                               0x8
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_PHY_FREEZE_IO_1_PREDFT_SHFT                               0x3
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_PHY_FREEZE_IO_0_PREDFT_BMSK                               0x4
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_PHY_FREEZE_IO_0_PREDFT_SHFT                               0x2
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_PHY_FREEZE_IO_1_BMSK                                      0x2
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_PHY_FREEZE_IO_1_SHFT                                      0x1
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_PHY_FREEZE_IO_0_BMSK                                      0x1
#define HWIO_DPCC_REG_DPCC_FREEZE_IO_STATUS_PHY_FREEZE_IO_0_SHFT                                      0x0

#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_CTRL_ADDR                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000258)
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_CTRL_OFFS                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000258)
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_CTRL_RMSK                                                        0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_CTRL_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHUB_GDSC_CTRL_ADDR)
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_CTRL_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHUB_GDSC_CTRL_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_CTRL_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_SHUB_GDSC_CTRL_ADDR,v)
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_SHUB_GDSC_CTRL_ADDR,m,v,HWIO_DPCC_REG_DPCC_SHUB_GDSC_CTRL_IN)
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_CTRL_LLCC_CLAMP_MEM_BMSK                                         0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_CTRL_LLCC_CLAMP_MEM_SHFT                                         0x0

#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_ADDR                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000260)
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_OFFS                                                 (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000260)
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_RMSK                                                   0x3fffff
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_ADDR)
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC5_CLAMP_MEM_BMSK                                     0x200000
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC5_CLAMP_MEM_SHFT                                         0x15
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC4_CLAMP_MEM_BMSK                                     0x100000
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC4_CLAMP_MEM_SHFT                                         0x14
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC5_ENR_ACK_BMSK                                        0xf0000
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC5_ENR_ACK_SHFT                                           0x10
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC5_ENF_ACK_BMSK                                         0xf000
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC5_ENF_ACK_SHFT                                            0xc
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC4_ENR_ACK_BMSK                                          0xf00
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC4_ENR_ACK_SHFT                                            0x8
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC4_ENF_ACK_BMSK                                           0xf0
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC4_ENF_ACK_SHFT                                            0x4
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC5_RETAIN_FF_BMSK                                          0x8
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC5_RETAIN_FF_SHFT                                          0x3
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC5_CLAMP_IO_BMSK                                           0x4
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC5_CLAMP_IO_SHFT                                           0x2
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC4_RETAIN_FF_BMSK                                          0x2
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC4_RETAIN_FF_SHFT                                          0x1
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC4_CLAMP_IO_BMSK                                           0x1
#define HWIO_DPCC_REG_DPCC_MC_GDSC_STATUS_MC4_CLAMP_IO_SHFT                                           0x0

#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_ADDR                                               (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000264)
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_OFFS                                               (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000264)
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_RMSK                                                   0x3fff
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_ADDR)
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_ADDR, m)
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_GEMNOC_ENR_ACK_BMSK                                    0x2000
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_GEMNOC_ENR_ACK_SHFT                                       0xd
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_GEMNOC_ENF_ACK_BMSK                                    0x1000
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_GEMNOC_ENF_ACK_SHFT                                       0xc
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_LLCC_ENR_ACK_BMSK                                       0xf00
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_LLCC_ENR_ACK_SHFT                                         0x8
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_LLCC_ENF_ACK_BMSK                                        0xf0
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_LLCC_ENF_ACK_SHFT                                         0x4
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_GEMNOC_CLAMP_MEM_BMSK                                     0x8
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_GEMNOC_CLAMP_MEM_SHFT                                     0x3
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_SHUB_RETAIN_FF_BMSK                                       0x4
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_SHUB_RETAIN_FF_SHFT                                       0x2
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_SHUB_CLAMP_MEM_BMSK                                       0x2
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_SHUB_CLAMP_MEM_SHFT                                       0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_SHUB_CLAMP_IO_BMSK                                        0x1
#define HWIO_DPCC_REG_DPCC_SHUB_GDSC_STATUS_SHUB_CLAMP_IO_SHFT                                        0x0

#define HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000268)
#define HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000268)
#define HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_RMSK                                                   0xfffff
#define HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_ADDR)
#define HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_PHY_CLAMP_MEM_BMSK                                     0xf0000
#define HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_PHY_CLAMP_MEM_SHFT                                        0x10
#define HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_PHY_RETAIN_FF_BMSK                                      0xf000
#define HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_PHY_RETAIN_FF_SHFT                                         0xc
#define HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_PHY_CLAMP_CLKS_BMSK                                      0xf00
#define HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_PHY_CLAMP_CLKS_SHFT                                        0x8
#define HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_PHY_CLAMP_DFT_BMSK                                        0xf0
#define HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_PHY_CLAMP_DFT_SHFT                                         0x4
#define HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_PHY_CLAMP_IO_BMSK                                          0xf
#define HWIO_DPCC_REG_DPCC_PHY_GDSC_STATUS_PHY_CLAMP_IO_SHFT                                          0x0

#define HWIO_DPCC_REG_DPCC_MC_GDSC_SW_OVRD_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000026c)
#define HWIO_DPCC_REG_DPCC_MC_GDSC_SW_OVRD_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000026c)
#define HWIO_DPCC_REG_DPCC_MC_GDSC_SW_OVRD_RMSK                                                       0x3
#define HWIO_DPCC_REG_DPCC_MC_GDSC_SW_OVRD_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_MC_GDSC_SW_OVRD_ADDR)
#define HWIO_DPCC_REG_DPCC_MC_GDSC_SW_OVRD_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_MC_GDSC_SW_OVRD_ADDR, m)
#define HWIO_DPCC_REG_DPCC_MC_GDSC_SW_OVRD_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_MC_GDSC_SW_OVRD_ADDR,v)
#define HWIO_DPCC_REG_DPCC_MC_GDSC_SW_OVRD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_MC_GDSC_SW_OVRD_ADDR,m,v,HWIO_DPCC_REG_DPCC_MC_GDSC_SW_OVRD_IN)
#define HWIO_DPCC_REG_DPCC_MC_GDSC_SW_OVRD_MC5_GDSC_EN_ACK_BMSK                                       0x2
#define HWIO_DPCC_REG_DPCC_MC_GDSC_SW_OVRD_MC5_GDSC_EN_ACK_SHFT                                       0x1
#define HWIO_DPCC_REG_DPCC_MC_GDSC_SW_OVRD_MC4_GDSC_EN_ACK_BMSK                                       0x1
#define HWIO_DPCC_REG_DPCC_MC_GDSC_SW_OVRD_MC4_GDSC_EN_ACK_SHFT                                       0x0

#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_ADDR                                           (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000270)
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_OFFS                                           (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000270)
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_RMSK                                               0xffff
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_ADDR)
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_ADDR, m)
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_ADDR,v)
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_ADDR,m,v,HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_IN)
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_PHY_ATB_CLK_BMSK                                   0x8000
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_PHY_ATB_CLK_SHFT                                      0xf
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_TS_CLK_BMSK                                        0x4000
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_TS_CLK_SHFT                                           0xe
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_SNOC_CLK_BMSK                                      0x2000
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_SNOC_CLK_SHFT                                         0xd
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_SNOC_SF_CLK_BMSK                                   0x1000
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_SNOC_SF_CLK_SHFT                                      0xc
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_SNOC_GC_CLK_BMSK                                    0x800
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_SNOC_GC_CLK_SHFT                                      0xb
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_SYS_TCU_CLK_BMSK                                    0x400
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_SYS_TCU_CLK_SHFT                                      0xa
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_PCIE_SF_CLK_BMSK                                    0x200
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_PCIE_SF_CLK_SHFT                                      0x9
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_MNOC_SF_CLK_BMSK                                    0x100
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_MNOC_SF_CLK_SHFT                                      0x8
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_MNOC_HF_CLK_BMSK                                     0x80
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_MNOC_HF_CLK_SHFT                                      0x7
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_GPU_CLK_BMSK                                         0x40
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_GPU_CLK_SHFT                                          0x6
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_CMPNOC_CLK_BMSK                                      0x20
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_CMPNOC_CLK_SHFT                                       0x5
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_ATB_CLK_BMSK                                         0x10
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_ATB_CLK_SHFT                                          0x4
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_SHUB_CLK_BMSK                                         0x8
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_SHUB_CLK_SHFT                                         0x3
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_SHRM_CLK_BMSK                                         0x4
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_SHRM_CLK_SHFT                                         0x2
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_SLEEP_CLK_BMSK                                        0x2
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_SLEEP_CLK_SHFT                                        0x1
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_XO_CLK_BMSK                                           0x1
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_EN_XO_CLK_SHFT                                           0x0

#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_ADDR                                          (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000274)
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_OFFS                                          (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000274)
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_RMSK                                              0xffff
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_ADDR)
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_ADDR, m)
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_ADDR,v)
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_ADDR,m,v,HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_IN)
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_PHY_ATB_CLK_BMSK                                  0x8000
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_PHY_ATB_CLK_SHFT                                     0xf
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_TS_CLK_BMSK                                       0x4000
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_TS_CLK_SHFT                                          0xe
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_SNOC_CLK_BMSK                                     0x2000
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_SNOC_CLK_SHFT                                        0xd
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_SNOC_SF_CLK_BMSK                                  0x1000
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_SNOC_SF_CLK_SHFT                                     0xc
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_SNOC_GC_CLK_BMSK                                   0x800
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_SNOC_GC_CLK_SHFT                                     0xb
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_SYS_TCU_CLK_BMSK                                   0x400
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_SYS_TCU_CLK_SHFT                                     0xa
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_PCIE_SF_CLK_BMSK                                   0x200
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_PCIE_SF_CLK_SHFT                                     0x9
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_MNOC_SF_CLK_BMSK                                   0x100
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_MNOC_SF_CLK_SHFT                                     0x8
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_MNOC_HF_CLK_BMSK                                    0x80
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_MNOC_HF_CLK_SHFT                                     0x7
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_GPU_CLK_BMSK                                        0x40
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_GPU_CLK_SHFT                                         0x6
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_CMPNOC_CLK_BMSK                                     0x20
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_CMPNOC_CLK_SHFT                                      0x5
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_ATB_CLK_BMSK                                        0x10
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_ATB_CLK_SHFT                                         0x4
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_SHUB_CLK_BMSK                                        0x8
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_SHUB_CLK_SHFT                                        0x3
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_SHRM_CLK_BMSK                                        0x4
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_SHRM_CLK_SHFT                                        0x2
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_SLEEP_CLK_BMSK                                       0x2
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_SLEEP_CLK_SHFT                                       0x1
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_XO_CLK_BMSK                                          0x1
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_CSR_HW_DIS_XO_CLK_SHFT                                          0x0

#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_ADDR                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000278)
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_OFFS                                              (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000278)
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_RMSK                                                  0xffff
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_ADDR)
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_ADDR, m)
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_PHY_ATB_CLK_BMSK                                      0x8000
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_PHY_ATB_CLK_SHFT                                         0xf
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_TS_CLK_BMSK                                           0x4000
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_TS_CLK_SHFT                                              0xe
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_SNOC_CLK_BMSK                                         0x2000
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_SNOC_CLK_SHFT                                            0xd
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_SNOC_SF_CLK_BMSK                                      0x1000
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_SNOC_SF_CLK_SHFT                                         0xc
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_SNOC_GC_CLK_BMSK                                       0x800
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_SNOC_GC_CLK_SHFT                                         0xb
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_SYS_TCU_CLK_BMSK                                       0x400
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_SYS_TCU_CLK_SHFT                                         0xa
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_PCIE_SF_CLK_BMSK                                       0x200
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_PCIE_SF_CLK_SHFT                                         0x9
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_MNOC_SF_CLK_BMSK                                       0x100
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_MNOC_SF_CLK_SHFT                                         0x8
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_MNOC_HF_CLK_BMSK                                        0x80
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_MNOC_HF_CLK_SHFT                                         0x7
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_GPU_CLK_BMSK                                            0x40
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_GPU_CLK_SHFT                                             0x6
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_CMPNOC_CLK_BMSK                                         0x20
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_CMPNOC_CLK_SHFT                                          0x5
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_ATB_CLK_BMSK                                            0x10
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_ATB_CLK_SHFT                                             0x4
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_SHUB_CLK_BMSK                                            0x8
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_SHUB_CLK_SHFT                                            0x3
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_SHRM_CLK_BMSK                                            0x4
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_SHRM_CLK_SHFT                                            0x2
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_SLEEP_CLK_BMSK                                           0x2
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_SLEEP_CLK_SHFT                                           0x1
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_XO_CLK_BMSK                                              0x1
#define HWIO_DPCC_REG_DPCC_GCC_CLK_ON_STATUS_XO_CLK_SHFT                                              0x0

#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_ADDR                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000280)
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_OFFS                                                (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000280)
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_RMSK                                                0xffffffff
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_IN)
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_PWR_ON_BMSK                                         0x80000000
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_PWR_ON_SHFT                                               0x1f
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_GDSC_SPARE_CTRL_OUT_BMSK                            0x7f800000
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_GDSC_SPARE_CTRL_OUT_SHFT                                  0x17
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_GDSC_PWR_DWN_START_BMSK                               0x400000
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_GDSC_PWR_DWN_START_SHFT                                   0x16
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_GDSC_PWR_UP_START_BMSK                                0x200000
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_GDSC_PWR_UP_START_SHFT                                    0x15
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_GDSC_POWER_UP_COMPLETE_BMSK                           0x100000
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_GDSC_POWER_UP_COMPLETE_SHFT                               0x14
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                          0x80000
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                             0x13
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_GDSC_STATE_BMSK                                        0x7f800
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_GDSC_STATE_SHFT                                            0xb
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_MULTI_MODE_GDSC_CTRL_BMSK                                0x7f8
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_MULTI_MODE_GDSC_CTRL_SHFT                                  0x3
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_RETAIN_FF_ENABLE_BMSK                                      0x4
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_RETAIN_FF_ENABLE_SHFT                                      0x2
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL                              0x0
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL                               0x1
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_HW_CONTROL_BMSK                                            0x2
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_HW_CONTROL_SHFT                                            0x1
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_HW_CONTROL_SW_CONTROL_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_HW_CONTROL_HW_CONTROL_FVAL                                 0x1
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_SW_COLLAPSE_BMSK                                           0x1
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_SW_COLLAPSE_SHFT                                           0x0
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_SW_COLLAPSE_DISABLE_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_PHY_CFG_MCGDSCR_SW_COLLAPSE_ENABLE_FVAL                                    0x1

#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_ADDR                                               (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000284)
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_OFFS                                               (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000284)
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_RMSK                                               0xffffffff
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_IN)
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_GDSC_TIMEOUT_BMSK                                  0xffff0000
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_GDSC_TIMEOUT_SHFT                                        0x10
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_GDSC_SPARE_CTRL_IN_BMSK                                0xf000
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_GDSC_SPARE_CTRL_IN_SHFT                                   0xc
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                          0xf00
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                            0x8
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_GDSC_HANDSHAKE_DIS_BMSK                                  0x80
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_GDSC_HANDSHAKE_DIS_SHFT                                   0x7
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                              0x40
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                               0x6
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                     0x30
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                      0x4
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                         0x8
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                         0x3
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                       0x4
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                       0x2
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                           0x2
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                           0x1
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                        0x1
#define HWIO_DPCC_REG_DPCC_PHY_CFG2_MCGDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                        0x0

#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_ADDR                                               (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000288)
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_OFFS                                               (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000288)
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_RMSK                                               0xffffffff
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_IN)
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_CLK_DIS_WAIT_BMSK                                  0xf0000000
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_CLK_DIS_WAIT_SHFT                                        0x1c
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_EN_REST_WAIT_BMSK                                   0xf000000
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_EN_REST_WAIT_SHFT                                        0x18
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_EN_FEW_WAIT_BMSK                                     0xf00000
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_EN_FEW_WAIT_SHFT                                         0x14
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_DLY_ENF_STAGGER_BMSK                                  0xf0000
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_DLY_ENF_STAGGER_SHFT                                     0x10
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_DLY_MEM_PWR_UP_BMSK                                    0xf000
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_DLY_MEM_PWR_UP_SHFT                                       0xc
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                             0xf00
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                               0x8
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                                0xf0
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                                 0x4
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                                  0xf
#define HWIO_DPCC_REG_DPCC_PHY_CFG3_MCGDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                                  0x0

#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_ADDR                                           (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x0000028c)
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_OFFS                                           (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x0000028c)
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_RMSK                                               0xffff
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_IN)
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                       0x8000
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                          0xf
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_MEM_PWR_ACK_STATUS_MEMORY_POWER_DOWN_COMPLETED_FVAL        0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_MEM_PWR_ACK_STATUS_MEMORY_POWER_UP_COMPLETED_FVAL        0x1
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_ENR_ACK_STATUS_BMSK                           0x4000
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_ENR_ACK_STATUS_SHFT                              0xe
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_ENR_ACK_STATUS_ENR_SWITCH_ARE_OFF_FVAL           0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_ENR_ACK_STATUS_ENR_SWITCH_ARE_ON_FVAL            0x1
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_ENF_ACK_STATUS_BMSK                           0x2000
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_ENF_ACK_STATUS_SHFT                              0xd
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_ENF_ACK_STATUS_ENF_SWITCH_ARE_OFF_FVAL           0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_ENF_ACK_STATUS_ENF_SWITCH_ARE_ON_FVAL            0x1
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_CLAMP_MEM_SW_BMSK                             0x1000
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_CLAMP_MEM_SW_SHFT                                0xc
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_CLAMP_MEM_SW_DISABLE_FVAL                        0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_CLAMP_MEM_SW_ENABLE_FVAL                         0x1
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                      0x800
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                        0xb
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                      0x400
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                        0xa
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                          0x200
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                            0x9
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_RESTORE_BMSK                                        0x100
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_RESTORE_SHFT                                          0x8
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_RESTORE_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_RESTORE_ENABLE_FVAL                                   0x1
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_SAVE_BMSK                                            0x80
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_SAVE_SHFT                                             0x7
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_SAVE_DISABLE_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_SAVE_ENABLE_FVAL                                      0x1
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_RETAIN_BMSK                                          0x40
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_RETAIN_SHFT                                           0x6
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_RETAIN_DISABLE_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_RETAIN_ENABLE_FVAL                                    0x1
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_EN_REST_BMSK                                         0x20
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_EN_REST_SHFT                                          0x5
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_EN_REST_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_EN_REST_ENABLE_FVAL                                   0x1
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_EN_FEW_BMSK                                          0x10
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_EN_FEW_SHFT                                           0x4
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_EN_FEW_DISABLE_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_EN_FEW_ENABLE_FVAL                                    0x1
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_CLAMP_IO_BMSK                                         0x8
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_CLAMP_IO_SHFT                                         0x3
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_CLAMP_IO_DISABLE_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_CLAMP_IO_ENABLE_FVAL                                  0x1
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_CLK_DISABLE_BMSK                                      0x4
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_CLK_DISABLE_SHFT                                      0x2
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL                      0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_CLK_DISABLE_CLK_DISABLE_FVAL                          0x1
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_PD_ARES_BMSK                                          0x2
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_PD_ARES_SHFT                                          0x1
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_PD_ARES_NO_RESET_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_PD_ARES_RESET_FVAL                                    0x1
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_SW_OVERRIDE_BMSK                                      0x1
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_SW_OVERRIDE_SHFT                                      0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_SW_OVERRIDE_DISABLE_FVAL                              0x0
#define HWIO_DPCC_REG_DPCC_PHY0_SW_OVRD_MCGDSCR_SW_OVERRIDE_ENABLE_FVAL                               0x1

#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_ADDR                                           (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000290)
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_OFFS                                           (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000290)
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_RMSK                                               0xffff
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_IN)
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                       0x8000
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                          0xf
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_MEM_PWR_ACK_STATUS_MEMORY_POWER_DOWN_COMPLETED_FVAL        0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_MEM_PWR_ACK_STATUS_MEMORY_POWER_UP_COMPLETED_FVAL        0x1
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_ENR_ACK_STATUS_BMSK                           0x4000
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_ENR_ACK_STATUS_SHFT                              0xe
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_ENR_ACK_STATUS_ENR_SWITCH_ARE_OFF_FVAL           0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_ENR_ACK_STATUS_ENR_SWITCH_ARE_ON_FVAL            0x1
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_ENF_ACK_STATUS_BMSK                           0x2000
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_ENF_ACK_STATUS_SHFT                              0xd
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_ENF_ACK_STATUS_ENF_SWITCH_ARE_OFF_FVAL           0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_ENF_ACK_STATUS_ENF_SWITCH_ARE_ON_FVAL            0x1
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_CLAMP_MEM_SW_BMSK                             0x1000
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_CLAMP_MEM_SW_SHFT                                0xc
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_CLAMP_MEM_SW_DISABLE_FVAL                        0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_CLAMP_MEM_SW_ENABLE_FVAL                         0x1
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                      0x800
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                        0xb
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                      0x400
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                        0xa
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                          0x200
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                            0x9
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_RESTORE_BMSK                                        0x100
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_RESTORE_SHFT                                          0x8
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_RESTORE_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_RESTORE_ENABLE_FVAL                                   0x1
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_SAVE_BMSK                                            0x80
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_SAVE_SHFT                                             0x7
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_SAVE_DISABLE_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_SAVE_ENABLE_FVAL                                      0x1
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_RETAIN_BMSK                                          0x40
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_RETAIN_SHFT                                           0x6
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_RETAIN_DISABLE_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_RETAIN_ENABLE_FVAL                                    0x1
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_EN_REST_BMSK                                         0x20
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_EN_REST_SHFT                                          0x5
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_EN_REST_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_EN_REST_ENABLE_FVAL                                   0x1
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_EN_FEW_BMSK                                          0x10
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_EN_FEW_SHFT                                           0x4
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_EN_FEW_DISABLE_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_EN_FEW_ENABLE_FVAL                                    0x1
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_CLAMP_IO_BMSK                                         0x8
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_CLAMP_IO_SHFT                                         0x3
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_CLAMP_IO_DISABLE_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_CLAMP_IO_ENABLE_FVAL                                  0x1
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_CLK_DISABLE_BMSK                                      0x4
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_CLK_DISABLE_SHFT                                      0x2
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL                      0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_CLK_DISABLE_CLK_DISABLE_FVAL                          0x1
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_PD_ARES_BMSK                                          0x2
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_PD_ARES_SHFT                                          0x1
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_PD_ARES_NO_RESET_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_PD_ARES_RESET_FVAL                                    0x1
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_SW_OVERRIDE_BMSK                                      0x1
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_SW_OVERRIDE_SHFT                                      0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_SW_OVERRIDE_DISABLE_FVAL                              0x0
#define HWIO_DPCC_REG_DPCC_PHY1_SW_OVRD_MCGDSCR_SW_OVERRIDE_ENABLE_FVAL                               0x1

#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_ADDR                                           (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000294)
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_OFFS                                           (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000294)
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_RMSK                                               0xffff
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_IN)
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                       0x8000
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                          0xf
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_MEM_PWR_ACK_STATUS_MEMORY_POWER_DOWN_COMPLETED_FVAL        0x0
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_MEM_PWR_ACK_STATUS_MEMORY_POWER_UP_COMPLETED_FVAL        0x1
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_ENR_ACK_STATUS_BMSK                           0x4000
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_ENR_ACK_STATUS_SHFT                              0xe
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_ENR_ACK_STATUS_ENR_SWITCH_ARE_OFF_FVAL           0x0
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_ENR_ACK_STATUS_ENR_SWITCH_ARE_ON_FVAL            0x1
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_ENF_ACK_STATUS_BMSK                           0x2000
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_ENF_ACK_STATUS_SHFT                              0xd
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_ENF_ACK_STATUS_ENF_SWITCH_ARE_OFF_FVAL           0x0
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_ENF_ACK_STATUS_ENF_SWITCH_ARE_ON_FVAL            0x1
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_CLAMP_MEM_SW_BMSK                             0x1000
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_CLAMP_MEM_SW_SHFT                                0xc
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_CLAMP_MEM_SW_DISABLE_FVAL                        0x0
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_CLAMP_MEM_SW_ENABLE_FVAL                         0x1
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                      0x800
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                        0xb
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                      0x400
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                        0xa
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                          0x200
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                            0x9
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_RESTORE_BMSK                                        0x100
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_RESTORE_SHFT                                          0x8
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_RESTORE_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_RESTORE_ENABLE_FVAL                                   0x1
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_SAVE_BMSK                                            0x80
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_SAVE_SHFT                                             0x7
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_SAVE_DISABLE_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_SAVE_ENABLE_FVAL                                      0x1
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_RETAIN_BMSK                                          0x40
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_RETAIN_SHFT                                           0x6
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_RETAIN_DISABLE_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_RETAIN_ENABLE_FVAL                                    0x1
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_EN_REST_BMSK                                         0x20
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_EN_REST_SHFT                                          0x5
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_EN_REST_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_EN_REST_ENABLE_FVAL                                   0x1
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_EN_FEW_BMSK                                          0x10
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_EN_FEW_SHFT                                           0x4
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_EN_FEW_DISABLE_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_EN_FEW_ENABLE_FVAL                                    0x1
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_CLAMP_IO_BMSK                                         0x8
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_CLAMP_IO_SHFT                                         0x3
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_CLAMP_IO_DISABLE_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_CLAMP_IO_ENABLE_FVAL                                  0x1
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_CLK_DISABLE_BMSK                                      0x4
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_CLK_DISABLE_SHFT                                      0x2
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL                      0x0
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_CLK_DISABLE_CLK_DISABLE_FVAL                          0x1
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_PD_ARES_BMSK                                          0x2
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_PD_ARES_SHFT                                          0x1
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_PD_ARES_NO_RESET_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_PD_ARES_RESET_FVAL                                    0x1
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_SW_OVERRIDE_BMSK                                      0x1
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_SW_OVERRIDE_SHFT                                      0x0
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_SW_OVERRIDE_DISABLE_FVAL                              0x0
#define HWIO_DPCC_REG_DPCC_PHY2_SW_OVRD_MCGDSCR_SW_OVERRIDE_ENABLE_FVAL                               0x1

#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_ADDR                                           (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00000298)
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_OFFS                                           (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00000298)
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_RMSK                                               0xffff
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_IN)
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                       0x8000
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                          0xf
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_MEM_PWR_ACK_STATUS_MEMORY_POWER_DOWN_COMPLETED_FVAL        0x0
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_MEM_PWR_ACK_STATUS_MEMORY_POWER_UP_COMPLETED_FVAL        0x1
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_ENR_ACK_STATUS_BMSK                           0x4000
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_ENR_ACK_STATUS_SHFT                              0xe
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_ENR_ACK_STATUS_ENR_SWITCH_ARE_OFF_FVAL           0x0
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_ENR_ACK_STATUS_ENR_SWITCH_ARE_ON_FVAL            0x1
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_ENF_ACK_STATUS_BMSK                           0x2000
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_ENF_ACK_STATUS_SHFT                              0xd
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_ENF_ACK_STATUS_ENF_SWITCH_ARE_OFF_FVAL           0x0
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_ENF_ACK_STATUS_ENF_SWITCH_ARE_ON_FVAL            0x1
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_CLAMP_MEM_SW_BMSK                             0x1000
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_CLAMP_MEM_SW_SHFT                                0xc
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_CLAMP_MEM_SW_DISABLE_FVAL                        0x0
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_CLAMP_MEM_SW_ENABLE_FVAL                         0x1
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                      0x800
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                        0xb
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                      0x400
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                        0xa
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                          0x200
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                            0x9
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_RESTORE_BMSK                                        0x100
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_RESTORE_SHFT                                          0x8
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_RESTORE_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_RESTORE_ENABLE_FVAL                                   0x1
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_SAVE_BMSK                                            0x80
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_SAVE_SHFT                                             0x7
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_SAVE_DISABLE_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_SAVE_ENABLE_FVAL                                      0x1
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_RETAIN_BMSK                                          0x40
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_RETAIN_SHFT                                           0x6
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_RETAIN_DISABLE_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_RETAIN_ENABLE_FVAL                                    0x1
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_EN_REST_BMSK                                         0x20
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_EN_REST_SHFT                                          0x5
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_EN_REST_DISABLE_FVAL                                  0x0
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_EN_REST_ENABLE_FVAL                                   0x1
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_EN_FEW_BMSK                                          0x10
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_EN_FEW_SHFT                                           0x4
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_EN_FEW_DISABLE_FVAL                                   0x0
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_EN_FEW_ENABLE_FVAL                                    0x1
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_CLAMP_IO_BMSK                                         0x8
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_CLAMP_IO_SHFT                                         0x3
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_CLAMP_IO_DISABLE_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_CLAMP_IO_ENABLE_FVAL                                  0x1
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_CLK_DISABLE_BMSK                                      0x4
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_CLK_DISABLE_SHFT                                      0x2
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_CLK_DISABLE_CLK_NOT_DISABLE_FVAL                      0x0
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_CLK_DISABLE_CLK_DISABLE_FVAL                          0x1
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_PD_ARES_BMSK                                          0x2
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_PD_ARES_SHFT                                          0x1
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_PD_ARES_NO_RESET_FVAL                                 0x0
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_PD_ARES_RESET_FVAL                                    0x1
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_SW_OVERRIDE_BMSK                                      0x1
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_SW_OVERRIDE_SHFT                                      0x0
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_SW_OVERRIDE_DISABLE_FVAL                              0x0
#define HWIO_DPCC_REG_DPCC_PHY3_SW_OVRD_MCGDSCR_SW_OVERRIDE_ENABLE_FVAL                               0x1

#define HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_ADDR                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE      + 0x00002010)
#define HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_OFFS                                                  (DPCC_REG_DPCC_DPCC_DPCC_REG_REG_BASE_OFFS + 0x00002010)
#define HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_RMSK                                                         0x3
#define HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_IN          \
        in_dword(HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_ADDR)
#define HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_ADDR, m)
#define HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_OUT(v)      \
        out_dword(HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_ADDR,v)
#define HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_ADDR,m,v,HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_IN)
#define HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK                                        0x2
#define HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT                                        0x1
#define HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_RETAIN_FF_ENABLE_DISABLE_FVAL                                0x0
#define HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_RETAIN_FF_ENABLE_ENABLE_FVAL                                 0x1
#define HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_SW_OVERRIDE_BMSK                                             0x1
#define HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_SW_OVERRIDE_SHFT                                             0x0
#define HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_SW_OVERRIDE_DISABLE_FVAL                                     0x0
#define HWIO_DPCC_REG_DPCC_TZ_PHY_SGDSCR_SW_OVERRIDE_ENABLE_FVAL                                      0x1

/*----------------------------------------------------------------------------
 * MODULE: MCCC_MCCC_MSTR
 *--------------------------------------------------------------------------*/

#define MCCC_MCCC_MSTR_REG_BASE                                             (DDR_SS_BASE      + 0x000ba000)
#define MCCC_MCCC_MSTR_REG_BASE_SIZE                                        0x800
#define MCCC_MCCC_MSTR_REG_BASE_USED                                        0x2a0
#define MCCC_MCCC_MSTR_REG_BASE_OFFS                                        0x000ba000

#define HWIO_MCCC_FREQ_SWITCH_UPDATE_ADDR                                   (MCCC_MCCC_MSTR_REG_BASE      + 0x00000000)
#define HWIO_MCCC_FREQ_SWITCH_UPDATE_OFFS                                   (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000000)
#define HWIO_MCCC_FREQ_SWITCH_UPDATE_RMSK                                          0x1
#define HWIO_MCCC_FREQ_SWITCH_UPDATE_IN          \
        in_dword(HWIO_MCCC_FREQ_SWITCH_UPDATE_ADDR)
#define HWIO_MCCC_FREQ_SWITCH_UPDATE_INM(m)      \
        in_dword_masked(HWIO_MCCC_FREQ_SWITCH_UPDATE_ADDR, m)
#define HWIO_MCCC_FREQ_SWITCH_UPDATE_OUT(v)      \
        out_dword(HWIO_MCCC_FREQ_SWITCH_UPDATE_ADDR,v)
#define HWIO_MCCC_FREQ_SWITCH_UPDATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_FREQ_SWITCH_UPDATE_ADDR,m,v,HWIO_MCCC_FREQ_SWITCH_UPDATE_IN)
#define HWIO_MCCC_FREQ_SWITCH_UPDATE_ACTIVE_BMSK                                   0x1
#define HWIO_MCCC_FREQ_SWITCH_UPDATE_ACTIVE_SHFT                                   0x0

#define HWIO_MCCC_FREQ_SWITCH_FSM_CFG_ADDR                                  (MCCC_MCCC_MSTR_REG_BASE      + 0x00000004)
#define HWIO_MCCC_FREQ_SWITCH_FSM_CFG_OFFS                                  (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000004)
#define HWIO_MCCC_FREQ_SWITCH_FSM_CFG_RMSK                                    0x1f1f1f
#define HWIO_MCCC_FREQ_SWITCH_FSM_CFG_IN          \
        in_dword(HWIO_MCCC_FREQ_SWITCH_FSM_CFG_ADDR)
#define HWIO_MCCC_FREQ_SWITCH_FSM_CFG_INM(m)      \
        in_dword_masked(HWIO_MCCC_FREQ_SWITCH_FSM_CFG_ADDR, m)
#define HWIO_MCCC_FREQ_SWITCH_FSM_CFG_OUT(v)      \
        out_dword(HWIO_MCCC_FREQ_SWITCH_FSM_CFG_ADDR,v)
#define HWIO_MCCC_FREQ_SWITCH_FSM_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_FREQ_SWITCH_FSM_CFG_ADDR,m,v,HWIO_MCCC_FREQ_SWITCH_FSM_CFG_IN)
#define HWIO_MCCC_FREQ_SWITCH_FSM_CFG_FINAL_STATE_BMSK                        0x1f0000
#define HWIO_MCCC_FREQ_SWITCH_FSM_CFG_FINAL_STATE_SHFT                            0x10
#define HWIO_MCCC_FREQ_SWITCH_FSM_CFG_WORK_END_STATE_BMSK                       0x1f00
#define HWIO_MCCC_FREQ_SWITCH_FSM_CFG_WORK_END_STATE_SHFT                          0x8
#define HWIO_MCCC_FREQ_SWITCH_FSM_CFG_PREWORK_END_STATE_BMSK                      0x1f
#define HWIO_MCCC_FREQ_SWITCH_FSM_CFG_PREWORK_END_STATE_SHFT                       0x0

#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_ADDR                              (MCCC_MCCC_MSTR_REG_BASE      + 0x00000020)
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_OFFS                              (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000020)
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_RMSK                              0xffffffff
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_IN          \
        in_dword(HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_ADDR)
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_INM(m)      \
        in_dword_masked(HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_ADDR, m)
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_OUT(v)      \
        out_dword(HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_ADDR,v)
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_ADDR,m,v,HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_IN)
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE31_EXIT_BMSK                 0x80000000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE31_EXIT_SHFT                       0x1f
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE31_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE31_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE30_EXIT_BMSK                 0x40000000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE30_EXIT_SHFT                       0x1e
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE30_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE30_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE29_EXIT_BMSK                 0x20000000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE29_EXIT_SHFT                       0x1d
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE29_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE29_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE28_EXIT_BMSK                 0x10000000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE28_EXIT_SHFT                       0x1c
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE28_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE28_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE27_EXIT_BMSK                  0x8000000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE27_EXIT_SHFT                       0x1b
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE27_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE27_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE26_EXIT_BMSK                  0x4000000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE26_EXIT_SHFT                       0x1a
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE26_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE26_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE25_EXIT_BMSK                  0x2000000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE25_EXIT_SHFT                       0x19
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE25_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE25_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE24_EXIT_BMSK                  0x1000000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE24_EXIT_SHFT                       0x18
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE24_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE24_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE23_EXIT_BMSK                   0x800000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE23_EXIT_SHFT                       0x17
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE23_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE23_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE22_EXIT_BMSK                   0x400000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE22_EXIT_SHFT                       0x16
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE22_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE22_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE21_EXIT_BMSK                   0x200000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE21_EXIT_SHFT                       0x15
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE21_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE21_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE20_EXIT_BMSK                   0x100000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE20_EXIT_SHFT                       0x14
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE20_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE20_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE19_EXIT_BMSK                    0x80000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE19_EXIT_SHFT                       0x13
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE19_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE19_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE18_EXIT_BMSK                    0x40000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE18_EXIT_SHFT                       0x12
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE18_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE18_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE17_EXIT_BMSK                    0x20000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE17_EXIT_SHFT                       0x11
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE17_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE17_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE16_EXIT_BMSK                    0x10000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE16_EXIT_SHFT                       0x10
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE16_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE16_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE15_EXIT_BMSK                     0x8000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE15_EXIT_SHFT                        0xf
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE15_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE15_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE14_EXIT_BMSK                     0x4000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE14_EXIT_SHFT                        0xe
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE14_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE14_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE13_EXIT_BMSK                     0x2000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE13_EXIT_SHFT                        0xd
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE13_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE13_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE12_EXIT_BMSK                     0x1000
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE12_EXIT_SHFT                        0xc
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE12_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE12_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE11_EXIT_BMSK                      0x800
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE11_EXIT_SHFT                        0xb
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE11_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE11_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE10_EXIT_BMSK                      0x400
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE10_EXIT_SHFT                        0xa
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE10_EXIT_PER_CHANNEL_FVAL            0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE10_EXIT_ALL_CHANNEL_FVAL            0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE9_EXIT_BMSK                       0x200
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE9_EXIT_SHFT                         0x9
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE9_EXIT_PER_CHANNEL_FVAL             0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE9_EXIT_ALL_CHANNEL_FVAL             0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE8_EXIT_BMSK                       0x100
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE8_EXIT_SHFT                         0x8
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE8_EXIT_PER_CHANNEL_FVAL             0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE8_EXIT_ALL_CHANNEL_FVAL             0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE7_EXIT_BMSK                        0x80
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE7_EXIT_SHFT                         0x7
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE7_EXIT_PER_CHANNEL_FVAL             0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE7_EXIT_ALL_CHANNEL_FVAL             0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE6_EXIT_BMSK                        0x40
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE6_EXIT_SHFT                         0x6
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE6_EXIT_PER_CHANNEL_FVAL             0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE6_EXIT_ALL_CHANNEL_FVAL             0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE5_EXIT_BMSK                        0x20
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE5_EXIT_SHFT                         0x5
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE5_EXIT_PER_CHANNEL_FVAL             0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE5_EXIT_ALL_CHANNEL_FVAL             0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE4_EXIT_BMSK                        0x10
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE4_EXIT_SHFT                         0x4
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE4_EXIT_PER_CHANNEL_FVAL             0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE4_EXIT_ALL_CHANNEL_FVAL             0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE3_EXIT_BMSK                         0x8
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE3_EXIT_SHFT                         0x3
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE3_EXIT_PER_CHANNEL_FVAL             0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE3_EXIT_ALL_CHANNEL_FVAL             0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE2_EXIT_BMSK                         0x4
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE2_EXIT_SHFT                         0x2
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE2_EXIT_PER_CHANNEL_FVAL             0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE2_EXIT_ALL_CHANNEL_FVAL             0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE1_EXIT_BMSK                         0x2
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE1_EXIT_SHFT                         0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE1_EXIT_PER_CHANNEL_FVAL             0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE1_EXIT_ALL_CHANNEL_FVAL             0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE0_EXIT_BMSK                         0x1
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE0_EXIT_SHFT                         0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE0_EXIT_PER_CHANNEL_FVAL             0x0
#define HWIO_MCCC_FSC_STATE_EXIT_COND_CFG_STATE0_EXIT_ALL_CHANNEL_FVAL             0x1

#define HWIO_MCCC_CLK_PERIOD_ADDR                                           (MCCC_MCCC_MSTR_REG_BASE      + 0x00000050)
#define HWIO_MCCC_CLK_PERIOD_OFFS                                           (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000050)
#define HWIO_MCCC_CLK_PERIOD_RMSK                                              0x1ffff
#define HWIO_MCCC_CLK_PERIOD_IN          \
        in_dword(HWIO_MCCC_CLK_PERIOD_ADDR)
#define HWIO_MCCC_CLK_PERIOD_INM(m)      \
        in_dword_masked(HWIO_MCCC_CLK_PERIOD_ADDR, m)
#define HWIO_MCCC_CLK_PERIOD_OUT(v)      \
        out_dword(HWIO_MCCC_CLK_PERIOD_ADDR,v)
#define HWIO_MCCC_CLK_PERIOD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_CLK_PERIOD_ADDR,m,v,HWIO_MCCC_CLK_PERIOD_IN)
#define HWIO_MCCC_CLK_PERIOD_PERIOD_BMSK                                       0x1ffff
#define HWIO_MCCC_CLK_PERIOD_PERIOD_SHFT                                           0x0

#define HWIO_MCCC_BAND0_UPPER_FREQ_THRESHOLD_ADDR                           (MCCC_MCCC_MSTR_REG_BASE      + 0x00000054)
#define HWIO_MCCC_BAND0_UPPER_FREQ_THRESHOLD_OFFS                           (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000054)
#define HWIO_MCCC_BAND0_UPPER_FREQ_THRESHOLD_RMSK                              0x1ffff
#define HWIO_MCCC_BAND0_UPPER_FREQ_THRESHOLD_IN          \
        in_dword(HWIO_MCCC_BAND0_UPPER_FREQ_THRESHOLD_ADDR)
#define HWIO_MCCC_BAND0_UPPER_FREQ_THRESHOLD_INM(m)      \
        in_dword_masked(HWIO_MCCC_BAND0_UPPER_FREQ_THRESHOLD_ADDR, m)
#define HWIO_MCCC_BAND0_UPPER_FREQ_THRESHOLD_OUT(v)      \
        out_dword(HWIO_MCCC_BAND0_UPPER_FREQ_THRESHOLD_ADDR,v)
#define HWIO_MCCC_BAND0_UPPER_FREQ_THRESHOLD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_BAND0_UPPER_FREQ_THRESHOLD_ADDR,m,v,HWIO_MCCC_BAND0_UPPER_FREQ_THRESHOLD_IN)
#define HWIO_MCCC_BAND0_UPPER_FREQ_THRESHOLD_THRESHOLD_PERIOD_BMSK             0x1ffff
#define HWIO_MCCC_BAND0_UPPER_FREQ_THRESHOLD_THRESHOLD_PERIOD_SHFT                 0x0

#define HWIO_MCCC_BAND1_UPPER_FREQ_THRESHOLD_ADDR                           (MCCC_MCCC_MSTR_REG_BASE      + 0x00000058)
#define HWIO_MCCC_BAND1_UPPER_FREQ_THRESHOLD_OFFS                           (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000058)
#define HWIO_MCCC_BAND1_UPPER_FREQ_THRESHOLD_RMSK                              0x1ffff
#define HWIO_MCCC_BAND1_UPPER_FREQ_THRESHOLD_IN          \
        in_dword(HWIO_MCCC_BAND1_UPPER_FREQ_THRESHOLD_ADDR)
#define HWIO_MCCC_BAND1_UPPER_FREQ_THRESHOLD_INM(m)      \
        in_dword_masked(HWIO_MCCC_BAND1_UPPER_FREQ_THRESHOLD_ADDR, m)
#define HWIO_MCCC_BAND1_UPPER_FREQ_THRESHOLD_OUT(v)      \
        out_dword(HWIO_MCCC_BAND1_UPPER_FREQ_THRESHOLD_ADDR,v)
#define HWIO_MCCC_BAND1_UPPER_FREQ_THRESHOLD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_BAND1_UPPER_FREQ_THRESHOLD_ADDR,m,v,HWIO_MCCC_BAND1_UPPER_FREQ_THRESHOLD_IN)
#define HWIO_MCCC_BAND1_UPPER_FREQ_THRESHOLD_THRESHOLD_PERIOD_BMSK             0x1ffff
#define HWIO_MCCC_BAND1_UPPER_FREQ_THRESHOLD_THRESHOLD_PERIOD_SHFT                 0x0

#define HWIO_MCCC_BAND2_UPPER_FREQ_THRESHOLD_ADDR                           (MCCC_MCCC_MSTR_REG_BASE      + 0x0000005c)
#define HWIO_MCCC_BAND2_UPPER_FREQ_THRESHOLD_OFFS                           (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x0000005c)
#define HWIO_MCCC_BAND2_UPPER_FREQ_THRESHOLD_RMSK                              0x1ffff
#define HWIO_MCCC_BAND2_UPPER_FREQ_THRESHOLD_IN          \
        in_dword(HWIO_MCCC_BAND2_UPPER_FREQ_THRESHOLD_ADDR)
#define HWIO_MCCC_BAND2_UPPER_FREQ_THRESHOLD_INM(m)      \
        in_dword_masked(HWIO_MCCC_BAND2_UPPER_FREQ_THRESHOLD_ADDR, m)
#define HWIO_MCCC_BAND2_UPPER_FREQ_THRESHOLD_OUT(v)      \
        out_dword(HWIO_MCCC_BAND2_UPPER_FREQ_THRESHOLD_ADDR,v)
#define HWIO_MCCC_BAND2_UPPER_FREQ_THRESHOLD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_BAND2_UPPER_FREQ_THRESHOLD_ADDR,m,v,HWIO_MCCC_BAND2_UPPER_FREQ_THRESHOLD_IN)
#define HWIO_MCCC_BAND2_UPPER_FREQ_THRESHOLD_THRESHOLD_PERIOD_BMSK             0x1ffff
#define HWIO_MCCC_BAND2_UPPER_FREQ_THRESHOLD_THRESHOLD_PERIOD_SHFT                 0x0

#define HWIO_MCCC_BAND3_UPPER_FREQ_THRESHOLD_ADDR                           (MCCC_MCCC_MSTR_REG_BASE      + 0x00000060)
#define HWIO_MCCC_BAND3_UPPER_FREQ_THRESHOLD_OFFS                           (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000060)
#define HWIO_MCCC_BAND3_UPPER_FREQ_THRESHOLD_RMSK                              0x1ffff
#define HWIO_MCCC_BAND3_UPPER_FREQ_THRESHOLD_IN          \
        in_dword(HWIO_MCCC_BAND3_UPPER_FREQ_THRESHOLD_ADDR)
#define HWIO_MCCC_BAND3_UPPER_FREQ_THRESHOLD_INM(m)      \
        in_dword_masked(HWIO_MCCC_BAND3_UPPER_FREQ_THRESHOLD_ADDR, m)
#define HWIO_MCCC_BAND3_UPPER_FREQ_THRESHOLD_OUT(v)      \
        out_dword(HWIO_MCCC_BAND3_UPPER_FREQ_THRESHOLD_ADDR,v)
#define HWIO_MCCC_BAND3_UPPER_FREQ_THRESHOLD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_BAND3_UPPER_FREQ_THRESHOLD_ADDR,m,v,HWIO_MCCC_BAND3_UPPER_FREQ_THRESHOLD_IN)
#define HWIO_MCCC_BAND3_UPPER_FREQ_THRESHOLD_THRESHOLD_PERIOD_BMSK             0x1ffff
#define HWIO_MCCC_BAND3_UPPER_FREQ_THRESHOLD_THRESHOLD_PERIOD_SHFT                 0x0

#define HWIO_MCCC_BAND4_UPPER_FREQ_THRESHOLD_ADDR                           (MCCC_MCCC_MSTR_REG_BASE      + 0x00000064)
#define HWIO_MCCC_BAND4_UPPER_FREQ_THRESHOLD_OFFS                           (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000064)
#define HWIO_MCCC_BAND4_UPPER_FREQ_THRESHOLD_RMSK                              0x1ffff
#define HWIO_MCCC_BAND4_UPPER_FREQ_THRESHOLD_IN          \
        in_dword(HWIO_MCCC_BAND4_UPPER_FREQ_THRESHOLD_ADDR)
#define HWIO_MCCC_BAND4_UPPER_FREQ_THRESHOLD_INM(m)      \
        in_dword_masked(HWIO_MCCC_BAND4_UPPER_FREQ_THRESHOLD_ADDR, m)
#define HWIO_MCCC_BAND4_UPPER_FREQ_THRESHOLD_OUT(v)      \
        out_dword(HWIO_MCCC_BAND4_UPPER_FREQ_THRESHOLD_ADDR,v)
#define HWIO_MCCC_BAND4_UPPER_FREQ_THRESHOLD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_BAND4_UPPER_FREQ_THRESHOLD_ADDR,m,v,HWIO_MCCC_BAND4_UPPER_FREQ_THRESHOLD_IN)
#define HWIO_MCCC_BAND4_UPPER_FREQ_THRESHOLD_THRESHOLD_PERIOD_BMSK             0x1ffff
#define HWIO_MCCC_BAND4_UPPER_FREQ_THRESHOLD_THRESHOLD_PERIOD_SHFT                 0x0

#define HWIO_MCCC_BAND0_CFG0_ADDR                                           (MCCC_MCCC_MSTR_REG_BASE      + 0x00000070)
#define HWIO_MCCC_BAND0_CFG0_OFFS                                           (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000070)
#define HWIO_MCCC_BAND0_CFG0_RMSK                                              0x13311
#define HWIO_MCCC_BAND0_CFG0_IN          \
        in_dword(HWIO_MCCC_BAND0_CFG0_ADDR)
#define HWIO_MCCC_BAND0_CFG0_INM(m)      \
        in_dword_masked(HWIO_MCCC_BAND0_CFG0_ADDR, m)
#define HWIO_MCCC_BAND0_CFG0_OUT(v)      \
        out_dword(HWIO_MCCC_BAND0_CFG0_ADDR,v)
#define HWIO_MCCC_BAND0_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_BAND0_CFG0_ADDR,m,v,HWIO_MCCC_BAND0_CFG0_IN)
#define HWIO_MCCC_BAND0_CFG0_FAST_FREQ_SWITCH_ENABLE_BMSK                      0x10000
#define HWIO_MCCC_BAND0_CFG0_FAST_FREQ_SWITCH_ENABLE_SHFT                         0x10
#define HWIO_MCCC_BAND0_CFG0_FAST_FREQ_SWITCH_ENABLE_DISABLE_FVAL                  0x0
#define HWIO_MCCC_BAND0_CFG0_FAST_FREQ_SWITCH_ENABLE_ENABLE_FVAL                   0x1
#define HWIO_MCCC_BAND0_CFG0_CLOCK_FREQ_RATIO_BMSK                              0x3000
#define HWIO_MCCC_BAND0_CFG0_CLOCK_FREQ_RATIO_SHFT                                 0xc
#define HWIO_MCCC_BAND0_CFG0_CLOCK_FREQ_RATIO_FULL_RATE_FVAL                       0x0
#define HWIO_MCCC_BAND0_CFG0_CLOCK_FREQ_RATIO_HALF_RATE_FVAL                       0x1
#define HWIO_MCCC_BAND0_CFG0_CLOCK_FREQ_RATIO_QTR_RATE_FVAL                        0x3
#define HWIO_MCCC_BAND0_CFG0_DATA_FREQ_RATIO_BMSK                                0x300
#define HWIO_MCCC_BAND0_CFG0_DATA_FREQ_RATIO_SHFT                                  0x8
#define HWIO_MCCC_BAND0_CFG0_DATA_FREQ_RATIO_FULL_RATE_FVAL                        0x0
#define HWIO_MCCC_BAND0_CFG0_DATA_FREQ_RATIO_HALF_RATE_FVAL                        0x1
#define HWIO_MCCC_BAND0_CFG0_DATA_FREQ_RATIO_QTR_RATE_FVAL                         0x3
#define HWIO_MCCC_BAND0_CFG0_DRAM_CLK_DELIVERY_BMSK                               0x10
#define HWIO_MCCC_BAND0_CFG0_DRAM_CLK_DELIVERY_SHFT                                0x4
#define HWIO_MCCC_BAND0_CFG0_DRAM_CLK_DELIVERY_QFI_FVAL                            0x0
#define HWIO_MCCC_BAND0_CFG0_DRAM_CLK_DELIVERY_DIST_NETWORK_FVAL                   0x1
#define HWIO_MCCC_BAND0_CFG0_MC_CLK_PLL_SRC_BMSK                                   0x1
#define HWIO_MCCC_BAND0_CFG0_MC_CLK_PLL_SRC_SHFT                                   0x0
#define HWIO_MCCC_BAND0_CFG0_MC_CLK_PLL_SRC_GCC_FVAL                               0x0
#define HWIO_MCCC_BAND0_CFG0_MC_CLK_PLL_SRC_DDRPHY_FVAL                            0x1

#define HWIO_MCCC_BAND1_CFG0_ADDR                                           (MCCC_MCCC_MSTR_REG_BASE      + 0x00000078)
#define HWIO_MCCC_BAND1_CFG0_OFFS                                           (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000078)
#define HWIO_MCCC_BAND1_CFG0_RMSK                                              0x13311
#define HWIO_MCCC_BAND1_CFG0_IN          \
        in_dword(HWIO_MCCC_BAND1_CFG0_ADDR)
#define HWIO_MCCC_BAND1_CFG0_INM(m)      \
        in_dword_masked(HWIO_MCCC_BAND1_CFG0_ADDR, m)
#define HWIO_MCCC_BAND1_CFG0_OUT(v)      \
        out_dword(HWIO_MCCC_BAND1_CFG0_ADDR,v)
#define HWIO_MCCC_BAND1_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_BAND1_CFG0_ADDR,m,v,HWIO_MCCC_BAND1_CFG0_IN)
#define HWIO_MCCC_BAND1_CFG0_FAST_FREQ_SWITCH_ENABLE_BMSK                      0x10000
#define HWIO_MCCC_BAND1_CFG0_FAST_FREQ_SWITCH_ENABLE_SHFT                         0x10
#define HWIO_MCCC_BAND1_CFG0_FAST_FREQ_SWITCH_ENABLE_DISABLE_FVAL                  0x0
#define HWIO_MCCC_BAND1_CFG0_FAST_FREQ_SWITCH_ENABLE_ENABLE_FVAL                   0x1
#define HWIO_MCCC_BAND1_CFG0_CLOCK_FREQ_RATIO_BMSK                              0x3000
#define HWIO_MCCC_BAND1_CFG0_CLOCK_FREQ_RATIO_SHFT                                 0xc
#define HWIO_MCCC_BAND1_CFG0_CLOCK_FREQ_RATIO_FULL_RATE_FVAL                       0x0
#define HWIO_MCCC_BAND1_CFG0_CLOCK_FREQ_RATIO_HALF_RATE_FVAL                       0x1
#define HWIO_MCCC_BAND1_CFG0_CLOCK_FREQ_RATIO_QTR_RATE_FVAL                        0x3
#define HWIO_MCCC_BAND1_CFG0_DATA_FREQ_RATIO_BMSK                                0x300
#define HWIO_MCCC_BAND1_CFG0_DATA_FREQ_RATIO_SHFT                                  0x8
#define HWIO_MCCC_BAND1_CFG0_DATA_FREQ_RATIO_FULL_RATE_FVAL                        0x0
#define HWIO_MCCC_BAND1_CFG0_DATA_FREQ_RATIO_HALF_RATE_FVAL                        0x1
#define HWIO_MCCC_BAND1_CFG0_DATA_FREQ_RATIO_QTR_RATE_FVAL                         0x3
#define HWIO_MCCC_BAND1_CFG0_DRAM_CLK_DELIVERY_BMSK                               0x10
#define HWIO_MCCC_BAND1_CFG0_DRAM_CLK_DELIVERY_SHFT                                0x4
#define HWIO_MCCC_BAND1_CFG0_DRAM_CLK_DELIVERY_QFI_FVAL                            0x0
#define HWIO_MCCC_BAND1_CFG0_DRAM_CLK_DELIVERY_DIST_NETWORK_FVAL                   0x1
#define HWIO_MCCC_BAND1_CFG0_MC_CLK_PLL_SRC_BMSK                                   0x1
#define HWIO_MCCC_BAND1_CFG0_MC_CLK_PLL_SRC_SHFT                                   0x0
#define HWIO_MCCC_BAND1_CFG0_MC_CLK_PLL_SRC_GCC_FVAL                               0x0
#define HWIO_MCCC_BAND1_CFG0_MC_CLK_PLL_SRC_DDRPHY_FVAL                            0x1

#define HWIO_MCCC_BAND2_CFG0_ADDR                                           (MCCC_MCCC_MSTR_REG_BASE      + 0x00000080)
#define HWIO_MCCC_BAND2_CFG0_OFFS                                           (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000080)
#define HWIO_MCCC_BAND2_CFG0_RMSK                                              0x13311
#define HWIO_MCCC_BAND2_CFG0_IN          \
        in_dword(HWIO_MCCC_BAND2_CFG0_ADDR)
#define HWIO_MCCC_BAND2_CFG0_INM(m)      \
        in_dword_masked(HWIO_MCCC_BAND2_CFG0_ADDR, m)
#define HWIO_MCCC_BAND2_CFG0_OUT(v)      \
        out_dword(HWIO_MCCC_BAND2_CFG0_ADDR,v)
#define HWIO_MCCC_BAND2_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_BAND2_CFG0_ADDR,m,v,HWIO_MCCC_BAND2_CFG0_IN)
#define HWIO_MCCC_BAND2_CFG0_FAST_FREQ_SWITCH_ENABLE_BMSK                      0x10000
#define HWIO_MCCC_BAND2_CFG0_FAST_FREQ_SWITCH_ENABLE_SHFT                         0x10
#define HWIO_MCCC_BAND2_CFG0_FAST_FREQ_SWITCH_ENABLE_DISABLE_FVAL                  0x0
#define HWIO_MCCC_BAND2_CFG0_FAST_FREQ_SWITCH_ENABLE_ENABLE_FVAL                   0x1
#define HWIO_MCCC_BAND2_CFG0_CLOCK_FREQ_RATIO_BMSK                              0x3000
#define HWIO_MCCC_BAND2_CFG0_CLOCK_FREQ_RATIO_SHFT                                 0xc
#define HWIO_MCCC_BAND2_CFG0_CLOCK_FREQ_RATIO_FULL_RATE_FVAL                       0x0
#define HWIO_MCCC_BAND2_CFG0_CLOCK_FREQ_RATIO_HALF_RATE_FVAL                       0x1
#define HWIO_MCCC_BAND2_CFG0_CLOCK_FREQ_RATIO_QTR_RATE_FVAL                        0x3
#define HWIO_MCCC_BAND2_CFG0_DATA_FREQ_RATIO_BMSK                                0x300
#define HWIO_MCCC_BAND2_CFG0_DATA_FREQ_RATIO_SHFT                                  0x8
#define HWIO_MCCC_BAND2_CFG0_DATA_FREQ_RATIO_FULL_RATE_FVAL                        0x0
#define HWIO_MCCC_BAND2_CFG0_DATA_FREQ_RATIO_HALF_RATE_FVAL                        0x1
#define HWIO_MCCC_BAND2_CFG0_DATA_FREQ_RATIO_QTR_RATE_FVAL                         0x3
#define HWIO_MCCC_BAND2_CFG0_DRAM_CLK_DELIVERY_BMSK                               0x10
#define HWIO_MCCC_BAND2_CFG0_DRAM_CLK_DELIVERY_SHFT                                0x4
#define HWIO_MCCC_BAND2_CFG0_DRAM_CLK_DELIVERY_QFI_FVAL                            0x0
#define HWIO_MCCC_BAND2_CFG0_DRAM_CLK_DELIVERY_DIST_NETWORK_FVAL                   0x1
#define HWIO_MCCC_BAND2_CFG0_MC_CLK_PLL_SRC_BMSK                                   0x1
#define HWIO_MCCC_BAND2_CFG0_MC_CLK_PLL_SRC_SHFT                                   0x0
#define HWIO_MCCC_BAND2_CFG0_MC_CLK_PLL_SRC_GCC_FVAL                               0x0
#define HWIO_MCCC_BAND2_CFG0_MC_CLK_PLL_SRC_DDRPHY_FVAL                            0x1

#define HWIO_MCCC_BAND3_CFG0_ADDR                                           (MCCC_MCCC_MSTR_REG_BASE      + 0x00000088)
#define HWIO_MCCC_BAND3_CFG0_OFFS                                           (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000088)
#define HWIO_MCCC_BAND3_CFG0_RMSK                                              0x13311
#define HWIO_MCCC_BAND3_CFG0_IN          \
        in_dword(HWIO_MCCC_BAND3_CFG0_ADDR)
#define HWIO_MCCC_BAND3_CFG0_INM(m)      \
        in_dword_masked(HWIO_MCCC_BAND3_CFG0_ADDR, m)
#define HWIO_MCCC_BAND3_CFG0_OUT(v)      \
        out_dword(HWIO_MCCC_BAND3_CFG0_ADDR,v)
#define HWIO_MCCC_BAND3_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_BAND3_CFG0_ADDR,m,v,HWIO_MCCC_BAND3_CFG0_IN)
#define HWIO_MCCC_BAND3_CFG0_FAST_FREQ_SWITCH_ENABLE_BMSK                      0x10000
#define HWIO_MCCC_BAND3_CFG0_FAST_FREQ_SWITCH_ENABLE_SHFT                         0x10
#define HWIO_MCCC_BAND3_CFG0_FAST_FREQ_SWITCH_ENABLE_DISABLE_FVAL                  0x0
#define HWIO_MCCC_BAND3_CFG0_FAST_FREQ_SWITCH_ENABLE_ENABLE_FVAL                   0x1
#define HWIO_MCCC_BAND3_CFG0_CLOCK_FREQ_RATIO_BMSK                              0x3000
#define HWIO_MCCC_BAND3_CFG0_CLOCK_FREQ_RATIO_SHFT                                 0xc
#define HWIO_MCCC_BAND3_CFG0_CLOCK_FREQ_RATIO_FULL_RATE_FVAL                       0x0
#define HWIO_MCCC_BAND3_CFG0_CLOCK_FREQ_RATIO_HALF_RATE_FVAL                       0x1
#define HWIO_MCCC_BAND3_CFG0_CLOCK_FREQ_RATIO_QTR_RATE_FVAL                        0x3
#define HWIO_MCCC_BAND3_CFG0_DATA_FREQ_RATIO_BMSK                                0x300
#define HWIO_MCCC_BAND3_CFG0_DATA_FREQ_RATIO_SHFT                                  0x8
#define HWIO_MCCC_BAND3_CFG0_DATA_FREQ_RATIO_FULL_RATE_FVAL                        0x0
#define HWIO_MCCC_BAND3_CFG0_DATA_FREQ_RATIO_HALF_RATE_FVAL                        0x1
#define HWIO_MCCC_BAND3_CFG0_DATA_FREQ_RATIO_QTR_RATE_FVAL                         0x3
#define HWIO_MCCC_BAND3_CFG0_DRAM_CLK_DELIVERY_BMSK                               0x10
#define HWIO_MCCC_BAND3_CFG0_DRAM_CLK_DELIVERY_SHFT                                0x4
#define HWIO_MCCC_BAND3_CFG0_DRAM_CLK_DELIVERY_QFI_FVAL                            0x0
#define HWIO_MCCC_BAND3_CFG0_DRAM_CLK_DELIVERY_DIST_NETWORK_FVAL                   0x1
#define HWIO_MCCC_BAND3_CFG0_MC_CLK_PLL_SRC_BMSK                                   0x1
#define HWIO_MCCC_BAND3_CFG0_MC_CLK_PLL_SRC_SHFT                                   0x0
#define HWIO_MCCC_BAND3_CFG0_MC_CLK_PLL_SRC_GCC_FVAL                               0x0
#define HWIO_MCCC_BAND3_CFG0_MC_CLK_PLL_SRC_DDRPHY_FVAL                            0x1

#define HWIO_MCCC_BAND4_CFG0_ADDR                                           (MCCC_MCCC_MSTR_REG_BASE      + 0x00000090)
#define HWIO_MCCC_BAND4_CFG0_OFFS                                           (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000090)
#define HWIO_MCCC_BAND4_CFG0_RMSK                                              0x13311
#define HWIO_MCCC_BAND4_CFG0_IN          \
        in_dword(HWIO_MCCC_BAND4_CFG0_ADDR)
#define HWIO_MCCC_BAND4_CFG0_INM(m)      \
        in_dword_masked(HWIO_MCCC_BAND4_CFG0_ADDR, m)
#define HWIO_MCCC_BAND4_CFG0_OUT(v)      \
        out_dword(HWIO_MCCC_BAND4_CFG0_ADDR,v)
#define HWIO_MCCC_BAND4_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_BAND4_CFG0_ADDR,m,v,HWIO_MCCC_BAND4_CFG0_IN)
#define HWIO_MCCC_BAND4_CFG0_FAST_FREQ_SWITCH_ENABLE_BMSK                      0x10000
#define HWIO_MCCC_BAND4_CFG0_FAST_FREQ_SWITCH_ENABLE_SHFT                         0x10
#define HWIO_MCCC_BAND4_CFG0_FAST_FREQ_SWITCH_ENABLE_DISABLE_FVAL                  0x0
#define HWIO_MCCC_BAND4_CFG0_FAST_FREQ_SWITCH_ENABLE_ENABLE_FVAL                   0x1
#define HWIO_MCCC_BAND4_CFG0_CLOCK_FREQ_RATIO_BMSK                              0x3000
#define HWIO_MCCC_BAND4_CFG0_CLOCK_FREQ_RATIO_SHFT                                 0xc
#define HWIO_MCCC_BAND4_CFG0_CLOCK_FREQ_RATIO_FULL_RATE_FVAL                       0x0
#define HWIO_MCCC_BAND4_CFG0_CLOCK_FREQ_RATIO_HALF_RATE_FVAL                       0x1
#define HWIO_MCCC_BAND4_CFG0_CLOCK_FREQ_RATIO_QTR_RATE_FVAL                        0x3
#define HWIO_MCCC_BAND4_CFG0_DATA_FREQ_RATIO_BMSK                                0x300
#define HWIO_MCCC_BAND4_CFG0_DATA_FREQ_RATIO_SHFT                                  0x8
#define HWIO_MCCC_BAND4_CFG0_DATA_FREQ_RATIO_FULL_RATE_FVAL                        0x0
#define HWIO_MCCC_BAND4_CFG0_DATA_FREQ_RATIO_HALF_RATE_FVAL                        0x1
#define HWIO_MCCC_BAND4_CFG0_DATA_FREQ_RATIO_QTR_RATE_FVAL                         0x3
#define HWIO_MCCC_BAND4_CFG0_DRAM_CLK_DELIVERY_BMSK                               0x10
#define HWIO_MCCC_BAND4_CFG0_DRAM_CLK_DELIVERY_SHFT                                0x4
#define HWIO_MCCC_BAND4_CFG0_DRAM_CLK_DELIVERY_QFI_FVAL                            0x0
#define HWIO_MCCC_BAND4_CFG0_DRAM_CLK_DELIVERY_DIST_NETWORK_FVAL                   0x1
#define HWIO_MCCC_BAND4_CFG0_MC_CLK_PLL_SRC_BMSK                                   0x1
#define HWIO_MCCC_BAND4_CFG0_MC_CLK_PLL_SRC_SHFT                                   0x0
#define HWIO_MCCC_BAND4_CFG0_MC_CLK_PLL_SRC_GCC_FVAL                               0x0
#define HWIO_MCCC_BAND4_CFG0_MC_CLK_PLL_SRC_DDRPHY_FVAL                            0x1

#define HWIO_MCCC_BAND5_CFG0_ADDR                                           (MCCC_MCCC_MSTR_REG_BASE      + 0x00000098)
#define HWIO_MCCC_BAND5_CFG0_OFFS                                           (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000098)
#define HWIO_MCCC_BAND5_CFG0_RMSK                                              0x13311
#define HWIO_MCCC_BAND5_CFG0_IN          \
        in_dword(HWIO_MCCC_BAND5_CFG0_ADDR)
#define HWIO_MCCC_BAND5_CFG0_INM(m)      \
        in_dword_masked(HWIO_MCCC_BAND5_CFG0_ADDR, m)
#define HWIO_MCCC_BAND5_CFG0_OUT(v)      \
        out_dword(HWIO_MCCC_BAND5_CFG0_ADDR,v)
#define HWIO_MCCC_BAND5_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_BAND5_CFG0_ADDR,m,v,HWIO_MCCC_BAND5_CFG0_IN)
#define HWIO_MCCC_BAND5_CFG0_FAST_FREQ_SWITCH_ENABLE_BMSK                      0x10000
#define HWIO_MCCC_BAND5_CFG0_FAST_FREQ_SWITCH_ENABLE_SHFT                         0x10
#define HWIO_MCCC_BAND5_CFG0_FAST_FREQ_SWITCH_ENABLE_DISABLE_FVAL                  0x0
#define HWIO_MCCC_BAND5_CFG0_FAST_FREQ_SWITCH_ENABLE_ENABLE_FVAL                   0x1
#define HWIO_MCCC_BAND5_CFG0_CLOCK_FREQ_RATIO_BMSK                              0x3000
#define HWIO_MCCC_BAND5_CFG0_CLOCK_FREQ_RATIO_SHFT                                 0xc
#define HWIO_MCCC_BAND5_CFG0_CLOCK_FREQ_RATIO_FULL_RATE_FVAL                       0x0
#define HWIO_MCCC_BAND5_CFG0_CLOCK_FREQ_RATIO_HALF_RATE_FVAL                       0x1
#define HWIO_MCCC_BAND5_CFG0_CLOCK_FREQ_RATIO_QTR_RATE_FVAL                        0x3
#define HWIO_MCCC_BAND5_CFG0_DATA_FREQ_RATIO_BMSK                                0x300
#define HWIO_MCCC_BAND5_CFG0_DATA_FREQ_RATIO_SHFT                                  0x8
#define HWIO_MCCC_BAND5_CFG0_DATA_FREQ_RATIO_FULL_RATE_FVAL                        0x0
#define HWIO_MCCC_BAND5_CFG0_DATA_FREQ_RATIO_HALF_RATE_FVAL                        0x1
#define HWIO_MCCC_BAND5_CFG0_DATA_FREQ_RATIO_QTR_RATE_FVAL                         0x3
#define HWIO_MCCC_BAND5_CFG0_DRAM_CLK_DELIVERY_BMSK                               0x10
#define HWIO_MCCC_BAND5_CFG0_DRAM_CLK_DELIVERY_SHFT                                0x4
#define HWIO_MCCC_BAND5_CFG0_DRAM_CLK_DELIVERY_QFI_FVAL                            0x0
#define HWIO_MCCC_BAND5_CFG0_DRAM_CLK_DELIVERY_DIST_NETWORK_FVAL                   0x1
#define HWIO_MCCC_BAND5_CFG0_MC_CLK_PLL_SRC_BMSK                                   0x1
#define HWIO_MCCC_BAND5_CFG0_MC_CLK_PLL_SRC_SHFT                                   0x0
#define HWIO_MCCC_BAND5_CFG0_MC_CLK_PLL_SRC_GCC_FVAL                               0x0
#define HWIO_MCCC_BAND5_CFG0_MC_CLK_PLL_SRC_DDRPHY_FVAL                            0x1

#define HWIO_MCCC_TASK_MASK_CFG0_ADDR                                       (MCCC_MCCC_MSTR_REG_BASE      + 0x00000130)
#define HWIO_MCCC_TASK_MASK_CFG0_OFFS                                       (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000130)
#define HWIO_MCCC_TASK_MASK_CFG0_RMSK                                       0x1070001f
#define HWIO_MCCC_TASK_MASK_CFG0_IN          \
        in_dword(HWIO_MCCC_TASK_MASK_CFG0_ADDR)
#define HWIO_MCCC_TASK_MASK_CFG0_INM(m)      \
        in_dword_masked(HWIO_MCCC_TASK_MASK_CFG0_ADDR, m)
#define HWIO_MCCC_TASK_MASK_CFG0_OUT(v)      \
        out_dword(HWIO_MCCC_TASK_MASK_CFG0_ADDR,v)
#define HWIO_MCCC_TASK_MASK_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_TASK_MASK_CFG0_ADDR,m,v,HWIO_MCCC_TASK_MASK_CFG0_IN)
#define HWIO_MCCC_TASK_MASK_CFG0_ENABLE_BMSK                                0x10000000
#define HWIO_MCCC_TASK_MASK_CFG0_ENABLE_SHFT                                      0x1c
#define HWIO_MCCC_TASK_MASK_CFG0_DEP_SAME_FREQ_RATIO_BMSK                     0x400000
#define HWIO_MCCC_TASK_MASK_CFG0_DEP_SAME_FREQ_RATIO_SHFT                         0x16
#define HWIO_MCCC_TASK_MASK_CFG0_DEP_SAME_PERIOD_BMSK                         0x200000
#define HWIO_MCCC_TASK_MASK_CFG0_DEP_SAME_PERIOD_SHFT                             0x15
#define HWIO_MCCC_TASK_MASK_CFG0_DEP_SAME_PLL_SRC_BMSK                        0x100000
#define HWIO_MCCC_TASK_MASK_CFG0_DEP_SAME_PLL_SRC_SHFT                            0x14
#define HWIO_MCCC_TASK_MASK_CFG0_TASK4_RX_DISABLE_MASK_BMSK                       0x10
#define HWIO_MCCC_TASK_MASK_CFG0_TASK4_RX_DISABLE_MASK_SHFT                        0x4
#define HWIO_MCCC_TASK_MASK_CFG0_TASK3_CDIV_MASK_BMSK                              0x8
#define HWIO_MCCC_TASK_MASK_CFG0_TASK3_CDIV_MASK_SHFT                              0x3
#define HWIO_MCCC_TASK_MASK_CFG0_TASK2_GFCM_SSP_CDIV_MASK_BMSK                     0x4
#define HWIO_MCCC_TASK_MASK_CFG0_TASK2_GFCM_SSP_CDIV_MASK_SHFT                     0x2
#define HWIO_MCCC_TASK_MASK_CFG0_TASK1_RX_CLKON_MASK_BMSK                          0x2
#define HWIO_MCCC_TASK_MASK_CFG0_TASK1_RX_CLKON_MASK_SHFT                          0x1
#define HWIO_MCCC_TASK_MASK_CFG0_TASK0_RX_ENABLE_MASK_BMSK                         0x1
#define HWIO_MCCC_TASK_MASK_CFG0_TASK0_RX_ENABLE_MASK_SHFT                         0x0

#define HWIO_MCCC_TASK_MASK_CFG1_ADDR                                       (MCCC_MCCC_MSTR_REG_BASE      + 0x00000134)
#define HWIO_MCCC_TASK_MASK_CFG1_OFFS                                       (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000134)
#define HWIO_MCCC_TASK_MASK_CFG1_RMSK                                       0x1070001f
#define HWIO_MCCC_TASK_MASK_CFG1_IN          \
        in_dword(HWIO_MCCC_TASK_MASK_CFG1_ADDR)
#define HWIO_MCCC_TASK_MASK_CFG1_INM(m)      \
        in_dword_masked(HWIO_MCCC_TASK_MASK_CFG1_ADDR, m)
#define HWIO_MCCC_TASK_MASK_CFG1_OUT(v)      \
        out_dword(HWIO_MCCC_TASK_MASK_CFG1_ADDR,v)
#define HWIO_MCCC_TASK_MASK_CFG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_TASK_MASK_CFG1_ADDR,m,v,HWIO_MCCC_TASK_MASK_CFG1_IN)
#define HWIO_MCCC_TASK_MASK_CFG1_ENABLE_BMSK                                0x10000000
#define HWIO_MCCC_TASK_MASK_CFG1_ENABLE_SHFT                                      0x1c
#define HWIO_MCCC_TASK_MASK_CFG1_DEP_SAME_FREQ_RATIO_BMSK                     0x400000
#define HWIO_MCCC_TASK_MASK_CFG1_DEP_SAME_FREQ_RATIO_SHFT                         0x16
#define HWIO_MCCC_TASK_MASK_CFG1_DEP_SAME_PERIOD_BMSK                         0x200000
#define HWIO_MCCC_TASK_MASK_CFG1_DEP_SAME_PERIOD_SHFT                             0x15
#define HWIO_MCCC_TASK_MASK_CFG1_DEP_SAME_PLL_SRC_BMSK                        0x100000
#define HWIO_MCCC_TASK_MASK_CFG1_DEP_SAME_PLL_SRC_SHFT                            0x14
#define HWIO_MCCC_TASK_MASK_CFG1_TASK4_RX_DISABLE_MASK_BMSK                       0x10
#define HWIO_MCCC_TASK_MASK_CFG1_TASK4_RX_DISABLE_MASK_SHFT                        0x4
#define HWIO_MCCC_TASK_MASK_CFG1_TASK3_CDIV_MASK_BMSK                              0x8
#define HWIO_MCCC_TASK_MASK_CFG1_TASK3_CDIV_MASK_SHFT                              0x3
#define HWIO_MCCC_TASK_MASK_CFG1_TASK2_GFCM_SSP_CDIV_MASK_BMSK                     0x4
#define HWIO_MCCC_TASK_MASK_CFG1_TASK2_GFCM_SSP_CDIV_MASK_SHFT                     0x2
#define HWIO_MCCC_TASK_MASK_CFG1_TASK1_RX_CLKON_MASK_BMSK                          0x2
#define HWIO_MCCC_TASK_MASK_CFG1_TASK1_RX_CLKON_MASK_SHFT                          0x1
#define HWIO_MCCC_TASK_MASK_CFG1_TASK0_RX_ENABLE_MASK_BMSK                         0x1
#define HWIO_MCCC_TASK_MASK_CFG1_TASK0_RX_ENABLE_MASK_SHFT                         0x0

#define HWIO_MCCC_SINGLE_TASK_ENGINE_UPDATE_ADDR                            (MCCC_MCCC_MSTR_REG_BASE      + 0x00000140)
#define HWIO_MCCC_SINGLE_TASK_ENGINE_UPDATE_OFFS                            (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000140)
#define HWIO_MCCC_SINGLE_TASK_ENGINE_UPDATE_RMSK                                   0x1
#define HWIO_MCCC_SINGLE_TASK_ENGINE_UPDATE_IN          \
        in_dword(HWIO_MCCC_SINGLE_TASK_ENGINE_UPDATE_ADDR)
#define HWIO_MCCC_SINGLE_TASK_ENGINE_UPDATE_INM(m)      \
        in_dword_masked(HWIO_MCCC_SINGLE_TASK_ENGINE_UPDATE_ADDR, m)
#define HWIO_MCCC_SINGLE_TASK_ENGINE_UPDATE_OUT(v)      \
        out_dword(HWIO_MCCC_SINGLE_TASK_ENGINE_UPDATE_ADDR,v)
#define HWIO_MCCC_SINGLE_TASK_ENGINE_UPDATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_SINGLE_TASK_ENGINE_UPDATE_ADDR,m,v,HWIO_MCCC_SINGLE_TASK_ENGINE_UPDATE_IN)
#define HWIO_MCCC_SINGLE_TASK_ENGINE_UPDATE_ACTIVE_BMSK                            0x1
#define HWIO_MCCC_SINGLE_TASK_ENGINE_UPDATE_ACTIVE_SHFT                            0x0

#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_ADDR                               (MCCC_MCCC_MSTR_REG_BASE      + 0x00000144)
#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_OFFS                               (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000144)
#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_RMSK                                     0x1f
#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_IN          \
        in_dword(HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_ADDR)
#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_INM(m)      \
        in_dword_masked(HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_ADDR, m)
#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_OUT(v)      \
        out_dword(HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_ADDR,v)
#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_ADDR,m,v,HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_IN)
#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_TASK4_RX_DISABLE_BMSK                    0x10
#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_TASK4_RX_DISABLE_SHFT                     0x4
#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_TASK3_CDIV_BMSK                           0x8
#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_TASK3_CDIV_SHFT                           0x3
#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_TASK2_GFCM_SSP_CDIV_BMSK                  0x4
#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_TASK2_GFCM_SSP_CDIV_SHFT                  0x2
#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_TASK1_RX_CLKON_BMSK                       0x2
#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_TASK1_RX_CLKON_SHFT                       0x1
#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_TASK0_RX_ENABLE_BMSK                      0x1
#define HWIO_MCCC_SINGLE_TASK_ENGINE_CFG_TASK0_RX_ENABLE_SHFT                      0x0

#define HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_ADDR                            (MCCC_MCCC_MSTR_REG_BASE      + 0x00000150)
#define HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_OFFS                            (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000150)
#define HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_RMSK                               0x11f1f
#define HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_IN          \
        in_dword(HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_ADDR)
#define HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_INM(m)      \
        in_dword_masked(HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_ADDR, m)
#define HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_OUT(v)      \
        out_dword(HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_ADDR,v)
#define HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_ADDR,m,v,HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_IN)
#define HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_FAST_FREQ_SWITCH_BMSK              0x10000
#define HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_FAST_FREQ_SWITCH_SHFT                 0x10
#define HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_STOP_STATE_BMSK                     0x1f00
#define HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_STOP_STATE_SHFT                        0x8
#define HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_START_STATE_BMSK                      0x1f
#define HWIO_MCCC_GCC_MC_CLKON_OVERRIDE_CFG_START_STATE_SHFT                       0x0

#define HWIO_MCCC_CLOCK_GATE_CFG_ADDR                                       (MCCC_MCCC_MSTR_REG_BASE      + 0x00000210)
#define HWIO_MCCC_CLOCK_GATE_CFG_OFFS                                       (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000210)
#define HWIO_MCCC_CLOCK_GATE_CFG_RMSK                                          0x11111
#define HWIO_MCCC_CLOCK_GATE_CFG_IN          \
        in_dword(HWIO_MCCC_CLOCK_GATE_CFG_ADDR)
#define HWIO_MCCC_CLOCK_GATE_CFG_INM(m)      \
        in_dword_masked(HWIO_MCCC_CLOCK_GATE_CFG_ADDR, m)
#define HWIO_MCCC_CLOCK_GATE_CFG_OUT(v)      \
        out_dword(HWIO_MCCC_CLOCK_GATE_CFG_ADDR,v)
#define HWIO_MCCC_CLOCK_GATE_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_CLOCK_GATE_CFG_ADDR,m,v,HWIO_MCCC_CLOCK_GATE_CFG_IN)
#define HWIO_MCCC_CLOCK_GATE_CFG_XO_RCG_SW_CLK_ON_BMSK                         0x10000
#define HWIO_MCCC_CLOCK_GATE_CFG_XO_RCG_SW_CLK_ON_SHFT                            0x10
#define HWIO_MCCC_CLOCK_GATE_CFG_MCCC_RCG_SW_CLK_ON_BMSK                        0x1000
#define HWIO_MCCC_CLOCK_GATE_CFG_MCCC_RCG_SW_CLK_ON_SHFT                           0xc
#define HWIO_MCCC_CLOCK_GATE_CFG_INTERWORK_CLK_ENABLE_BMSK                       0x100
#define HWIO_MCCC_CLOCK_GATE_CFG_INTERWORK_CLK_ENABLE_SHFT                         0x8
#define HWIO_MCCC_CLOCK_GATE_CFG_MCCC_CLK_DISABLE_BMSK                            0x10
#define HWIO_MCCC_CLOCK_GATE_CFG_MCCC_CLK_DISABLE_SHFT                             0x4
#define HWIO_MCCC_CLOCK_GATE_CFG_MCCC_HW_CLKGATE_EN_BMSK                           0x1
#define HWIO_MCCC_CLOCK_GATE_CFG_MCCC_HW_CLKGATE_EN_SHFT                           0x0

#define HWIO_MCCC_FREQ_SWITCH_DISABLE_ADDR                                  (MCCC_MCCC_MSTR_REG_BASE      + 0x00000214)
#define HWIO_MCCC_FREQ_SWITCH_DISABLE_OFFS                                  (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000214)
#define HWIO_MCCC_FREQ_SWITCH_DISABLE_RMSK                                         0x1
#define HWIO_MCCC_FREQ_SWITCH_DISABLE_IN          \
        in_dword(HWIO_MCCC_FREQ_SWITCH_DISABLE_ADDR)
#define HWIO_MCCC_FREQ_SWITCH_DISABLE_INM(m)      \
        in_dword_masked(HWIO_MCCC_FREQ_SWITCH_DISABLE_ADDR, m)
#define HWIO_MCCC_FREQ_SWITCH_DISABLE_OUT(v)      \
        out_dword(HWIO_MCCC_FREQ_SWITCH_DISABLE_ADDR,v)
#define HWIO_MCCC_FREQ_SWITCH_DISABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_FREQ_SWITCH_DISABLE_ADDR,m,v,HWIO_MCCC_FREQ_SWITCH_DISABLE_IN)
#define HWIO_MCCC_FREQ_SWITCH_DISABLE_DISABLE_BMSK                                 0x1
#define HWIO_MCCC_FREQ_SWITCH_DISABLE_DISABLE_SHFT                                 0x0
#define HWIO_MCCC_FREQ_SWITCH_DISABLE_DISABLE_NOT_DISABLE_FVAL                     0x0
#define HWIO_MCCC_FREQ_SWITCH_DISABLE_DISABLE_DISABLE_FVAL                         0x1

#define HWIO_MCCC_CHANNEL_DISABLE_ADDR                                      (MCCC_MCCC_MSTR_REG_BASE      + 0x00000218)
#define HWIO_MCCC_CHANNEL_DISABLE_OFFS                                      (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000218)
#define HWIO_MCCC_CHANNEL_DISABLE_RMSK                                             0xf
#define HWIO_MCCC_CHANNEL_DISABLE_IN          \
        in_dword(HWIO_MCCC_CHANNEL_DISABLE_ADDR)
#define HWIO_MCCC_CHANNEL_DISABLE_INM(m)      \
        in_dword_masked(HWIO_MCCC_CHANNEL_DISABLE_ADDR, m)
#define HWIO_MCCC_CHANNEL_DISABLE_OUT(v)      \
        out_dword(HWIO_MCCC_CHANNEL_DISABLE_ADDR,v)
#define HWIO_MCCC_CHANNEL_DISABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_CHANNEL_DISABLE_ADDR,m,v,HWIO_MCCC_CHANNEL_DISABLE_IN)
#define HWIO_MCCC_CHANNEL_DISABLE_CH3_DISABLE_BMSK                                 0x8
#define HWIO_MCCC_CHANNEL_DISABLE_CH3_DISABLE_SHFT                                 0x3
#define HWIO_MCCC_CHANNEL_DISABLE_CH3_DISABLE_NOT_DISABLE_FVAL                     0x0
#define HWIO_MCCC_CHANNEL_DISABLE_CH3_DISABLE_DISABLE_FVAL                         0x1
#define HWIO_MCCC_CHANNEL_DISABLE_CH2_DISABLE_BMSK                                 0x4
#define HWIO_MCCC_CHANNEL_DISABLE_CH2_DISABLE_SHFT                                 0x2
#define HWIO_MCCC_CHANNEL_DISABLE_CH2_DISABLE_NOT_DISABLE_FVAL                     0x0
#define HWIO_MCCC_CHANNEL_DISABLE_CH2_DISABLE_DISABLE_FVAL                         0x1
#define HWIO_MCCC_CHANNEL_DISABLE_CH1_DISABLE_BMSK                                 0x2
#define HWIO_MCCC_CHANNEL_DISABLE_CH1_DISABLE_SHFT                                 0x1
#define HWIO_MCCC_CHANNEL_DISABLE_CH1_DISABLE_NOT_DISABLE_FVAL                     0x0
#define HWIO_MCCC_CHANNEL_DISABLE_CH1_DISABLE_DISABLE_FVAL                         0x1
#define HWIO_MCCC_CHANNEL_DISABLE_CH0_DISABLE_BMSK                                 0x1
#define HWIO_MCCC_CHANNEL_DISABLE_CH0_DISABLE_SHFT                                 0x0
#define HWIO_MCCC_CHANNEL_DISABLE_CH0_DISABLE_NOT_DISABLE_FVAL                     0x0
#define HWIO_MCCC_CHANNEL_DISABLE_CH0_DISABLE_DISABLE_FVAL                         0x1

#define HWIO_MCCC_SPARE0_ADDR                                               (MCCC_MCCC_MSTR_REG_BASE      + 0x00000230)
#define HWIO_MCCC_SPARE0_OFFS                                               (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000230)
#define HWIO_MCCC_SPARE0_RMSK                                                      0xf
#define HWIO_MCCC_SPARE0_IN          \
        in_dword(HWIO_MCCC_SPARE0_ADDR)
#define HWIO_MCCC_SPARE0_INM(m)      \
        in_dword_masked(HWIO_MCCC_SPARE0_ADDR, m)
#define HWIO_MCCC_SPARE0_OUT(v)      \
        out_dword(HWIO_MCCC_SPARE0_ADDR,v)
#define HWIO_MCCC_SPARE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_SPARE0_ADDR,m,v,HWIO_MCCC_SPARE0_IN)
#define HWIO_MCCC_SPARE0_SPARE_BMSK                                                0xf
#define HWIO_MCCC_SPARE0_SPARE_SHFT                                                0x0

#define HWIO_MCCC_SPARE1_ADDR                                               (MCCC_MCCC_MSTR_REG_BASE      + 0x00000234)
#define HWIO_MCCC_SPARE1_OFFS                                               (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000234)
#define HWIO_MCCC_SPARE1_RMSK                                                      0xf
#define HWIO_MCCC_SPARE1_IN          \
        in_dword(HWIO_MCCC_SPARE1_ADDR)
#define HWIO_MCCC_SPARE1_INM(m)      \
        in_dword_masked(HWIO_MCCC_SPARE1_ADDR, m)
#define HWIO_MCCC_SPARE1_OUT(v)      \
        out_dword(HWIO_MCCC_SPARE1_ADDR,v)
#define HWIO_MCCC_SPARE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_SPARE1_ADDR,m,v,HWIO_MCCC_SPARE1_IN)
#define HWIO_MCCC_SPARE1_SPARE_BMSK                                                0xf
#define HWIO_MCCC_SPARE1_SPARE_SHFT                                                0x0

#define HWIO_MCCC_SW_CTL0_ADDR                                              (MCCC_MCCC_MSTR_REG_BASE      + 0x00000244)
#define HWIO_MCCC_SW_CTL0_OFFS                                              (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000244)
#define HWIO_MCCC_SW_CTL0_RMSK                                                  0x1113
#define HWIO_MCCC_SW_CTL0_IN          \
        in_dword(HWIO_MCCC_SW_CTL0_ADDR)
#define HWIO_MCCC_SW_CTL0_INM(m)      \
        in_dword_masked(HWIO_MCCC_SW_CTL0_ADDR, m)
#define HWIO_MCCC_SW_CTL0_OUT(v)      \
        out_dword(HWIO_MCCC_SW_CTL0_ADDR,v)
#define HWIO_MCCC_SW_CTL0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_SW_CTL0_ADDR,m,v,HWIO_MCCC_SW_CTL0_IN)
#define HWIO_MCCC_SW_CTL0_INTER_PLL_SRC_TOGGLE_BMSK                             0x1000
#define HWIO_MCCC_SW_CTL0_INTER_PLL_SRC_TOGGLE_SHFT                                0xc
#define HWIO_MCCC_SW_CTL0_FIRST_FREQ_SWITCH_TOGGLE_BMSK                          0x100
#define HWIO_MCCC_SW_CTL0_FIRST_FREQ_SWITCH_TOGGLE_SHFT                            0x8
#define HWIO_MCCC_SW_CTL0_FREQ_SWITCH_TOGGLE_MASK_BMSK                            0x10
#define HWIO_MCCC_SW_CTL0_FREQ_SWITCH_TOGGLE_MASK_SHFT                             0x4
#define HWIO_MCCC_SW_CTL0_MC_CLK_MUX_POL_BMSK                                      0x2
#define HWIO_MCCC_SW_CTL0_MC_CLK_MUX_POL_SHFT                                      0x1
#define HWIO_MCCC_SW_CTL0_MC_CLK_MUX_POL_SRC0_FVAL                                 0x0
#define HWIO_MCCC_SW_CTL0_MC_CLK_MUX_POL_SRC1_FVAL                                 0x1
#define HWIO_MCCC_SW_CTL0_MC_CLK_MUX_POL_SW_CTL_BMSK                               0x1
#define HWIO_MCCC_SW_CTL0_MC_CLK_MUX_POL_SW_CTL_SHFT                               0x0
#define HWIO_MCCC_SW_CTL0_MC_CLK_MUX_POL_SW_CTL_HW_CONTROL_FVAL                    0x0
#define HWIO_MCCC_SW_CTL0_MC_CLK_MUX_POL_SW_CTL_SW_CONTROL_FVAL                    0x1

#define HWIO_MCCC_SW_OVERRIDE_UPDATE_ADDR                                   (MCCC_MCCC_MSTR_REG_BASE      + 0x00000250)
#define HWIO_MCCC_SW_OVERRIDE_UPDATE_OFFS                                   (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000250)
#define HWIO_MCCC_SW_OVERRIDE_UPDATE_RMSK                                          0x1
#define HWIO_MCCC_SW_OVERRIDE_UPDATE_IN          \
        in_dword(HWIO_MCCC_SW_OVERRIDE_UPDATE_ADDR)
#define HWIO_MCCC_SW_OVERRIDE_UPDATE_INM(m)      \
        in_dword_masked(HWIO_MCCC_SW_OVERRIDE_UPDATE_ADDR, m)
#define HWIO_MCCC_SW_OVERRIDE_UPDATE_OUT(v)      \
        out_dword(HWIO_MCCC_SW_OVERRIDE_UPDATE_ADDR,v)
#define HWIO_MCCC_SW_OVERRIDE_UPDATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_SW_OVERRIDE_UPDATE_ADDR,m,v,HWIO_MCCC_SW_OVERRIDE_UPDATE_IN)
#define HWIO_MCCC_SW_OVERRIDE_UPDATE_UPDATE_BMSK                                   0x1
#define HWIO_MCCC_SW_OVERRIDE_UPDATE_UPDATE_SHFT                                   0x0

#define HWIO_MCCC_SW_OVERRIDE0_ADDR                                         (MCCC_MCCC_MSTR_REG_BASE      + 0x00000258)
#define HWIO_MCCC_SW_OVERRIDE0_OFFS                                         (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000258)
#define HWIO_MCCC_SW_OVERRIDE0_RMSK                                          0xf0001f1
#define HWIO_MCCC_SW_OVERRIDE0_IN          \
        in_dword(HWIO_MCCC_SW_OVERRIDE0_ADDR)
#define HWIO_MCCC_SW_OVERRIDE0_INM(m)      \
        in_dword_masked(HWIO_MCCC_SW_OVERRIDE0_ADDR, m)
#define HWIO_MCCC_SW_OVERRIDE0_OUT(v)      \
        out_dword(HWIO_MCCC_SW_OVERRIDE0_ADDR,v)
#define HWIO_MCCC_SW_OVERRIDE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_SW_OVERRIDE0_ADDR,m,v,HWIO_MCCC_SW_OVERRIDE0_IN)
#define HWIO_MCCC_SW_OVERRIDE0_STE_CH3_ACK_MASK_BMSK                         0x8000000
#define HWIO_MCCC_SW_OVERRIDE0_STE_CH3_ACK_MASK_SHFT                              0x1b
#define HWIO_MCCC_SW_OVERRIDE0_STE_CH2_ACK_MASK_BMSK                         0x4000000
#define HWIO_MCCC_SW_OVERRIDE0_STE_CH2_ACK_MASK_SHFT                              0x1a
#define HWIO_MCCC_SW_OVERRIDE0_STE_CH1_ACK_MASK_BMSK                         0x2000000
#define HWIO_MCCC_SW_OVERRIDE0_STE_CH1_ACK_MASK_SHFT                              0x19
#define HWIO_MCCC_SW_OVERRIDE0_STE_CH0_ACK_MASK_BMSK                         0x1000000
#define HWIO_MCCC_SW_OVERRIDE0_STE_CH0_ACK_MASK_SHFT                              0x18
#define HWIO_MCCC_SW_OVERRIDE0_BREAKPOINT_STATE_BMSK                             0x1f0
#define HWIO_MCCC_SW_OVERRIDE0_BREAKPOINT_STATE_SHFT                               0x4
#define HWIO_MCCC_SW_OVERRIDE0_BREAKPOINT_SW_CTL_BMSK                              0x1
#define HWIO_MCCC_SW_OVERRIDE0_BREAKPOINT_SW_CTL_SHFT                              0x0

#define HWIO_MCCC_SW_OVERRIDE1_ADDR                                         (MCCC_MCCC_MSTR_REG_BASE      + 0x0000025c)
#define HWIO_MCCC_SW_OVERRIDE1_OFFS                                         (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x0000025c)
#define HWIO_MCCC_SW_OVERRIDE1_RMSK                                               0x33
#define HWIO_MCCC_SW_OVERRIDE1_IN          \
        in_dword(HWIO_MCCC_SW_OVERRIDE1_ADDR)
#define HWIO_MCCC_SW_OVERRIDE1_INM(m)      \
        in_dword_masked(HWIO_MCCC_SW_OVERRIDE1_ADDR, m)
#define HWIO_MCCC_SW_OVERRIDE1_OUT(v)      \
        out_dword(HWIO_MCCC_SW_OVERRIDE1_ADDR,v)
#define HWIO_MCCC_SW_OVERRIDE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_SW_OVERRIDE1_ADDR,m,v,HWIO_MCCC_SW_OVERRIDE1_IN)
#define HWIO_MCCC_SW_OVERRIDE1_GCC_SRC1_CLK_ON_BMSK                               0x20
#define HWIO_MCCC_SW_OVERRIDE1_GCC_SRC1_CLK_ON_SHFT                                0x5
#define HWIO_MCCC_SW_OVERRIDE1_GCC_SRC1_CLK_ON_SW_CTL_BMSK                        0x10
#define HWIO_MCCC_SW_OVERRIDE1_GCC_SRC1_CLK_ON_SW_CTL_SHFT                         0x4
#define HWIO_MCCC_SW_OVERRIDE1_GCC_SRC0_CLK_ON_BMSK                                0x2
#define HWIO_MCCC_SW_OVERRIDE1_GCC_SRC0_CLK_ON_SHFT                                0x1
#define HWIO_MCCC_SW_OVERRIDE1_GCC_SRC0_CLK_ON_SW_CTL_BMSK                         0x1
#define HWIO_MCCC_SW_OVERRIDE1_GCC_SRC0_CLK_ON_SW_CTL_SHFT                         0x0

#define HWIO_MCCC_TEST_CLOCK_CFG_ADDR                                       (MCCC_MCCC_MSTR_REG_BASE      + 0x00000270)
#define HWIO_MCCC_TEST_CLOCK_CFG_OFFS                                       (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000270)
#define HWIO_MCCC_TEST_CLOCK_CFG_RMSK                                              0x1
#define HWIO_MCCC_TEST_CLOCK_CFG_IN          \
        in_dword(HWIO_MCCC_TEST_CLOCK_CFG_ADDR)
#define HWIO_MCCC_TEST_CLOCK_CFG_INM(m)      \
        in_dword_masked(HWIO_MCCC_TEST_CLOCK_CFG_ADDR, m)
#define HWIO_MCCC_TEST_CLOCK_CFG_OUT(v)      \
        out_dword(HWIO_MCCC_TEST_CLOCK_CFG_ADDR,v)
#define HWIO_MCCC_TEST_CLOCK_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MCCC_TEST_CLOCK_CFG_ADDR,m,v,HWIO_MCCC_TEST_CLOCK_CFG_IN)
#define HWIO_MCCC_TEST_CLOCK_CFG_MCCC_CLK_ENABLE_BMSK                              0x1
#define HWIO_MCCC_TEST_CLOCK_CFG_MCCC_CLK_ENABLE_SHFT                              0x0
#define HWIO_MCCC_TEST_CLOCK_CFG_MCCC_CLK_ENABLE_DISABLE_FVAL                      0x0
#define HWIO_MCCC_TEST_CLOCK_CFG_MCCC_CLK_ENABLE_ENABLE_FVAL                       0x1

#define HWIO_MCCC_CRG_STATUS_ADDR                                           (MCCC_MCCC_MSTR_REG_BASE      + 0x00000280)
#define HWIO_MCCC_CRG_STATUS_OFFS                                           (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000280)
#define HWIO_MCCC_CRG_STATUS_RMSK                                              0x11111
#define HWIO_MCCC_CRG_STATUS_IN          \
        in_dword(HWIO_MCCC_CRG_STATUS_ADDR)
#define HWIO_MCCC_CRG_STATUS_INM(m)      \
        in_dword_masked(HWIO_MCCC_CRG_STATUS_ADDR, m)
#define HWIO_MCCC_CRG_STATUS_MCCC_CLK_ON_BMSK                                  0x10000
#define HWIO_MCCC_CRG_STATUS_MCCC_CLK_ON_SHFT                                     0x10
#define HWIO_MCCC_CRG_STATUS_MCCC_XO_CLK_ON_BMSK                                0x1000
#define HWIO_MCCC_CRG_STATUS_MCCC_XO_CLK_ON_SHFT                                   0xc
#define HWIO_MCCC_CRG_STATUS_GCC_SRC1_CLK_ON_BMSK                                0x100
#define HWIO_MCCC_CRG_STATUS_GCC_SRC1_CLK_ON_SHFT                                  0x8
#define HWIO_MCCC_CRG_STATUS_GCC_SRC0_CLK_ON_BMSK                                 0x10
#define HWIO_MCCC_CRG_STATUS_GCC_SRC0_CLK_ON_SHFT                                  0x4
#define HWIO_MCCC_CRG_STATUS_MCCC_CGC_CLK_EN_BMSK                                  0x1
#define HWIO_MCCC_CRG_STATUS_MCCC_CGC_CLK_EN_SHFT                                  0x0

#define HWIO_MCCC_FSC_STATUS0_ADDR                                          (MCCC_MCCC_MSTR_REG_BASE      + 0x00000288)
#define HWIO_MCCC_FSC_STATUS0_OFFS                                          (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000288)
#define HWIO_MCCC_FSC_STATUS0_RMSK                                          0x1001001f
#define HWIO_MCCC_FSC_STATUS0_IN          \
        in_dword(HWIO_MCCC_FSC_STATUS0_ADDR)
#define HWIO_MCCC_FSC_STATUS0_INM(m)      \
        in_dword_masked(HWIO_MCCC_FSC_STATUS0_ADDR, m)
#define HWIO_MCCC_FSC_STATUS0_STATE_BPT_HOLD_BMSK                           0x10000000
#define HWIO_MCCC_FSC_STATUS0_STATE_BPT_HOLD_SHFT                                 0x1c
#define HWIO_MCCC_FSC_STATUS0_STATE_BPT_MATCH_BMSK                             0x10000
#define HWIO_MCCC_FSC_STATUS0_STATE_BPT_MATCH_SHFT                                0x10
#define HWIO_MCCC_FSC_STATUS0_STATE_BPT_BMSK                                      0x1f
#define HWIO_MCCC_FSC_STATUS0_STATE_BPT_SHFT                                       0x0

#define HWIO_MCCC_FSC_STATUS1_ADDR                                          (MCCC_MCCC_MSTR_REG_BASE      + 0x0000028c)
#define HWIO_MCCC_FSC_STATUS1_OFFS                                          (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x0000028c)
#define HWIO_MCCC_FSC_STATUS1_RMSK                                          0x1f111117
#define HWIO_MCCC_FSC_STATUS1_IN          \
        in_dword(HWIO_MCCC_FSC_STATUS1_ADDR)
#define HWIO_MCCC_FSC_STATUS1_INM(m)      \
        in_dword_masked(HWIO_MCCC_FSC_STATUS1_ADDR, m)
#define HWIO_MCCC_FSC_STATUS1_FREQ_SWITCH_DISABLE_BMSK                      0x10000000
#define HWIO_MCCC_FSC_STATUS1_FREQ_SWITCH_DISABLE_SHFT                            0x1c
#define HWIO_MCCC_FSC_STATUS1_CHANNEL_DISABLE_BMSK                           0xf000000
#define HWIO_MCCC_FSC_STATUS1_CHANNEL_DISABLE_SHFT                                0x18
#define HWIO_MCCC_FSC_STATUS1_FAST_FREQ_SWITCH_MATCH_BMSK                     0x100000
#define HWIO_MCCC_FSC_STATUS1_FAST_FREQ_SWITCH_MATCH_SHFT                         0x14
#define HWIO_MCCC_FSC_STATUS1_FIRST_FREQ_SWITCH_MATCH_BMSK                     0x10000
#define HWIO_MCCC_FSC_STATUS1_FIRST_FREQ_SWITCH_MATCH_SHFT                        0x10
#define HWIO_MCCC_FSC_STATUS1_PREV_MUX_POL_BMSK                                 0x1000
#define HWIO_MCCC_FSC_STATUS1_PREV_MUX_POL_SHFT                                    0xc
#define HWIO_MCCC_FSC_STATUS1_MUX_POL_BMSK                                       0x100
#define HWIO_MCCC_FSC_STATUS1_MUX_POL_SHFT                                         0x8
#define HWIO_MCCC_FSC_STATUS1_FREQ_SWITCH_CLR_BMSK                                0x10
#define HWIO_MCCC_FSC_STATUS1_FREQ_SWITCH_CLR_SHFT                                 0x4
#define HWIO_MCCC_FSC_STATUS1_FREQ_SWITCH_ACTIVE_BMSK                              0x7
#define HWIO_MCCC_FSC_STATUS1_FREQ_SWITCH_ACTIVE_SHFT                              0x0

#define HWIO_MCCC_FSC_STATUS2_ADDR                                          (MCCC_MCCC_MSTR_REG_BASE      + 0x00000290)
#define HWIO_MCCC_FSC_STATUS2_OFFS                                          (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000290)
#define HWIO_MCCC_FSC_STATUS2_RMSK                                          0x30111111
#define HWIO_MCCC_FSC_STATUS2_IN          \
        in_dword(HWIO_MCCC_FSC_STATUS2_ADDR)
#define HWIO_MCCC_FSC_STATUS2_INM(m)      \
        in_dword_masked(HWIO_MCCC_FSC_STATUS2_ADDR, m)
#define HWIO_MCCC_FSC_STATUS2_TASK_MASK_CFG1_VALID_BMSK                     0x20000000
#define HWIO_MCCC_FSC_STATUS2_TASK_MASK_CFG1_VALID_SHFT                           0x1d
#define HWIO_MCCC_FSC_STATUS2_TASK_MASK_CFG0_VALID_BMSK                     0x10000000
#define HWIO_MCCC_FSC_STATUS2_TASK_MASK_CFG0_VALID_SHFT                           0x1c
#define HWIO_MCCC_FSC_STATUS2_STE_CH3_ACK_BMSK                                0x100000
#define HWIO_MCCC_FSC_STATUS2_STE_CH3_ACK_SHFT                                    0x14
#define HWIO_MCCC_FSC_STATUS2_STE_CH2_ACK_BMSK                                 0x10000
#define HWIO_MCCC_FSC_STATUS2_STE_CH2_ACK_SHFT                                    0x10
#define HWIO_MCCC_FSC_STATUS2_STE_CH1_ACK_BMSK                                  0x1000
#define HWIO_MCCC_FSC_STATUS2_STE_CH1_ACK_SHFT                                     0xc
#define HWIO_MCCC_FSC_STATUS2_STE_CH0_ACK_BMSK                                   0x100
#define HWIO_MCCC_FSC_STATUS2_STE_CH0_ACK_SHFT                                     0x8
#define HWIO_MCCC_FSC_STATUS2_STE_CLR_BMSK                                        0x10
#define HWIO_MCCC_FSC_STATUS2_STE_CLR_SHFT                                         0x4
#define HWIO_MCCC_FSC_STATUS2_STE_ACTIVE_BMSK                                      0x1
#define HWIO_MCCC_FSC_STATUS2_STE_ACTIVE_SHFT                                      0x0

#define HWIO_MCCC_FSC_STATUS3_ADDR                                          (MCCC_MCCC_MSTR_REG_BASE      + 0x00000294)
#define HWIO_MCCC_FSC_STATUS3_OFFS                                          (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000294)
#define HWIO_MCCC_FSC_STATUS3_RMSK                                             0x1ffff
#define HWIO_MCCC_FSC_STATUS3_IN          \
        in_dword(HWIO_MCCC_FSC_STATUS3_ADDR)
#define HWIO_MCCC_FSC_STATUS3_INM(m)      \
        in_dword_masked(HWIO_MCCC_FSC_STATUS3_ADDR, m)
#define HWIO_MCCC_FSC_STATUS3_BAND_CFG0_BMSK                                   0x1ffff
#define HWIO_MCCC_FSC_STATUS3_BAND_CFG0_SHFT                                       0x0

#define HWIO_MCCC_FSC_STATUS4_ADDR                                          (MCCC_MCCC_MSTR_REG_BASE      + 0x00000298)
#define HWIO_MCCC_FSC_STATUS4_OFFS                                          (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x00000298)
#define HWIO_MCCC_FSC_STATUS4_RMSK                                             0x1ffff
#define HWIO_MCCC_FSC_STATUS4_IN          \
        in_dword(HWIO_MCCC_FSC_STATUS4_ADDR)
#define HWIO_MCCC_FSC_STATUS4_INM(m)      \
        in_dword_masked(HWIO_MCCC_FSC_STATUS4_ADDR, m)
#define HWIO_MCCC_FSC_STATUS4_PREV_BAND_CFG0_BMSK                              0x1ffff
#define HWIO_MCCC_FSC_STATUS4_PREV_BAND_CFG0_SHFT                                  0x0

#define HWIO_MCCC_FSC_STATUS5_ADDR                                          (MCCC_MCCC_MSTR_REG_BASE      + 0x0000029c)
#define HWIO_MCCC_FSC_STATUS5_OFFS                                          (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x0000029c)
#define HWIO_MCCC_FSC_STATUS5_RMSK                                             0x1ffff
#define HWIO_MCCC_FSC_STATUS5_IN          \
        in_dword(HWIO_MCCC_FSC_STATUS5_ADDR)
#define HWIO_MCCC_FSC_STATUS5_INM(m)      \
        in_dword_masked(HWIO_MCCC_FSC_STATUS5_ADDR, m)
#define HWIO_MCCC_FSC_STATUS5_PERIOD_BMSK                                      0x1ffff
#define HWIO_MCCC_FSC_STATUS5_PERIOD_SHFT                                          0x0

#define HWIO_MCCC_FSC_STATUS6_ADDR                                          (MCCC_MCCC_MSTR_REG_BASE      + 0x000002a0)
#define HWIO_MCCC_FSC_STATUS6_OFFS                                          (MCCC_MCCC_MSTR_REG_BASE_OFFS + 0x000002a0)
#define HWIO_MCCC_FSC_STATUS6_RMSK                                             0x1ffff
#define HWIO_MCCC_FSC_STATUS6_IN          \
        in_dword(HWIO_MCCC_FSC_STATUS6_ADDR)
#define HWIO_MCCC_FSC_STATUS6_INM(m)      \
        in_dword_masked(HWIO_MCCC_FSC_STATUS6_ADDR, m)
#define HWIO_MCCC_FSC_STATUS6_PREV_PERIOD_BMSK                                 0x1ffff
#define HWIO_MCCC_FSC_STATUS6_PREV_PERIOD_SHFT                                     0x0

/*----------------------------------------------------------------------------
 * MODULE: SHRM_CSR_SHRM_CSR
 *--------------------------------------------------------------------------*/

#define SHRM_CSR_SHRM_CSR_REG_BASE                                                                 (DDR_SS_BASE      + 0x00050000)
#define SHRM_CSR_SHRM_CSR_REG_BASE_SIZE                                                            0x2000
#define SHRM_CSR_SHRM_CSR_REG_BASE_USED                                                            0x1088
#define SHRM_CSR_SHRM_CSR_REG_BASE_OFFS                                                            0x00050000

#define HWIO_SHRM_CSR_HW_INFO_ADDR                                                                 (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000000)
#define HWIO_SHRM_CSR_HW_INFO_OFFS                                                                 (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000000)
#define HWIO_SHRM_CSR_HW_INFO_RMSK                                                                 0xffffffff
#define HWIO_SHRM_CSR_HW_INFO_IN          \
        in_dword(HWIO_SHRM_CSR_HW_INFO_ADDR)
#define HWIO_SHRM_CSR_HW_INFO_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_HW_INFO_ADDR, m)
#define HWIO_SHRM_CSR_HW_INFO_MAJOR_REVISION_BMSK                                                  0xff000000
#define HWIO_SHRM_CSR_HW_INFO_MAJOR_REVISION_SHFT                                                        0x18
#define HWIO_SHRM_CSR_HW_INFO_BRANCH_REVISION_BMSK                                                   0xff0000
#define HWIO_SHRM_CSR_HW_INFO_BRANCH_REVISION_SHFT                                                       0x10
#define HWIO_SHRM_CSR_HW_INFO_MINOR_REVISION_BMSK                                                      0xff00
#define HWIO_SHRM_CSR_HW_INFO_MINOR_REVISION_SHFT                                                         0x8
#define HWIO_SHRM_CSR_HW_INFO_ECO_REVISION_BMSK                                                          0xff
#define HWIO_SHRM_CSR_HW_INFO_ECO_REVISION_SHFT                                                           0x0

#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_ADDR                                                  (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000004)
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_OFFS                                                  (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000004)
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_RMSK                                                     0x11111
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_ADDR)
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_ADDR,m,v,HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_IN)
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_GLOBAL_CGC_BMSK                                          0x10000
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_GLOBAL_CGC_SHFT                                             0x10
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_GLOBAL_CGC_DISABLE_FVAL                                      0x0
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_GLOBAL_CGC_ENABLE_FVAL                                       0x1
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_IRAM_BMSK                                                 0x1000
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_IRAM_SHFT                                                    0xc
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_IRAM_DISABLE_FVAL                                            0x0
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_IRAM_ENABLE_FVAL                                             0x1
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_DRAM_BMSK                                                  0x100
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_DRAM_SHFT                                                    0x8
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_DRAM_DISABLE_FVAL                                            0x0
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_DRAM_ENABLE_FVAL                                             0x1
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_SPROC_BMSK                                                  0x10
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_SPROC_SHFT                                                   0x4
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_SPROC_DISABLE_FVAL                                           0x0
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_SPROC_ENABLE_FVAL                                            0x1
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_RCI_BMSK                                                     0x1
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_RCI_SHFT                                                     0x0
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_RCI_DISABLE_FVAL                                             0x0
#define HWIO_SHRM_CSR_SHRM_CGC_OVERRIDE_CTRL_RCI_ENABLE_FVAL                                              0x1

#define HWIO_SHRM_CSR_SHRM_SPROC_STATUS_ADDR                                                       (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000008)
#define HWIO_SHRM_CSR_SHRM_SPROC_STATUS_OFFS                                                       (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000008)
#define HWIO_SHRM_CSR_SHRM_SPROC_STATUS_RMSK                                                              0x1
#define HWIO_SHRM_CSR_SHRM_SPROC_STATUS_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_SPROC_STATUS_ADDR)
#define HWIO_SHRM_CSR_SHRM_SPROC_STATUS_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_SPROC_STATUS_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_SPROC_STATUS_STATE_BMSK                                                        0x1
#define HWIO_SHRM_CSR_SHRM_SPROC_STATUS_STATE_SHFT                                                        0x0
#define HWIO_SHRM_CSR_SHRM_SPROC_STATUS_STATE_RUN_STATE_FVAL                                              0x0
#define HWIO_SHRM_CSR_SHRM_SPROC_STATUS_STATE_WAITI_STATE_FVAL                                            0x1

#define HWIO_SHRM_CSR_SHRM_SW_LOGGING_ADDR                                                         (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x0000000c)
#define HWIO_SHRM_CSR_SHRM_SW_LOGGING_OFFS                                                         (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x0000000c)
#define HWIO_SHRM_CSR_SHRM_SW_LOGGING_RMSK                                                         0xffffffff
#define HWIO_SHRM_CSR_SHRM_SW_LOGGING_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_SW_LOGGING_ADDR)
#define HWIO_SHRM_CSR_SHRM_SW_LOGGING_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_SW_LOGGING_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_SW_LOGGING_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_SW_LOGGING_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_SW_LOGGING_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_SW_LOGGING_ADDR,m,v,HWIO_SHRM_CSR_SHRM_SW_LOGGING_IN)
#define HWIO_SHRM_CSR_SHRM_SW_LOGGING_VALUE_BMSK                                                   0xffffffff
#define HWIO_SHRM_CSR_SHRM_SW_LOGGING_VALUE_SHFT                                                          0x0

#define HWIO_SHRM_CSR_SHRM_RSI_PATH_ADDR                                                           (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000010)
#define HWIO_SHRM_CSR_SHRM_RSI_PATH_OFFS                                                           (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000010)
#define HWIO_SHRM_CSR_SHRM_RSI_PATH_RMSK                                                                  0x1
#define HWIO_SHRM_CSR_SHRM_RSI_PATH_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_RSI_PATH_ADDR)
#define HWIO_SHRM_CSR_SHRM_RSI_PATH_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_RSI_PATH_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_RSI_PATH_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_RSI_PATH_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_RSI_PATH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_RSI_PATH_ADDR,m,v,HWIO_SHRM_CSR_SHRM_RSI_PATH_IN)
#define HWIO_SHRM_CSR_SHRM_RSI_PATH_SEL_BMSK                                                              0x1
#define HWIO_SHRM_CSR_SHRM_RSI_PATH_SEL_SHFT                                                              0x0
#define HWIO_SHRM_CSR_SHRM_RSI_PATH_SEL_RSI_OVERRIDE_PATH_FVAL                                            0x0
#define HWIO_SHRM_CSR_SHRM_RSI_PATH_SEL_RSI_PATH_FVAL                                                     0x1

#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_EN_ADDR                                                   (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000020)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_EN_OFFS                                                   (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000020)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_EN_RMSK                                                          0x1
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_EN_IN          \
        in_dword(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_EN_ADDR)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_EN_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_EN_ADDR, m)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_EN_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_EN_ADDR,v)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_EN_ADDR,m,v,HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_EN_IN)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_EN_EN_BMSK                                                       0x1
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_EN_EN_SHFT                                                       0x0
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_EN_EN_DISABLE_FVAL                                               0x0
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_EN_EN_ENABLE_FVAL                                                0x1

#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_TRIGGER_ADDR                                              (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000024)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_TRIGGER_OFFS                                              (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000024)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_TRIGGER_RMSK                                                     0x1
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_TRIGGER_IN          \
        in_dword(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_TRIGGER_ADDR)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_TRIGGER_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_TRIGGER_ADDR, m)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_TRIGGER_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_TRIGGER_ADDR,v)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_TRIGGER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_TRIGGER_ADDR,m,v,HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_TRIGGER_IN)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_TRIGGER_TRIGGER_BMSK                                             0x1
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_TRIGGER_TRIGGER_SHFT                                             0x0
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_TRIGGER_TRIGGER_CLR_FVAL                                         0x0
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_TRIGGER_TRIGGER_SET_FVAL                                         0x1

#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_CMD_ADDR                                                  (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000028)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_CMD_OFFS                                                  (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000028)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_CMD_RMSK                                                  0xffffffff
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_CMD_IN          \
        in_dword(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_CMD_ADDR)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_CMD_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_CMD_ADDR, m)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_CMD_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_CMD_ADDR,v)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_CMD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_CMD_ADDR,m,v,HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_CMD_IN)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_CMD_CMD_PAYLOAD_BMSK                                      0xffffffff
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_CMD_CMD_PAYLOAD_SHFT                                             0x0

#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_STATUS_ADDR                                               (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x0000001c)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_STATUS_OFFS                                               (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x0000001c)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_STATUS_RMSK                                                      0x1
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_STATUS_IN          \
        in_dword(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_STATUS_ADDR)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_STATUS_ADDR, m)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_STATUS_STATUS_BMSK                                               0x1
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_STATUS_STATUS_SHFT                                               0x0
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_STATUS_STATUS_COMPLETED_FVAL                                     0x0
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_STATUS_STATUS_PROCESSING_FVAL                                    0x1

#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_RESPONSE_ADDR                                             (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x0000002c)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_RESPONSE_OFFS                                             (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x0000002c)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_RESPONSE_RMSK                                             0xffffffff
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_RESPONSE_IN          \
        in_dword(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_RESPONSE_ADDR)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_RESPONSE_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_RESPONSE_ADDR, m)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_RESPONSE_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_RESPONSE_ADDR,v)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_RESPONSE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_RESPONSE_ADDR,m,v,HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_RESPONSE_IN)
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_RESPONSE_RSP_PAYLOAD_BMSK                                 0xffffffff
#define HWIO_SHRM_CSR_AOP2SHRM_INTERRUPT_RESPONSE_RSP_PAYLOAD_SHFT                                        0x0

#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_EN_ADDR                                                   (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000040)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_EN_OFFS                                                   (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000040)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_EN_RMSK                                                          0x1
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_EN_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_EN_ADDR)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_EN_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_EN_ADDR, m)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_EN_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_EN_ADDR,v)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_EN_ADDR,m,v,HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_EN_IN)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_EN_EN_BMSK                                                       0x1
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_EN_EN_SHFT                                                       0x0
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_EN_EN_DISABLE_FVAL                                               0x0
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_EN_EN_ENABLE_FVAL                                                0x1

#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_TRIGGER_ADDR                                              (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000044)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_TRIGGER_OFFS                                              (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000044)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_TRIGGER_RMSK                                                     0x1
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_TRIGGER_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_TRIGGER_ADDR)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_TRIGGER_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_TRIGGER_ADDR, m)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_TRIGGER_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_TRIGGER_ADDR,v)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_TRIGGER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_TRIGGER_ADDR,m,v,HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_TRIGGER_IN)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_TRIGGER_TRIGGER_BMSK                                             0x1
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_TRIGGER_TRIGGER_SHFT                                             0x0
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_TRIGGER_TRIGGER_CLR_FVAL                                         0x0
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_TRIGGER_TRIGGER_SET_FVAL                                         0x1

#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_CMD_ADDR                                                  (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000048)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_CMD_OFFS                                                  (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000048)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_CMD_RMSK                                                  0xffffffff
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_CMD_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_CMD_ADDR)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_CMD_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_CMD_ADDR, m)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_CMD_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_CMD_ADDR,v)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_CMD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_CMD_ADDR,m,v,HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_CMD_IN)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_CMD_CMD_PAYLOAD_BMSK                                      0xffffffff
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_CMD_CMD_PAYLOAD_SHFT                                             0x0

#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_STATUS_ADDR                                               (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000050)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_STATUS_OFFS                                               (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000050)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_STATUS_RMSK                                                      0x1
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_STATUS_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_STATUS_ADDR)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_STATUS_ADDR, m)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_STATUS_STATUS_BMSK                                               0x1
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_STATUS_STATUS_SHFT                                               0x0
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_STATUS_STATUS_COMPLETED_FVAL                                     0x0
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_STATUS_STATUS_PROCESSING_FVAL                                    0x1

#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_RESPONSE_ADDR                                             (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x0000004c)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_RESPONSE_OFFS                                             (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x0000004c)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_RESPONSE_RMSK                                             0xffffffff
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_RESPONSE_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_RESPONSE_ADDR)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_RESPONSE_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_RESPONSE_ADDR, m)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_RESPONSE_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_RESPONSE_ADDR,v)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_RESPONSE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_RESPONSE_ADDR,m,v,HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_RESPONSE_IN)
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_RESPONSE_RSP_PAYLOAD_BMSK                                 0xffffffff
#define HWIO_SHRM_CSR_SHRM2AOP_INTERRUPT_RESPONSE_RSP_PAYLOAD_SHFT                                        0x0

#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_EN_ADDR                                               (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000060)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_EN_OFFS                                               (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000060)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_EN_RMSK                                                      0x1
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_EN_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_EN_ADDR)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_EN_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_EN_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_EN_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_EN_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_EN_ADDR,m,v,HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_EN_IN)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_EN_EN_BMSK                                                   0x1
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_EN_EN_SHFT                                                   0x0
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_EN_EN_DISABLE_FVAL                                           0x0
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_EN_EN_ENABLE_FVAL                                            0x1

#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_TRIGGER_ADDR                                          (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000064)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_TRIGGER_OFFS                                          (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000064)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_TRIGGER_RMSK                                                 0x1
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_TRIGGER_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_TRIGGER_ADDR)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_TRIGGER_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_TRIGGER_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_TRIGGER_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_TRIGGER_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_TRIGGER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_TRIGGER_ADDR,m,v,HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_TRIGGER_IN)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_TRIGGER_TRIGGER_BMSK                                         0x1
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_TRIGGER_TRIGGER_SHFT                                         0x0
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_TRIGGER_TRIGGER_CLR_FVAL                                     0x0
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_TRIGGER_TRIGGER_SET_FVAL                                     0x1

#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_CMD_ADDR                                              (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000068)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_CMD_OFFS                                              (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000068)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_CMD_RMSK                                              0xffffffff
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_CMD_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_CMD_ADDR)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_CMD_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_CMD_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_CMD_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_CMD_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_CMD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_CMD_ADDR,m,v,HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_CMD_IN)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_CMD_CMD_PAYLOAD_BMSK                                  0xffffffff
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_CMD_CMD_PAYLOAD_SHFT                                         0x0

#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_RESPONSE_ADDR                                         (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x0000006c)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_RESPONSE_OFFS                                         (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x0000006c)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_RESPONSE_RMSK                                         0xffffffff
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_RESPONSE_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_RESPONSE_ADDR)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_RESPONSE_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_RESPONSE_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_RESPONSE_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_RESPONSE_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_RESPONSE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_RESPONSE_ADDR,m,v,HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_RESPONSE_IN)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_RESPONSE_RSP_PAYLOAD_BMSK                             0xffffffff
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_RESPONSE_RSP_PAYLOAD_SHFT                                    0x0

#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_STATUS_ADDR                                           (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000070)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_STATUS_OFFS                                           (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000070)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_STATUS_RMSK                                                  0x1
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_STATUS_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_STATUS_ADDR)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_STATUS_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_STATUS_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_STATUS_STATUS_BMSK                                           0x1
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_STATUS_STATUS_SHFT                                           0x0
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_STATUS_STATUS_COMPLETED_FVAL                                 0x0
#define HWIO_SHRM_CSR_SHRM_RPM_PORT_OVERRIDE_STATUS_STATUS_PROCESSING_FVAL                                0x1

#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_CTRL_ADDR                                                     (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000074)
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_CTRL_OFFS                                                     (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000074)
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_CTRL_RMSK                                                            0x1
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_CTRL_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_APB_DEBUG_CTRL_ADDR)
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_CTRL_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_APB_DEBUG_CTRL_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_CTRL_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_APB_DEBUG_CTRL_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_APB_DEBUG_CTRL_ADDR,m,v,HWIO_SHRM_CSR_SHRM_APB_DEBUG_CTRL_IN)
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_CTRL_EN_BMSK                                                         0x1
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_CTRL_EN_SHFT                                                         0x0
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_CTRL_EN_DISABLE_FVAL                                                 0x0
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_CTRL_EN_ENSABLE_FVAL                                                 0x1

#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_STATUS_ADDR                                                   (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000078)
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_STATUS_OFFS                                                   (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000078)
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_STATUS_RMSK                                                     0xffffff
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_STATUS_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_APB_DEBUG_STATUS_ADDR)
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_STATUS_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_APB_DEBUG_STATUS_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_STATUS_STATUS_BMSK                                              0xff0000
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_STATUS_STATUS_SHFT                                                  0x10
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_STATUS_PC_BMSK                                                    0xffff
#define HWIO_SHRM_CSR_SHRM_APB_DEBUG_STATUS_PC_SHFT                                                       0x0

#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_ADDR(n)                                             (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000080 + 0x4 * (n))
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_OFFS(n)                                             (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000080 + 0x4 * (n))
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_RMSK                                                     0x101
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_MAXn                                                         1
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_INI(n)        \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_ADDR(n), HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_RMSK)
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_INMI(n,mask)    \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_ADDR(n), mask)
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_OUTI(n,val)    \
        out_dword(HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_ADDR(n),val)
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_ADDR(n),mask,val,HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_INI(n))
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_CLR_BMSK                                                 0x100
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_CLR_SHFT                                                   0x8
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_RUN_STOP_BMSK                                              0x1
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTL_RUN_STOP_SHFT                                              0x0

#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTR_ADDR(n)                                             (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000090 + 0x4 * (n))
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTR_OFFS(n)                                             (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000090 + 0x4 * (n))
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTR_RMSK                                                0xffffffff
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTR_MAXn                                                         1
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTR_INI(n)        \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTR_ADDR(n), HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTR_RMSK)
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTR_INMI(n,mask)    \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTR_ADDR(n), mask)
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTR_VALUE_BMSK                                          0xffffffff
#define HWIO_SHRM_CSR_SHRM_PERF_COUNTER_n_CNTR_VALUE_SHFT                                                 0x0

#define HWIO_SHRM_CSR_SHRM_QOS_ENCODING_ADDR                                                       (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x000000a0)
#define HWIO_SHRM_CSR_SHRM_QOS_ENCODING_OFFS                                                       (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x000000a0)
#define HWIO_SHRM_CSR_SHRM_QOS_ENCODING_RMSK                                                       0xffffffff
#define HWIO_SHRM_CSR_SHRM_QOS_ENCODING_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_QOS_ENCODING_ADDR)
#define HWIO_SHRM_CSR_SHRM_QOS_ENCODING_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_ENCODING_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_QOS_ENCODING_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_QOS_ENCODING_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_QOS_ENCODING_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_QOS_ENCODING_ADDR,m,v,HWIO_SHRM_CSR_SHRM_QOS_ENCODING_IN)
#define HWIO_SHRM_CSR_SHRM_QOS_ENCODING_ACV_CTRL_BMSK                                              0xff000000
#define HWIO_SHRM_CSR_SHRM_QOS_ENCODING_ACV_CTRL_SHFT                                                    0x18
#define HWIO_SHRM_CSR_SHRM_QOS_ENCODING_ALC_CTRL_BMSK                                                0xff0000
#define HWIO_SHRM_CSR_SHRM_QOS_ENCODING_ALC_CTRL_SHFT                                                    0x10
#define HWIO_SHRM_CSR_SHRM_QOS_ENCODING_ACV_BMSK                                                       0xff00
#define HWIO_SHRM_CSR_SHRM_QOS_ENCODING_ACV_SHFT                                                          0x8
#define HWIO_SHRM_CSR_SHRM_QOS_ENCODING_ALC_BMSK                                                         0xff
#define HWIO_SHRM_CSR_SHRM_QOS_ENCODING_ALC_SHFT                                                          0x0

#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_ADDR                                         (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x000000a4)
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_OFFS                                         (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x000000a4)
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_RMSK                                          0x1ffffff
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_ADDR)
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_ADDR,m,v,HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_IN)
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_PHY_POLICY_OVERRIDE_VALUE_BMSK                0x1e00000
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_PHY_POLICY_OVERRIDE_VALUE_SHFT                     0x15
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_THROTTLE_POLICY_OVERRIDE_VALUE_BMSK            0x1e0000
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_THROTTLE_POLICY_OVERRIDE_VALUE_SHFT                0x11
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_MEMNOC_POLICY_OVERRIDE_VALUE_BMSK               0x1e000
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_MEMNOC_POLICY_OVERRIDE_VALUE_SHFT                   0xd
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_MC_POLICY_OVERRIDE_VALUE_BMSK                    0x1e00
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_MC_POLICY_OVERRIDE_VALUE_SHFT                       0x9
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_LLCC_POLICY_OVERRIDE_VALUE_BMSK                   0x1e0
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_LLCC_POLICY_OVERRIDE_VALUE_SHFT                     0x5
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_PHY_POLICY_OVERRIDE_EN_BMSK                        0x10
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_PHY_POLICY_OVERRIDE_EN_SHFT                         0x4
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_THROTTLE_POLICY_OVERRIDE_EN_BMSK                    0x8
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_THROTTLE_POLICY_OVERRIDE_EN_SHFT                    0x3
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_MEMNOC_POLICY_OVERRIDE_EN_BMSK                      0x4
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_MEMNOC_POLICY_OVERRIDE_EN_SHFT                      0x2
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_MC_POLICY_OVERRIDE_EN_BMSK                          0x2
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_MC_POLICY_OVERRIDE_EN_SHFT                          0x1
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_LLCC_POLICY_OVERRIDE_EN_BMSK                        0x1
#define HWIO_SHRM_CSR_SHRM_QOS_OUTPUT_POLICY_OVERRIDE_LLCC_POLICY_OVERRIDE_EN_SHFT                        0x0

#define HWIO_SHRM_CSR_SHRM_CGC_THRESHOLD_CTRL_ADDR                                                 (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x000000b0)
#define HWIO_SHRM_CSR_SHRM_CGC_THRESHOLD_CTRL_OFFS                                                 (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x000000b0)
#define HWIO_SHRM_CSR_SHRM_CGC_THRESHOLD_CTRL_RMSK                                                   0xff00ff
#define HWIO_SHRM_CSR_SHRM_CGC_THRESHOLD_CTRL_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_CGC_THRESHOLD_CTRL_ADDR)
#define HWIO_SHRM_CSR_SHRM_CGC_THRESHOLD_CTRL_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_CGC_THRESHOLD_CTRL_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_CGC_THRESHOLD_CTRL_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_CGC_THRESHOLD_CTRL_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_CGC_THRESHOLD_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_CGC_THRESHOLD_CTRL_ADDR,m,v,HWIO_SHRM_CSR_SHRM_CGC_THRESHOLD_CTRL_IN)
#define HWIO_SHRM_CSR_SHRM_CGC_THRESHOLD_CTRL_SHRM_BMSK                                              0xff0000
#define HWIO_SHRM_CSR_SHRM_CGC_THRESHOLD_CTRL_SHRM_SHFT                                                  0x10
#define HWIO_SHRM_CSR_SHRM_CGC_THRESHOLD_CTRL_CFG_BMSK                                                   0xff
#define HWIO_SHRM_CSR_SHRM_CGC_THRESHOLD_CTRL_CFG_SHFT                                                    0x0

#define HWIO_SHRM_CSR_SCRATCH_n_REG_ADDR(n)                                                        (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000100 + 0x4 * (n))
#define HWIO_SHRM_CSR_SCRATCH_n_REG_OFFS(n)                                                        (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000100 + 0x4 * (n))
#define HWIO_SHRM_CSR_SCRATCH_n_REG_RMSK                                                           0xffffffff
#define HWIO_SHRM_CSR_SCRATCH_n_REG_MAXn                                                                   15
#define HWIO_SHRM_CSR_SCRATCH_n_REG_INI(n)        \
        in_dword_masked(HWIO_SHRM_CSR_SCRATCH_n_REG_ADDR(n), HWIO_SHRM_CSR_SCRATCH_n_REG_RMSK)
#define HWIO_SHRM_CSR_SCRATCH_n_REG_INMI(n,mask)    \
        in_dword_masked(HWIO_SHRM_CSR_SCRATCH_n_REG_ADDR(n), mask)
#define HWIO_SHRM_CSR_SCRATCH_n_REG_OUTI(n,val)    \
        out_dword(HWIO_SHRM_CSR_SCRATCH_n_REG_ADDR(n),val)
#define HWIO_SHRM_CSR_SCRATCH_n_REG_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SCRATCH_n_REG_ADDR(n),mask,val,HWIO_SHRM_CSR_SCRATCH_n_REG_INI(n))
#define HWIO_SHRM_CSR_SCRATCH_n_REG_DATA_BMSK                                                      0xffffffff
#define HWIO_SHRM_CSR_SCRATCH_n_REG_DATA_SHFT                                                             0x0

#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_ADDR(n,m)                                          (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000400 + 0x20 * (n) + 0x4 * (m))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_OFFS(n,m)                                          (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000400 + 0x20 * (n) + 0x4 * (m))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_RMSK                                               0x70000f0f
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_MAXn                                                       15
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_MAXm                                                        3
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_INI2(n,m)        \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_ADDR(n,m), HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_RMSK)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_INMI2(n,m,mask)    \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_ADDR(n,m), mask)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_OUTI2(n,m,val)    \
        out_dword(HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_ADDR(n,m),val)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_OUTMI2(n,m,mask,val) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_ADDR(n,m),mask,val,HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_INI2(n,m))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_OPERATION_BMSK                                     0x70000000
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_OPERATION_SHFT                                           0x1c
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_MASK_BMSK                                               0xf00
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_MASK_SHFT                                                 0x8
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_MATCH_BMSK                                                0xf
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_LUTm_INPUT_MATCH_SHFT                                                0x0

#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_ADDR(n)                                  (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000800 + 0x4 * (n))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_OFFS(n)                                  (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000800 + 0x4 * (n))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_RMSK                                        0xf030f
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_MAXn                                             15
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_INI(n)        \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_ADDR(n), HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_RMSK)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_INMI(n,mask)    \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_ADDR(n), mask)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_OUTI(n,val)    \
        out_dword(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_ADDR(n),val)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_ADDR(n),mask,val,HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_INI(n))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_POLICY_BMSK                                 0xf0000
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_POLICY_SHFT                                    0x10
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_MODE_BMSK                                     0x300
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_MODE_SHFT                                       0x8
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_VALUE_BMSK                                      0xf
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_THROTTLE_CNTL_VALUE_SHFT                                      0x0

#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_ADDR(n)                                    (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000840 + 0x4 * (n))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_OFFS(n)                                    (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000840 + 0x4 * (n))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_RMSK                                          0xf030f
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_MAXn                                               15
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_INI(n)        \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_ADDR(n), HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_RMSK)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_INMI(n,mask)    \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_ADDR(n), mask)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_OUTI(n,val)    \
        out_dword(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_ADDR(n),val)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_ADDR(n),mask,val,HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_INI(n))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_POLICY_BMSK                                   0xf0000
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_POLICY_SHFT                                      0x10
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_MODE_BMSK                                       0x300
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_MODE_SHFT                                         0x8
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_VALUE_BMSK                                        0xf
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MEMNOC_CNTL_VALUE_SHFT                                        0x0

#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_ADDR(n)                                        (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000880 + 0x4 * (n))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_OFFS(n)                                        (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000880 + 0x4 * (n))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_RMSK                                              0xf030f
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_MAXn                                                   15
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_INI(n)        \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_ADDR(n), HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_RMSK)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_INMI(n,mask)    \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_ADDR(n), mask)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_OUTI(n,val)    \
        out_dword(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_ADDR(n),val)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_ADDR(n),mask,val,HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_INI(n))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_POLICY_BMSK                                       0xf0000
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_POLICY_SHFT                                          0x10
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_MODE_BMSK                                           0x300
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_MODE_SHFT                                             0x8
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_VALUE_BMSK                                            0xf
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_MC_CNTL_VALUE_SHFT                                            0x0

#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_ADDR(n)                                      (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x000008c0 + 0x4 * (n))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_OFFS(n)                                      (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x000008c0 + 0x4 * (n))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_RMSK                                            0xf030f
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_MAXn                                                 15
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_INI(n)        \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_ADDR(n), HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_RMSK)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_INMI(n,mask)    \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_ADDR(n), mask)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_OUTI(n,val)    \
        out_dword(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_ADDR(n),val)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_ADDR(n),mask,val,HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_INI(n))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_POLICY_BMSK                                     0xf0000
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_POLICY_SHFT                                        0x10
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_MODE_BMSK                                         0x300
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_MODE_SHFT                                           0x8
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_VALUE_BMSK                                          0xf
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_LLCC_CNTL_VALUE_SHFT                                          0x0

#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_ADDR(n)                                       (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000900 + 0x4 * (n))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_OFFS(n)                                       (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000900 + 0x4 * (n))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_RMSK                                             0xf030f
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_MAXn                                                  15
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_INI(n)        \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_ADDR(n), HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_RMSK)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_INMI(n,mask)    \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_ADDR(n), mask)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_OUTI(n,val)    \
        out_dword(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_ADDR(n),val)
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_ADDR(n),mask,val,HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_INI(n))
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_POLICY_BMSK                                      0xf0000
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_POLICY_SHFT                                         0x10
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_MODE_BMSK                                          0x300
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_MODE_SHFT                                            0x8
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_VALUE_BMSK                                           0xf
#define HWIO_SHRM_CSR_SHRM_QOS_INSTn_OUTPUT_PHY_CNTL_VALUE_SHFT                                           0x0

#define HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_ADDR                                          (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000940)
#define HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_OFFS                                          (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000940)
#define HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_RMSK                                              0xff03
#define HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_ADDR)
#define HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_ADDR,m,v,HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_IN)
#define HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_ALC_INPUT_POLICY_OVERRIDE_VALUE_BMSK              0xf000
#define HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_ALC_INPUT_POLICY_OVERRIDE_VALUE_SHFT                 0xc
#define HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_ACV_INPUT_POLICY_OVERRIDE_VALUE_BMSK               0xf00
#define HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_ACV_INPUT_POLICY_OVERRIDE_VALUE_SHFT                 0x8
#define HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_ALC_INPUT_POLICY_OVERRIDE_EN_BMSK                    0x2
#define HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_ALC_INPUT_POLICY_OVERRIDE_EN_SHFT                    0x1
#define HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_ACV_INPUT_POLICY_OVERRIDE_EN_BMSK                    0x1
#define HWIO_SHRM_CSR_SHRM_QOS_INPUT_POLICY_OVERRIDE_ACV_INPUT_POLICY_OVERRIDE_EN_SHFT                    0x0

#define HWIO_SHRM_CSR_SHRM_QOS_MASKING_ADDR                                                        (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000944)
#define HWIO_SHRM_CSR_SHRM_QOS_MASKING_OFFS                                                        (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000944)
#define HWIO_SHRM_CSR_SHRM_QOS_MASKING_RMSK                                                        0xffffffff
#define HWIO_SHRM_CSR_SHRM_QOS_MASKING_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_QOS_MASKING_ADDR)
#define HWIO_SHRM_CSR_SHRM_QOS_MASKING_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_MASKING_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_QOS_MASKING_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_QOS_MASKING_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_QOS_MASKING_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_QOS_MASKING_ADDR,m,v,HWIO_SHRM_CSR_SHRM_QOS_MASKING_IN)
#define HWIO_SHRM_CSR_SHRM_QOS_MASKING_ACV_CTL_MASK_BMSK                                           0xff000000
#define HWIO_SHRM_CSR_SHRM_QOS_MASKING_ACV_CTL_MASK_SHFT                                                 0x18
#define HWIO_SHRM_CSR_SHRM_QOS_MASKING_ALC_CTL_MASK_BMSK                                             0xff0000
#define HWIO_SHRM_CSR_SHRM_QOS_MASKING_ALC_CTL_MASK_SHFT                                                 0x10
#define HWIO_SHRM_CSR_SHRM_QOS_MASKING_ACV_CMD_MASK_BMSK                                               0xff00
#define HWIO_SHRM_CSR_SHRM_QOS_MASKING_ACV_CMD_MASK_SHFT                                                  0x8
#define HWIO_SHRM_CSR_SHRM_QOS_MASKING_ALC_CMD_MASK_BMSK                                                 0xff
#define HWIO_SHRM_CSR_SHRM_QOS_MASKING_ALC_CMD_MASK_SHFT                                                  0x0

#define HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_ADDR                                                  (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000948)
#define HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_OFFS                                                  (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000948)
#define HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_RMSK                                                   0x1ffffe0
#define HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_ADDR)
#define HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_PHY_POLICY_STATUS_BMSK                                 0x1e00000
#define HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_PHY_POLICY_STATUS_SHFT                                      0x15
#define HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_THROTTLE_POLICY_STATUS_BMSK                             0x1e0000
#define HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_THROTTLE_POLICY_STATUS_SHFT                                 0x11
#define HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_MEMNOC_POLICY_STATUS_BMSK                                0x1e000
#define HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_MEMNOC_POLICY_STATUS_SHFT                                    0xd
#define HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_MC_POLICY_STATUS_BMSK                                     0x1e00
#define HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_MC_POLICY_STATUS_SHFT                                        0x9
#define HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_LLCC_POLICY_STATUS_BMSK                                    0x1e0
#define HWIO_SHRM_CSR_SHRM_QOS_POLICY_STATUS_LLCC_POLICY_STATUS_SHFT                                      0x5

#define HWIO_SHRM_CSR_SHRM_QOS_CTRL_ADDR                                                           (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x0000094c)
#define HWIO_SHRM_CSR_SHRM_QOS_CTRL_OFFS                                                           (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x0000094c)
#define HWIO_SHRM_CSR_SHRM_QOS_CTRL_RMSK                                                                  0x1
#define HWIO_SHRM_CSR_SHRM_QOS_CTRL_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_QOS_CTRL_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_QOS_CTRL_LOAD_PARAMETERS_BMSK                                                  0x1
#define HWIO_SHRM_CSR_SHRM_QOS_CTRL_LOAD_PARAMETERS_SHFT                                                  0x0

#define HWIO_SHRM_CSR_SHRM_SPROC_CTRL_ADDR                                                         (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00001000)
#define HWIO_SHRM_CSR_SHRM_SPROC_CTRL_OFFS                                                         (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00001000)
#define HWIO_SHRM_CSR_SHRM_SPROC_CTRL_RMSK                                                              0x101
#define HWIO_SHRM_CSR_SHRM_SPROC_CTRL_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_SPROC_CTRL_ADDR)
#define HWIO_SHRM_CSR_SHRM_SPROC_CTRL_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_SPROC_CTRL_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_SPROC_CTRL_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_SPROC_CTRL_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_SPROC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_SPROC_CTRL_ADDR,m,v,HWIO_SHRM_CSR_SHRM_SPROC_CTRL_IN)
#define HWIO_SHRM_CSR_SHRM_SPROC_CTRL_START_VEC_SEL_BMSK                                                0x100
#define HWIO_SHRM_CSR_SHRM_SPROC_CTRL_START_VEC_SEL_SHFT                                                  0x8
#define HWIO_SHRM_CSR_SHRM_SPROC_CTRL_RUN_STALL_BMSK                                                      0x1
#define HWIO_SHRM_CSR_SHRM_SPROC_CTRL_RUN_STALL_SHFT                                                      0x0

#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_EN_ADDR                                                  (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00001020)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_EN_OFFS                                                  (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00001020)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_EN_RMSK                                                         0x1
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_EN_IN          \
        in_dword(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_EN_ADDR)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_EN_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_EN_ADDR, m)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_EN_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_EN_ADDR,v)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_EN_ADDR,m,v,HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_EN_IN)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_EN_EN_BMSK                                                      0x1
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_EN_EN_SHFT                                                      0x0
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_EN_EN_DISABLE_FVAL                                              0x0
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_EN_EN_ENABLE_FVAL                                               0x1

#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_TRIGGER_ADDR                                             (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00001024)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_TRIGGER_OFFS                                             (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00001024)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_TRIGGER_RMSK                                                    0x1
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_TRIGGER_IN          \
        in_dword(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_TRIGGER_ADDR)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_TRIGGER_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_TRIGGER_ADDR, m)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_TRIGGER_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_TRIGGER_ADDR,v)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_TRIGGER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_TRIGGER_ADDR,m,v,HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_TRIGGER_IN)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_TRIGGER_TRIGGER_BMSK                                            0x1
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_TRIGGER_TRIGGER_SHFT                                            0x0
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_TRIGGER_TRIGGER_CLR_FVAL                                        0x0
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_TRIGGER_TRIGGER_SET_FVAL                                        0x1

#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_CMD_ADDR                                                 (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00001028)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_CMD_OFFS                                                 (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00001028)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_CMD_RMSK                                                 0xffffffff
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_CMD_IN          \
        in_dword(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_CMD_ADDR)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_CMD_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_CMD_ADDR, m)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_CMD_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_CMD_ADDR,v)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_CMD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_CMD_ADDR,m,v,HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_CMD_IN)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_CMD_CMD_PAYLOAD_BMSK                                     0xffffffff
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_CMD_CMD_PAYLOAD_SHFT                                            0x0

#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_STATUS_ADDR                                              (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00000030)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_STATUS_OFFS                                              (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00000030)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_STATUS_RMSK                                                     0x1
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_STATUS_IN          \
        in_dword(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_STATUS_ADDR)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_STATUS_ADDR, m)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_STATUS_STATUS_BMSK                                              0x1
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_STATUS_STATUS_SHFT                                              0x0
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_STATUS_STATUS_COMPLETED_FVAL                                    0x0
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_STATUS_STATUS_PROCESSING_FVAL                                   0x1

#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_RESPONSE_ADDR                                            (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x0000102c)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_RESPONSE_OFFS                                            (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x0000102c)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_RESPONSE_RMSK                                            0xffffffff
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_RESPONSE_IN          \
        in_dword(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_RESPONSE_ADDR)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_RESPONSE_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_RESPONSE_ADDR, m)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_RESPONSE_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_RESPONSE_ADDR,v)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_RESPONSE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_RESPONSE_ADDR,m,v,HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_RESPONSE_IN)
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_RESPONSE_RSP_PAYLOAD_BMSK                                0xffffffff
#define HWIO_SHRM_CSR_APPS2SHRM_INTERRUPT_RESPONSE_RSP_PAYLOAD_SHFT                                       0x0

#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_EN_ADDR                                                  (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00001040)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_EN_OFFS                                                  (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00001040)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_EN_RMSK                                                         0x1
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_EN_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_EN_ADDR)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_EN_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_EN_ADDR, m)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_EN_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_EN_ADDR,v)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_EN_ADDR,m,v,HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_EN_IN)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_EN_EN_BMSK                                                      0x1
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_EN_EN_SHFT                                                      0x0
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_EN_EN_DISABLE_FVAL                                              0x0
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_EN_EN_ENABLE_FVAL                                               0x1

#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_TRIGGER_ADDR                                             (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00001044)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_TRIGGER_OFFS                                             (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00001044)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_TRIGGER_RMSK                                                    0x1
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_TRIGGER_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_TRIGGER_ADDR)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_TRIGGER_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_TRIGGER_ADDR, m)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_TRIGGER_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_TRIGGER_ADDR,v)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_TRIGGER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_TRIGGER_ADDR,m,v,HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_TRIGGER_IN)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_TRIGGER_TRIGGER_BMSK                                            0x1
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_TRIGGER_TRIGGER_SHFT                                            0x0
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_TRIGGER_TRIGGER_CLR_FVAL                                        0x0
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_TRIGGER_TRIGGER_SET_FVAL                                        0x1

#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_CMD_ADDR                                                 (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00001048)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_CMD_OFFS                                                 (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00001048)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_CMD_RMSK                                                 0xffffffff
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_CMD_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_CMD_ADDR)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_CMD_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_CMD_ADDR, m)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_CMD_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_CMD_ADDR,v)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_CMD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_CMD_ADDR,m,v,HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_CMD_IN)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_CMD_CMD_PAYLOAD_BMSK                                     0xffffffff
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_CMD_CMD_PAYLOAD_SHFT                                            0x0

#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_STATUS_ADDR                                              (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x0000104c)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_STATUS_OFFS                                              (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x0000104c)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_STATUS_RMSK                                                     0x1
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_STATUS_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_STATUS_ADDR)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_STATUS_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_STATUS_ADDR, m)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_STATUS_STATUS_BMSK                                              0x1
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_STATUS_STATUS_SHFT                                              0x0
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_STATUS_STATUS_COMPLETED_FVAL                                    0x0
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_STATUS_STATUS_PROCESSING_FVAL                                   0x1

#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_RESPONSE_ADDR                                            (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00001050)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_RESPONSE_OFFS                                            (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00001050)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_RESPONSE_RMSK                                            0xffffffff
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_RESPONSE_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_RESPONSE_ADDR)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_RESPONSE_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_RESPONSE_ADDR, m)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_RESPONSE_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_RESPONSE_ADDR,v)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_RESPONSE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_RESPONSE_ADDR,m,v,HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_RESPONSE_IN)
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_RESPONSE_RSP_PAYLOAD_BMSK                                0xffffffff
#define HWIO_SHRM_CSR_SHRM2APPS_INTERRUPT_RESPONSE_RSP_PAYLOAD_SHFT                                       0x0

#define HWIO_SHRM_CSR_SHRM_SWRST_TRIG_ADDR                                                         (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00001080)
#define HWIO_SHRM_CSR_SHRM_SWRST_TRIG_OFFS                                                         (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00001080)
#define HWIO_SHRM_CSR_SHRM_SWRST_TRIG_RMSK                                                                0x1
#define HWIO_SHRM_CSR_SHRM_SWRST_TRIG_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_SWRST_TRIG_ADDR)
#define HWIO_SHRM_CSR_SHRM_SWRST_TRIG_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_SWRST_TRIG_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_SWRST_TRIG_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_SWRST_TRIG_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_SWRST_TRIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_SWRST_TRIG_ADDR,m,v,HWIO_SHRM_CSR_SHRM_SWRST_TRIG_IN)
#define HWIO_SHRM_CSR_SHRM_SWRST_TRIG_SWRESET_ENA_BMSK                                                    0x1
#define HWIO_SHRM_CSR_SHRM_SWRST_TRIG_SWRESET_ENA_SHFT                                                    0x0

#define HWIO_SHRM_CSR_SHRM_SWRST_CLKGATE_SEQ_ADDR                                                  (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00001084)
#define HWIO_SHRM_CSR_SHRM_SWRST_CLKGATE_SEQ_OFFS                                                  (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00001084)
#define HWIO_SHRM_CSR_SHRM_SWRST_CLKGATE_SEQ_RMSK                                                  0xffffffff
#define HWIO_SHRM_CSR_SHRM_SWRST_CLKGATE_SEQ_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_SWRST_CLKGATE_SEQ_ADDR)
#define HWIO_SHRM_CSR_SHRM_SWRST_CLKGATE_SEQ_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_SWRST_CLKGATE_SEQ_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_SWRST_CLKGATE_SEQ_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_SWRST_CLKGATE_SEQ_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_SWRST_CLKGATE_SEQ_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_SWRST_CLKGATE_SEQ_ADDR,m,v,HWIO_SHRM_CSR_SHRM_SWRST_CLKGATE_SEQ_IN)
#define HWIO_SHRM_CSR_SHRM_SWRST_CLKGATE_SEQ_SWRESET_CLK_EN_BMSK                                   0xffffffff
#define HWIO_SHRM_CSR_SHRM_SWRST_CLKGATE_SEQ_SWRESET_CLK_EN_SHFT                                          0x0

#define HWIO_SHRM_CSR_SHRM_SWRST_RES_SEQ_ADDR                                                      (SHRM_CSR_SHRM_CSR_REG_BASE      + 0x00001088)
#define HWIO_SHRM_CSR_SHRM_SWRST_RES_SEQ_OFFS                                                      (SHRM_CSR_SHRM_CSR_REG_BASE_OFFS + 0x00001088)
#define HWIO_SHRM_CSR_SHRM_SWRST_RES_SEQ_RMSK                                                      0xffffffff
#define HWIO_SHRM_CSR_SHRM_SWRST_RES_SEQ_IN          \
        in_dword(HWIO_SHRM_CSR_SHRM_SWRST_RES_SEQ_ADDR)
#define HWIO_SHRM_CSR_SHRM_SWRST_RES_SEQ_INM(m)      \
        in_dword_masked(HWIO_SHRM_CSR_SHRM_SWRST_RES_SEQ_ADDR, m)
#define HWIO_SHRM_CSR_SHRM_SWRST_RES_SEQ_OUT(v)      \
        out_dword(HWIO_SHRM_CSR_SHRM_SWRST_RES_SEQ_ADDR,v)
#define HWIO_SHRM_CSR_SHRM_SWRST_RES_SEQ_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SHRM_CSR_SHRM_SWRST_RES_SEQ_ADDR,m,v,HWIO_SHRM_CSR_SHRM_SWRST_RES_SEQ_IN)
#define HWIO_SHRM_CSR_SHRM_SWRST_RES_SEQ_SWRESET_ARES_SET_BMSK                                     0xffffffff
#define HWIO_SHRM_CSR_SHRM_SWRST_RES_SEQ_SWRESET_ARES_SET_SHFT                                            0x0

/*----------------------------------------------------------------------------
* MODULE: CABO_BROADCAST_CABO_SHKE
*--------------------------------------------------------------------------*/

#define CABO_BROADCAST_CABO_SHKE_REG_BASE                                                                   (DDR_SS_BASE      + 0x00665000)
#define CABO_BROADCAST_CABO_SHKE_REG_BASE_SIZE                                                              0x1000
#define CABO_BROADCAST_CABO_SHKE_REG_BASE_USED                                                              0xb38
#define CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS                                                              (DDR_SS_BASE_PHYS + 0x00665000)
#define CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS                                                              0x00665000

#define HWIO_CABO_BROADCAST_CABO_SHKE_LOAD_CONFIG_ADDR                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000020)
#define HWIO_CABO_BROADCAST_CABO_SHKE_LOAD_CONFIG_PHYS                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000020)
#define HWIO_CABO_BROADCAST_CABO_SHKE_LOAD_CONFIG_OFFS                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000020)
#define HWIO_CABO_BROADCAST_CABO_SHKE_LOAD_CONFIG_RMSK                                                             0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_LOAD_CONFIG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_LOAD_CONFIG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_LOAD_CONFIG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_LOAD_CONFIG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_LOAD_CONFIG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_LOAD_CONFIG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_LOAD_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_LOAD_CONFIG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_LOAD_CONFIG_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_LOAD_CONFIG_LOAD_CONFIG_BMSK                                                 0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_LOAD_CONFIG_LOAD_CONFIG_SHFT                                                 0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_ADDR                                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000030)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_PHYS                                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000030)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_OFFS                                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000030)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_RMSK                                                             0x37ff
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_RFU_13_12_BMSK                                                   0x3000
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_RFU_13_12_SHFT                                                      0xc
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_SW_LOAD_ASYNC_CG_EN_BMSK                                          0x400
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_SW_LOAD_ASYNC_CG_EN_SHFT                                            0xa
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_EVENT_ASYNC_CG_EN_BMSK                                            0x200
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_EVENT_ASYNC_CG_EN_SHFT                                              0x9
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_ARB_CG_EN_BMSK                                                    0x100
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_ARB_CG_EN_SHFT                                                      0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_SW_CMD_CG_EN_BMSK                                                  0x80
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_SW_CMD_CG_EN_SHFT                                                   0x7
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_FSW_CG_EN_BMSK                                                     0x40
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_FSW_CG_EN_SHFT                                                      0x6
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_DIT_CG_EN_BMSK                                                     0x20
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_DIT_CG_EN_SHFT                                                      0x5
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_SELF_REFRESH_CG_EN_BMSK                                            0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_SELF_REFRESH_CG_EN_SHFT                                             0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_REFRESH_CG_EN_BMSK                                                  0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_REFRESH_CG_EN_SHFT                                                  0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_ZQ_CG_EN_BMSK                                                       0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_ZQ_CG_EN_SHFT                                                       0x2
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_INTERVAL_TIMER_CG_EN_BMSK                                           0x2
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_INTERVAL_TIMER_CG_EN_SHFT                                           0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_STALL_CG_EN_BMSK                                                    0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_CLK_CTRL_STALL_CG_EN_SHFT                                                    0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_ADDR                                                           (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000040)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_PHYS                                                           (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000040)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_OFFS                                                           (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000040)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_RMSK                                                                0x737
#define HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_DEVICE_CFG_RANK1_BMSK                                               0x700
#define HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_DEVICE_CFG_RANK1_SHFT                                                 0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_RANK_EN_BMSK                                                         0x30
#define HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_RANK_EN_SHFT                                                          0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_DEVICE_CFG_BMSK                                                       0x7
#define HWIO_CABO_BROADCAST_CABO_SHKE_CONFIG_DEVICE_CFG_SHFT                                                       0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_ADDR                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000050)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_PHYS                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000050)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_OFFS                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000050)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_RMSK                                                             0xf
#define HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_RFU_3_2_BMSK                                                     0xc
#define HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_RFU_3_2_SHFT                                                     0x2
#define HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_RANK_READY_BMSK                                                  0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_INIT_CONFIG_RANK_READY_SHFT                                                  0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_ADDR                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000060)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_PHYS                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000060)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_OFFS                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000060)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_RMSK                                                          0x3333
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_DQ3_BMSK                                                      0x3000
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_DQ3_SHFT                                                         0xc
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_DQ2_BMSK                                                       0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_DQ2_SHFT                                                         0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_DQ1_BMSK                                                        0x30
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_DQ1_SHFT                                                         0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_DQ0_BMSK                                                         0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_BYTE_MAP_DQ0_SHFT                                                         0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_MRR_SAMPLE_INDEX_ADDR                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000064)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MRR_SAMPLE_INDEX_PHYS                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000064)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MRR_SAMPLE_INDEX_OFFS                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000064)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MRR_SAMPLE_INDEX_RMSK                                                        0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_MRR_SAMPLE_INDEX_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_MRR_SAMPLE_INDEX_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MRR_SAMPLE_INDEX_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_MRR_SAMPLE_INDEX_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MRR_SAMPLE_INDEX_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_MRR_SAMPLE_INDEX_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MRR_SAMPLE_INDEX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_MRR_SAMPLE_INDEX_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_MRR_SAMPLE_INDEX_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MRR_SAMPLE_INDEX_SAMPLE_INDEX_BMSK                                           0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_MRR_SAMPLE_INDEX_SAMPLE_INDEX_SHFT                                           0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_ADDR                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000080)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_PHYS                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000080)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_OFFS                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000080)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_RMSK                                                 0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_TYPE3_STALL_CYCLES_BMSK                              0xff000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_TYPE3_STALL_CYCLES_SHFT                                    0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_TYPE2_STALL_CYCLES_BMSK                                0xff0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_TYPE2_STALL_CYCLES_SHFT                                    0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_TYPE1_STALL_CYCLES_BMSK                                  0xff00
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_TYPE1_STALL_CYCLES_SHFT                                     0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_TYPE0_STALL_CYCLES_BMSK                                    0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CFG_TYPE0_STALL_CYCLES_SHFT                                     0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_ADDR                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000084)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_PHYS                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000084)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_OFFS                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000084)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_RMSK                                                       0xf
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_RFU_3_2_BMSK                                               0xc
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_RFU_3_2_SHFT                                               0x2
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_PRIORITY_BMSK                                              0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_FINITE_STALL_CTRL_PRIORITY_SHFT                                              0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_ADDR                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000090)
#define HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_PHYS                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000090)
#define HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_OFFS                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000090)
#define HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_RMSK                                                      0x311
#define HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_DERATE_STALL_TYPE_BMSK                                    0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_DERATE_STALL_TYPE_SHFT                                      0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_DERATE_STALL_EN_BMSK                                       0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_DERATE_STALL_EN_SHFT                                        0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_DERATE_REQ_EN_BMSK                                          0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_TEMP_DERATE_CTRL_DERATE_REQ_EN_SHFT                                          0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_ADDR                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x000000a0)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_PHYS                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x000000a0)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_OFFS                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x000000a0)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_RMSK                                                       0x1ff0731
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_STALL_DT_B4_FSW_DT_BMSK                                    0x1000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_STALL_DT_B4_FSW_DT_SHFT                                         0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_DT_STALL_CYCLES_THRESHOLD_BMSK                              0xff0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_DT_STALL_CYCLES_THRESHOLD_SHFT                                  0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_RFU_10_9_BMSK                                                  0x600
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_RFU_10_9_SHFT                                                    0x9
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_DT_PRIORITY_BMSK                                               0x100
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_DT_PRIORITY_SHFT                                                 0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_DT_TYPE_BMSK                                                    0x30
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_DT_TYPE_SHFT                                                     0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_DT_REQ_EN_BMSK                                                   0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_CTRL_DT_REQ_EN_SHFT                                                   0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_ADDR(n)                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000100 + 0x20 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_PHYS(n)                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000100 + 0x20 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_OFFS(n)                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000100 + 0x20 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_RMSK                                            0xd113ffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_MAXn                                                     4
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_RFU_31_30_BMSK                                  0xc0000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_RFU_31_30_SHFT                                        0x1e
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_SW_LOAD_BMSK                                    0x10000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_SW_LOAD_SHFT                                          0x1c
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_PREDECESSOR_TRIGGER_EN_BMSK                      0x1000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_PREDECESSOR_TRIGGER_EN_SHFT                           0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_AUTO_LOAD_EN_BMSK                                 0x100000
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_AUTO_LOAD_EN_SHFT                                     0x14
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_CLK_SELECT_BMSK                                    0x30000
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_CLK_SELECT_SHFT                                       0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_INTERVAL_BMSK                                       0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_TIMER_CTRL_n_INTERVAL_SHFT                                          0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_ADDR(n)                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000108 + 0x20 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_PHYS(n)                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000108 + 0x20 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_OFFS(n)                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000108 + 0x20 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_RMSK                                             0x333fff3
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_MAXn                                                     4
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_ESCALATED_PRIORITY_BMSK                          0x3000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_ESCALATED_PRIORITY_SHFT                               0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_PRIORITY_BMSK                                     0x300000
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_PRIORITY_SHFT                                         0x14
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_EVENT_SELECT_BMSK                                  0x3ff00
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_EVENT_SELECT_SHFT                                      0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_RFU_7_5_BMSK                                          0xe0
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_RFU_7_5_SHFT                                           0x5
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_EVENT_EN_BMSK                                         0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_EVENT_EN_SHFT                                          0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_RANK_EN_BMSK                                           0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_CTRL_n_RANK_EN_SHFT                                           0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_ADDR(n)                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x0000010c + 0x20 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_PHYS(n)                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x0000010c + 0x20 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_OFFS(n)                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x0000010c + 0x20 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_RMSK                                    0xffff0311
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_MAXn                                             4
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_STAGGER_RANKS_OFFSET_BMSK               0xffff0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_STAGGER_RANKS_OFFSET_SHFT                     0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_RFU_9_8_BMSK                                 0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_RFU_9_8_SHFT                                   0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_GLOBAL_TIMER_WINDOW_EN_BMSK                   0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_GLOBAL_TIMER_WINDOW_EN_SHFT                    0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_STAGGER_RANKS_EN_BMSK                          0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_STAGGER_RANKS_EN_SHFT                          0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STATUS_n_ADDR(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000110 + 0x20 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STATUS_n_PHYS(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000110 + 0x20 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STATUS_n_OFFS(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000110 + 0x20 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STATUS_n_RMSK                                                0x33
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STATUS_n_MAXn                                                   4
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STATUS_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STATUS_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STATUS_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STATUS_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STATUS_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STATUS_n_EVENT_OVERFLOW_BMSK                                 0x30
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STATUS_n_EVENT_OVERFLOW_SHFT                                  0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STATUS_n_EVENT_PENDING_BMSK                                   0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_INTERVAL_EVENT_STATUS_n_EVENT_PENDING_SHFT                                   0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_ADDR                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000200)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_PHYS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000200)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_OFFS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000200)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_RMSK                                               0xd113ffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_RFU_31_30_BMSK                                     0xc0000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_RFU_31_30_SHFT                                           0x1e
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_SW_LOAD_BMSK                                       0x10000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_SW_LOAD_SHFT                                             0x1c
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_RFU_24_BMSK                                         0x1000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_RFU_24_SHFT                                              0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_AUTO_LOAD_EN_BMSK                                    0x100000
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_AUTO_LOAD_EN_SHFT                                        0x14
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_CLK_SELECT_BMSK                                       0x30000
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_CLK_SELECT_SHFT                                          0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_INTERVAL_BMSK                                          0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_TIMER_CTRL_INTERVAL_SHFT                                             0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_ADDR                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000208)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_PHYS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000208)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_OFFS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000208)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_RMSK                                                0x3300313
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_ESCALATED_PRIORITY_BMSK                             0x3000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_ESCALATED_PRIORITY_SHFT                                  0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_PRIORITY_BMSK                                        0x300000
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_PRIORITY_SHFT                                            0x14
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_RFU_9_8_BMSK                                            0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_RFU_9_8_SHFT                                              0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_EVENT_EN_BMSK                                            0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_EVENT_EN_SHFT                                             0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_RANK_EN_BMSK                                              0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_EVENT_CTRL_RANK_EN_SHFT                                              0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_ADDR                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x0000020c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_PHYS                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x0000020c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_OFFS                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x0000020c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_RMSK                                             0xffff0311
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_STAGGER_RANKS_OFFSET_BMSK                        0xffff0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_STAGGER_RANKS_OFFSET_SHFT                              0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_RFU_9_8_BMSK                                          0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_RFU_9_8_SHFT                                            0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_GLOBAL_TIMER_WINDOW_EN_BMSK                            0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_GLOBAL_TIMER_WINDOW_EN_SHFT                             0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_STAGGER_RANKS_EN_BMSK                                   0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STAGGER_CTRL_STAGGER_RANKS_EN_SHFT                                   0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STATUS_ADDR                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000210)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STATUS_PHYS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000210)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STATUS_OFFS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000210)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STATUS_RMSK                                                         0x33
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STATUS_EVENT_OVERFLOW_BMSK                                          0x30
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STATUS_EVENT_OVERFLOW_SHFT                                           0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STATUS_EVENT_PENDING_BMSK                                            0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQSTART_STATUS_EVENT_PENDING_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_ADDR                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000220)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_PHYS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000220)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_OFFS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000220)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_RMSK                                               0xd113ffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_RFU_31_30_BMSK                                     0xc0000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_RFU_31_30_SHFT                                           0x1e
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_SW_LOAD_BMSK                                       0x10000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_SW_LOAD_SHFT                                             0x1c
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_ZQSTART_TRIGGER_EN_BMSK                             0x1000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_ZQSTART_TRIGGER_EN_SHFT                                  0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_AUTO_LOAD_EN_BMSK                                    0x100000
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_AUTO_LOAD_EN_SHFT                                        0x14
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_CLK_SELECT_BMSK                                       0x30000
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_CLK_SELECT_SHFT                                          0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_INTERVAL_BMSK                                          0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_TIMER_CTRL_INTERVAL_SHFT                                             0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_ADDR                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000228)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_PHYS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000228)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_OFFS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000228)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_RMSK                                                0x3300313
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_ESCALATED_PRIORITY_BMSK                             0x3000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_ESCALATED_PRIORITY_SHFT                                  0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_PRIORITY_BMSK                                        0x300000
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_PRIORITY_SHFT                                            0x14
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_RFU_9_8_BMSK                                            0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_RFU_9_8_SHFT                                              0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_EVENT_EN_BMSK                                            0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_EVENT_EN_SHFT                                             0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_RANK_EN_BMSK                                              0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_EVENT_CTRL_RANK_EN_SHFT                                              0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_ADDR                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x0000022c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_PHYS                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x0000022c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_OFFS                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x0000022c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_RMSK                                             0xffff0311
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_STAGGER_RANKS_OFFSET_BMSK                        0xffff0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_STAGGER_RANKS_OFFSET_SHFT                              0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_RFU_9_8_BMSK                                          0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_RFU_9_8_SHFT                                            0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_GLOBAL_TIMER_WINDOW_EN_BMSK                            0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_GLOBAL_TIMER_WINDOW_EN_SHFT                             0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_STAGGER_RANKS_EN_BMSK                                   0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STAGGER_CTRL_STAGGER_RANKS_EN_SHFT                                   0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STATUS_ADDR                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000230)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STATUS_PHYS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000230)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STATUS_OFFS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000230)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STATUS_RMSK                                                         0x33
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STATUS_EVENT_OVERFLOW_BMSK                                          0x30
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STATUS_EVENT_OVERFLOW_SHFT                                           0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STATUS_EVENT_PENDING_BMSK                                            0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQLATCH_STATUS_EVENT_PENDING_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_ADDR(n)                                     (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000240 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_PHYS(n)                                     (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000240 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_OFFS(n)                                     (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000240 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_RMSK                                        0xd001ffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_MAXn                                                 1
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_RFU_31_30_BMSK                              0xc0000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_RFU_31_30_SHFT                                    0x1e
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_SW_LOAD_BMSK                                0x10000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_SW_LOAD_SHFT                                      0x1c
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_AUTO_LOAD_EN_BMSK                              0x10000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_AUTO_LOAD_EN_SHFT                                 0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_TREFI_BMSK                                      0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TIMER_CTRL_RANK_n_TREFI_SHFT                                         0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_ADDR                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000248)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_PHYS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000248)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_OFFS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000248)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_RMSK                                                0x3300333
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_ESCALATED_PRIORITY_BMSK                             0x3000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_ESCALATED_PRIORITY_SHFT                                  0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_PRIORITY_BMSK                                        0x300000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_PRIORITY_SHFT                                            0x14
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_RFU_9_8_BMSK                                            0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_RFU_9_8_SHFT                                              0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_REFRESH_PB_RANK_EN_BMSK                                  0x30
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_REFRESH_PB_RANK_EN_SHFT                                   0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_RANK_EN_BMSK                                              0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_EVENT_CTRL_RANK_EN_SHFT                                              0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_ADDR                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x0000024c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_PHYS                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x0000024c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_OFFS                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x0000024c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_RMSK                                                  0x371
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_RFU_9_8_BMSK                                          0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_RFU_9_8_SHFT                                            0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_STAGGER_DIS_DEBIT_THRESHOLD_BMSK                       0x70
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_STAGGER_DIS_DEBIT_THRESHOLD_SHFT                        0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_STAGGER_RANKS_EN_BMSK                                   0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STAGGER_CTRL_STAGGER_RANKS_EN_SHFT                                   0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_ADDR(n)                                          (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000250 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_PHYS(n)                                          (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000250 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_OFFS(n)                                          (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000250 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_RMSK                                             0xffff7337
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_MAXn                                                      3
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_RFU_31_24_BMSK                                   0xff000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_RFU_31_24_SHFT                                         0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_TIMING_MODE_BMSK                           0x800000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_TIMING_MODE_SHFT                               0x17
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_PULL_IN_LIMIT_EN_BMSK                      0x400000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_PULL_IN_LIMIT_EN_SHFT                          0x16
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_PULL_IN_THRESHOLD_BMSK                     0x300000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_PULL_IN_THRESHOLD_SHFT                         0x14
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_AB_BANK_THRESHOLD_BMSK                      0xe0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_AB_BANK_THRESHOLD_SHFT                         0x11
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_RDYLVL_IGNORE_BMSK                          0x10000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_RDYLVL_IGNORE_SHFT                             0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_BUSY_BANKS_THRESHOLD_BMSK                    0x7000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_BUSY_BANKS_THRESHOLD_SHFT                       0xc
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_RDYLVL_BUSY_THRESHOLD_BMSK                    0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_RDYLVL_BUSY_THRESHOLD_SHFT                      0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_RDYLVL_THRESHOLD_BMSK                          0x30
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_RDYLVL_THRESHOLD_SHFT                           0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_AB_DEBIT_THRESHOLD_BMSK                         0x7
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_AB_DEBIT_THRESHOLD_SHFT                         0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_ADDR                                           (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000270)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_PHYS                                           (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000270)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_OFFS                                           (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000270)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_RMSK                                           0xf11ffff1
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_RFU_31_BMSK                                    0x80000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_RFU_31_SHFT                                          0x1f
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_REFRESH_RATE_THRESHOLD_BMSK                    0x70000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_REFRESH_RATE_THRESHOLD_SHFT                          0x1c
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_REFRESH_RATE_THRESHOLD_EN_BMSK                  0x1000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_REFRESH_RATE_THRESHOLD_EN_SHFT                       0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_REFRESH_PB_FREQ_THRESHOLD_BMSK                   0x1ffff0
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_REFRESH_PB_FREQ_THRESHOLD_SHFT                        0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_REFRESH_PB_FREQ_THRESHOLD_EN_BMSK                     0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_AB_SWITCH_CTRL_REFRESH_PB_FREQ_THRESHOLD_EN_SHFT                     0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_ADDR                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000274)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_PHYS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000274)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_OFFS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000274)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_RMSK                                               0xf1ffff11
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_RFU_31_BMSK                                        0x80000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_RFU_31_SHFT                                              0x1f
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_REFRESH_CREDIT_BURST_LEN_BMSK                      0x70000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_REFRESH_CREDIT_BURST_LEN_SHFT                            0x1c
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_REFRESH_BURST_FREQ_THRESHOLD_BMSK                   0x1ffff00
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_REFRESH_BURST_FREQ_THRESHOLD_SHFT                         0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_REFRESH_BURST_FREQ_THRESHOLD_EN_BMSK                     0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_REFRESH_BURST_FREQ_THRESHOLD_EN_SHFT                      0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_REFRESH_BURST_EN_BMSK                                     0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_BURST_CTRL_REFRESH_BURST_EN_SHFT                                     0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_ADDR                                    (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000280)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_PHYS                                    (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000280)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_OFFS                                    (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000280)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_RMSK                                         0x311
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_RFU_9_8_BMSK                                 0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_RFU_9_8_SHFT                                   0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_TEMP_UPDATE_FLAG_OVERRIDE_BMSK                0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_TEMP_UPDATE_FLAG_OVERRIDE_SHFT                 0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_TEMP_UPDATE_TIMER_EN_BMSK                      0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_TEMP_UPDATE_TIMER_EN_SHFT                      0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_ADDR                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000284)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_PHYS                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000284)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_OFFS                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000284)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_RMSK                                                   0x77
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_LOW_TEMP_THRESHOLD_BMSK                                0x70
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_LOW_TEMP_THRESHOLD_SHFT                                 0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_HIGH_TEMP_THRESHOLD_BMSK                                0x7
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_TEMP_ERR_CFG_HIGH_TEMP_THRESHOLD_SHFT                                0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_ADDR(n)                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000300 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_PHYS(n)                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000300 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_OFFS(n)                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000300 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_RMSK                                        0x3ffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_MAXn                                              3
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_RFU_17_16_BMSK                              0x30000
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_RFU_17_16_SHFT                                 0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_IDLE_TIMER_BMSK                              0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_IDLE_TIMER_SHFT                                 0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_ADDR                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000328)
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_PHYS                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000328)
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_OFFS                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000328)
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_RMSK                                             0x73307133
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_REFRESH_FLUSH_B4_SRE_BMSK                        0x40000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_REFRESH_FLUSH_B4_SRE_SHFT                              0x1e
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_REFRESH_AFTER_SRX_EN_BMSK                        0x20000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_REFRESH_AFTER_SRX_EN_SHFT                              0x1d
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_REFRESH_BEFORE_SRE_EN_BMSK                       0x10000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_REFRESH_BEFORE_SRE_EN_SHFT                             0x1c
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_SRX_PRIORITY_BMSK                                 0x3000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_SRX_PRIORITY_SHFT                                      0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_SRE_PRIORITY_BMSK                                  0x300000
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_SRE_PRIORITY_SHFT                                      0x14
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_RFU_14_12_BMSK                                       0x7000
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_RFU_14_12_SHFT                                          0xc
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_CONCURRENT_SR_EN_BMSK                                 0x100
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_CONCURRENT_SR_EN_SHFT                                   0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_SR_ABORT_EN_BMSK                                       0x30
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_SR_ABORT_EN_SHFT                                        0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_RANK_EN_BMSK                                            0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_HW_SELF_REFRESH_CTRL_RANK_EN_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_ADDR                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000340)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_PHYS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000340)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_OFFS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000340)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_RMSK                                               0xd003ffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_RFU_31_30_BMSK                                     0xc0000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_RFU_31_30_SHFT                                           0x1e
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_SW_LOAD_BMSK                                       0x10000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_SW_LOAD_SHFT                                             0x1c
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_CLK_SELECT_BMSK                                       0x30000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_CLK_SELECT_SHFT                                          0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_ACQ_INTERVAL_BMSK                                      0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_TIMER_CTRL_ACQ_INTERVAL_SHFT                                         0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_ADDR                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000348)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_PHYS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000348)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_OFFS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000348)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_RMSK                                                0x33ff313
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_ESCALATED_PRIORITY_BMSK                             0x3000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_ESCALATED_PRIORITY_SHFT                                  0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_PRIORITY_BMSK                                        0x300000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_PRIORITY_SHFT                                            0x14
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_NUM_SAMPLES_BMSK                                      0xff000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_NUM_SAMPLES_SHFT                                          0xc
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_RFU_9_8_BMSK                                            0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_RFU_9_8_SHFT                                              0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_MPC_STOP_EN_BMSK                                         0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_MPC_STOP_EN_SHFT                                          0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_RANK_EN_BMSK                                              0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_EVENT_CTRL_RANK_EN_SHFT                                              0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_ADDR                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x0000034c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_PHYS                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x0000034c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_OFFS                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x0000034c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_RMSK                                             0xffff0301
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_STAGGER_RANKS_OFFSET_BMSK                        0xffff0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_STAGGER_RANKS_OFFSET_SHFT                              0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_RFU_9_8_BMSK                                          0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_RFU_9_8_SHFT                                            0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_STAGGER_RANKS_EN_BMSK                                   0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_ACQ_STAGGER_CTRL_STAGGER_RANKS_EN_SHFT                                   0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_ADDR                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000360)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_PHYS                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000360)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_OFFS                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000360)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_RMSK                                              0xd003ffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_RFU_31_30_BMSK                                    0xc0000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_RFU_31_30_SHFT                                          0x1e
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_SW_LOAD_BMSK                                      0x10000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_SW_LOAD_SHFT                                            0x1c
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_CLK_SELECT_BMSK                                      0x30000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_CLK_SELECT_SHFT                                         0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_TRAC_INTERVAL_BMSK                                    0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_TIMER_CTRL_TRAC_INTERVAL_SHFT                                       0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_ADDR                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000368)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_PHYS                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000368)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_OFFS                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000368)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_RMSK                                               0x33ff313
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_ESCALATED_PRIORITY_BMSK                            0x3000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_ESCALATED_PRIORITY_SHFT                                 0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_PRIORITY_BMSK                                       0x300000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_PRIORITY_SHFT                                           0x14
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_NUM_SAMPLES_BMSK                                     0xff000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_NUM_SAMPLES_SHFT                                         0xc
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_RFU_9_8_BMSK                                           0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_RFU_9_8_SHFT                                             0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_MPC_STOP_EN_BMSK                                        0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_MPC_STOP_EN_SHFT                                         0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_RANK_EN_BMSK                                             0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_EVENT_CTRL_RANK_EN_SHFT                                             0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_ADDR                                            (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x0000036c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_PHYS                                            (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x0000036c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_OFFS                                            (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x0000036c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_RMSK                                            0xffff0301
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_STAGGER_RANKS_OFFSET_BMSK                       0xffff0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_STAGGER_RANKS_OFFSET_SHFT                             0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_RFU_9_8_BMSK                                         0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_RFU_9_8_SHFT                                           0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_STAGGER_RANKS_EN_BMSK                                  0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_STAGGER_CTRL_STAGGER_RANKS_EN_SHFT                                  0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_ADDR                                           (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000370)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_PHYS                                           (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000370)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_OFFS                                           (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000370)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_RMSK                                           0x301ffff1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_RFU_29_28_BMSK                                 0x30000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_RFU_29_28_SHFT                                       0x1c
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_TRAC_FREQ_THRESHOLD_BMSK                         0x1ffff0
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_TRAC_FREQ_THRESHOLD_SHFT                              0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_TRAC_FREQ_THRESHOLD_EN_BMSK                           0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_TRAC_THRESHOLD_CFG_TRAC_FREQ_THRESHOLD_EN_SHFT                           0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_ADDR                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000380)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_PHYS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000380)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_OFFS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000380)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_RMSK                                               0xc3ffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_RFU_31_30_BMSK                                     0xc0000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_RFU_31_30_SHFT                                           0x1e
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_CLK_SELECT_BMSK                                     0x3000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_CLK_SELECT_SHFT                                          0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_MPC_STOP_TO_MRR_BMSK                                 0xff0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_MPC_STOP_TO_MRR_SHFT                                     0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_MPC_START_TO_MRR_BMSK                                  0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_MRR_TIMER_CTRL_MPC_START_TO_MRR_SHFT                                     0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_ADDR                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x000003a0)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_PHYS                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x000003a0)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_OFFS                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x000003a0)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_RMSK                                                     0x311
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_RFU_9_8_BMSK                                             0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_RFU_9_8_SHFT                                               0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_TRAC_PERIODIC_EVENT_EN_BMSK                               0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_TRAC_PERIODIC_EVENT_EN_SHFT                                0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_TRAC_EVENT_EN_BMSK                                         0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_CFG_TRAC_EVENT_EN_SHFT                                         0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_ADDR                                     (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x000003a4)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_PHYS                                     (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x000003a4)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_OFFS                                     (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x000003a4)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_RMSK                                     0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_DIT_HIGH_THRESHOLD_BMSK                  0xffff0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_DIT_HIGH_THRESHOLD_SHFT                        0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_DIT_LOW_THRESHOLD_BMSK                       0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_DIT_LOW_THRESHOLD_SHFT                          0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_STATUS_ADDR                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x000003b0)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_STATUS_PHYS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x000003b0)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_STATUS_OFFS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x000003b0)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_STATUS_RMSK                                                          0xf
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_STATUS_FSM_STATE_BMSK                                                0xf
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_STATUS_FSM_STATE_SHFT                                                0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_STATUS_ADDR                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x000003b4)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_STATUS_PHYS                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x000003b4)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_STATUS_OFFS                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x000003b4)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_STATUS_RMSK                                                0x30011
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_STATUS_LAST_DIT_RANK_BMSK                                  0x30000
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_STATUS_LAST_DIT_RANK_SHFT                                     0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_STATUS_TRAC_PERIODIC_EVENT_STATUS_BMSK                        0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_STATUS_TRAC_PERIODIC_EVENT_STATUS_SHFT                         0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_STATUS_TRAC_EVENT_STATUS_BMSK                                  0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_EVENT_STATUS_TRAC_EVENT_STATUS_SHFT                                  0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_ADDR(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x000003c0 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_PHYS(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x000003c0 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_OFFS(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x000003c0 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_RMSK                                              0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_MAXn                                                   1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_MR19_BMSK                                         0xff00
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_MR19_SHFT                                            0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_MR18_BMSK                                           0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_MR18_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_ADDR(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x000003e0 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_PHYS(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x000003e0 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_OFFS(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x000003e0 + 0x4 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_RMSK                                              0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_MAXn                                                   1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_MR19_BMSK                                         0xff00
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_MR19_SHFT                                            0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_MR18_BMSK                                           0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_MR18_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_ADDR(n)                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000400 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_PHYS(n)                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000400 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_OFFS(n)                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000400 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_RMSK                                            0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_MAXn                                               1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_NUM_SAMPLES_BMSK                                0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_NUM_SAMPLES_SHFT                                 0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_ADDR(n)                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000404 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_PHYS(n)                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000404 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_OFFS(n)                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000404 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_RMSK                                         0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_MAXn                                                  1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_ACCU_VALUE_BMSK                              0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_ACCU_VALUE_SHFT                                     0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_ADDR(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000408 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_PHYS(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000408 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_OFFS(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000408 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_RMSK                                              0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_MAXn                                                   1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_MR19_BMSK                                         0xff00
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_MR19_SHFT                                            0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_MR18_BMSK                                           0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_MR18_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_ADDR(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x0000040c + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_PHYS(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x0000040c + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_OFFS(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x0000040c + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_RMSK                                              0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_MAXn                                                   1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_MR19_BMSK                                         0xff00
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_MR19_SHFT                                            0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_MR18_BMSK                                           0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_MR18_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_ADDR(n)                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000480 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_PHYS(n)                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000480 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_OFFS(n)                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000480 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_RMSK                                            0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_MAXn                                               1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_NUM_SAMPLES_BMSK                                0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_NUM_SAMPLES_SHFT                                 0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_ADDR(n)                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000484 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_PHYS(n)                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000484 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_OFFS(n)                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000484 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_RMSK                                         0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_MAXn                                                  1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_ACCU_VALUE_BMSK                              0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_ACCU_VALUE_SHFT                                     0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_ADDR(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000488 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_PHYS(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000488 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_OFFS(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000488 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_RMSK                                              0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_MAXn                                                   1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_MR19_BMSK                                         0xff00
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_MR19_SHFT                                            0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_MR18_BMSK                                           0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_MR18_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_ADDR(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x0000048c + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_PHYS(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x0000048c + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_OFFS(n)                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x0000048c + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_RMSK                                              0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_MAXn                                                   1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_MR19_BMSK                                         0xff00
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_MR19_SHFT                                            0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_MR18_BMSK                                           0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_MR18_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ADDR(n)                               (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000504 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_PHYS(n)                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000504 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_OFFS(n)                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000504 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_RMSK                                  0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_MAXn                                           1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ACCU_VALUE_BMSK                       0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ACCU_VALUE_SHFT                              0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_ADDR(n)                                (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000508 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_PHYS(n)                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000508 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_OFFS(n)                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000508 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_RMSK                                       0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_MAXn                                            1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_MR19_BMSK                                  0xff00
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_MR19_SHFT                                     0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_MR18_BMSK                                    0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_MR18_SHFT                                     0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_ADDR(n)                                (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x0000050c + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_PHYS(n)                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x0000050c + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_OFFS(n)                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x0000050c + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_RMSK                                       0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_MAXn                                            1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_MR19_BMSK                                  0xff00
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_MR19_SHFT                                     0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_MR18_BMSK                                    0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_MR18_SHFT                                     0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ADDR(n)                               (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000584 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_PHYS(n)                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000584 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_OFFS(n)                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000584 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_RMSK                                  0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_MAXn                                           1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ACCU_VALUE_BMSK                       0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ACCU_VALUE_SHFT                              0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_ADDR(n)                                (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000588 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_PHYS(n)                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000588 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_OFFS(n)                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000588 + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_RMSK                                       0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_MAXn                                            1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_MR19_BMSK                                  0xff00
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_MR19_SHFT                                     0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_MR18_BMSK                                    0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_MR18_SHFT                                     0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_ADDR(n)                                (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x0000058c + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_PHYS(n)                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x0000058c + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_OFFS(n)                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x0000058c + 0x10 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_RMSK                                       0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_MAXn                                            1
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_MR19_BMSK                                  0xff00
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_MR19_SHFT                                     0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_MR18_BMSK                                    0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_MR18_SHFT                                     0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_ADDR(n)                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000600 + 0x8 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_PHYS(n)                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000600 + 0x8 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_OFFS(n)                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000600 + 0x8 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_RMSK                                                   0x301f1f01
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_MAXn                                                           15
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_RFU_29_28_BMSK                                         0x30000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_RFU_29_28_SHFT                                               0x1c
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_END_STATE_BMSK                                           0x1f0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_END_STATE_SHFT                                               0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_START_STATE_BMSK                                           0x1f00
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_START_STATE_SHFT                                              0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_TASK_EN_BMSK                                                  0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_CFG_n_TASK_EN_SHFT                                                  0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_ADDR(n)                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000604 + 0x8 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_PHYS(n)                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000604 + 0x8 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_OFFS(n)                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000604 + 0x8 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_RMSK                                               0x3ffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_MAXn                                                    15
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_RFU_17_16_BMSK                                     0x30000
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_RFU_17_16_SHFT                                        0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_TASK_DEPENDENCY_BMSK                                0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_TASK_DEPENDENCY_n_TASK_DEPENDENCY_SHFT                                   0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_ADDR                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x000006c0)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_PHYS                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x000006c0)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_OFFS                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x000006c0)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_RMSK                                                     0x31f
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_RFU_9_8_BMSK                                             0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_RFU_9_8_SHFT                                               0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_FSW_END_STATE_BMSK                                        0x1f
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_END_STATE_CFG_FSW_END_STATE_SHFT                                         0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_ADDR                                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x000006c4)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_PHYS                                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x000006c4)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_OFFS                                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x000006c4)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_RMSK                                                             0xf3
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_RFU_7_5_BMSK                                                     0xe0
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_RFU_7_5_SHFT                                                      0x5
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_DT_PRIORITY_BMSK                                                 0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_DT_PRIORITY_SHFT                                                  0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_DT_TYPE_BMSK                                                      0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_DT_CFG_DT_TYPE_SHFT                                                      0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ADDR                                                    (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x000006c8)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_PHYS                                                    (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x000006c8)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_OFFS                                                    (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x000006c8)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_RMSK                                                    0x31133113
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_RFU_29_28_BMSK                                          0x30000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_RFU_29_28_SHFT                                                0x1c
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ZQLATCH_GTW_EN_BMSK                                      0x1000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ZQLATCH_GTW_EN_SHFT                                           0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ZQLATCH_STAGGER_RANKS_EN_BMSK                             0x100000
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ZQLATCH_STAGGER_RANKS_EN_SHFT                                 0x14
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ZQLATCH_RANK_EN_BMSK                                       0x30000
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ZQLATCH_RANK_EN_SHFT                                          0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_RFU_13_12_BMSK                                              0x3000
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_RFU_13_12_SHFT                                                 0xc
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ZQSTART_GTW_EN_BMSK                                          0x100
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ZQSTART_GTW_EN_SHFT                                            0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ZQSTART_STAGGER_RANKS_EN_BMSK                                 0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ZQSTART_STAGGER_RANKS_EN_SHFT                                  0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ZQSTART_RANK_EN_BMSK                                           0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_ZQCAL_CFG_ZQSTART_RANK_EN_SHFT                                           0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_ZQCAL_ADDR                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x000006e0)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_ZQCAL_PHYS                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x000006e0)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_ZQCAL_OFFS                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x000006e0)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_ZQCAL_RMSK                                                 0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_ZQCAL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_ZQCAL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_ZQCAL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_ZQCAL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_ZQCAL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_ZQCAL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_ZQCAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_ZQCAL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_ZQCAL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_ZQCAL_CMD_SELECT_BMSK                                      0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_ZQCAL_CMD_SELECT_SHFT                                             0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_STALL_ADDR                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x000006e4)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_STALL_PHYS                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x000006e4)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_STALL_OFFS                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x000006e4)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_STALL_RMSK                                                 0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_STALL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_STALL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_STALL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_STALL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_STALL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_STALL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_STALL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_STALL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_STALL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_STALL_CMD_SELECT_BMSK                                      0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_STALL_CMD_SELECT_SHFT                                             0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_DUR_STALL_ADDR                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x000006e8)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_DUR_STALL_PHYS                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x000006e8)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_DUR_STALL_OFFS                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x000006e8)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_DUR_STALL_RMSK                                                0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_DUR_STALL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_DUR_STALL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_DUR_STALL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_DUR_STALL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_DUR_STALL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_DUR_STALL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_DUR_STALL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_DUR_STALL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_DUR_STALL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_DUR_STALL_CMD_SELECT_BMSK                                     0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_DUR_STALL_CMD_SELECT_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_UNSTALL_ADDR                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x000006ec)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_UNSTALL_PHYS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x000006ec)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_UNSTALL_OFFS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x000006ec)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_UNSTALL_RMSK                                               0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_UNSTALL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_UNSTALL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_UNSTALL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_UNSTALL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_UNSTALL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_UNSTALL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_UNSTALL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_UNSTALL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_UNSTALL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_UNSTALL_CMD_SELECT_BMSK                                    0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_MRW_BF_UNSTALL_CMD_SELECT_SHFT                                           0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_ADDR(n)                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000700 + 0x8 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_PHYS(n)                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000700 + 0x8 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_OFFS(n)                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000700 + 0x8 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_RMSK                                                    0xffff33ff
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_MAXn                                                            31
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_MR_DATA_BMSK                                            0xff000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_MR_DATA_SHFT                                                  0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_MR_ADDR_BMSK                                              0xff0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_MR_ADDR_SHFT                                                  0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_RANK_SEL_BMSK                                               0x3000
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_RANK_SEL_SHFT                                                  0xc
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_EVENT_SEL_BMSK                                               0x3ff
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_CFG_n_EVENT_SEL_SHFT                                                 0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_ADDR(n)                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000704 + 0x8 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_PHYS(n)                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000704 + 0x8 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_OFFS(n)                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000704 + 0x8 * (n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_RMSK                                             0x313ffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_MAXn                                                    31
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_INI(n)        \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_ADDR(n), HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_RMSK)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_INMI(n,mask)    \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_ADDR(n), mask)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_OUTI(n,val)    \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_ADDR(n),val)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_ADDR(n),mask,val,HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_INI(n))
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_RFU_25_24_BMSK                                   0x3000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_RFU_25_24_SHFT                                        0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_STAGGER_RANKS_EN_BMSK                             0x100000
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_STAGGER_RANKS_EN_SHFT                                 0x14
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_CLK_SELECT_BMSK                                    0x30000
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_CLK_SELECT_SHFT                                       0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_INTERVAL_BMSK                                       0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_CMD_SET_STAGGER_CFG_n_INTERVAL_SHFT                                          0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_ADDR                                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000800)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_PHYS                                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000800)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_OFFS                                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000800)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_RMSK                                                       0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_CMD_SELECT_BMSK                                            0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_CMD_SELECT_SHFT                                                   0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_TRIGGER_ADDR                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000804)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_TRIGGER_PHYS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000804)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_TRIGGER_OFFS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000804)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_TRIGGER_RMSK                                                          0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_TRIGGER_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_TRIGGER_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_TRIGGER_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_TRIGGER_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_TRIGGER_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_TRIGGER_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_TRIGGER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_TRIGGER_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_TRIGGER_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_TRIGGER_SEQ_TRIGGER_BMSK                                              0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_TRIGGER_SEQ_TRIGGER_SHFT                                              0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_ADDR                                                    (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000808)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_PHYS                                                    (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000808)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_OFFS                                                    (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000808)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_RMSK                                                         0x111
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_RFSH_HALT_BMSK                                               0x100
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_RFSH_HALT_SHFT                                                 0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_PERIOD_ARB_LOCK_BMSK                                          0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_PERIOD_ARB_LOCK_SHFT                                           0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_RFSH_ARB_LOCK_BMSK                                             0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_STALL_CTRL_RFSH_ARB_LOCK_SHFT                                             0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_ADDR                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000810)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_PHYS                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000810)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_OFFS                                             (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000810)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_RMSK                                                   0x33
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_RFU_5_4_BMSK                                           0x30
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_RFU_5_4_SHFT                                            0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_RANK_VOTE_EN_BMSK                                       0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_SELF_REFRESH_VOTE_RANK_VOTE_EN_SHFT                                       0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_PRIORITY_ADDR                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000814)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_PRIORITY_PHYS                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000814)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_PRIORITY_OFFS                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000814)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_PRIORITY_RMSK                                                     0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_PRIORITY_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_PRIORITY_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_PRIORITY_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_PRIORITY_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_PRIORITY_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_PRIORITY_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_PRIORITY_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_PRIORITY_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_PRIORITY_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_PRIORITY_PRIORITY_BMSK                                            0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_SEQ_PRIORITY_PRIORITY_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_CMD_SEQ_ADDR                                                     (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000820)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_CMD_SEQ_PHYS                                                     (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000820)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_CMD_SEQ_OFFS                                                     (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000820)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_CMD_SEQ_RMSK                                                     0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_CMD_SEQ_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_CMD_SEQ_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_CMD_SEQ_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_CMD_SEQ_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_CMD_SEQ_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_CMD_SEQ_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_CMD_SEQ_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_CMD_SEQ_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_CMD_SEQ_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_CMD_SEQ_CMD_SELECT_BMSK                                          0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_CMD_SEQ_CMD_SELECT_SHFT                                                 0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_DIT_CTRL_ADDR                                                    (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000824)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_DIT_CTRL_PHYS                                                    (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000824)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_DIT_CTRL_OFFS                                                    (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000824)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_DIT_CTRL_RMSK                                                           0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_DIT_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_DIT_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_DIT_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_DIT_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_DIT_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_DIT_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_DIT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_DIT_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_DIT_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_DIT_CTRL_ADIT_HALT_EN_BMSK                                              0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_DIT_CTRL_ADIT_HALT_EN_SHFT                                              0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_ADDR                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000830)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_PHYS                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000830)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_OFFS                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000830)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_RMSK                                                        0x11
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_FSP_OP_BMSK                                                 0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_FSP_OP_SHFT                                                  0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_FSP_OP_OVERRIDE_EN_BMSK                                      0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_OP_OVERRIDE_FSP_OP_OVERRIDE_EN_SHFT                                      0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_TIMEOUT_STATUS_ADDR                                          (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000840)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_TIMEOUT_STATUS_PHYS                                          (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000840)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_TIMEOUT_STATUS_OFFS                                          (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000840)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_TIMEOUT_STATUS_RMSK                                                0x11
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_TIMEOUT_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_TIMEOUT_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_TIMEOUT_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_TIMEOUT_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_TIMEOUT_STATUS_RANK1_BMSK                                          0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_TIMEOUT_STATUS_RANK1_SHFT                                           0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_TIMEOUT_STATUS_RANK0_BMSK                                           0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_TIMEOUT_STATUS_RANK0_SHFT                                           0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK0_ADDR                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000844)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK0_PHYS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000844)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK0_OFFS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000844)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK0_RMSK                                                   0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK0_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK0_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK0_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK0_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK0_MR_RDATA_BMSK                                          0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK0_MR_RDATA_SHFT                                                 0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK1_ADDR                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000848)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK1_PHYS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000848)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK1_OFFS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000848)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK1_RMSK                                                   0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK1_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK1_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK1_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK1_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK1_MR_RDATA_BMSK                                          0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR_RDATA_RANK1_MR_RDATA_SHFT                                                 0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_ADDR                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000900)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_PHYS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000900)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_OFFS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000900)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_RMSK                                                   0x3f3f3f3f
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_CA_CYCLE3_BMSK                                         0x3f000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_CA_CYCLE3_SHFT                                               0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_CA_CYCLE2_BMSK                                           0x3f0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_CA_CYCLE2_SHFT                                               0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_CA_CYCLE1_BMSK                                             0x3f00
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_CA_CYCLE1_SHFT                                                0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_CA_CYCLE0_BMSK                                               0x3f
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CA_CTRL_CA_CYCLE0_SHFT                                                0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_ADDR                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000904)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_PHYS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000904)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_OFFS                                               (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000904)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_RMSK                                               0x33333333
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_CKE_CYCLE3_BMSK                                    0x30000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_CKE_CYCLE3_SHFT                                          0x1c
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_CKE_CYCLE2_BMSK                                     0x3000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_CKE_CYCLE2_SHFT                                          0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_CKE_CYCLE1_BMSK                                      0x300000
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_CKE_CYCLE1_SHFT                                          0x14
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_CKE_CYCLE0_BMSK                                       0x30000
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_CKE_CYCLE0_SHFT                                          0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_CS_CYCLE3_BMSK                                         0x3000
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_CS_CYCLE3_SHFT                                            0xc
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_CS_CYCLE2_BMSK                                          0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_CS_CYCLE2_SHFT                                            0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_CS_CYCLE1_BMSK                                           0x30
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_CS_CYCLE1_SHFT                                            0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_CS_CYCLE0_BMSK                                            0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_CS_CKE_CTRL_CS_CYCLE0_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_DQ_CTRL_ADDR                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000908)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_DQ_CTRL_PHYS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000908)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_DQ_CTRL_OFFS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000908)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_DQ_CTRL_RMSK                                                         0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_DQ_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_DQ_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_DQ_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_DQ_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_DQ_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_DQ_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_DQ_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_DQ_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_DQ_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_DQ_CTRL_DQS_CYCLES_BMSK                                              0xff
#define HWIO_CABO_BROADCAST_CABO_SHKE_CUSTOM_DQ_CTRL_DQS_CYCLES_SHFT                                               0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN0_ADDR                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000910)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN0_PHYS                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000910)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN0_OFFS                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000910)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN0_RMSK                                                      0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN0_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN0_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN0_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN0_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN0_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN0_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN0_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN0_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN0_DQ_DATA_BMSK                                              0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN0_DQ_DATA_SHFT                                                     0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN1_ADDR                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000914)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN1_PHYS                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000914)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN1_OFFS                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000914)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN1_RMSK                                                      0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN1_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN1_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN1_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN1_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN1_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN1_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN1_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN1_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN1_DQ_DATA_BMSK                                              0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN1_DQ_DATA_SHFT                                                     0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_CTRL_ADDR                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000918)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_CTRL_PHYS                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000918)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_CTRL_OFFS                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000918)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_CTRL_RMSK                                                      0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_CTRL_PATTERN_SEL_BMSK                                          0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_CTRL_PATTERN_SEL_SHFT                                             0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_INV_CTRL_ADDR                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x0000091c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_INV_CTRL_PHYS                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x0000091c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_INV_CTRL_OFFS                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x0000091c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_INV_CTRL_RMSK                                                  0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_INV_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_INV_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_INV_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_INV_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_INV_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_INV_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_INV_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_INV_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_INV_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_INV_CTRL_PATTERN_INVERT_SEL_BMSK                               0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_DQ_PATTERN_INV_CTRL_PATTERN_INVERT_SEL_SHFT                                  0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_ADDR                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000920)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_PHYS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000920)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_OFFS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000920)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_RMSK                                                          0x7
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_NUM_RCH_BEATS_BMSK                                            0x7
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_NUM_RCH_BEATS_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_ADDR                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000924)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_PHYS                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000924)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_OFFS                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000924)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_RMSK                                                0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_BYTE1_PASS_BMSK                                     0xffff0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_BYTE1_PASS_SHFT                                           0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_BYTE0_PASS_BMSK                                         0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_BYTE0_PASS_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_1_ADDR                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000928)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_1_PHYS                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000928)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_1_OFFS                                                 (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000928)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_1_RMSK                                                        0x7
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_1_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_1_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_1_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_1_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_1_NUM_RCH_BEATS_BMSK                                          0x7
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_BEAT_STATUS_1_NUM_RCH_BEATS_SHFT                                          0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_1_ADDR                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x0000092c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_1_PHYS                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x0000092c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_1_OFFS                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x0000092c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_1_RMSK                                              0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_1_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_1_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_1_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_1_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_1_BYTE1_PASS_BMSK                                   0xffff0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_1_BYTE1_PASS_SHFT                                         0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_1_BYTE0_PASS_BMSK                                       0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_RD_COMPARE_STATUS_1_BYTE0_PASS_SHFT                                          0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_MPC_RWFIFO_CTRL_ADDR                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000940)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MPC_RWFIFO_CTRL_PHYS                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000940)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MPC_RWFIFO_CTRL_OFFS                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000940)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MPC_RWFIFO_CTRL_RMSK                                                         0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_MPC_RWFIFO_CTRL_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_MPC_RWFIFO_CTRL_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MPC_RWFIFO_CTRL_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_MPC_RWFIFO_CTRL_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MPC_RWFIFO_CTRL_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_MPC_RWFIFO_CTRL_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MPC_RWFIFO_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_MPC_RWFIFO_CTRL_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_MPC_RWFIFO_CTRL_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MPC_RWFIFO_CTRL_RANK_PEND_EN_BMSK                                            0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_MPC_RWFIFO_CTRL_RANK_PEND_EN_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MASK_ADDR                                            (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000980)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MASK_PHYS                                            (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000980)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MASK_OFFS                                            (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000980)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MASK_RMSK                                            0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MASK_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MASK_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MASK_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MASK_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MASK_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MASK_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MASK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MASK_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MASK_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MASK_MASK_VALUE_BMSK                                 0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MASK_MASK_VALUE_SHFT                                        0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MATCH_ADDR                                           (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000984)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MATCH_PHYS                                           (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000984)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MATCH_OFFS                                           (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000984)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MATCH_RMSK                                           0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MATCH_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MATCH_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MATCH_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MATCH_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MATCH_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MATCH_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MATCH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MATCH_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MATCH_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MATCH_MATCH_VALUE_BMSK                               0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_MATCH_MATCH_VALUE_SHFT                                      0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MASK_ADDR                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000988)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MASK_PHYS                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000988)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MASK_OFFS                                         (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000988)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MASK_RMSK                                         0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MASK_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MASK_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MASK_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MASK_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MASK_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MASK_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MASK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MASK_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MASK_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MASK_HP_MASK_VALUE_BMSK                           0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MASK_HP_MASK_VALUE_SHFT                                  0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_ADDR                                        (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x0000098c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_PHYS                                        (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x0000098c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_OFFS                                        (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x0000098c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_RMSK                                        0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_HP_MATCH_VALUE_BMSK                         0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_HP_MATCH_VALUE_SHFT                                0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_SPARE_REG_ADDR                                                        (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000a00)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SPARE_REG_PHYS                                                        (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000a00)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SPARE_REG_OFFS                                                        (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000a00)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SPARE_REG_RMSK                                                        0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_SPARE_REG_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_SPARE_REG_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SPARE_REG_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_SPARE_REG_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SPARE_REG_OUT(v)      \
        out_dword(HWIO_CABO_BROADCAST_CABO_SHKE_SPARE_REG_ADDR,v)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SPARE_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CABO_BROADCAST_CABO_SHKE_SPARE_REG_ADDR,m,v,HWIO_CABO_BROADCAST_CABO_SHKE_SPARE_REG_IN)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SPARE_REG_SPARE_FIELD_BMSK                                            0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_SPARE_REG_SPARE_FIELD_SHFT                                                   0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_IDLE_STATUS_ADDR                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000b00)
#define HWIO_CABO_BROADCAST_CABO_SHKE_IDLE_STATUS_PHYS                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000b00)
#define HWIO_CABO_BROADCAST_CABO_SHKE_IDLE_STATUS_OFFS                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000b00)
#define HWIO_CABO_BROADCAST_CABO_SHKE_IDLE_STATUS_RMSK                                                      0x80030000
#define HWIO_CABO_BROADCAST_CABO_SHKE_IDLE_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_IDLE_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_IDLE_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_IDLE_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_IDLE_STATUS_CLKON_BMSK                                                0x80000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_IDLE_STATUS_CLKON_SHFT                                                      0x1f
#define HWIO_CABO_BROADCAST_CABO_SHKE_IDLE_STATUS_RANK_IDLE_BMSK                                               0x30000
#define HWIO_CABO_BROADCAST_CABO_SHKE_IDLE_STATUS_RANK_IDLE_SHFT                                                  0x10

#define HWIO_CABO_BROADCAST_CABO_SHKE_BANK_UNAVAIL_STATUS_ADDR                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000b04)
#define HWIO_CABO_BROADCAST_CABO_SHKE_BANK_UNAVAIL_STATUS_PHYS                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000b04)
#define HWIO_CABO_BROADCAST_CABO_SHKE_BANK_UNAVAIL_STATUS_OFFS                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000b04)
#define HWIO_CABO_BROADCAST_CABO_SHKE_BANK_UNAVAIL_STATUS_RMSK                                                  0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_BANK_UNAVAIL_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_BANK_UNAVAIL_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_BANK_UNAVAIL_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_BANK_UNAVAIL_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_BANK_UNAVAIL_STATUS_UNAVAIL_STATUS_BMSK                                   0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_BANK_UNAVAIL_STATUS_UNAVAIL_STATUS_SHFT                                      0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_ADDR                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000b08)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_PHYS                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000b08)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_OFFS                                              (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000b08)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_RMSK                                                 0x33333
#define HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_SELF_REFRESH_BUSY_BMSK                               0x30000
#define HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_SELF_REFRESH_BUSY_SHFT                                  0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_FSW_SELF_REFRESH_BMSK                                 0x3000
#define HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_FSW_SELF_REFRESH_SHFT                                    0xc
#define HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_WDOG_SELF_REFRESH_BMSK                                 0x300
#define HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_WDOG_SELF_REFRESH_SHFT                                   0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_SW_SELF_REFRESH_BMSK                                    0x30
#define HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_SW_SELF_REFRESH_SHFT                                     0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_SELF_REFRESH_BMSK                                        0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_SELF_REFRESH_STATUS_SELF_REFRESH_SHFT                                        0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_STATUS_ADDR                                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000b0c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_STATUS_PHYS                                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000b0c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_STATUS_OFFS                                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000b0c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_STATUS_RMSK                                                       0xdf1fffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_FSW_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_STATUS_FSM_STATE_BMSK                                             0xc0000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_STATUS_FSM_STATE_SHFT                                                   0x1e
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_STATUS_CURR_FSW_ACK_STATE_BMSK                                    0x1f000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_STATUS_CURR_FSW_ACK_STATE_SHFT                                          0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_STATUS_CURR_FSW_REQ_STATE_BMSK                                      0x1f0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_STATUS_CURR_FSW_REQ_STATE_SHFT                                          0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_STATUS_TASK_COMPLETE_BMSK                                             0xffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSW_STATUS_TASK_COMPLETE_SHFT                                                0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_STATUS_ADDR                                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000b10)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_STATUS_PHYS                                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000b10)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_STATUS_OFFS                                                       (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000b10)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_STATUS_RMSK                                                              0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_FSP_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_FSP_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_STATUS_CURR_FSP_BMSK                                                     0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_FSP_STATUS_CURR_FSP_SHFT                                                     0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_ACK_STATUS_ADDR                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000b14)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_ACK_STATUS_PHYS                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000b14)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_ACK_STATUS_OFFS                                                (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000b14)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_ACK_STATUS_RMSK                                                      0x11
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_ACK_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_ACK_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_ACK_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_ACK_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_ACK_STATUS_DT_ACK_BMSK                                               0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_ACK_STATUS_DT_ACK_SHFT                                                0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_ACK_STATUS_DT_REQ_BMSK                                                0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_DT_REQ_ACK_STATUS_DT_REQ_SHFT                                                0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQCAL_STATUS_ADDR                                                     (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000b18)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQCAL_STATUS_PHYS                                                     (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000b18)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQCAL_STATUS_OFFS                                                     (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000b18)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQCAL_STATUS_RMSK                                                            0x7
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQCAL_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_ZQCAL_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQCAL_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_ZQCAL_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQCAL_STATUS_ZQCAL_FSM_STATE_BMSK                                            0x7
#define HWIO_CABO_BROADCAST_CABO_SHKE_ZQCAL_STATUS_ZQCAL_FSM_STATE_SHFT                                            0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_ADDR                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000b1c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_PHYS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000b1c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_OFFS                                                   (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000b1c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_RMSK                                                   0x777f7f33
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_RANK1_REFRESH_RATE_BMSK                                0x70000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_RANK1_REFRESH_RATE_SHFT                                      0x1c
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_RANK0_REFRESH_RATE_BMSK                                 0x7000000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_RANK0_REFRESH_RATE_SHFT                                      0x18
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_RANK1_CREDIT_COUNT_BMSK                                  0x700000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_RANK1_CREDIT_COUNT_SHFT                                      0x14
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_RANK1_PEND_COUNT_BMSK                                     0xf0000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_RANK1_PEND_COUNT_SHFT                                        0x10
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_RANK0_CREDIT_COUNT_BMSK                                    0x7000
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_RANK0_CREDIT_COUNT_SHFT                                       0xc
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_RANK0_PEND_COUNT_BMSK                                       0xf00
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_RANK0_PEND_COUNT_SHFT                                         0x8
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_REFRESH_OVERFLOW_BMSK                                        0x30
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_REFRESH_OVERFLOW_SHFT                                         0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_REFRESH_PENDING_BMSK                                          0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_REFRESH_STATUS_REFRESH_PENDING_SHFT                                          0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK1_ADDR                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000b20)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK1_PHYS                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000b20)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK1_OFFS                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000b20)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK1_RMSK                                                  0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK1_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK1_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK1_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK1_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK1_MR4_RDATA_BMSK                                        0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK1_MR4_RDATA_SHFT                                               0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK0_ADDR                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000b24)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK0_PHYS                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000b24)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK0_OFFS                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000b24)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK0_RMSK                                                  0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK0_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK0_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK0_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK0_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK0_MR4_RDATA_BMSK                                        0xffffffff
#define HWIO_CABO_BROADCAST_CABO_SHKE_MR4_RDATA_RANK0_MR4_RDATA_SHFT                                               0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_STATUS_ADDR                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000b28)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_STATUS_PHYS                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000b28)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_STATUS_OFFS                                                      (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000b28)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_STATUS_RMSK                                                           0x1f1
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_STATUS_FSM_STATE_BMSK                                                 0x1f0
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_STATUS_FSM_STATE_SHFT                                                   0x4
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_STATUS_PRE_ARES_DONE_BMSK                                               0x1
#define HWIO_CABO_BROADCAST_CABO_SHKE_WDOG_STATUS_PRE_ARES_DONE_SHFT                                               0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_STATUS_ADDR                                                    (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000b2c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_STATUS_PHYS                                                    (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000b2c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_STATUS_OFFS                                                    (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000b2c)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_STATUS_RMSK                                                           0xf
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_STATUS_FSM_STATE_BMSK                                                 0xf
#define HWIO_CABO_BROADCAST_CABO_SHKE_SW_CMD_STATUS_FSM_STATE_SHFT                                                 0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_STALL_STATUS_ADDR                                                     (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000b30)
#define HWIO_CABO_BROADCAST_CABO_SHKE_STALL_STATUS_PHYS                                                     (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000b30)
#define HWIO_CABO_BROADCAST_CABO_SHKE_STALL_STATUS_OFFS                                                     (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000b30)
#define HWIO_CABO_BROADCAST_CABO_SHKE_STALL_STATUS_RMSK                                                            0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_STALL_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_STALL_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_STALL_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_STALL_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_STALL_STATUS_FSM_STATE_BMSK                                                  0x3
#define HWIO_CABO_BROADCAST_CABO_SHKE_STALL_STATUS_FSM_STATE_SHFT                                                  0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_DTC_CTRL_STATUS_ADDR                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000b34)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DTC_CTRL_STATUS_PHYS                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000b34)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DTC_CTRL_STATUS_OFFS                                                  (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000b34)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DTC_CTRL_STATUS_RMSK                                                        0x1f
#define HWIO_CABO_BROADCAST_CABO_SHKE_DTC_CTRL_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_DTC_CTRL_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DTC_CTRL_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_DTC_CTRL_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_DTC_CTRL_STATUS_FSM_STATE_BMSK                                              0x1f
#define HWIO_CABO_BROADCAST_CABO_SHKE_DTC_CTRL_STATUS_FSM_STATE_SHFT                                               0x0

#define HWIO_CABO_BROADCAST_CABO_SHKE_SR_STATUS_ADDR                                                        (CABO_BROADCAST_CABO_SHKE_REG_BASE      + 0x00000b38)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SR_STATUS_PHYS                                                        (CABO_BROADCAST_CABO_SHKE_REG_BASE_PHYS + 0x00000b38)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SR_STATUS_OFFS                                                        (CABO_BROADCAST_CABO_SHKE_REG_BASE_OFFS + 0x00000b38)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SR_STATUS_RMSK                                                             0x3ff
#define HWIO_CABO_BROADCAST_CABO_SHKE_SR_STATUS_IN          \
        in_dword(HWIO_CABO_BROADCAST_CABO_SHKE_SR_STATUS_ADDR)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SR_STATUS_INM(m)      \
        in_dword_masked(HWIO_CABO_BROADCAST_CABO_SHKE_SR_STATUS_ADDR, m)
#define HWIO_CABO_BROADCAST_CABO_SHKE_SR_STATUS_FSM_STATE_1_BMSK                                                 0x3e0
#define HWIO_CABO_BROADCAST_CABO_SHKE_SR_STATUS_FSM_STATE_1_SHFT                                                   0x5
#define HWIO_CABO_BROADCAST_CABO_SHKE_SR_STATUS_FSM_STATE_0_BMSK                                                  0x1f
#define HWIO_CABO_BROADCAST_CABO_SHKE_SR_STATUS_FSM_STATE_0_SHFT                                                   0x0

/*----------------------------------------------------------------------------
 * MODULE: MC_BROADCAST_MC5_SHKE
 *--------------------------------------------------------------------------*/

#define MC_BROADCAST_MC5_SHKE_REG_BASE                                                                             (DDR_SS_BASE      + 0x00675000)
#define MC_BROADCAST_MC5_SHKE_REG_BASE_SIZE                                                                        0x1000
#define MC_BROADCAST_MC5_SHKE_REG_BASE_USED                                                                        0xf00
#define MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS                                                                        (DDR_SS_BASE_PHYS + 0x00675000)
#define MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS                                                                        0x00675000

#define HWIO_MC_BROADCAST_MC5_SHKE_LOAD_CONFIG_ADDR                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000020)
#define HWIO_MC_BROADCAST_MC5_SHKE_LOAD_CONFIG_PHYS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000020)
#define HWIO_MC_BROADCAST_MC5_SHKE_LOAD_CONFIG_OFFS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000020)
#define HWIO_MC_BROADCAST_MC5_SHKE_LOAD_CONFIG_RMSK                                                                       0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_LOAD_CONFIG_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_LOAD_CONFIG_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_LOAD_CONFIG_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_LOAD_CONFIG_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_LOAD_CONFIG_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_LOAD_CONFIG_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_LOAD_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_LOAD_CONFIG_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_LOAD_CONFIG_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_LOAD_CONFIG_LOAD_CONFIG_BMSK                                                           0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_LOAD_CONFIG_LOAD_CONFIG_SHFT                                                           0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_ADDR                                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000030)
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_PHYS                                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000030)
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_OFFS                                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000030)
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_RMSK                                                                       0x37ff
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_RFU_13_12_BMSK                                                             0x3000
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_RFU_13_12_SHFT                                                                0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_SW_LOAD_ASYNC_CG_EN_BMSK                                                    0x400
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_SW_LOAD_ASYNC_CG_EN_SHFT                                                      0xa
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_EVENT_ASYNC_CG_EN_BMSK                                                      0x200
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_EVENT_ASYNC_CG_EN_SHFT                                                        0x9
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_ARB_CG_EN_BMSK                                                              0x100
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_ARB_CG_EN_SHFT                                                                0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_SW_CMD_CG_EN_BMSK                                                            0x80
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_SW_CMD_CG_EN_SHFT                                                             0x7
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_FSW_CG_EN_BMSK                                                               0x40
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_FSW_CG_EN_SHFT                                                                0x6
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_DIT_CG_EN_BMSK                                                               0x20
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_DIT_CG_EN_SHFT                                                                0x5
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_SELF_REFRESH_CG_EN_BMSK                                                      0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_SELF_REFRESH_CG_EN_SHFT                                                       0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_REFRESH_CG_EN_BMSK                                                            0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_REFRESH_CG_EN_SHFT                                                            0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_ZQ_CG_EN_BMSK                                                                 0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_ZQ_CG_EN_SHFT                                                                 0x2
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_INTERVAL_TIMER_CG_EN_BMSK                                                     0x2
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_INTERVAL_TIMER_CG_EN_SHFT                                                     0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_STALL_CG_EN_BMSK                                                              0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_CLK_CTRL_STALL_CG_EN_SHFT                                                              0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_ADDR                                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000040)
#define HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_PHYS                                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000040)
#define HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_OFFS                                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000040)
#define HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_RMSK                                                                          0x737
#define HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_DEVICE_CFG_RANK1_BMSK                                                         0x700
#define HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_DEVICE_CFG_RANK1_SHFT                                                           0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_RANK_EN_BMSK                                                                   0x30
#define HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_RANK_EN_SHFT                                                                    0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_DEVICE_CFG_BMSK                                                                 0x7
#define HWIO_MC_BROADCAST_MC5_SHKE_CONFIG_DEVICE_CFG_SHFT                                                                 0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_ADDR                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000050)
#define HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_PHYS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000050)
#define HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_OFFS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000050)
#define HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_RMSK                                                                       0xf
#define HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_RFU_3_2_BMSK                                                               0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_RFU_3_2_SHFT                                                               0x2
#define HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_RANK_READY_BMSK                                                            0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_INIT_CONFIG_RANK_READY_SHFT                                                            0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_ADDR                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000060)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_PHYS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000060)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_OFFS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000060)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_RMSK                                                                    0x3333
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_DQ3_BMSK                                                                0x3000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_DQ3_SHFT                                                                   0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_DQ2_BMSK                                                                 0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_DQ2_SHFT                                                                   0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_DQ1_BMSK                                                                  0x30
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_DQ1_SHFT                                                                   0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_DQ0_BMSK                                                                   0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_BYTE_MAP_DQ0_SHFT                                                                   0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_MRR_SAMPLE_INDEX_ADDR                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000064)
#define HWIO_MC_BROADCAST_MC5_SHKE_MRR_SAMPLE_INDEX_PHYS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000064)
#define HWIO_MC_BROADCAST_MC5_SHKE_MRR_SAMPLE_INDEX_OFFS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000064)
#define HWIO_MC_BROADCAST_MC5_SHKE_MRR_SAMPLE_INDEX_RMSK                                                                  0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_MRR_SAMPLE_INDEX_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_MRR_SAMPLE_INDEX_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_MRR_SAMPLE_INDEX_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_MRR_SAMPLE_INDEX_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_MRR_SAMPLE_INDEX_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_MRR_SAMPLE_INDEX_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_MRR_SAMPLE_INDEX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_MRR_SAMPLE_INDEX_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_MRR_SAMPLE_INDEX_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_MRR_SAMPLE_INDEX_SAMPLE_INDEX_BMSK                                                     0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_MRR_SAMPLE_INDEX_SAMPLE_INDEX_SHFT                                                     0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_ADDR                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000080)
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_PHYS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000080)
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_OFFS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000080)
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_RMSK                                                           0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_TYPE3_STALL_CYCLES_BMSK                                        0xff000000
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_TYPE3_STALL_CYCLES_SHFT                                              0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_TYPE2_STALL_CYCLES_BMSK                                          0xff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_TYPE2_STALL_CYCLES_SHFT                                              0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_TYPE1_STALL_CYCLES_BMSK                                            0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_TYPE1_STALL_CYCLES_SHFT                                               0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_TYPE0_STALL_CYCLES_BMSK                                              0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CFG_TYPE0_STALL_CYCLES_SHFT                                               0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_ADDR                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000084)
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_PHYS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000084)
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_OFFS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000084)
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_RMSK                                                           0x1ffff0f
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_MSI_FSW_STALL_ACK_DELAY_EN_BMSK                                0x1000000
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_MSI_FSW_STALL_ACK_DELAY_EN_SHFT                                     0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_MSI_FSW_STALL_ACK_DELAY_CYCLES_BMSK                             0xff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_MSI_FSW_STALL_ACK_DELAY_CYCLES_SHFT                                 0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_STALL_CYCLES_OFFSET_BMSK                                          0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_STALL_CYCLES_OFFSET_SHFT                                             0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_RFU_3_2_BMSK                                                         0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_RFU_3_2_SHFT                                                         0x2
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_PRIORITY_BMSK                                                        0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_FINITE_STALL_CTRL_PRIORITY_SHFT                                                        0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_ADDR                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000090)
#define HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_PHYS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000090)
#define HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_OFFS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000090)
#define HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_RMSK                                                                0x311
#define HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_DERATE_STALL_TYPE_BMSK                                              0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_DERATE_STALL_TYPE_SHFT                                                0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_DERATE_STALL_EN_BMSK                                                 0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_DERATE_STALL_EN_SHFT                                                  0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_DERATE_REQ_EN_BMSK                                                    0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_TEMP_DERATE_CTRL_DERATE_REQ_EN_SHFT                                                    0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_ADDR                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000000a0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_PHYS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000000a0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_OFFS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000000a0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_RMSK                                                                  0xff0731
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_DT_STALL_CYCLES_THRESHOLD_BMSK                                        0xff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_DT_STALL_CYCLES_THRESHOLD_SHFT                                            0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_RFU_10_9_BMSK                                                            0x600
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_RFU_10_9_SHFT                                                              0x9
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_DT_PRIORITY_BMSK                                                         0x100
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_DT_PRIORITY_SHFT                                                           0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_DT_TYPE_BMSK                                                              0x30
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_DT_TYPE_SHFT                                                               0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_DT_REQ_EN_BMSK                                                             0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_CTRL_DT_REQ_EN_SHFT                                                             0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_ADDR(n)                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000100 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_PHYS(n)                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000100 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_OFFS(n)                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000100 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_RMSK                                                      0xd113ffff
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_MAXn                                                               4
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_RFU_31_30_BMSK                                            0xc0000000
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_RFU_31_30_SHFT                                                  0x1e
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_SW_LOAD_BMSK                                              0x10000000
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_SW_LOAD_SHFT                                                    0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_PREDECESSOR_TRIGGER_EN_BMSK                                0x1000000
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_PREDECESSOR_TRIGGER_EN_SHFT                                     0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_AUTO_LOAD_EN_BMSK                                           0x100000
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_AUTO_LOAD_EN_SHFT                                               0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_CLK_SELECT_BMSK                                              0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_CLK_SELECT_SHFT                                                 0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_INTERVAL_BMSK                                                 0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_TIMER_CTRL_n_INTERVAL_SHFT                                                    0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_ADDR(n)                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000108 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_PHYS(n)                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000108 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_OFFS(n)                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000108 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_RMSK                                                       0x333fff3
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_MAXn                                                               4
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_ESCALATED_PRIORITY_BMSK                                    0x3000000
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_ESCALATED_PRIORITY_SHFT                                         0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_PRIORITY_BMSK                                               0x300000
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_PRIORITY_SHFT                                                   0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_EVENT_SELECT_BMSK                                            0x3ff00
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_EVENT_SELECT_SHFT                                                0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_RFU_7_5_BMSK                                                    0xe0
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_RFU_7_5_SHFT                                                     0x5
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_EVENT_EN_BMSK                                                   0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_EVENT_EN_SHFT                                                    0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_RANK_EN_BMSK                                                     0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_CTRL_n_RANK_EN_SHFT                                                     0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_ADDR(n)                                           (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000010c + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_PHYS(n)                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000010c + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_OFFS(n)                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000010c + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_RMSK                                              0xffff0311
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_MAXn                                                       4
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_STAGGER_RANKS_OFFSET_BMSK                         0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_STAGGER_RANKS_OFFSET_SHFT                               0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_RFU_9_8_BMSK                                           0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_RFU_9_8_SHFT                                             0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_GLOBAL_TIMER_WINDOW_EN_BMSK                             0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_GLOBAL_TIMER_WINDOW_EN_SHFT                              0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_STAGGER_RANKS_EN_BMSK                                    0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STAGGER_CTRL_n_STAGGER_RANKS_EN_SHFT                                    0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STATUS_n_ADDR(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000110 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STATUS_n_PHYS(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000110 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STATUS_n_OFFS(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000110 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STATUS_n_RMSK                                                          0x33
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STATUS_n_MAXn                                                             4
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STATUS_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STATUS_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STATUS_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STATUS_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STATUS_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STATUS_n_EVENT_OVERFLOW_BMSK                                           0x30
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STATUS_n_EVENT_OVERFLOW_SHFT                                            0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STATUS_n_EVENT_PENDING_BMSK                                             0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_INTERVAL_EVENT_STATUS_n_EVENT_PENDING_SHFT                                             0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_ADDR                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000200)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_PHYS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000200)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_OFFS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000200)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_RMSK                                                         0xd113ffff
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_RFU_31_30_BMSK                                               0xc0000000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_RFU_31_30_SHFT                                                     0x1e
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_SW_LOAD_BMSK                                                 0x10000000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_SW_LOAD_SHFT                                                       0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_RFU_24_BMSK                                                   0x1000000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_RFU_24_SHFT                                                        0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_AUTO_LOAD_EN_BMSK                                              0x100000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_AUTO_LOAD_EN_SHFT                                                  0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_CLK_SELECT_BMSK                                                 0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_CLK_SELECT_SHFT                                                    0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_INTERVAL_BMSK                                                    0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_TIMER_CTRL_INTERVAL_SHFT                                                       0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_ADDR                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000208)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_PHYS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000208)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_OFFS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000208)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_RMSK                                                          0x3300313
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_ESCALATED_PRIORITY_BMSK                                       0x3000000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_ESCALATED_PRIORITY_SHFT                                            0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_PRIORITY_BMSK                                                  0x300000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_PRIORITY_SHFT                                                      0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_RFU_9_8_BMSK                                                      0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_RFU_9_8_SHFT                                                        0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_EVENT_EN_BMSK                                                      0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_EVENT_EN_SHFT                                                       0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_RANK_EN_BMSK                                                        0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_EVENT_CTRL_RANK_EN_SHFT                                                        0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_ADDR                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000020c)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_PHYS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000020c)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_OFFS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000020c)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_RMSK                                                       0xffff0311
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_STAGGER_RANKS_OFFSET_BMSK                                  0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_STAGGER_RANKS_OFFSET_SHFT                                        0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_RFU_9_8_BMSK                                                    0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_RFU_9_8_SHFT                                                      0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_GLOBAL_TIMER_WINDOW_EN_BMSK                                      0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_GLOBAL_TIMER_WINDOW_EN_SHFT                                       0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_STAGGER_RANKS_EN_BMSK                                             0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STAGGER_CTRL_STAGGER_RANKS_EN_SHFT                                             0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STATUS_ADDR                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000210)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STATUS_PHYS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000210)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STATUS_OFFS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000210)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STATUS_RMSK                                                                   0x33
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STATUS_EVENT_OVERFLOW_BMSK                                                    0x30
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STATUS_EVENT_OVERFLOW_SHFT                                                     0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STATUS_EVENT_PENDING_BMSK                                                      0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTART_STATUS_EVENT_PENDING_SHFT                                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_ADDR                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000220)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_PHYS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000220)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_OFFS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000220)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_RMSK                                                         0xd113ffff
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_RFU_31_30_BMSK                                               0xc0000000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_RFU_31_30_SHFT                                                     0x1e
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_SW_LOAD_BMSK                                                 0x10000000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_SW_LOAD_SHFT                                                       0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_ZQSTART_TRIGGER_EN_BMSK                                       0x1000000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_ZQSTART_TRIGGER_EN_SHFT                                            0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_AUTO_LOAD_EN_BMSK                                              0x100000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_AUTO_LOAD_EN_SHFT                                                  0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_CLK_SELECT_BMSK                                                 0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_CLK_SELECT_SHFT                                                    0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_INTERVAL_BMSK                                                    0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_TIMER_CTRL_INTERVAL_SHFT                                                       0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_ADDR                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000228)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_PHYS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000228)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_OFFS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000228)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_RMSK                                                          0x3300313
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_ESCALATED_PRIORITY_BMSK                                       0x3000000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_ESCALATED_PRIORITY_SHFT                                            0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_PRIORITY_BMSK                                                  0x300000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_PRIORITY_SHFT                                                      0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_RFU_9_8_BMSK                                                      0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_RFU_9_8_SHFT                                                        0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_EVENT_EN_BMSK                                                      0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_EVENT_EN_SHFT                                                       0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_RANK_EN_BMSK                                                        0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_EVENT_CTRL_RANK_EN_SHFT                                                        0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_ADDR                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000022c)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_PHYS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000022c)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_OFFS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000022c)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_RMSK                                                       0xffff0311
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_STAGGER_RANKS_OFFSET_BMSK                                  0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_STAGGER_RANKS_OFFSET_SHFT                                        0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_RFU_9_8_BMSK                                                    0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_RFU_9_8_SHFT                                                      0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_GLOBAL_TIMER_WINDOW_EN_BMSK                                      0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_GLOBAL_TIMER_WINDOW_EN_SHFT                                       0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_STAGGER_RANKS_EN_BMSK                                             0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STAGGER_CTRL_STAGGER_RANKS_EN_SHFT                                             0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STATUS_ADDR                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000230)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STATUS_PHYS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000230)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STATUS_OFFS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000230)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STATUS_RMSK                                                                   0x33
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STATUS_EVENT_OVERFLOW_BMSK                                                    0x30
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STATUS_EVENT_OVERFLOW_SHFT                                                     0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STATUS_EVENT_PENDING_BMSK                                                      0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQLATCH_STATUS_EVENT_PENDING_SHFT                                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_ADDR                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000234)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_PHYS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000234)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_OFFS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000234)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_RMSK                                                          0xd113ffff
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_RFU_31_30_BMSK                                                0xc0000000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_RFU_31_30_SHFT                                                      0x1e
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_SW_LOAD_BMSK                                                  0x10000000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_SW_LOAD_SHFT                                                        0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_ZQSTART_TRIGGER_EN_BMSK                                        0x1000000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_ZQSTART_TRIGGER_EN_SHFT                                             0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_AUTO_LOAD_EN_BMSK                                               0x100000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_AUTO_LOAD_EN_SHFT                                                   0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_CLK_SELECT_BMSK                                                  0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_CLK_SELECT_SHFT                                                     0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_INTERVAL_BMSK                                                     0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_TIMER_CTRL_INTERVAL_SHFT                                                        0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_ADDR                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000238)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_PHYS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000238)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_OFFS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000238)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_RMSK                                                           0x3300313
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_ESCALATED_PRIORITY_BMSK                                        0x3000000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_ESCALATED_PRIORITY_SHFT                                             0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_PRIORITY_BMSK                                                   0x300000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_PRIORITY_SHFT                                                       0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_RFU_9_8_BMSK                                                       0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_RFU_9_8_SHFT                                                         0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_EVENT_EN_BMSK                                                       0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_EVENT_EN_SHFT                                                        0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_RANK_EN_BMSK                                                         0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_EVENT_CTRL_RANK_EN_SHFT                                                         0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_ADDR                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000023c)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_PHYS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000023c)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_OFFS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000023c)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_RMSK                                                        0xffff0311
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_STAGGER_RANKS_OFFSET_BMSK                                   0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_STAGGER_RANKS_OFFSET_SHFT                                         0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_RFU_9_8_BMSK                                                     0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_RFU_9_8_SHFT                                                       0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_GLOBAL_TIMER_WINDOW_EN_BMSK                                       0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_GLOBAL_TIMER_WINDOW_EN_SHFT                                        0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_STAGGER_RANKS_EN_BMSK                                              0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STAGGER_CTRL_STAGGER_RANKS_EN_SHFT                                              0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_ADDR(n)                                               (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000240 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_PHYS(n)                                               (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000240 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_OFFS(n)                                               (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000240 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_RMSK                                                  0xd001ffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_MAXn                                                           1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_RFU_31_30_BMSK                                        0xc0000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_RFU_31_30_SHFT                                              0x1e
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_SW_LOAD_BMSK                                          0x10000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_SW_LOAD_SHFT                                                0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_AUTO_LOAD_EN_BMSK                                        0x10000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_AUTO_LOAD_EN_SHFT                                           0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_TREFI_1P0X_BMSK                                           0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_RANK_n_TREFI_1P0X_SHFT                                              0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_ADDR                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000248)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_PHYS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000248)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_OFFS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000248)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_RMSK                                                          0x33f1333
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_ESCALATED_PRIORITY_BMSK                                       0x3000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_ESCALATED_PRIORITY_SHFT                                            0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_PRIORITY_BMSK                                                  0x300000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_PRIORITY_SHFT                                                      0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_REFRESH_PB_BA_MASK_2B_MODE_BMSK                                 0xf0000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_REFRESH_PB_BA_MASK_2B_MODE_SHFT                                    0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_REFRESH_PB_1B_MODE_BMSK                                          0x1000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_REFRESH_PB_1B_MODE_SHFT                                             0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_RFU_9_8_BMSK                                                      0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_RFU_9_8_SHFT                                                        0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_REFRESH_PB_RANK_EN_BMSK                                            0x30
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_REFRESH_PB_RANK_EN_SHFT                                             0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_RANK_EN_BMSK                                                        0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_EVENT_CTRL_RANK_EN_SHFT                                                        0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_ADDR                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000024c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_PHYS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000024c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_OFFS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000024c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_RMSK                                                            0x371
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_RFU_9_8_BMSK                                                    0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_RFU_9_8_SHFT                                                      0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_STAGGER_DIS_DEBIT_THRESHOLD_BMSK                                 0x70
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_STAGGER_DIS_DEBIT_THRESHOLD_SHFT                                  0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_STAGGER_RANKS_EN_BMSK                                             0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STAGGER_CTRL_STAGGER_RANKS_EN_SHFT                                             0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_ADDR(n)                                                    (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000250 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_PHYS(n)                                                    (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000250 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_OFFS(n)                                                    (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000250 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_RMSK                                                       0xf1fff337
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_MAXn                                                                3
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_AB_BANK_THRESHOLD_BMSK                             0xf0000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_AB_BANK_THRESHOLD_SHFT                                   0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_PB_TREFI_DIV8_EN_BMSK                               0x1000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_PB_TREFI_DIV8_EN_SHFT                                    0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_TIMING_MODE_BMSK                                     0x800000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_TIMING_MODE_SHFT                                         0x17
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_PULL_IN_LIMIT_EN_BMSK                                0x400000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_PULL_IN_LIMIT_EN_SHFT                                    0x16
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_RFU_21_17_BMSK                                               0x3e0000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_RFU_21_17_SHFT                                                   0x11
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_RDYLVL_IGNORE_BMSK                                    0x10000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_RDYLVL_IGNORE_SHFT                                       0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_BUSY_BANKS_THRESHOLD_BMSK                              0xf000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_BUSY_BANKS_THRESHOLD_SHFT                                 0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_RDYLVL_BUSY_THRESHOLD_BMSK                              0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_RDYLVL_BUSY_THRESHOLD_SHFT                                0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_RDYLVL_THRESHOLD_BMSK                                    0x30
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_RDYLVL_THRESHOLD_SHFT                                     0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_AB_DEBIT_THRESHOLD_BMSK                                   0x7
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_DEBIT_CTRL_n_REFRESH_AB_DEBIT_THRESHOLD_SHFT                                   0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_ADDR                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000270)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_PHYS                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000270)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_OFFS                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000270)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_RMSK                                                     0xf91ffff1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_REFRESH_RATE_THRESHOLD_BMSK                              0xf8000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_REFRESH_RATE_THRESHOLD_SHFT                                    0x1b
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_REFRESH_RATE_THRESHOLD_EN_BMSK                            0x1000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_REFRESH_RATE_THRESHOLD_EN_SHFT                                 0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_REFRESH_PB_FREQ_THRESHOLD_BMSK                             0x1ffff0
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_REFRESH_PB_FREQ_THRESHOLD_SHFT                                  0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_REFRESH_PB_FREQ_THRESHOLD_EN_BMSK                               0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_AB_SWITCH_CTRL_REFRESH_PB_FREQ_THRESHOLD_EN_SHFT                               0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_ADDR                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000274)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_PHYS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000274)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_OFFS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000274)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_RMSK                                                         0xf1ffff11
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_RFU_31_BMSK                                                  0x80000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_RFU_31_SHFT                                                        0x1f
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_REFRESH_CREDIT_BURST_LEN_BMSK                                0x70000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_REFRESH_CREDIT_BURST_LEN_SHFT                                      0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_REFRESH_BURST_FREQ_THRESHOLD_BMSK                             0x1ffff00
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_REFRESH_BURST_FREQ_THRESHOLD_SHFT                                   0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_REFRESH_BURST_FREQ_THRESHOLD_EN_BMSK                               0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_REFRESH_BURST_FREQ_THRESHOLD_EN_SHFT                                0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_REFRESH_BURST_EN_BMSK                                               0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_CTRL_REFRESH_BURST_EN_SHFT                                               0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_ADDR                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000278)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_PHYS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000278)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_OFFS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000278)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_RMSK                                                            0x800001f1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_RFU_31_BMSK                                                     0x80000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_RFU_31_SHFT                                                           0x1f
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_REFRESH_RATE_TPBR2PBR_THRESHOLD_BMSK                                 0x1f0
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_REFRESH_RATE_TPBR2PBR_THRESHOLD_SHFT                                   0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_REFRESH_RATE_TPBR2PBR_THRESHOLD_EN_BMSK                                0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PB_CTRL_REFRESH_RATE_TPBR2PBR_THRESHOLD_EN_SHFT                                0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_ADDR                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000027c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_PHYS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000027c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_OFFS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000027c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_RMSK                                                       0xbff1f111
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_RFU_31_BMSK                                                0x80000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_RFU_31_SHFT                                                      0x1f
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_REFRESH_PEND_OFFSET_NEW_TREFI_EN_BMSK                      0x20000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_REFRESH_PEND_OFFSET_NEW_TREFI_EN_SHFT                            0x1d
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_REFRESH_RATE_PEND_OFFSET_NEW_TREFI_THRESHOLD_BMSK          0x1f000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_REFRESH_RATE_PEND_OFFSET_NEW_TREFI_THRESHOLD_SHFT                0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_REFRESH_PEND_OFFSET_NEW_TREFI_BMSK                           0xf00000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_REFRESH_PEND_OFFSET_NEW_TREFI_SHFT                               0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_REFRESH_RATE_SR_EXTRA_RFSH_EXCLUDE_THRESHOLD_BMSK             0x1f000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_REFRESH_RATE_SR_EXTRA_RFSH_EXCLUDE_THRESHOLD_SHFT                 0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_SR_EXTRA_RFSH_EXCLUDE_EN_BMSK                                   0x100
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_SR_EXTRA_RFSH_EXCLUDE_EN_SHFT                                     0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_REFRESH_MRR_VALID_INDUCED_TREFI_PULSE_EN_BMSK                    0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_REFRESH_MRR_VALID_INDUCED_TREFI_PULSE_EN_SHFT                     0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_REFRESH_DONE_BASED_COUNT_PULL_IN_EN_BMSK                          0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_CTRL_REFRESH_DONE_BASED_COUNT_PULL_IN_EN_SHFT                          0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_ADDR                                              (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000280)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_PHYS                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000280)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_OFFS                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000280)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_RMSK                                                   0x311
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_RFU_9_8_BMSK                                           0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_RFU_9_8_SHFT                                             0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_TEMP_UPDATE_FLAG_OVERRIDE_BMSK                          0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_TEMP_UPDATE_FLAG_OVERRIDE_SHFT                           0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_TEMP_UPDATE_TIMER_EN_BMSK                                0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_UPDATE_TIMER_CFG_TEMP_UPDATE_TIMER_EN_SHFT                                0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_ADDR                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000284)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_PHYS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000284)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_OFFS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000284)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_RMSK                                                          0x1f01f
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_LOW_TEMP_THRESHOLD_BMSK                                       0x1f000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_LOW_TEMP_THRESHOLD_SHFT                                           0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_HIGH_TEMP_THRESHOLD_BMSK                                         0x1f
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TEMP_ERR_CFG_HIGH_TEMP_THRESHOLD_SHFT                                          0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_ADDR                                                (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000288)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_PHYS                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000288)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_OFFS                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000288)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_RMSK                                                0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_REFRESH_PULL_IN_THRESHOLD_2P0X_BMSK                 0xf0000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_REFRESH_PULL_IN_THRESHOLD_2P0X_SHFT                       0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_REFRESH_PULL_IN_THRESHOLD_1P7X_BMSK                  0xf000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_REFRESH_PULL_IN_THRESHOLD_1P7X_SHFT                       0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_REFRESH_PULL_IN_THRESHOLD_1P3X_BMSK                   0xf00000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_REFRESH_PULL_IN_THRESHOLD_1P3X_SHFT                       0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_REFRESH_PULL_IN_THRESHOLD_1P0X_BMSK                    0xf0000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_REFRESH_PULL_IN_THRESHOLD_1P0X_SHFT                       0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_REFRESH_PULL_IN_THRESHOLD_0P7X_BMSK                     0xf000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_REFRESH_PULL_IN_THRESHOLD_0P7X_SHFT                        0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_REFRESH_PULL_IN_THRESHOLD_0P5X_BMSK                      0xf00
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_REFRESH_PULL_IN_THRESHOLD_0P5X_SHFT                        0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_REFRESH_PULL_IN_THRESHOLD_0P25X_BMSK                      0xf0
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_REFRESH_PULL_IN_THRESHOLD_0P25X_SHFT                       0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_REFRESH_PULL_IN_THRESHOLD_0P125X_BMSK                      0xf
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_1_REFRESH_PULL_IN_THRESHOLD_0P125X_SHFT                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_ADDR                                                (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000028c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_PHYS                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000028c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_OFFS                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000028c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_RMSK                                                  0xffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_RFU_23_20_BMSK                                        0xf00000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_RFU_23_20_SHFT                                            0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_REFRESH_PULL_IN_THRESHOLD_8P0X_BMSK                    0xf0000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_REFRESH_PULL_IN_THRESHOLD_8P0X_SHFT                       0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_REFRESH_PULL_IN_THRESHOLD_6P0X_BMSK                     0xf000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_REFRESH_PULL_IN_THRESHOLD_6P0X_SHFT                        0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_REFRESH_PULL_IN_THRESHOLD_4P0X_BMSK                      0xf00
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_REFRESH_PULL_IN_THRESHOLD_4P0X_SHFT                        0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_REFRESH_PULL_IN_THRESHOLD_3P3X_BMSK                       0xf0
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_REFRESH_PULL_IN_THRESHOLD_3P3X_SHFT                        0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_REFRESH_PULL_IN_THRESHOLD_2P5X_BMSK                        0xf
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_PULL_IN_LIMIT_CFG_2_REFRESH_PULL_IN_THRESHOLD_2P5X_SHFT                        0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_ADDR                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000290)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_PHYS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000290)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_OFFS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000290)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_RMSK                                                          0x800001f1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_RFU_31_BMSK                                                   0x80000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_RFU_31_SHFT                                                         0x1f
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_REFRESH_RATE_OVERRIDE_BMSK                                         0x1f0
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_REFRESH_RATE_OVERRIDE_SHFT                                           0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_REFRESH_RATE_OVERRIDE_EN_BMSK                                        0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_CTRL_REFRESH_RATE_OVERRIDE_EN_SHFT                                        0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_ADDR(n)                                            (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000300 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_PHYS(n)                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000300 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_OFFS(n)                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000300 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_RMSK                                                  0x3ffff
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_MAXn                                                        3
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_RFU_17_16_BMSK                                        0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_RFU_17_16_SHFT                                           0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_IDLE_TIMER_BMSK                                        0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_TIMER_CTRL_n_IDLE_TIMER_SHFT                                           0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_ADDR                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000328)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_PHYS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000328)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_OFFS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000328)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_RMSK                                                       0x7330f933
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_REFRESH_FLUSH_B4_SRE_BMSK                                  0x40000000
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_REFRESH_FLUSH_B4_SRE_SHFT                                        0x1e
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_REFRESH_AFTER_SRX_EN_BMSK                                  0x20000000
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_REFRESH_AFTER_SRX_EN_SHFT                                        0x1d
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_REFRESH_BEFORE_SRE_EN_BMSK                                 0x10000000
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_REFRESH_BEFORE_SRE_EN_SHFT                                       0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_SRX_PRIORITY_BMSK                                           0x3000000
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_SRX_PRIORITY_SHFT                                                0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_SRE_PRIORITY_BMSK                                            0x300000
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_SRE_PRIORITY_SHFT                                                0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_RFU_15_14_BMSK                                                 0xc000
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_RFU_15_14_SHFT                                                    0xe
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_RFU_13_12_BMSK                                                 0x3000
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_RFU_13_12_SHFT                                                    0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_SRPD_CMD_EN_BMSK                                                0x800
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_SRPD_CMD_EN_SHFT                                                  0xb
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_CONCURRENT_SR_EN_BMSK                                           0x100
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_CONCURRENT_SR_EN_SHFT                                             0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_SR_ABORT_EN_BMSK                                                 0x30
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_SR_ABORT_EN_SHFT                                                  0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_RANK_EN_BMSK                                                      0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_SELF_REFRESH_CTRL_RANK_EN_SHFT                                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_ADDR                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000032c)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_PHYS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000032c)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_OFFS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000032c)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_RMSK                                                           0x3ffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_CLK_SELECT_BMSK                                                0x3000000
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_CLK_SELECT_SHFT                                                     0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_RFU_23_16_BMSK                                                  0xff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_RFU_23_16_SHFT                                                      0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_TPDN_BMSK                                                         0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_TPDN_SHFT                                                            0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_IDLE_TIMER_BMSK                                                     0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_IDLE_TIMER_SHFT                                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_ADDR                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000330)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_PHYS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000330)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_OFFS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000330)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_RMSK                                                        0xff03ffff
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_RFU_31_24_BMSK                                              0xff000000
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_RFU_31_24_SHFT                                                    0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_CLK_SELECT_BMSK                                                0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_CLK_SELECT_SHFT                                                   0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_TXSR_DSM_BMSK                                                   0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_TIMER_CTRL_1_TXSR_DSM_SHFT                                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_ADDR                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000334)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_PHYS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000334)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_OFFS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000334)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_RMSK                                                                   0xfff33
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_DSMX_PRIORITY_BMSK                                                     0xc0000
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_DSMX_PRIORITY_SHFT                                                        0x12
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_DSME_PRIORITY_BMSK                                                     0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_DSME_PRIORITY_SHFT                                                        0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_RFU_15_8_BMSK                                                           0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_RFU_15_8_SHFT                                                              0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_DSM_EN_BMSK                                                               0x20
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_DSM_EN_SHFT                                                                0x5
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_CONCURRENT_DSM_EN_BMSK                                                    0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_CONCURRENT_DSM_EN_SHFT                                                     0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_RANK_EN_BMSK                                                               0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_HW_DSM_CTRL_RANK_EN_SHFT                                                               0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_ADDR                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000340)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_PHYS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000340)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_OFFS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000340)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_RMSK                                                         0xd003ffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_RFU_31_30_BMSK                                               0xc0000000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_RFU_31_30_SHFT                                                     0x1e
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_SW_LOAD_BMSK                                                 0x10000000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_SW_LOAD_SHFT                                                       0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_CLK_SELECT_BMSK                                                 0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_CLK_SELECT_SHFT                                                    0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_ACQ_INTERVAL_BMSK                                                0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_TIMER_CTRL_ACQ_INTERVAL_SHFT                                                   0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_ADDR                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000348)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_PHYS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000348)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_OFFS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000348)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_RMSK                                                          0x33ff313
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_ESCALATED_PRIORITY_BMSK                                       0x3000000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_ESCALATED_PRIORITY_SHFT                                            0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_PRIORITY_BMSK                                                  0x300000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_PRIORITY_SHFT                                                      0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_NUM_SAMPLES_BMSK                                                0xff000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_NUM_SAMPLES_SHFT                                                    0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_RFU_9_8_BMSK                                                      0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_RFU_9_8_SHFT                                                        0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_MPC_STOP_EN_BMSK                                                   0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_MPC_STOP_EN_SHFT                                                    0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_RANK_EN_BMSK                                                        0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_EVENT_CTRL_RANK_EN_SHFT                                                        0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_ADDR                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000034c)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_PHYS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000034c)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_OFFS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000034c)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_RMSK                                                       0xffff0301
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_STAGGER_RANKS_OFFSET_BMSK                                  0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_STAGGER_RANKS_OFFSET_SHFT                                        0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_RFU_9_8_BMSK                                                    0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_RFU_9_8_SHFT                                                      0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_STAGGER_RANKS_EN_BMSK                                             0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_ACQ_STAGGER_CTRL_STAGGER_RANKS_EN_SHFT                                             0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_ADDR                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000360)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_PHYS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000360)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_OFFS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000360)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_RMSK                                                        0xd003ffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_RFU_31_30_BMSK                                              0xc0000000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_RFU_31_30_SHFT                                                    0x1e
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_SW_LOAD_BMSK                                                0x10000000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_SW_LOAD_SHFT                                                      0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_CLK_SELECT_BMSK                                                0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_CLK_SELECT_SHFT                                                   0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_TRAC_INTERVAL_BMSK                                              0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_TIMER_CTRL_TRAC_INTERVAL_SHFT                                                 0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_ADDR                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000364)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_PHYS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000364)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_OFFS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000364)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_RMSK                                                       0xffff0301
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_EVENT_OFFSET_BMSK                                          0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_EVENT_OFFSET_SHFT                                                0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_RFU_9_8_BMSK                                                    0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_RFU_9_8_SHFT                                                      0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_OFFSET_EN_BMSK                                                    0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_OFFSET_CTRL_OFFSET_EN_SHFT                                                    0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_ADDR                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000368)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_PHYS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000368)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_OFFS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000368)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_RMSK                                                         0x33ff313
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_ESCALATED_PRIORITY_BMSK                                      0x3000000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_ESCALATED_PRIORITY_SHFT                                           0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_PRIORITY_BMSK                                                 0x300000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_PRIORITY_SHFT                                                     0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_NUM_SAMPLES_BMSK                                               0xff000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_NUM_SAMPLES_SHFT                                                   0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_RFU_9_8_BMSK                                                     0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_RFU_9_8_SHFT                                                       0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_MPC_STOP_EN_BMSK                                                  0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_MPC_STOP_EN_SHFT                                                   0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_RANK_EN_BMSK                                                       0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_EVENT_CTRL_RANK_EN_SHFT                                                       0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_ADDR                                                      (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000036c)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_PHYS                                                      (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000036c)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_OFFS                                                      (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000036c)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_RMSK                                                      0xffff0301
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_STAGGER_RANKS_OFFSET_BMSK                                 0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_STAGGER_RANKS_OFFSET_SHFT                                       0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_RFU_9_8_BMSK                                                   0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_RFU_9_8_SHFT                                                     0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_STAGGER_RANKS_EN_BMSK                                            0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_STAGGER_CTRL_STAGGER_RANKS_EN_SHFT                                            0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_ADDR                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000370)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_PHYS                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000370)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_OFFS                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000370)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_RMSK                                                     0x301ffff1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_RFU_29_28_BMSK                                           0x30000000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_RFU_29_28_SHFT                                                 0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_TRAC_FREQ_THRESHOLD_BMSK                                   0x1ffff0
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_TRAC_FREQ_THRESHOLD_SHFT                                        0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_TRAC_FREQ_THRESHOLD_EN_BMSK                                     0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_TRAC_THRESHOLD_CFG_TRAC_FREQ_THRESHOLD_EN_SHFT                                     0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_ADDR                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000380)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_PHYS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000380)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_OFFS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000380)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_RMSK                                                         0xc3ffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_RFU_31_30_BMSK                                               0xc0000000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_RFU_31_30_SHFT                                                     0x1e
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_CLK_SELECT_BMSK                                               0x3000000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_CLK_SELECT_SHFT                                                    0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_MPC_STOP_TO_MRR_BMSK                                           0xff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_MPC_STOP_TO_MRR_SHFT                                               0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_MPC_START_TO_MRR_BMSK                                            0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_MRR_TIMER_CTRL_MPC_START_TO_MRR_SHFT                                               0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_ADDR                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000003a0)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_PHYS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000003a0)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_OFFS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000003a0)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_RMSK                                                               0x311
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_RFU_9_8_BMSK                                                       0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_RFU_9_8_SHFT                                                         0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_TRAC_PERIODIC_EVENT_EN_BMSK                                         0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_TRAC_PERIODIC_EVENT_EN_SHFT                                          0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_TRAC_EVENT_EN_BMSK                                                   0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_CFG_TRAC_EVENT_EN_SHFT                                                   0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_ADDR                                               (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000003a4)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_PHYS                                               (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000003a4)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_OFFS                                               (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000003a4)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_RMSK                                               0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_DIT_HIGH_THRESHOLD_BMSK                            0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_DIT_HIGH_THRESHOLD_SHFT                                  0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_DIT_LOW_THRESHOLD_BMSK                                 0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_FILTER_THRESHOLD_CFG_DIT_LOW_THRESHOLD_SHFT                                    0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_STATUS_ADDR                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000003b0)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_STATUS_PHYS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000003b0)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_STATUS_OFFS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000003b0)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_STATUS_RMSK                                                                    0xf
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_STATUS_FSM_STATE_BMSK                                                          0xf
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_STATUS_FSM_STATE_SHFT                                                          0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_STATUS_ADDR                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000003b4)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_STATUS_PHYS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000003b4)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_STATUS_OFFS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000003b4)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_STATUS_RMSK                                                          0x30011
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_STATUS_LAST_DIT_RANK_BMSK                                            0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_STATUS_LAST_DIT_RANK_SHFT                                               0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_STATUS_TRAC_PERIODIC_EVENT_STATUS_BMSK                                  0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_STATUS_TRAC_PERIODIC_EVENT_STATUS_SHFT                                   0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_STATUS_TRAC_EVENT_STATUS_BMSK                                            0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_EVENT_STATUS_TRAC_EVENT_STATUS_SHFT                                            0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_ADDR(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000003c0 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_PHYS(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000003c0 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_OFFS(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000003c0 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_RMSK                                                        0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_MAXn                                                             1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_MR_UPPER_BYTE_BMSK                                          0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_MR_UPPER_BYTE_SHFT                                             0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_MR_LOWER_BYTE_BMSK                                            0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK0_BYTE_n_MR_LOWER_BYTE_SHFT                                             0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_ADDR(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000003e0 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_PHYS(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000003e0 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_OFFS(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000003e0 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_RMSK                                                        0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_MAXn                                                             1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_MR_UPPER_BYTE_BMSK                                          0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_MR_UPPER_BYTE_SHFT                                             0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_MR_LOWER_BYTE_BMSK                                            0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_CNT_RNK1_BYTE_n_MR_LOWER_BYTE_SHFT                                             0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_ADDR(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000400 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_PHYS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000400 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_OFFS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000400 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_RMSK                                                      0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_MAXn                                                         1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_NUM_SAMPLES_BMSK                                          0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK0_BYTE_n_NUM_SAMPLES_SHFT                                           0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_ADDR(n)                                                (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000404 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_PHYS(n)                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000404 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_OFFS(n)                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000404 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_RMSK                                                   0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_MAXn                                                            1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_ACCU_VALUE_BMSK                                        0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK0_BYTE_n_ACCU_VALUE_SHFT                                               0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_ADDR(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000408 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_PHYS(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000408 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_OFFS(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000408 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_RMSK                                                        0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_MAXn                                                             1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_MR_UPPER_BYTE_BMSK                                          0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_MR_UPPER_BYTE_SHFT                                             0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_MR_LOWER_BYTE_BMSK                                            0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK0_BYTE_n_MR_LOWER_BYTE_SHFT                                             0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_ADDR(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000040c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_PHYS(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000040c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_OFFS(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000040c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_RMSK                                                        0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_MAXn                                                             1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_MR_UPPER_BYTE_BMSK                                          0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_MR_UPPER_BYTE_SHFT                                             0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_MR_LOWER_BYTE_BMSK                                            0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK0_BYTE_n_MR_LOWER_BYTE_SHFT                                             0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_ADDR(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000480 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_PHYS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000480 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_OFFS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000480 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_RMSK                                                      0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_MAXn                                                         1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_NUM_SAMPLES_BMSK                                          0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_SAMPLES_RNK1_BYTE_n_NUM_SAMPLES_SHFT                                           0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_ADDR(n)                                                (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000484 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_PHYS(n)                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000484 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_OFFS(n)                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000484 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_RMSK                                                   0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_MAXn                                                            1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_ACCU_VALUE_BMSK                                        0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_RNK1_BYTE_n_ACCU_VALUE_SHFT                                               0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_ADDR(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000488 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_PHYS(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000488 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_OFFS(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000488 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_RMSK                                                        0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_MAXn                                                             1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_MR_UPPER_BYTE_BMSK                                          0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_MR_UPPER_BYTE_SHFT                                             0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_MR_LOWER_BYTE_BMSK                                            0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_RNK1_BYTE_n_MR_LOWER_BYTE_SHFT                                             0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_ADDR(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000048c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_PHYS(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000048c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_OFFS(n)                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000048c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_RMSK                                                        0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_MAXn                                                             1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_MR_UPPER_BYTE_BMSK                                          0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_MR_UPPER_BYTE_SHFT                                             0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_MR_LOWER_BYTE_BMSK                                            0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_RNK1_BYTE_n_MR_LOWER_BYTE_SHFT                                             0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ADDR(n)                                         (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000504 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_PHYS(n)                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000504 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_OFFS(n)                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000504 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_RMSK                                            0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_MAXn                                                     1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ACCU_VALUE_BMSK                                 0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ACCU_VALUE_SHFT                                        0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_ADDR(n)                                          (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000508 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_PHYS(n)                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000508 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_OFFS(n)                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000508 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_RMSK                                                 0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_MAXn                                                      1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_MR_UPPER_BYTE_BMSK                                   0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_MR_UPPER_BYTE_SHFT                                      0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_MR_LOWER_BYTE_BMSK                                     0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_MR_LOWER_BYTE_SHFT                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_ADDR(n)                                          (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000050c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_PHYS(n)                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000050c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_OFFS(n)                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000050c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_RMSK                                                 0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_MAXn                                                      1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_MR_UPPER_BYTE_BMSK                                   0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_MR_UPPER_BYTE_SHFT                                      0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_MR_LOWER_BYTE_BMSK                                     0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_MR_LOWER_BYTE_SHFT                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ADDR(n)                                         (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000584 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_PHYS(n)                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000584 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_OFFS(n)                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000584 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_RMSK                                            0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_MAXn                                                     1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ACCU_VALUE_BMSK                                 0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ACCU_VALUE_SHFT                                        0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_ADDR(n)                                          (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000588 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_PHYS(n)                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000588 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_OFFS(n)                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000588 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_RMSK                                                 0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_MAXn                                                      1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_MR_UPPER_BYTE_BMSK                                   0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_MR_UPPER_BYTE_SHFT                                      0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_MR_LOWER_BYTE_BMSK                                     0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_MR_LOWER_BYTE_SHFT                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_ADDR(n)                                          (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000058c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_PHYS(n)                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000058c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_OFFS(n)                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000058c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_RMSK                                                 0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_MAXn                                                      1
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_MR_UPPER_BYTE_BMSK                                   0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_MR_UPPER_BYTE_SHFT                                      0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_MR_LOWER_BYTE_BMSK                                     0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_MR_LOWER_BYTE_SHFT                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_ADDR(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000005c0 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_PHYS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000005c0 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_OFFS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000005c0 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_RMSK                                                0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_MAXn                                                         1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_TREFI_0P25X_BMSK                                    0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_TREFI_0P25X_SHFT                                          0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_TREFI_0P125X_BMSK                                       0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_1_RANK_n_TREFI_0P125X_SHFT                                          0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_ADDR(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000005c4 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_PHYS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000005c4 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_OFFS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000005c4 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_RMSK                                                0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_MAXn                                                         1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_TREFI_0P7X_BMSK                                     0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_TREFI_0P7X_SHFT                                           0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_TREFI_0P5X_BMSK                                         0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_2_RANK_n_TREFI_0P5X_SHFT                                            0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_ADDR(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000005c8 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_PHYS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000005c8 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_OFFS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000005c8 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_RMSK                                                0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_MAXn                                                         1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_TREFI_1P7X_BMSK                                     0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_TREFI_1P7X_SHFT                                           0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_TREFI_1P3X_BMSK                                         0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_3_RANK_n_TREFI_1P3X_SHFT                                            0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_ADDR(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000005cc + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_PHYS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000005cc + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_OFFS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000005cc + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_RMSK                                                0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_MAXn                                                         1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_TREFI_2P5X_BMSK                                     0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_TREFI_2P5X_SHFT                                           0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_TREFI_2P0X_BMSK                                         0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_4_RANK_n_TREFI_2P0X_SHFT                                            0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_ADDR(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000005d0 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_PHYS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000005d0 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_OFFS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000005d0 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_RMSK                                                0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_MAXn                                                         1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_TREFI_4P0X_BMSK                                     0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_TREFI_4P0X_SHFT                                           0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_TREFI_3P3X_BMSK                                         0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_5_RANK_n_TREFI_3P3X_SHFT                                            0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_ADDR(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000005d4 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_PHYS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000005d4 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_OFFS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000005d4 + 0x20 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_RMSK                                                0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_MAXn                                                         1
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_TREFI_8P0X_BMSK                                     0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_TREFI_8P0X_SHFT                                           0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_TREFI_6P0X_BMSK                                         0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TIMER_CTRL_6_RANK_n_TREFI_6P0X_SHFT                                            0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_ADDR(n)                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000600 + 0x8 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_PHYS(n)                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000600 + 0x8 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_OFFS(n)                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000600 + 0x8 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_RMSK                                                             0x301f1f01
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_MAXn                                                                     15
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_RFU_29_28_BMSK                                                   0x30000000
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_RFU_29_28_SHFT                                                         0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_END_STATE_BMSK                                                     0x1f0000
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_END_STATE_SHFT                                                         0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_START_STATE_BMSK                                                     0x1f00
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_START_STATE_SHFT                                                        0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_TASK_EN_BMSK                                                            0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_CFG_n_TASK_EN_SHFT                                                            0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_ADDR(n)                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000604 + 0x8 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_PHYS(n)                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000604 + 0x8 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_OFFS(n)                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000604 + 0x8 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_RMSK                                                       0x1f0ffff
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_MAXn                                                              15
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_TIMER_DEPENDENCY_BMSK                                      0x1000000
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_TIMER_DEPENDENCY_SHFT                                           0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_RFU_23_20_BMSK                                              0xf00000
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_RFU_23_20_SHFT                                                  0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_TASK_DEPENDENCY_BMSK                                          0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_TASK_DEPENDENCY_n_TASK_DEPENDENCY_SHFT                                             0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_ADDR                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000006c0)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_PHYS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000006c0)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_OFFS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000006c0)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_RMSK                                                               0x31f
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_RFU_9_8_BMSK                                                       0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_RFU_9_8_SHFT                                                         0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_FSW_END_STATE_BMSK                                                  0x1f
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_END_STATE_CFG_FSW_END_STATE_SHFT                                                   0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_ADDR                                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000006c4)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_PHYS                                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000006c4)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_OFFS                                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000006c4)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_RMSK                                                                       0xf3
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_RFU_7_5_BMSK                                                               0xe0
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_RFU_7_5_SHFT                                                                0x5
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_DT_PRIORITY_BMSK                                                           0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_DT_PRIORITY_SHFT                                                            0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_DT_TYPE_BMSK                                                                0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_DT_CFG_DT_TYPE_SHFT                                                                0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ADDR                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000006c8)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_PHYS                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000006c8)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_OFFS                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000006c8)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_RMSK                                                              0x31133113
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_RFU_29_28_BMSK                                                    0x30000000
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_RFU_29_28_SHFT                                                          0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ZQLATCH_GTW_EN_BMSK                                                0x1000000
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ZQLATCH_GTW_EN_SHFT                                                     0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ZQLATCH_STAGGER_RANKS_EN_BMSK                                       0x100000
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ZQLATCH_STAGGER_RANKS_EN_SHFT                                           0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ZQLATCH_RANK_EN_BMSK                                                 0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ZQLATCH_RANK_EN_SHFT                                                    0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_RFU_13_12_BMSK                                                        0x3000
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_RFU_13_12_SHFT                                                           0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ZQSTART_GTW_EN_BMSK                                                    0x100
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ZQSTART_GTW_EN_SHFT                                                      0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ZQSTART_STAGGER_RANKS_EN_BMSK                                           0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ZQSTART_STAGGER_RANKS_EN_SHFT                                            0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ZQSTART_RANK_EN_BMSK                                                     0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_ZQCAL_CFG_ZQSTART_RANK_EN_SHFT                                                     0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_ZQCAL_ADDR                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000006e0)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_ZQCAL_PHYS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000006e0)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_ZQCAL_OFFS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000006e0)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_ZQCAL_RMSK                                                           0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_ZQCAL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_ZQCAL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_ZQCAL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_ZQCAL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_ZQCAL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_ZQCAL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_ZQCAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_ZQCAL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_ZQCAL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_ZQCAL_CMD_SELECT_BMSK                                                0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_ZQCAL_CMD_SELECT_SHFT                                                       0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_STALL_ADDR                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000006e4)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_STALL_PHYS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000006e4)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_STALL_OFFS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000006e4)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_STALL_RMSK                                                           0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_STALL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_STALL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_STALL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_STALL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_STALL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_STALL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_STALL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_STALL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_STALL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_STALL_CMD_SELECT_BMSK                                                0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_STALL_CMD_SELECT_SHFT                                                       0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_DUR_STALL_ADDR                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000006e8)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_DUR_STALL_PHYS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000006e8)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_DUR_STALL_OFFS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000006e8)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_DUR_STALL_RMSK                                                          0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_DUR_STALL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_DUR_STALL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_DUR_STALL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_DUR_STALL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_DUR_STALL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_DUR_STALL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_DUR_STALL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_DUR_STALL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_DUR_STALL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_DUR_STALL_CMD_SELECT_BMSK                                               0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_DUR_STALL_CMD_SELECT_SHFT                                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_UNSTALL_ADDR                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000006ec)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_UNSTALL_PHYS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000006ec)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_UNSTALL_OFFS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000006ec)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_UNSTALL_RMSK                                                         0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_UNSTALL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_UNSTALL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_UNSTALL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_UNSTALL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_UNSTALL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_UNSTALL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_UNSTALL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_UNSTALL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_UNSTALL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_UNSTALL_CMD_SELECT_BMSK                                              0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_MRW_BF_UNSTALL_CMD_SELECT_SHFT                                                     0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_ADDR(n)                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000700 + 0x8 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_PHYS(n)                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000700 + 0x8 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_OFFS(n)                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000700 + 0x8 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_RMSK                                                              0xffff33ff
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_MAXn                                                                      31
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_MR_DATA_BMSK                                                      0xff000000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_MR_DATA_SHFT                                                            0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_MR_ADDR_BMSK                                                        0xff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_MR_ADDR_SHFT                                                            0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_RANK_SEL_BMSK                                                         0x3000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_RANK_SEL_SHFT                                                            0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_EVENT_SEL_BMSK                                                         0x3ff
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_CFG_n_EVENT_SEL_SHFT                                                           0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_ADDR(n)                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000704 + 0x8 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_PHYS(n)                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000704 + 0x8 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_OFFS(n)                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000704 + 0x8 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_RMSK                                                       0x313ffff
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_MAXn                                                              31
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_RFU_25_24_BMSK                                             0x3000000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_RFU_25_24_SHFT                                                  0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_STAGGER_RANKS_EN_BMSK                                       0x100000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_STAGGER_RANKS_EN_SHFT                                           0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_CLK_SELECT_BMSK                                              0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_CLK_SELECT_SHFT                                                 0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_INTERVAL_BMSK                                                 0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET_STAGGER_CFG_n_INTERVAL_SHFT                                                    0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_ADDR                                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000800)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_PHYS                                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000800)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_OFFS                                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000800)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_RMSK                                                                 0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CMD_SELECT_BMSK                                                      0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CMD_SELECT_SHFT                                                             0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER_ADDR                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000804)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER_PHYS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000804)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER_OFFS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000804)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER_RMSK                                                                    0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER_SEQ_TRIGGER_BMSK                                                        0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER_SEQ_TRIGGER_SHFT                                                        0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_ADDR                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000808)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_PHYS                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000808)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_OFFS                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000808)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_RMSK                                                                   0x111
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_RFSH_HALT_BMSK                                                         0x100
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_RFSH_HALT_SHFT                                                           0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_PERIOD_ARB_LOCK_BMSK                                                    0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_PERIOD_ARB_LOCK_SHFT                                                     0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_RFSH_ARB_LOCK_BMSK                                                       0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_STALL_CTRL_RFSH_ARB_LOCK_SHFT                                                       0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_ADDR                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000810)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_PHYS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000810)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_OFFS                                                       (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000810)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_RMSK                                                             0x33
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_RFU_5_4_BMSK                                                     0x30
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_RFU_5_4_SHFT                                                      0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_RANK_VOTE_EN_BMSK                                                 0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_SELF_REFRESH_VOTE_RANK_VOTE_EN_SHFT                                                 0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_PRIORITY_ADDR                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000814)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_PRIORITY_PHYS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000814)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_PRIORITY_OFFS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000814)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_PRIORITY_RMSK                                                               0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_PRIORITY_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_PRIORITY_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_PRIORITY_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_PRIORITY_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_PRIORITY_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_PRIORITY_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_PRIORITY_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_PRIORITY_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_PRIORITY_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_PRIORITY_PRIORITY_BMSK                                                      0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_PRIORITY_PRIORITY_SHFT                                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_ADDR                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000818)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_PHYS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000818)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_OFFS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000818)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_RMSK                                                                0xff01
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_TFC_INTERVAL_BMSK                                                   0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_TFC_INTERVAL_SHFT                                                      0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_CMD_TIMER_CONC_EN_BMSK                                                 0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ_CTRL_CMD_TIMER_CONC_EN_SHFT                                                 0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ_ADDR                                                               (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000820)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ_PHYS                                                               (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000820)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ_OFFS                                                               (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000820)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ_RMSK                                                               0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ_CMD_SELECT_BMSK                                                    0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ_CMD_SELECT_SHFT                                                           0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_DIT_CTRL_ADDR                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000824)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_DIT_CTRL_PHYS                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000824)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_DIT_CTRL_OFFS                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000824)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_DIT_CTRL_RMSK                                                                     0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_DIT_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_WDOG_DIT_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_DIT_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_WDOG_DIT_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_DIT_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_WDOG_DIT_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_DIT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_WDOG_DIT_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_WDOG_DIT_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_DIT_CTRL_ADIT_HALT_EN_BMSK                                                        0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_DIT_CTRL_ADIT_HALT_EN_SHFT                                                        0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_ADDR                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000082c)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_PHYS                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000082c)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_OFFS                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000082c)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_RMSK                                                              0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_RFU_31_16_BMSK                                                    0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_RFU_31_16_SHFT                                                          0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_CMD_SELECT_BMSK                                                       0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_CMD_SEQ1_CMD_SELECT_SHFT                                                          0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_ADDR                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000830)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_PHYS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000830)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_OFFS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000830)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_RMSK                                                                  0x31
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_FSP_OP_BMSK                                                           0x30
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_FSP_OP_SHFT                                                            0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_FSP_OP_OVERRIDE_EN_BMSK                                                0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_OP_OVERRIDE_FSP_OP_OVERRIDE_EN_SHFT                                                0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_TIMEOUT_STATUS_ADDR                                                    (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000840)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_TIMEOUT_STATUS_PHYS                                                    (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000840)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_TIMEOUT_STATUS_OFFS                                                    (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000840)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_TIMEOUT_STATUS_RMSK                                                          0x11
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_TIMEOUT_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_TIMEOUT_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_TIMEOUT_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_TIMEOUT_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_TIMEOUT_STATUS_RANK1_BMSK                                                    0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_TIMEOUT_STATUS_RANK1_SHFT                                                     0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_TIMEOUT_STATUS_RANK0_BMSK                                                     0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_TIMEOUT_STATUS_RANK0_SHFT                                                     0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK0_ADDR                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000844)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK0_PHYS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000844)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK0_OFFS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000844)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK0_RMSK                                                             0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK0_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK0_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK0_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK0_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK0_MR_RDATA_BMSK                                                    0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK0_MR_RDATA_SHFT                                                           0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK1_ADDR                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000848)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK1_PHYS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000848)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK1_OFFS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000848)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK1_RMSK                                                             0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK1_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK1_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK1_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK1_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK1_MR_RDATA_BMSK                                                    0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_MR_RDATA_RANK1_MR_RDATA_SHFT                                                           0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_ADDR                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000900)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_PHYS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000900)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_OFFS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000900)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_RMSK                                                             0x7f7f7f7f
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_CA_CYCLE3_BMSK                                                   0x7f000000
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_CA_CYCLE3_SHFT                                                         0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_CA_CYCLE2_BMSK                                                     0x7f0000
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_CA_CYCLE2_SHFT                                                         0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_CA_CYCLE1_BMSK                                                       0x7f00
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_CA_CYCLE1_SHFT                                                          0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_CA_CYCLE0_BMSK                                                         0x7f
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_CTRL_CA_CYCLE0_SHFT                                                          0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_ADDR                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000904)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_PHYS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000904)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_OFFS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000904)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_RMSK                                                         0x33333333
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_CKE_CYCLE3_BMSK                                              0x30000000
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_CKE_CYCLE3_SHFT                                                    0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_CKE_CYCLE2_BMSK                                               0x3000000
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_CKE_CYCLE2_SHFT                                                    0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_CKE_CYCLE1_BMSK                                                0x300000
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_CKE_CYCLE1_SHFT                                                    0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_CKE_CYCLE0_BMSK                                                 0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_CKE_CYCLE0_SHFT                                                    0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_CS_CYCLE3_BMSK                                                   0x3000
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_CS_CYCLE3_SHFT                                                      0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_CS_CYCLE2_BMSK                                                    0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_CS_CYCLE2_SHFT                                                      0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_CS_CYCLE1_BMSK                                                     0x30
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_CS_CYCLE1_SHFT                                                      0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_CS_CYCLE0_BMSK                                                      0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CS_CKE_CTRL_CS_CYCLE0_SHFT                                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_DQ_CTRL_ADDR                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000908)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_DQ_CTRL_PHYS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000908)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_DQ_CTRL_OFFS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000908)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_DQ_CTRL_RMSK                                                                   0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_DQ_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_DQ_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_DQ_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_DQ_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_DQ_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_DQ_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_DQ_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_DQ_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_DQ_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_DQ_CTRL_DQS_CYCLES_BMSK                                                        0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_DQ_CTRL_DQS_CYCLES_SHFT                                                         0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_ADDR                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000090c)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_PHYS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000090c)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_OFFS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000090c)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_RMSK                                                           0x7f7f7f7f
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_CA_CYCLE3_BMSK                                                 0x7f000000
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_CA_CYCLE3_SHFT                                                       0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_CA_CYCLE2_BMSK                                                   0x7f0000
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_CA_CYCLE2_SHFT                                                       0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_CA_CYCLE1_BMSK                                                     0x7f00
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_CA_CYCLE1_SHFT                                                        0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_CA_CYCLE0_BMSK                                                       0x7f
#define HWIO_MC_BROADCAST_MC5_SHKE_CUSTOM_CA_N_CTRL_CA_CYCLE0_SHFT                                                        0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN0_ADDR                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000910)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN0_PHYS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000910)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN0_OFFS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000910)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN0_RMSK                                                                0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN0_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN0_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN0_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN0_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN0_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN0_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN0_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN0_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN0_DQ_DATA_BMSK                                                        0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN0_DQ_DATA_SHFT                                                               0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN1_ADDR                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000914)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN1_PHYS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000914)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN1_OFFS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000914)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN1_RMSK                                                                0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN1_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN1_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN1_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN1_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN1_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN1_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN1_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN1_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN1_DQ_DATA_BMSK                                                        0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN1_DQ_DATA_SHFT                                                               0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_CTRL_ADDR                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000918)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_CTRL_PHYS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000918)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_CTRL_OFFS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000918)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_CTRL_RMSK                                                                0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_CTRL_PATTERN_SEL_BMSK                                                    0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_CTRL_PATTERN_SEL_SHFT                                                       0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_INV_CTRL_ADDR                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000091c)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_INV_CTRL_PHYS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000091c)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_INV_CTRL_OFFS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000091c)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_INV_CTRL_RMSK                                                            0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_INV_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_INV_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_INV_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_INV_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_INV_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_INV_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_INV_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_INV_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_INV_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_INV_CTRL_PATTERN_INVERT_SEL_BMSK                                         0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQ_PATTERN_INV_CTRL_PATTERN_INVERT_SEL_SHFT                                            0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_ADDR                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000920)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_PHYS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000920)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_OFFS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000920)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_RMSK                                                                    0x7
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_NUM_RCH_BEATS_BMSK                                                      0x7
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_NUM_RCH_BEATS_SHFT                                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_ADDR                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000924)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_PHYS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000924)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_OFFS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000924)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_RMSK                                                          0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_BYTE1_PASS_BMSK                                               0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_BYTE1_PASS_SHFT                                                     0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_BYTE0_PASS_BMSK                                                   0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_BYTE0_PASS_SHFT                                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_1_ADDR                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000928)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_1_PHYS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000928)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_1_OFFS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000928)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_1_RMSK                                                                  0x7
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_1_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_1_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_1_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_1_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_1_NUM_RCH_BEATS_BMSK                                                    0x7
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_BEAT_STATUS_1_NUM_RCH_BEATS_SHFT                                                    0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_1_ADDR                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000092c)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_1_PHYS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000092c)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_1_OFFS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000092c)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_1_RMSK                                                        0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_1_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_1_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_1_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_1_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_1_BYTE1_PASS_BMSK                                             0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_1_BYTE1_PASS_SHFT                                                   0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_1_BYTE0_PASS_BMSK                                                 0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_RD_COMPARE_STATUS_1_BYTE0_PASS_SHFT                                                    0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_MPC_RWFIFO_CTRL_ADDR                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000940)
#define HWIO_MC_BROADCAST_MC5_SHKE_MPC_RWFIFO_CTRL_PHYS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000940)
#define HWIO_MC_BROADCAST_MC5_SHKE_MPC_RWFIFO_CTRL_OFFS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000940)
#define HWIO_MC_BROADCAST_MC5_SHKE_MPC_RWFIFO_CTRL_RMSK                                                                   0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_MPC_RWFIFO_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_MPC_RWFIFO_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_MPC_RWFIFO_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_MPC_RWFIFO_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_MPC_RWFIFO_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_MPC_RWFIFO_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_MPC_RWFIFO_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_MPC_RWFIFO_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_MPC_RWFIFO_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_MPC_RWFIFO_CTRL_RANK_PEND_EN_BMSK                                                      0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_MPC_RWFIFO_CTRL_RANK_PEND_EN_SHFT                                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MASK_ADDR                                                      (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000980)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MASK_PHYS                                                      (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000980)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MASK_OFFS                                                      (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000980)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MASK_RMSK                                                      0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MASK_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MASK_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MASK_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MASK_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MASK_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MASK_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MASK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MASK_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MASK_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MASK_MASK_VALUE_BMSK                                           0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MASK_MASK_VALUE_SHFT                                                  0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MATCH_ADDR                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000984)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MATCH_PHYS                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000984)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MATCH_OFFS                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000984)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MATCH_RMSK                                                     0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MATCH_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MATCH_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MATCH_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MATCH_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MATCH_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MATCH_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MATCH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MATCH_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MATCH_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MATCH_MATCH_VALUE_BMSK                                         0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_MATCH_MATCH_VALUE_SHFT                                                0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MASK_ADDR                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000988)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MASK_PHYS                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000988)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MASK_OFFS                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000988)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MASK_RMSK                                                   0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MASK_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MASK_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MASK_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MASK_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MASK_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MASK_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MASK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MASK_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MASK_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MASK_HP_MASK_VALUE_BMSK                                     0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MASK_HP_MASK_VALUE_SHFT                                            0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_ADDR                                                  (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x0000098c)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_PHYS                                                  (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x0000098c)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_OFFS                                                  (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x0000098c)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_RMSK                                                  0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_HP_MATCH_VALUE_BMSK                                   0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_GLOBAL_TIMER_HP_MATCH_HP_MATCH_VALUE_SHFT                                          0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_ADDR                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000990)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_PHYS                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000990)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_OFFS                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000990)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_RMSK                                                              0x1fffff0f
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_BANK_UNAVAIL_ARB_STG_BUBBLE_DISABLE_BMSK                          0x10000000
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_BANK_UNAVAIL_ARB_STG_BUBBLE_DISABLE_SHFT                                0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_BANK_UNAVAIL_VALID_VEC_BMSK                                        0xfff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_BANK_UNAVAIL_VALID_VEC_SHFT                                             0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_RFU_15_8_BMSK                                                         0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_RFU_15_8_SHFT                                                            0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_BANK_UNAVAIL_EARLY_CYCLES_EN_BMSK                                        0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_BANK_UNAVAIL_EARLY_CYCLES_EN_SHFT                                        0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_BANK_UNAVAIL_CTRL_DISABLE_BMSK                                           0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_BANK_UNAVAIL_CTRL_DISABLE_SHFT                                           0x2
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_EARLY_CAS_EN_BMSK                                                        0x2
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_EARLY_CAS_EN_SHFT                                                        0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_PRIORITY_INHERIT_EN_BMSK                                                 0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_ARB_MISC_CTRL_PRIORITY_INHERIT_EN_SHFT                                                 0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_ADDR                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000009a0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_PHYS                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000009a0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_OFFS                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000009a0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_RMSK                                                     0xd003ffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_RFU_31_30_BMSK                                           0xc0000000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_RFU_31_30_SHFT                                                 0x1e
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_SW_LOAD_BMSK                                             0x10000000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_SW_LOAD_SHFT                                                   0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_CLK_SELECT_BMSK                                             0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_CLK_SELECT_SHFT                                                0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_ACQ_INTERVAL_BMSK                                            0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_TIMER_CTRL_ACQ_INTERVAL_SHFT                                               0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_ADDR                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000009a8)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_PHYS                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000009a8)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_OFFS                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000009a8)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_RMSK                                                      0x33ff313
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_ESCALATED_PRIORITY_BMSK                                   0x3000000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_ESCALATED_PRIORITY_SHFT                                        0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_PRIORITY_BMSK                                              0x300000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_PRIORITY_SHFT                                                  0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_NUM_SAMPLES_BMSK                                            0xff000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_NUM_SAMPLES_SHFT                                                0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_RFU_9_8_BMSK                                                  0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_RFU_9_8_SHFT                                                    0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_MPC_STOP_EN_BMSK                                               0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_MPC_STOP_EN_SHFT                                                0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_RANK_EN_BMSK                                                    0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_EVENT_CTRL_RANK_EN_SHFT                                                    0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_ADDR                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000009ac)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_PHYS                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000009ac)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_OFFS                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000009ac)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_RMSK                                                   0xffff0301
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_STAGGER_RANKS_OFFSET_BMSK                              0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_STAGGER_RANKS_OFFSET_SHFT                                    0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_RFU_9_8_BMSK                                                0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_RFU_9_8_SHFT                                                  0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_STAGGER_RANKS_EN_BMSK                                         0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_ACQ_STAGGER_CTRL_STAGGER_RANKS_EN_SHFT                                         0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_ADDR                                                    (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000009b0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_PHYS                                                    (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000009b0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_OFFS                                                    (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000009b0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_RMSK                                                    0xd003ffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_RFU_31_30_BMSK                                          0xc0000000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_RFU_31_30_SHFT                                                0x1e
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_SW_LOAD_BMSK                                            0x10000000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_SW_LOAD_SHFT                                                  0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_CLK_SELECT_BMSK                                            0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_CLK_SELECT_SHFT                                               0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_TRAC_INTERVAL_BMSK                                          0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_TIMER_CTRL_TRAC_INTERVAL_SHFT                                             0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_ADDR                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000009b4)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_PHYS                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000009b4)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_OFFS                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000009b4)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_RMSK                                                   0xffff0301
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_EVENT_OFFSET_BMSK                                      0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_EVENT_OFFSET_SHFT                                            0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_RFU_9_8_BMSK                                                0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_RFU_9_8_SHFT                                                  0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_OFFSET_EN_BMSK                                                0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_OFFSET_CTRL_OFFSET_EN_SHFT                                                0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_ADDR                                                    (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000009b8)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_PHYS                                                    (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000009b8)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_OFFS                                                    (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000009b8)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_RMSK                                                     0x33ff313
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_ESCALATED_PRIORITY_BMSK                                  0x3000000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_ESCALATED_PRIORITY_SHFT                                       0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_PRIORITY_BMSK                                             0x300000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_PRIORITY_SHFT                                                 0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_NUM_SAMPLES_BMSK                                           0xff000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_NUM_SAMPLES_SHFT                                               0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_RFU_9_8_BMSK                                                 0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_RFU_9_8_SHFT                                                   0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_MPC_STOP_EN_BMSK                                              0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_MPC_STOP_EN_SHFT                                               0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_RANK_EN_BMSK                                                   0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_EVENT_CTRL_RANK_EN_SHFT                                                   0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_ADDR                                                  (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000009bc)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_PHYS                                                  (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000009bc)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_OFFS                                                  (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000009bc)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_RMSK                                                  0xffff0301
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_STAGGER_RANKS_OFFSET_BMSK                             0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_STAGGER_RANKS_OFFSET_SHFT                                   0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_RFU_9_8_BMSK                                               0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_RFU_9_8_SHFT                                                 0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_STAGGER_RANKS_EN_BMSK                                        0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_STAGGER_CTRL_STAGGER_RANKS_EN_SHFT                                        0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_ADDR                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000009c0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_PHYS                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000009c0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_OFFS                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000009c0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_RMSK                                                 0x301ffff1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_RFU_29_28_BMSK                                       0x30000000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_RFU_29_28_SHFT                                             0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_TRAC_FREQ_THRESHOLD_BMSK                               0x1ffff0
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_TRAC_FREQ_THRESHOLD_SHFT                                    0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_TRAC_FREQ_THRESHOLD_EN_BMSK                                 0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_TRAC_THRESHOLD_CFG_TRAC_FREQ_THRESHOLD_EN_SHFT                                 0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_ADDR                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000009c8)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_PHYS                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000009c8)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_OFFS                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000009c8)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_RMSK                                                     0xc3ffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_RFU_31_30_BMSK                                           0xc0000000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_RFU_31_30_SHFT                                                 0x1e
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_CLK_SELECT_BMSK                                           0x3000000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_CLK_SELECT_SHFT                                                0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_MPC_STOP_TO_MRR_BMSK                                       0xff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_MPC_STOP_TO_MRR_SHFT                                           0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_MPC_START_TO_MRR_BMSK                                        0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_MRR_TIMER_CTRL_MPC_START_TO_MRR_SHFT                                           0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_ADDR                                                      (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000009d0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_PHYS                                                      (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000009d0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_OFFS                                                      (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000009d0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_RMSK                                                           0x311
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_RFU_9_8_BMSK                                                   0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_RFU_9_8_SHFT                                                     0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_TRAC_PERIODIC_EVENT_EN_BMSK                                     0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_TRAC_PERIODIC_EVENT_EN_SHFT                                      0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_TRAC_EVENT_EN_BMSK                                               0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_CFG_TRAC_EVENT_EN_SHFT                                               0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_ADDR                                           (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000009d4)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_PHYS                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000009d4)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_OFFS                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000009d4)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_RMSK                                           0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_DIT_HIGH_THRESHOLD_BMSK                        0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_DIT_HIGH_THRESHOLD_SHFT                              0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_DIT_LOW_THRESHOLD_BMSK                             0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_FILTER_THRESHOLD_CFG_DIT_LOW_THRESHOLD_SHFT                                0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_STATUS_ADDR                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000009dc)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_STATUS_PHYS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000009dc)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_STATUS_OFFS                                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000009dc)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_STATUS_RMSK                                                                0xf
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_STATUS_FSM_STATE_BMSK                                                      0xf
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_STATUS_FSM_STATE_SHFT                                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_STATUS_ADDR                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000009e0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_STATUS_PHYS                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000009e0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_STATUS_OFFS                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000009e0)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_STATUS_RMSK                                                      0x30011
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_STATUS_LAST_DIT_RANK_BMSK                                        0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_STATUS_LAST_DIT_RANK_SHFT                                           0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_STATUS_TRAC_PERIODIC_EVENT_STATUS_BMSK                              0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_STATUS_TRAC_PERIODIC_EVENT_STATUS_SHFT                               0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_STATUS_TRAC_EVENT_STATUS_BMSK                                        0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_EVENT_STATUS_TRAC_EVENT_STATUS_SHFT                                        0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK0_BYTE_n_ADDR(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000009e4 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK0_BYTE_n_PHYS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000009e4 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK0_BYTE_n_OFFS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000009e4 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK0_BYTE_n_RMSK                                                    0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK0_BYTE_n_MAXn                                                         1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK0_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK0_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK0_BYTE_n_MR_UPPER_BYTE_DQO_BMSK                                  0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK0_BYTE_n_MR_UPPER_BYTE_DQO_SHFT                                     0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK0_BYTE_n_MR_LOWER_BYTE_DQO_BMSK                                    0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK0_BYTE_n_MR_LOWER_BYTE_DQO_SHFT                                     0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK1_BYTE_n_ADDR(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x000009f4 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK1_BYTE_n_PHYS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x000009f4 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK1_BYTE_n_OFFS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x000009f4 + 0x4 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK1_BYTE_n_RMSK                                                    0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK1_BYTE_n_MAXn                                                         1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK1_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK1_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK1_BYTE_n_MR_UPPER_BYTE_DQO_BMSK                                  0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK1_BYTE_n_MR_UPPER_BYTE_DQO_SHFT                                     0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK1_BYTE_n_MR_LOWER_BYTE_DQO_BMSK                                    0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_CNT_RNK1_BYTE_n_MR_LOWER_BYTE_DQO_SHFT                                     0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK0_BYTE_n_ADDR(n)                                         (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000a04 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK0_BYTE_n_PHYS(n)                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000a04 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK0_BYTE_n_OFFS(n)                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000a04 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK0_BYTE_n_RMSK                                                  0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK0_BYTE_n_MAXn                                                     1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK0_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK0_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK0_BYTE_n_NUM_SAMPLES_BMSK                                      0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK0_BYTE_n_NUM_SAMPLES_SHFT                                       0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK0_BYTE_n_ADDR(n)                                            (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000a08 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK0_BYTE_n_PHYS(n)                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000a08 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK0_BYTE_n_OFFS(n)                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000a08 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK0_BYTE_n_RMSK                                               0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK0_BYTE_n_MAXn                                                        1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK0_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK0_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK0_BYTE_n_ACCU_VALUE_BMSK                                    0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK0_BYTE_n_ACCU_VALUE_SHFT                                           0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK0_BYTE_n_ADDR(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000a0c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK0_BYTE_n_PHYS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000a0c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK0_BYTE_n_OFFS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000a0c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK0_BYTE_n_RMSK                                                    0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK0_BYTE_n_MAXn                                                         1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK0_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK0_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK0_BYTE_n_MR_UPPER_BYTE_DQO_BMSK                                  0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK0_BYTE_n_MR_UPPER_BYTE_DQO_SHFT                                     0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK0_BYTE_n_MR_LOWER_BYTE_DQO_BMSK                                    0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK0_BYTE_n_MR_LOWER_BYTE_DQO_SHFT                                     0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK0_BYTE_n_ADDR(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000a10 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK0_BYTE_n_PHYS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000a10 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK0_BYTE_n_OFFS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000a10 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK0_BYTE_n_RMSK                                                    0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK0_BYTE_n_MAXn                                                         1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK0_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK0_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK0_BYTE_n_MR_UPPER_BYTE_DQO_BMSK                                  0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK0_BYTE_n_MR_UPPER_BYTE_DQO_SHFT                                     0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK0_BYTE_n_MR_LOWER_BYTE_DQO_BMSK                                    0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK0_BYTE_n_MR_LOWER_BYTE_DQO_SHFT                                     0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK1_BYTE_n_ADDR(n)                                         (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000a44 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK1_BYTE_n_PHYS(n)                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000a44 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK1_BYTE_n_OFFS(n)                                         (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000a44 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK1_BYTE_n_RMSK                                                  0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK1_BYTE_n_MAXn                                                     1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK1_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK1_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK1_BYTE_n_NUM_SAMPLES_BMSK                                      0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_SAMPLES_RNK1_BYTE_n_NUM_SAMPLES_SHFT                                       0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK1_BYTE_n_ADDR(n)                                            (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000a48 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK1_BYTE_n_PHYS(n)                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000a48 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK1_BYTE_n_OFFS(n)                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000a48 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK1_BYTE_n_RMSK                                               0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK1_BYTE_n_MAXn                                                        1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK1_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK1_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK1_BYTE_n_ACCU_VALUE_BMSK                                    0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_RNK1_BYTE_n_ACCU_VALUE_SHFT                                           0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK1_BYTE_n_ADDR(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000a4c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK1_BYTE_n_PHYS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000a4c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK1_BYTE_n_OFFS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000a4c + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK1_BYTE_n_RMSK                                                    0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK1_BYTE_n_MAXn                                                         1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK1_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK1_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK1_BYTE_n_MR_UPPER_BYTE_DQO_BMSK                                  0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK1_BYTE_n_MR_UPPER_BYTE_DQO_SHFT                                     0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK1_BYTE_n_MR_LOWER_BYTE_DQO_BMSK                                    0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_RNK1_BYTE_n_MR_LOWER_BYTE_DQO_SHFT                                     0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK1_BYTE_n_ADDR(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000a50 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK1_BYTE_n_PHYS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000a50 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK1_BYTE_n_OFFS(n)                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000a50 + 0x10 * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK1_BYTE_n_RMSK                                                    0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK1_BYTE_n_MAXn                                                         1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK1_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK1_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK1_BYTE_n_MR_UPPER_BYTE_DQO_BMSK                                  0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK1_BYTE_n_MR_UPPER_BYTE_DQO_SHFT                                     0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK1_BYTE_n_MR_LOWER_BYTE_DQO_BMSK                                    0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_RNK1_BYTE_n_MR_LOWER_BYTE_DQO_SHFT                                     0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ADDR(n)                                     (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000a84 + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_PHYS(n)                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000a84 + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_OFFS(n)                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000a84 + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_RMSK                                        0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_MAXn                                                 1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ACCU_VALUE_BMSK                             0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK0_BYTE_n_ACCU_VALUE_SHFT                                    0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_ADDR(n)                                      (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000a88 + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_PHYS(n)                                      (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000a88 + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_OFFS(n)                                      (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000a88 + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_RMSK                                             0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_MAXn                                                  1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_MR_UPPER_BYTE_DQO_BMSK                           0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_MR_UPPER_BYTE_DQO_SHFT                              0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_MR_LOWER_BYTE_DQO_BMSK                             0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK0_BYTE_n_MR_LOWER_BYTE_DQO_SHFT                              0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_ADDR(n)                                      (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000a8c + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_PHYS(n)                                      (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000a8c + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_OFFS(n)                                      (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000a8c + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_RMSK                                             0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_MAXn                                                  1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_MR_UPPER_BYTE_DQO_BMSK                           0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_MR_UPPER_BYTE_DQO_SHFT                              0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_MR_LOWER_BYTE_DQO_BMSK                             0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK0_BYTE_n_MR_LOWER_BYTE_DQO_SHFT                              0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ADDR(n)                                     (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000ab4 + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_PHYS(n)                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000ab4 + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_OFFS(n)                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000ab4 + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_RMSK                                        0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_MAXn                                                 1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ACCU_VALUE_BMSK                             0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_ACCU_SCALED_RNK1_BYTE_n_ACCU_VALUE_SHFT                                    0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_ADDR(n)                                      (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000ab8 + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_PHYS(n)                                      (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000ab8 + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_OFFS(n)                                      (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000ab8 + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_RMSK                                             0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_MAXn                                                  1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_MR_UPPER_BYTE_DQO_BMSK                           0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_MR_UPPER_BYTE_DQO_SHFT                              0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_MR_LOWER_BYTE_DQO_BMSK                             0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MAX_SCALED_RNK1_BYTE_n_MR_LOWER_BYTE_DQO_SHFT                              0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_ADDR(n)                                      (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000abc + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_PHYS(n)                                      (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000abc + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_OFFS(n)                                      (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000abc + 0xC * (n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_RMSK                                             0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_MAXn                                                  1
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_INI(n)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_ADDR(n), HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_ADDR(n), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_OUTI(n,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_ADDR(n),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_ADDR(n),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_INI(n))
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_MR_UPPER_BYTE_DQO_BMSK                           0xff00
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_MR_UPPER_BYTE_DQO_SHFT                              0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_MR_LOWER_BYTE_DQO_BMSK                             0xff
#define HWIO_MC_BROADCAST_MC5_SHKE_DQO_PDT_DIT_MIN_SCALED_RNK1_BYTE_n_MR_LOWER_BYTE_DQO_SHFT                              0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_ADDR(m)                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000af0 + 0x8 * (m))
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_PHYS(m)                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000af0 + 0x8 * (m))
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_OFFS(m)                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000af0 + 0x8 * (m))
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_RMSK                                                             0xffff33ff
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_MAXm                                                                     15
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_INI(m)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_ADDR(m), HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_INMI(m,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_ADDR(m), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_OUTI(m,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_ADDR(m),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_OUTMI(m,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_ADDR(m),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_INI(m))
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_MR_DATA_BMSK                                                     0xff000000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_MR_DATA_SHFT                                                           0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_MR_ADDR_BMSK                                                       0xff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_MR_ADDR_SHFT                                                           0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_RANK_SEL_BMSK                                                        0x3000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_RANK_SEL_SHFT                                                           0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_EVENT_SEL_BMSK                                                        0x3ff
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_CFG_m_EVENT_SEL_SHFT                                                          0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_ADDR(m)                                                  (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000af4 + 0x8 * (m))
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_PHYS(m)                                                  (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000af4 + 0x8 * (m))
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_OFFS(m)                                                  (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000af4 + 0x8 * (m))
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_RMSK                                                      0x313ffff
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_MAXm                                                             15
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_INI(m)        \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_ADDR(m), HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_RMSK)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_INMI(m,mask)    \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_ADDR(m), mask)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_OUTI(m,val)    \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_ADDR(m),val)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_OUTMI(m,mask,val) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_ADDR(m),mask,val,HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_INI(m))
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_RFU_25_24_BMSK                                            0x3000000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_RFU_25_24_SHFT                                                 0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_STAGGER_RANKS_EN_BMSK                                      0x100000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_STAGGER_RANKS_EN_SHFT                                          0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_CLK_SELECT_BMSK                                             0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_CLK_SELECT_SHFT                                                0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_INTERVAL_BMSK                                                0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_SET1_STAGGER_CFG_m_INTERVAL_SHFT                                                   0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ1_ADDR                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000b70)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ1_PHYS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000b70)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ1_OFFS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000b70)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ1_RMSK                                                                0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ1_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ1_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ1_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ1_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ1_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ1_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ1_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ1_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ1_CMD_SELECT_BMSK                                                     0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_SEQ1_CMD_SELECT_SHFT                                                            0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER1_ADDR                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000b74)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER1_PHYS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000b74)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER1_OFFS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000b74)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER1_RMSK                                                                   0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER1_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER1_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER1_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER1_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER1_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER1_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER1_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER1_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER1_SEQ_TRIGGER_BMSK                                                       0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_TRIGGER1_SEQ_TRIGGER_SHFT                                                       0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_ADDR                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000bc0)
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_PHYS                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000bc0)
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_OFFS                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000bc0)
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_RMSK                                                              0xff0300ff
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_RFU_31_24_BMSK                                                    0xff000000
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_RFU_31_24_SHFT                                                          0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_CLK_SELECT_BMSK                                                      0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_CLK_SELECT_SHFT                                                         0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_RFU_7_6_BMSK                                                            0xc0
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_RFU_7_6_SHFT                                                             0x6
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_ZQ_MODE_BMSK                                                            0x20
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_ZQ_MODE_SHFT                                                             0x5
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_RFU_4_BMSK                                                              0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_RFU_4_SHFT                                                               0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_ZQ_INTERVAL_BMSK                                                         0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_ZQ_INTERVAL_SHFT                                                         0x2
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_ZQ_STOP_BMSK                                                             0x2
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_ZQ_STOP_SHFT                                                             0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_ZQ_RESET_BMSK                                                            0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_BGZQ_CMD_CTRL_ZQ_RESET_SHFT                                                            0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_IDLE_STATUS_ADDR                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c00)
#define HWIO_MC_BROADCAST_MC5_SHKE_IDLE_STATUS_PHYS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c00)
#define HWIO_MC_BROADCAST_MC5_SHKE_IDLE_STATUS_OFFS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c00)
#define HWIO_MC_BROADCAST_MC5_SHKE_IDLE_STATUS_RMSK                                                                0x80030000
#define HWIO_MC_BROADCAST_MC5_SHKE_IDLE_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_IDLE_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_IDLE_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_IDLE_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_IDLE_STATUS_CLKON_BMSK                                                          0x80000000
#define HWIO_MC_BROADCAST_MC5_SHKE_IDLE_STATUS_CLKON_SHFT                                                                0x1f
#define HWIO_MC_BROADCAST_MC5_SHKE_IDLE_STATUS_RANK_IDLE_BMSK                                                         0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_IDLE_STATUS_RANK_IDLE_SHFT                                                            0x10

#define HWIO_MC_BROADCAST_MC5_SHKE_BANK_UNAVAIL_STATUS_ADDR                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c04)
#define HWIO_MC_BROADCAST_MC5_SHKE_BANK_UNAVAIL_STATUS_PHYS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c04)
#define HWIO_MC_BROADCAST_MC5_SHKE_BANK_UNAVAIL_STATUS_OFFS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c04)
#define HWIO_MC_BROADCAST_MC5_SHKE_BANK_UNAVAIL_STATUS_RMSK                                                        0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_BANK_UNAVAIL_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_BANK_UNAVAIL_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_BANK_UNAVAIL_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_BANK_UNAVAIL_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_BANK_UNAVAIL_STATUS_UNAVAIL_STATUS_BMSK                                         0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_BANK_UNAVAIL_STATUS_UNAVAIL_STATUS_SHFT                                                0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_ADDR                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c08)
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_PHYS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c08)
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_OFFS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c08)
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_RMSK                                                           0xf3333
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_DSM_STATUS_BMSK                                                0xc0000
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_DSM_STATUS_SHFT                                                   0x12
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_SELF_REFRESH_BUSY_BMSK                                         0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_SELF_REFRESH_BUSY_SHFT                                            0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_FSW_SELF_REFRESH_BMSK                                           0x3000
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_FSW_SELF_REFRESH_SHFT                                              0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_WDOG_SELF_REFRESH_BMSK                                           0x300
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_WDOG_SELF_REFRESH_SHFT                                             0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_SW_SELF_REFRESH_BMSK                                              0x30
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_SW_SELF_REFRESH_SHFT                                               0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_SELF_REFRESH_BMSK                                                  0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_SELF_REFRESH_STATUS_SELF_REFRESH_SHFT                                                  0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS_ADDR                                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c0c)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS_PHYS                                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c0c)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS_OFFS                                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c0c)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS_RMSK                                                                 0xdf1fffff
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS_FSM_STATE_BMSK                                                       0xc0000000
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS_FSM_STATE_SHFT                                                             0x1e
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS_CURR_FSW_ACK_STATE_BMSK                                              0x1f000000
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS_CURR_FSW_ACK_STATE_SHFT                                                    0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS_CURR_FSW_REQ_STATE_BMSK                                                0x1f0000
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS_CURR_FSW_REQ_STATE_SHFT                                                    0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS_TASK_COMPLETE_BMSK                                                       0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS_TASK_COMPLETE_SHFT                                                          0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_STATUS_ADDR                                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c10)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_STATUS_PHYS                                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c10)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_STATUS_OFFS                                                                 (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c10)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_STATUS_RMSK                                                                        0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSP_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FSP_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_STATUS_CURR_FSP_BMSK                                                               0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_FSP_STATUS_CURR_FSP_SHFT                                                               0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_ACK_STATUS_ADDR                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c14)
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_ACK_STATUS_PHYS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c14)
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_ACK_STATUS_OFFS                                                          (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c14)
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_ACK_STATUS_RMSK                                                                0x11
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_ACK_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_ACK_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_ACK_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_ACK_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_ACK_STATUS_DT_ACK_BMSK                                                         0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_ACK_STATUS_DT_ACK_SHFT                                                          0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_ACK_STATUS_DT_REQ_BMSK                                                          0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_DT_REQ_ACK_STATUS_DT_REQ_SHFT                                                          0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ZQCAL_STATUS_ADDR                                                               (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c18)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQCAL_STATUS_PHYS                                                               (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c18)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQCAL_STATUS_OFFS                                                               (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c18)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQCAL_STATUS_RMSK                                                                      0x7
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQCAL_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQCAL_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQCAL_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ZQCAL_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQCAL_STATUS_ZQCAL_FSM_STATE_BMSK                                                      0x7
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQCAL_STATUS_ZQCAL_FSM_STATE_SHFT                                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_ADDR                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c1c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_PHYS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c1c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_OFFS                                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c1c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_RMSK                                                             0xf77f7fff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_RPB_MODE_BMSK                                                    0xc0000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_RPB_MODE_SHFT                                                          0x1e
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_BURST_MODE_BMSK                                                  0x30000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_BURST_MODE_SHFT                                                        0x1c
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_DEBIT_TH_ACT_BMSK                                                 0x7000000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_DEBIT_TH_ACT_SHFT                                                      0x18
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_RANK1_CREDIT_COUNT_BMSK                                            0x700000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_RANK1_CREDIT_COUNT_SHFT                                                0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_RANK1_PEND_COUNT_BMSK                                               0xf0000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_RANK1_PEND_COUNT_SHFT                                                  0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_RANK0_CREDIT_COUNT_BMSK                                              0x7000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_RANK0_CREDIT_COUNT_SHFT                                                 0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_RANK0_PEND_COUNT_BMSK                                                 0xf00
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_RANK0_PEND_COUNT_SHFT                                                   0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_ENFORCE_RAB_BMSK                                                       0xc0
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_ENFORCE_RAB_SHFT                                                        0x6
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_REFRESH_OVERFLOW_BMSK                                                  0x30
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_REFRESH_OVERFLOW_SHFT                                                   0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_RAB_DEBIT_HIGH_BMSK                                                     0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_RAB_DEBIT_HIGH_SHFT                                                     0x2
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_REFRESH_PENDING_BMSK                                                    0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_STATUS_REFRESH_PENDING_SHFT                                                    0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK1_ADDR                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c20)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK1_PHYS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c20)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK1_OFFS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c20)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK1_RMSK                                                            0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK1_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK1_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK1_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK1_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK1_MR4_RDATA_BMSK                                                  0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK1_MR4_RDATA_SHFT                                                         0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK0_ADDR                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c24)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK0_PHYS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c24)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK0_OFFS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c24)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK0_RMSK                                                            0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK0_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK0_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK0_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK0_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK0_MR4_RDATA_BMSK                                                  0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_MR4_RDATA_RANK0_MR4_RDATA_SHFT                                                         0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_STATUS_ADDR                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c28)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_STATUS_PHYS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c28)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_STATUS_OFFS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c28)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_STATUS_RMSK                                                                     0x1f1
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_WDOG_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_WDOG_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_STATUS_FSM_STATE_BMSK                                                           0x1f0
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_STATUS_FSM_STATE_SHFT                                                             0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_STATUS_PRE_ARES_DONE_BMSK                                                         0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_WDOG_STATUS_PRE_ARES_DONE_SHFT                                                         0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_STATUS_ADDR                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c2c)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_STATUS_PHYS                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c2c)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_STATUS_OFFS                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c2c)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_STATUS_RMSK                                                                     0xf
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_STATUS_FSM_STATE_BMSK                                                           0xf
#define HWIO_MC_BROADCAST_MC5_SHKE_SW_CMD_STATUS_FSM_STATE_SHFT                                                           0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_STALL_STATUS_ADDR                                                               (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c30)
#define HWIO_MC_BROADCAST_MC5_SHKE_STALL_STATUS_PHYS                                                               (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c30)
#define HWIO_MC_BROADCAST_MC5_SHKE_STALL_STATUS_OFFS                                                               (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c30)
#define HWIO_MC_BROADCAST_MC5_SHKE_STALL_STATUS_RMSK                                                                     0x73
#define HWIO_MC_BROADCAST_MC5_SHKE_STALL_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_STALL_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_STALL_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_STALL_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_STALL_STATUS_STALL_FSM_STATE_BMSK                                                     0x70
#define HWIO_MC_BROADCAST_MC5_SHKE_STALL_STATUS_STALL_FSM_STATE_SHFT                                                      0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_STALL_STATUS_DOWNTIME_FSM_STATE_BMSK                                                   0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_STALL_STATUS_DOWNTIME_FSM_STATE_SHFT                                                   0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DTC_CTRL_STATUS_ADDR                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c34)
#define HWIO_MC_BROADCAST_MC5_SHKE_DTC_CTRL_STATUS_PHYS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c34)
#define HWIO_MC_BROADCAST_MC5_SHKE_DTC_CTRL_STATUS_OFFS                                                            (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c34)
#define HWIO_MC_BROADCAST_MC5_SHKE_DTC_CTRL_STATUS_RMSK                                                                  0x1f
#define HWIO_MC_BROADCAST_MC5_SHKE_DTC_CTRL_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DTC_CTRL_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DTC_CTRL_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DTC_CTRL_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DTC_CTRL_STATUS_FSM_STATE_BMSK                                                        0x1f
#define HWIO_MC_BROADCAST_MC5_SHKE_DTC_CTRL_STATUS_FSM_STATE_SHFT                                                         0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_SR_STATUS_ADDR                                                                  (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c38)
#define HWIO_MC_BROADCAST_MC5_SHKE_SR_STATUS_PHYS                                                                  (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c38)
#define HWIO_MC_BROADCAST_MC5_SHKE_SR_STATUS_OFFS                                                                  (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c38)
#define HWIO_MC_BROADCAST_MC5_SHKE_SR_STATUS_RMSK                                                                       0x3ff
#define HWIO_MC_BROADCAST_MC5_SHKE_SR_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_SR_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_SR_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_SR_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_SR_STATUS_FSM_STATE_1_BMSK                                                           0x3e0
#define HWIO_MC_BROADCAST_MC5_SHKE_SR_STATUS_FSM_STATE_1_SHFT                                                             0x5
#define HWIO_MC_BROADCAST_MC5_SHKE_SR_STATUS_FSM_STATE_0_BMSK                                                            0x1f
#define HWIO_MC_BROADCAST_MC5_SHKE_SR_STATUS_FSM_STATE_0_SHFT                                                             0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_STATUS_ADDR                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c3c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_STATUS_PHYS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c3c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_STATUS_OFFS                                                        (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c3c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_STATUS_RMSK                                                            0x1f1f
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_STATUS_RANK1_REFRESH_RATE_BMSK                                         0x1f00
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_STATUS_RANK1_REFRESH_RATE_SHFT                                            0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_STATUS_RANK0_REFRESH_RATE_BMSK                                           0x1f
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_RATE_STATUS_RANK0_REFRESH_RATE_SHFT                                            0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_ADDR                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c40)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_PHYS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c40)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_OFFS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c40)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_RMSK                                                             0xffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_OUTSTAND_RCMD_FULL_CNT_BMSK                                      0xf00000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_OUTSTAND_RCMD_FULL_CNT_SHFT                                          0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_OUTSTAND_DIT_RCMD_OCCUPANCY_BMSK                                  0xf0000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_OUTSTAND_DIT_RCMD_OCCUPANCY_SHFT                                     0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_OUTSTAND_MR4_CMD_OCCUPANCY_BMSK                                    0xf000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_OUTSTAND_MR4_CMD_OCCUPANCY_SHFT                                       0xc
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_OUTSTAND_SW_RCMD_OCCUPANCY_BMSK                                     0xf00
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_OUTSTAND_SW_RCMD_OCCUPANCY_SHFT                                       0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_OUTSTAND_RCMD_OCCUPANCY_BMSK                                         0xf0
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_OUTSTAND_RCMD_OCCUPANCY_SHFT                                          0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_RCMD_DATA_FIFO_FULL_BMSK                                              0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_RCMD_DATA_FIFO_FULL_SHFT                                              0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_RCMD_DATA_FIFO_EMPTY_BMSK                                             0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_RCMD_DATA_FIFO_EMPTY_SHFT                                             0x2
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_OUTSTAND_RCMD_FIFO_FULL_BMSK                                          0x2
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_OUTSTAND_RCMD_FIFO_FULL_SHFT                                          0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_OUTSTAND_RCMD_FIFO_EMPTY_BMSK                                         0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS0_OUTSTAND_RCMD_FIFO_EMPTY_SHFT                                         0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS1_ADDR                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c44)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS1_PHYS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c44)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS1_OFFS                                                           (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c44)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS1_RMSK                                                            0x1ffdf3f
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS1_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS1_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS1_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS1_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS1_ARB1_STG1_Q_BMSK                                                0x1f00000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS1_ARB1_STG1_Q_SHFT                                                     0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS1_ARB0_STG1_Q_BMSK                                                  0xfc000
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS1_ARB0_STG1_Q_SHFT                                                      0xe
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS1_ARB1_STG0_Q_BMSK                                                   0x1f00
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS1_ARB1_STG0_Q_SHFT                                                      0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS1_ARB0_STG0_Q_BMSK                                                     0x3f
#define HWIO_MC_BROADCAST_MC5_SHKE_CMD_INTF_STATUS1_ARB0_STG0_Q_SHFT                                                      0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS1_ADDR                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c4c)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS1_PHYS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c4c)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS1_OFFS                                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c4c)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS1_RMSK                                                                       0xf
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS1_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS1_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS1_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS1_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS1_MC_STALL_STATUS_BMSK                                                       0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS1_MC_STALL_STATUS_SHFT                                                       0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS1_MSI_FSW_COMPLETE_BMSK                                                      0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS1_MSI_FSW_COMPLETE_SHFT                                                      0x2
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS1_MSI_FSW_STALL_ACK_BMSK                                                     0x2
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS1_MSI_FSW_STALL_ACK_SHFT                                                     0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS1_MSI_FSW_STALL_REQ_BMSK                                                     0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_FSW_STATUS1_MSI_FSW_STALL_REQ_SHFT                                                     0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STATUS_ADDR                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c50)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STATUS_PHYS                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c50)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STATUS_OFFS                                                              (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c50)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STATUS_RMSK                                                                    0x33
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STATUS_EVENT_OVERFLOW_BMSK                                                     0x30
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STATUS_EVENT_OVERFLOW_SHFT                                                      0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STATUS_EVENT_PENDING_BMSK                                                       0x3
#define HWIO_MC_BROADCAST_MC5_SHKE_ZQSTOP_STATUS_EVENT_PENDING_SHFT                                                       0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TREFI_ACT_STATUS_ADDR                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c54)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TREFI_ACT_STATUS_PHYS                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c54)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TREFI_ACT_STATUS_OFFS                                                   (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c54)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TREFI_ACT_STATUS_RMSK                                                   0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TREFI_ACT_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TREFI_ACT_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TREFI_ACT_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TREFI_ACT_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TREFI_ACT_STATUS_RANK1_TREFI_ACT_BMSK                                   0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TREFI_ACT_STATUS_RANK1_TREFI_ACT_SHFT                                         0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TREFI_ACT_STATUS_RANK0_TREFI_ACT_BMSK                                       0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_TREFI_ACT_STATUS_RANK0_TREFI_ACT_SHFT                                          0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BANK_UNAVAIL_STATUS_ADDR                                                (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c58)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BANK_UNAVAIL_STATUS_PHYS                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c58)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BANK_UNAVAIL_STATUS_OFFS                                                (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c58)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BANK_UNAVAIL_STATUS_RMSK                                                0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BANK_UNAVAIL_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BANK_UNAVAIL_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BANK_UNAVAIL_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BANK_UNAVAIL_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BANK_UNAVAIL_STATUS_RANK1_BANK_UNAVAIL_BMSK                             0xffff0000
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BANK_UNAVAIL_STATUS_RANK1_BANK_UNAVAIL_SHFT                                   0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BANK_UNAVAIL_STATUS_RANK0_BANK_UNAVAIL_BMSK                                 0xffff
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BANK_UNAVAIL_STATUS_RANK0_BANK_UNAVAIL_SHFT                                    0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_LIMIT_ACT_STATUS_ADDR                                             (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c5c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_LIMIT_ACT_STATUS_PHYS                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c5c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_LIMIT_ACT_STATUS_OFFS                                             (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c5c)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_LIMIT_ACT_STATUS_RMSK                                                 0x1f1f
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_LIMIT_ACT_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_LIMIT_ACT_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_LIMIT_ACT_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_LIMIT_ACT_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_LIMIT_ACT_STATUS_RANK1_PULL_IN_TH_ACT_BMSK                            0x1f00
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_LIMIT_ACT_STATUS_RANK1_PULL_IN_TH_ACT_SHFT                               0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_LIMIT_ACT_STATUS_RANK0_PULL_IN_TH_ACT_BMSK                              0x1f
#define HWIO_MC_BROADCAST_MC5_SHKE_REFRESH_BURST_LIMIT_ACT_STATUS_RANK0_PULL_IN_TH_ACT_SHFT                               0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_ADDR                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000c60)
#define HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_PHYS                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000c60)
#define HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_OFFS                                                     (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000c60)
#define HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_RMSK                                                      0xff30f11
#define HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_DIT_ARB_OUTSTAND_CMD_BMSK                                 0xff00000
#define HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_DIT_ARB_OUTSTAND_CMD_SHFT                                      0x14
#define HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_DIT_ARB_GRANT_BMSK                                          0x30000
#define HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_DIT_ARB_GRANT_SHFT                                             0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_DIT_MRR_RCMD_FIFO_OCCUPANCY_BMSK                              0xf00
#define HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_DIT_MRR_RCMD_FIFO_OCCUPANCY_SHFT                                0x8
#define HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_DIT_MRR_RCMD_FIFO_FULL_BMSK                                    0x10
#define HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_DIT_MRR_RCMD_FIFO_FULL_SHFT                                     0x4
#define HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_DIT_MRR_RD_CMD_FIFO_EMPTY_BMSK                                  0x1
#define HWIO_MC_BROADCAST_MC5_SHKE_DIT_ARB_RD_FIFO_STATUS_DIT_MRR_RD_CMD_FIFO_EMPTY_SHFT                                  0x0

#define HWIO_MC_BROADCAST_MC5_SHKE_SPARE_REG_ADDR                                                                  (MC_BROADCAST_MC5_SHKE_REG_BASE      + 0x00000f00)
#define HWIO_MC_BROADCAST_MC5_SHKE_SPARE_REG_PHYS                                                                  (MC_BROADCAST_MC5_SHKE_REG_BASE_PHYS + 0x00000f00)
#define HWIO_MC_BROADCAST_MC5_SHKE_SPARE_REG_OFFS                                                                  (MC_BROADCAST_MC5_SHKE_REG_BASE_OFFS + 0x00000f00)
#define HWIO_MC_BROADCAST_MC5_SHKE_SPARE_REG_RMSK                                                                  0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_SPARE_REG_IN          \
        in_dword(HWIO_MC_BROADCAST_MC5_SHKE_SPARE_REG_ADDR)
#define HWIO_MC_BROADCAST_MC5_SHKE_SPARE_REG_INM(m)      \
        in_dword_masked(HWIO_MC_BROADCAST_MC5_SHKE_SPARE_REG_ADDR, m)
#define HWIO_MC_BROADCAST_MC5_SHKE_SPARE_REG_OUT(v)      \
        out_dword(HWIO_MC_BROADCAST_MC5_SHKE_SPARE_REG_ADDR,v)
#define HWIO_MC_BROADCAST_MC5_SHKE_SPARE_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MC_BROADCAST_MC5_SHKE_SPARE_REG_ADDR,m,v,HWIO_MC_BROADCAST_MC5_SHKE_SPARE_REG_IN)
#define HWIO_MC_BROADCAST_MC5_SHKE_SPARE_REG_SPARE_FIELD_BMSK                                                      0xffffffff
#define HWIO_MC_BROADCAST_MC5_SHKE_SPARE_REG_SPARE_FIELD_SHFT                                                             0x0

#endif /* __DDR_HWIO_TEST_H__ */

