#ifndef __HAL_DP_PHY_1_2_0_HWIO_H__
#define __HAL_DP_PHY_1_2_0_HWIO_H__
/*
===========================================================================
*/
/**
  @file hal_dp_phy_1_2_0_hwio.h
  @brief Auto-generated HWIO interface include file.

  This file contains HWIO register definitions for the following modules:
    AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM
    AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL
    AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX
    AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX
    AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX
    AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX
    AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY
    AHB2EDPPHY_CM_EDP_PHY.*
    AHB2EDPPHY_CM_DPPHY2.*

  'Include' filters applied: <none>
  'Exclude' filters applied: RESERVED DUMMY 
*/
/*
  ===========================================================================

  Copyright (c) 2018 Qualcomm Technologies Incorporated.
  All Rights Reserved.
  Qualcomm Confidential and Proprietary

  Export of this technology or software is regulated by the U.S. Government.
  Diversion contrary to U.S. law prohibited.

  All ideas, data and information contained in or disclosed by
  this document are confidential and proprietary information of
  Qualcomm Technologies Incorporated and all rights therein are expressly reserved.
  By accepting this material the recipient agrees that this material
  and the information contained therein are held in confidence and in
  trust and will not be used, copied, reproduced in whole or in part,
  nor its contents revealed in any manner to others without the express
  written permission of Qualcomm Technologies Incorporated.

  ===========================================================================

  $Header: //components/rel/boot.xf/3.2/QcomPkg/Library/HALDPLib/hal_dp_phy_1_2_0_hwio.h#1 $
  $DateTime: 2018/07/26 18:39:07 $
  $Author: pwbldsvc $

  ===========================================================================
*/

/*----------------------------------------------------------------------------
 * MODULE: AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM
 *--------------------------------------------------------------------------*/

#define AHB2PHY_SOUTH_AHB2PHY_SOUTH_BASE  0x088E0000

#define AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE                         (AHB2PHY_SOUTH_AHB2PHY_SOUTH_BASE      + 0x00008000)
#define AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE_OFFS                    0x00008000

#define AHB2PHY_SOUTH_USB3_DP_PHY_SECUSB3_DP_PHY_SECCM_USB3_DP_CON_SW_REG_BASE                         (AHB2PHY_SOUTH_AHB2PHY_SOUTH_BASE      + 0x0000d000)
#define AHB2PHY_SOUTH_USB3_DP_PHY_SECUSB3_DP_PHY_SECCM_USB3_DP_CON_SW_REG_BASE_OFFS                     0x0000d000
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PHY_MODE_CTRL_ADDR                                  (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE      + 0x00000000)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PHY_MODE_CTRL_OFFS                                  (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE_OFFS + 0x00000000)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PHY_MODE_CTRL_RMSK                                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PHY_MODE_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PHY_MODE_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PHY_MODE_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PHY_MODE_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PHY_MODE_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PHY_MODE_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PHY_MODE_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PHY_MODE_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PHY_MODE_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PHY_MODE_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PHY_MODE_CTRL_PHY_MODE_BMSK                                0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PHY_MODE_CTRL_PHY_MODE_SHFT                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SW_RESET_ADDR                                       (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE      + 0x00000004)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SW_RESET_OFFS                                       (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE_OFFS + 0x00000004)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SW_RESET_RMSK                                              0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SW_RESET_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SW_RESET_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SW_RESET_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SW_RESET_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SW_RESET_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SW_RESET_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SW_RESET_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SW_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SW_RESET_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SW_RESET_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SW_RESET_SW_RESET_BMSK                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SW_RESET_SW_RESET_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_ADDR                                (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE      + 0x00000008)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_OFFS                                (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE_OFFS + 0x00000008)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_RMSK                                       0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_PLACEHOLDER_CLK_EN_BMSK                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_PLACEHOLDER_CLK_EN_SHFT                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_SW_PWRDN_B_BMSK                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_POWER_DOWN_CTRL_SW_PWRDN_B_SHFT                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_ADDR                                       (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE      + 0x0000000c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_OFFS                                       (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE_OFFS + 0x0000000c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_RMSK                                              0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_DP_SWI_ACT_ACCESS_EN_BMSK                         0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_DP_SWI_ACT_ACCESS_EN_SHFT                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_USB3_SWI_ACT_ACCESS_EN_BMSK                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_SWI_CTRL_USB3_SWI_ACT_ACCESS_EN_SHFT                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE      + 0x00000010)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE_OFFS + 0x00000010)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_RMSK                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_SW_L1_CMN_SEL_MUX_BMSK                         0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_SW_L1_CMN_SEL_MUX_SHFT                          0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_SW_L1_CMN_SEL_BMSK                             0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_SW_L1_CMN_SEL_SHFT                              0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_SW_L0_CMN_SEL_MUX_BMSK                         0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_SW_L0_CMN_SEL_MUX_SHFT                          0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_SW_L0_CMN_SEL_BMSK                             0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_SW_L0_CMN_SEL_SHFT                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_HW_PORTSELECT_SEL_BMSK                          0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_HW_PORTSELECT_SEL_SHFT                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_PORTSELECT_POLARITY_BMSK                        0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_PORTSELECT_POLARITY_SHFT                        0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_SW_PORTSELECT_MUX_BMSK                          0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_SW_PORTSELECT_MUX_SHFT                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_SW_PORTSELECT_BMSK                              0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_CTRL_SW_PORTSELECT_SHFT                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_ADDR                               (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE      + 0x00000014)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_OFFS                               (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE_OFFS + 0x00000014)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_RMSK                                     0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_SW_L1_PWRDN_B_MUX_BMSK                   0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_SW_L1_PWRDN_B_MUX_SHFT                    0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_SW_L1_PWRDN_B_BMSK                        0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_SW_L1_PWRDN_B_SHFT                        0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_SW_L0_PWRDN_B_MUX_BMSK                    0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_SW_L0_PWRDN_B_MUX_SHFT                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_SW_L0_PWRDN_B_BMSK                        0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_SW_L0_PWRDN_B_SHFT                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_UNUSED_LANE_PWRDN_EN_BMSK                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_PWRDN_CTRL_UNUSED_LANE_PWRDN_EN_SHFT                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_ADDR                                  (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE      + 0x00000018)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_OFFS                                  (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE_OFFS + 0x00000018)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_RMSK                                        0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_SW_C0_PWRDN_B_MUX_BMSK                      0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_SW_C0_PWRDN_B_MUX_SHFT                       0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_SW_C0_PWRDN_B_BMSK                          0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_SW_C0_PWRDN_B_SHFT                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_SW_C0_RESET_MUX_BMSK                         0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_SW_C0_RESET_MUX_SHFT                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_HW_C0_RESET_BMSK                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_HW_C0_RESET_SHFT                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_SW_C0_RESET_BMSK                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_SW_C0_RESET_SHFT                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_SW_DP_BIST_SEL_BMSK                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DP_BIST_CFG_0_SW_DP_BIST_SEL_SHFT                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_ADDR                                (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE      + 0x0000001c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_OFFS                                (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE_OFFS + 0x0000001c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_RMSK                                       0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_SW_USB3PHY_RESET_MUX_BMSK                  0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_SW_USB3PHY_RESET_MUX_SHFT                  0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_SW_USB3PHY_RESET_BMSK                      0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_SW_USB3PHY_RESET_SHFT                      0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_SW_DPPHY_RESET_MUX_BMSK                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_SW_DPPHY_RESET_MUX_SHFT                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_SW_DPPHY_RESET_BMSK                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_RESET_OVRD_CTRL_SW_DPPHY_RESET_SHFT                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_ADDR                               (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE      + 0x00000020)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_OFFS                               (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE_OFFS + 0x00000020)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_RMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_DEBUG_CLK_DIV_BMSK                       0xf0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_DEBUG_CLK_DIV_SHFT                        0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_DEBUG_CLK_SEL_BMSK                        0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_DBG_CLK_MUX_CTRL_DEBUG_CLK_SEL_SHFT                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_STATUS_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE      + 0x00000024)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_STATUS_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE_OFFS + 0x00000024)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_STATUS_RMSK                                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_STATUS_PORTSELECT_PCS_BMSK                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_STATUS_PORTSELECT_PCS_SHFT                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_STATUS_PORTSELECT_RAW_BMSK                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_TYPEC_STATUS_PORTSELECT_RAW_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PLACEHOLDER_STATUS_ADDR                             (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE      + 0x00000028)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PLACEHOLDER_STATUS_OFFS                             (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE_OFFS + 0x00000028)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PLACEHOLDER_STATUS_RMSK                                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PLACEHOLDER_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PLACEHOLDER_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PLACEHOLDER_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PLACEHOLDER_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PLACEHOLDER_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PLACEHOLDER_STATUS_PLACEHOLDER_STATUS_BMSK                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_PLACEHOLDER_STATUS_PLACEHOLDER_STATUS_SHFT                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID0_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE      + 0x0000002c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID0_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE_OFFS + 0x0000002c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID0_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID0_STEP_7_0_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID0_STEP_7_0_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID1_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE      + 0x00000030)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID1_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE_OFFS + 0x00000030)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID1_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID1_STEP_15_8_BMSK                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID1_STEP_15_8_SHFT                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID2_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE      + 0x00000034)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID2_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE_OFFS + 0x00000034)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID2_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID2_MINOR_7_0_BMSK                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID2_MINOR_7_0_SHFT                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID3_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE      + 0x00000038)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID3_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM_REG_BASE_OFFS + 0x00000038)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID3_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID3_MAJOR_BMSK                                   0xf0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID3_MAJOR_SHFT                                    0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID3_MINOR_11_8_BMSK                               0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_USB3_DP_COM_REVISION_ID3_MINOR_11_8_SHFT                               0x0

/*----------------------------------------------------------------------------
 * MODULE: AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL
 *--------------------------------------------------------------------------*/

#define AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE                                      (AHB2PHY_SOUTH_AHB2PHY_SOUTH_BASE      + 0x0000a000)
#define AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS                                 0x0000a000

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL1_ADDR                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000000)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL1_OFFS                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000000)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL1_RMSK                                                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL1_ATB_SEL_7_0_BMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL1_ATB_SEL_7_0_SHFT                                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL2_ADDR                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000004)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL2_OFFS                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000004)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL2_RMSK                                                                  0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL2_ATB_SEL_10_8_BMSK                                                     0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_ATB_SEL2_ATB_SEL_10_8_SHFT                                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_FREQ_UPDATE_ADDR                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000008)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_FREQ_UPDATE_OFFS                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000008)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_FREQ_UPDATE_RMSK                                                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_FREQ_UPDATE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_FREQ_UPDATE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_FREQ_UPDATE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_FREQ_UPDATE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_FREQ_UPDATE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_FREQ_UPDATE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_FREQ_UPDATE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_FREQ_UPDATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_FREQ_UPDATE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_FREQ_UPDATE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_FREQ_UPDATE_PLL_FREQ_UPDATE_BMSK                                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_FREQ_UPDATE_PLL_FREQ_UPDATE_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_ADDR                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000000c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_OFFS                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000000c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_RMSK                                                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_SYSCLK_WAKE_BYPASS_BMSK                                              0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_SYSCLK_WAKE_BYPASS_SHFT                                               0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_SYSCLK_WAKE_TIME_BMSK                                                0x70
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_SYSCLK_WAKE_TIME_SHFT                                                 0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_REFCLK_FREQ_SEL_BMSK                                                  0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_REFCLK_FREQ_SEL_SHFT                                                  0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_RSVD_BMSK                                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_RSVD_SHFT                                                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_BIAS_WAIT_TIME_BMSK                                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BG_TIMER_BIAS_WAIT_TIME_SHFT                                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000010)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000010)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_RMSK                                                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_SSC_CENTER_BMSK                                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_SSC_CENTER_SHFT                                                  0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_SSC_EN_BMSK                                                      0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_EN_CENTER_SSC_EN_SHFT                                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER1_ADDR                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000014)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER1_OFFS                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000014)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER1_RMSK                                                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER1_SSC_ADJPER_7_0_BMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER1_SSC_ADJPER_7_0_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER2_ADDR                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000018)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER2_OFFS                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000018)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER2_RMSK                                                              0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER2_SSC_ADJPER_9_8_BMSK                                               0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_ADJ_PER2_SSC_ADJPER_9_8_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER1_ADDR                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000001c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER1_OFFS                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000001c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER1_RMSK                                                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER1_SSC_PER_7_0_BMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER1_SSC_PER_7_0_SHFT                                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER2_ADDR                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000020)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER2_OFFS                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000020)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER2_RMSK                                                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER2_SSC_PER_15_8_BMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_PER2_SSC_PER_15_8_SHFT                                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000024)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000024)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_SSC_STEPSIZE_MODE0_7_0_BMSK                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_SSC_STEPSIZE_MODE0_7_0_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000028)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000028)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_SSC_STEPSIZE_MODE0_15_8_BMSK                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_SSC_STEPSIZE_MODE0_15_8_SHFT                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000002c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000002c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_RMSK                                                      0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_SSC_STEPSIZE_MODE0_16_16_BMSK                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_SSC_STEPSIZE_MODE0_16_16_SHFT                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000030)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000030)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_SSC_STEPSIZE_MODE1_7_0_BMSK                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_SSC_STEPSIZE_MODE1_7_0_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000034)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000034)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_SSC_STEPSIZE_MODE1_15_8_BMSK                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_SSC_STEPSIZE_MODE1_15_8_SHFT                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000038)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000038)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_RMSK                                                      0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_SSC_STEPSIZE_MODE1_16_16_BMSK                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_SSC_STEPSIZE_MODE1_16_16_SHFT                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_ADDR                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000003c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_OFFS                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000003c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_RMSK                                                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_PLL_POSTDIV_7_0_BMSK                                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_PLL_POSTDIV_7_0_SHFT                                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_ADDR                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000040)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_OFFS                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000040)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_RMSK                                                             0x11
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_PLL_POSTDIV_MUX_BMSK                                             0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_PLL_POSTDIV_MUX_SHFT                                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_PLL_POSTDIV_8_8_BMSK                                              0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_POST_DIV_MUX_PLL_POSTDIV_8_8_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000044)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000044)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_RMSK                                                      0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_EN_SYSCLK_TX_SEL_BMSK                                     0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_EN_SYSCLK_TX_SEL_SHFT                                      0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_CLKBUF_L_EN_BMSK                                           0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_CLKBUF_L_EN_SHFT                                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_CLKBUF_R_EN_BMSK                                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_CLKBUF_R_EN_SHFT                                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_BIAS_EN_MUX_BMSK                                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_BIAS_EN_MUX_SHFT                                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_BIAS_EN_BMSK                                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_BIAS_EN_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_ADDR                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000048)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_OFFS                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000048)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_RMSK                                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_CLKDRVIDLE_EN_BMSK                                                0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_CLKDRVIDLE_EN_SHFT                                                 0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_EN_SYSCLK_TX_PS3PS4_BMSK                                          0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_EN_SYSCLK_TX_PS3PS4_SHFT                                           0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_EN_SYSCLK_TX_PS0PS1PS2_BMSK                                       0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_EN_SYSCLK_TX_PS0PS1PS2_SHFT                                        0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_CLK_EP_EN_BMSK                                                    0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_CLK_EP_EN_SHFT                                                     0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_PLL_CLKOUT_EN_MUX_BMSK                                             0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_PLL_CLKOUT_EN_MUX_SHFT                                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_PLL_CLKOUT_EN_BMSK                                                 0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_PLL_CLKOUT_EN_SHFT                                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_EXT_CLKBUF_EN_MUX_BMSK                                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_EXT_CLKBUF_EN_MUX_SHFT                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_EXT_CLKBUF_EN_BMSK                                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_ENABLE1_EXT_CLKBUF_EN_SHFT                                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_ADDR                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000004c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_OFFS                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000004c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_RMSK                                                             0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_EP_GLITCHFREE_BYPASS_BMSK                                        0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_EP_GLITCHFREE_BYPASS_SHFT                                         0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_TX_SYSCLKSEL_MUX_BMSK                                     0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_TX_SYSCLKSEL_MUX_SHFT                                      0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_TX_SYSCLKSEL_BMSK                                         0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_TX_SYSCLKSEL_SHFT                                          0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_DIV2_SEL_BMSK                                              0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_DIV2_SEL_SHFT                                              0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_CM_BMSK                                                    0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_CM_SHFT                                                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_AC_COUPLE_BMSK                                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_AC_COUPLE_SHFT                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_GNDTERM_BMSK                                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_GNDTERM_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000050)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000050)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_RMSK                                                         0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_EN_CTRL_BY_PSM_BMSK                                   0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_EN_CTRL_BY_PSM_SHFT                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_EN_PS3PS4_BMSK                                        0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_EN_PS3PS4_SHFT                                        0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_BUF_EN_MUX_BMSK                                       0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_BUF_EN_MUX_SHFT                                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_SW_SYSCLK_BUF_EN_BMSK                                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_BUF_ENABLE_SW_SYSCLK_BUF_EN_SHFT                                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_ADDR                                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000054)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_OFFS                                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000054)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_RMSK                                                                    0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_PLL_EN_MUX_BMSK                                                         0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_PLL_EN_MUX_SHFT                                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_PLL_EN_BMSK                                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_EN_PLL_EN_SHFT                                                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_IVCO_ADDR                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000058)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_IVCO_OFFS                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000058)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_IVCO_RMSK                                                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_IVCO_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_IVCO_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_IVCO_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_IVCO_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_IVCO_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_IVCO_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_IVCO_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_IVCO_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_IVCO_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_IVCO_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_IVCO_PLL_IVCO_BMSK                                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_IVCO_PLL_IVCO_SHFT                                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IETRIM_ADDR                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000005c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IETRIM_OFFS                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000005c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IETRIM_RMSK                                                               0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IETRIM_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IETRIM_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IETRIM_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IETRIM_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IETRIM_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IETRIM_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IETRIM_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IETRIM_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IETRIM_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IETRIM_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IETRIM_IETRIM_BMSK                                                        0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IETRIM_IETRIM_SHFT                                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IPTRIM_ADDR                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000060)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IPTRIM_OFFS                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000060)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IPTRIM_RMSK                                                               0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IPTRIM_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IPTRIM_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IPTRIM_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IPTRIM_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IPTRIM_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IPTRIM_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IPTRIM_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IPTRIM_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IPTRIM_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IPTRIM_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IPTRIM_IPTRIM_BMSK                                                        0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_IPTRIM_IPTRIM_SHFT                                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000064)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000064)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_RMSK                                                     0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_DIVSEL_MUX_BMSK                            0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_DIVSEL_MUX_SHFT                             0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_DIVSEL_BMSK                                0x18
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_DIVSEL_SHFT                                 0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_FORCE_BMSK                                  0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_FORCE_SHFT                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_EN_MUX_BMSK                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_EN_MUX_SHFT                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_EN_BMSK                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_EN_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000068)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000068)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_RMSK                                                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_SYSCLK_CLKDET_COMP_BMSK                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_SYSCLK_CLKDET_COMP_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE0_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000006c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE0_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000006c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE0_RMSK                                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE0_CLK_EP_DIV_MODE0_BMSK                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE0_CLK_EP_DIV_MODE0_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE1_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000070)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE1_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000070)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE1_RMSK                                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE1_CLK_EP_DIV_MODE1_BMSK                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_EP_DIV_MODE1_CLK_EP_DIV_MODE1_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE0_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000074)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE0_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000074)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE0_RMSK                                                            0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE0_PLL_CPCTRL_MODE0_BMSK                                           0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE0_PLL_CPCTRL_MODE0_SHFT                                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE1_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000078)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE1_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000078)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE1_RMSK                                                            0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE1_PLL_CPCTRL_MODE1_BMSK                                           0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CP_CTRL_MODE1_PLL_CPCTRL_MODE1_SHFT                                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE0_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000007c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE0_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000007c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE0_RMSK                                                          0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE0_PLL_RCTRL_MODE0_BMSK                                          0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE0_PLL_RCTRL_MODE0_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE1_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000080)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE1_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000080)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE1_RMSK                                                          0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE1_PLL_RCTRL_MODE1_BMSK                                          0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_RCTRL_MODE1_PLL_RCTRL_MODE1_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE0_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000084)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE0_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000084)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE0_RMSK                                                          0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE0_PLL_CCTRL_MODE0_BMSK                                          0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE0_PLL_CCTRL_MODE0_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE1_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000088)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE1_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000088)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE1_RMSK                                                          0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE1_PLL_CCTRL_MODE1_BMSK                                          0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CCTRL_MODE1_PLL_CCTRL_MODE1_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_ADDR                                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000008c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_OFFS                                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000008c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_RMSK                                                                0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_PLL_STABLE_TIME_BMSK                                                0x60
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_PLL_STABLE_TIME_SHFT                                                 0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_MASH_RESET_MUX_BMSK                                                 0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_MASH_RESET_MUX_SHFT                                                  0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_MASH_RESET_BMSK                                                      0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_MASH_RESET_SHFT                                                      0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_PLL_CPLIN_BMSK                                                       0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_PLL_CPLIN_SHFT                                                       0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_PLL_DIV_FFEN_BMSK                                                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_PLL_DIV_FFEN_SHFT                                                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_PLL_DIV_ORD_BMSK                                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_CNTRL_PLL_DIV_ORD_SHFT                                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000090)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000090)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_RMSK                                                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_BIAS_EN_CTRL_BY_PSM_BMSK                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_BIAS_EN_CTRL_BY_PSM_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000094)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000094)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_RMSK                                                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_CML_SYSCLK_SEL_BMSK                                             0xe0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_CML_SYSCLK_SEL_SHFT                                              0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_TERM_SEL_BMSK                                            0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_TERM_SEL_SHFT                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_SEL_BMSK                                                  0xc
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_SEL_SHFT                                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_EN_MUX_BMSK                                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_EN_MUX_SHFT                                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_EN_BMSK                                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_EN_SHFT                                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CML_SYSCLK_SEL_ADDR                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000098)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CML_SYSCLK_SEL_OFFS                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000098)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CML_SYSCLK_SEL_RMSK                                                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CML_SYSCLK_SEL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CML_SYSCLK_SEL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CML_SYSCLK_SEL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CML_SYSCLK_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CML_SYSCLK_SEL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CML_SYSCLK_SEL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CML_SYSCLK_SEL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CML_SYSCLK_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CML_SYSCLK_SEL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CML_SYSCLK_SEL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CML_SYSCLK_SEL_CML_SYSCLK_SEL_MUX_BMSK                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CML_SYSCLK_SEL_CML_SYSCLK_SEL_MUX_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000009c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000009c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_RMSK                                                            0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_FORCE_C_READY_BMSK                                              0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_FORCE_C_READY_SHFT                                               0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_TSYNC_SEL_BMSK                                                  0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_TSYNC_SEL_SHFT                                                   0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_DISABLE_CLKGATE_BMSK                                            0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_DISABLE_CLKGATE_SHFT                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_PLL_UNLOCK_DISABLE_BMSK                                          0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_PLL_UNLOCK_DISABLE_SHFT                                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_RSM_START_MUX_BMSK                                               0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_RSM_START_MUX_SHFT                                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_RSM_START_BMSK                                                   0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_RSM_START_SHFT                                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_FORCE_PLLLOCK_BMSK                                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL_FORCE_PLLLOCK_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_ADDR                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_OFFS                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_RMSK                                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_CORE_PLL_EN_MUX_BMSK                                           0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_CORE_PLL_EN_MUX_SHFT                                            0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_CORE_PLL_EN_BMSK                                               0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_CORE_PLL_EN_SHFT                                                0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_BYPASS_RSM_BIAS_BMSK                                           0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_BYPASS_RSM_BIAS_SHFT                                            0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_BYPASS_RSM_INTEGLOOP_CAL_BMSK                                  0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_BYPASS_RSM_INTEGLOOP_CAL_SHFT                                   0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_PULSE_WIDTH_BMSK                                          0xc
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_PULSE_WIDTH_SHFT                                          0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_MUX_BMSK                                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_MUX_SHFT                                                  0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_BMSK                                                      0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_SHFT                                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_ADDR                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_OFFS                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_RMSK                                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_RNG_2_BMSK                                                0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_RNG_2_SHFT                                                 0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_CNT_2_BMSK                                                0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_CNT_2_SHFT                                                 0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_EN_MUX_BMSK                                               0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_EN_MUX_SHFT                                                0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_EN_BMSK                                                   0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_EN_SHFT                                                    0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_RNG_BMSK                                                   0xc
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_RNG_SHFT                                                   0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_CNT_BMSK                                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_CNT_SHFT                                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_ADDR                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_OFFS                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_RMSK                                                              0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_PLLLOCK_RNG_UPDATE_DISABLE_BMSK                                   0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_PLLLOCK_RNG_UPDATE_DISABLE_SHFT                                   0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_PLLLOCK_STOP_COUNT_BMSK                                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_PLLLOCK_STOP_COUNT_SHFT                                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_BYP_PLLLOCK_BMSK                                                  0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP_CFG_BYP_PLLLOCK_SHFT                                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE0_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE0_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE0_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE0_PLLLOCK_CMP_MODE0_7_0_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE0_PLLLOCK_CMP_MODE0_7_0_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE0_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE0_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE0_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE0_PLLLOCK_CMP_MODE0_15_8_BMSK                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE0_PLLLOCK_CMP_MODE0_15_8_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE1_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE1_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE1_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE1_PLLLOCK_CMP_MODE1_7_0_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP1_MODE1_PLLLOCK_CMP_MODE1_7_0_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE1_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE1_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE1_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE1_PLLLOCK_CMP_MODE1_15_8_BMSK                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_LOCK_CMP2_MODE1_PLLLOCK_CMP_MODE1_15_8_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE0_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE0_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE0_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE0_DEC_START_MODE0_7_0_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE0_DEC_START_MODE0_7_0_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE0_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000c0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE0_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000c0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE0_RMSK                                                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE0_DEC_START_MODE0_8_8_BMSK                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE0_DEC_START_MODE0_8_8_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE1_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000c4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE1_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000c4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE1_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE1_DEC_START_MODE1_7_0_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MODE1_DEC_START_MODE1_7_0_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE1_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000c8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE1_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000c8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE1_RMSK                                                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE1_DEC_START_MODE1_8_8_BMSK                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEC_START_MSB_MODE1_DEC_START_MODE1_8_8_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE0_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000cc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE0_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000cc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE0_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE0_DIV_FRAC_START_MODE0_7_0_BMSK                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE0_DIV_FRAC_START_MODE0_7_0_SHFT                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE0_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000d0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE0_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000d0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE0_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE0_DIV_FRAC_START_MODE0_15_8_BMSK                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE0_DIV_FRAC_START_MODE0_15_8_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE0_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000d4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE0_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000d4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE0_RMSK                                                     0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE0_DIV_FRAC_START_MODE0_19_16_BMSK                          0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE0_DIV_FRAC_START_MODE0_19_16_SHFT                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE1_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000d8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE1_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000d8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE1_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE1_DIV_FRAC_START_MODE1_7_0_BMSK                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START1_MODE1_DIV_FRAC_START_MODE1_7_0_SHFT                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE1_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000dc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE1_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000dc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE1_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE1_DIV_FRAC_START_MODE1_15_8_BMSK                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START2_MODE1_DIV_FRAC_START_MODE1_15_8_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE1_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000e0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE1_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000e0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE1_RMSK                                                     0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE1_DIV_FRAC_START_MODE1_19_16_BMSK                          0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DIV_FRAC_START3_MODE1_DIV_FRAC_START_MODE1_19_16_SHFT                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_INITVAL_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000e4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_INITVAL_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000e4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_INITVAL_RMSK                                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_INITVAL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_INITVAL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_INITVAL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_INITVAL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_INITVAL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_INITVAL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_INITVAL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_INITVAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_INITVAL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_INITVAL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_INITVAL_INTEGLOOP_INITVAL_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_INITVAL_INTEGLOOP_INITVAL_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_ADDR                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000e8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_OFFS                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000e8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_RMSK                                                              0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_P_GAIN_SIGN_FLIP_BMSK                                             0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_P_GAIN_SIGN_FLIP_SHFT                                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_CODE_BYPASS_BMSK                                        0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_CODE_BYPASS_SHFT                                        0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_EN_MUX_BMSK                                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_EN_MUX_SHFT                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_EN_BMSK                                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_EN_SHFT                                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000ec)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000ec)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_INTEGLOOP_GAIN_MODE0_7_0_BMSK                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_INTEGLOOP_GAIN_MODE0_7_0_SHFT                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000f0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000f0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_RMSK                                                     0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_INTEGLOOP_GAIN_MODE0_11_8_BMSK                           0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_INTEGLOOP_GAIN_MODE0_11_8_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000f4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000f4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_INTEGLOOP_GAIN_MODE1_7_0_BMSK                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_INTEGLOOP_GAIN_MODE1_7_0_SHFT                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000f8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000f8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_RMSK                                                     0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_INTEGLOOP_GAIN_MODE1_11_8_BMSK                           0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_INTEGLOOP_GAIN_MODE1_11_8_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000000fc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000000fc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_INTEGLOOP_P_GAIN_7_0_BMSK                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_INTEGLOOP_P_GAIN_7_0_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000100)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000100)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_RMSK                                                    0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_INTEGLOOP_P_GAIN_9_8_BMSK                               0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_INTEGLOOP_P_GAIN_9_8_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000104)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000104)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_RMSK                                                      0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_TOO_SLOW_CNTSEL_BMSK                                0x18
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_TOO_SLOW_CNTSEL_SHFT                                 0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FORCE_CORRECT_POL_BMSK                                     0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FORCE_CORRECT_POL_SHFT                                     0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_DEAD_CORRECT_EN_BMSK                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_DEAD_CORRECT_EN_SHFT                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_DEAD_TIME_BMSK                                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_DEAD_TIME_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000108)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000108)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_RMSK                                                            0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_BIN_VCOCAL_FORCE_DONE_BMSK                                      0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_BIN_VCOCAL_FORCE_DONE_SHFT                                       0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_VCOCAL_TYPE_SEL_BMSK                                            0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_VCOCAL_TYPE_SEL_SHFT                                             0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_VCOCAL_POS_SLOPE_BMSK                                           0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_VCOCAL_POS_SLOPE_SHFT                                            0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_BYP_VCOCAL_MODE1_BMSK                                            0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_BYP_VCOCAL_MODE1_SHFT                                            0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_BYP_VCOCAL_MODE0_BMSK                                            0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_BYP_VCOCAL_MODE0_SHFT                                            0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_VCO_TUNE_EN_MUX_BMSK                                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_VCO_TUNE_EN_MUX_SHFT                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_VCO_TUNE_EN_BMSK                                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_CTRL_VCO_TUNE_EN_SHFT                                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_ADDR                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000010c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_OFFS                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000010c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_RMSK                                                              0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_VCO_DEFAULT_FREQ_BMSK                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_VCO_DEFAULT_FREQ_SHFT                                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_MAP_LANE_PS0B_BMSK                                                0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_MAP_LANE_PS0B_SHFT                                                0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_MAP_LANE_PS0A_BMSK                                                0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAP_MAP_LANE_PS0A_SHFT                                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE0_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000110)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE0_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000110)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE0_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE0_PLL_VCOTUNE_MODE0_7_0_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE0_PLL_VCOTUNE_MODE0_7_0_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE0_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000114)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE0_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000114)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE0_RMSK                                                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE0_PLL_VCOTUNE_MODE0_9_8_BMSK                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE0_PLL_VCOTUNE_MODE0_9_8_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE1_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000118)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE1_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000118)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE1_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE1_PLL_VCOTUNE_MODE1_7_0_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE1_MODE1_PLL_VCOTUNE_MODE1_7_0_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE1_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000011c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE1_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000011c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE1_RMSK                                                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE1_PLL_VCOTUNE_MODE1_9_8_BMSK                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE2_MODE1_PLL_VCOTUNE_MODE1_9_8_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL1_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000120)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL1_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000120)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL1_RMSK                                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL1_VCO_TUNE_INITVAL_7_0_BMSK                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL1_VCO_TUNE_INITVAL_7_0_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL2_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000124)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL2_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000124)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL2_RMSK                                                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL2_VCO_TUNE_INITVAL_9_8_BMSK                                    0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_INITVAL2_VCO_TUNE_INITVAL_9_8_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL1_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000128)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL1_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000128)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL1_RMSK                                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL1_VCO_TUNE_MINVAL_7_0_BMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL1_VCO_TUNE_MINVAL_7_0_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL2_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000012c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL2_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000012c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL2_RMSK                                                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL2_VCO_TUNE_MINVAL_9_8_BMSK                                      0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MINVAL2_VCO_TUNE_MINVAL_9_8_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL1_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000130)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL1_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000130)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL1_RMSK                                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL1_VCO_TUNE_MAXVAL_7_0_BMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL1_VCO_TUNE_MAXVAL_7_0_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL2_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000134)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL2_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000134)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL2_RMSK                                                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL2_VCO_TUNE_MAXVAL_9_8_BMSK                                      0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_MAXVAL2_VCO_TUNE_MAXVAL_9_8_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER1_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000138)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER1_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000138)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER1_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER1_PLL_VCOTUNE_TIMER_7_0_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER1_PLL_VCOTUNE_TIMER_7_0_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER2_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000013c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER2_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000013c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER2_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER2_PLL_VCOTUNE_TIMER_15_8_BMSK                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_TUNE_TIMER2_PLL_VCOTUNE_TIMER_15_8_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_ADDR                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000140)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_OFFS                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000140)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_RMSK                                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_REFGEN_READY_BMSK                                                  0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_REFGEN_READY_SHFT                                                   0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_FREEZEIO_D_BMSK                                                    0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_FREEZEIO_D_SHFT                                                     0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_SWITCH_TO_REFCLK_DONE_BMSK                                         0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_SWITCH_TO_REFCLK_DONE_SHFT                                          0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_SWITCH_TO_CORECLK_DONE_BMSK                                        0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_SWITCH_TO_CORECLK_DONE_SHFT                                         0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_SWITCH_TO_AUXCLK_DONE_BMSK                                          0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_SWITCH_TO_AUXCLK_DONE_SHFT                                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_PLL_UNLOCKED_BMSK                                                   0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_PLL_UNLOCKED_SHFT                                                   0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_PLL_LOCKED_BMSK                                                     0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_PLL_LOCKED_SHFT                                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_PLL_FREQ_DONE_BMSK                                                  0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_STATUS_PLL_FREQ_DONE_SHFT                                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESET_SM_STATUS_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000144)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESET_SM_STATUS_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000144)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESET_SM_STATUS_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESET_SM_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESET_SM_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESET_SM_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESET_SM_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESET_SM_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESET_SM_STATUS_RESETSM_BMSK                                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESET_SM_STATUS_RESETSM_SHFT                                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESTRIM_CODE_STATUS_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000148)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESTRIM_CODE_STATUS_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000148)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESTRIM_CODE_STATUS_RMSK                                                      0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESTRIM_CODE_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESTRIM_CODE_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESTRIM_CODE_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESTRIM_CODE_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESTRIM_CODE_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESTRIM_CODE_STATUS_RESTRIM_CODE_BMSK                                         0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_RESTRIM_CODE_STATUS_RESTRIM_CODE_SHFT                                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE1_STATUS_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000014c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE1_STATUS_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000014c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE1_STATUS_RMSK                                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE1_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE1_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE1_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE1_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE1_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE1_STATUS_VCO_CTUNE_BINCODE_7_0_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE1_STATUS_VCO_CTUNE_BINCODE_7_0_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE2_STATUS_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000150)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE2_STATUS_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000150)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE2_STATUS_RMSK                                                       0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE2_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE2_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE2_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE2_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE2_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE2_STATUS_VCO_CTUNE_BINCODE_9_8_BMSK                                 0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLLCAL_CODE2_STATUS_VCO_CTUNE_BINCODE_9_8_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_ADDR                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000154)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_OFFS                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000154)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_RMSK                                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_REFCLK_DRV_EN_MUX_BMSK                                             0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_REFCLK_DRV_EN_MUX_SHFT                                              0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_REFCLK_DRV_EN_BMSK                                                 0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_REFCLK_DRV_EN_SHFT                                                  0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_TSYNC_EN_MUX_BMSK                                                  0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_TSYNC_EN_MUX_SHFT                                                   0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_TSYNC_EN_BMSK                                                      0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_TSYNC_EN_SHFT                                                       0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_SYSCLK_CMOS_PAD_SEL_BMSK                                            0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_SYSCLK_CMOS_PAD_SEL_SHFT                                            0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_SYSCLK_TX_SWINGSEL_BMSK                                             0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_SYSCLK_TX_SWINGSEL_SHFT                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_EP_REFCLK_SEL_BMSK                                                  0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CLK_SELECT_EP_REFCLK_SEL_SHFT                                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_ADDR                                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000158)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_OFFS                                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000158)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_RMSK                                                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_HSCLK_DIVSEL_MODE1_BMSK                                             0xf0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_HSCLK_DIVSEL_MODE1_SHFT                                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_HSCLK_DIVSEL_MODE0_BMSK                                              0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_SEL_HSCLK_DIVSEL_MODE0_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000015c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000015c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_RMSK                                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_HSCLK_SWITCH_DIVSEL_MODE1_BMSK                            0xf0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_HSCLK_SWITCH_DIVSEL_MODE1_SHFT                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_HSCLK_SWITCH_DIVSEL_MODE0_BMSK                             0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_HSCLK_SWITCH_DIVSEL_MODE0_SHFT                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_ADDR                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000160)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_OFFS                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000160)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_RMSK                                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_INTEGLOOP_BINCODE_BMSK                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_INTEGLOOP_BINCODE_SHFT                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_ANALOG_ADDR                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000164)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_ANALOG_OFFS                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000164)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_ANALOG_RMSK                                                                0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_ANALOG_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_ANALOG_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_ANALOG_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_ANALOG_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_ANALOG_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_ANALOG_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_ANALOG_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_ANALOG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_ANALOG_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_ANALOG_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_ANALOG_PLL_ANALOG_BMSK                                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_PLL_ANALOG_PLL_ANALOG_SHFT                                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE0_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000168)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE0_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000168)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE0_RMSK                                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE0_CORE_CLK_DIV_MODE0_BMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE0_CORE_CLK_DIV_MODE0_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE1_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000016c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE1_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000016c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE1_RMSK                                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE1_CORE_CLK_DIV_MODE1_BMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORECLK_DIV_MODE1_CORE_CLK_DIV_MODE1_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SW_RESET_ADDR                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000170)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SW_RESET_OFFS                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000170)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SW_RESET_RMSK                                                                  0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SW_RESET_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SW_RESET_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SW_RESET_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SW_RESET_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SW_RESET_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SW_RESET_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SW_RESET_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SW_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SW_RESET_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SW_RESET_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SW_RESET_SW_RESET_BMSK                                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SW_RESET_SW_RESET_SHFT                                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_ADDR                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000174)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_OFFS                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000174)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_RMSK                                                              0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_CLKS_PLL_DIVSEL_MODE1_BMSK                                        0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_CLKS_PLL_DIVSEL_MODE1_SHFT                                         0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_CLKS_PLL_DIVSEL_MODE0_BMSK                                        0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_CLKS_PLL_DIVSEL_MODE0_SHFT                                         0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_CORECLK_EN_MUX_BMSK                                                0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_CORECLK_EN_MUX_SHFT                                                0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_CORECLK_EN_BMSK                                                    0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_CORECLK_EN_SHFT                                                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_AUXCLK_EN_MUX_BMSK                                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_AUXCLK_EN_MUX_SHFT                                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_AUXCLK_EN_BMSK                                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CORE_CLK_EN_AUXCLK_EN_SHFT                                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_C_READY_STATUS_ADDR                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000178)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_C_READY_STATUS_OFFS                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000178)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_C_READY_STATUS_RMSK                                                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_C_READY_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_C_READY_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_C_READY_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_C_READY_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_C_READY_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_C_READY_STATUS_C_READY_BMSK                                                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_C_READY_STATUS_C_READY_SHFT                                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_ADDR                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000017c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_OFFS                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000017c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_RMSK                                                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_FORCE_REFGEN_READY_BMSK                                            0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_FORCE_REFGEN_READY_SHFT                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_PSM_SWITCH_CORECLK_BMSK                                             0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_PSM_SWITCH_CORECLK_SHFT                                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_PSM_SWITCH_AUXCLK_BMSK                                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_PSM_SWITCH_AUXCLK_SHFT                                              0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_PLL_FBCLK_SEL_BMSK                                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_PLL_FBCLK_SEL_SHFT                                                  0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_CLK_BIAS_REFSEL_BMSK                                                0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_CONFIG_CLK_BIAS_REFSEL_SHFT                                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000180)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000180)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_RMSK                                                        0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_PLL_HS_SWITCH_MUX_BMSK                                      0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_PLL_HS_SWITCH_MUX_SHFT                                       0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_PLL_HS_SWITCH_BMSK                                           0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_PLL_HS_SWITCH_SHFT                                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_SW_UPDATE_BMSK                                      0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_SW_UPDATE_SHFT                                      0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_SW_SEL_BMSK                                         0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_SW_SEL_SHFT                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_CODE_BMSK                                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_CODE_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000184)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000184)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_RMSK                                                          0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_PLL_DIGCLK_DIVSEL_MODE1_BMSK                                  0xc
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_PLL_DIGCLK_DIVSEL_MODE1_SHFT                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_PLL_DIGCLK_DIVSEL_MODE0_BMSK                                  0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_SVS_MODE_CLK_SEL_PLL_DIGCLK_DIVSEL_MODE0_SHFT                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS0_ADDR                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000188)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS0_OFFS                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000188)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS0_RMSK                                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS0_DEBUG_BUS_7_0_BMSK                                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS0_DEBUG_BUS_7_0_SHFT                                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS1_ADDR                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000018c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS1_OFFS                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000018c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS1_RMSK                                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS1_DEBUG_BUS_15_8_BMSK                                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS1_DEBUG_BUS_15_8_SHFT                                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS2_ADDR                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000190)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS2_OFFS                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000190)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS2_RMSK                                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS2_DEBUG_BUS_23_16_BMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS2_DEBUG_BUS_23_16_SHFT                                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS3_ADDR                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000194)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS3_OFFS                                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000194)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS3_RMSK                                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS3_DEBUG_BUS_31_24_BMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS3_DEBUG_BUS_31_24_SHFT                                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x00000198)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x00000198)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_RMSK                                                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_CLK_DEBUG_SEL_BMSK                                              0xf0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_CLK_DEBUG_SEL_SHFT                                               0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_DEBUG_BUS_SEL_BMSK                                               0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DEBUG_BUS_SEL_DEBUG_BUS_SEL_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_ADDR                                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x0000019c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_OFFS                                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x0000019c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_RMSK                                                                0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_DIS_CG_RATE_CHANGE_BMSK                                             0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_DIS_CG_RATE_CHANGE_SHFT                                              0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_DIS_CG_SYSGLITCH_BMSK                                               0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_DIS_CG_SYSGLITCH_SHFT                                                0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_PLL_RESET_MUX_BMSK                                                  0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_PLL_RESET_MUX_SHFT                                                   0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_PLL_RESET_BMSK                                                       0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_PLL_RESET_SHFT                                                       0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_PLL_VREG_READY_MUX_BMSK                                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_PLL_VREG_READY_MUX_SHFT                                              0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_PLL_VREG_READY_BMSK                                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_PLL_VREG_READY_SHFT                                                  0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_DISABLE_B2T_INTEGLOOP_CLKGATE_BMSK                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC1_DISABLE_B2T_INTEGLOOP_CLKGATE_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC2_ADDR                                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000001a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC2_OFFS                                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000001a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC2_RMSK                                                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC2_RSVD_BMSK                                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MISC2_RSVD_SHFT                                                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MODE_ADDR                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000001a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MODE_OFFS                                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000001a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MODE_RMSK                                                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MODE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MODE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MODE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MODE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MODE_CMN_MODE_BMSK                                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_CMN_MODE_CMN_MODE_SHFT                                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000001a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000001a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_RMSK                                                        0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_PLL_VREFGEN_REFSEL_BMSK                                     0x60
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_PLL_VREFGEN_REFSEL_SHFT                                      0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_PLL_VAR_DCCTRL_BMSK                                         0x18
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_PLL_VAR_DCCTRL_SHFT                                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_CMN_VREG_SEL_BMSK                                            0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL_CMN_VREG_SEL_SHFT                                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000001ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000001ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_BIN_VCOCAL_MEAS_CNT_MODE0_7_0_BMSK                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_BIN_VCOCAL_MEAS_CNT_MODE0_7_0_SHFT                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000001b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000001b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_BIN_VCOCAL_MEAS_CNT_MODE0_15_8_BMSK                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_BIN_VCOCAL_MEAS_CNT_MODE0_15_8_SHFT                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000001b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000001b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_BIN_VCOCAL_MEAS_CNT_MODE1_7_0_BMSK                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_BIN_VCOCAL_MEAS_CNT_MODE1_7_0_SHFT                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000001b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000001b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_BIN_VCOCAL_MEAS_CNT_MODE1_15_8_BMSK                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_BIN_VCOCAL_MEAS_CNT_MODE1_15_8_SHFT                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE      + 0x000001bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL_REG_BASE_OFFS + 0x000001bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_BIN_VCOCAL_HSCLK_SEL_MODE1_BMSK                          0xf0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_BIN_VCOCAL_HSCLK_SEL_MODE1_SHFT                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_BIN_VCOCAL_HSCLK_SEL_MODE0_BMSK                           0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_BIN_VCOCAL_HSCLK_SEL_MODE0_SHFT                           0x0

/*----------------------------------------------------------------------------
 * MODULE: AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX
 *--------------------------------------------------------------------------*/

#define AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE                             (AHB2PHY_SOUTH_AHB2PHY_SOUTH_BASE      + 0x0000a200)
#define AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS                        0x0000a200

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000000)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000000)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_BIST_ERROR_INJECT_BMSK                             0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_BIST_ERROR_INJECT_SHFT                              0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_BIST_LANE_NUMBER_BMSK                              0x60
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_BIST_LANE_NUMBER_SHFT                               0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_BISTMODE_BMSK                                      0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_MODE_LANENO_BISTMODE_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000004)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000004)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_RMSK                                                     0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_BIST_FROM_PCS_BMSK                                       0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_BIST_FROM_PCS_SHFT                                       0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_BIST_INVERT_RX_BMSK                                      0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_BIST_INVERT_RX_SHFT                                      0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_BIST_INVERT_TX_BMSK                                      0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_INVERT_BIST_INVERT_TX_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000008)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000008)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_RMSK                                                  0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_DISABLE_LPB_TX_CLKGATE_BMSK                           0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_DISABLE_LPB_TX_CLKGATE_SHFT                            0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_TXONLY_CLOCK_EDGE_BMSK                                0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_TXONLY_CLOCK_EDGE_SHFT                                 0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_GATED_CLK_EN_BMSK                                     0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_GATED_CLK_EN_SHFT                                      0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_CLKBUF_EN_LANE1_MUX_BMSK                               0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_CLKBUF_EN_LANE1_MUX_SHFT                               0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_CLKBUF_EN_LANE1_BMSK                                   0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_CLKBUF_EN_LANE1_SHFT                                   0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_CLKBUF_EN_LANE0_MUX_BMSK                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_CLKBUF_EN_LANE0_MUX_SHFT                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_CLKBUF_EN_LANE0_BMSK                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_CLKBUF_ENABLE_CLKBUF_EN_LANE0_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x0000000c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000000c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_RMSK                                               0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_TX_EMP_POST1_LVL_MUX_BMSK                          0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_TX_EMP_POST1_LVL_MUX_SHFT                           0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_TX_EMP_POST1_LVL_BMSK                              0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_EMP_POST1_LVL_TX_EMP_POST1_LVL_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_ADDR                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000010)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_OFFS                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000010)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_RMSK                                           0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_TX_IDLE_LVL_MUX_BMSK                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_TX_IDLE_LVL_MUX_SHFT                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_TX_IDLE_LVL_BMSK                               0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP_TX_IDLE_LVL_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000014)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000014)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_RMSK                                                     0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_TX_DRV_LVL_MUX_BMSK                                      0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_TX_DRV_LVL_MUX_SHFT                                       0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_TX_DRV_LVL_BMSK                                          0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_TX_DRV_LVL_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OFFSET_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000018)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OFFSET_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000018)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OFFSET_RMSK                                               0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OFFSET_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OFFSET_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OFFSET_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OFFSET_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OFFSET_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OFFSET_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OFFSET_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OFFSET_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OFFSET_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OFFSET_TX_DRV_LVL_OFFSET_BMSK                             0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_DRV_LVL_OFFSET_TX_DRV_LVL_OFFSET_SHFT                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_ADDR                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x0000001c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_OFFS                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000001c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_RMSK                                                  0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_RESET_TSYNC_EN_MUX_BMSK                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_RESET_TSYNC_EN_MUX_SHFT                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_RESET_TSYNC_EN_BMSK                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_TSYNC_EN_RESET_TSYNC_EN_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000020)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000020)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_RMSK                                          0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_STALL_EN_MUX_BMSK                             0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_STALL_EN_MUX_SHFT                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_STALL_EN_BMSK                                 0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_STALL_EN_SHFT                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_PRE_EN_MUX_BMSK                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_PRE_EN_MUX_SHFT                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_PRE_EN_BMSK                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN_PRE_EN_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000024)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000024)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_RMSK                                                         0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_TX_BAND_MUX_BMSK                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_TX_BAND_MUX_SHFT                                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_TX_BAND_BMSK                                                 0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_BAND_TX_BAND_SHFT                                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000028)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000028)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_RMSK                                                       0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_SLEW_CNTL_MUX_BMSK                                         0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_SLEW_CNTL_MUX_SHFT                                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_SLEW_CNTL_BMSK                                             0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SLEW_CNTL_SLEW_CNTL_SHFT                                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x0000002c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000002c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_RMSK                                               0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_TX_CLKDIV_PHASE_BMSK                               0x60
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_TX_CLKDIV_PHASE_SHFT                                0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_TX_PWM_PHASE_BMSK                                  0x18
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_TX_PWM_PHASE_SHFT                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_SEL_20B_10B_BMSK                                    0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_SEL_20B_10B_SHFT                                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_SEL_10B_8B_MUX_BMSK                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_SEL_10B_8B_MUX_SHFT                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_SEL_10B_8B_BMSK                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_INTERFACE_SELECT_SEL_10B_8B_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000030)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000030)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_RMSK                                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_PLACEHOLDER_CHAIN_INPUT_BMSK                                 0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_PLACEHOLDER_CHAIN_INPUT_SHFT                                  0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_LINE_LPB_EN_MUX_BMSK                                         0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_LINE_LPB_EN_MUX_SHFT                                          0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_LINE_LPB_EN_BMSK                                             0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_LINE_LPB_EN_SHFT                                              0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_TX_RCLK_LPB_EN_BMSK                                          0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_TX_RCLK_LPB_EN_SHFT                                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_SER_LPB_EN_MUX_BMSK                                           0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_SER_LPB_EN_MUX_SHFT                                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_SER_LPB_EN_BMSK                                               0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_SER_LPB_EN_SHFT                                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_PAR_LPB_EN_BMSK                                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_PAR_LPB_EN_SHFT                                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_RCLK_LPB_EN_BMSK                                              0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LPB_EN_RCLK_LPB_EN_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000034)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000034)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_RES_CODE_LANE_TX_MUX_BMSK                          0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_RES_CODE_LANE_TX_MUX_SHFT                           0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_RES_CODE_LANE_TX_BMSK                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_TX_RES_CODE_LANE_TX_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000038)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000038)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_RES_CODE_LANE_RX_MUX_BMSK                          0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_RES_CODE_LANE_RX_MUX_SHFT                           0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_RES_CODE_LANE_RX_BMSK                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_RX_RES_CODE_LANE_RX_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_TX_ADDR                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x0000003c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_TX_OFFS                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000003c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_TX_RMSK                                        0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_TX_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_TX_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_TX_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_TX_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_TX_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_TX_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_TX_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_TX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_TX_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_TX_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_TX_RES_CODE_LANE_OFFSET_TX_BMSK                0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_TX_RES_CODE_LANE_OFFSET_TX_SHFT                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_RX_ADDR                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000040)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_RX_OFFS                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000040)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_RX_RMSK                                        0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_RX_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_RX_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_RX_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_RX_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_RX_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_RX_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_RX_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_RX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_RX_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_RX_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_RX_RES_CODE_LANE_OFFSET_RX_BMSK                0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_RX_RES_CODE_LANE_OFFSET_RX_SHFT                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH1_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000044)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH1_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000044)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH1_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH1_PERL_LENGTH1_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH1_PERL_LENGTH1_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH2_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000048)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH2_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000048)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH2_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH2_PERL_LENGTH2_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PERL_LENGTH2_PERL_LENGTH2_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x0000004c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000004c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_RMSK                                              0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_MUX_BMSK                           0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_MUX_SHFT                            0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_BMSK                               0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_SHFT                                0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_EN_MUX_BMSK                         0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_EN_MUX_SHFT                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_EN_BMSK                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_EN_SHFT                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_IN_EN_MUX_BMSK                          0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_IN_EN_MUX_SHFT                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_IN_EN_BMSK                              0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_IN_EN_SHFT                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS_SEL_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000050)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS_SEL_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000050)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS_SEL_RMSK                                                   0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS_SEL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS_SEL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS_SEL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS_SEL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS_SEL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS_SEL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS_SEL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS_SEL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS_SEL_DEBUGBUS_SEL_BMSK                                      0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS_SEL_DEBUGBUS_SEL_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000054)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000054)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_RMSK                                            0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_TRANSCEIVER_BIAS_EN_MUX_BMSK                    0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_TRANSCEIVER_BIAS_EN_MUX_SHFT                     0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_TRANSCEIVER_BIAS_EN_BMSK                        0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_TRANSCEIVER_BIAS_EN_SHFT                         0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_TX_EN_LANE1_MUX_BMSK                             0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_TX_EN_LANE1_MUX_SHFT                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_TX_EN_LANE1_BMSK                                 0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_TX_EN_LANE1_SHFT                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_TX_EN_LANE0_MUX_BMSK                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_TX_EN_LANE0_MUX_SHFT                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_TX_EN_LANE0_BMSK                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN_TX_EN_LANE0_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000058)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000058)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_RMSK                                                  0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_DRVR_EN_BMSK                                          0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_DRVR_EN_SHFT                                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_MUX_BMSK                                0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_MUX_SHFT                                0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_BMSK                                    0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_SHFT                                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_MUX_BMSK                                0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_MUX_SHFT                                0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_BMSK                                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x0000005c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000005c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_RMSK                                                      0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_TX_POL_INV_LANE1_MUX_BMSK                                 0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_TX_POL_INV_LANE1_MUX_SHFT                                 0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_TX_POL_INV_LANE1_BMSK                                     0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_TX_POL_INV_LANE1_SHFT                                     0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_TX_POL_INV_LANE0_MUX_BMSK                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_TX_POL_INV_LANE0_MUX_SHFT                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_TX_POL_INV_LANE0_BMSK                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_POL_INV_TX_POL_INV_LANE0_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_ADDR                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000060)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_OFFS                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000060)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_RMSK                                     0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_PAR_RATE_MUX_BMSK                        0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_PAR_RATE_MUX_SHFT                         0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_PAR_RATE_BMSK                            0x30
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_PAR_RATE_SHFT                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_IDLE_EN_MUX_BMSK                          0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_IDLE_EN_MUX_SHFT                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_IDLE_EN_BMSK                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_IDLE_EN_SHFT                              0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_RCV_DET_EN_MUX_BMSK                       0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_RCV_DET_EN_MUX_SHFT                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_RCV_DET_EN_BMSK                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN_RCV_DET_EN_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN1_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000064)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN1_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000064)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN1_RMSK                                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN1_BIST_PATTERN1_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN1_BIST_PATTERN1_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN2_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000068)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN2_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000068)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN2_RMSK                                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN2_BIST_PATTERN2_BMSK                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN2_BIST_PATTERN2_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN3_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x0000006c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN3_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000006c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN3_RMSK                                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN3_BIST_PATTERN3_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN3_BIST_PATTERN3_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN4_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000070)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN4_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000070)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN4_RMSK                                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN4_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN4_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN4_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN4_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN4_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN4_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN4_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN4_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN4_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN4_BIST_PATTERN4_BMSK                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN4_BIST_PATTERN4_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN5_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000074)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN5_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000074)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN5_RMSK                                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN5_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN5_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN5_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN5_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN5_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN5_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN5_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN5_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN5_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN5_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN5_BIST_PATTERN5_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN5_BIST_PATTERN5_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN6_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000078)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN6_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000078)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN6_RMSK                                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN6_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN6_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN6_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN6_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN6_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN6_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN6_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN6_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN6_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN6_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN6_BIST_PATTERN6_BMSK                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN6_BIST_PATTERN6_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN7_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x0000007c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN7_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000007c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN7_RMSK                                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN7_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN7_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN7_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN7_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN7_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN7_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN7_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN7_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN7_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN7_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN7_BIST_PATTERN7_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN7_BIST_PATTERN7_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN8_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000080)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN8_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000080)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN8_RMSK                                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN8_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN8_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN8_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN8_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN8_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN8_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN8_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN8_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN8_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN8_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN8_BIST_PATTERN8_BMSK                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_PATTERN8_BIST_PATTERN8_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_1_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000084)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_1_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000084)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_1_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_1_LANE_MODE1_BMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_1_LANE_MODE1_SHFT                                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_2_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000088)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_2_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000088)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_2_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_2_LANE_MODE2_BMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_2_LANE_MODE2_SHFT                                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_3_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x0000008c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_3_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000008c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_3_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_3_LANE_MODE3_BMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_MODE_3_LANE_MODE3_SHFT                                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL1_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000090)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL1_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000090)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL1_RMSK                                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL1_ATB_SEL1_BMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL1_ATB_SEL1_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL2_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000094)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL2_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000094)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL2_RMSK                                                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL2_ATB_SEL2_BMSK                                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ATB_SEL2_ATB_SEL2_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_ADDR                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000098)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_OFFS                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000098)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_RMSK                                                  0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_RCV_DET_LVL_MUX_BMSK                                  0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_RCV_DET_LVL_MUX_SHFT                                  0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_RCV_DET_LVL_BMSK                                      0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_RCV_DET_LVL_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x0000009c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000009c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_RMSK                                               0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_RCV_DET_LVL_2_BMSK                                 0x38
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_RCV_DET_LVL_2_SHFT                                  0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_RCV_DET_LVL_1_BMSK                                  0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RCV_DETECT_LVL_2_RCV_DET_LVL_1_SHFT                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED1_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED1_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED1_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED1_PRBS_SEED1_BMSK                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED1_PRBS_SEED1_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED2_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED2_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED2_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED2_PRBS_SEED2_BMSK                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED2_PRBS_SEED2_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED3_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED3_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED3_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED3_PRBS_SEED3_BMSK                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED3_PRBS_SEED3_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED4_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED4_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED4_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED4_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED4_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED4_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED4_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED4_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED4_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED4_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED4_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED4_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED4_PRBS_SEED4_BMSK                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRBS_SEED4_PRBS_SEED4_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_RMSK                                                      0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_SW_CDR_RESET_BMSK                                         0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_SW_CDR_RESET_SHFT                                          0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_JITTER_GEN_RESET_BMSK                                     0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_JITTER_GEN_RESET_SHFT                                      0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_SW_TSYNC_BMSK                                             0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_SW_TSYNC_SHFT                                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_SW_RSYNC_BMSK                                              0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_SW_RSYNC_SHFT                                              0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_RSVD_BMSK                                                  0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_RSVD_SHFT                                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_BIST_TX_RESET_BMSK                                         0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_BIST_TX_RESET_SHFT                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_BIST_RX_RESET_BMSK                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_BIST_RX_RESET_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_RMSK                                                 0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_TSYNC_MUX_BMSK                                       0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_TSYNC_MUX_SHFT                                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_RSYNC_MUX_BMSK                                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_RESET_GEN_MUXES_RSYNC_MUX_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_RMSK                                                0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_TX_LVL_UPDATE_MUX_BMSK                              0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_TX_LVL_UPDATE_MUX_SHFT                              0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_TX_LVL_UPDATE_BMSK                                  0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_TX_LVL_UPDATE_SHFT                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_EMP_EN_MUX_BMSK                                     0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_EMP_EN_MUX_SHFT                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_EMP_EN_BMSK                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TRAN_DRVR_EMP_EN_EMP_EN_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_INTERFACE_MODE_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_INTERFACE_MODE_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_INTERFACE_MODE_RMSK                                               0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_INTERFACE_MODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_INTERFACE_MODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_INTERFACE_MODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_INTERFACE_MODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_INTERFACE_MODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_INTERFACE_MODE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_INTERFACE_MODE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_INTERFACE_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_INTERFACE_MODE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_INTERFACE_MODE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_INTERFACE_MODE_TXINTERFACE_MODE_BMSK                              0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_TX_INTERFACE_MODE_TXINTERFACE_MODE_SHFT                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000c0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000c0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_RMSK                                                       0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_TX_PWM_GEAR_MUX_BMSK                                       0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_TX_PWM_GEAR_MUX_SHFT                                        0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_TX_PWM_GEAR_BMSK                                           0x1c
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_TX_PWM_GEAR_SHFT                                            0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_TX_PWM_EN_MUX_BMSK                                          0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_TX_PWM_EN_MUX_SHFT                                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_TX_PWM_EN_BMSK                                              0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_CTRL_TX_PWM_EN_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000c4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000c4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_RMSK                                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_TX_PWM_NDATA_MUX_BMSK                            0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_TX_PWM_NDATA_MUX_SHFT                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_TX_PWM_NDATA_BMSK                                0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_ENCODED_OR_DATA_TX_PWM_NDATA_SHFT                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND2_ADDR                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000c8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND2_OFFS                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000c8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND2_RMSK                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND2_TX_PWM_DIVGEAR1_BMSK                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND2_TX_PWM_DIVGEAR1_SHFT                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND2_ADDR                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000cc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND2_OFFS                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000cc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND2_RMSK                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND2_TX_PWM_DIVGEAR2_BMSK                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND2_TX_PWM_DIVGEAR2_SHFT                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND2_ADDR                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000d0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND2_OFFS                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000d0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND2_RMSK                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND2_TX_PWM_DIVGEAR3_BMSK                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND2_TX_PWM_DIVGEAR3_SHFT                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND2_ADDR                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000d4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND2_OFFS                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000d4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND2_RMSK                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND2_TX_PWM_DIVGEAR4_BMSK                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND2_TX_PWM_DIVGEAR4_SHFT                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1_ADDR                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000d8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1_OFFS                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000d8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1_RMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1_TX_PWM_DIVGEAR1A_BMSK                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1_TX_PWM_DIVGEAR1A_SHFT                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1_ADDR                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000dc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1_OFFS                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000dc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1_RMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1_TX_PWM_DIVGEAR2A_BMSK                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1_TX_PWM_DIVGEAR2A_SHFT                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1_ADDR                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000e0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1_OFFS                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000e0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1_RMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1_TX_PWM_DIVGEAR3A_BMSK                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1_TX_PWM_DIVGEAR3A_SHFT                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1_ADDR                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000e4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1_OFFS                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000e4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1_RMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1_TX_PWM_DIVGEAR4A_BMSK                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1_TX_PWM_DIVGEAR4A_SHFT                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VMODE_CTRL1_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000e8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VMODE_CTRL1_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000e8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VMODE_CTRL1_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VMODE_CTRL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VMODE_CTRL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VMODE_CTRL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VMODE_CTRL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VMODE_CTRL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VMODE_CTRL1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VMODE_CTRL1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VMODE_CTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VMODE_CTRL1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VMODE_CTRL1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VMODE_CTRL1_VMODE_CTRL1_BMSK                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VMODE_CTRL1_VMODE_CTRL1_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_CTRL_1_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000ec)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_CTRL_1_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000ec)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_CTRL_1_RMSK                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_CTRL_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_CTRL_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_CTRL_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_CTRL_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_CTRL_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_CTRL_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_CTRL_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_CTRL_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_CTRL_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_CTRL_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_CTRL_1_ALOG_OBSV_BUS_CTRL_1_SEL_BMSK                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_CTRL_1_ALOG_OBSV_BUS_CTRL_1_SEL_SHFT                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_STATUS_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000f0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_STATUS_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000f0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_STATUS_RMSK                                                     0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_STATUS_BIST_STATUS_RO_BMSK                                      0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_STATUS_BIST_STATUS_RO_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT1_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000f4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT1_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000f4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT1_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT1_BIST_ERROR_COUNT1_STATUS_BMSK                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT1_BIST_ERROR_COUNT1_STATUS_SHFT                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT2_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000f8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT2_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000f8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT2_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT2_BIST_ERROR_COUNT2_STATUS_BMSK                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_BIST_ERROR_COUNT2_BIST_ERROR_COUNT2_STATUS_SHFT                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_STATUS_1_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x000000fc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_STATUS_1_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000fc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_STATUS_1_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_STATUS_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_STATUS_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_STATUS_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_STATUS_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_STATUS_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_STATUS_1_ALOG_OBSV_BUS_STATUS_1_BMSK                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_ALOG_OBSV_BUS_STATUS_1_ALOG_OBSV_BUS_STATUS_1_SHFT                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000100)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000100)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_RMSK                                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_RSVD_BMSK                                           0xfe
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_RSVD_SHFT                                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_LANE_PWRDN_B_BMSK                                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_LANE_DIG_CONFIG_LANE_PWRDN_B_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PI_QEC_CTRL_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000104)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PI_QEC_CTRL_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000104)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PI_QEC_CTRL_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PI_QEC_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PI_QEC_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PI_QEC_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PI_QEC_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PI_QEC_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PI_QEC_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PI_QEC_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PI_QEC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PI_QEC_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PI_QEC_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PI_QEC_CTRL_PI_QEC_CTRL_BMSK                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PI_QEC_CTRL_PI_QEC_CTRL_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000108)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000108)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_RMSK                                                       0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_PREEMPH_VAL_MUX_BMSK                                       0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_PREEMPH_VAL_MUX_SHFT                                        0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_PREEMPH_BMSK                                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_PRE_EMPH_PREEMPH_SHFT                                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SW_RESET_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x0000010c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SW_RESET_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000010c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SW_RESET_RMSK                                                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SW_RESET_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SW_RESET_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SW_RESET_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SW_RESET_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SW_RESET_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SW_RESET_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SW_RESET_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SW_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SW_RESET_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SW_RESET_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SW_RESET_SW_RESET_BMSK                                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_SW_RESET_SW_RESET_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DIG_BKUP_CTRL_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000110)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DIG_BKUP_CTRL_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000110)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DIG_BKUP_CTRL_RMSK                                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DIG_BKUP_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DIG_BKUP_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DIG_BKUP_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DIG_BKUP_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DIG_BKUP_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DIG_BKUP_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DIG_BKUP_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DIG_BKUP_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DIG_BKUP_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DIG_BKUP_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DIG_BKUP_CTRL_RSVD_BMSK                                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DIG_BKUP_CTRL_RSVD_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS0_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000114)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS0_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000114)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS0_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS0_DEBUG_BUS_7_0_BMSK                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS0_DEBUG_BUS_7_0_SHFT                                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS1_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000118)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS1_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000118)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS1_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS1_DEBUG_BUS_15_8_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS1_DEBUG_BUS_15_8_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS2_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x0000011c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS2_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000011c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS2_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS2_DEBUG_BUS_23_16_BMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS2_DEBUG_BUS_23_16_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS3_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000120)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS3_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000120)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS3_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS3_DEBUG_BUS_31_24_BMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DEBUG_BUS3_DEBUG_BUS_31_24_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_EQCODE_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000124)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_EQCODE_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000124)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_EQCODE_RMSK                                                     0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_EQCODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_EQCODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_EQCODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_EQCODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_EQCODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_EQCODE_READ_EQCODE_STATUS_BMSK                                  0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_EQCODE_READ_EQCODE_STATUS_SHFT                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_OFFSETCODE_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000128)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_OFFSETCODE_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000128)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_OFFSETCODE_RMSK                                                0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_OFFSETCODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_OFFSETCODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_OFFSETCODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_OFFSETCODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_OFFSETCODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_OFFSETCODE_READ_OFFSETCODE_STATUS_BMSK                         0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_READ_OFFSETCODE_READ_OFFSETCODE_STATUS_SHFT                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_LOW_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x0000012c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_LOW_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000012c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_LOW_RMSK                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_LOW_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_LOW_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_LOW_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_LOW_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_LOW_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_LOW_IACOMPARE_COUNT_LOW_BMSK                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_LOW_IACOMPARE_COUNT_LOW_SHFT                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_HIGH_ADDR                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000130)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_HIGH_OFFS                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000130)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_HIGH_RMSK                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_HIGH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_HIGH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_HIGH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_HIGH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_HIGH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_HIGH_IACOMPARE_COUNT_HIGH_BMSK                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IA_ERROR_COUNTER_HIGH_IACOMPARE_COUNT_HIGH_SHFT                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VGA_READ_CODE_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000134)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VGA_READ_CODE_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000134)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VGA_READ_CODE_RMSK                                                   0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VGA_READ_CODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VGA_READ_CODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VGA_READ_CODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VGA_READ_CODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VGA_READ_CODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VGA_READ_CODE_READ_VGACODE_BMSK                                      0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VGA_READ_CODE_READ_VGACODE_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VTH_READ_CODE_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000138)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VTH_READ_CODE_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000138)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VTH_READ_CODE_RMSK                                                  0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VTH_READ_CODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VTH_READ_CODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VTH_READ_CODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VTH_READ_CODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VTH_READ_CODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VTH_READ_CODE_VTH_CODE_DEBUG_BMSK                                   0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_VTH_READ_CODE_VTH_CODE_DEBUG_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP1_READ_CODE_ADDR                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x0000013c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP1_READ_CODE_OFFS                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000013c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP1_READ_CODE_RMSK                                              0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP1_READ_CODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP1_READ_CODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP1_READ_CODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP1_READ_CODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP1_READ_CODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP1_READ_CODE_READ_TAP1CODE_BMSK                                0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP1_READ_CODE_READ_TAP1CODE_SHFT                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP2_READ_CODE_ADDR                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000140)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP2_READ_CODE_OFFS                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000140)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP2_READ_CODE_RMSK                                             0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP2_READ_CODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP2_READ_CODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP2_READ_CODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP2_READ_CODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP2_READ_CODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP2_READ_CODE_READ_TAP2CODE_BMSK                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DFE_TAP2_READ_CODE_READ_TAP2CODE_SHFT                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_I_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000144)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_I_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000144)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_I_RMSK                                                  0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_I_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_I_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_I_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_I_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_I_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_I_IDAC_I_STATUS_BMSK                                    0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_I_IDAC_I_STATUS_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_IBAR_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000148)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_IBAR_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000148)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_IBAR_RMSK                                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_IBAR_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_IBAR_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_IBAR_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_IBAR_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_IBAR_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_IBAR_IDAC_IB_STATUS_BMSK                                0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_IBAR_IDAC_IB_STATUS_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_Q_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x0000014c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_Q_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000014c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_Q_RMSK                                                  0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_Q_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_Q_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_Q_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_Q_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_Q_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_Q_IDAC_Q_STATUS_BMSK                                    0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_Q_IDAC_Q_STATUS_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_QBAR_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000150)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_QBAR_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000150)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_QBAR_RMSK                                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_QBAR_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_QBAR_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_QBAR_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_QBAR_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_QBAR_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_QBAR_IDAC_QB_STATUS_BMSK                                0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_QBAR_IDAC_QB_STATUS_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_A_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000154)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_A_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000154)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_A_RMSK                                                  0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_A_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_A_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_A_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_A_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_A_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_A_IDAC_A_STATUS_BMSK                                    0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_A_IDAC_A_STATUS_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_ABAR_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000158)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_ABAR_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000158)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_ABAR_RMSK                                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_ABAR_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_ABAR_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_ABAR_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_ABAR_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_ABAR_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_ABAR_IDAC_AB_STATUS_BMSK                                0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_ABAR_IDAC_AB_STATUS_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SM_ON_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x0000015c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SM_ON_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000015c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SM_ON_RMSK                                              0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SM_ON_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SM_ON_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SM_ON_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SM_ON_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SM_ON_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SM_ON_IDAC_CAL_DONE_STATUS_BMSK                         0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SM_ON_IDAC_CAL_DONE_STATUS_SHFT                          0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SM_ON_IDAC_CAL_ON_STATUS_BMSK                            0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SM_ON_IDAC_CAL_ON_STATUS_SHFT                            0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SM_ON_IDAC_SM_STATUS_BMSK                                0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SM_ON_IDAC_SM_STATUS_SHFT                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000160)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000160)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_RMSK                                           0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_AB_BMSK                          0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_AB_SHFT                           0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_A_BMSK                           0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_A_SHFT                            0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_QB_BMSK                           0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_QB_SHFT                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_Q_BMSK                            0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_Q_SHFT                            0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_IB_BMSK                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_IB_SHFT                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_I_BMSK                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_I_SHFT                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_ADDR                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000164)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_OFFS                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000164)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_RMSK                                          0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_AB_BMSK                      0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_AB_SHFT                       0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_A_BMSK                       0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_A_SHFT                        0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_QB_BMSK                       0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_QB_SHFT                       0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_Q_BMSK                        0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_Q_SHFT                        0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_IB_BMSK                       0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_IB_SHFT                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_I_BMSK                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_I_SHFT                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DCC_CAL_STATUS_ADDR                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE      + 0x00000168)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DCC_CAL_STATUS_OFFS                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000168)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DCC_CAL_STATUS_RMSK                                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DCC_CAL_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DCC_CAL_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DCC_CAL_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DCC_CAL_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DCC_CAL_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DCC_CAL_STATUS_DCC_CAL_EN_STATUS_BMSK                               0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DCC_CAL_STATUS_DCC_CAL_EN_STATUS_SHFT                                0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DCC_CAL_STATUS_DCC_CAL_DONE_STATUS_BMSK                             0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DCC_CAL_STATUS_DCC_CAL_DONE_STATUS_SHFT                              0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DCC_CAL_STATUS_DCC_CAL_PTR_STATUS_BMSK                              0x3c
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DCC_CAL_STATUS_DCC_CAL_PTR_STATUS_SHFT                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DCC_CAL_STATUS_DCC_CAL_STATE_STATUS_BMSK                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX0_DCC_CAL_STATUS_DCC_CAL_STATE_STATUS_SHFT                             0x0

/*----------------------------------------------------------------------------
 * MODULE: AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX
 *--------------------------------------------------------------------------*/

#define AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE                                 (AHB2PHY_SOUTH_AHB2PHY_SOUTH_BASE      + 0x0000a400)
#define AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS                            0x0000a400

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_HALF_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000000)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_HALF_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000000)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_HALF_RMSK                                                  0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_HALF_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_HALF_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_HALF_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_HALF_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_HALF_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_HALF_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_HALF_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_HALF_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_HALF_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_HALF_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_HALF_UCDR_FO_GAIN_HALF_BMSK                                0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_HALF_UCDR_FO_GAIN_HALF_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_QUARTER_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000004)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_QUARTER_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000004)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_QUARTER_RMSK                                               0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_QUARTER_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_QUARTER_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_QUARTER_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_QUARTER_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_QUARTER_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_QUARTER_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_QUARTER_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_QUARTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_QUARTER_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_QUARTER_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_QUARTER_UCDR_FO_GAIN_QUARTER_BMSK                          0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_QUARTER_UCDR_FO_GAIN_QUARTER_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000008)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000008)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_RMSK                                                       0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_UCDR_FO_GAIN_BMSK                                          0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_GAIN_UCDR_FO_GAIN_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_HALF_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000000c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_HALF_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000000c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_HALF_RMSK                                                  0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_HALF_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_HALF_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_HALF_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_HALF_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_HALF_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_HALF_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_HALF_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_HALF_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_HALF_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_HALF_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_HALF_UCDR_SO_GAIN_HALF_BMSK                                0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_HALF_UCDR_SO_GAIN_HALF_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_QUARTER_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000010)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_QUARTER_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000010)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_QUARTER_RMSK                                               0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_QUARTER_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_QUARTER_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_QUARTER_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_QUARTER_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_QUARTER_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_QUARTER_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_QUARTER_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_QUARTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_QUARTER_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_QUARTER_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_QUARTER_UCDR_SO_GAIN_QUARTER_BMSK                          0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_QUARTER_UCDR_SO_GAIN_QUARTER_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000014)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000014)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_RMSK                                                       0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_UCDR_SO_GAIN_BMSK                                          0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_GAIN_UCDR_SO_GAIN_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_HALF_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000018)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_HALF_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000018)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_HALF_RMSK                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_HALF_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_HALF_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_HALF_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_HALF_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_HALF_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_HALF_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_HALF_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_HALF_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_HALF_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_HALF_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_HALF_UCDR_SVS_FO_GAIN_HALF_BMSK                        0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_HALF_UCDR_SVS_FO_GAIN_HALF_SHFT                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_QUARTER_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000001c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_QUARTER_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000001c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_QUARTER_RMSK                                           0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_QUARTER_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_QUARTER_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_QUARTER_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_QUARTER_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_QUARTER_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_QUARTER_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_QUARTER_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_QUARTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_QUARTER_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_QUARTER_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_QUARTER_UCDR_SVS_FO_GAIN_QUARTER_BMSK                  0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_QUARTER_UCDR_SVS_FO_GAIN_QUARTER_SHFT                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000020)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000020)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_RMSK                                                   0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_UCDR_SVS_FO_GAIN_BMSK                                  0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_UCDR_SVS_FO_GAIN_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000024)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000024)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF_RMSK                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF_UCDR_SVS_SO_GAIN_HALF_BMSK                        0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF_UCDR_SVS_SO_GAIN_HALF_SHFT                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000028)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000028)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER_RMSK                                           0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER_UCDR_SVS_SO_GAIN_QUARTER_BMSK                  0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER_UCDR_SVS_SO_GAIN_QUARTER_SHFT                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000002c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000002c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_RMSK                                                   0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_UCDR_SVS_SO_GAIN_BMSK                                  0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_UCDR_SVS_SO_GAIN_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000030)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000030)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_RMSK                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_UCDR_FASTLOCK_FO_GAIN_BMSK                        0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_UCDR_FASTLOCK_FO_GAIN_SHFT                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_ADDR                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000034)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_OFFS                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000034)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_RMSK                                      0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_UCDR_ENABLE_BMSK                          0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_UCDR_ENABLE_SHFT                           0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_UCDR_SO_SATURATION_BMSK                   0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE_UCDR_SO_SATURATION_SHFT                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_TO_SO_DELAY_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000038)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_TO_SO_DELAY_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000038)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_TO_SO_DELAY_RMSK                                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_TO_SO_DELAY_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_TO_SO_DELAY_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_TO_SO_DELAY_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_TO_SO_DELAY_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_TO_SO_DELAY_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_TO_SO_DELAY_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_TO_SO_DELAY_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_TO_SO_DELAY_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_TO_SO_DELAY_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_TO_SO_DELAY_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_TO_SO_DELAY_UCDR_FO_TO_SO_DELAY_BMSK                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FO_TO_SO_DELAY_UCDR_FO_TO_SO_DELAY_SHFT                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000003c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000003c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW_RMSK                                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW_UCDR_FASTLOCK_COUNTER_LOW_BMSK                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW_UCDR_FASTLOCK_COUNTER_LOW_SHFT                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000040)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000040)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_RMSK                                            0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_UCDR_FASTLOCK_COUNTER_HIGH_BMSK                 0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_UCDR_FASTLOCK_COUNTER_HIGH_SHFT                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000044)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000044)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_SB2_EN_BMSK                                            0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_SB2_EN_SHFT                                             0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_TRAN_CDRCLK_DIV6_SEL_10_BMSK                           0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_TRAN_CDRCLK_DIV6_SEL_10_SHFT                            0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_TRAN_CDRCLK_DIV6_SEL_01_BMSK                           0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_TRAN_CDRCLK_DIV6_SEL_01_SHFT                            0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_TRAN_CDRCLK_DIV6_SEL_00_BMSK                           0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_TRAN_CDRCLK_DIV6_SEL_00_SHFT                            0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_UCDR_BLOCK_STEP_BY_TWO_BMSK                             0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_UCDR_BLOCK_STEP_BY_TWO_SHFT                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_UCDR_STEP_BY_TWO_MUX_BMSK                               0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_UCDR_STEP_BY_TWO_MUX_SHFT                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_UCDR_STEP_BY_TWO_BMSK                                   0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_UCDR_STEP_BY_TWO_SHFT                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_UCDR_FASTLOCK_ENABLE_BMSK                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CONTROLS_UCDR_FASTLOCK_ENABLE_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000048)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000048)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_RMSK                                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_RXCLK_SWITCH_DIV_EN_BMSK                                  0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_RXCLK_SWITCH_DIV_EN_SHFT                                   0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_CDR_SB2_10_BMSK                                           0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_CDR_SB2_10_SHFT                                            0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_CDR_SB2_01_BMSK                                           0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_CDR_SB2_01_SHFT                                            0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_CDR_SB2_00_BMSK                                           0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_CDR_SB2_00_SHFT                                            0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_CDRCLK_DIV8_SB2_BMSK                                       0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_CDRCLK_DIV8_SB2_SHFT                                       0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_TRAN_CDRCLK_DIV8_SEL_10_BMSK                               0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_TRAN_CDRCLK_DIV8_SEL_10_SHFT                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_TRAN_CDRCLK_DIV8_SEL_01_BMSK                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_TRAN_CDRCLK_DIV8_SEL_01_SHFT                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_TRAN_CDRCLK_DIV8_SEL_00_BMSK                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_PI_CTRL2_TRAN_CDRCLK_DIV8_SEL_00_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH1_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000004c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH1_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000004c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH1_RMSK                                                   0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH1_DIV6PD_THRESH1_BMSK                                    0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH1_DIV6PD_THRESH1_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH2_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000050)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH2_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000050)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH2_RMSK                                                   0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH2_DIV6PD_THRESH2_BMSK                                    0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_THRESH2_DIV6PD_THRESH2_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN1_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000054)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN1_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000054)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN1_RMSK                                                     0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN1_DIV6PD_GAIN1_BMSK                                        0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN1_DIV6PD_GAIN1_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN2_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000058)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN2_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000058)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN2_RMSK                                                     0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN2_DIV6PD_GAIN2_BMSK                                        0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_UCDR_SB2_GAIN2_DIV6PD_GAIN2_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_CONTROL_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000005c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_CONTROL_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000005c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_CONTROL_RMSK                                                        0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_CONTROL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_CONTROL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_CONTROL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_CONTROL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_CONTROL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_CONTROL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_CONTROL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_CONTROL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_CONTROL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_CONTROL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_CONTROL_AUX_OFFSET_BMSK                                             0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_CONTROL_AUX_OFFSET_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_ADDR                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000060)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_OFFS                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000060)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_RMSK                                             0xf0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_AUXDATA_THRESH_FORCE_BMSK                        0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_AUXDATA_THRESH_FORCE_SHFT                         0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_AUXDATA_TCOARSE_BMSK                             0x70
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE_AUXDATA_TCOARSE_SHFT                              0x4

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000064)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000064)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_AUXDATA_EN_BMSK                                        0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_AUXDATA_EN_SHFT                                         0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_AUXDATA_EN_MUX_BMSK                                    0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_AUXDATA_EN_MUX_SHFT                                     0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_AUXCLK_EN_BMSK                                         0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_AUXCLK_EN_SHFT                                          0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_AUXCLK_EN_MUX_BMSK                                     0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_AUXCLK_EN_MUX_SHFT                                      0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_IACOMPARE_CLEAR_BMSK                                    0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_IACOMPARE_CLEAR_SHFT                                    0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_IACOMPARE_ENABLE_BMSK                                   0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_IACOMPARE_ENABLE_SHFT                                   0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_AUXDATA_SEL_BMSK                                        0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_AUXDATA_SEL_SHFT                                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_RCLK_SEL_BMSK                                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RCLK_AUXDATA_SEL_RCLK_SEL_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_ENABLE_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000068)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_ENABLE_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000068)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_ENABLE_RMSK                                                      0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_ENABLE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_ENABLE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_ENABLE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_ENABLE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_ENABLE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_ENABLE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_ENABLE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_ENABLE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_ENABLE_AC_JTAG_EN_BMSK                                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_ENABLE_AC_JTAG_EN_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000006c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000006c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_RMSK                                                       0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_AC_JTAG_INITP_MUX_BMSK                                     0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_AC_JTAG_INITP_MUX_SHFT                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_AC_JTAG_INITP_BMSK                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITP_AC_JTAG_INITP_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000070)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000070)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_RMSK                                                       0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_AC_JTAG_INITN_MUX_BMSK                                     0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_AC_JTAG_INITN_MUX_SHFT                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_AC_JTAG_INITN_BMSK                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_INITN_AC_JTAG_INITN_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_LVL_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000074)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_LVL_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000074)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_LVL_RMSK                                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_LVL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_LVL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_LVL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_LVL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_LVL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_LVL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_LVL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_LVL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_LVL_AC_JTAG_LVL_BMSK                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_LVL_AC_JTAG_LVL_SHFT                                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_MODE_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000078)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_MODE_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000078)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_MODE_RMSK                                                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_MODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_MODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_MODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_MODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_MODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_MODE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_MODE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_MODE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_MODE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_MODE_AC_JTAG_MODE_BMSK                                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_MODE_AC_JTAG_MODE_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_RESET_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000007c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_RESET_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000007c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_RESET_RMSK                                                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_RESET_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_RESET_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_RESET_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_RESET_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_RESET_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_RESET_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_RESET_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_RESET_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_RESET_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_RESET_AC_JTAG_RESET_BMSK                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_RESET_AC_JTAG_RESET_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000080)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000080)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_RMSK                                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_RX_TERM_BW_BAND3_BMSK                                        0xc0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_RX_TERM_BW_BAND3_SHFT                                         0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_RX_TERM_BW_BAND2_BMSK                                        0x30
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_RX_TERM_BW_BAND2_SHFT                                         0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_RX_TERM_BW_BAND1_BMSK                                         0xc
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_RX_TERM_BW_BAND1_SHFT                                         0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_RX_TERM_BW_BAND0_BMSK                                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_BW_RX_TERM_BW_BAND0_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000084)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000084)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_RMSK                                                      0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_RX_POL_INV_BMSK                                           0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_RX_POL_INV_SHFT                                            0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_RX_Q_EN_MUX_BMSK                                          0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_RX_Q_EN_MUX_SHFT                                           0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_RX_Q_EN_BMSK                                              0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_RX_Q_EN_SHFT                                               0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_RX_I_EN_MUX_BMSK                                           0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_RX_I_EN_MUX_SHFT                                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_RX_I_EN_BMSK                                               0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_RX_I_EN_SHFT                                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_RCVR_EN_MUX_BMSK                                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_RCVR_EN_MUX_SHFT                                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_RCVR_EN_BMSK                                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_RCVR_IQ_EN_RCVR_EN_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_I_DC_OFFSETS_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000088)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_I_DC_OFFSETS_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000088)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_I_DC_OFFSETS_RMSK                                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_I_DC_OFFSETS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_I_DC_OFFSETS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_I_DC_OFFSETS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_I_DC_OFFSETS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_I_DC_OFFSETS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_I_DC_OFFSETS_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_I_DC_OFFSETS_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_I_DC_OFFSETS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_I_DC_OFFSETS_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_I_DC_OFFSETS_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_I_DC_OFFSETS_IDAC_I_BMSK                                        0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_I_DC_OFFSETS_IDAC_I_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_IBAR_DC_OFFSETS_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000008c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_IBAR_DC_OFFSETS_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000008c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_IBAR_DC_OFFSETS_RMSK                                            0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_IBAR_DC_OFFSETS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_IBAR_DC_OFFSETS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_IBAR_DC_OFFSETS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_IBAR_DC_OFFSETS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_IBAR_DC_OFFSETS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_IBAR_DC_OFFSETS_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_IBAR_DC_OFFSETS_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_IBAR_DC_OFFSETS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_IBAR_DC_OFFSETS_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_IBAR_DC_OFFSETS_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_IBAR_DC_OFFSETS_IDAC_IB_BMSK                                    0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_IBAR_DC_OFFSETS_IDAC_IB_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_Q_DC_OFFSETS_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000090)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_Q_DC_OFFSETS_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000090)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_Q_DC_OFFSETS_RMSK                                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_Q_DC_OFFSETS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_Q_DC_OFFSETS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_Q_DC_OFFSETS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_Q_DC_OFFSETS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_Q_DC_OFFSETS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_Q_DC_OFFSETS_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_Q_DC_OFFSETS_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_Q_DC_OFFSETS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_Q_DC_OFFSETS_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_Q_DC_OFFSETS_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_Q_DC_OFFSETS_IDAC_Q_BMSK                                        0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_Q_DC_OFFSETS_IDAC_Q_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_QBAR_DC_OFFSETS_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000094)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_QBAR_DC_OFFSETS_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000094)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_QBAR_DC_OFFSETS_RMSK                                            0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_QBAR_DC_OFFSETS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_QBAR_DC_OFFSETS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_QBAR_DC_OFFSETS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_QBAR_DC_OFFSETS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_QBAR_DC_OFFSETS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_QBAR_DC_OFFSETS_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_QBAR_DC_OFFSETS_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_QBAR_DC_OFFSETS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_QBAR_DC_OFFSETS_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_QBAR_DC_OFFSETS_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_QBAR_DC_OFFSETS_IDAC_QB_BMSK                                    0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_QBAR_DC_OFFSETS_IDAC_QB_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_A_DC_OFFSETS_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000098)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_A_DC_OFFSETS_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000098)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_A_DC_OFFSETS_RMSK                                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_A_DC_OFFSETS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_A_DC_OFFSETS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_A_DC_OFFSETS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_A_DC_OFFSETS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_A_DC_OFFSETS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_A_DC_OFFSETS_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_A_DC_OFFSETS_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_A_DC_OFFSETS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_A_DC_OFFSETS_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_A_DC_OFFSETS_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_A_DC_OFFSETS_IDAC_A_BMSK                                        0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_A_DC_OFFSETS_IDAC_A_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ABAR_DC_OFFSETS_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000009c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ABAR_DC_OFFSETS_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000009c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ABAR_DC_OFFSETS_RMSK                                            0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ABAR_DC_OFFSETS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ABAR_DC_OFFSETS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ABAR_DC_OFFSETS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ABAR_DC_OFFSETS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ABAR_DC_OFFSETS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ABAR_DC_OFFSETS_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ABAR_DC_OFFSETS_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ABAR_DC_OFFSETS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ABAR_DC_OFFSETS_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ABAR_DC_OFFSETS_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ABAR_DC_OFFSETS_IDAC_AB_BMSK                                    0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ABAR_DC_OFFSETS_IDAC_AB_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_RMSK                                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_IDAC_ONE_BIT_DET_EN_BMSK                                     0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_IDAC_ONE_BIT_DET_EN_SHFT                                      0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_CORE_IDAC_FORCE_MASK_BMSK                                    0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_CORE_IDAC_FORCE_MASK_SHFT                                     0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_IDAC_MUX_BMSK                                                0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_IDAC_MUX_SHFT                                                 0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_IDAC_CAL_BYPASS_BMSK                                         0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_IDAC_CAL_BYPASS_SHFT                                          0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_IDAC_CAL_EN_MUX_BMSK                                          0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_IDAC_CAL_EN_MUX_SHFT                                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_IDAC_CAL_EN_BMSK                                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_IDAC_CAL_EN_SHFT                                              0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_CORE_RX_IDAC_CAL_EN_MUX_BMSK                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_CORE_RX_IDAC_CAL_EN_MUX_SHFT                                  0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_CORE_RX_IDAC_CAL_EN_BMSK                                      0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_EN_CORE_RX_IDAC_CAL_EN_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ENABLES_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ENABLES_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ENABLES_RMSK                                                    0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ENABLES_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ENABLES_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ENABLES_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ENABLES_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ENABLES_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ENABLES_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ENABLES_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ENABLES_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ENABLES_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ENABLES_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ENABLES_IDAC_ENABLE_BMSK                                        0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ENABLES_IDAC_ENABLE_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_SIGN_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_SIGN_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_SIGN_RMSK                                                       0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_SIGN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_SIGN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_SIGN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_SIGN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_SIGN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_SIGN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_SIGN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_SIGN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_SIGN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_SIGN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_SIGN_IDAC_SIGN_BMSK                                             0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_SIGN_IDAC_SIGN_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_RMSK                                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_RX_HIGHZ_MUX_BMSK                                      0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_RX_HIGHZ_MUX_SHFT                                      0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_RX_HIGHZ_BMSK                                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE_RX_HIGHZ_SHFT                                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_ADDR                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_OFFS                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RMSK                                 0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_AC_COUPLE_MUX_BMSK                0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_AC_COUPLE_MUX_SHFT                 0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_AC_COUPLE_BMSK                    0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_AC_COUPLE_SHFT                     0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_DC_COUPLE_MUX_BMSK                 0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_DC_COUPLE_MUX_SHFT                 0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_DC_COUPLE_BMSK                     0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_DC_COUPLE_SHFT                     0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_DC_OFFSET_MUX_BMSK                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_DC_OFFSET_MUX_SHFT                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_DC_OFFSET_BMSK                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_DC_OFFSET_SHFT                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_ADDR                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_OFFS                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_RMSK                                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_TAP1CODE_MAN_VAL_BMSK                                             0x78
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_TAP1CODE_MAN_VAL_SHFT                                              0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_KTAP1_BMSK                                                         0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_1_KTAP1_SHFT                                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_ADDR                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_OFFS                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_RMSK                                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_TAP2CODE_MAN_VAL_BMSK                                             0xf8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_TAP2CODE_MAN_VAL_SHFT                                              0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_KTAP2_BMSK                                                         0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_2_KTAP2_SHFT                                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_ADDR                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_OFFS                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_RMSK                                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_TAP2ADP_MODE_BMSK                                                 0xc0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_TAP2ADP_MODE_SHFT                                                  0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_TAP2ADP_EN_BMSK                                                   0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_TAP2ADP_EN_SHFT                                                    0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_TAP2ADP_FLIP_SIGN_BMSK                                            0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_TAP2ADP_FLIP_SIGN_SHFT                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_TAP1ADP_MODE_BMSK                                                  0xc
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_TAP1ADP_MODE_SHFT                                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_TAP1ADP_EN_BMSK                                                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_TAP1ADP_EN_SHFT                                                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_TAP1ADP_FLIP_SIGN_BMSK                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_3_TAP1ADP_FLIP_SIGN_SHFT                                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_ADDR                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000c0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_OFFS                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000c0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_RMSK                                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_VTHADP_SEL_BMSK                                                   0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_VTHADP_SEL_SHFT                                                    0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_TX_ADPT_EN_MUX_BMSK                                               0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_TX_ADPT_EN_MUX_SHFT                                                0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_TX_ADPT_EN_BMSK                                                   0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_TX_ADPT_EN_SHFT                                                    0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_TAP2ADP_BYP_EN_MUX_BMSK                                            0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_TAP2ADP_BYP_EN_MUX_SHFT                                            0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_TAP2ADP_EN_MUX_BMSK                                                0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_TAP2ADP_EN_MUX_SHFT                                                0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_TAP1ADP_BYP_EN_MUX_BMSK                                            0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_TAP1ADP_BYP_EN_MUX_SHFT                                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_TAP1ADP_EN_MUX_BMSK                                                0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_4_TAP1ADP_EN_MUX_SHFT                                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH1_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000c4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH1_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000c4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH1_RMSK                                               0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH1_PRE_THRESH1_BMSK                                   0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH1_PRE_THRESH1_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH2_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000c8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH2_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000c8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH2_RMSK                                               0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH2_PRE_THRESH2_BMSK                                   0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH2_PRE_THRESH2_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000cc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000cc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_POST_THRESH2_BMSK                                  0xf0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_POST_THRESH2_SHFT                                   0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_POST_THRESH1_BMSK                                   0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_POST_THRESH_POST_THRESH1_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000d0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000d0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_MAIN_THRESH2_BMSK                                  0xf0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_MAIN_THRESH2_SHFT                                   0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_MAIN_THRESH1_BMSK                                   0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH_MAIN_THRESH1_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000d4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000d4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_VGA_UNROLL_BMSK                                          0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_VGA_UNROLL_SHFT                                           0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_VGAADP_MODE_BMSK                                         0x60
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_VGAADP_MODE_SHFT                                          0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_VGAADP_EN_BMSK                                           0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_VGAADP_EN_SHFT                                            0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_VGAADP_FLIP_SIGN_BMSK                                     0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_VGAADP_FLIP_SIGN_SHFT                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_KVGA_BMSK                                                 0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL1_KVGA_SHFT                                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000d8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000d8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_VTH_CAL_KVGA_BMSK                                        0xc0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_VTH_CAL_KVGA_SHFT                                         0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_VGAADP_BYP_EN_MUX_BMSK                                   0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_VGAADP_BYP_EN_MUX_SHFT                                    0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_VGAADP_EN_MUX_BMSK                                       0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_VGAADP_EN_MUX_SHFT                                        0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_VGACODE_MAN_VAL_BMSK                                      0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VGA_CAL_CNTRL2_VGACODE_MAN_VAL_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_ADDR                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000dc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_OFFS                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000dc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_RMSK                                                             0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_TRAN_RCVR_GMCAL_RES_BMSK                                         0x1e
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_TRAN_RCVR_GMCAL_RES_SHFT                                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_TRAN_RX_GMCAL_EN_BMSK                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_GM_CAL_TRAN_RX_GMCAL_EN_SHFT                                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_LSB_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000e0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_LSB_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000e0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_LSB_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_LSB_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_LSB_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_LSB_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_LSB_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_LSB_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_LSB_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_LSB_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_LSB_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_LSB_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_LSB_RX_VGA_GAIN2_LSB_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_LSB_RX_VGA_GAIN2_LSB_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_MSB_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000e4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_MSB_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000e4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_MSB_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_MSB_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_MSB_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_MSB_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_MSB_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_MSB_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_MSB_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_MSB_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_MSB_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_MSB_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_MSB_RX_VGA_GAIN2_MSB_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_VGA_GAIN2_MSB_RX_VGA_GAIN2_MSB_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000e8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000e8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_RMSK                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_EQDEGCAP_LOW_SPEED_BMSK                           0x78
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_EQDEGCAP_LOW_SPEED_SHFT                            0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_OFFSETADP_MODE_MUX_BMSK                            0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_OFFSETADP_MODE_MUX_SHFT                            0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_DES_EDGE_EN_MUX_BMSK                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_DES_EDGE_EN_MUX_SHFT                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_DES_EDGE_EN_BMSK                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1_DES_EDGE_EN_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000ec)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000ec)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_RMSK                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_EQADP_EN_MUX_BMSK                                 0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_EQADP_EN_MUX_SHFT                                  0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_EQADP_EN_BMSK                                     0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_EQADP_EN_SHFT                                      0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_VGA_GAIN2_MUX_BMSK                                0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_VGA_GAIN2_MUX_SHFT                                 0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_EQDEGCAP_BMSK                                      0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2_EQDEGCAP_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000f0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000f0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_RMSK                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_KEQ_BMSK                                          0x70
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_KEQ_SHFT                                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_EQADP_FLIP_SIGN_BMSK                               0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_EQADP_FLIP_SIGN_SHFT                               0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_EQADP_BYPASS_OFF_BMSK                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_EQADP_BYPASS_OFF_SHFT                              0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_EQADP_MODE_BMSK                                    0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3_EQADP_MODE_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000f4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000f4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_RMSK                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_EQ_FORCE_EN_MUX_BMSK                              0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_EQ_FORCE_EN_MUX_SHFT                               0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_EQ_FORCE_EN_BMSK                                  0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_EQ_FORCE_EN_SHFT                                   0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_RSVD_BMSK                                         0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_RSVD_SHFT                                          0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_EQCODE_MAN_VAL_BMSK                                0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4_EQCODE_MAN_VAL_SHFT                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_LOW_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000f8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_LOW_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000f8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_LOW_RMSK                                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_LOW_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_LOW_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_LOW_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_LOW_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_LOW_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_LOW_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_LOW_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_LOW_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_LOW_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_LOW_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_LOW_TSETTLE_LOW_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_LOW_TSETTLE_LOW_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_HIGH_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000000fc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_HIGH_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000fc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_HIGH_RMSK                                                0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_HIGH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_HIGH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_HIGH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_HIGH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_HIGH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_HIGH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_HIGH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_HIGH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_HIGH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_HIGH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_HIGH_TSETTLE_HIGH_BMSK                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_TSETTLE_HIGH_TSETTLE_HIGH_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_MEASURE_TIME_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000100)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_MEASURE_TIME_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000100)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_MEASURE_TIME_RMSK                                               0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_MEASURE_TIME_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_MEASURE_TIME_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_MEASURE_TIME_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_MEASURE_TIME_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_MEASURE_TIME_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_MEASURE_TIME_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_MEASURE_TIME_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_MEASURE_TIME_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_MEASURE_TIME_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_MEASURE_TIME_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_MEASURE_TIME_IDAC_MEASURE_TIME_BMSK                             0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_MEASURE_TIME_IDAC_MEASURE_TIME_SHFT                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000104)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000104)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_RMSK                                                0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_IDAC_SKIP_ACCUM_BMSK                                0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_IDAC_SKIP_ACCUM_SHFT                                 0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_IDAC_ACCUM_SAT_VALUE_BMSK                           0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR_IDAC_ACCUM_SAT_VALUE_SHFT                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_LSB_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000108)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_LSB_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000108)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_LSB_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_LSB_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_LSB_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_LSB_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_LSB_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_LSB_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_LSB_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_LSB_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_LSB_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_LSB_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_LSB_RX_EQ_OFFSET_LSB_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_LSB_RX_EQ_OFFSET_LSB_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_MSB_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000010c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_MSB_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000010c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_MSB_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_MSB_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_MSB_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_MSB_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_MSB_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_MSB_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_MSB_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_MSB_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_MSB_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_MSB_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_MSB_RX_EQ_OFFSET_MSB_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_MSB_RX_EQ_OFFSET_MSB_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_ADDR                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000110)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFS                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000110)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_RMSK                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_RX_EQ_OFFSET_MUX_BMSK                       0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_RX_EQ_OFFSET_MUX_SHFT                        0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_KOFFSET_BMSK                                0x70
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_KOFFSET_SHFT                                 0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFSETADP_FLIP_SIGN_BMSK                     0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFSETADP_FLIP_SIGN_SHFT                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFSETADP_MODE_BMSK                          0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFSETADP_MODE_SHFT                          0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFSETADP_EN_MUX_BMSK                        0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFSETADP_EN_MUX_SHFT                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFSETADP_EN_BMSK                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFSETADP_EN_SHFT                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000114)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000114)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2_RMSK                                           0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2_OFFSETCODE_MAN_VAL_BMSK                        0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2_OFFSETCODE_MAN_VAL_SHFT                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000118)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000118)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_CORE_RX_SIGDET_MUX_BMSK                                  0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_CORE_RX_SIGDET_MUX_SHFT                                   0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_CORE_RX_SIGDET_BMSK                                      0x60
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_CORE_RX_SIGDET_SHFT                                       0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_SIGDET_FLT_BYP_BMSK                                      0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_SIGDET_FLT_BYP_SHFT                                       0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_SIGDET_LP_EN_MUX_BMSK                                     0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_SIGDET_LP_EN_MUX_SHFT                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_SIGDET_LP_EN_BMSK                                         0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_SIGDET_LP_EN_SHFT                                         0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_SIGDET_EN_MUX_BMSK                                        0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_SIGDET_EN_MUX_SHFT                                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_SIGDET_EN_BMSK                                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_ENABLES_SIGDET_EN_SHFT                                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000011c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000011c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_RMSK                                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_SIGDET_CAP_CTRL_BMSK                                       0xf0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_SIGDET_CAP_CTRL_SHFT                                        0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_SIGDET_BW_CTRL_BMSK                                         0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_CNTRL_SIGDET_BW_CTRL_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000120)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000120)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_RMSK                                                         0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_SIGDET_UFS_MODE_BMSK                                         0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_SIGDET_UFS_MODE_SHFT                                          0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_SIGDET_LVL_MUX_BMSK                                          0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_SIGDET_LVL_MUX_SHFT                                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_SIGDET_LVL_BMSK                                               0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_LVL_SIGDET_LVL_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000124)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000124)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_RMSK                                              0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_SIGDET_DEGLITCH_CTRL_BMSK                         0x1e
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_SIGDET_DEGLITCH_CTRL_SHFT                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_SIGDET_DEGLITCH_BYP_BMSK                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL_SIGDET_DEGLITCH_BYP_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000128)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000128)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_RMSK                                                            0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_RX_MODE_BAND_COUPLED_BMSK                                       0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_RX_MODE_BAND_COUPLED_SHFT                                        0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_RX_BAND_UNMODIFIED_MUX_BMSK                                     0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_RX_BAND_UNMODIFIED_MUX_SHFT                                      0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_RX_BAND_10_HALF_BMSK                                            0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_RX_BAND_10_HALF_SHFT                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_RX_BAND_01_HALF_BMSK                                             0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_RX_BAND_01_HALF_SHFT                                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_RX_BAND_MUX_BMSK                                                 0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_RX_BAND_MUX_SHFT                                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_RX_BAND_BMSK                                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_BAND_RX_BAND_SHFT                                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000012c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000012c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_RMSK                                                    0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_CDR_DN_BMSK                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_CDR_DN_SHFT                                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_CDR_UP_BMSK                                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_CDR_UP_SHFT                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_CDR_FREEZE_BMSK                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_FREEZE_UP_DN_CDR_FREEZE_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_ADDR                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000130)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_OFFS                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000130)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_RMSK                                                  0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_CDR_RESET_OVERRIDE_MUX_BMSK                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_CDR_RESET_OVERRIDE_MUX_SHFT                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_CDR_RESET_OVERRIDE_BMSK                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_CDR_RESET_OVERRIDE_CDR_RESET_OVERRIDE_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000134)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000134)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_RMSK                                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_SVS_MODE_MUX_BMSK                                     0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_SVS_MODE_MUX_SHFT                                      0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_SVS_MODE_BMSK                                         0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_SVS_MODE_SHFT                                          0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_RX_CLOCK_EDGE_BMSK                                    0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_RX_CLOCK_EDGE_SHFT                                     0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_RXCLK_HS_SWITCH_FORCE_DISABLE_BMSK                    0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_RXCLK_HS_SWITCH_FORCE_DISABLE_SHFT                     0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_RXCLK_HS_SWITCH_MUX_BMSK                               0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_RXCLK_HS_SWITCH_MUX_SHFT                               0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_RXCLK_HS_SWITCH_BMSK                                   0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_RXCLK_HS_SWITCH_SHFT                                   0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_IDATA_MARKER_FLIP_BMSK                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_IDATA_MARKER_FLIP_SHFT                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_QUARTER_RATE_EDGE_ON_FIVE_ONE_BMSK                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_INTERFACE_MODE_QUARTER_RATE_EDGE_ON_FIVE_ONE_SHFT                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_JITTER_GEN_MODE_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000138)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_JITTER_GEN_MODE_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000138)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_JITTER_GEN_MODE_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_JITTER_GEN_MODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_JITTER_GEN_MODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_JITTER_GEN_MODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_JITTER_GEN_MODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_JITTER_GEN_MODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_JITTER_GEN_MODE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_JITTER_GEN_MODE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_JITTER_GEN_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_JITTER_GEN_MODE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_JITTER_GEN_MODE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_JITTER_GEN_MODE_JITTERGENMODE_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_JITTER_GEN_MODE_JITTERGENMODE_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP1_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000013c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP1_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000013c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP1_RMSK                                                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP1_SJ_AMPLITUDE1_BMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP1_SJ_AMPLITUDE1_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP2_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000140)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP2_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000140)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP2_RMSK                                                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP2_SJ_AMPLITUDE2_BMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_AMP2_SJ_AMPLITUDE2_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER1_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000144)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER1_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000144)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER1_RMSK                                                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER1_SJ_PERIOD1_BMSK                                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER1_SJ_PERIOD1_SHFT                                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER2_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000148)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER2_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000148)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER2_RMSK                                                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER2_SJ_PERIOD2_BMSK                                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SJ_PER2_SJ_PERIOD2_SHFT                                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET1_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000014c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET1_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000014c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET1_RMSK                                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET1_PPMOFFSET1_BMSK                                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET1_PPMOFFSET1_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET2_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000150)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET2_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000150)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET2_RMSK                                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET2_PPMOFFSET2_BMSK                                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PPM_OFFSET2_PPMOFFSET2_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD1_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000154)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD1_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000154)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD1_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD1_SIGN_PPM_PERIOD1_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD1_SIGN_PPM_PERIOD1_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD2_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000158)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD2_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000158)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD2_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD2_SIGN_PPM_PERIOD2_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_SIGN_PPM_PERIOD2_SIGN_PPM_PERIOD2_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_ADDR                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000015c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_OFFS                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000015c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_RMSK                                             0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_RX_PWM_GEAR_MUX_BMSK                             0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_RX_PWM_GEAR_MUX_SHFT                              0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_RX_PWM_GEAR_BMSK                                 0x1c
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_RX_PWM_GEAR_SHFT                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_RX_PWM_EN_MUX_BMSK                                0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_RX_PWM_EN_MUX_SHFT                                0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_RX_PWM_EN_BMSK                                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_ENABLE_AND_DATA_RX_PWM_EN_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR1_TIMEOUT_COUNT_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000160)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR1_TIMEOUT_COUNT_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000160)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR1_TIMEOUT_COUNT_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR1_TIMEOUT_COUNT_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR1_TIMEOUT_COUNT_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR1_TIMEOUT_COUNT_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR1_TIMEOUT_COUNT_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR1_TIMEOUT_COUNT_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR1_TIMEOUT_COUNT_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR1_TIMEOUT_COUNT_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR1_TIMEOUT_COUNT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR1_TIMEOUT_COUNT_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR1_TIMEOUT_COUNT_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR1_TIMEOUT_COUNT_RX_PWM_GEAR1_COUNT_BMSK                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR1_TIMEOUT_COUNT_RX_PWM_GEAR1_COUNT_SHFT                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR2_TIMEOUT_COUNT_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000164)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR2_TIMEOUT_COUNT_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000164)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR2_TIMEOUT_COUNT_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR2_TIMEOUT_COUNT_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR2_TIMEOUT_COUNT_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR2_TIMEOUT_COUNT_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR2_TIMEOUT_COUNT_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR2_TIMEOUT_COUNT_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR2_TIMEOUT_COUNT_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR2_TIMEOUT_COUNT_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR2_TIMEOUT_COUNT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR2_TIMEOUT_COUNT_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR2_TIMEOUT_COUNT_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR2_TIMEOUT_COUNT_RX_PWM_GEAR2_COUNT_BMSK                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR2_TIMEOUT_COUNT_RX_PWM_GEAR2_COUNT_SHFT                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR3_TIMEOUT_COUNT_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000168)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR3_TIMEOUT_COUNT_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000168)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR3_TIMEOUT_COUNT_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR3_TIMEOUT_COUNT_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR3_TIMEOUT_COUNT_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR3_TIMEOUT_COUNT_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR3_TIMEOUT_COUNT_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR3_TIMEOUT_COUNT_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR3_TIMEOUT_COUNT_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR3_TIMEOUT_COUNT_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR3_TIMEOUT_COUNT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR3_TIMEOUT_COUNT_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR3_TIMEOUT_COUNT_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR3_TIMEOUT_COUNT_RX_PWM_GEAR3_COUNT_BMSK                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR3_TIMEOUT_COUNT_RX_PWM_GEAR3_COUNT_SHFT                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR4_TIMEOUT_COUNT_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000016c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR4_TIMEOUT_COUNT_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000016c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR4_TIMEOUT_COUNT_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR4_TIMEOUT_COUNT_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR4_TIMEOUT_COUNT_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR4_TIMEOUT_COUNT_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR4_TIMEOUT_COUNT_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR4_TIMEOUT_COUNT_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR4_TIMEOUT_COUNT_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR4_TIMEOUT_COUNT_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR4_TIMEOUT_COUNT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR4_TIMEOUT_COUNT_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR4_TIMEOUT_COUNT_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR4_TIMEOUT_COUNT_RX_PWM_GEAR4_COUNT_BMSK                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_PWM_GEAR4_TIMEOUT_COUNT_RX_PWM_GEAR4_COUNT_SHFT                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_LOW_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000170)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_LOW_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000170)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_LOW_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_LOW_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_LOW_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_LOW_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_LOW_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_LOW_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_LOW_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_LOW_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_LOW_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_LOW_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_LOW_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_LOW_RX_MODE_00_7_0_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_LOW_RX_MODE_00_7_0_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000174)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000174)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH_RX_MODE_00_15_8_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH_RX_MODE_00_15_8_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH2_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000178)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH2_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000178)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH2_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH2_RX_MODE_00_23_16_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH2_RX_MODE_00_23_16_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH3_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000017c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH3_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000017c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH3_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH3_RX_MODE_00_31_24_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH3_RX_MODE_00_31_24_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH4_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000180)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH4_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000180)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH4_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH4_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH4_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH4_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH4_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH4_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH4_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH4_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH4_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH4_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH4_RX_MODE_00_39_32_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_00_HIGH4_RX_MODE_00_39_32_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_LOW_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000184)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_LOW_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000184)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_LOW_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_LOW_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_LOW_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_LOW_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_LOW_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_LOW_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_LOW_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_LOW_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_LOW_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_LOW_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_LOW_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_LOW_RX_MODE_01_7_0_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_LOW_RX_MODE_01_7_0_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000188)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000188)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH_RX_MODE_01_15_8_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH_RX_MODE_01_15_8_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH2_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000018c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH2_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000018c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH2_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH2_RX_MODE_01_23_16_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH2_RX_MODE_01_23_16_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH3_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000190)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH3_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000190)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH3_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH3_RX_MODE_01_31_24_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH3_RX_MODE_01_31_24_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH4_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000194)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH4_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000194)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH4_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH4_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH4_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH4_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH4_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH4_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH4_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH4_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH4_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH4_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH4_RX_MODE_01_39_32_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_01_HIGH4_RX_MODE_01_39_32_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_LOW_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x00000198)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_LOW_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000198)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_LOW_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_LOW_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_LOW_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_LOW_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_LOW_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_LOW_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_LOW_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_LOW_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_LOW_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_LOW_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_LOW_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_LOW_RX_MODE_10_7_0_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_LOW_RX_MODE_10_7_0_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x0000019c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000019c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH_RX_MODE_10_15_8_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH_RX_MODE_10_15_8_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH2_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH2_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH2_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH2_RX_MODE_10_23_16_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH2_RX_MODE_10_23_16_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH3_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH3_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH3_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH3_RX_MODE_10_31_24_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH3_RX_MODE_10_31_24_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH4_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH4_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH4_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH4_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH4_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH4_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH4_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH4_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH4_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH4_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH4_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH4_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH4_RX_MODE_10_39_32_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_MODE_10_HIGH4_RX_MODE_10_39_32_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_RMSK                                                         0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_PHPRE_GAIN_SIGN_BMSK                                         0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_PHPRE_GAIN_SIGN_SHFT                                          0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_PHPRE_GAIN_BMSK                                              0x3c
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_PHPRE_GAIN_SHFT                                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_PHPRE_EN_MUX_BMSK                                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_PHPRE_EN_MUX_SHFT                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_PHPRE_EN_BMSK                                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_CTRL_PHPRE_EN_SHFT                                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_INITVAL_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_INITVAL_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_INITVAL_RMSK                                                      0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_INITVAL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_INITVAL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_INITVAL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_INITVAL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_INITVAL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_INITVAL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_INITVAL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_INITVAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_INITVAL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_INITVAL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_INITVAL_PHPRE_INITVAL_BMSK                                        0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PHPRE_INITVAL_PHPRE_INITVAL_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_EN_TIMER_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_EN_TIMER_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_EN_TIMER_RMSK                                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_EN_TIMER_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_EN_TIMER_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_EN_TIMER_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_EN_TIMER_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_EN_TIMER_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_EN_TIMER_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_EN_TIMER_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_EN_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_EN_TIMER_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_EN_TIMER_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_EN_TIMER_VGA_DFE_EN_TIMER_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_EN_TIMER_VGA_DFE_EN_TIMER_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_RMSK                                           0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_POST_CAL_CTLE_OFFSET_BMSK                      0x38
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_POST_CAL_CTLE_OFFSET_SHFT                       0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_POST_CAL_TAP1_OFFSET_BMSK                       0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET_POST_CAL_TAP1_OFFSET_SHFT                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_RX_DCC_CAL_ANA_EN_MUX_BMSK                                    0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_RX_DCC_CAL_ANA_EN_MUX_SHFT                                     0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_RX_DCC_CAL_ANA_EN_BMSK                                        0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_RX_DCC_CAL_ANA_EN_SHFT                                         0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_DCC_SETTLE_TIME_BMSK                                          0x30
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_DCC_SETTLE_TIME_SHFT                                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_DCC_MAG_POL_FLIP_BMSK                                          0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_DCC_MAG_POL_FLIP_SHFT                                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_DCC_SIGN_POL_FLIP_BMSK                                         0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_DCC_SIGN_POL_FLIP_SHFT                                         0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_RX_DCC_CAL_EN_MUX_BMSK                                         0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_RX_DCC_CAL_EN_MUX_SHFT                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_RX_DCC_CAL_EN_BMSK                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL1_RX_DCC_CAL_EN_SHFT                                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001c0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001c0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_RMSK                                                          0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_IDCC_CODE_MUX_BMSK                                            0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_IDCC_CODE_MUX_SHFT                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_IDCC_CODE_BMSK                                                 0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DCC_CTRL2_IDCC_CODE_SHFT                                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_CODE_ADDR                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001c4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_CODE_OFFS                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001c4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_CODE_RMSK                                                           0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_CODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_CODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_CODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_CODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_CODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_CODE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_CODE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_CODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_CODE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_CODE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_CODE_VTH_CODE_BMSK                                                  0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_CODE_VTH_CODE_SHFT                                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MIN_THRESH_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001c8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MIN_THRESH_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001c8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MIN_THRESH_RMSK                                                     0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MIN_THRESH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MIN_THRESH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MIN_THRESH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MIN_THRESH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MIN_THRESH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MIN_THRESH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MIN_THRESH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MIN_THRESH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MIN_THRESH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MIN_THRESH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MIN_THRESH_VTH_MIN_THRESH_BMSK                                      0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MIN_THRESH_VTH_MIN_THRESH_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MAX_THRESH_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001cc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MAX_THRESH_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001cc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MAX_THRESH_RMSK                                                     0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MAX_THRESH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MAX_THRESH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MAX_THRESH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MAX_THRESH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MAX_THRESH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MAX_THRESH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MAX_THRESH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MAX_THRESH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MAX_THRESH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MAX_THRESH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MAX_THRESH_VTH_MAX_THRESH_BMSK                                      0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_VTH_MAX_THRESH_VTH_MAX_THRESH_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_CTRL_1_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001d0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_CTRL_1_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001d0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_CTRL_1_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_CTRL_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_CTRL_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_CTRL_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_CTRL_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_CTRL_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_CTRL_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_CTRL_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_CTRL_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_CTRL_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_CTRL_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_CTRL_1_ALOG_OBSV_BUS_CTRL_1_SEL_BMSK                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_CTRL_1_ALOG_OBSV_BUS_CTRL_1_SEL_SHFT                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL1_ADDR                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001d4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL1_OFFS                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001d4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL1_RMSK                                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL1_PI_CTRL1_STATUS_BMSK                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL1_PI_CTRL1_STATUS_SHFT                                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL2_ADDR                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001d8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL2_OFFS                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001d8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL2_RMSK                                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL2_PI_CTRL2_STATUS_BMSK                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_CTRL2_PI_CTRL2_STATUS_SHFT                                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_QUAD_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001dc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_QUAD_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001dc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_QUAD_RMSK                                                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_QUAD_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_QUAD_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_QUAD_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_QUAD_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_QUAD_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_QUAD_PI_QUAD_STATUS_BMSK                                              0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_PI_QUAD_PI_QUAD_STATUS_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA1_ADDR                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001e0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA1_OFFS                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001e0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA1_RMSK                                                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA1_IDATA1_STATUS_BMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA1_IDATA1_STATUS_SHFT                                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA2_ADDR                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001e4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA2_OFFS                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001e4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA2_RMSK                                                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA2_IDATA2_STATUS_BMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_IDATA2_IDATA2_STATUS_SHFT                                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA1_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001e8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA1_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001e8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA1_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA1_AUXDATA1_STATUS_BMSK                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA1_AUXDATA1_STATUS_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA2_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001ec)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA2_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001ec)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA2_RMSK                                                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA2_AUXDATA2_STATUS_BMSK                                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AUX_DATA2_AUXDATA2_STATUS_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTP_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001f0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTP_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001f0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTP_RMSK                                                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTP_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTP_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTP_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTP_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTP_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTP_AC_JTAG_OUTP_STATUS_BMSK                                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTP_AC_JTAG_OUTP_STATUS_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTN_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001f4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTN_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001f4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTN_RMSK                                                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTN_AC_JTAG_OUTN_STATUS_BMSK                                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_AC_JTAG_OUTN_AC_JTAG_OUTN_STATUS_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_SIGDET_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001f8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_SIGDET_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001f8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_SIGDET_RMSK                                                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_SIGDET_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_SIGDET_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_SIGDET_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_SIGDET_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_SIGDET_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_SIGDET_RX_SIGDET_OUT_STATUS_BMSK                                      0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_RX_SIGDET_RX_SIGDET_OUT_STATUS_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_STATUS_1_ADDR                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE      + 0x000001fc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_STATUS_1_OFFS                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001fc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_STATUS_1_RMSK                                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_STATUS_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_STATUS_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_STATUS_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_STATUS_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_STATUS_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_STATUS_1_ALOG_OBSV_BUS_STATUS_1_BMSK                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX0_ALOG_OBSV_BUS_STATUS_1_ALOG_OBSV_BUS_STATUS_1_SHFT                       0x0

/*----------------------------------------------------------------------------
 * MODULE: AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX
 *--------------------------------------------------------------------------*/

#define AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE                             (AHB2PHY_SOUTH_AHB2PHY_SOUTH_BASE      + 0x0000a600)
#define AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS                        0x0000a600

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000000)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000000)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_BIST_ERROR_INJECT_BMSK                             0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_BIST_ERROR_INJECT_SHFT                              0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_BIST_LANE_NUMBER_BMSK                              0x60
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_BIST_LANE_NUMBER_SHFT                               0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_BISTMODE_BMSK                                      0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_MODE_LANENO_BISTMODE_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000004)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000004)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_RMSK                                                     0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_BIST_FROM_PCS_BMSK                                       0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_BIST_FROM_PCS_SHFT                                       0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_BIST_INVERT_RX_BMSK                                      0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_BIST_INVERT_RX_SHFT                                      0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_BIST_INVERT_TX_BMSK                                      0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_INVERT_BIST_INVERT_TX_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000008)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000008)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_RMSK                                                  0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_DISABLE_LPB_TX_CLKGATE_BMSK                           0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_DISABLE_LPB_TX_CLKGATE_SHFT                            0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_TXONLY_CLOCK_EDGE_BMSK                                0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_TXONLY_CLOCK_EDGE_SHFT                                 0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_GATED_CLK_EN_BMSK                                     0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_GATED_CLK_EN_SHFT                                      0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_CLKBUF_EN_LANE1_MUX_BMSK                               0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_CLKBUF_EN_LANE1_MUX_SHFT                               0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_CLKBUF_EN_LANE1_BMSK                                   0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_CLKBUF_EN_LANE1_SHFT                                   0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_CLKBUF_EN_LANE0_MUX_BMSK                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_CLKBUF_EN_LANE0_MUX_SHFT                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_CLKBUF_EN_LANE0_BMSK                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_CLKBUF_ENABLE_CLKBUF_EN_LANE0_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x0000000c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000000c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_RMSK                                               0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_TX_EMP_POST1_LVL_MUX_BMSK                          0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_TX_EMP_POST1_LVL_MUX_SHFT                           0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_TX_EMP_POST1_LVL_BMSK                              0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_EMP_POST1_LVL_TX_EMP_POST1_LVL_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_ADDR                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000010)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_OFFS                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000010)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_RMSK                                           0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_TX_IDLE_LVL_MUX_BMSK                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_TX_IDLE_LVL_MUX_SHFT                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_TX_IDLE_LVL_BMSK                               0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP_TX_IDLE_LVL_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000014)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000014)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_RMSK                                                     0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_TX_DRV_LVL_MUX_BMSK                                      0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_TX_DRV_LVL_MUX_SHFT                                       0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_TX_DRV_LVL_BMSK                                          0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_TX_DRV_LVL_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OFFSET_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000018)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OFFSET_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000018)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OFFSET_RMSK                                               0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OFFSET_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OFFSET_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OFFSET_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OFFSET_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OFFSET_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OFFSET_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OFFSET_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OFFSET_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OFFSET_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OFFSET_TX_DRV_LVL_OFFSET_BMSK                             0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_DRV_LVL_OFFSET_TX_DRV_LVL_OFFSET_SHFT                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_ADDR                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x0000001c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_OFFS                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000001c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_RMSK                                                  0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_RESET_TSYNC_EN_MUX_BMSK                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_RESET_TSYNC_EN_MUX_SHFT                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_RESET_TSYNC_EN_BMSK                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_TSYNC_EN_RESET_TSYNC_EN_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000020)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000020)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_RMSK                                          0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_STALL_EN_MUX_BMSK                             0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_STALL_EN_MUX_SHFT                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_STALL_EN_BMSK                                 0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_STALL_EN_SHFT                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_PRE_EN_MUX_BMSK                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_PRE_EN_MUX_SHFT                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_PRE_EN_BMSK                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN_PRE_EN_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000024)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000024)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_RMSK                                                         0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_TX_BAND_MUX_BMSK                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_TX_BAND_MUX_SHFT                                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_TX_BAND_BMSK                                                 0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_BAND_TX_BAND_SHFT                                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000028)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000028)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_RMSK                                                       0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_SLEW_CNTL_MUX_BMSK                                         0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_SLEW_CNTL_MUX_SHFT                                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_SLEW_CNTL_BMSK                                             0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SLEW_CNTL_SLEW_CNTL_SHFT                                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x0000002c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000002c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_RMSK                                               0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_TX_CLKDIV_PHASE_BMSK                               0x60
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_TX_CLKDIV_PHASE_SHFT                                0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_TX_PWM_PHASE_BMSK                                  0x18
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_TX_PWM_PHASE_SHFT                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_SEL_20B_10B_BMSK                                    0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_SEL_20B_10B_SHFT                                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_SEL_10B_8B_MUX_BMSK                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_SEL_10B_8B_MUX_SHFT                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_SEL_10B_8B_BMSK                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_INTERFACE_SELECT_SEL_10B_8B_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000030)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000030)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_RMSK                                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_PLACEHOLDER_CHAIN_INPUT_BMSK                                 0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_PLACEHOLDER_CHAIN_INPUT_SHFT                                  0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_LINE_LPB_EN_MUX_BMSK                                         0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_LINE_LPB_EN_MUX_SHFT                                          0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_LINE_LPB_EN_BMSK                                             0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_LINE_LPB_EN_SHFT                                              0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_TX_RCLK_LPB_EN_BMSK                                          0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_TX_RCLK_LPB_EN_SHFT                                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_SER_LPB_EN_MUX_BMSK                                           0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_SER_LPB_EN_MUX_SHFT                                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_SER_LPB_EN_BMSK                                               0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_SER_LPB_EN_SHFT                                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_PAR_LPB_EN_BMSK                                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_PAR_LPB_EN_SHFT                                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_RCLK_LPB_EN_BMSK                                              0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LPB_EN_RCLK_LPB_EN_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000034)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000034)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_RES_CODE_LANE_TX_MUX_BMSK                          0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_RES_CODE_LANE_TX_MUX_SHFT                           0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_RES_CODE_LANE_TX_BMSK                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_TX_RES_CODE_LANE_TX_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000038)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000038)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_RES_CODE_LANE_RX_MUX_BMSK                          0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_RES_CODE_LANE_RX_MUX_SHFT                           0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_RES_CODE_LANE_RX_BMSK                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_RX_RES_CODE_LANE_RX_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_TX_ADDR                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x0000003c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_TX_OFFS                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000003c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_TX_RMSK                                        0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_TX_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_TX_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_TX_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_TX_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_TX_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_TX_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_TX_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_TX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_TX_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_TX_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_TX_RES_CODE_LANE_OFFSET_TX_BMSK                0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_TX_RES_CODE_LANE_OFFSET_TX_SHFT                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_RX_ADDR                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000040)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_RX_OFFS                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000040)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_RX_RMSK                                        0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_RX_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_RX_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_RX_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_RX_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_RX_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_RX_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_RX_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_RX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_RX_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_RX_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_RX_RES_CODE_LANE_OFFSET_RX_BMSK                0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_RX_RES_CODE_LANE_OFFSET_RX_SHFT                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH1_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000044)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH1_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000044)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH1_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH1_PERL_LENGTH1_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH1_PERL_LENGTH1_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH2_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000048)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH2_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000048)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH2_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH2_PERL_LENGTH2_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PERL_LENGTH2_PERL_LENGTH2_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x0000004c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000004c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_RMSK                                              0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_MUX_BMSK                           0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_MUX_SHFT                            0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_BMSK                               0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_SHFT                                0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_EN_MUX_BMSK                         0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_EN_MUX_SHFT                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_EN_BMSK                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_EN_SHFT                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_IN_EN_MUX_BMSK                          0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_IN_EN_MUX_SHFT                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_IN_EN_BMSK                              0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_IN_EN_SHFT                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS_SEL_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000050)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS_SEL_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000050)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS_SEL_RMSK                                                   0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS_SEL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS_SEL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS_SEL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS_SEL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS_SEL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS_SEL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS_SEL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS_SEL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS_SEL_DEBUGBUS_SEL_BMSK                                      0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS_SEL_DEBUGBUS_SEL_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000054)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000054)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_RMSK                                            0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_TRANSCEIVER_BIAS_EN_MUX_BMSK                    0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_TRANSCEIVER_BIAS_EN_MUX_SHFT                     0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_TRANSCEIVER_BIAS_EN_BMSK                        0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_TRANSCEIVER_BIAS_EN_SHFT                         0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_TX_EN_LANE1_MUX_BMSK                             0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_TX_EN_LANE1_MUX_SHFT                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_TX_EN_LANE1_BMSK                                 0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_TX_EN_LANE1_SHFT                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_TX_EN_LANE0_MUX_BMSK                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_TX_EN_LANE0_MUX_SHFT                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_TX_EN_LANE0_BMSK                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN_TX_EN_LANE0_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000058)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000058)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_RMSK                                                  0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_DRVR_EN_BMSK                                          0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_DRVR_EN_SHFT                                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_MUX_BMSK                                0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_MUX_SHFT                                0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_BMSK                                    0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_SHFT                                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_MUX_BMSK                                0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_MUX_SHFT                                0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_BMSK                                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x0000005c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000005c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_RMSK                                                      0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_TX_POL_INV_LANE1_MUX_BMSK                                 0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_TX_POL_INV_LANE1_MUX_SHFT                                 0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_TX_POL_INV_LANE1_BMSK                                     0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_TX_POL_INV_LANE1_SHFT                                     0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_TX_POL_INV_LANE0_MUX_BMSK                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_TX_POL_INV_LANE0_MUX_SHFT                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_TX_POL_INV_LANE0_BMSK                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_POL_INV_TX_POL_INV_LANE0_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_ADDR                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000060)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_OFFS                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000060)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_RMSK                                     0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_PAR_RATE_MUX_BMSK                        0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_PAR_RATE_MUX_SHFT                         0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_PAR_RATE_BMSK                            0x30
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_PAR_RATE_SHFT                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_IDLE_EN_MUX_BMSK                          0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_IDLE_EN_MUX_SHFT                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_IDLE_EN_BMSK                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_IDLE_EN_SHFT                              0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_RCV_DET_EN_MUX_BMSK                       0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_RCV_DET_EN_MUX_SHFT                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_RCV_DET_EN_BMSK                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN_RCV_DET_EN_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN1_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000064)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN1_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000064)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN1_RMSK                                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN1_BIST_PATTERN1_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN1_BIST_PATTERN1_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN2_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000068)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN2_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000068)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN2_RMSK                                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN2_BIST_PATTERN2_BMSK                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN2_BIST_PATTERN2_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN3_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x0000006c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN3_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000006c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN3_RMSK                                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN3_BIST_PATTERN3_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN3_BIST_PATTERN3_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN4_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000070)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN4_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000070)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN4_RMSK                                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN4_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN4_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN4_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN4_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN4_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN4_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN4_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN4_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN4_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN4_BIST_PATTERN4_BMSK                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN4_BIST_PATTERN4_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN5_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000074)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN5_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000074)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN5_RMSK                                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN5_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN5_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN5_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN5_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN5_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN5_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN5_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN5_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN5_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN5_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN5_BIST_PATTERN5_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN5_BIST_PATTERN5_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN6_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000078)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN6_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000078)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN6_RMSK                                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN6_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN6_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN6_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN6_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN6_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN6_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN6_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN6_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN6_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN6_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN6_BIST_PATTERN6_BMSK                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN6_BIST_PATTERN6_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN7_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x0000007c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN7_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000007c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN7_RMSK                                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN7_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN7_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN7_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN7_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN7_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN7_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN7_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN7_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN7_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN7_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN7_BIST_PATTERN7_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN7_BIST_PATTERN7_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN8_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000080)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN8_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000080)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN8_RMSK                                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN8_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN8_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN8_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN8_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN8_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN8_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN8_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN8_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN8_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN8_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN8_BIST_PATTERN8_BMSK                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_PATTERN8_BIST_PATTERN8_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_1_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000084)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_1_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000084)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_1_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_1_LANE_MODE1_BMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_1_LANE_MODE1_SHFT                                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_2_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000088)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_2_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000088)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_2_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_2_LANE_MODE2_BMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_2_LANE_MODE2_SHFT                                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_3_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x0000008c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_3_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000008c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_3_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_3_LANE_MODE3_BMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_MODE_3_LANE_MODE3_SHFT                                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL1_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000090)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL1_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000090)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL1_RMSK                                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL1_ATB_SEL1_BMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL1_ATB_SEL1_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL2_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000094)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL2_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000094)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL2_RMSK                                                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL2_ATB_SEL2_BMSK                                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ATB_SEL2_ATB_SEL2_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_ADDR                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000098)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_OFFS                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000098)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_RMSK                                                  0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_RCV_DET_LVL_MUX_BMSK                                  0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_RCV_DET_LVL_MUX_SHFT                                  0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_RCV_DET_LVL_BMSK                                      0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_RCV_DET_LVL_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x0000009c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000009c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_RMSK                                               0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_RCV_DET_LVL_2_BMSK                                 0x38
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_RCV_DET_LVL_2_SHFT                                  0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_RCV_DET_LVL_1_BMSK                                  0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RCV_DETECT_LVL_2_RCV_DET_LVL_1_SHFT                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED1_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED1_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED1_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED1_PRBS_SEED1_BMSK                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED1_PRBS_SEED1_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED2_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED2_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED2_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED2_PRBS_SEED2_BMSK                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED2_PRBS_SEED2_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED3_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED3_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED3_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED3_PRBS_SEED3_BMSK                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED3_PRBS_SEED3_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED4_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED4_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED4_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED4_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED4_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED4_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED4_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED4_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED4_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED4_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED4_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED4_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED4_PRBS_SEED4_BMSK                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRBS_SEED4_PRBS_SEED4_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_RMSK                                                      0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_SW_CDR_RESET_BMSK                                         0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_SW_CDR_RESET_SHFT                                          0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_JITTER_GEN_RESET_BMSK                                     0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_JITTER_GEN_RESET_SHFT                                      0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_SW_TSYNC_BMSK                                             0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_SW_TSYNC_SHFT                                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_SW_RSYNC_BMSK                                              0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_SW_RSYNC_SHFT                                              0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_RSVD_BMSK                                                  0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_RSVD_SHFT                                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_BIST_TX_RESET_BMSK                                         0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_BIST_TX_RESET_SHFT                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_BIST_RX_RESET_BMSK                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_BIST_RX_RESET_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_RMSK                                                 0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_TSYNC_MUX_BMSK                                       0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_TSYNC_MUX_SHFT                                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_RSYNC_MUX_BMSK                                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_RESET_GEN_MUXES_RSYNC_MUX_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_RMSK                                                0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_TX_LVL_UPDATE_MUX_BMSK                              0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_TX_LVL_UPDATE_MUX_SHFT                              0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_TX_LVL_UPDATE_BMSK                                  0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_TX_LVL_UPDATE_SHFT                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_EMP_EN_MUX_BMSK                                     0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_EMP_EN_MUX_SHFT                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_EMP_EN_BMSK                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TRAN_DRVR_EMP_EN_EMP_EN_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_INTERFACE_MODE_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_INTERFACE_MODE_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_INTERFACE_MODE_RMSK                                               0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_INTERFACE_MODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_INTERFACE_MODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_INTERFACE_MODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_INTERFACE_MODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_INTERFACE_MODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_INTERFACE_MODE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_INTERFACE_MODE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_INTERFACE_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_INTERFACE_MODE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_INTERFACE_MODE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_INTERFACE_MODE_TXINTERFACE_MODE_BMSK                              0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_TX_INTERFACE_MODE_TXINTERFACE_MODE_SHFT                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000c0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000c0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_RMSK                                                       0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_TX_PWM_GEAR_MUX_BMSK                                       0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_TX_PWM_GEAR_MUX_SHFT                                        0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_TX_PWM_GEAR_BMSK                                           0x1c
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_TX_PWM_GEAR_SHFT                                            0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_TX_PWM_EN_MUX_BMSK                                          0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_TX_PWM_EN_MUX_SHFT                                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_TX_PWM_EN_BMSK                                              0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_CTRL_TX_PWM_EN_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000c4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000c4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_RMSK                                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_TX_PWM_NDATA_MUX_BMSK                            0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_TX_PWM_NDATA_MUX_SHFT                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_TX_PWM_NDATA_BMSK                                0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_ENCODED_OR_DATA_TX_PWM_NDATA_SHFT                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND2_ADDR                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000c8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND2_OFFS                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000c8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND2_RMSK                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND2_TX_PWM_DIVGEAR1_BMSK                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND2_TX_PWM_DIVGEAR1_SHFT                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND2_ADDR                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000cc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND2_OFFS                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000cc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND2_RMSK                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND2_TX_PWM_DIVGEAR2_BMSK                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND2_TX_PWM_DIVGEAR2_SHFT                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND2_ADDR                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000d0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND2_OFFS                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000d0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND2_RMSK                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND2_TX_PWM_DIVGEAR3_BMSK                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND2_TX_PWM_DIVGEAR3_SHFT                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND2_ADDR                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000d4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND2_OFFS                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000d4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND2_RMSK                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND2_TX_PWM_DIVGEAR4_BMSK                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND2_TX_PWM_DIVGEAR4_SHFT                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1_ADDR                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000d8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1_OFFS                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000d8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1_RMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1_TX_PWM_DIVGEAR1A_BMSK                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1_TX_PWM_DIVGEAR1A_SHFT                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1_ADDR                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000dc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1_OFFS                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000dc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1_RMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1_TX_PWM_DIVGEAR2A_BMSK                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1_TX_PWM_DIVGEAR2A_SHFT                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1_ADDR                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000e0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1_OFFS                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000e0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1_RMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1_TX_PWM_DIVGEAR3A_BMSK                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1_TX_PWM_DIVGEAR3A_SHFT                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1_ADDR                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000e4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1_OFFS                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000e4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1_RMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1_TX_PWM_DIVGEAR4A_BMSK                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1_TX_PWM_DIVGEAR4A_SHFT                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VMODE_CTRL1_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000e8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VMODE_CTRL1_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000e8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VMODE_CTRL1_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VMODE_CTRL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VMODE_CTRL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VMODE_CTRL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VMODE_CTRL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VMODE_CTRL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VMODE_CTRL1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VMODE_CTRL1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VMODE_CTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VMODE_CTRL1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VMODE_CTRL1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VMODE_CTRL1_VMODE_CTRL1_BMSK                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VMODE_CTRL1_VMODE_CTRL1_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_CTRL_1_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000ec)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_CTRL_1_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000ec)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_CTRL_1_RMSK                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_CTRL_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_CTRL_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_CTRL_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_CTRL_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_CTRL_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_CTRL_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_CTRL_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_CTRL_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_CTRL_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_CTRL_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_CTRL_1_ALOG_OBSV_BUS_CTRL_1_SEL_BMSK                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_CTRL_1_ALOG_OBSV_BUS_CTRL_1_SEL_SHFT                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_STATUS_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000f0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_STATUS_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000f0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_STATUS_RMSK                                                     0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_STATUS_BIST_STATUS_RO_BMSK                                      0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_STATUS_BIST_STATUS_RO_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT1_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000f4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT1_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000f4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT1_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT1_BIST_ERROR_COUNT1_STATUS_BMSK                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT1_BIST_ERROR_COUNT1_STATUS_SHFT                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT2_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000f8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT2_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000f8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT2_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT2_BIST_ERROR_COUNT2_STATUS_BMSK                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_BIST_ERROR_COUNT2_BIST_ERROR_COUNT2_STATUS_SHFT                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_STATUS_1_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x000000fc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_STATUS_1_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x000000fc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_STATUS_1_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_STATUS_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_STATUS_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_STATUS_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_STATUS_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_STATUS_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_STATUS_1_ALOG_OBSV_BUS_STATUS_1_BMSK                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_ALOG_OBSV_BUS_STATUS_1_ALOG_OBSV_BUS_STATUS_1_SHFT                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000100)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000100)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_RMSK                                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_RSVD_BMSK                                           0xfe
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_RSVD_SHFT                                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_LANE_PWRDN_B_BMSK                                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_LANE_DIG_CONFIG_LANE_PWRDN_B_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PI_QEC_CTRL_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000104)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PI_QEC_CTRL_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000104)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PI_QEC_CTRL_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PI_QEC_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PI_QEC_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PI_QEC_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PI_QEC_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PI_QEC_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PI_QEC_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PI_QEC_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PI_QEC_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PI_QEC_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PI_QEC_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PI_QEC_CTRL_PI_QEC_CTRL_BMSK                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PI_QEC_CTRL_PI_QEC_CTRL_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000108)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000108)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_RMSK                                                       0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_PREEMPH_VAL_MUX_BMSK                                       0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_PREEMPH_VAL_MUX_SHFT                                        0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_PREEMPH_BMSK                                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_PRE_EMPH_PREEMPH_SHFT                                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SW_RESET_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x0000010c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SW_RESET_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000010c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SW_RESET_RMSK                                                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SW_RESET_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SW_RESET_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SW_RESET_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SW_RESET_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SW_RESET_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SW_RESET_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SW_RESET_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SW_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SW_RESET_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SW_RESET_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SW_RESET_SW_RESET_BMSK                                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_SW_RESET_SW_RESET_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DIG_BKUP_CTRL_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000110)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DIG_BKUP_CTRL_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000110)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DIG_BKUP_CTRL_RMSK                                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DIG_BKUP_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DIG_BKUP_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DIG_BKUP_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DIG_BKUP_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DIG_BKUP_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DIG_BKUP_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DIG_BKUP_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DIG_BKUP_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DIG_BKUP_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DIG_BKUP_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DIG_BKUP_CTRL_RSVD_BMSK                                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DIG_BKUP_CTRL_RSVD_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS0_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000114)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS0_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000114)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS0_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS0_DEBUG_BUS_7_0_BMSK                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS0_DEBUG_BUS_7_0_SHFT                                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS1_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000118)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS1_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000118)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS1_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS1_DEBUG_BUS_15_8_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS1_DEBUG_BUS_15_8_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS2_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x0000011c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS2_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000011c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS2_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS2_DEBUG_BUS_23_16_BMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS2_DEBUG_BUS_23_16_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS3_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000120)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS3_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000120)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS3_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS3_DEBUG_BUS_31_24_BMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DEBUG_BUS3_DEBUG_BUS_31_24_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_EQCODE_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000124)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_EQCODE_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000124)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_EQCODE_RMSK                                                     0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_EQCODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_EQCODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_EQCODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_EQCODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_EQCODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_EQCODE_READ_EQCODE_STATUS_BMSK                                  0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_EQCODE_READ_EQCODE_STATUS_SHFT                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_OFFSETCODE_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000128)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_OFFSETCODE_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000128)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_OFFSETCODE_RMSK                                                0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_OFFSETCODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_OFFSETCODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_OFFSETCODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_OFFSETCODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_OFFSETCODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_OFFSETCODE_READ_OFFSETCODE_STATUS_BMSK                         0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_READ_OFFSETCODE_READ_OFFSETCODE_STATUS_SHFT                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_LOW_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x0000012c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_LOW_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000012c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_LOW_RMSK                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_LOW_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_LOW_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_LOW_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_LOW_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_LOW_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_LOW_IACOMPARE_COUNT_LOW_BMSK                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_LOW_IACOMPARE_COUNT_LOW_SHFT                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_HIGH_ADDR                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000130)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_HIGH_OFFS                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000130)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_HIGH_RMSK                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_HIGH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_HIGH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_HIGH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_HIGH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_HIGH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_HIGH_IACOMPARE_COUNT_HIGH_BMSK                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IA_ERROR_COUNTER_HIGH_IACOMPARE_COUNT_HIGH_SHFT                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VGA_READ_CODE_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000134)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VGA_READ_CODE_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000134)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VGA_READ_CODE_RMSK                                                   0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VGA_READ_CODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VGA_READ_CODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VGA_READ_CODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VGA_READ_CODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VGA_READ_CODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VGA_READ_CODE_READ_VGACODE_BMSK                                      0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VGA_READ_CODE_READ_VGACODE_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VTH_READ_CODE_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000138)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VTH_READ_CODE_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000138)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VTH_READ_CODE_RMSK                                                  0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VTH_READ_CODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VTH_READ_CODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VTH_READ_CODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VTH_READ_CODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VTH_READ_CODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VTH_READ_CODE_VTH_CODE_DEBUG_BMSK                                   0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_VTH_READ_CODE_VTH_CODE_DEBUG_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP1_READ_CODE_ADDR                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x0000013c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP1_READ_CODE_OFFS                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000013c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP1_READ_CODE_RMSK                                              0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP1_READ_CODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP1_READ_CODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP1_READ_CODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP1_READ_CODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP1_READ_CODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP1_READ_CODE_READ_TAP1CODE_BMSK                                0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP1_READ_CODE_READ_TAP1CODE_SHFT                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP2_READ_CODE_ADDR                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000140)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP2_READ_CODE_OFFS                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000140)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP2_READ_CODE_RMSK                                             0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP2_READ_CODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP2_READ_CODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP2_READ_CODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP2_READ_CODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP2_READ_CODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP2_READ_CODE_READ_TAP2CODE_BMSK                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DFE_TAP2_READ_CODE_READ_TAP2CODE_SHFT                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_I_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000144)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_I_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000144)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_I_RMSK                                                  0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_I_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_I_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_I_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_I_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_I_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_I_IDAC_I_STATUS_BMSK                                    0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_I_IDAC_I_STATUS_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_IBAR_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000148)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_IBAR_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000148)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_IBAR_RMSK                                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_IBAR_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_IBAR_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_IBAR_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_IBAR_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_IBAR_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_IBAR_IDAC_IB_STATUS_BMSK                                0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_IBAR_IDAC_IB_STATUS_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_Q_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x0000014c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_Q_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000014c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_Q_RMSK                                                  0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_Q_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_Q_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_Q_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_Q_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_Q_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_Q_IDAC_Q_STATUS_BMSK                                    0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_Q_IDAC_Q_STATUS_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_QBAR_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000150)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_QBAR_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000150)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_QBAR_RMSK                                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_QBAR_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_QBAR_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_QBAR_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_QBAR_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_QBAR_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_QBAR_IDAC_QB_STATUS_BMSK                                0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_QBAR_IDAC_QB_STATUS_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_A_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000154)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_A_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000154)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_A_RMSK                                                  0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_A_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_A_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_A_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_A_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_A_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_A_IDAC_A_STATUS_BMSK                                    0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_A_IDAC_A_STATUS_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_ABAR_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000158)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_ABAR_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000158)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_ABAR_RMSK                                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_ABAR_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_ABAR_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_ABAR_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_ABAR_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_ABAR_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_ABAR_IDAC_AB_STATUS_BMSK                                0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_ABAR_IDAC_AB_STATUS_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SM_ON_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x0000015c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SM_ON_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x0000015c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SM_ON_RMSK                                              0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SM_ON_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SM_ON_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SM_ON_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SM_ON_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SM_ON_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SM_ON_IDAC_CAL_DONE_STATUS_BMSK                         0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SM_ON_IDAC_CAL_DONE_STATUS_SHFT                          0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SM_ON_IDAC_CAL_ON_STATUS_BMSK                            0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SM_ON_IDAC_CAL_ON_STATUS_SHFT                            0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SM_ON_IDAC_SM_STATUS_BMSK                                0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SM_ON_IDAC_SM_STATUS_SHFT                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000160)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000160)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_RMSK                                           0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_AB_BMSK                          0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_AB_SHFT                           0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_A_BMSK                           0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_A_SHFT                            0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_QB_BMSK                           0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_QB_SHFT                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_Q_BMSK                            0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_Q_SHFT                            0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_IB_BMSK                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_IB_SHFT                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_I_BMSK                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE_IDAC_CAL_DONE_I_SHFT                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_ADDR                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000164)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_OFFS                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000164)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_RMSK                                          0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_AB_BMSK                      0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_AB_SHFT                       0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_A_BMSK                       0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_A_SHFT                        0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_QB_BMSK                       0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_QB_SHFT                       0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_Q_BMSK                        0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_Q_SHFT                        0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_IB_BMSK                       0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_IB_SHFT                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_I_BMSK                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR_SIGNERROR_STATUS_I_SHFT                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DCC_CAL_STATUS_ADDR                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE      + 0x00000168)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DCC_CAL_STATUS_OFFS                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX_REG_BASE_OFFS + 0x00000168)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DCC_CAL_STATUS_RMSK                                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DCC_CAL_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DCC_CAL_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DCC_CAL_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DCC_CAL_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DCC_CAL_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DCC_CAL_STATUS_DCC_CAL_EN_STATUS_BMSK                               0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DCC_CAL_STATUS_DCC_CAL_EN_STATUS_SHFT                                0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DCC_CAL_STATUS_DCC_CAL_DONE_STATUS_BMSK                             0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DCC_CAL_STATUS_DCC_CAL_DONE_STATUS_SHFT                              0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DCC_CAL_STATUS_DCC_CAL_PTR_STATUS_BMSK                              0x3c
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DCC_CAL_STATUS_DCC_CAL_PTR_STATUS_SHFT                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DCC_CAL_STATUS_DCC_CAL_STATE_STATUS_BMSK                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_TX1_DCC_CAL_STATUS_DCC_CAL_STATE_STATUS_SHFT                             0x0

/*----------------------------------------------------------------------------
 * MODULE: AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX
 *--------------------------------------------------------------------------*/

#define AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE                                 (AHB2PHY_SOUTH_AHB2PHY_SOUTH_BASE      + 0x0000a800)
#define AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS                            0x0000a800

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_HALF_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000000)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_HALF_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000000)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_HALF_RMSK                                                  0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_HALF_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_HALF_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_HALF_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_HALF_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_HALF_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_HALF_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_HALF_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_HALF_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_HALF_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_HALF_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_HALF_UCDR_FO_GAIN_HALF_BMSK                                0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_HALF_UCDR_FO_GAIN_HALF_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_QUARTER_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000004)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_QUARTER_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000004)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_QUARTER_RMSK                                               0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_QUARTER_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_QUARTER_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_QUARTER_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_QUARTER_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_QUARTER_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_QUARTER_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_QUARTER_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_QUARTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_QUARTER_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_QUARTER_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_QUARTER_UCDR_FO_GAIN_QUARTER_BMSK                          0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_QUARTER_UCDR_FO_GAIN_QUARTER_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000008)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000008)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_RMSK                                                       0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_UCDR_FO_GAIN_BMSK                                          0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_GAIN_UCDR_FO_GAIN_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_HALF_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000000c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_HALF_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000000c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_HALF_RMSK                                                  0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_HALF_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_HALF_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_HALF_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_HALF_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_HALF_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_HALF_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_HALF_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_HALF_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_HALF_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_HALF_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_HALF_UCDR_SO_GAIN_HALF_BMSK                                0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_HALF_UCDR_SO_GAIN_HALF_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_QUARTER_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000010)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_QUARTER_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000010)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_QUARTER_RMSK                                               0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_QUARTER_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_QUARTER_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_QUARTER_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_QUARTER_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_QUARTER_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_QUARTER_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_QUARTER_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_QUARTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_QUARTER_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_QUARTER_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_QUARTER_UCDR_SO_GAIN_QUARTER_BMSK                          0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_QUARTER_UCDR_SO_GAIN_QUARTER_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000014)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000014)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_RMSK                                                       0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_UCDR_SO_GAIN_BMSK                                          0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_GAIN_UCDR_SO_GAIN_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_HALF_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000018)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_HALF_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000018)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_HALF_RMSK                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_HALF_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_HALF_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_HALF_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_HALF_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_HALF_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_HALF_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_HALF_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_HALF_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_HALF_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_HALF_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_HALF_UCDR_SVS_FO_GAIN_HALF_BMSK                        0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_HALF_UCDR_SVS_FO_GAIN_HALF_SHFT                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_QUARTER_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000001c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_QUARTER_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000001c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_QUARTER_RMSK                                           0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_QUARTER_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_QUARTER_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_QUARTER_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_QUARTER_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_QUARTER_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_QUARTER_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_QUARTER_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_QUARTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_QUARTER_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_QUARTER_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_QUARTER_UCDR_SVS_FO_GAIN_QUARTER_BMSK                  0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_QUARTER_UCDR_SVS_FO_GAIN_QUARTER_SHFT                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000020)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000020)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_RMSK                                                   0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_UCDR_SVS_FO_GAIN_BMSK                                  0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_UCDR_SVS_FO_GAIN_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000024)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000024)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF_RMSK                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF_UCDR_SVS_SO_GAIN_HALF_BMSK                        0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF_UCDR_SVS_SO_GAIN_HALF_SHFT                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000028)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000028)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER_RMSK                                           0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER_UCDR_SVS_SO_GAIN_QUARTER_BMSK                  0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER_UCDR_SVS_SO_GAIN_QUARTER_SHFT                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000002c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000002c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_RMSK                                                   0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_UCDR_SVS_SO_GAIN_BMSK                                  0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_UCDR_SVS_SO_GAIN_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000030)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000030)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_RMSK                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_UCDR_FASTLOCK_FO_GAIN_BMSK                        0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_UCDR_FASTLOCK_FO_GAIN_SHFT                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_ADDR                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000034)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_OFFS                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000034)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_RMSK                                      0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_UCDR_ENABLE_BMSK                          0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_UCDR_ENABLE_SHFT                           0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_UCDR_SO_SATURATION_BMSK                   0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE_UCDR_SO_SATURATION_SHFT                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_TO_SO_DELAY_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000038)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_TO_SO_DELAY_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000038)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_TO_SO_DELAY_RMSK                                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_TO_SO_DELAY_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_TO_SO_DELAY_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_TO_SO_DELAY_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_TO_SO_DELAY_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_TO_SO_DELAY_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_TO_SO_DELAY_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_TO_SO_DELAY_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_TO_SO_DELAY_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_TO_SO_DELAY_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_TO_SO_DELAY_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_TO_SO_DELAY_UCDR_FO_TO_SO_DELAY_BMSK                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FO_TO_SO_DELAY_UCDR_FO_TO_SO_DELAY_SHFT                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000003c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000003c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW_RMSK                                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW_UCDR_FASTLOCK_COUNTER_LOW_BMSK                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW_UCDR_FASTLOCK_COUNTER_LOW_SHFT                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000040)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000040)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_RMSK                                            0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_UCDR_FASTLOCK_COUNTER_HIGH_BMSK                 0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_UCDR_FASTLOCK_COUNTER_HIGH_SHFT                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000044)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000044)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_SB2_EN_BMSK                                            0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_SB2_EN_SHFT                                             0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_TRAN_CDRCLK_DIV6_SEL_10_BMSK                           0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_TRAN_CDRCLK_DIV6_SEL_10_SHFT                            0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_TRAN_CDRCLK_DIV6_SEL_01_BMSK                           0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_TRAN_CDRCLK_DIV6_SEL_01_SHFT                            0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_TRAN_CDRCLK_DIV6_SEL_00_BMSK                           0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_TRAN_CDRCLK_DIV6_SEL_00_SHFT                            0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_UCDR_BLOCK_STEP_BY_TWO_BMSK                             0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_UCDR_BLOCK_STEP_BY_TWO_SHFT                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_UCDR_STEP_BY_TWO_MUX_BMSK                               0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_UCDR_STEP_BY_TWO_MUX_SHFT                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_UCDR_STEP_BY_TWO_BMSK                                   0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_UCDR_STEP_BY_TWO_SHFT                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_UCDR_FASTLOCK_ENABLE_BMSK                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CONTROLS_UCDR_FASTLOCK_ENABLE_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000048)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000048)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_RMSK                                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_RXCLK_SWITCH_DIV_EN_BMSK                                  0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_RXCLK_SWITCH_DIV_EN_SHFT                                   0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_CDR_SB2_10_BMSK                                           0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_CDR_SB2_10_SHFT                                            0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_CDR_SB2_01_BMSK                                           0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_CDR_SB2_01_SHFT                                            0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_CDR_SB2_00_BMSK                                           0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_CDR_SB2_00_SHFT                                            0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_CDRCLK_DIV8_SB2_BMSK                                       0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_CDRCLK_DIV8_SB2_SHFT                                       0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_TRAN_CDRCLK_DIV8_SEL_10_BMSK                               0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_TRAN_CDRCLK_DIV8_SEL_10_SHFT                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_TRAN_CDRCLK_DIV8_SEL_01_BMSK                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_TRAN_CDRCLK_DIV8_SEL_01_SHFT                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_TRAN_CDRCLK_DIV8_SEL_00_BMSK                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_PI_CTRL2_TRAN_CDRCLK_DIV8_SEL_00_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH1_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000004c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH1_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000004c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH1_RMSK                                                   0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH1_DIV6PD_THRESH1_BMSK                                    0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH1_DIV6PD_THRESH1_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH2_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000050)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH2_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000050)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH2_RMSK                                                   0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH2_DIV6PD_THRESH2_BMSK                                    0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_THRESH2_DIV6PD_THRESH2_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN1_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000054)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN1_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000054)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN1_RMSK                                                     0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN1_DIV6PD_GAIN1_BMSK                                        0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN1_DIV6PD_GAIN1_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN2_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000058)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN2_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000058)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN2_RMSK                                                     0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN2_DIV6PD_GAIN2_BMSK                                        0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_UCDR_SB2_GAIN2_DIV6PD_GAIN2_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_CONTROL_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000005c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_CONTROL_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000005c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_CONTROL_RMSK                                                        0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_CONTROL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_CONTROL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_CONTROL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_CONTROL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_CONTROL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_CONTROL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_CONTROL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_CONTROL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_CONTROL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_CONTROL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_CONTROL_AUX_OFFSET_BMSK                                             0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_CONTROL_AUX_OFFSET_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_ADDR                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000060)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_OFFS                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000060)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_RMSK                                             0xf0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_AUXDATA_THRESH_FORCE_BMSK                        0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_AUXDATA_THRESH_FORCE_SHFT                         0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_AUXDATA_TCOARSE_BMSK                             0x70
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE_AUXDATA_TCOARSE_SHFT                              0x4

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000064)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000064)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_AUXDATA_EN_BMSK                                        0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_AUXDATA_EN_SHFT                                         0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_AUXDATA_EN_MUX_BMSK                                    0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_AUXDATA_EN_MUX_SHFT                                     0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_AUXCLK_EN_BMSK                                         0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_AUXCLK_EN_SHFT                                          0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_AUXCLK_EN_MUX_BMSK                                     0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_AUXCLK_EN_MUX_SHFT                                      0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_IACOMPARE_CLEAR_BMSK                                    0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_IACOMPARE_CLEAR_SHFT                                    0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_IACOMPARE_ENABLE_BMSK                                   0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_IACOMPARE_ENABLE_SHFT                                   0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_AUXDATA_SEL_BMSK                                        0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_AUXDATA_SEL_SHFT                                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_RCLK_SEL_BMSK                                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RCLK_AUXDATA_SEL_RCLK_SEL_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_ENABLE_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000068)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_ENABLE_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000068)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_ENABLE_RMSK                                                      0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_ENABLE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_ENABLE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_ENABLE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_ENABLE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_ENABLE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_ENABLE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_ENABLE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_ENABLE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_ENABLE_AC_JTAG_EN_BMSK                                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_ENABLE_AC_JTAG_EN_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000006c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000006c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_RMSK                                                       0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_AC_JTAG_INITP_MUX_BMSK                                     0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_AC_JTAG_INITP_MUX_SHFT                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_AC_JTAG_INITP_BMSK                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITP_AC_JTAG_INITP_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000070)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000070)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_RMSK                                                       0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_AC_JTAG_INITN_MUX_BMSK                                     0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_AC_JTAG_INITN_MUX_SHFT                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_AC_JTAG_INITN_BMSK                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_INITN_AC_JTAG_INITN_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_LVL_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000074)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_LVL_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000074)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_LVL_RMSK                                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_LVL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_LVL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_LVL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_LVL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_LVL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_LVL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_LVL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_LVL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_LVL_AC_JTAG_LVL_BMSK                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_LVL_AC_JTAG_LVL_SHFT                                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_MODE_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000078)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_MODE_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000078)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_MODE_RMSK                                                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_MODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_MODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_MODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_MODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_MODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_MODE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_MODE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_MODE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_MODE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_MODE_AC_JTAG_MODE_BMSK                                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_MODE_AC_JTAG_MODE_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_RESET_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000007c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_RESET_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000007c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_RESET_RMSK                                                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_RESET_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_RESET_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_RESET_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_RESET_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_RESET_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_RESET_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_RESET_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_RESET_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_RESET_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_RESET_AC_JTAG_RESET_BMSK                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_RESET_AC_JTAG_RESET_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000080)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000080)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_RMSK                                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_RX_TERM_BW_BAND3_BMSK                                        0xc0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_RX_TERM_BW_BAND3_SHFT                                         0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_RX_TERM_BW_BAND2_BMSK                                        0x30
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_RX_TERM_BW_BAND2_SHFT                                         0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_RX_TERM_BW_BAND1_BMSK                                         0xc
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_RX_TERM_BW_BAND1_SHFT                                         0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_RX_TERM_BW_BAND0_BMSK                                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_BW_RX_TERM_BW_BAND0_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000084)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000084)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_RMSK                                                      0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_RX_POL_INV_BMSK                                           0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_RX_POL_INV_SHFT                                            0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_RX_Q_EN_MUX_BMSK                                          0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_RX_Q_EN_MUX_SHFT                                           0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_RX_Q_EN_BMSK                                              0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_RX_Q_EN_SHFT                                               0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_RX_I_EN_MUX_BMSK                                           0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_RX_I_EN_MUX_SHFT                                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_RX_I_EN_BMSK                                               0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_RX_I_EN_SHFT                                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_RCVR_EN_MUX_BMSK                                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_RCVR_EN_MUX_SHFT                                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_RCVR_EN_BMSK                                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_RCVR_IQ_EN_RCVR_EN_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_I_DC_OFFSETS_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000088)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_I_DC_OFFSETS_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000088)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_I_DC_OFFSETS_RMSK                                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_I_DC_OFFSETS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_I_DC_OFFSETS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_I_DC_OFFSETS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_I_DC_OFFSETS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_I_DC_OFFSETS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_I_DC_OFFSETS_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_I_DC_OFFSETS_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_I_DC_OFFSETS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_I_DC_OFFSETS_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_I_DC_OFFSETS_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_I_DC_OFFSETS_IDAC_I_BMSK                                        0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_I_DC_OFFSETS_IDAC_I_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_IBAR_DC_OFFSETS_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000008c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_IBAR_DC_OFFSETS_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000008c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_IBAR_DC_OFFSETS_RMSK                                            0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_IBAR_DC_OFFSETS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_IBAR_DC_OFFSETS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_IBAR_DC_OFFSETS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_IBAR_DC_OFFSETS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_IBAR_DC_OFFSETS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_IBAR_DC_OFFSETS_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_IBAR_DC_OFFSETS_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_IBAR_DC_OFFSETS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_IBAR_DC_OFFSETS_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_IBAR_DC_OFFSETS_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_IBAR_DC_OFFSETS_IDAC_IB_BMSK                                    0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_IBAR_DC_OFFSETS_IDAC_IB_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_Q_DC_OFFSETS_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000090)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_Q_DC_OFFSETS_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000090)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_Q_DC_OFFSETS_RMSK                                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_Q_DC_OFFSETS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_Q_DC_OFFSETS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_Q_DC_OFFSETS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_Q_DC_OFFSETS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_Q_DC_OFFSETS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_Q_DC_OFFSETS_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_Q_DC_OFFSETS_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_Q_DC_OFFSETS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_Q_DC_OFFSETS_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_Q_DC_OFFSETS_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_Q_DC_OFFSETS_IDAC_Q_BMSK                                        0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_Q_DC_OFFSETS_IDAC_Q_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_QBAR_DC_OFFSETS_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000094)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_QBAR_DC_OFFSETS_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000094)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_QBAR_DC_OFFSETS_RMSK                                            0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_QBAR_DC_OFFSETS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_QBAR_DC_OFFSETS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_QBAR_DC_OFFSETS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_QBAR_DC_OFFSETS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_QBAR_DC_OFFSETS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_QBAR_DC_OFFSETS_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_QBAR_DC_OFFSETS_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_QBAR_DC_OFFSETS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_QBAR_DC_OFFSETS_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_QBAR_DC_OFFSETS_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_QBAR_DC_OFFSETS_IDAC_QB_BMSK                                    0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_QBAR_DC_OFFSETS_IDAC_QB_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_A_DC_OFFSETS_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000098)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_A_DC_OFFSETS_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000098)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_A_DC_OFFSETS_RMSK                                               0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_A_DC_OFFSETS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_A_DC_OFFSETS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_A_DC_OFFSETS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_A_DC_OFFSETS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_A_DC_OFFSETS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_A_DC_OFFSETS_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_A_DC_OFFSETS_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_A_DC_OFFSETS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_A_DC_OFFSETS_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_A_DC_OFFSETS_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_A_DC_OFFSETS_IDAC_A_BMSK                                        0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_A_DC_OFFSETS_IDAC_A_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ABAR_DC_OFFSETS_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000009c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ABAR_DC_OFFSETS_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000009c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ABAR_DC_OFFSETS_RMSK                                            0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ABAR_DC_OFFSETS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ABAR_DC_OFFSETS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ABAR_DC_OFFSETS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ABAR_DC_OFFSETS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ABAR_DC_OFFSETS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ABAR_DC_OFFSETS_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ABAR_DC_OFFSETS_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ABAR_DC_OFFSETS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ABAR_DC_OFFSETS_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ABAR_DC_OFFSETS_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ABAR_DC_OFFSETS_IDAC_AB_BMSK                                    0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ABAR_DC_OFFSETS_IDAC_AB_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_RMSK                                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_IDAC_ONE_BIT_DET_EN_BMSK                                     0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_IDAC_ONE_BIT_DET_EN_SHFT                                      0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_CORE_IDAC_FORCE_MASK_BMSK                                    0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_CORE_IDAC_FORCE_MASK_SHFT                                     0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_IDAC_MUX_BMSK                                                0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_IDAC_MUX_SHFT                                                 0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_IDAC_CAL_BYPASS_BMSK                                         0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_IDAC_CAL_BYPASS_SHFT                                          0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_IDAC_CAL_EN_MUX_BMSK                                          0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_IDAC_CAL_EN_MUX_SHFT                                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_IDAC_CAL_EN_BMSK                                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_IDAC_CAL_EN_SHFT                                              0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_CORE_RX_IDAC_CAL_EN_MUX_BMSK                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_CORE_RX_IDAC_CAL_EN_MUX_SHFT                                  0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_CORE_RX_IDAC_CAL_EN_BMSK                                      0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_EN_CORE_RX_IDAC_CAL_EN_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ENABLES_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ENABLES_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ENABLES_RMSK                                                    0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ENABLES_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ENABLES_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ENABLES_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ENABLES_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ENABLES_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ENABLES_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ENABLES_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ENABLES_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ENABLES_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ENABLES_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ENABLES_IDAC_ENABLE_BMSK                                        0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ENABLES_IDAC_ENABLE_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_SIGN_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_SIGN_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_SIGN_RMSK                                                       0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_SIGN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_SIGN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_SIGN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_SIGN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_SIGN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_SIGN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_SIGN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_SIGN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_SIGN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_SIGN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_SIGN_IDAC_SIGN_BMSK                                             0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_SIGN_IDAC_SIGN_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_RMSK                                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_RX_HIGHZ_MUX_BMSK                                      0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_RX_HIGHZ_MUX_SHFT                                      0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_RX_HIGHZ_BMSK                                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE_RX_HIGHZ_SHFT                                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_ADDR                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_OFFS                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RMSK                                 0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_AC_COUPLE_MUX_BMSK                0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_AC_COUPLE_MUX_SHFT                 0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_AC_COUPLE_BMSK                    0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_AC_COUPLE_SHFT                     0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_DC_COUPLE_MUX_BMSK                 0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_DC_COUPLE_MUX_SHFT                 0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_DC_COUPLE_BMSK                     0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_DC_COUPLE_SHFT                     0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_DC_OFFSET_MUX_BMSK                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_DC_OFFSET_MUX_SHFT                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_DC_OFFSET_BMSK                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET_RX_DC_OFFSET_SHFT                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_ADDR                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_OFFS                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_RMSK                                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_TAP1CODE_MAN_VAL_BMSK                                             0x78
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_TAP1CODE_MAN_VAL_SHFT                                              0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_KTAP1_BMSK                                                         0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_1_KTAP1_SHFT                                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_ADDR                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_OFFS                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_RMSK                                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_TAP2CODE_MAN_VAL_BMSK                                             0xf8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_TAP2CODE_MAN_VAL_SHFT                                              0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_KTAP2_BMSK                                                         0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_2_KTAP2_SHFT                                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_ADDR                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_OFFS                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_RMSK                                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_TAP2ADP_MODE_BMSK                                                 0xc0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_TAP2ADP_MODE_SHFT                                                  0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_TAP2ADP_EN_BMSK                                                   0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_TAP2ADP_EN_SHFT                                                    0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_TAP2ADP_FLIP_SIGN_BMSK                                            0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_TAP2ADP_FLIP_SIGN_SHFT                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_TAP1ADP_MODE_BMSK                                                  0xc
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_TAP1ADP_MODE_SHFT                                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_TAP1ADP_EN_BMSK                                                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_TAP1ADP_EN_SHFT                                                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_TAP1ADP_FLIP_SIGN_BMSK                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_3_TAP1ADP_FLIP_SIGN_SHFT                                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_ADDR                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000c0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_OFFS                                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000c0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_RMSK                                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_VTHADP_SEL_BMSK                                                   0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_VTHADP_SEL_SHFT                                                    0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_TX_ADPT_EN_MUX_BMSK                                               0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_TX_ADPT_EN_MUX_SHFT                                                0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_TX_ADPT_EN_BMSK                                                   0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_TX_ADPT_EN_SHFT                                                    0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_TAP2ADP_BYP_EN_MUX_BMSK                                            0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_TAP2ADP_BYP_EN_MUX_SHFT                                            0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_TAP2ADP_EN_MUX_BMSK                                                0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_TAP2ADP_EN_MUX_SHFT                                                0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_TAP1ADP_BYP_EN_MUX_BMSK                                            0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_TAP1ADP_BYP_EN_MUX_SHFT                                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_TAP1ADP_EN_MUX_BMSK                                                0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_4_TAP1ADP_EN_MUX_SHFT                                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH1_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000c4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH1_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000c4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH1_RMSK                                               0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH1_PRE_THRESH1_BMSK                                   0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH1_PRE_THRESH1_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH2_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000c8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH2_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000c8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH2_RMSK                                               0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH2_PRE_THRESH2_BMSK                                   0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH2_PRE_THRESH2_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000cc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000cc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_POST_THRESH2_BMSK                                  0xf0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_POST_THRESH2_SHFT                                   0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_POST_THRESH1_BMSK                                   0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_POST_THRESH_POST_THRESH1_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000d0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000d0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_MAIN_THRESH2_BMSK                                  0xf0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_MAIN_THRESH2_SHFT                                   0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_MAIN_THRESH1_BMSK                                   0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH_MAIN_THRESH1_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000d4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000d4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_VGA_UNROLL_BMSK                                          0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_VGA_UNROLL_SHFT                                           0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_VGAADP_MODE_BMSK                                         0x60
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_VGAADP_MODE_SHFT                                          0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_VGAADP_EN_BMSK                                           0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_VGAADP_EN_SHFT                                            0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_VGAADP_FLIP_SIGN_BMSK                                     0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_VGAADP_FLIP_SIGN_SHFT                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_KVGA_BMSK                                                 0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL1_KVGA_SHFT                                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000d8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000d8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_VTH_CAL_KVGA_BMSK                                        0xc0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_VTH_CAL_KVGA_SHFT                                         0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_VGAADP_BYP_EN_MUX_BMSK                                   0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_VGAADP_BYP_EN_MUX_SHFT                                    0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_VGAADP_EN_MUX_BMSK                                       0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_VGAADP_EN_MUX_SHFT                                        0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_VGACODE_MAN_VAL_BMSK                                      0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VGA_CAL_CNTRL2_VGACODE_MAN_VAL_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_ADDR                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000dc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_OFFS                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000dc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_RMSK                                                             0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_TRAN_RCVR_GMCAL_RES_BMSK                                         0x1e
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_TRAN_RCVR_GMCAL_RES_SHFT                                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_TRAN_RX_GMCAL_EN_BMSK                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_GM_CAL_TRAN_RX_GMCAL_EN_SHFT                                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_LSB_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000e0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_LSB_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000e0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_LSB_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_LSB_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_LSB_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_LSB_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_LSB_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_LSB_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_LSB_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_LSB_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_LSB_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_LSB_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_LSB_RX_VGA_GAIN2_LSB_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_LSB_RX_VGA_GAIN2_LSB_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_MSB_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000e4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_MSB_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000e4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_MSB_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_MSB_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_MSB_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_MSB_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_MSB_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_MSB_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_MSB_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_MSB_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_MSB_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_MSB_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_MSB_RX_VGA_GAIN2_MSB_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_VGA_GAIN2_MSB_RX_VGA_GAIN2_MSB_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000e8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000e8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_RMSK                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_EQDEGCAP_LOW_SPEED_BMSK                           0x78
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_EQDEGCAP_LOW_SPEED_SHFT                            0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_OFFSETADP_MODE_MUX_BMSK                            0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_OFFSETADP_MODE_MUX_SHFT                            0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_DES_EDGE_EN_MUX_BMSK                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_DES_EDGE_EN_MUX_SHFT                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_DES_EDGE_EN_BMSK                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1_DES_EDGE_EN_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000ec)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000ec)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_RMSK                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_EQADP_EN_MUX_BMSK                                 0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_EQADP_EN_MUX_SHFT                                  0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_EQADP_EN_BMSK                                     0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_EQADP_EN_SHFT                                      0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_VGA_GAIN2_MUX_BMSK                                0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_VGA_GAIN2_MUX_SHFT                                 0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_EQDEGCAP_BMSK                                      0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2_EQDEGCAP_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000f0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000f0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_RMSK                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_KEQ_BMSK                                          0x70
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_KEQ_SHFT                                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_EQADP_FLIP_SIGN_BMSK                               0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_EQADP_FLIP_SIGN_SHFT                               0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_EQADP_BYPASS_OFF_BMSK                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_EQADP_BYPASS_OFF_SHFT                              0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_EQADP_MODE_BMSK                                    0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3_EQADP_MODE_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000f4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000f4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_RMSK                                              0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_EQ_FORCE_EN_MUX_BMSK                              0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_EQ_FORCE_EN_MUX_SHFT                               0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_EQ_FORCE_EN_BMSK                                  0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_EQ_FORCE_EN_SHFT                                   0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_RSVD_BMSK                                         0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_RSVD_SHFT                                          0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_EQCODE_MAN_VAL_BMSK                                0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4_EQCODE_MAN_VAL_SHFT                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_LOW_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000f8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_LOW_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000f8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_LOW_RMSK                                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_LOW_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_LOW_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_LOW_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_LOW_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_LOW_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_LOW_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_LOW_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_LOW_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_LOW_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_LOW_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_LOW_TSETTLE_LOW_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_LOW_TSETTLE_LOW_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_HIGH_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000000fc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_HIGH_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000000fc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_HIGH_RMSK                                                0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_HIGH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_HIGH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_HIGH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_HIGH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_HIGH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_HIGH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_HIGH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_HIGH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_HIGH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_HIGH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_HIGH_TSETTLE_HIGH_BMSK                                   0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_TSETTLE_HIGH_TSETTLE_HIGH_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_MEASURE_TIME_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000100)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_MEASURE_TIME_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000100)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_MEASURE_TIME_RMSK                                               0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_MEASURE_TIME_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_MEASURE_TIME_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_MEASURE_TIME_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_MEASURE_TIME_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_MEASURE_TIME_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_MEASURE_TIME_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_MEASURE_TIME_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_MEASURE_TIME_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_MEASURE_TIME_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_MEASURE_TIME_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_MEASURE_TIME_IDAC_MEASURE_TIME_BMSK                             0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_MEASURE_TIME_IDAC_MEASURE_TIME_SHFT                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000104)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000104)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_RMSK                                                0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_IDAC_SKIP_ACCUM_BMSK                                0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_IDAC_SKIP_ACCUM_SHFT                                 0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_IDAC_ACCUM_SAT_VALUE_BMSK                           0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR_IDAC_ACCUM_SAT_VALUE_SHFT                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_LSB_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000108)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_LSB_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000108)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_LSB_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_LSB_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_LSB_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_LSB_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_LSB_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_LSB_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_LSB_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_LSB_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_LSB_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_LSB_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_LSB_RX_EQ_OFFSET_LSB_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_LSB_RX_EQ_OFFSET_LSB_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_MSB_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000010c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_MSB_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000010c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_MSB_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_MSB_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_MSB_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_MSB_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_MSB_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_MSB_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_MSB_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_MSB_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_MSB_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_MSB_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_MSB_RX_EQ_OFFSET_MSB_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_MSB_RX_EQ_OFFSET_MSB_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_ADDR                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000110)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFS                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000110)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_RMSK                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_RX_EQ_OFFSET_MUX_BMSK                       0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_RX_EQ_OFFSET_MUX_SHFT                        0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_KOFFSET_BMSK                                0x70
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_KOFFSET_SHFT                                 0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFSETADP_FLIP_SIGN_BMSK                     0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFSETADP_FLIP_SIGN_SHFT                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFSETADP_MODE_BMSK                          0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFSETADP_MODE_SHFT                          0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFSETADP_EN_MUX_BMSK                        0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFSETADP_EN_MUX_SHFT                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFSETADP_EN_BMSK                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1_OFFSETADP_EN_SHFT                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000114)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000114)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2_RMSK                                           0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2_OFFSETCODE_MAN_VAL_BMSK                        0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2_OFFSETCODE_MAN_VAL_SHFT                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000118)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000118)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_CORE_RX_SIGDET_MUX_BMSK                                  0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_CORE_RX_SIGDET_MUX_SHFT                                   0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_CORE_RX_SIGDET_BMSK                                      0x60
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_CORE_RX_SIGDET_SHFT                                       0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_SIGDET_FLT_BYP_BMSK                                      0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_SIGDET_FLT_BYP_SHFT                                       0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_SIGDET_LP_EN_MUX_BMSK                                     0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_SIGDET_LP_EN_MUX_SHFT                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_SIGDET_LP_EN_BMSK                                         0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_SIGDET_LP_EN_SHFT                                         0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_SIGDET_EN_MUX_BMSK                                        0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_SIGDET_EN_MUX_SHFT                                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_SIGDET_EN_BMSK                                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_ENABLES_SIGDET_EN_SHFT                                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000011c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000011c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_RMSK                                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_SIGDET_CAP_CTRL_BMSK                                       0xf0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_SIGDET_CAP_CTRL_SHFT                                        0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_SIGDET_BW_CTRL_BMSK                                         0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_CNTRL_SIGDET_BW_CTRL_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000120)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000120)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_RMSK                                                         0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_SIGDET_UFS_MODE_BMSK                                         0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_SIGDET_UFS_MODE_SHFT                                          0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_SIGDET_LVL_MUX_BMSK                                          0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_SIGDET_LVL_MUX_SHFT                                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_SIGDET_LVL_BMSK                                               0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_LVL_SIGDET_LVL_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000124)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000124)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_RMSK                                              0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_SIGDET_DEGLITCH_CTRL_BMSK                         0x1e
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_SIGDET_DEGLITCH_CTRL_SHFT                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_SIGDET_DEGLITCH_BYP_BMSK                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL_SIGDET_DEGLITCH_BYP_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000128)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000128)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_RMSK                                                            0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_RX_MODE_BAND_COUPLED_BMSK                                       0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_RX_MODE_BAND_COUPLED_SHFT                                        0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_RX_BAND_UNMODIFIED_MUX_BMSK                                     0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_RX_BAND_UNMODIFIED_MUX_SHFT                                      0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_RX_BAND_10_HALF_BMSK                                            0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_RX_BAND_10_HALF_SHFT                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_RX_BAND_01_HALF_BMSK                                             0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_RX_BAND_01_HALF_SHFT                                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_RX_BAND_MUX_BMSK                                                 0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_RX_BAND_MUX_SHFT                                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_RX_BAND_BMSK                                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_BAND_RX_BAND_SHFT                                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000012c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000012c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_RMSK                                                    0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_CDR_DN_BMSK                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_CDR_DN_SHFT                                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_CDR_UP_BMSK                                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_CDR_UP_SHFT                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_CDR_FREEZE_BMSK                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_FREEZE_UP_DN_CDR_FREEZE_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_ADDR                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000130)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_OFFS                                           (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000130)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_RMSK                                                  0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_CDR_RESET_OVERRIDE_MUX_BMSK                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_CDR_RESET_OVERRIDE_MUX_SHFT                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_CDR_RESET_OVERRIDE_BMSK                               0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_CDR_RESET_OVERRIDE_CDR_RESET_OVERRIDE_SHFT                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_ADDR                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000134)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_OFFS                                            (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000134)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_RMSK                                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_SVS_MODE_MUX_BMSK                                     0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_SVS_MODE_MUX_SHFT                                      0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_SVS_MODE_BMSK                                         0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_SVS_MODE_SHFT                                          0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_RX_CLOCK_EDGE_BMSK                                    0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_RX_CLOCK_EDGE_SHFT                                     0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_RXCLK_HS_SWITCH_FORCE_DISABLE_BMSK                    0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_RXCLK_HS_SWITCH_FORCE_DISABLE_SHFT                     0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_RXCLK_HS_SWITCH_MUX_BMSK                               0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_RXCLK_HS_SWITCH_MUX_SHFT                               0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_RXCLK_HS_SWITCH_BMSK                                   0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_RXCLK_HS_SWITCH_SHFT                                   0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_IDATA_MARKER_FLIP_BMSK                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_IDATA_MARKER_FLIP_SHFT                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_QUARTER_RATE_EDGE_ON_FIVE_ONE_BMSK                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_INTERFACE_MODE_QUARTER_RATE_EDGE_ON_FIVE_ONE_SHFT                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_JITTER_GEN_MODE_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000138)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_JITTER_GEN_MODE_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000138)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_JITTER_GEN_MODE_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_JITTER_GEN_MODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_JITTER_GEN_MODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_JITTER_GEN_MODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_JITTER_GEN_MODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_JITTER_GEN_MODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_JITTER_GEN_MODE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_JITTER_GEN_MODE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_JITTER_GEN_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_JITTER_GEN_MODE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_JITTER_GEN_MODE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_JITTER_GEN_MODE_JITTERGENMODE_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_JITTER_GEN_MODE_JITTERGENMODE_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP1_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000013c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP1_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000013c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP1_RMSK                                                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP1_SJ_AMPLITUDE1_BMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP1_SJ_AMPLITUDE1_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP2_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000140)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP2_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000140)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP2_RMSK                                                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP2_SJ_AMPLITUDE2_BMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_AMP2_SJ_AMPLITUDE2_SHFT                                               0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER1_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000144)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER1_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000144)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER1_RMSK                                                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER1_SJ_PERIOD1_BMSK                                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER1_SJ_PERIOD1_SHFT                                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER2_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000148)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER2_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000148)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER2_RMSK                                                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER2_SJ_PERIOD2_BMSK                                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SJ_PER2_SJ_PERIOD2_SHFT                                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET1_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000014c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET1_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000014c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET1_RMSK                                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET1_PPMOFFSET1_BMSK                                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET1_PPMOFFSET1_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET2_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000150)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET2_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000150)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET2_RMSK                                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET2_PPMOFFSET2_BMSK                                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PPM_OFFSET2_PPMOFFSET2_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD1_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000154)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD1_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000154)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD1_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD1_SIGN_PPM_PERIOD1_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD1_SIGN_PPM_PERIOD1_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD2_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000158)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD2_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000158)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD2_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD2_SIGN_PPM_PERIOD2_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_SIGN_PPM_PERIOD2_SIGN_PPM_PERIOD2_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_ADDR                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000015c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_OFFS                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000015c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_RMSK                                             0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_RX_PWM_GEAR_MUX_BMSK                             0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_RX_PWM_GEAR_MUX_SHFT                              0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_RX_PWM_GEAR_BMSK                                 0x1c
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_RX_PWM_GEAR_SHFT                                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_RX_PWM_EN_MUX_BMSK                                0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_RX_PWM_EN_MUX_SHFT                                0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_RX_PWM_EN_BMSK                                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_ENABLE_AND_DATA_RX_PWM_EN_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR1_TIMEOUT_COUNT_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000160)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR1_TIMEOUT_COUNT_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000160)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR1_TIMEOUT_COUNT_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR1_TIMEOUT_COUNT_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR1_TIMEOUT_COUNT_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR1_TIMEOUT_COUNT_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR1_TIMEOUT_COUNT_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR1_TIMEOUT_COUNT_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR1_TIMEOUT_COUNT_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR1_TIMEOUT_COUNT_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR1_TIMEOUT_COUNT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR1_TIMEOUT_COUNT_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR1_TIMEOUT_COUNT_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR1_TIMEOUT_COUNT_RX_PWM_GEAR1_COUNT_BMSK                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR1_TIMEOUT_COUNT_RX_PWM_GEAR1_COUNT_SHFT                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR2_TIMEOUT_COUNT_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000164)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR2_TIMEOUT_COUNT_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000164)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR2_TIMEOUT_COUNT_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR2_TIMEOUT_COUNT_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR2_TIMEOUT_COUNT_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR2_TIMEOUT_COUNT_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR2_TIMEOUT_COUNT_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR2_TIMEOUT_COUNT_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR2_TIMEOUT_COUNT_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR2_TIMEOUT_COUNT_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR2_TIMEOUT_COUNT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR2_TIMEOUT_COUNT_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR2_TIMEOUT_COUNT_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR2_TIMEOUT_COUNT_RX_PWM_GEAR2_COUNT_BMSK                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR2_TIMEOUT_COUNT_RX_PWM_GEAR2_COUNT_SHFT                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR3_TIMEOUT_COUNT_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000168)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR3_TIMEOUT_COUNT_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000168)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR3_TIMEOUT_COUNT_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR3_TIMEOUT_COUNT_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR3_TIMEOUT_COUNT_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR3_TIMEOUT_COUNT_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR3_TIMEOUT_COUNT_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR3_TIMEOUT_COUNT_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR3_TIMEOUT_COUNT_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR3_TIMEOUT_COUNT_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR3_TIMEOUT_COUNT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR3_TIMEOUT_COUNT_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR3_TIMEOUT_COUNT_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR3_TIMEOUT_COUNT_RX_PWM_GEAR3_COUNT_BMSK                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR3_TIMEOUT_COUNT_RX_PWM_GEAR3_COUNT_SHFT                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR4_TIMEOUT_COUNT_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000016c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR4_TIMEOUT_COUNT_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000016c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR4_TIMEOUT_COUNT_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR4_TIMEOUT_COUNT_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR4_TIMEOUT_COUNT_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR4_TIMEOUT_COUNT_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR4_TIMEOUT_COUNT_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR4_TIMEOUT_COUNT_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR4_TIMEOUT_COUNT_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR4_TIMEOUT_COUNT_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR4_TIMEOUT_COUNT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR4_TIMEOUT_COUNT_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR4_TIMEOUT_COUNT_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR4_TIMEOUT_COUNT_RX_PWM_GEAR4_COUNT_BMSK                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_PWM_GEAR4_TIMEOUT_COUNT_RX_PWM_GEAR4_COUNT_SHFT                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_LOW_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000170)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_LOW_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000170)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_LOW_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_LOW_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_LOW_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_LOW_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_LOW_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_LOW_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_LOW_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_LOW_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_LOW_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_LOW_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_LOW_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_LOW_RX_MODE_00_7_0_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_LOW_RX_MODE_00_7_0_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000174)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000174)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH_RX_MODE_00_15_8_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH_RX_MODE_00_15_8_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH2_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000178)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH2_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000178)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH2_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH2_RX_MODE_00_23_16_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH2_RX_MODE_00_23_16_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH3_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000017c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH3_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000017c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH3_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH3_RX_MODE_00_31_24_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH3_RX_MODE_00_31_24_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH4_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000180)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH4_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000180)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH4_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH4_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH4_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH4_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH4_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH4_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH4_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH4_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH4_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH4_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH4_RX_MODE_00_39_32_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_00_HIGH4_RX_MODE_00_39_32_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_LOW_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000184)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_LOW_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000184)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_LOW_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_LOW_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_LOW_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_LOW_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_LOW_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_LOW_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_LOW_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_LOW_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_LOW_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_LOW_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_LOW_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_LOW_RX_MODE_01_7_0_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_LOW_RX_MODE_01_7_0_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000188)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000188)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH_RX_MODE_01_15_8_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH_RX_MODE_01_15_8_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH2_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000018c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH2_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000018c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH2_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH2_RX_MODE_01_23_16_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH2_RX_MODE_01_23_16_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH3_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000190)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH3_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000190)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH3_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH3_RX_MODE_01_31_24_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH3_RX_MODE_01_31_24_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH4_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000194)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH4_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000194)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH4_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH4_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH4_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH4_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH4_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH4_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH4_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH4_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH4_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH4_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH4_RX_MODE_01_39_32_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_01_HIGH4_RX_MODE_01_39_32_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_LOW_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x00000198)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_LOW_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x00000198)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_LOW_RMSK                                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_LOW_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_LOW_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_LOW_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_LOW_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_LOW_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_LOW_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_LOW_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_LOW_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_LOW_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_LOW_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_LOW_RX_MODE_10_7_0_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_LOW_RX_MODE_10_7_0_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x0000019c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x0000019c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH_RX_MODE_10_15_8_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH_RX_MODE_10_15_8_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH2_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH2_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH2_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH2_RX_MODE_10_23_16_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH2_RX_MODE_10_23_16_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH3_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH3_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH3_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH3_RX_MODE_10_31_24_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH3_RX_MODE_10_31_24_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH4_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH4_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH4_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH4_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH4_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH4_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH4_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH4_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH4_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH4_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH4_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH4_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH4_RX_MODE_10_39_32_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_MODE_10_HIGH4_RX_MODE_10_39_32_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_RMSK                                                         0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_PHPRE_GAIN_SIGN_BMSK                                         0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_PHPRE_GAIN_SIGN_SHFT                                          0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_PHPRE_GAIN_BMSK                                              0x3c
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_PHPRE_GAIN_SHFT                                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_PHPRE_EN_MUX_BMSK                                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_PHPRE_EN_MUX_SHFT                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_PHPRE_EN_BMSK                                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_CTRL_PHPRE_EN_SHFT                                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_INITVAL_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_INITVAL_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_INITVAL_RMSK                                                      0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_INITVAL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_INITVAL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_INITVAL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_INITVAL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_INITVAL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_INITVAL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_INITVAL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_INITVAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_INITVAL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_INITVAL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_INITVAL_PHPRE_INITVAL_BMSK                                        0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PHPRE_INITVAL_PHPRE_INITVAL_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_EN_TIMER_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_EN_TIMER_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_EN_TIMER_RMSK                                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_EN_TIMER_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_EN_TIMER_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_EN_TIMER_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_EN_TIMER_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_EN_TIMER_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_EN_TIMER_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_EN_TIMER_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_EN_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_EN_TIMER_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_EN_TIMER_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_EN_TIMER_VGA_DFE_EN_TIMER_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_EN_TIMER_VGA_DFE_EN_TIMER_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_RMSK                                           0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_POST_CAL_CTLE_OFFSET_BMSK                      0x38
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_POST_CAL_CTLE_OFFSET_SHFT                       0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_POST_CAL_TAP1_OFFSET_BMSK                       0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET_POST_CAL_TAP1_OFFSET_SHFT                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_RX_DCC_CAL_ANA_EN_MUX_BMSK                                    0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_RX_DCC_CAL_ANA_EN_MUX_SHFT                                     0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_RX_DCC_CAL_ANA_EN_BMSK                                        0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_RX_DCC_CAL_ANA_EN_SHFT                                         0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_DCC_SETTLE_TIME_BMSK                                          0x30
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_DCC_SETTLE_TIME_SHFT                                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_DCC_MAG_POL_FLIP_BMSK                                          0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_DCC_MAG_POL_FLIP_SHFT                                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_DCC_SIGN_POL_FLIP_BMSK                                         0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_DCC_SIGN_POL_FLIP_SHFT                                         0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_RX_DCC_CAL_EN_MUX_BMSK                                         0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_RX_DCC_CAL_EN_MUX_SHFT                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_RX_DCC_CAL_EN_BMSK                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL1_RX_DCC_CAL_EN_SHFT                                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001c0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001c0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_RMSK                                                          0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_IDCC_CODE_MUX_BMSK                                            0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_IDCC_CODE_MUX_SHFT                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_IDCC_CODE_BMSK                                                 0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DCC_CTRL2_IDCC_CODE_SHFT                                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_CODE_ADDR                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001c4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_CODE_OFFS                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001c4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_CODE_RMSK                                                           0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_CODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_CODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_CODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_CODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_CODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_CODE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_CODE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_CODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_CODE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_CODE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_CODE_VTH_CODE_BMSK                                                  0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_CODE_VTH_CODE_SHFT                                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MIN_THRESH_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001c8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MIN_THRESH_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001c8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MIN_THRESH_RMSK                                                     0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MIN_THRESH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MIN_THRESH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MIN_THRESH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MIN_THRESH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MIN_THRESH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MIN_THRESH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MIN_THRESH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MIN_THRESH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MIN_THRESH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MIN_THRESH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MIN_THRESH_VTH_MIN_THRESH_BMSK                                      0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MIN_THRESH_VTH_MIN_THRESH_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MAX_THRESH_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001cc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MAX_THRESH_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001cc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MAX_THRESH_RMSK                                                     0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MAX_THRESH_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MAX_THRESH_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MAX_THRESH_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MAX_THRESH_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MAX_THRESH_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MAX_THRESH_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MAX_THRESH_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MAX_THRESH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MAX_THRESH_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MAX_THRESH_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MAX_THRESH_VTH_MAX_THRESH_BMSK                                      0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_VTH_MAX_THRESH_VTH_MAX_THRESH_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_CTRL_1_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001d0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_CTRL_1_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001d0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_CTRL_1_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_CTRL_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_CTRL_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_CTRL_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_CTRL_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_CTRL_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_CTRL_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_CTRL_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_CTRL_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_CTRL_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_CTRL_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_CTRL_1_ALOG_OBSV_BUS_CTRL_1_SEL_BMSK                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_CTRL_1_ALOG_OBSV_BUS_CTRL_1_SEL_SHFT                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL1_ADDR                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001d4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL1_OFFS                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001d4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL1_RMSK                                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL1_PI_CTRL1_STATUS_BMSK                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL1_PI_CTRL1_STATUS_SHFT                                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL2_ADDR                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001d8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL2_OFFS                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001d8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL2_RMSK                                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL2_PI_CTRL2_STATUS_BMSK                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_CTRL2_PI_CTRL2_STATUS_SHFT                                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_QUAD_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001dc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_QUAD_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001dc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_QUAD_RMSK                                                             0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_QUAD_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_QUAD_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_QUAD_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_QUAD_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_QUAD_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_QUAD_PI_QUAD_STATUS_BMSK                                              0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_PI_QUAD_PI_QUAD_STATUS_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA1_ADDR                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001e0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA1_OFFS                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001e0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA1_RMSK                                                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA1_IDATA1_STATUS_BMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA1_IDATA1_STATUS_SHFT                                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA2_ADDR                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001e4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA2_OFFS                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001e4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA2_RMSK                                                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA2_IDATA2_STATUS_BMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_IDATA2_IDATA2_STATUS_SHFT                                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA1_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001e8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA1_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001e8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA1_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA1_AUXDATA1_STATUS_BMSK                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA1_AUXDATA1_STATUS_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA2_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001ec)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA2_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001ec)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA2_RMSK                                                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA2_AUXDATA2_STATUS_BMSK                                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AUX_DATA2_AUXDATA2_STATUS_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTP_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001f0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTP_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001f0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTP_RMSK                                                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTP_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTP_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTP_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTP_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTP_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTP_AC_JTAG_OUTP_STATUS_BMSK                                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTP_AC_JTAG_OUTP_STATUS_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTN_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001f4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTN_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001f4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTN_RMSK                                                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTN_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTN_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTN_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTN_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTN_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTN_AC_JTAG_OUTN_STATUS_BMSK                                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_AC_JTAG_OUTN_AC_JTAG_OUTN_STATUS_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_SIGDET_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001f8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_SIGDET_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001f8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_SIGDET_RMSK                                                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_SIGDET_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_SIGDET_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_SIGDET_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_SIGDET_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_SIGDET_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_SIGDET_RX_SIGDET_OUT_STATUS_BMSK                                      0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_RX_SIGDET_RX_SIGDET_OUT_STATUS_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_STATUS_1_ADDR                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE      + 0x000001fc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_STATUS_1_OFFS                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX_REG_BASE_OFFS + 0x000001fc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_STATUS_1_RMSK                                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_STATUS_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_STATUS_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_STATUS_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_STATUS_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_STATUS_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_STATUS_1_ALOG_OBSV_BUS_STATUS_1_BMSK                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_QSERDES_RX1_ALOG_OBSV_BUS_STATUS_1_ALOG_OBSV_BUS_STATUS_1_SHFT                       0x0

/*----------------------------------------------------------------------------
 * MODULE: AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY
 *--------------------------------------------------------------------------*/

#define AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE                                                         (AHB2PHY_SOUTH_AHB2PHY_SOUTH_BASE      + 0x0000aa00)
#define AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS                                                    0x0000aa00

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID0_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000000)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID0_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000000)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID0_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID0_STEP_7_0_BMSK                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID0_STEP_7_0_SHFT                                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID1_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000004)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID1_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000004)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID1_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID1_STEP_15_8_BMSK                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID1_STEP_15_8_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID2_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000008)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID2_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000008)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID2_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID2_MINOR_7_0_BMSK                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID2_MINOR_7_0_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID3_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000000c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID3_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000000c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID3_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID3_MAJOR_BMSK                                              0xf0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID3_MAJOR_SHFT                                               0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID3_MINOR_11_8_BMSK                                          0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_REVISION_ID3_MINOR_11_8_SHFT                                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_ADDR                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000010)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_OFFS                                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000010)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_RMSK                                                             0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_DP_CFG_SPARE_BMSK                                                0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_DP_CFG_SPARE_SHFT                                                 0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_AUX_RESET_BMSK                                                   0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_AUX_RESET_SHFT                                                    0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_CORE_RESET_TSYNC_BMSK                                            0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_CORE_RESET_TSYNC_SHFT                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_PLL_START_BMSK                                                    0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_PLL_START_SHFT                                                    0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_PLL_RESET_BMSK                                                    0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_PLL_RESET_SHFT                                                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_SW_RESET_BMSK                                                     0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_SW_RESET_SHFT                                                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_RETIMING_ENABLE_BMSK                                              0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_RETIMING_ENABLE_SHFT                                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_ADDR                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000014)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_OFFS                                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000014)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_RMSK                                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_C_READY_MUX_BMSK                                               0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_C_READY_MUX_SHFT                                                0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_SW_C_READY_BMSK                                                0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_SW_C_READY_SHFT                                                 0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_TCLK_LINKCLK_SEL_BMSK                                          0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_TCLK_LINKCLK_SEL_SHFT                                           0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_DISABLE_CGC_EN_BMSK                                            0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_DISABLE_CGC_EN_SHFT                                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_RT_BUFFER_LANE3_EN_BMSK                                         0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_RT_BUFFER_LANE3_EN_SHFT                                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_RT_BUFFER_LANE2_EN_BMSK                                         0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_RT_BUFFER_LANE2_EN_SHFT                                         0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_RT_BUFFER_LANE1_EN_BMSK                                         0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_RT_BUFFER_LANE1_EN_SHFT                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_RT_BUFFER_LANE0_EN_BMSK                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_CFG_1_RT_BUFFER_LANE0_EN_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000018)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000018)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_SPARE_PWRDN_B_BMSK                                            0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_SPARE_PWRDN_B_SHFT                                             0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_DP_CLAMP_EN_B_BMSK                                            0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_DP_CLAMP_EN_B_SHFT                                             0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_PLL_PWRDN_B_BMSK                                              0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_PLL_PWRDN_B_SHFT                                               0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_LANE_2_3_PWRDN_B_BMSK                                         0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_LANE_2_3_PWRDN_B_SHFT                                          0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_LANE_0_1_PWRDN_B_BMSK                                          0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_LANE_0_1_PWRDN_B_SHFT                                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_AUX_PWRDN_B_BMSK                                               0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_AUX_PWRDN_B_SHFT                                               0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_PSR_PWRDN_BMSK                                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_PSR_PWRDN_SHFT                                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_PWRDN_B_BMSK                                                   0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_PD_CTL_PWRDN_B_SHFT                                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_ADDR                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000001c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_OFFS                                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000001c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_RMSK                                                            0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_RETIME_BUFFER_SIZE_BMSK                                         0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_RETIME_BUFFER_SIZE_SHFT                                          0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_LINK_CLOCK_SEL_MUX_BMSK                                         0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_LINK_CLOCK_SEL_MUX_SHFT                                          0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_LINK_CLOCK_SEL_BMSK                                             0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_LINK_CLOCK_SEL_SHFT                                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_PAR_RATE_BMSK                                                    0xc
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_PAR_RATE_SHFT                                                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_TX_BAND_BMSK                                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MODE_TX_BAND_SHFT                                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000020)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000020)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_RMSK                                                         0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_AUX_FORCE_TX_EN_BMSK                                         0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_AUX_FORCE_TX_EN_SHFT                                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_AUX_BYPASS_BMSK                                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_AUX_BYPASS_SHFT                                              0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_RSVD_BMSK                                                    0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG0_RSVD_SHFT                                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG1_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000024)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG1_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000024)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG1_RMSK                                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG1_AUX_DCTRL_7_0_BMSK                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG1_AUX_DCTRL_7_0_SHFT                                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG2_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000028)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG2_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000028)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG2_RMSK                                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG2_AUX_DCTRL_15_8_BMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG2_AUX_DCTRL_15_8_SHFT                                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000002c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000002c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_RMSK                                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_AUX_FORCE_RX_EN_BMSK                                        0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_AUX_FORCE_RX_EN_SHFT                                         0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_AUX_TX_PRECHARGE_BMSK                                       0x70
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_AUX_TX_PRECHARGE_SHFT                                        0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_AUX_PARALLEL_LBK_BMSK                                        0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_AUX_PARALLEL_LBK_SHFT                                        0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_AUX_BYPASS_MANCH_LBK_BMSK                                    0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_AUX_BYPASS_MANCH_LBK_SHFT                                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_AUX_SERIAL_LBK_BMSK                                          0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_AUX_SERIAL_LBK_SHFT                                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_AUX_NEAREND_LBK_BMSK                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG3_AUX_NEAREND_LBK_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG4_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000030)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG4_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000030)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG4_RMSK                                                        0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG4_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG4_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG4_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG4_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG4_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG4_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG4_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG4_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG4_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG4_AUX_TX_MANCH_HALFCYC_BMSK                                   0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG4_AUX_TX_MANCH_HALFCYC_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG5_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000034)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG5_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000034)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG5_RMSK                                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG5_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG5_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG5_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG5_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG5_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG5_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG5_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG5_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG5_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG5_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG5_AUX_RX_MANCH_TWOCYC_BMSK                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG5_AUX_RX_MANCH_TWOCYC_SHFT                                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG6_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000038)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG6_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000038)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG6_RMSK                                                        0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG6_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG6_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG6_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG6_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG6_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG6_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG6_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG6_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG6_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG6_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG6_AUX_RX_MANCH_HALFCYC_BMSK                                   0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG6_AUX_RX_MANCH_HALFCYC_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG7_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000003c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG7_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000003c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG7_RMSK                                                         0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG7_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG7_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG7_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG7_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG7_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG7_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG7_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG7_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG7_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG7_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG7_AUX_RX_MANCH_CYCJITTER_BMSK                                  0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG7_AUX_RX_MANCH_CYCJITTER_SHFT                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000040)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000040)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_RMSK                                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_AUX_TX_PREAMBLE_BMSK                                        0xf0
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_AUX_TX_PREAMBLE_SHFT                                         0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_AUX_RX_PREAMBLE_BMSK                                         0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG8_AUX_RX_PREAMBLE_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_ADDR                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000044)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_OFFS                                                  (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000044)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_RMSK                                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_OVERRIDE_TWOCYC_BMSK                                        0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_OVERRIDE_TWOCYC_SHFT                                         0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_OVERRIDE_HALFCYC_BMSK                                       0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_OVERRIDE_HALFCYC_SHFT                                        0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_OVERRIDE_AUX_TIMING_BMSK                                    0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_OVERRIDE_AUX_TIMING_SHFT                                     0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_AUX_RX_CFG_SPARE_BMSK                                       0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_AUX_RX_CFG_SPARE_SHFT                                        0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_AUX_RX_ZERO_IDLE_CNT_BMSK                                    0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG9_AUX_RX_ZERO_IDLE_CNT_SHFT                                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000048)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000048)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_RMSK                                                       0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_AUX_RX_START_DEBOUNCE_ENA_BMSK                             0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_AUX_RX_START_DEBOUNCE_ENA_SHFT                              0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_AUX_RXOUT_DEBOUNCE_ENA_BMSK                                0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_AUX_RXOUT_DEBOUNCE_ENA_SHFT                                 0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_AUX_DBOUNCE_SPARE_BMSK                                      0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG10_AUX_DBOUNCE_SPARE_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000004c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000004c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_RMSK                                                        0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_DLY_AUX_RX_VALID_BMSK                                       0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_DLY_AUX_RX_VALID_SHFT                                       0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_USE_AUXRX_GEN1_BMSK                                         0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG11_USE_AUXRX_GEN1_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG12_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000050)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG12_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000050)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG12_RMSK                                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG12_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG12_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG12_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG12_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG12_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG12_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG12_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG12_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG12_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG12_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG12_AUX_DCTRL_23_16_BMSK                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_CFG12_AUX_DCTRL_23_16_SHFT                                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000054)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000054)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_RMSK                                              0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_AUX_TX_REQ_ERR_MASK_BMSK                          0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_AUX_TX_REQ_ERR_MASK_SHFT                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_ALIGN_ERR_MASK_BMSK                         0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_ALIGN_ERR_MASK_SHFT                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_SYNC_ERR_MASK_BMSK                          0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_SYNC_ERR_MASK_SHFT                          0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_DEC_ERR_MASK_BMSK                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_DEC_ERR_MASK_SHFT                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_STOP_ERR_MASK_BMSK                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_STOP_ERR_MASK_SHFT                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_ADDR                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000058)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_OFFS                                       (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000058)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_RMSK                                             0x9f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_GLOBE_REQ_CLR_CMD_BMSK                       0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_GLOBE_REQ_CLR_CMD_SHFT                        0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_TX_REQ_ERR_CLR_BMSK                          0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_TX_REQ_ERR_CLR_SHFT                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_ALIGN_ERR_CLR_BMSK                         0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_ALIGN_ERR_CLR_SHFT                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_SYNC_ERR_CLR_BMSK                          0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_SYNC_ERR_CLR_SHFT                          0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_DEC_ERR_CLR_BMSK                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_DEC_ERR_CLR_SHFT                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_STOP_ERR_CLR_BMSK                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_STOP_ERR_CLR_SHFT                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_ADDR                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000005c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_OFFS                                              (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000005c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_RMSK                                                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_AUX_BIST_MODE_BMSK                                      0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_AUX_BIST_MODE_SHFT                                       0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_AUX_BIST_SEL_BMSK                                       0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_AUX_BIST_SEL_SHFT                                        0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_AUX_TX_PATGEN_EN_BMSK                                   0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_AUX_TX_PATGEN_EN_SHFT                                    0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_AUX_TX_FIXPAT_BMSK                                      0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_AUX_TX_FIXPAT_SHFT                                       0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_EN_BMSK                                  0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_EN_SHFT                                  0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_GEN_SHORT_BMSK                           0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_GEN_SHORT_SHFT                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_ERR_EN_BMSK                              0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_ERR_EN_SHFT                              0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_CLR_ERROR_COUNT_BMSK                     0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_CLR_ERROR_COUNT_SHFT                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_SEED_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000060)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_SEED_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000060)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_SEED_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_SEED_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_SEED_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_SEED_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_SEED_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_SEED_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_SEED_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_SEED_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_SEED_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_SEED_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_SEED_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_SEED_AUX_BIST_PRBS_SEED_BMSK                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_SEED_AUX_BIST_PRBS_SEED_SHFT                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_POLY_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000064)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_POLY_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000064)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_POLY_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_POLY_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_POLY_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_POLY_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_POLY_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_POLY_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_POLY_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_POLY_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_POLY_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_POLY_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_POLY_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_POLY_AUX_BIST_PRBS_POLY_BMSK                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_PRBS_POLY_AUX_BIST_PRBS_POLY_SHFT                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000068)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000068)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_AUX_TX_PROG_PAT_16B_7_0_BMSK                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_AUX_TX_PROG_PAT_16B_7_0_SHFT                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000006c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000006c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_AUX_TX_PROG_PAT_16B_15_8_BMSK                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_AUX_TX_PROG_PAT_16B_15_8_SHFT                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_ADDR                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000070)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_OFFS                                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000070)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_RMSK                                                          0xb
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_FORCE_CLKBUF_EN_BMSK                                          0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_FORCE_CLKBUF_EN_SHFT                                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_VCO_DIV_CLK_SEL_BMSK                                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_VCO_DIV_VCO_DIV_CLK_SEL_SHFT                                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000074)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000074)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_RMSK                                                      0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_SW_C_EXT_CLKBUF_EN_MUX_BMSK                               0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_SW_C_EXT_CLKBUF_EN_MUX_SHFT                                0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_SW_C_EXT_CLKBUF_EN_BMSK                                   0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_SW_C_EXT_CLKBUF_EN_SHFT                                    0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_SW_TSYNC_DONE_MUX_BMSK                                     0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_SW_TSYNC_DONE_MUX_SHFT                                     0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_SW_TSYNC_DONE_BMSK                                         0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_SW_TSYNC_DONE_SHFT                                         0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_SW_EXT_TSYNC_MUX_BMSK                                      0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_SW_EXT_TSYNC_MUX_SHFT                                      0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_SW_EXT_TSYNC_BMSK                                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TSYNC_OVRD_SW_EXT_TSYNC_SHFT                                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000078)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000078)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_RMSK                                                 0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_L0_CORE_TXCLK_EN_BMSK                                0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_L0_CORE_TXCLK_EN_SHFT                                0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_L0_CORE_PLL_EN_BMSK                                  0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_LANE_CTL_L0_CORE_PLL_EN_SHFT                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000007c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000007c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_RMSK                                               0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TX_HDR_PRBS_SEL_BMSK                       0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TX_HDR_PRBS_SEL_SHFT                        0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TCLK_SEL_BMSK                              0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TCLK_SEL_SHFT                               0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TX_GEN_EN_BMSK                             0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TX_GEN_EN_SHFT                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_RX_PRBS_CHK_EN_BMSK                         0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_RX_PRBS_CHK_EN_SHFT                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_RX_PRBS_GEN_SHORT_BMSK                      0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_RX_PRBS_GEN_SHORT_SHFT                      0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_ERROR_INJECT_BMSK                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_ERROR_INJECT_SHFT                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_ERROR_CLEAR_BMSK                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_ERROR_CLEAR_SHFT                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000080)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000080)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_RX_RESET_PCS_BMSK                          0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_RX_RESET_PCS_SHFT                           0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_TX_RESET_PCS_BMSK                          0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_TX_RESET_PCS_SHFT                           0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_MODE_BMSK                                  0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_MODE_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG2_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000084)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG2_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000084)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG2_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG2_L0_HEADER_PAT_7_0_BMSK                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG2_L0_HEADER_PAT_7_0_SHFT                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000088)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000088)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_RMSK                                                0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_L0_BIST_TX_MASK_BMSK                                0xc
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_L0_BIST_TX_MASK_SHFT                                0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_L0_HEADER_PAT_9_8_BMSK                              0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_CFG3_L0_HEADER_PAT_9_8_SHFT                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000008c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000008c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_L0_PRBS_SEED_7_0_BMSK                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_L0_PRBS_SEED_7_0_SHFT                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000090)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000090)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_RMSK                                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_L0_PRBS_SEED_9_8_BMSK                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_L0_PRBS_SEED_9_8_SHFT                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN0_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000094)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN0_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000094)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN0_RMSK                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN0_L0_PRBS_POLY_7_0_BMSK                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN0_L0_PRBS_POLY_7_0_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN1_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000098)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN1_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000098)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN1_RMSK                                            0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN1_L0_PRBS_POLY_9_8_BMSK                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_PATTERN1_L0_PRBS_POLY_9_8_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000009c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000009c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_RMSK                                                 0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_L1_CORE_TXCLK_EN_BMSK                                0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_L1_CORE_TXCLK_EN_SHFT                                0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_L1_CORE_PLL_EN_BMSK                                  0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_LANE_CTL_L1_CORE_PLL_EN_SHFT                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000a0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_RMSK                                               0x7f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TX_HDR_PRBS_SEL_BMSK                       0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TX_HDR_PRBS_SEL_SHFT                        0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TCLK_SEL_BMSK                              0x20
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TCLK_SEL_SHFT                               0x5
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TX_GEN_EN_BMSK                             0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TX_GEN_EN_SHFT                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_RX_PRBS_CHK_EN_BMSK                         0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_RX_PRBS_CHK_EN_SHFT                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_RX_PRBS_GEN_SHORT_BMSK                      0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_RX_PRBS_GEN_SHORT_SHFT                      0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_ERROR_INJECT_BMSK                           0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_ERROR_INJECT_SHFT                           0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_ERROR_CLEAR_BMSK                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_ERROR_CLEAR_SHFT                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000a4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_RX_RESET_PCS_BMSK                          0x80
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_RX_RESET_PCS_SHFT                           0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_TX_RESET_PCS_BMSK                          0x40
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_TX_RESET_PCS_SHFT                           0x6
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_MODE_BMSK                                  0x3f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_MODE_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG2_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG2_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000a8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG2_RMSK                                               0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG2_L1_HEADER_PAT_7_0_BMSK                             0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG2_L1_HEADER_PAT_7_0_SHFT                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_ADDR                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_OFFS                                         (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000ac)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_RMSK                                                0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_L1_BIST_TX_MASK_BMSK                                0xc
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_L1_BIST_TX_MASK_SHFT                                0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_L1_HEADER_PAT_9_8_BMSK                              0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_CFG3_L1_HEADER_PAT_9_8_SHFT                              0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000b0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_RMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_L1_PRBS_SEED_7_0_BMSK                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_L1_PRBS_SEED_7_0_SHFT                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_ADDR                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_OFFS                                   (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000b4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_RMSK                                          0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_L1_PRBS_SEED_9_8_BMSK                         0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_L1_PRBS_SEED_9_8_SHFT                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN0_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN0_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000b8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN0_RMSK                                           0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN0_L1_PRBS_POLY_7_0_BMSK                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN0_L1_PRBS_POLY_7_0_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN1_ADDR                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN1_OFFS                                     (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000bc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN1_RMSK                                            0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN1_L1_PRBS_POLY_9_8_BMSK                           0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_PATTERN1_L1_PRBS_POLY_9_8_SHFT                           0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_ADDR                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000c0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_OFFS                                                 (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000c0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_RMSK                                                        0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_MISR_CLEAR_BMSK                                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_MISR_CLEAR_SHFT                                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_MISR_ENABLE_BMSK                                            0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_CTRL_MISR_ENABLE_SHFT                                            0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS_SEL_ADDR                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000c4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS_SEL_OFFS                                             (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000c4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS_SEL_RMSK                                                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS_SEL_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS_SEL_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS_SEL_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS_SEL_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS_SEL_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS_SEL_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS_SEL_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS_SEL_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS_SEL_DEBUG_BUS_SEL_BMSK                                     0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS_SEL_DEBUG_BUS_SEL_SHFT                                      0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE0_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000c8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE0_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000c8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE0_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE0_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE0_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE0_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE0_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE0_EDPPHY_SPARE_7_0_BMSK                                         0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE0_EDPPHY_SPARE_7_0_SHFT                                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE1_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000cc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE1_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000cc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE1_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE1_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE1_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE1_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE1_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE1_EDPPHY_SPARE_15_8_BMSK                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE1_EDPPHY_SPARE_15_8_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE2_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000d0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE2_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000d0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE2_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE2_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE2_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE2_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE2_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE2_EDPPHY_SPARE_23_16_BMSK                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE2_EDPPHY_SPARE_23_16_SHFT                                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE3_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000d4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE3_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000d4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE3_RMSK                                                          0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE3_OUT(v)      \
        out_dword(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE3_ADDR,v)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE3_ADDR,m,v,HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE3_IN)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE3_EDPPHY_SPARE_31_24_BMSK                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_SPARE3_EDPPHY_SPARE_31_24_SHFT                                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000d8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000d8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_RMSK                                            0x1f
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_TX_REQ_ERR_BMSK                             0x10
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_TX_REQ_ERR_SHFT                              0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_ALIGN_ERR_BMSK                            0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_ALIGN_ERR_SHFT                            0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_SYNC_ERR_BMSK                             0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_SYNC_ERR_SHFT                             0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_DEC_ERR_BMSK                              0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_DEC_ERR_SHFT                              0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_STOP_ERR_BMSK                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_STOP_ERR_SHFT                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_STATUS_ADDR                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000dc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_STATUS_OFFS                                                    (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000dc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_STATUS_RMSK                                                           0x7
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_STATUS_C_READY_BMSK                                                   0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_STATUS_C_READY_SHFT                                                   0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_STATUS_PHY_READY_BMSK                                                 0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_STATUS_PHY_READY_SHFT                                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_STATUS_TSYNC_DONE_BMSK                                                0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_STATUS_TSYNC_DONE_SHFT                                                0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS0_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000e0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS0_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000e0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS0_RMSK                                                 0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS0_AUX_BIST_CHECK_DONE_BMSK                             0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS0_AUX_BIST_CHECK_DONE_SHFT                             0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS1_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000e4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS1_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000e4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS1_RMSK                                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS1_AUX_BIST_ERROR_COUNT_7_0_BMSK                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS1_AUX_BIST_ERROR_COUNT_7_0_SHFT                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS2_ADDR                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000e8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS2_OFFS                                          (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000e8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS2_RMSK                                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS2_AUX_BIST_ERROR_COUNT_15_8_BMSK                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_AUX_BIST_STATUS2_AUX_BIST_ERROR_COUNT_15_8_SHFT                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS0_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000ec)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS0_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000ec)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS0_RMSK                                             0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_RXCHK_HEADER_SEL_BMSK                    0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_RXCHK_HEADER_SEL_SHFT                    0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_PAT_DATA_NOT_FOUND_BMSK                  0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_PAT_DATA_NOT_FOUND_SHFT                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_HEADER_NOT_FOUND_BMSK                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_HEADER_NOT_FOUND_SHFT                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_CHECK_DONE_BMSK                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_CHECK_DONE_SHFT                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS1_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000f0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS1_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000f0)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS1_RMSK                                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS1_L0_BIST_ERROR_COUNT_7_0_BMSK                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS1_L0_BIST_ERROR_COUNT_7_0_SHFT                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS2_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000f4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS2_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000f4)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS2_RMSK                                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS2_L0_BIST_ERROR_COUNT_15_8_BMSK                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_TX1_BIST_STATUS2_L0_BIST_ERROR_COUNT_15_8_SHFT                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS0_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000f8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS0_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000f8)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS0_RMSK                                             0xf
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_RXCHK_HEADER_SEL_BMSK                    0x8
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_RXCHK_HEADER_SEL_SHFT                    0x3
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_PAT_DATA_NOT_FOUND_BMSK                  0x4
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_PAT_DATA_NOT_FOUND_SHFT                  0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_HEADER_NOT_FOUND_BMSK                    0x2
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_HEADER_NOT_FOUND_SHFT                    0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_CHECK_DONE_BMSK                          0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_CHECK_DONE_SHFT                          0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS1_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x000000fc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS1_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x000000fc)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS1_RMSK                                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS1_L1_BIST_ERROR_COUNT_7_0_BMSK                    0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS1_L1_BIST_ERROR_COUNT_7_0_SHFT                     0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS2_ADDR                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000100)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS2_OFFS                                      (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000100)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS2_RMSK                                            0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS2_L1_BIST_ERROR_COUNT_15_8_BMSK                   0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_TX3_BIST_STATUS2_L1_BIST_ERROR_COUNT_15_8_SHFT                    0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_STATUS_ADDR                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000104)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_STATUS_OFFS                                               (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000104)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_STATUS_RMSK                                                      0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_STATUS_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_STATUS_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_STATUS_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_STATUS_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_STATUS_MISR_CAPTURED_BMSK                                        0x1
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_MISR_STATUS_MISR_CAPTURED_SHFT                                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS000_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000108)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS000_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000108)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS000_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS000_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS000_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS000_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS000_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS000_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS000_L0_MISR_7_0_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS000_L0_MISR_7_0_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS001_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000010c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS001_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000010c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS001_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS001_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS001_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS001_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS001_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS001_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS001_L0_MISR_15_8_BMSK                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS001_L0_MISR_15_8_SHFT                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS010_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000110)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS010_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000110)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS010_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS010_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS010_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS010_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS010_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS010_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS010_L0_MISR_23_16_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS010_L0_MISR_23_16_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS011_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000114)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS011_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000114)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS011_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS011_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS011_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS011_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS011_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS011_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS011_L0_MISR_31_24_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS011_L0_MISR_31_24_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS100_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000118)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS100_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000118)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS100_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS100_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS100_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS100_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS100_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS100_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS100_L0_MISR_39_32_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS100_L0_MISR_39_32_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS101_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000011c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS101_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000011c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS101_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS101_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS101_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS101_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS101_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS101_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS101_L0_MISR_47_40_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS101_L0_MISR_47_40_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS110_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000120)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS110_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000120)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS110_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS110_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS110_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS110_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS110_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS110_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS110_L0_MISR_55_48_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS110_L0_MISR_55_48_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS111_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000124)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS111_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000124)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS111_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS111_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS111_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS111_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS111_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS111_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS111_L0_MISR_63_56_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX0_MISR_STATUS111_L0_MISR_63_56_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS000_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000128)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS000_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000128)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS000_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS000_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS000_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS000_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS000_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS000_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS000_L1_MISR_7_0_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS000_L1_MISR_7_0_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS001_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000012c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS001_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000012c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS001_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS001_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS001_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS001_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS001_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS001_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS001_L1_MISR_15_8_BMSK                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS001_L1_MISR_15_8_SHFT                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS010_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000130)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS010_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000130)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS010_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS010_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS010_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS010_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS010_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS010_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS010_L1_MISR_23_16_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS010_L1_MISR_23_16_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS011_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000134)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS011_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000134)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS011_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS011_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS011_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS011_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS011_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS011_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS011_L1_MISR_31_24_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS011_L1_MISR_31_24_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS100_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000138)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS100_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000138)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS100_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS100_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS100_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS100_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS100_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS100_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS100_L1_MISR_39_32_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS100_L1_MISR_39_32_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS101_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000013c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS101_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000013c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS101_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS101_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS101_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS101_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS101_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS101_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS101_L1_MISR_47_40_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS101_L1_MISR_47_40_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS110_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000140)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS110_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000140)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS110_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS110_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS110_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS110_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS110_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS110_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS110_L1_MISR_55_48_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS110_L1_MISR_55_48_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS111_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000144)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS111_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000144)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS111_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS111_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS111_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS111_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS111_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS111_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS111_L1_MISR_63_56_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX1_MISR_STATUS111_L1_MISR_63_56_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS000_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000148)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS000_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000148)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS000_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS000_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS000_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS000_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS000_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS000_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS000_L2_MISR_7_0_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS000_L2_MISR_7_0_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS001_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000014c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS001_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000014c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS001_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS001_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS001_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS001_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS001_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS001_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS001_L2_MISR_15_8_BMSK                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS001_L2_MISR_15_8_SHFT                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS010_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000150)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS010_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000150)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS010_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS010_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS010_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS010_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS010_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS010_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS010_L2_MISR_23_16_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS010_L2_MISR_23_16_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS011_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000154)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS011_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000154)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS011_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS011_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS011_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS011_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS011_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS011_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS011_L2_MISR_31_24_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS011_L2_MISR_31_24_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS100_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000158)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS100_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000158)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS100_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS100_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS100_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS100_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS100_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS100_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS100_L2_MISR_39_32_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS100_L2_MISR_39_32_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS101_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000015c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS101_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000015c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS101_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS101_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS101_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS101_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS101_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS101_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS101_L2_MISR_47_40_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS101_L2_MISR_47_40_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS110_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000160)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS110_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000160)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS110_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS110_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS110_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS110_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS110_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS110_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS110_L2_MISR_55_48_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS110_L2_MISR_55_48_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS111_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000164)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS111_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000164)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS111_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS111_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS111_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS111_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS111_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS111_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS111_L2_MISR_63_56_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX2_MISR_STATUS111_L2_MISR_63_56_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS000_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000168)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS000_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000168)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS000_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS000_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS000_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS000_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS000_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS000_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS000_L3_MISR_7_0_BMSK                                  0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS000_L3_MISR_7_0_SHFT                                   0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS001_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000016c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS001_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000016c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS001_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS001_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS001_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS001_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS001_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS001_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS001_L3_MISR_15_8_BMSK                                 0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS001_L3_MISR_15_8_SHFT                                  0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS010_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000170)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS010_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000170)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS010_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS010_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS010_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS010_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS010_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS010_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS010_L3_MISR_23_16_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS010_L3_MISR_23_16_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS011_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000174)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS011_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000174)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS011_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS011_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS011_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS011_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS011_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS011_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS011_L3_MISR_31_24_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS011_L3_MISR_31_24_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS100_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000178)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS100_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000178)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS100_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS100_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS100_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS100_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS100_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS100_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS100_L3_MISR_39_32_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS100_L3_MISR_39_32_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS101_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000017c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS101_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000017c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS101_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS101_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS101_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS101_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS101_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS101_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS101_L3_MISR_47_40_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS101_L3_MISR_47_40_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS110_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000180)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS110_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000180)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS110_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS110_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS110_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS110_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS110_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS110_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS110_L3_MISR_55_48_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS110_L3_MISR_55_48_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS111_ADDR                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000184)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS111_OFFS                                        (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000184)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS111_RMSK                                              0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS111_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS111_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS111_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS111_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS111_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS111_L3_MISR_63_56_BMSK                                0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_TX3_MISR_STATUS111_L3_MISR_63_56_SHFT                                 0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS0_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000188)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS0_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000188)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS0_RMSK                                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS0_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS0_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS0_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS0_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS0_DEBUG_BUS_7_0_BMSK                                        0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS0_DEBUG_BUS_7_0_SHFT                                         0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS1_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x0000018c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS1_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x0000018c)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS1_RMSK                                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS1_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS1_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS1_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS1_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS1_DEBUG_BUS_15_8_BMSK                                       0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS1_DEBUG_BUS_15_8_SHFT                                        0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS2_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000190)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS2_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000190)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS2_RMSK                                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS2_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS2_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS2_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS2_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS2_DEBUG_BUS_23_16_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS2_DEBUG_BUS_23_16_SHFT                                       0x0

#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS3_ADDR                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE      + 0x00000194)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS3_OFFS                                                (AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_DP_PHY_REG_BASE_OFFS + 0x00000194)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS3_RMSK                                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS3_IN          \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS3_ADDR, HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS3_RMSK)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS3_INM(m)      \
        in_dword_masked(HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS3_ADDR, m)
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS3_DEBUG_BUS_31_24_BMSK                                      0xff
#define HWIO_AHB2PHY_SOUTH_USB3_DP_PHY_DP_DP_PHY_DEBUG_BUS3_DEBUG_BUS_31_24_SHFT                                       0x0

/*----------------------------------------------------------------------------
 * MODULE: AHB2EDPPHY_CM_EDP_PHY
 *--------------------------------------------------------------------------*/

#define AHB2EDPPHY_CM_EDP_PHY_REG_BASE (MDSS_BASE      + 0x000c0000)
#define AHB2EDPPHY_CM_EDP_PHY_REG_BASE_OFFS 0x000c0000

/*----------------------------------------------------------------------------
 * MODULE: AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL
 *--------------------------------------------------------------------------*/

#define AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE                                         (MDSS_BASE      + 0x000c2000)
#define AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS                                    0x000c2000

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL1_ADDR                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000000)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL1_OFFS                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000000)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL1_RMSK                                                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL1_ATB_SEL_7_0_BMSK                                                     0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL1_ATB_SEL_7_0_SHFT                                                      0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL2_ADDR                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000004)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL2_OFFS                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000004)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL2_RMSK                                                                  0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL2_ATB_SEL_10_8_BMSK                                                     0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_ATB_SEL2_ATB_SEL_10_8_SHFT                                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_FREQ_UPDATE_ADDR                                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000008)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_FREQ_UPDATE_OFFS                                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000008)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_FREQ_UPDATE_RMSK                                                               0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_FREQ_UPDATE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_FREQ_UPDATE_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_FREQ_UPDATE_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_FREQ_UPDATE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_FREQ_UPDATE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_FREQ_UPDATE_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_FREQ_UPDATE_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_FREQ_UPDATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_FREQ_UPDATE_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_FREQ_UPDATE_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_FREQ_UPDATE_PLL_FREQ_UPDATE_BMSK                                               0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_FREQ_UPDATE_PLL_FREQ_UPDATE_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_ADDR                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000000c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_OFFS                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000000c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_RMSK                                                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_SYSCLK_WAKE_BYPASS_BMSK                                              0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_SYSCLK_WAKE_BYPASS_SHFT                                               0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_SYSCLK_WAKE_TIME_BMSK                                                0x70
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_SYSCLK_WAKE_TIME_SHFT                                                 0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_REFCLK_FREQ_SEL_BMSK                                                  0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_REFCLK_FREQ_SEL_SHFT                                                  0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_RSVD_BMSK                                                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_RSVD_SHFT                                                             0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_BIAS_WAIT_TIME_BMSK                                                   0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BG_TIMER_BIAS_WAIT_TIME_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_ADDR                                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000010)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_OFFS                                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000010)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_RMSK                                                             0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_SSC_CENTER_BMSK                                                  0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_SSC_CENTER_SHFT                                                  0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_SSC_EN_BMSK                                                      0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_EN_CENTER_SSC_EN_SHFT                                                      0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER1_ADDR                                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000014)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER1_OFFS                                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000014)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER1_RMSK                                                             0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER1_SSC_ADJPER_7_0_BMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER1_SSC_ADJPER_7_0_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER2_ADDR                                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000018)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER2_OFFS                                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000018)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER2_RMSK                                                              0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER2_SSC_ADJPER_9_8_BMSK                                               0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_ADJ_PER2_SSC_ADJPER_9_8_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER1_ADDR                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000001c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER1_OFFS                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000001c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER1_RMSK                                                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER1_SSC_PER_7_0_BMSK                                                     0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER1_SSC_PER_7_0_SHFT                                                      0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER2_ADDR                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000020)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER2_OFFS                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000020)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER2_RMSK                                                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER2_SSC_PER_15_8_BMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_PER2_SSC_PER_15_8_SHFT                                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_ADDR                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000024)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_OFFS                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000024)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_RMSK                                                     0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_SSC_STEPSIZE_MODE0_7_0_BMSK                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_SSC_STEPSIZE_MODE0_7_0_SHFT                               0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_ADDR                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000028)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_OFFS                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000028)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_RMSK                                                     0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_SSC_STEPSIZE_MODE0_15_8_BMSK                             0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_SSC_STEPSIZE_MODE0_15_8_SHFT                              0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_ADDR                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000002c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_OFFS                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000002c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_RMSK                                                      0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_SSC_STEPSIZE_MODE0_16_16_BMSK                             0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_SSC_STEPSIZE_MODE0_16_16_SHFT                             0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_ADDR                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000030)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_OFFS                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000030)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_RMSK                                                     0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_SSC_STEPSIZE_MODE1_7_0_BMSK                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_SSC_STEPSIZE_MODE1_7_0_SHFT                               0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_ADDR                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000034)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_OFFS                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000034)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_RMSK                                                     0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_SSC_STEPSIZE_MODE1_15_8_BMSK                             0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_SSC_STEPSIZE_MODE1_15_8_SHFT                              0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_ADDR                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000038)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_OFFS                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000038)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_RMSK                                                      0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_SSC_STEPSIZE_MODE1_16_16_BMSK                             0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_SSC_STEPSIZE_MODE1_16_16_SHFT                             0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_ADDR                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000003c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_OFFS                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000003c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_RMSK                                                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_PLL_POSTDIV_7_0_BMSK                                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_PLL_POSTDIV_7_0_SHFT                                                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_ADDR                                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000040)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_OFFS                                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000040)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_RMSK                                                             0x11
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_PLL_POSTDIV_MUX_BMSK                                             0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_PLL_POSTDIV_MUX_SHFT                                              0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_PLL_POSTDIV_8_8_BMSK                                              0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_POST_DIV_MUX_PLL_POSTDIV_8_8_SHFT                                              0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000044)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000044)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_RMSK                                                      0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_EN_SYSCLK_TX_SEL_BMSK                                     0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_EN_SYSCLK_TX_SEL_SHFT                                      0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_CLKBUF_L_EN_BMSK                                           0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_CLKBUF_L_EN_SHFT                                           0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_CLKBUF_R_EN_BMSK                                           0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_CLKBUF_R_EN_SHFT                                           0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_BIAS_EN_MUX_BMSK                                           0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_BIAS_EN_MUX_SHFT                                           0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_BIAS_EN_BMSK                                               0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_BIAS_EN_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_ADDR                                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000048)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_OFFS                                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000048)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_RMSK                                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_CLKDRVIDLE_EN_BMSK                                                0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_CLKDRVIDLE_EN_SHFT                                                 0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_EN_SYSCLK_TX_PS3PS4_BMSK                                          0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_EN_SYSCLK_TX_PS3PS4_SHFT                                           0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_EN_SYSCLK_TX_PS0PS1PS2_BMSK                                       0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_EN_SYSCLK_TX_PS0PS1PS2_SHFT                                        0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_CLK_EP_EN_BMSK                                                    0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_CLK_EP_EN_SHFT                                                     0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_PLL_CLKOUT_EN_MUX_BMSK                                             0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_PLL_CLKOUT_EN_MUX_SHFT                                             0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_PLL_CLKOUT_EN_BMSK                                                 0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_PLL_CLKOUT_EN_SHFT                                                 0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_EXT_CLKBUF_EN_MUX_BMSK                                             0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_EXT_CLKBUF_EN_MUX_SHFT                                             0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_EXT_CLKBUF_EN_BMSK                                                 0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_ENABLE1_EXT_CLKBUF_EN_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_ADDR                                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000004c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_OFFS                                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000004c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_RMSK                                                             0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_EP_GLITCHFREE_BYPASS_BMSK                                        0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_EP_GLITCHFREE_BYPASS_SHFT                                         0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_TX_SYSCLKSEL_MUX_BMSK                                     0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_TX_SYSCLKSEL_MUX_SHFT                                      0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_TX_SYSCLKSEL_BMSK                                         0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_TX_SYSCLKSEL_SHFT                                          0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_DIV2_SEL_BMSK                                              0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_DIV2_SEL_SHFT                                              0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_CM_BMSK                                                    0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_CM_SHFT                                                    0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_AC_COUPLE_BMSK                                             0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_AC_COUPLE_SHFT                                             0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_GNDTERM_BMSK                                               0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_GNDTERM_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000050)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000050)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_RMSK                                                         0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_EN_CTRL_BY_PSM_BMSK                                   0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_EN_CTRL_BY_PSM_SHFT                                   0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_EN_PS3PS4_BMSK                                        0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_EN_PS3PS4_SHFT                                        0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_BUF_EN_MUX_BMSK                                       0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_BUF_EN_MUX_SHFT                                       0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_SW_SYSCLK_BUF_EN_BMSK                                        0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_SW_SYSCLK_BUF_EN_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_ADDR                                                             (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000054)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_OFFS                                                             (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000054)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_RMSK                                                                    0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_PLL_EN_MUX_BMSK                                                         0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_PLL_EN_MUX_SHFT                                                         0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_PLL_EN_BMSK                                                             0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_EN_PLL_EN_SHFT                                                             0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_IVCO_ADDR                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000058)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_IVCO_OFFS                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000058)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_IVCO_RMSK                                                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_IVCO_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_IVCO_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_IVCO_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_IVCO_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_IVCO_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_IVCO_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_IVCO_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_IVCO_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_IVCO_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_IVCO_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_IVCO_PLL_IVCO_BMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_IVCO_PLL_IVCO_SHFT                                                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IETRIM_ADDR                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000005c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IETRIM_OFFS                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000005c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IETRIM_RMSK                                                               0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IETRIM_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IETRIM_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IETRIM_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IETRIM_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IETRIM_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IETRIM_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IETRIM_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IETRIM_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IETRIM_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IETRIM_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IETRIM_IETRIM_BMSK                                                        0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IETRIM_IETRIM_SHFT                                                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IPTRIM_ADDR                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000060)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IPTRIM_OFFS                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000060)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IPTRIM_RMSK                                                               0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IPTRIM_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IPTRIM_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IPTRIM_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IPTRIM_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IPTRIM_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IPTRIM_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IPTRIM_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IPTRIM_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IPTRIM_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IPTRIM_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IPTRIM_IPTRIM_BMSK                                                        0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_IPTRIM_IPTRIM_SHFT                                                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_ADDR                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000064)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_OFFS                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000064)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_RMSK                                                     0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_DIVSEL_MUX_BMSK                            0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_DIVSEL_MUX_SHFT                             0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_DIVSEL_BMSK                                0x18
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_DIVSEL_SHFT                                 0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_FORCE_BMSK                                  0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_FORCE_SHFT                                  0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_EN_MUX_BMSK                                 0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_EN_MUX_SHFT                                 0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_EN_BMSK                                     0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_EN_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_ADDR                                             (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000068)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_OFFS                                             (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000068)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_RMSK                                                    0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_SYSCLK_CLKDET_COMP_BMSK                                 0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_SYSCLK_CLKDET_COMP_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000006c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000006c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_RMSK                                                         0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_CLK_EP_DIV_MODE0_BMSK                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_CLK_EP_DIV_MODE0_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000070)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000070)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_RMSK                                                         0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_CLK_EP_DIV_MODE1_BMSK                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_CLK_EP_DIV_MODE1_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE0_ADDR                                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000074)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE0_OFFS                                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000074)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE0_RMSK                                                            0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE0_PLL_CPCTRL_MODE0_BMSK                                           0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE0_PLL_CPCTRL_MODE0_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE1_ADDR                                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000078)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE1_OFFS                                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000078)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE1_RMSK                                                            0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE1_PLL_CPCTRL_MODE1_BMSK                                           0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CP_CTRL_MODE1_PLL_CPCTRL_MODE1_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE0_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000007c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE0_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000007c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE0_RMSK                                                          0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE0_PLL_RCTRL_MODE0_BMSK                                          0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE0_PLL_RCTRL_MODE0_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE1_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000080)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE1_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000080)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE1_RMSK                                                          0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE1_PLL_RCTRL_MODE1_BMSK                                          0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_RCTRL_MODE1_PLL_RCTRL_MODE1_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE0_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000084)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE0_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000084)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE0_RMSK                                                          0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE0_PLL_CCTRL_MODE0_BMSK                                          0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE0_PLL_CCTRL_MODE0_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE1_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000088)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE1_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000088)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE1_RMSK                                                          0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE1_PLL_CCTRL_MODE1_BMSK                                          0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CCTRL_MODE1_PLL_CCTRL_MODE1_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_ADDR                                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000008c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_OFFS                                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000008c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_RMSK                                                                0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_PLL_STABLE_TIME_BMSK                                                0x60
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_PLL_STABLE_TIME_SHFT                                                 0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_MASH_RESET_MUX_BMSK                                                 0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_MASH_RESET_MUX_SHFT                                                  0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_MASH_RESET_BMSK                                                      0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_MASH_RESET_SHFT                                                      0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_PLL_CPLIN_BMSK                                                       0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_PLL_CPLIN_SHFT                                                       0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_PLL_DIV_FFEN_BMSK                                                    0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_PLL_DIV_FFEN_SHFT                                                    0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_PLL_DIV_ORD_BMSK                                                     0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_CNTRL_PLL_DIV_ORD_SHFT                                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000090)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000090)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_RMSK                                                       0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_BIAS_EN_CTRL_BY_PSM_BMSK                                   0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_BIAS_EN_CTRL_BY_PSM_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_ADDR                                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000094)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_OFFS                                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000094)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_RMSK                                                            0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_CML_SYSCLK_SEL_BMSK                                             0xe0
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_CML_SYSCLK_SEL_SHFT                                              0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_TERM_SEL_BMSK                                            0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_TERM_SEL_SHFT                                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_SEL_BMSK                                                  0xc
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_SEL_SHFT                                                  0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_EN_MUX_BMSK                                               0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_EN_MUX_SHFT                                               0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_EN_BMSK                                                   0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_EN_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CML_SYSCLK_SEL_ADDR                                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000098)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CML_SYSCLK_SEL_OFFS                                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000098)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CML_SYSCLK_SEL_RMSK                                                            0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CML_SYSCLK_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CML_SYSCLK_SEL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CML_SYSCLK_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CML_SYSCLK_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CML_SYSCLK_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CML_SYSCLK_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CML_SYSCLK_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CML_SYSCLK_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CML_SYSCLK_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CML_SYSCLK_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CML_SYSCLK_SEL_CML_SYSCLK_SEL_MUX_BMSK                                         0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CML_SYSCLK_SEL_CML_SYSCLK_SEL_MUX_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_ADDR                                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000009c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_OFFS                                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000009c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_RMSK                                                            0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_FORCE_C_READY_BMSK                                              0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_FORCE_C_READY_SHFT                                               0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_TSYNC_SEL_BMSK                                                  0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_TSYNC_SEL_SHFT                                                   0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_DISABLE_CLKGATE_BMSK                                            0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_DISABLE_CLKGATE_SHFT                                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_PLL_UNLOCK_DISABLE_BMSK                                          0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_PLL_UNLOCK_DISABLE_SHFT                                          0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_RSM_START_MUX_BMSK                                               0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_RSM_START_MUX_SHFT                                               0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_RSM_START_BMSK                                                   0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_RSM_START_SHFT                                                   0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_FORCE_PLLLOCK_BMSK                                               0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL_FORCE_PLLLOCK_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_ADDR                                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000a0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_OFFS                                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000a0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_RMSK                                                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_CORE_PLL_EN_MUX_BMSK                                           0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_CORE_PLL_EN_MUX_SHFT                                            0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_CORE_PLL_EN_BMSK                                               0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_CORE_PLL_EN_SHFT                                                0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_BYPASS_RSM_BIAS_BMSK                                           0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_BYPASS_RSM_BIAS_SHFT                                            0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_BYPASS_RSM_INTEGLOOP_CAL_BMSK                                  0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_BYPASS_RSM_INTEGLOOP_CAL_SHFT                                   0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_PULSE_WIDTH_BMSK                                          0xc
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_PULSE_WIDTH_SHFT                                          0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_MUX_BMSK                                                  0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_MUX_SHFT                                                  0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_BMSK                                                      0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_SHFT                                                      0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_ADDR                                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000a4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_OFFS                                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000a4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_RMSK                                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_RNG_2_BMSK                                                0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_RNG_2_SHFT                                                 0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_CNT_2_BMSK                                                0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_CNT_2_SHFT                                                 0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_EN_MUX_BMSK                                               0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_EN_MUX_SHFT                                                0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_EN_BMSK                                                   0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_EN_SHFT                                                    0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_RNG_BMSK                                                   0xc
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_RNG_SHFT                                                   0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_CNT_BMSK                                                   0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_CNT_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_ADDR                                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000a8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_OFFS                                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000a8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_RMSK                                                              0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_PLLLOCK_RNG_UPDATE_DISABLE_BMSK                                   0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_PLLLOCK_RNG_UPDATE_DISABLE_SHFT                                   0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_PLLLOCK_STOP_COUNT_BMSK                                           0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_PLLLOCK_STOP_COUNT_SHFT                                           0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_BYP_PLLLOCK_BMSK                                                  0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP_CFG_BYP_PLLLOCK_SHFT                                                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE0_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000ac)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE0_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000ac)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE0_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE0_PLLLOCK_CMP_MODE0_7_0_BMSK                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE0_PLLLOCK_CMP_MODE0_7_0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE0_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000b0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE0_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000b0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE0_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE0_PLLLOCK_CMP_MODE0_15_8_BMSK                                   0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE0_PLLLOCK_CMP_MODE0_15_8_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE1_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000b4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE1_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000b4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE1_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE1_PLLLOCK_CMP_MODE1_7_0_BMSK                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP1_MODE1_PLLLOCK_CMP_MODE1_7_0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE1_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000b8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE1_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000b8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE1_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE1_PLLLOCK_CMP_MODE1_15_8_BMSK                                   0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_LOCK_CMP2_MODE1_PLLLOCK_CMP_MODE1_15_8_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE0_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000bc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE0_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000bc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE0_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE0_DEC_START_MODE0_7_0_BMSK                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE0_DEC_START_MODE0_7_0_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE0_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000c0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE0_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000c0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE0_RMSK                                                       0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE0_DEC_START_MODE0_8_8_BMSK                                   0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE0_DEC_START_MODE0_8_8_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE1_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000c4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE1_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000c4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE1_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE1_DEC_START_MODE1_7_0_BMSK                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MODE1_DEC_START_MODE1_7_0_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE1_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000c8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE1_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000c8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE1_RMSK                                                       0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE1_DEC_START_MODE1_8_8_BMSK                                   0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEC_START_MSB_MODE1_DEC_START_MODE1_8_8_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000cc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000cc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_DIV_FRAC_START_MODE0_7_0_BMSK                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_DIV_FRAC_START_MODE0_7_0_SHFT                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000d0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000d0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_DIV_FRAC_START_MODE0_15_8_BMSK                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_DIV_FRAC_START_MODE0_15_8_SHFT                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000d4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000d4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_RMSK                                                     0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_DIV_FRAC_START_MODE0_19_16_BMSK                          0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_DIV_FRAC_START_MODE0_19_16_SHFT                          0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000d8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000d8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_DIV_FRAC_START_MODE1_7_0_BMSK                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_DIV_FRAC_START_MODE1_7_0_SHFT                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000dc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000dc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_DIV_FRAC_START_MODE1_15_8_BMSK                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_DIV_FRAC_START_MODE1_15_8_SHFT                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000e0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000e0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_RMSK                                                     0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_DIV_FRAC_START_MODE1_19_16_BMSK                          0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_DIV_FRAC_START_MODE1_19_16_SHFT                          0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_INITVAL_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000e4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_INITVAL_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000e4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_INITVAL_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_INITVAL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_INITVAL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_INITVAL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_INITVAL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_INITVAL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_INITVAL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_INITVAL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_INITVAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_INITVAL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_INITVAL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_INITVAL_INTEGLOOP_INITVAL_BMSK                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_INITVAL_INTEGLOOP_INITVAL_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_ADDR                                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000e8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_OFFS                                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000e8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_RMSK                                                              0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_P_GAIN_SIGN_FLIP_BMSK                                             0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_P_GAIN_SIGN_FLIP_SHFT                                             0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_CODE_BYPASS_BMSK                                        0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_CODE_BYPASS_SHFT                                        0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_EN_MUX_BMSK                                             0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_EN_MUX_SHFT                                             0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_EN_BMSK                                                 0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_EN_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000ec)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000ec)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_INTEGLOOP_GAIN_MODE0_7_0_BMSK                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_INTEGLOOP_GAIN_MODE0_7_0_SHFT                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000f0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000f0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_RMSK                                                     0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_INTEGLOOP_GAIN_MODE0_11_8_BMSK                           0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_INTEGLOOP_GAIN_MODE0_11_8_SHFT                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000f4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000f4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_INTEGLOOP_GAIN_MODE1_7_0_BMSK                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_INTEGLOOP_GAIN_MODE1_7_0_SHFT                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000f8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000f8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_RMSK                                                     0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_INTEGLOOP_GAIN_MODE1_11_8_BMSK                           0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_INTEGLOOP_GAIN_MODE1_11_8_SHFT                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_ADDR                                             (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000fc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_OFFS                                             (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000fc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_RMSK                                                   0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_INTEGLOOP_P_GAIN_7_0_BMSK                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_INTEGLOOP_P_GAIN_7_0_SHFT                               0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_ADDR                                             (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000100)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_OFFS                                             (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000100)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_RMSK                                                    0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_INTEGLOOP_P_GAIN_9_8_BMSK                               0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_INTEGLOOP_P_GAIN_9_8_SHFT                               0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000104)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000104)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_RMSK                                                      0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_TOO_SLOW_CNTSEL_BMSK                                0x18
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_TOO_SLOW_CNTSEL_SHFT                                 0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FORCE_CORRECT_POL_BMSK                                     0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FORCE_CORRECT_POL_SHFT                                     0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_DEAD_CORRECT_EN_BMSK                                 0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_DEAD_CORRECT_EN_SHFT                                 0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_DEAD_TIME_BMSK                                       0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_DEAD_TIME_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_ADDR                                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000108)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_OFFS                                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000108)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_RMSK                                                            0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_BIN_VCOCAL_FORCE_DONE_BMSK                                      0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_BIN_VCOCAL_FORCE_DONE_SHFT                                       0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_VCOCAL_TYPE_SEL_BMSK                                            0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_VCOCAL_TYPE_SEL_SHFT                                             0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_VCOCAL_POS_SLOPE_BMSK                                           0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_VCOCAL_POS_SLOPE_SHFT                                            0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_BYP_VCOCAL_MODE1_BMSK                                            0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_BYP_VCOCAL_MODE1_SHFT                                            0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_BYP_VCOCAL_MODE0_BMSK                                            0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_BYP_VCOCAL_MODE0_SHFT                                            0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_VCO_TUNE_EN_MUX_BMSK                                             0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_VCO_TUNE_EN_MUX_SHFT                                             0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_VCO_TUNE_EN_BMSK                                                 0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_CTRL_VCO_TUNE_EN_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_ADDR                                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000010c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_OFFS                                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000010c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_RMSK                                                              0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_VCO_DEFAULT_FREQ_BMSK                                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_VCO_DEFAULT_FREQ_SHFT                                             0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_MAP_LANE_PS0B_BMSK                                                0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_MAP_LANE_PS0B_SHFT                                                0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_MAP_LANE_PS0A_BMSK                                                0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAP_MAP_LANE_PS0A_SHFT                                                0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE0_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000110)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE0_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000110)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE0_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE0_PLL_VCOTUNE_MODE0_7_0_BMSK                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE0_PLL_VCOTUNE_MODE0_7_0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE0_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000114)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE0_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000114)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE0_RMSK                                                           0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE0_PLL_VCOTUNE_MODE0_9_8_BMSK                                     0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE0_PLL_VCOTUNE_MODE0_9_8_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE1_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000118)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE1_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000118)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE1_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE1_PLL_VCOTUNE_MODE1_7_0_BMSK                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE1_MODE1_PLL_VCOTUNE_MODE1_7_0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE1_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000011c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE1_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000011c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE1_RMSK                                                           0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE1_PLL_VCOTUNE_MODE1_9_8_BMSK                                     0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE2_MODE1_PLL_VCOTUNE_MODE1_9_8_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000120)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000120)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_VCO_TUNE_INITVAL_7_0_BMSK                                   0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_VCO_TUNE_INITVAL_7_0_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000124)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000124)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_RMSK                                                         0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_VCO_TUNE_INITVAL_9_8_BMSK                                    0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_VCO_TUNE_INITVAL_9_8_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000128)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000128)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_RMSK                                                         0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_VCO_TUNE_MINVAL_7_0_BMSK                                     0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_VCO_TUNE_MINVAL_7_0_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000012c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000012c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_RMSK                                                          0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_VCO_TUNE_MINVAL_9_8_BMSK                                      0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_VCO_TUNE_MINVAL_9_8_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000130)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000130)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_RMSK                                                         0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_VCO_TUNE_MAXVAL_7_0_BMSK                                     0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_VCO_TUNE_MAXVAL_7_0_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000134)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000134)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_RMSK                                                          0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_VCO_TUNE_MAXVAL_9_8_BMSK                                      0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_VCO_TUNE_MAXVAL_9_8_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER1_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000138)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER1_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000138)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER1_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER1_PLL_VCOTUNE_TIMER_7_0_BMSK                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER1_PLL_VCOTUNE_TIMER_7_0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER2_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000013c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER2_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000013c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER2_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER2_PLL_VCOTUNE_TIMER_15_8_BMSK                                   0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_TUNE_TIMER2_PLL_VCOTUNE_TIMER_15_8_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_ADDR                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000140)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_OFFS                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000140)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_RMSK                                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_REFGEN_READY_BMSK                                                  0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_REFGEN_READY_SHFT                                                   0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_FREEZEIO_D_BMSK                                                    0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_FREEZEIO_D_SHFT                                                     0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_SWITCH_TO_REFCLK_DONE_BMSK                                         0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_SWITCH_TO_REFCLK_DONE_SHFT                                          0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_SWITCH_TO_CORECLK_DONE_BMSK                                        0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_SWITCH_TO_CORECLK_DONE_SHFT                                         0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_SWITCH_TO_AUXCLK_DONE_BMSK                                          0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_SWITCH_TO_AUXCLK_DONE_SHFT                                          0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_PLL_UNLOCKED_BMSK                                                   0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_PLL_UNLOCKED_SHFT                                                   0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_PLL_LOCKED_BMSK                                                     0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_PLL_LOCKED_SHFT                                                     0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_PLL_FREQ_DONE_BMSK                                                  0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_STATUS_PLL_FREQ_DONE_SHFT                                                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESET_SM_STATUS_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000144)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESET_SM_STATUS_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000144)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESET_SM_STATUS_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESET_SM_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESET_SM_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESET_SM_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESET_SM_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESET_SM_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESET_SM_STATUS_RESETSM_BMSK                                                  0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESET_SM_STATUS_RESETSM_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000148)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000148)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_RMSK                                                      0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_RESTRIM_CODE_BMSK                                         0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_RESTRIM_CODE_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000014c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000014c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_VCO_CTUNE_BINCODE_7_0_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_VCO_CTUNE_BINCODE_7_0_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000150)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000150)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_RMSK                                                       0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_VCO_CTUNE_BINCODE_9_8_BMSK                                 0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_VCO_CTUNE_BINCODE_9_8_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_ADDR                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000154)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_OFFS                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000154)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_RMSK                                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_REFCLK_DRV_EN_MUX_BMSK                                             0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_REFCLK_DRV_EN_MUX_SHFT                                              0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_REFCLK_DRV_EN_BMSK                                                 0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_REFCLK_DRV_EN_SHFT                                                  0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_TSYNC_EN_MUX_BMSK                                                  0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_TSYNC_EN_MUX_SHFT                                                   0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_TSYNC_EN_BMSK                                                      0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_TSYNC_EN_SHFT                                                       0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_SYSCLK_CMOS_PAD_SEL_BMSK                                            0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_SYSCLK_CMOS_PAD_SEL_SHFT                                            0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_SYSCLK_TX_SWINGSEL_BMSK                                             0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_SYSCLK_TX_SWINGSEL_SHFT                                             0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_EP_REFCLK_SEL_BMSK                                                  0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CLK_SELECT_EP_REFCLK_SEL_SHFT                                                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_ADDR                                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000158)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_OFFS                                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000158)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_RMSK                                                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_HSCLK_DIVSEL_MODE1_BMSK                                             0xf0
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_HSCLK_DIVSEL_MODE1_SHFT                                              0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_HSCLK_DIVSEL_MODE0_BMSK                                              0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_SEL_HSCLK_DIVSEL_MODE0_SHFT                                              0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000015c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000015c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_HSCLK_SWITCH_DIVSEL_MODE1_BMSK                            0xf0
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_HSCLK_SWITCH_DIVSEL_MODE1_SHFT                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_HSCLK_SWITCH_DIVSEL_MODE0_BMSK                             0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_HSCLK_SWITCH_DIVSEL_MODE0_SHFT                             0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_ADDR                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000160)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_OFFS                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000160)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_RMSK                                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_INTEGLOOP_BINCODE_BMSK                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_INTEGLOOP_BINCODE_SHFT                                0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_ANALOG_ADDR                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000164)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_ANALOG_OFFS                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000164)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_ANALOG_RMSK                                                                0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_ANALOG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_ANALOG_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_ANALOG_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_ANALOG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_ANALOG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_ANALOG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_ANALOG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_ANALOG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_ANALOG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_ANALOG_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_ANALOG_PLL_ANALOG_BMSK                                                     0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_PLL_ANALOG_PLL_ANALOG_SHFT                                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE0_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000168)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE0_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000168)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE0_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE0_CORE_CLK_DIV_MODE0_BMSK                                     0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE0_CORE_CLK_DIV_MODE0_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE1_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000016c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE1_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000016c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE1_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE1_CORE_CLK_DIV_MODE1_BMSK                                     0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORECLK_DIV_MODE1_CORE_CLK_DIV_MODE1_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SW_RESET_ADDR                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000170)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SW_RESET_OFFS                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000170)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SW_RESET_RMSK                                                                  0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SW_RESET_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SW_RESET_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SW_RESET_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SW_RESET_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SW_RESET_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SW_RESET_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SW_RESET_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SW_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SW_RESET_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SW_RESET_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SW_RESET_SW_RESET_BMSK                                                         0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SW_RESET_SW_RESET_SHFT                                                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_ADDR                                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000174)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_OFFS                                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000174)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_RMSK                                                              0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_CLKS_PLL_DIVSEL_MODE1_BMSK                                        0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_CLKS_PLL_DIVSEL_MODE1_SHFT                                         0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_CLKS_PLL_DIVSEL_MODE0_BMSK                                        0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_CLKS_PLL_DIVSEL_MODE0_SHFT                                         0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_CORECLK_EN_MUX_BMSK                                                0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_CORECLK_EN_MUX_SHFT                                                0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_CORECLK_EN_BMSK                                                    0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_CORECLK_EN_SHFT                                                    0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_AUXCLK_EN_MUX_BMSK                                                 0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_AUXCLK_EN_MUX_SHFT                                                 0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_AUXCLK_EN_BMSK                                                     0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CORE_CLK_EN_AUXCLK_EN_SHFT                                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_C_READY_STATUS_ADDR                                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000178)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_C_READY_STATUS_OFFS                                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000178)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_C_READY_STATUS_RMSK                                                            0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_C_READY_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_C_READY_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_C_READY_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_C_READY_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_C_READY_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_C_READY_STATUS_C_READY_BMSK                                                    0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_C_READY_STATUS_C_READY_SHFT                                                    0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_ADDR                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000017c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_OFFS                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000017c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_RMSK                                                               0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_FORCE_REFGEN_READY_BMSK                                            0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_FORCE_REFGEN_READY_SHFT                                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_PSM_SWITCH_CORECLK_BMSK                                             0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_PSM_SWITCH_CORECLK_SHFT                                             0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_PSM_SWITCH_AUXCLK_BMSK                                              0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_PSM_SWITCH_AUXCLK_SHFT                                              0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_PLL_FBCLK_SEL_BMSK                                                  0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_PLL_FBCLK_SEL_SHFT                                                  0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_CLK_BIAS_REFSEL_BMSK                                                0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_CONFIG_CLK_BIAS_REFSEL_SHFT                                                0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000180)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000180)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_RMSK                                                        0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_PLL_HS_SWITCH_MUX_BMSK                                      0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_PLL_HS_SWITCH_MUX_SHFT                                       0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_PLL_HS_SWITCH_BMSK                                           0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_PLL_HS_SWITCH_SHFT                                           0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_SW_UPDATE_BMSK                                      0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_SW_UPDATE_SHFT                                      0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_SW_SEL_BMSK                                         0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_SW_SEL_SHFT                                         0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_CODE_BMSK                                           0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_CODE_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000184)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000184)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_RMSK                                                          0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_PLL_DIGCLK_DIVSEL_MODE1_BMSK                                  0xc
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_PLL_DIGCLK_DIVSEL_MODE1_SHFT                                  0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_PLL_DIGCLK_DIVSEL_MODE0_BMSK                                  0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_PLL_DIGCLK_DIVSEL_MODE0_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS0_ADDR                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000188)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS0_OFFS                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000188)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS0_RMSK                                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS0_DEBUG_BUS_7_0_BMSK                                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS0_DEBUG_BUS_7_0_SHFT                                                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS1_ADDR                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000018c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS1_OFFS                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000018c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS1_RMSK                                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS1_DEBUG_BUS_15_8_BMSK                                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS1_DEBUG_BUS_15_8_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS2_ADDR                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000190)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS2_OFFS                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000190)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS2_RMSK                                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS2_DEBUG_BUS_23_16_BMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS2_DEBUG_BUS_23_16_SHFT                                                0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS3_ADDR                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000194)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS3_OFFS                                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000194)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS3_RMSK                                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS3_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS3_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS3_DEBUG_BUS_31_24_BMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS3_DEBUG_BUS_31_24_SHFT                                                0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_ADDR                                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000198)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_OFFS                                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000198)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_RMSK                                                            0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_CLK_DEBUG_SEL_BMSK                                              0xf0
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_CLK_DEBUG_SEL_SHFT                                               0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_DEBUG_BUS_SEL_BMSK                                               0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_DEBUG_BUS_SEL_DEBUG_BUS_SEL_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_ADDR                                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000019c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_OFFS                                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000019c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_RMSK                                                                0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_DIS_CG_RATE_CHANGE_BMSK                                             0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_DIS_CG_RATE_CHANGE_SHFT                                              0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_DIS_CG_SYSGLITCH_BMSK                                               0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_DIS_CG_SYSGLITCH_SHFT                                                0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_PLL_RESET_MUX_BMSK                                                  0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_PLL_RESET_MUX_SHFT                                                   0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_PLL_RESET_BMSK                                                       0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_PLL_RESET_SHFT                                                       0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_PLL_VREG_READY_MUX_BMSK                                              0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_PLL_VREG_READY_MUX_SHFT                                              0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_PLL_VREG_READY_BMSK                                                  0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_PLL_VREG_READY_SHFT                                                  0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_DISABLE_B2T_INTEGLOOP_CLKGATE_BMSK                                   0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC1_DISABLE_B2T_INTEGLOOP_CLKGATE_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC2_ADDR                                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000001a0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC2_OFFS                                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000001a0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC2_RMSK                                                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC2_RSVD_BMSK                                                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MISC2_RSVD_SHFT                                                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MODE_ADDR                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000001a4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MODE_OFFS                                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000001a4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MODE_RMSK                                                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MODE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MODE_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MODE_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MODE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MODE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MODE_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MODE_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MODE_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MODE_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MODE_CMN_MODE_BMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_CMN_MODE_CMN_MODE_SHFT                                                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000001a8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000001a8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_RMSK                                                        0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_PLL_VREFGEN_REFSEL_BMSK                                     0x60
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_PLL_VREFGEN_REFSEL_SHFT                                      0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_PLL_VAR_DCCTRL_BMSK                                         0x18
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_PLL_VAR_DCCTRL_SHFT                                          0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_CMN_VREG_SEL_BMSK                                            0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_CMN_VREG_SEL_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_ADDR                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000001ac)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_OFFS                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000001ac)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_RMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_BIN_VCOCAL_MEAS_CNT_MODE0_7_0_BMSK                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_BIN_VCOCAL_MEAS_CNT_MODE0_7_0_SHFT                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_ADDR                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000001b0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_OFFS                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000001b0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_RMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_BIN_VCOCAL_MEAS_CNT_MODE0_15_8_BMSK                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_BIN_VCOCAL_MEAS_CNT_MODE0_15_8_SHFT                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_ADDR                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000001b4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_OFFS                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000001b4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_RMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_BIN_VCOCAL_MEAS_CNT_MODE1_7_0_BMSK                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_BIN_VCOCAL_MEAS_CNT_MODE1_7_0_SHFT                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_ADDR                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000001b8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_OFFS                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000001b8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_RMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_BIN_VCOCAL_MEAS_CNT_MODE1_15_8_BMSK                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_BIN_VCOCAL_MEAS_CNT_MODE1_15_8_SHFT                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_ADDR                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000001bc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_OFFS                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000001bc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_RMSK                                                     0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_BIN_VCOCAL_HSCLK_SEL_MODE1_BMSK                          0xf0
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_BIN_VCOCAL_HSCLK_SEL_MODE1_SHFT                           0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_BIN_VCOCAL_HSCLK_SEL_MODE0_BMSK                           0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_BIN_VCOCAL_HSCLK_SEL_MODE0_SHFT                           0x0

/*----------------------------------------------------------------------------
 * MODULE: AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE
 *--------------------------------------------------------------------------*/

#define AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE                                       (MDSS_BASE      + 0x000c2200)
#define AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS                                  0x000c2200

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000000)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000000)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_RMSK                                                    0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_DISABLE_LPB_TX_CLKGATE_BMSK                             0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_DISABLE_LPB_TX_CLKGATE_SHFT                              0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_TXONLY_CLOCK_EDGE_BMSK                                   0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_TXONLY_CLOCK_EDGE_SHFT                                   0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_GATED_CLK_EN_BMSK                                        0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_GATED_CLK_EN_SHFT                                        0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_CLKBUF_EN_LANE1_BMSK                                     0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_CLKBUF_EN_LANE1_SHFT                                     0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_CLKBUF_EN_LANE0_BMSK                                     0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_CLKBUF_ENABLE_CLKBUF_EN_LANE0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_EMP_POST1_LVL_ADDR                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000004)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_EMP_POST1_LVL_OFFS                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000004)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_EMP_POST1_LVL_RMSK                                                 0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_EMP_POST1_LVL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_EMP_POST1_LVL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_EMP_POST1_LVL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_EMP_POST1_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_EMP_POST1_LVL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_EMP_POST1_LVL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_EMP_POST1_LVL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_EMP_POST1_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_EMP_POST1_LVL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_EMP_POST1_LVL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_EMP_POST1_LVL_EMP_POST1_LVL_BMSK                                   0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_EMP_POST1_LVL_EMP_POST1_LVL_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POST2_EMPH_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000008)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POST2_EMPH_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000008)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POST2_EMPH_RMSK                                                     0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POST2_EMPH_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POST2_EMPH_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POST2_EMPH_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POST2_EMPH_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POST2_EMPH_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POST2_EMPH_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POST2_EMPH_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POST2_EMPH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POST2_EMPH_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POST2_EMPH_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POST2_EMPH_POST2_EMPH_BMSK                                          0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POST2_EMPH_POST2_EMPH_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_ADDR                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000000c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_OFFS                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000000c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_RMSK                                               0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_TX_BOOST_LVL_DN_BMSK                               0x38
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_TX_BOOST_LVL_DN_SHFT                                0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_TX_BOOST_LVL_UP_BMSK                                0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_TX_BOOST_LVL_UP_SHFT                                0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_ADDR                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000010)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_OFFS                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000010)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_RMSK                                             0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_TX_IDLE_LVL_BMSK                                 0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_TX_IDLE_LVL_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000014)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000014)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_RMSK                                                       0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_TX_DRV_LVL_BMSK                                            0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_TX_DRV_LVL_SHFT                                             0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_ADDR                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000018)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_OFFS                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000018)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_RMSK                                                0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_TX_LVL_UPDATE_BMSK                                  0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_TX_LVL_UPDATE_SHFT                                   0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_TX_DRV_LVL_OFFSET_BMSK                               0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_TX_DRV_LVL_OFFSET_SHFT                               0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_ADDR                                             (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000001c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_OFFS                                             (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000001c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_RMSK                                                    0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_RESET_RSYNC_EN_MUX_BMSK                                 0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_RESET_RSYNC_EN_MUX_SHFT                                 0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_RESET_RSYNC_EN_BMSK                                     0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_RESET_RSYNC_EN_SHFT                                     0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_RESET_TSYNC_EN_MUX_BMSK                                 0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_RESET_TSYNC_EN_MUX_SHFT                                 0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_RESET_TSYNC_EN_BMSK                                     0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_TSYNC_EN_RESET_TSYNC_EN_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000020)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000020)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_RMSK                                                         0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_BOOST_EN_BMSK                                                0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_BOOST_EN_SHFT                                                 0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_SPARE_FOR_LDO_BMSK                                           0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_SPARE_FOR_LDO_SHFT                                            0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_PREEMPH_BMSK                                                 0x3e
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_PREEMPH_SHFT                                                  0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_PRE_EN_BMSK                                                   0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PRE_EMPH_PRE_EN_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_INTERFACE_SELECT_ADDR                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000024)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_INTERFACE_SELECT_OFFS                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000024)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_INTERFACE_SELECT_RMSK                                                  0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_INTERFACE_SELECT_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_INTERFACE_SELECT_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_INTERFACE_SELECT_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_INTERFACE_SELECT_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_INTERFACE_SELECT_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_INTERFACE_SELECT_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_INTERFACE_SELECT_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_INTERFACE_SELECT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_INTERFACE_SELECT_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_INTERFACE_SELECT_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_INTERFACE_SELECT_SEL_10B_8B_BMSK                                       0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_INTERFACE_SELECT_SEL_10B_8B_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000028)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000028)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_RMSK                                                           0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_TX_BAND_MUX_BMSK                                               0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_TX_BAND_MUX_SHFT                                               0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_TX_BAND_BMSK                                                   0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_BAND_TX_BAND_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SLEW_CNTL_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000002c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SLEW_CNTL_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000002c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SLEW_CNTL_RMSK                                                         0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SLEW_CNTL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SLEW_CNTL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SLEW_CNTL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SLEW_CNTL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SLEW_CNTL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SLEW_CNTL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SLEW_CNTL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SLEW_CNTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SLEW_CNTL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SLEW_CNTL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SLEW_CNTL_SLEW_CNTL_BMSK                                               0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SLEW_CNTL_SLEW_CNTL_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000030)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000030)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_RMSK                                                         0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_LPB_DIV10_SEL_DIG_BMSK                                       0x30
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_LPB_DIV10_SEL_DIG_SHFT                                        0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_LPB_CLK_DELAY_DIV10_TX1_BMSK                                  0xc
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_LPB_CLK_DELAY_DIV10_TX1_SHFT                                  0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_LPB_CLK_DELAY_DIV10_TX0_BMSK                                  0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG0_LPB_CLK_DELAY_DIV10_TX0_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000034)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000034)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_RMSK                                                         0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_BIST_RCLK_EN_BMSK                                            0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_BIST_RCLK_EN_SHFT                                             0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_TX_RCLK_LPB_EN_BMSK                                          0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_TX_RCLK_LPB_EN_SHFT                                           0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_SER_LPB_EN_BMSK                                              0x18
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_SER_LPB_EN_SHFT                                               0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_LPB_PATH_SEL_BMSK                                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_LPB_PATH_SEL_SHFT                                             0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_TRAN_LPB_DIV10_SEL_BMSK                                       0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG1_TRAN_LPB_DIV10_SEL_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000038)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000038)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_RMSK                                                         0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_LPB_DIV2_SEL_BMSK                                            0x30
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_LPB_DIV2_SEL_SHFT                                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_LPB_CLK_DELAY_DIV2_TX1_BMSK                                   0xc
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_LPB_CLK_DELAY_DIV2_TX1_SHFT                                   0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_LPB_CLK_DELAY_DIV2_TX0_BMSK                                   0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LPB_CFG2_LPB_CLK_DELAY_DIV2_TX0_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_ADDR                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000003c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_OFFS                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000003c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_RMSK                                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_RES_CODE_TX0_MUX_BMSK                                0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_RES_CODE_TX0_MUX_SHFT                                 0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_RES_CODE_TX0_BMSK                                    0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX_RES_CODE_TX0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_ADDR                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000040)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_OFFS                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000040)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_RMSK                                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_RES_CODE_TX1_MUX_BMSK                               0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_RES_CODE_TX1_MUX_SHFT                                0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_RES_CODE_TX1_BMSK                                   0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_TX1_RES_CODE_TX1_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_ADDR                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000044)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_OFFS                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000044)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_RMSK                                         0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_RES_CODE_LANE_OFFSET_TX0_BMSK                0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_RES_CODE_LANE_OFFSET_TX0_SHFT                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_ADDR                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000048)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_OFFS                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000048)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_RMSK                                         0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_RES_CODE_LANE_OFFSET_TX1_BMSK                0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_RES_CODE_LANE_OFFSET_TX1_SHFT                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_ADDR                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000004c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_OFFS                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000004c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_RMSK                                                 0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_BMSK                                  0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_SHFT                                  0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_EN_BMSK                                   0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_EN_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000050)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000050)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_DEBUG_CLK_SEL_BMSK                                      0xf0
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_DEBUG_CLK_SEL_SHFT                                       0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_DEBUGBUS_SEL_BMSK                                        0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS_SEL_DEBUGBUS_SEL_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000054)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000054)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_RMSK                                               0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_TX_EN_LANE1_BMSK                                   0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_TX_EN_LANE1_SHFT                                   0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_TX_EN_LANE0_BMSK                                   0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_TX_EN_LANE0_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000058)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000058)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_RMSK                                                    0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_MUX_BMSK                                 0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_MUX_SHFT                                  0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_MUX_BMSK                                  0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_MUX_SHFT                                  0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_DRVR_EN_BMSK                                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_DRVR_EN_SHFT                                             0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_BMSK                                      0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_SHFT                                      0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_BMSK                                      0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000005c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000005c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_RMSK                                                        0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_TX_POL_INV_LANE1_BMSK                                       0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_TX_POL_INV_LANE1_SHFT                                       0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_TX_POL_INV_LANE0_BMSK                                       0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TX_POL_INV_TX_POL_INV_LANE0_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_ADDR                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000060)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_OFFS                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000060)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_RMSK                                        0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_PAR_RATE_BMSK                               0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_PAR_RATE_SHFT                               0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_IDLE_EN_BMSK                                0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_IDLE_EN_SHFT                                0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_1_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000064)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_1_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000064)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_1_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_1_LANE_MODE1_BMSK                                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_1_LANE_MODE1_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_2_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000068)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_2_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000068)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_2_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_2_LANE_MODE2_BMSK                                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_MODE_2_LANE_MODE2_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL1_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000006c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL1_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000006c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL1_RMSK                                                         0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL1_ATB_SEL1_BMSK                                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL1_ATB_SEL1_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL2_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000070)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL2_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000070)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL2_RMSK                                                          0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL2_ATB_SEL2_BMSK                                                 0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_ATB_SEL2_ATB_SEL2_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_ADDR                                            (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000074)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_OFFS                                            (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000074)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_RMSK                                                   0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_RSYNC_MUX_BMSK                                         0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_RSYNC_MUX_SHFT                                         0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_RSYNC_BMSK                                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_RSYNC_SHFT                                             0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_TSYNC_MUX_BMSK                                         0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_TSYNC_MUX_SHFT                                         0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_TSYNC_BMSK                                             0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_RESET_GEN_MUXES_TSYNC_SHFT                                             0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_ADDR                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000078)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_OFFS                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000078)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_RMSK                                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_RSVD_BMSK                                            0xfe
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_RSVD_SHFT                                             0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_EMP_EN_BMSK                                           0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_EMP_EN_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_VMODE_CTRL1_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000007c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_VMODE_CTRL1_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000007c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_VMODE_CTRL1_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_VMODE_CTRL1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_VMODE_CTRL1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_VMODE_CTRL1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_VMODE_CTRL1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_VMODE_CTRL1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_VMODE_CTRL1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_VMODE_CTRL1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_VMODE_CTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_VMODE_CTRL1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_VMODE_CTRL1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_VMODE_CTRL1_VMODE_CTRL1_BMSK                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_VMODE_CTRL1_VMODE_CTRL1_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_ADDR                                            (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000080)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_OFFS                                            (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000080)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_RMSK                                                  0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_RSVD_BMSK                                             0xf8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_RSVD_SHFT                                              0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_LANE_PWRDN_B_BMSK                                      0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_LANE_PWRDN_B_SHFT                                      0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_RCLK_OUT_INV_BMSK                                      0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_RCLK_OUT_INV_SHFT                                      0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_TCLK_OUT_INV_BMSK                                      0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LANE_DIG_CONFIG_TCLK_OUT_INV_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000084)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000084)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_LDO_VREG_LVL_BMSK                                          0xc0
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_LDO_VREG_LVL_SHFT                                           0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_LDO_BIAS_SEL_BMSK                                          0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_LDO_BIAS_SEL_SHFT                                           0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_LDO_VREF_SEL_BMSK                                          0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_LDO_VREF_SEL_SHFT                                           0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_LDO_HIGHZ_BMSK                                              0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_LDO_HIGHZ_SHFT                                              0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_LDO_TEST_EN_BMSK                                            0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_LDO_TEST_EN_SHFT                                            0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_LDO_EN_BMSK                                                 0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_LDO_CONFIG_LDO_EN_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DIG_BKUP_CTRL_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000088)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DIG_BKUP_CTRL_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000088)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DIG_BKUP_CTRL_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DIG_BKUP_CTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DIG_BKUP_CTRL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DIG_BKUP_CTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DIG_BKUP_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DIG_BKUP_CTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DIG_BKUP_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DIG_BKUP_CTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DIG_BKUP_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DIG_BKUP_CTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DIG_BKUP_CTRL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DIG_BKUP_CTRL_RSVD_BMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DIG_BKUP_CTRL_RSVD_SHFT                                                0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS0_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000008c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS0_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000008c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS0_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS0_DEBUG_BUS_7_0_BMSK                                         0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS0_DEBUG_BUS_7_0_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS1_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000090)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS1_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000090)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS1_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS1_DEBUG_BUS_15_8_BMSK                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS1_DEBUG_BUS_15_8_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS2_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000094)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS2_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000094)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS2_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS2_DEBUG_BUS_23_16_BMSK                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS2_DEBUG_BUS_23_16_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS3_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000098)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS3_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000098)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS3_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS3_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS3_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS3_DEBUG_BUS_31_24_BMSK                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_DEBUG_BUS3_DEBUG_BUS_31_24_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_READ_OFFSETCODE_ADDR                                            (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000009c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_READ_OFFSETCODE_OFFS                                            (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000009c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_READ_OFFSETCODE_RMSK                                                  0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_READ_OFFSETCODE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_READ_OFFSETCODE_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_READ_OFFSETCODE_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_READ_OFFSETCODE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_READ_OFFSETCODE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_READ_OFFSETCODE_READ_OFFSETCODE_STATUS_BMSK                           0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX0_READ_OFFSETCODE_READ_OFFSETCODE_STATUS_SHFT                            0x0

/*----------------------------------------------------------------------------
 * MODULE: AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE
 *--------------------------------------------------------------------------*/

#define AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE                                       (MDSS_BASE      + 0x000c2600)
#define AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS                                  0x000c2600

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000000)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000000)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_RMSK                                                    0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_DISABLE_LPB_TX_CLKGATE_BMSK                             0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_DISABLE_LPB_TX_CLKGATE_SHFT                              0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_TXONLY_CLOCK_EDGE_BMSK                                   0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_TXONLY_CLOCK_EDGE_SHFT                                   0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_GATED_CLK_EN_BMSK                                        0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_GATED_CLK_EN_SHFT                                        0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_CLKBUF_EN_LANE1_BMSK                                     0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_CLKBUF_EN_LANE1_SHFT                                     0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_CLKBUF_EN_LANE0_BMSK                                     0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_CLKBUF_ENABLE_CLKBUF_EN_LANE0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_EMP_POST1_LVL_ADDR                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000004)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_EMP_POST1_LVL_OFFS                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000004)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_EMP_POST1_LVL_RMSK                                                 0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_EMP_POST1_LVL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_EMP_POST1_LVL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_EMP_POST1_LVL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_EMP_POST1_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_EMP_POST1_LVL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_EMP_POST1_LVL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_EMP_POST1_LVL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_EMP_POST1_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_EMP_POST1_LVL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_EMP_POST1_LVL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_EMP_POST1_LVL_EMP_POST1_LVL_BMSK                                   0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_EMP_POST1_LVL_EMP_POST1_LVL_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POST2_EMPH_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000008)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POST2_EMPH_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000008)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POST2_EMPH_RMSK                                                     0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POST2_EMPH_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POST2_EMPH_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POST2_EMPH_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POST2_EMPH_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POST2_EMPH_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POST2_EMPH_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POST2_EMPH_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POST2_EMPH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POST2_EMPH_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POST2_EMPH_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POST2_EMPH_POST2_EMPH_BMSK                                          0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POST2_EMPH_POST2_EMPH_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_ADDR                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000000c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_OFFS                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000000c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_RMSK                                               0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_TX_BOOST_LVL_DN_BMSK                               0x38
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_TX_BOOST_LVL_DN_SHFT                                0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_TX_BOOST_LVL_UP_BMSK                                0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_TX_BOOST_LVL_UP_SHFT                                0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_ADDR                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000010)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_OFFS                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000010)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_RMSK                                             0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_TX_IDLE_LVL_BMSK                                 0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_TX_IDLE_LVL_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000014)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000014)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_RMSK                                                       0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_TX_DRV_LVL_BMSK                                            0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_TX_DRV_LVL_SHFT                                             0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_ADDR                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000018)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_OFFS                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000018)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_RMSK                                                0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_TX_LVL_UPDATE_BMSK                                  0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_TX_LVL_UPDATE_SHFT                                   0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_TX_DRV_LVL_OFFSET_BMSK                               0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_TX_DRV_LVL_OFFSET_SHFT                               0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_ADDR                                             (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000001c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_OFFS                                             (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000001c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_RMSK                                                    0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_RESET_RSYNC_EN_MUX_BMSK                                 0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_RESET_RSYNC_EN_MUX_SHFT                                 0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_RESET_RSYNC_EN_BMSK                                     0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_RESET_RSYNC_EN_SHFT                                     0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_RESET_TSYNC_EN_MUX_BMSK                                 0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_RESET_TSYNC_EN_MUX_SHFT                                 0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_RESET_TSYNC_EN_BMSK                                     0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_TSYNC_EN_RESET_TSYNC_EN_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000020)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000020)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_RMSK                                                         0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_BOOST_EN_BMSK                                                0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_BOOST_EN_SHFT                                                 0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_SPARE_FOR_LDO_BMSK                                           0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_SPARE_FOR_LDO_SHFT                                            0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_PREEMPH_BMSK                                                 0x3e
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_PREEMPH_SHFT                                                  0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_PRE_EN_BMSK                                                   0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PRE_EMPH_PRE_EN_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_INTERFACE_SELECT_ADDR                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000024)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_INTERFACE_SELECT_OFFS                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000024)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_INTERFACE_SELECT_RMSK                                                  0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_INTERFACE_SELECT_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_INTERFACE_SELECT_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_INTERFACE_SELECT_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_INTERFACE_SELECT_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_INTERFACE_SELECT_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_INTERFACE_SELECT_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_INTERFACE_SELECT_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_INTERFACE_SELECT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_INTERFACE_SELECT_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_INTERFACE_SELECT_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_INTERFACE_SELECT_SEL_10B_8B_BMSK                                       0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_INTERFACE_SELECT_SEL_10B_8B_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000028)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000028)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_RMSK                                                           0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_TX_BAND_MUX_BMSK                                               0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_TX_BAND_MUX_SHFT                                               0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_TX_BAND_BMSK                                                   0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_BAND_TX_BAND_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SLEW_CNTL_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000002c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SLEW_CNTL_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000002c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SLEW_CNTL_RMSK                                                         0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SLEW_CNTL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SLEW_CNTL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SLEW_CNTL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SLEW_CNTL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SLEW_CNTL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SLEW_CNTL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SLEW_CNTL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SLEW_CNTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SLEW_CNTL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SLEW_CNTL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SLEW_CNTL_SLEW_CNTL_BMSK                                               0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SLEW_CNTL_SLEW_CNTL_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000030)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000030)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_RMSK                                                         0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_LPB_DIV10_SEL_DIG_BMSK                                       0x30
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_LPB_DIV10_SEL_DIG_SHFT                                        0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_LPB_CLK_DELAY_DIV10_TX1_BMSK                                  0xc
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_LPB_CLK_DELAY_DIV10_TX1_SHFT                                  0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_LPB_CLK_DELAY_DIV10_TX0_BMSK                                  0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG0_LPB_CLK_DELAY_DIV10_TX0_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000034)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000034)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_RMSK                                                         0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_BIST_RCLK_EN_BMSK                                            0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_BIST_RCLK_EN_SHFT                                             0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_TX_RCLK_LPB_EN_BMSK                                          0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_TX_RCLK_LPB_EN_SHFT                                           0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_SER_LPB_EN_BMSK                                              0x18
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_SER_LPB_EN_SHFT                                               0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_LPB_PATH_SEL_BMSK                                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_LPB_PATH_SEL_SHFT                                             0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_TRAN_LPB_DIV10_SEL_BMSK                                       0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG1_TRAN_LPB_DIV10_SEL_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000038)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000038)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_RMSK                                                         0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_LPB_DIV2_SEL_BMSK                                            0x30
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_LPB_DIV2_SEL_SHFT                                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_LPB_CLK_DELAY_DIV2_TX1_BMSK                                   0xc
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_LPB_CLK_DELAY_DIV2_TX1_SHFT                                   0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_LPB_CLK_DELAY_DIV2_TX0_BMSK                                   0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LPB_CFG2_LPB_CLK_DELAY_DIV2_TX0_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_ADDR                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000003c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_OFFS                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000003c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_RMSK                                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_RES_CODE_TX0_MUX_BMSK                                0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_RES_CODE_TX0_MUX_SHFT                                 0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_RES_CODE_TX0_BMSK                                    0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX_RES_CODE_TX0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_ADDR                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000040)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_OFFS                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000040)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_RMSK                                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_RES_CODE_TX1_MUX_BMSK                               0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_RES_CODE_TX1_MUX_SHFT                                0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_RES_CODE_TX1_BMSK                                   0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_TX1_RES_CODE_TX1_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_ADDR                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000044)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_OFFS                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000044)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_RMSK                                         0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_RES_CODE_LANE_OFFSET_TX0_BMSK                0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_RES_CODE_LANE_OFFSET_TX0_SHFT                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_ADDR                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000048)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_OFFS                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000048)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_RMSK                                         0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_RES_CODE_LANE_OFFSET_TX1_BMSK                0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_RES_CODE_LANE_OFFSET_TX1_SHFT                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_ADDR                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000004c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_OFFS                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000004c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_RMSK                                                 0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_BMSK                                  0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_SHFT                                  0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_EN_BMSK                                   0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_EN_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000050)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000050)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_DEBUG_CLK_SEL_BMSK                                      0xf0
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_DEBUG_CLK_SEL_SHFT                                       0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_DEBUGBUS_SEL_BMSK                                        0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS_SEL_DEBUGBUS_SEL_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000054)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000054)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_RMSK                                               0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_TX_EN_LANE1_BMSK                                   0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_TX_EN_LANE1_SHFT                                   0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_TX_EN_LANE0_BMSK                                   0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_TX_EN_LANE0_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000058)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000058)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_RMSK                                                    0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_MUX_BMSK                                 0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_MUX_SHFT                                  0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_MUX_BMSK                                  0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_MUX_SHFT                                  0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_DRVR_EN_BMSK                                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_DRVR_EN_SHFT                                             0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_BMSK                                      0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_SHFT                                      0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_BMSK                                      0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000005c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000005c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_RMSK                                                        0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_TX_POL_INV_LANE1_BMSK                                       0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_TX_POL_INV_LANE1_SHFT                                       0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_TX_POL_INV_LANE0_BMSK                                       0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TX_POL_INV_TX_POL_INV_LANE0_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_ADDR                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000060)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_OFFS                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000060)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_RMSK                                        0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_PAR_RATE_BMSK                               0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_PAR_RATE_SHFT                               0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_IDLE_EN_BMSK                                0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_IDLE_EN_SHFT                                0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_1_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000064)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_1_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000064)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_1_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_1_LANE_MODE1_BMSK                                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_1_LANE_MODE1_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_2_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000068)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_2_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000068)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_2_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_2_LANE_MODE2_BMSK                                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_MODE_2_LANE_MODE2_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL1_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000006c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL1_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000006c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL1_RMSK                                                         0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL1_ATB_SEL1_BMSK                                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL1_ATB_SEL1_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL2_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000070)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL2_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000070)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL2_RMSK                                                          0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL2_ATB_SEL2_BMSK                                                 0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_ATB_SEL2_ATB_SEL2_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_ADDR                                            (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000074)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_OFFS                                            (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000074)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_RMSK                                                   0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_RSYNC_MUX_BMSK                                         0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_RSYNC_MUX_SHFT                                         0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_RSYNC_BMSK                                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_RSYNC_SHFT                                             0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_TSYNC_MUX_BMSK                                         0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_TSYNC_MUX_SHFT                                         0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_TSYNC_BMSK                                             0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_RESET_GEN_MUXES_TSYNC_SHFT                                             0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_ADDR                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000078)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_OFFS                                           (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000078)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_RMSK                                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_RSVD_BMSK                                            0xfe
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_RSVD_SHFT                                             0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_EMP_EN_BMSK                                           0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_EMP_EN_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_VMODE_CTRL1_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000007c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_VMODE_CTRL1_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000007c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_VMODE_CTRL1_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_VMODE_CTRL1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_VMODE_CTRL1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_VMODE_CTRL1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_VMODE_CTRL1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_VMODE_CTRL1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_VMODE_CTRL1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_VMODE_CTRL1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_VMODE_CTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_VMODE_CTRL1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_VMODE_CTRL1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_VMODE_CTRL1_VMODE_CTRL1_BMSK                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_VMODE_CTRL1_VMODE_CTRL1_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_ADDR                                            (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000080)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_OFFS                                            (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000080)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_RMSK                                                  0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_RSVD_BMSK                                             0xf8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_RSVD_SHFT                                              0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_LANE_PWRDN_B_BMSK                                      0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_LANE_PWRDN_B_SHFT                                      0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_RCLK_OUT_INV_BMSK                                      0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_RCLK_OUT_INV_SHFT                                      0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_TCLK_OUT_INV_BMSK                                      0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LANE_DIG_CONFIG_TCLK_OUT_INV_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000084)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000084)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_LDO_VREG_LVL_BMSK                                          0xc0
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_LDO_VREG_LVL_SHFT                                           0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_LDO_BIAS_SEL_BMSK                                          0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_LDO_BIAS_SEL_SHFT                                           0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_LDO_VREF_SEL_BMSK                                          0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_LDO_VREF_SEL_SHFT                                           0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_LDO_HIGHZ_BMSK                                              0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_LDO_HIGHZ_SHFT                                              0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_LDO_TEST_EN_BMSK                                            0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_LDO_TEST_EN_SHFT                                            0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_LDO_EN_BMSK                                                 0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_LDO_CONFIG_LDO_EN_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DIG_BKUP_CTRL_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000088)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DIG_BKUP_CTRL_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000088)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DIG_BKUP_CTRL_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DIG_BKUP_CTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DIG_BKUP_CTRL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DIG_BKUP_CTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DIG_BKUP_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DIG_BKUP_CTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DIG_BKUP_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DIG_BKUP_CTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DIG_BKUP_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DIG_BKUP_CTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DIG_BKUP_CTRL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DIG_BKUP_CTRL_RSVD_BMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DIG_BKUP_CTRL_RSVD_SHFT                                                0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS0_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000008c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS0_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000008c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS0_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS0_DEBUG_BUS_7_0_BMSK                                         0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS0_DEBUG_BUS_7_0_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS1_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000090)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS1_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000090)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS1_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS1_DEBUG_BUS_15_8_BMSK                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS1_DEBUG_BUS_15_8_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS2_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000094)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS2_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000094)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS2_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS2_DEBUG_BUS_23_16_BMSK                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS2_DEBUG_BUS_23_16_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS3_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000098)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS3_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000098)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS3_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS3_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS3_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS3_DEBUG_BUS_31_24_BMSK                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_DEBUG_BUS3_DEBUG_BUS_31_24_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_READ_OFFSETCODE_ADDR                                            (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000009c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_READ_OFFSETCODE_OFFS                                            (AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000009c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_READ_OFFSETCODE_RMSK                                                  0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_READ_OFFSETCODE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_READ_OFFSETCODE_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_READ_OFFSETCODE_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_READ_OFFSETCODE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_READ_OFFSETCODE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_READ_OFFSETCODE_READ_OFFSETCODE_STATUS_BMSK                           0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_LANE_TX1_READ_OFFSETCODE_READ_OFFSETCODE_STATUS_SHFT                            0x0

/*----------------------------------------------------------------------------
 * MODULE: AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY
 *--------------------------------------------------------------------------*/

#define AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE                                                       (MDSS_BASE      + 0x000c2a00)
#define AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS                                                  0x000c2a00

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID0_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000000)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID0_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000000)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID0_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID0_STEP_7_0_BMSK                                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID0_STEP_7_0_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID1_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000004)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID1_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000004)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID1_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID1_STEP_15_8_BMSK                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID1_STEP_15_8_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID2_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000008)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID2_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000008)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID2_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID2_MINOR_7_0_BMSK                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID2_MINOR_7_0_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID3_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000000c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID3_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000000c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID3_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID3_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID3_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID3_MAJOR_BMSK                                              0xf0
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID3_MAJOR_SHFT                                               0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID3_MINOR_11_8_BMSK                                          0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_REVISION_ID3_MINOR_11_8_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_ADDR                                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000010)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_OFFS                                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000010)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_RMSK                                                             0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_DP_CFG_SPARE_BMSK                                                0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_DP_CFG_SPARE_SHFT                                                 0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_AUX_RESET_BMSK                                                   0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_AUX_RESET_SHFT                                                    0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_CORE_RESET_TSYNC_BMSK                                            0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_CORE_RESET_TSYNC_SHFT                                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_PLL_START_BMSK                                                    0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_PLL_START_SHFT                                                    0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_PLL_RESET_BMSK                                                    0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_PLL_RESET_SHFT                                                    0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_SW_RESET_BMSK                                                     0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_SW_RESET_SHFT                                                     0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_RETIMING_ENABLE_BMSK                                              0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_RETIMING_ENABLE_SHFT                                              0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_ADDR                                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000014)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_OFFS                                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000014)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_RMSK                                                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_C_READY_MUX_BMSK                                               0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_C_READY_MUX_SHFT                                                0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_SW_C_READY_BMSK                                                0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_SW_C_READY_SHFT                                                 0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_TCLK_LINKCLK_SEL_BMSK                                          0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_TCLK_LINKCLK_SEL_SHFT                                           0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_DISABLE_CGC_EN_BMSK                                            0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_DISABLE_CGC_EN_SHFT                                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_RT_BUFFER_LANE3_EN_BMSK                                         0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_RT_BUFFER_LANE3_EN_SHFT                                         0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_RT_BUFFER_LANE2_EN_BMSK                                         0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_RT_BUFFER_LANE2_EN_SHFT                                         0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_RT_BUFFER_LANE1_EN_BMSK                                         0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_RT_BUFFER_LANE1_EN_SHFT                                         0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_RT_BUFFER_LANE0_EN_BMSK                                         0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_1_RT_BUFFER_LANE0_EN_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_ADDR                                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000018)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_OFFS                                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000018)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_RMSK                                                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_DEBUG_CLK_DIV_BMSK                                             0xf0
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_DEBUG_CLK_DIV_SHFT                                              0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_DEBUG_CLK_SEL_BMSK                                              0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_CFG_2_DEBUG_CLK_SEL_SHFT                                              0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000001c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000001c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_SPARE_PWRDN_B_BMSK                                            0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_SPARE_PWRDN_B_SHFT                                             0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_DP_CLAMP_EN_B_BMSK                                            0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_DP_CLAMP_EN_B_SHFT                                             0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_PLL_PWRDN_B_BMSK                                              0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_PLL_PWRDN_B_SHFT                                               0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_LANE_2_3_PWRDN_B_BMSK                                         0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_LANE_2_3_PWRDN_B_SHFT                                          0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_LANE_0_1_PWRDN_B_BMSK                                          0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_LANE_0_1_PWRDN_B_SHFT                                          0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_AUX_PWRDN_B_BMSK                                               0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_AUX_PWRDN_B_SHFT                                               0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_PSR_PWRDN_BMSK                                                 0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_PSR_PWRDN_SHFT                                                 0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_PWRDN_B_BMSK                                                   0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_PD_CTL_PWRDN_B_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_ADDR                                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000020)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_OFFS                                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000020)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_RMSK                                                            0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_REFGEN_REQ_BMSK                                                 0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_REFGEN_REQ_SHFT                                                  0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_RETIME_BUFFER_SIZE_BMSK                                         0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_RETIME_BUFFER_SIZE_SHFT                                          0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_LINK_CLOCK_SEL_MUX_BMSK                                         0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_LINK_CLOCK_SEL_MUX_SHFT                                          0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_LINK_CLOCK_SEL_BMSK                                             0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_LINK_CLOCK_SEL_SHFT                                              0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_PAR_RATE_BMSK                                                    0xc
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_PAR_RATE_SHFT                                                    0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_TX_BAND_BMSK                                                     0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MODE_TX_BAND_SHFT                                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000024)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000024)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_RMSK                                                         0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_AUX_FORCE_TX_EN_BMSK                                         0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_AUX_FORCE_TX_EN_SHFT                                         0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_AUX_BYPASS_BMSK                                              0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_AUX_BYPASS_SHFT                                              0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_RSVD_BMSK                                                    0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG0_RSVD_SHFT                                                    0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG1_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000028)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG1_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000028)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG1_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG1_AUX_DCTRL_7_0_BMSK                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG1_AUX_DCTRL_7_0_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG2_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000002c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG2_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000002c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG2_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG2_AUX_DCTRL_15_8_BMSK                                         0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG2_AUX_DCTRL_15_8_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000030)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000030)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_AUX_FORCE_RX_EN_BMSK                                        0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_AUX_FORCE_RX_EN_SHFT                                         0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_AUX_TX_PRECHARGE_BMSK                                       0x70
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_AUX_TX_PRECHARGE_SHFT                                        0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_AUX_PARALLEL_LBK_BMSK                                        0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_AUX_PARALLEL_LBK_SHFT                                        0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_AUX_BYPASS_MANCH_LBK_BMSK                                    0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_AUX_BYPASS_MANCH_LBK_SHFT                                    0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_AUX_SERIAL_LBK_BMSK                                          0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_AUX_SERIAL_LBK_SHFT                                          0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_AUX_NEAREND_LBK_BMSK                                         0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG3_AUX_NEAREND_LBK_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG4_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000034)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG4_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000034)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG4_RMSK                                                        0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG4_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG4_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG4_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG4_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG4_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG4_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG4_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG4_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG4_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG4_AUX_TX_MANCH_HALFCYC_BMSK                                   0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG4_AUX_TX_MANCH_HALFCYC_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG5_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000038)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG5_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000038)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG5_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG5_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG5_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG5_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG5_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG5_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG5_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG5_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG5_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG5_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG5_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG5_AUX_RX_MANCH_TWOCYC_BMSK                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG5_AUX_RX_MANCH_TWOCYC_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG6_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000003c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG6_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000003c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG6_RMSK                                                        0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG6_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG6_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG6_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG6_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG6_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG6_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG6_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG6_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG6_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG6_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG6_AUX_RX_MANCH_HALFCYC_BMSK                                   0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG6_AUX_RX_MANCH_HALFCYC_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG7_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000040)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG7_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000040)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG7_RMSK                                                         0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG7_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG7_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG7_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG7_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG7_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG7_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG7_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG7_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG7_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG7_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG7_AUX_RX_MANCH_CYCJITTER_BMSK                                  0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG7_AUX_RX_MANCH_CYCJITTER_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000044)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000044)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_AUX_TX_PREAMBLE_BMSK                                        0xf0
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_AUX_TX_PREAMBLE_SHFT                                         0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_AUX_RX_PREAMBLE_BMSK                                         0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG8_AUX_RX_PREAMBLE_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_ADDR                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000048)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_OFFS                                                  (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000048)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_OVERRIDE_TWOCYC_BMSK                                        0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_OVERRIDE_TWOCYC_SHFT                                         0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_OVERRIDE_HALFCYC_BMSK                                       0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_OVERRIDE_HALFCYC_SHFT                                        0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_OVERRIDE_AUX_TIMING_BMSK                                    0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_OVERRIDE_AUX_TIMING_SHFT                                     0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_AUX_RX_CFG_SPARE_BMSK                                       0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_AUX_RX_CFG_SPARE_SHFT                                        0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_AUX_RX_ZERO_IDLE_CNT_BMSK                                    0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG9_AUX_RX_ZERO_IDLE_CNT_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000004c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000004c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_RMSK                                                       0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_AUX_RX_START_DEBOUNCE_ENA_BMSK                             0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_AUX_RX_START_DEBOUNCE_ENA_SHFT                              0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_AUX_RXOUT_DEBOUNCE_ENA_BMSK                                0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_AUX_RXOUT_DEBOUNCE_ENA_SHFT                                 0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_AUX_DBOUNCE_SPARE_BMSK                                      0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG10_AUX_DBOUNCE_SPARE_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000050)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000050)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_RMSK                                                        0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_DLY_AUX_RX_VALID_BMSK                                       0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_DLY_AUX_RX_VALID_SHFT                                       0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_USE_AUXRX_GEN1_BMSK                                         0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG11_USE_AUXRX_GEN1_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG12_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000054)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG12_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000054)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG12_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG12_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG12_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG12_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG12_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG12_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG12_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG12_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG12_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG12_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG12_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG12_AUX_DCTRL_23_16_BMSK                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_CFG12_AUX_DCTRL_23_16_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000058)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000058)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_RMSK                                              0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_TX_REQ_ERR_MASK_BMSK                          0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_TX_REQ_ERR_MASK_SHFT                           0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_ALIGN_ERR_MASK_BMSK                         0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_ALIGN_ERR_MASK_SHFT                         0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_SYNC_ERR_MASK_BMSK                          0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_SYNC_ERR_MASK_SHFT                          0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_DEC_ERR_MASK_BMSK                           0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_DEC_ERR_MASK_SHFT                           0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_STOP_ERR_MASK_BMSK                          0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_STOP_ERR_MASK_SHFT                          0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_ADDR                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000005c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_OFFS                                       (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000005c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_RMSK                                             0x9f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_GLOBE_REQ_CLR_CMD_BMSK                       0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_GLOBE_REQ_CLR_CMD_SHFT                        0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_TX_REQ_ERR_CLR_BMSK                          0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_TX_REQ_ERR_CLR_SHFT                           0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_ALIGN_ERR_CLR_BMSK                         0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_ALIGN_ERR_CLR_SHFT                         0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_SYNC_ERR_CLR_BMSK                          0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_SYNC_ERR_CLR_SHFT                          0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_DEC_ERR_CLR_BMSK                           0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_DEC_ERR_CLR_SHFT                           0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_STOP_ERR_CLR_BMSK                          0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_STOP_ERR_CLR_SHFT                          0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_ADDR                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000060)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_OFFS                                              (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000060)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_AUX_BIST_MODE_BMSK                                      0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_AUX_BIST_MODE_SHFT                                       0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_AUX_BIST_SEL_BMSK                                       0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_AUX_BIST_SEL_SHFT                                        0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_AUX_TX_PATGEN_EN_BMSK                                   0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_AUX_TX_PATGEN_EN_SHFT                                    0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_AUX_TX_FIXPAT_BMSK                                      0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_AUX_TX_FIXPAT_SHFT                                       0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_EN_BMSK                                  0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_EN_SHFT                                  0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_GEN_SHORT_BMSK                           0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_GEN_SHORT_SHFT                           0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_ERR_EN_BMSK                              0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_ERR_EN_SHFT                              0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_CLR_ERROR_COUNT_BMSK                     0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_CLR_ERROR_COUNT_SHFT                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_SEED_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000064)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_SEED_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000064)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_SEED_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_SEED_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_SEED_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_SEED_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_SEED_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_SEED_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_SEED_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_SEED_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_SEED_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_SEED_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_SEED_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_SEED_AUX_BIST_PRBS_SEED_BMSK                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_SEED_AUX_BIST_PRBS_SEED_SHFT                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_POLY_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000068)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_POLY_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000068)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_POLY_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_POLY_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_POLY_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_POLY_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_POLY_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_POLY_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_POLY_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_POLY_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_POLY_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_POLY_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_POLY_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_POLY_AUX_BIST_PRBS_POLY_BMSK                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_PRBS_POLY_AUX_BIST_PRBS_POLY_SHFT                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_ADDR                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000006c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_OFFS                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000006c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_RMSK                                         0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_AUX_TX_PROG_PAT_16B_7_0_BMSK                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_AUX_TX_PROG_PAT_16B_7_0_SHFT                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_ADDR                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000070)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_OFFS                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000070)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_RMSK                                         0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_AUX_TX_PROG_PAT_16B_15_8_BMSK                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_AUX_TX_PROG_PAT_16B_15_8_SHFT                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_ADDR                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000074)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_OFFS                                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000074)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_RMSK                                                          0xb
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_FORCE_CLKBUF_EN_BMSK                                          0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_FORCE_CLKBUF_EN_SHFT                                          0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_VCO_DIV_CLK_SEL_BMSK                                          0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_VCO_DIV_VCO_DIV_CLK_SEL_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000078)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000078)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_RMSK                                                      0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_SW_C_EXT_CLKBUF_EN_MUX_BMSK                               0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_SW_C_EXT_CLKBUF_EN_MUX_SHFT                                0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_SW_C_EXT_CLKBUF_EN_BMSK                                   0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_SW_C_EXT_CLKBUF_EN_SHFT                                    0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_SW_TSYNC_DONE_MUX_BMSK                                     0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_SW_TSYNC_DONE_MUX_SHFT                                     0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_SW_TSYNC_DONE_BMSK                                         0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_SW_TSYNC_DONE_SHFT                                         0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_SW_EXT_TSYNC_MUX_BMSK                                      0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_SW_EXT_TSYNC_MUX_SHFT                                      0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_SW_EXT_TSYNC_BMSK                                          0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TSYNC_OVRD_SW_EXT_TSYNC_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_ADDR                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000007c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_OFFS                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000007c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_RMSK                                                 0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_L0_CORE_TXCLK_EN_BMSK                                0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_L0_CORE_TXCLK_EN_SHFT                                0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_L0_CORE_PLL_EN_BMSK                                  0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_LANE_CTL_L0_CORE_PLL_EN_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_ADDR                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000080)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_OFFS                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000080)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_RMSK                                               0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TX_HDR_PRBS_SEL_BMSK                       0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TX_HDR_PRBS_SEL_SHFT                        0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TCLK_SEL_BMSK                              0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TCLK_SEL_SHFT                               0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TX_GEN_EN_BMSK                             0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TX_GEN_EN_SHFT                              0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_RX_PRBS_CHK_EN_BMSK                         0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_RX_PRBS_CHK_EN_SHFT                         0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_RX_PRBS_GEN_SHORT_BMSK                      0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_RX_PRBS_GEN_SHORT_SHFT                      0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_ERROR_INJECT_BMSK                           0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_ERROR_INJECT_SHFT                           0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_ERROR_CLEAR_BMSK                            0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_ERROR_CLEAR_SHFT                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_ADDR                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000084)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_OFFS                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000084)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_RMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_RX_RESET_PCS_BMSK                          0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_RX_RESET_PCS_SHFT                           0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_TX_RESET_PCS_BMSK                          0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_TX_RESET_PCS_SHFT                           0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_MODE_BMSK                                  0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_MODE_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG2_ADDR                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000088)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG2_OFFS                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000088)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG2_RMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG2_L0_HEADER_PAT_7_0_BMSK                             0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG2_L0_HEADER_PAT_7_0_SHFT                              0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_ADDR                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000008c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_OFFS                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000008c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_RMSK                                                0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_L0_BIST_TX_MASK_BMSK                                0xc
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_L0_BIST_TX_MASK_SHFT                                0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_L0_HEADER_PAT_9_8_BMSK                              0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_CFG3_L0_HEADER_PAT_9_8_SHFT                              0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_ADDR                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000090)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_OFFS                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000090)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_RMSK                                         0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_L0_PRBS_SEED_7_0_BMSK                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_L0_PRBS_SEED_7_0_SHFT                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_ADDR                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000094)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_OFFS                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000094)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_RMSK                                          0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_L0_PRBS_SEED_9_8_BMSK                         0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_L0_PRBS_SEED_9_8_SHFT                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_ADDR                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000098)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_OFFS                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000098)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_RMSK                                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_L0_PRBS_POLY_7_0_BMSK                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_L0_PRBS_POLY_7_0_SHFT                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_ADDR                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000009c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_OFFS                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000009c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_RMSK                                            0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_L0_PRBS_POLY_9_8_BMSK                           0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_L0_PRBS_POLY_9_8_SHFT                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_ADDR                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000a0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_OFFS                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000a0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_RMSK                                                 0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_L1_CORE_TXCLK_EN_BMSK                                0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_L1_CORE_TXCLK_EN_SHFT                                0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_L1_CORE_PLL_EN_BMSK                                  0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_LANE_CTL_L1_CORE_PLL_EN_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_ADDR                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000a4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_OFFS                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000a4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_RMSK                                               0x7f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TX_HDR_PRBS_SEL_BMSK                       0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TX_HDR_PRBS_SEL_SHFT                        0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TCLK_SEL_BMSK                              0x20
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TCLK_SEL_SHFT                               0x5
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TX_GEN_EN_BMSK                             0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TX_GEN_EN_SHFT                              0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_RX_PRBS_CHK_EN_BMSK                         0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_RX_PRBS_CHK_EN_SHFT                         0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_RX_PRBS_GEN_SHORT_BMSK                      0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_RX_PRBS_GEN_SHORT_SHFT                      0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_ERROR_INJECT_BMSK                           0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_ERROR_INJECT_SHFT                           0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_ERROR_CLEAR_BMSK                            0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_ERROR_CLEAR_SHFT                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_ADDR                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000a8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_OFFS                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000a8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_RMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_RX_RESET_PCS_BMSK                          0x80
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_RX_RESET_PCS_SHFT                           0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_TX_RESET_PCS_BMSK                          0x40
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_TX_RESET_PCS_SHFT                           0x6
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_MODE_BMSK                                  0x3f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_MODE_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG2_ADDR                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000ac)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG2_OFFS                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000ac)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG2_RMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG2_L1_HEADER_PAT_7_0_BMSK                             0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG2_L1_HEADER_PAT_7_0_SHFT                              0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_ADDR                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000b0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_OFFS                                         (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000b0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_RMSK                                                0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_L1_BIST_TX_MASK_BMSK                                0xc
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_L1_BIST_TX_MASK_SHFT                                0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_L1_HEADER_PAT_9_8_BMSK                              0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_CFG3_L1_HEADER_PAT_9_8_SHFT                              0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_ADDR                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000b4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_OFFS                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000b4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_RMSK                                         0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_L1_PRBS_SEED_7_0_BMSK                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_L1_PRBS_SEED_7_0_SHFT                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_ADDR                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000b8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_OFFS                                   (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000b8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_RMSK                                          0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_L1_PRBS_SEED_9_8_BMSK                         0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_L1_PRBS_SEED_9_8_SHFT                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_ADDR                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000bc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_OFFS                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000bc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_RMSK                                           0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_L1_PRBS_POLY_7_0_BMSK                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_L1_PRBS_POLY_7_0_SHFT                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_ADDR                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000c0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_OFFS                                     (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000c0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_RMSK                                            0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_L1_PRBS_POLY_9_8_BMSK                           0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_L1_PRBS_POLY_9_8_SHFT                           0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_ADDR                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000c4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_OFFS                                                 (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000c4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_RMSK                                                        0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_MISR_CLEAR_BMSK                                             0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_MISR_CLEAR_SHFT                                             0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_MISR_ENABLE_BMSK                                            0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_CTRL_MISR_ENABLE_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS_SEL_ADDR                                             (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000c8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS_SEL_OFFS                                             (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000c8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS_SEL_RMSK                                                   0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS_SEL_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS_SEL_DEBUG_BUS_SEL_BMSK                                     0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS_SEL_DEBUG_BUS_SEL_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE0_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000cc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE0_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000cc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE0_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE0_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE0_EDPPHY_SPARE_7_0_BMSK                                         0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE0_EDPPHY_SPARE_7_0_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE1_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000d0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE1_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000d0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE1_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE1_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE1_EDPPHY_SPARE_15_8_BMSK                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE1_EDPPHY_SPARE_15_8_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE2_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000d4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE2_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000d4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE2_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE2_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE2_EDPPHY_SPARE_23_16_BMSK                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE2_EDPPHY_SPARE_23_16_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE3_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000d8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE3_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000d8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE3_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE3_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE3_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE3_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE3_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE3_ADDR,m,v,HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE3_IN)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE3_EDPPHY_SPARE_31_24_BMSK                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_SPARE3_EDPPHY_SPARE_31_24_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_ADDR                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000dc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_OFFS                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000dc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_RMSK                                            0x1f
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_TX_REQ_ERR_BMSK                             0x10
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_TX_REQ_ERR_SHFT                              0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_ALIGN_ERR_BMSK                            0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_ALIGN_ERR_SHFT                            0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_SYNC_ERR_BMSK                             0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_SYNC_ERR_SHFT                             0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_DEC_ERR_BMSK                              0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_DEC_ERR_SHFT                              0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_STOP_ERR_BMSK                             0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_STOP_ERR_SHFT                             0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_STATUS_ADDR                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000e0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_STATUS_OFFS                                                    (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000e0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_STATUS_RMSK                                                           0x7
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_STATUS_C_READY_BMSK                                                   0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_STATUS_C_READY_SHFT                                                   0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_STATUS_PHY_READY_BMSK                                                 0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_STATUS_PHY_READY_SHFT                                                 0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_STATUS_TSYNC_DONE_BMSK                                                0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_STATUS_TSYNC_DONE_SHFT                                                0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS0_ADDR                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000e4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS0_OFFS                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000e4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS0_RMSK                                                 0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS0_AUX_BIST_CHECK_DONE_BMSK                             0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS0_AUX_BIST_CHECK_DONE_SHFT                             0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS1_ADDR                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000e8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS1_OFFS                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000e8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS1_RMSK                                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS1_AUX_BIST_ERROR_COUNT_7_0_BMSK                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS1_AUX_BIST_ERROR_COUNT_7_0_SHFT                        0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS2_ADDR                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000ec)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS2_OFFS                                          (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000ec)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS2_RMSK                                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS2_AUX_BIST_ERROR_COUNT_15_8_BMSK                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_AUX_BIST_STATUS2_AUX_BIST_ERROR_COUNT_15_8_SHFT                       0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_ADDR                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000f0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_OFFS                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000f0)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_RMSK                                             0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_RXCHK_HEADER_SEL_BMSK                    0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_RXCHK_HEADER_SEL_SHFT                    0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_PAT_DATA_NOT_FOUND_BMSK                  0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_PAT_DATA_NOT_FOUND_SHFT                  0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_HEADER_NOT_FOUND_BMSK                    0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_HEADER_NOT_FOUND_SHFT                    0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_CHECK_DONE_BMSK                          0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_CHECK_DONE_SHFT                          0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_ADDR                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000f4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_OFFS                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000f4)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_RMSK                                            0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_L0_BIST_ERROR_COUNT_7_0_BMSK                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_L0_BIST_ERROR_COUNT_7_0_SHFT                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_ADDR                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000f8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_OFFS                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000f8)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_RMSK                                            0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_L0_BIST_ERROR_COUNT_15_8_BMSK                   0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_L0_BIST_ERROR_COUNT_15_8_SHFT                    0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_ADDR                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000fc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_OFFS                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000fc)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_RMSK                                             0xf
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_RXCHK_HEADER_SEL_BMSK                    0x8
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_RXCHK_HEADER_SEL_SHFT                    0x3
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_PAT_DATA_NOT_FOUND_BMSK                  0x4
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_PAT_DATA_NOT_FOUND_SHFT                  0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_HEADER_NOT_FOUND_BMSK                    0x2
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_HEADER_NOT_FOUND_SHFT                    0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_CHECK_DONE_BMSK                          0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_CHECK_DONE_SHFT                          0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_ADDR                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000100)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_OFFS                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000100)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_RMSK                                            0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_L1_BIST_ERROR_COUNT_7_0_BMSK                    0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_L1_BIST_ERROR_COUNT_7_0_SHFT                     0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_ADDR                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000104)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_OFFS                                      (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000104)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_RMSK                                            0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_L1_BIST_ERROR_COUNT_15_8_BMSK                   0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_L1_BIST_ERROR_COUNT_15_8_SHFT                    0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_STATUS_ADDR                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000108)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_STATUS_OFFS                                               (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000108)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_STATUS_RMSK                                                      0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_STATUS_MISR_CAPTURED_BMSK                                        0x1
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_MISR_STATUS_MISR_CAPTURED_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS000_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000010c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS000_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000010c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS000_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS000_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS000_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS000_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS000_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS000_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS000_L0_MISR_7_0_BMSK                                  0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS000_L0_MISR_7_0_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS001_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000110)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS001_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000110)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS001_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS001_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS001_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS001_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS001_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS001_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS001_L0_MISR_15_8_BMSK                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS001_L0_MISR_15_8_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS010_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000114)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS010_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000114)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS010_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS010_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS010_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS010_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS010_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS010_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS010_L0_MISR_23_16_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS010_L0_MISR_23_16_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS011_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000118)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS011_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000118)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS011_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS011_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS011_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS011_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS011_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS011_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS011_L0_MISR_31_24_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS011_L0_MISR_31_24_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS100_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000011c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS100_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000011c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS100_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS100_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS100_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS100_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS100_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS100_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS100_L0_MISR_39_32_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS100_L0_MISR_39_32_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS101_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000120)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS101_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000120)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS101_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS101_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS101_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS101_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS101_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS101_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS101_L0_MISR_47_40_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS101_L0_MISR_47_40_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS110_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000124)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS110_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000124)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS110_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS110_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS110_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS110_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS110_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS110_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS110_L0_MISR_55_48_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS110_L0_MISR_55_48_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS111_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000128)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS111_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000128)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS111_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS111_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS111_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS111_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS111_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS111_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS111_L0_MISR_63_56_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX0_MISR_STATUS111_L0_MISR_63_56_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS000_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000012c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS000_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000012c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS000_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS000_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS000_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS000_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS000_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS000_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS000_L1_MISR_7_0_BMSK                                  0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS000_L1_MISR_7_0_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS001_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000130)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS001_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000130)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS001_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS001_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS001_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS001_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS001_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS001_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS001_L1_MISR_15_8_BMSK                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS001_L1_MISR_15_8_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS010_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000134)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS010_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000134)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS010_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS010_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS010_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS010_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS010_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS010_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS010_L1_MISR_23_16_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS010_L1_MISR_23_16_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS011_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000138)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS011_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000138)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS011_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS011_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS011_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS011_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS011_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS011_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS011_L1_MISR_31_24_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS011_L1_MISR_31_24_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS100_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000013c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS100_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000013c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS100_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS100_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS100_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS100_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS100_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS100_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS100_L1_MISR_39_32_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS100_L1_MISR_39_32_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS101_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000140)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS101_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000140)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS101_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS101_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS101_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS101_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS101_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS101_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS101_L1_MISR_47_40_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS101_L1_MISR_47_40_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS110_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000144)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS110_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000144)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS110_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS110_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS110_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS110_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS110_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS110_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS110_L1_MISR_55_48_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS110_L1_MISR_55_48_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS111_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000148)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS111_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000148)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS111_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS111_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS111_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS111_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS111_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS111_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS111_L1_MISR_63_56_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX1_MISR_STATUS111_L1_MISR_63_56_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS000_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000014c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS000_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000014c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS000_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS000_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS000_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS000_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS000_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS000_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS000_L2_MISR_7_0_BMSK                                  0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS000_L2_MISR_7_0_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS001_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000150)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS001_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000150)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS001_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS001_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS001_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS001_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS001_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS001_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS001_L2_MISR_15_8_BMSK                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS001_L2_MISR_15_8_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS010_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000154)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS010_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000154)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS010_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS010_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS010_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS010_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS010_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS010_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS010_L2_MISR_23_16_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS010_L2_MISR_23_16_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS011_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000158)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS011_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000158)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS011_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS011_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS011_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS011_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS011_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS011_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS011_L2_MISR_31_24_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS011_L2_MISR_31_24_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS100_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000015c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS100_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000015c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS100_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS100_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS100_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS100_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS100_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS100_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS100_L2_MISR_39_32_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS100_L2_MISR_39_32_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS101_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000160)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS101_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000160)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS101_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS101_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS101_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS101_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS101_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS101_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS101_L2_MISR_47_40_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS101_L2_MISR_47_40_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS110_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000164)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS110_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000164)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS110_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS110_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS110_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS110_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS110_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS110_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS110_L2_MISR_55_48_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS110_L2_MISR_55_48_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS111_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000168)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS111_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000168)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS111_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS111_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS111_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS111_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS111_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS111_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS111_L2_MISR_63_56_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX2_MISR_STATUS111_L2_MISR_63_56_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS000_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000016c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS000_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000016c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS000_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS000_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS000_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS000_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS000_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS000_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS000_L3_MISR_7_0_BMSK                                  0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS000_L3_MISR_7_0_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS001_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000170)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS001_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000170)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS001_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS001_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS001_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS001_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS001_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS001_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS001_L3_MISR_15_8_BMSK                                 0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS001_L3_MISR_15_8_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS010_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000174)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS010_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000174)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS010_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS010_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS010_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS010_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS010_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS010_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS010_L3_MISR_23_16_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS010_L3_MISR_23_16_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS011_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000178)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS011_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000178)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS011_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS011_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS011_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS011_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS011_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS011_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS011_L3_MISR_31_24_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS011_L3_MISR_31_24_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS100_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000017c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS100_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000017c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS100_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS100_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS100_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS100_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS100_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS100_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS100_L3_MISR_39_32_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS100_L3_MISR_39_32_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS101_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000180)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS101_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000180)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS101_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS101_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS101_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS101_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS101_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS101_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS101_L3_MISR_47_40_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS101_L3_MISR_47_40_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS110_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000184)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS110_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000184)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS110_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS110_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS110_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS110_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS110_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS110_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS110_L3_MISR_55_48_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS110_L3_MISR_55_48_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS111_ADDR                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000188)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS111_OFFS                                        (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000188)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS111_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS111_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS111_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS111_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS111_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS111_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS111_L3_MISR_63_56_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_TX3_MISR_STATUS111_L3_MISR_63_56_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS0_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000018c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS0_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000018c)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS0_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS0_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS0_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS0_DEBUG_BUS_7_0_BMSK                                        0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS0_DEBUG_BUS_7_0_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS1_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000190)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS1_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000190)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS1_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS1_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS1_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS1_DEBUG_BUS_15_8_BMSK                                       0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS1_DEBUG_BUS_15_8_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS2_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000194)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS2_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000194)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS2_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS2_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS2_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS2_DEBUG_BUS_23_16_BMSK                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS2_DEBUG_BUS_23_16_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS3_ADDR                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000198)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS3_OFFS                                                (AHB2EDPPHY_CM_EDP_PHY_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000198)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS3_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS3_ADDR, HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS3_RMSK)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS3_DEBUG_BUS_31_24_BMSK                                      0xff
#define HWIO_AHB2EDPPHY_CM_EDP_PHY_EDP_DP_PHY_DEBUG_BUS3_DEBUG_BUS_31_24_SHFT                                       0x0

/*----------------------------------------------------------------------------
 * MODULE: AHB2EDPPHY_CM_DPPHY2
 *--------------------------------------------------------------------------*/

#define AHB2EDPPHY_CM_DPPHY2_REG_BASE (MDSS_BASE      + 0x000c3000)
#define AHB2EDPPHY_CM_DPPHY2_REG_BASE_OFFS 0x000c3000

/*----------------------------------------------------------------------------
 * MODULE: AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL
 *--------------------------------------------------------------------------*/

#define AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE                                         (MDSS_BASE      + 0x000c5000)
#define AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS                                    0x000c5000

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL1_ADDR                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000000)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL1_OFFS                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000000)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL1_RMSK                                                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL1_ATB_SEL_7_0_BMSK                                                     0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL1_ATB_SEL_7_0_SHFT                                                      0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL2_ADDR                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000004)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL2_OFFS                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000004)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL2_RMSK                                                                  0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL2_ATB_SEL_10_8_BMSK                                                     0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_ATB_SEL2_ATB_SEL_10_8_SHFT                                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_FREQ_UPDATE_ADDR                                                        (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000008)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_FREQ_UPDATE_OFFS                                                        (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000008)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_FREQ_UPDATE_RMSK                                                               0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_FREQ_UPDATE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_FREQ_UPDATE_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_FREQ_UPDATE_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_FREQ_UPDATE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_FREQ_UPDATE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_FREQ_UPDATE_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_FREQ_UPDATE_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_FREQ_UPDATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_FREQ_UPDATE_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_FREQ_UPDATE_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_FREQ_UPDATE_PLL_FREQ_UPDATE_BMSK                                               0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_FREQ_UPDATE_PLL_FREQ_UPDATE_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_ADDR                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000000c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_OFFS                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000000c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_RMSK                                                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_SYSCLK_WAKE_BYPASS_BMSK                                              0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_SYSCLK_WAKE_BYPASS_SHFT                                               0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_SYSCLK_WAKE_TIME_BMSK                                                0x70
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_SYSCLK_WAKE_TIME_SHFT                                                 0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_REFCLK_FREQ_SEL_BMSK                                                  0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_REFCLK_FREQ_SEL_SHFT                                                  0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_RSVD_BMSK                                                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_RSVD_SHFT                                                             0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_BIAS_WAIT_TIME_BMSK                                                   0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BG_TIMER_BIAS_WAIT_TIME_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_ADDR                                                      (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000010)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_OFFS                                                      (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000010)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_RMSK                                                             0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_SSC_CENTER_BMSK                                                  0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_SSC_CENTER_SHFT                                                  0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_SSC_EN_BMSK                                                      0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_EN_CENTER_SSC_EN_SHFT                                                      0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER1_ADDR                                                       (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000014)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER1_OFFS                                                       (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000014)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER1_RMSK                                                             0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER1_SSC_ADJPER_7_0_BMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER1_SSC_ADJPER_7_0_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER2_ADDR                                                       (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000018)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER2_OFFS                                                       (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000018)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER2_RMSK                                                              0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER2_SSC_ADJPER_9_8_BMSK                                               0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_ADJ_PER2_SSC_ADJPER_9_8_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER1_ADDR                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000001c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER1_OFFS                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000001c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER1_RMSK                                                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER1_SSC_PER_7_0_BMSK                                                     0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER1_SSC_PER_7_0_SHFT                                                      0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER2_ADDR                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000020)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER2_OFFS                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000020)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER2_RMSK                                                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER2_SSC_PER_15_8_BMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_PER2_SSC_PER_15_8_SHFT                                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_ADDR                                               (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000024)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_OFFS                                               (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000024)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_RMSK                                                     0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_SSC_STEPSIZE_MODE0_7_0_BMSK                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE0_SSC_STEPSIZE_MODE0_7_0_SHFT                               0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_ADDR                                               (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000028)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_OFFS                                               (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000028)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_RMSK                                                     0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_SSC_STEPSIZE_MODE0_15_8_BMSK                             0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE0_SSC_STEPSIZE_MODE0_15_8_SHFT                              0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_ADDR                                               (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000002c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_OFFS                                               (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000002c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_RMSK                                                      0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_SSC_STEPSIZE_MODE0_16_16_BMSK                             0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE0_SSC_STEPSIZE_MODE0_16_16_SHFT                             0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_ADDR                                               (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000030)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_OFFS                                               (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000030)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_RMSK                                                     0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_SSC_STEPSIZE_MODE1_7_0_BMSK                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE1_MODE1_SSC_STEPSIZE_MODE1_7_0_SHFT                               0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_ADDR                                               (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000034)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_OFFS                                               (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000034)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_RMSK                                                     0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_SSC_STEPSIZE_MODE1_15_8_BMSK                             0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE2_MODE1_SSC_STEPSIZE_MODE1_15_8_SHFT                              0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_ADDR                                               (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000038)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_OFFS                                               (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000038)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_RMSK                                                      0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_SSC_STEPSIZE_MODE1_16_16_BMSK                             0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SSC_STEP_SIZE3_MODE1_SSC_STEPSIZE_MODE1_16_16_SHFT                             0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_ADDR                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000003c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_OFFS                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000003c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_RMSK                                                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_PLL_POSTDIV_7_0_BMSK                                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_PLL_POSTDIV_7_0_SHFT                                                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_ADDR                                                       (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000040)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_OFFS                                                       (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000040)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_RMSK                                                             0x11
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_PLL_POSTDIV_MUX_BMSK                                             0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_PLL_POSTDIV_MUX_SHFT                                              0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_PLL_POSTDIV_8_8_BMSK                                              0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_POST_DIV_MUX_PLL_POSTDIV_8_8_SHFT                                              0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000044)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000044)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_RMSK                                                      0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_EN_SYSCLK_TX_SEL_BMSK                                     0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_EN_SYSCLK_TX_SEL_SHFT                                      0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_CLKBUF_L_EN_BMSK                                           0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_CLKBUF_L_EN_SHFT                                           0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_CLKBUF_R_EN_BMSK                                           0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_CLKBUF_R_EN_SHFT                                           0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_BIAS_EN_MUX_BMSK                                           0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_BIAS_EN_MUX_SHFT                                           0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_BIAS_EN_BMSK                                               0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN_BIAS_EN_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_ADDR                                                        (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000048)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_OFFS                                                        (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000048)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_RMSK                                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_CLKDRVIDLE_EN_BMSK                                                0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_CLKDRVIDLE_EN_SHFT                                                 0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_EN_SYSCLK_TX_PS3PS4_BMSK                                          0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_EN_SYSCLK_TX_PS3PS4_SHFT                                           0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_EN_SYSCLK_TX_PS0PS1PS2_BMSK                                       0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_EN_SYSCLK_TX_PS0PS1PS2_SHFT                                        0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_CLK_EP_EN_BMSK                                                    0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_CLK_EP_EN_SHFT                                                     0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_PLL_CLKOUT_EN_MUX_BMSK                                             0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_PLL_CLKOUT_EN_MUX_SHFT                                             0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_PLL_CLKOUT_EN_BMSK                                                 0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_PLL_CLKOUT_EN_SHFT                                                 0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_EXT_CLKBUF_EN_MUX_BMSK                                             0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_EXT_CLKBUF_EN_MUX_SHFT                                             0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_EXT_CLKBUF_EN_BMSK                                                 0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_ENABLE1_EXT_CLKBUF_EN_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_ADDR                                                       (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000004c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_OFFS                                                       (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000004c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_RMSK                                                             0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_EP_GLITCHFREE_BYPASS_BMSK                                        0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_EP_GLITCHFREE_BYPASS_SHFT                                         0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_TX_SYSCLKSEL_MUX_BMSK                                     0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_TX_SYSCLKSEL_MUX_SHFT                                      0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_TX_SYSCLKSEL_BMSK                                         0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_TX_SYSCLKSEL_SHFT                                          0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_DIV2_SEL_BMSK                                              0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_DIV2_SEL_SHFT                                              0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_CM_BMSK                                                    0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_CM_SHFT                                                    0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_AC_COUPLE_BMSK                                             0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_AC_COUPLE_SHFT                                             0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_GNDTERM_BMSK                                               0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYS_CLK_CTRL_SYSCLK_GNDTERM_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000050)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000050)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_RMSK                                                         0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_EN_CTRL_BY_PSM_BMSK                                   0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_EN_CTRL_BY_PSM_SHFT                                   0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_EN_PS3PS4_BMSK                                        0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_EN_PS3PS4_SHFT                                        0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_BUF_EN_MUX_BMSK                                       0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_SYSCLK_BUF_EN_MUX_SHFT                                       0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_SW_SYSCLK_BUF_EN_BMSK                                        0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_BUF_ENABLE_SW_SYSCLK_BUF_EN_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_ADDR                                                             (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000054)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_OFFS                                                             (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000054)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_RMSK                                                                    0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_PLL_EN_MUX_BMSK                                                         0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_PLL_EN_MUX_SHFT                                                         0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_PLL_EN_BMSK                                                             0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_EN_PLL_EN_SHFT                                                             0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_IVCO_ADDR                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000058)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_IVCO_OFFS                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000058)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_IVCO_RMSK                                                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_IVCO_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_IVCO_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_IVCO_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_IVCO_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_IVCO_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_IVCO_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_IVCO_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_IVCO_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_IVCO_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_IVCO_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_IVCO_PLL_IVCO_BMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_IVCO_PLL_IVCO_SHFT                                                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IETRIM_ADDR                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000005c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IETRIM_OFFS                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000005c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IETRIM_RMSK                                                               0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IETRIM_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IETRIM_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IETRIM_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IETRIM_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IETRIM_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IETRIM_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IETRIM_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IETRIM_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IETRIM_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IETRIM_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IETRIM_IETRIM_BMSK                                                        0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IETRIM_IETRIM_SHFT                                                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IPTRIM_ADDR                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000060)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IPTRIM_OFFS                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000060)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IPTRIM_RMSK                                                               0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IPTRIM_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IPTRIM_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IPTRIM_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IPTRIM_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IPTRIM_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IPTRIM_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IPTRIM_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IPTRIM_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IPTRIM_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IPTRIM_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IPTRIM_IPTRIM_BMSK                                                        0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_IPTRIM_IPTRIM_SHFT                                                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_ADDR                                               (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000064)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_OFFS                                               (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000064)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_RMSK                                                     0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_DIVSEL_MUX_BMSK                            0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_DIVSEL_MUX_SHFT                             0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_DIVSEL_BMSK                                0x18
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_DIVSEL_SHFT                                 0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_FORCE_BMSK                                  0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_FORCE_SHFT                                  0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_EN_MUX_BMSK                                 0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_EN_MUX_SHFT                                 0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_EN_BMSK                                     0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EP_CLOCK_DETECT_CTRL_SYSCLK_CLKDET_EN_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_ADDR                                             (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000068)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_OFFS                                             (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000068)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_RMSK                                                    0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_SYSCLK_CLKDET_COMP_BMSK                                 0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_DET_COMP_STATUS_SYSCLK_CLKDET_COMP_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000006c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000006c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_RMSK                                                         0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_CLK_EP_DIV_MODE0_BMSK                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE0_CLK_EP_DIV_MODE0_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000070)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000070)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_RMSK                                                         0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_CLK_EP_DIV_MODE1_BMSK                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_EP_DIV_MODE1_CLK_EP_DIV_MODE1_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE0_ADDR                                                      (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000074)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE0_OFFS                                                      (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000074)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE0_RMSK                                                            0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE0_PLL_CPCTRL_MODE0_BMSK                                           0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE0_PLL_CPCTRL_MODE0_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE1_ADDR                                                      (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000078)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE1_OFFS                                                      (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000078)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE1_RMSK                                                            0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE1_PLL_CPCTRL_MODE1_BMSK                                           0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CP_CTRL_MODE1_PLL_CPCTRL_MODE1_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE0_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000007c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE0_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000007c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE0_RMSK                                                          0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE0_PLL_RCTRL_MODE0_BMSK                                          0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE0_PLL_RCTRL_MODE0_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE1_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000080)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE1_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000080)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE1_RMSK                                                          0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE1_PLL_RCTRL_MODE1_BMSK                                          0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_RCTRL_MODE1_PLL_RCTRL_MODE1_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE0_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000084)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE0_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000084)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE0_RMSK                                                          0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE0_PLL_CCTRL_MODE0_BMSK                                          0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE0_PLL_CCTRL_MODE0_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE1_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000088)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE1_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000088)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE1_RMSK                                                          0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE1_PLL_CCTRL_MODE1_BMSK                                          0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CCTRL_MODE1_PLL_CCTRL_MODE1_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_ADDR                                                          (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000008c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_OFFS                                                          (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000008c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_RMSK                                                                0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_PLL_STABLE_TIME_BMSK                                                0x60
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_PLL_STABLE_TIME_SHFT                                                 0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_MASH_RESET_MUX_BMSK                                                 0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_MASH_RESET_MUX_SHFT                                                  0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_MASH_RESET_BMSK                                                      0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_MASH_RESET_SHFT                                                      0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_PLL_CPLIN_BMSK                                                       0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_PLL_CPLIN_SHFT                                                       0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_PLL_DIV_FFEN_BMSK                                                    0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_PLL_DIV_FFEN_SHFT                                                    0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_PLL_DIV_ORD_BMSK                                                     0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_CNTRL_PLL_DIV_ORD_SHFT                                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000090)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000090)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_RMSK                                                       0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_BIAS_EN_CTRL_BY_PSM_BMSK                                   0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM_BIAS_EN_CTRL_BY_PSM_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_ADDR                                                      (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000094)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_OFFS                                                      (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000094)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_RMSK                                                            0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_CML_SYSCLK_SEL_BMSK                                             0xe0
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_CML_SYSCLK_SEL_SHFT                                              0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_TERM_SEL_BMSK                                            0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_TERM_SEL_SHFT                                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_SEL_BMSK                                                  0xc
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_SEL_SHFT                                                  0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_EN_MUX_BMSK                                               0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_EN_MUX_SHFT                                               0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_EN_BMSK                                                   0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SYSCLK_EN_SEL_SYSCLK_EN_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CML_SYSCLK_SEL_ADDR                                                     (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000098)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CML_SYSCLK_SEL_OFFS                                                     (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000098)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CML_SYSCLK_SEL_RMSK                                                            0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CML_SYSCLK_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CML_SYSCLK_SEL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CML_SYSCLK_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CML_SYSCLK_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CML_SYSCLK_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CML_SYSCLK_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CML_SYSCLK_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CML_SYSCLK_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CML_SYSCLK_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CML_SYSCLK_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CML_SYSCLK_SEL_CML_SYSCLK_SEL_MUX_BMSK                                         0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CML_SYSCLK_SEL_CML_SYSCLK_SEL_MUX_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_ADDR                                                      (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000009c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_OFFS                                                      (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000009c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_RMSK                                                            0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_FORCE_C_READY_BMSK                                              0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_FORCE_C_READY_SHFT                                               0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_TSYNC_SEL_BMSK                                                  0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_TSYNC_SEL_SHFT                                                   0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_DISABLE_CLKGATE_BMSK                                            0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_DISABLE_CLKGATE_SHFT                                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_PLL_UNLOCK_DISABLE_BMSK                                          0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_PLL_UNLOCK_DISABLE_SHFT                                          0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_RSM_START_MUX_BMSK                                               0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_RSM_START_MUX_SHFT                                               0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_RSM_START_BMSK                                                   0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_RSM_START_SHFT                                                   0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_FORCE_PLLLOCK_BMSK                                               0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL_FORCE_PLLLOCK_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_ADDR                                                     (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000a0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_OFFS                                                     (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000a0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_RMSK                                                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_CORE_PLL_EN_MUX_BMSK                                           0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_CORE_PLL_EN_MUX_SHFT                                            0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_CORE_PLL_EN_BMSK                                               0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_CORE_PLL_EN_SHFT                                                0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_BYPASS_RSM_BIAS_BMSK                                           0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_BYPASS_RSM_BIAS_SHFT                                            0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_BYPASS_RSM_INTEGLOOP_CAL_BMSK                                  0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_BYPASS_RSM_INTEGLOOP_CAL_SHFT                                   0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_PULSE_WIDTH_BMSK                                          0xc
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_PULSE_WIDTH_SHFT                                          0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_MUX_BMSK                                                  0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_MUX_SHFT                                                  0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_BMSK                                                      0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESETSM_CNTRL2_TSYNC_SHFT                                                      0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_ADDR                                                        (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000a4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_OFFS                                                        (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000a4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_RMSK                                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_RNG_2_BMSK                                                0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_RNG_2_SHFT                                                 0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_CNT_2_BMSK                                                0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_CNT_2_SHFT                                                 0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_EN_MUX_BMSK                                               0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_EN_MUX_SHFT                                                0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_EN_BMSK                                                   0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_EN_SHFT                                                    0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_RNG_BMSK                                                   0xc
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_RNG_SHFT                                                   0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_CNT_BMSK                                                   0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_EN_PLLLOCK_CNT_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_ADDR                                                       (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000a8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_OFFS                                                       (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000a8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_RMSK                                                              0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_PLLLOCK_RNG_UPDATE_DISABLE_BMSK                                   0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_PLLLOCK_RNG_UPDATE_DISABLE_SHFT                                   0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_PLLLOCK_STOP_COUNT_BMSK                                           0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_PLLLOCK_STOP_COUNT_SHFT                                           0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_BYP_PLLLOCK_BMSK                                                  0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP_CFG_BYP_PLLLOCK_SHFT                                                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE0_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000ac)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE0_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000ac)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE0_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE0_PLLLOCK_CMP_MODE0_7_0_BMSK                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE0_PLLLOCK_CMP_MODE0_7_0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE0_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000b0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE0_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000b0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE0_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE0_PLLLOCK_CMP_MODE0_15_8_BMSK                                   0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE0_PLLLOCK_CMP_MODE0_15_8_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE1_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000b4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE1_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000b4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE1_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE1_PLLLOCK_CMP_MODE1_7_0_BMSK                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP1_MODE1_PLLLOCK_CMP_MODE1_7_0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE1_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000b8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE1_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000b8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE1_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE1_PLLLOCK_CMP_MODE1_15_8_BMSK                                   0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_LOCK_CMP2_MODE1_PLLLOCK_CMP_MODE1_15_8_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE0_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000bc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE0_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000bc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE0_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE0_DEC_START_MODE0_7_0_BMSK                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE0_DEC_START_MODE0_7_0_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE0_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000c0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE0_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000c0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE0_RMSK                                                       0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE0_DEC_START_MODE0_8_8_BMSK                                   0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE0_DEC_START_MODE0_8_8_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE1_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000c4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE1_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000c4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE1_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE1_DEC_START_MODE1_7_0_BMSK                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MODE1_DEC_START_MODE1_7_0_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE1_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000c8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE1_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000c8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE1_RMSK                                                       0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE1_DEC_START_MODE1_8_8_BMSK                                   0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEC_START_MSB_MODE1_DEC_START_MODE1_8_8_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000cc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000cc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_DIV_FRAC_START_MODE0_7_0_BMSK                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE0_DIV_FRAC_START_MODE0_7_0_SHFT                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000d0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000d0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_DIV_FRAC_START_MODE0_15_8_BMSK                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE0_DIV_FRAC_START_MODE0_15_8_SHFT                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000d4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000d4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_RMSK                                                     0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_DIV_FRAC_START_MODE0_19_16_BMSK                          0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE0_DIV_FRAC_START_MODE0_19_16_SHFT                          0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000d8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000d8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_DIV_FRAC_START_MODE1_7_0_BMSK                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START1_MODE1_DIV_FRAC_START_MODE1_7_0_SHFT                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000dc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000dc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_DIV_FRAC_START_MODE1_15_8_BMSK                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START2_MODE1_DIV_FRAC_START_MODE1_15_8_SHFT                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000e0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000e0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_RMSK                                                     0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_DIV_FRAC_START_MODE1_19_16_BMSK                          0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DIV_FRAC_START3_MODE1_DIV_FRAC_START_MODE1_19_16_SHFT                          0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_INITVAL_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000e4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_INITVAL_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000e4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_INITVAL_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_INITVAL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_INITVAL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_INITVAL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_INITVAL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_INITVAL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_INITVAL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_INITVAL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_INITVAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_INITVAL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_INITVAL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_INITVAL_INTEGLOOP_INITVAL_BMSK                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_INITVAL_INTEGLOOP_INITVAL_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_ADDR                                                       (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000e8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_OFFS                                                       (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000e8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_RMSK                                                              0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_P_GAIN_SIGN_FLIP_BMSK                                             0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_P_GAIN_SIGN_FLIP_SHFT                                             0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_CODE_BYPASS_BMSK                                        0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_CODE_BYPASS_SHFT                                        0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_EN_MUX_BMSK                                             0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_EN_MUX_SHFT                                             0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_EN_BMSK                                                 0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_EN_INTEGLOOP_EN_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000ec)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000ec)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_INTEGLOOP_GAIN_MODE0_7_0_BMSK                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0_INTEGLOOP_GAIN_MODE0_7_0_SHFT                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000f0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000f0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_RMSK                                                     0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_INTEGLOOP_GAIN_MODE0_11_8_BMSK                           0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0_INTEGLOOP_GAIN_MODE0_11_8_SHFT                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000f4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000f4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_INTEGLOOP_GAIN_MODE1_7_0_BMSK                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1_INTEGLOOP_GAIN_MODE1_7_0_SHFT                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000f8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000f8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_RMSK                                                     0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_INTEGLOOP_GAIN_MODE1_11_8_BMSK                           0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1_INTEGLOOP_GAIN_MODE1_11_8_SHFT                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_ADDR                                             (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000000fc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_OFFS                                             (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000000fc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_RMSK                                                   0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_INTEGLOOP_P_GAIN_7_0_BMSK                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0_INTEGLOOP_P_GAIN_7_0_SHFT                               0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_ADDR                                             (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000100)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_OFFS                                             (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000100)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_RMSK                                                    0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_INTEGLOOP_P_GAIN_9_8_BMSK                               0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1_INTEGLOOP_P_GAIN_9_8_SHFT                               0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000104)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000104)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_RMSK                                                      0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_TOO_SLOW_CNTSEL_BMSK                                0x18
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_TOO_SLOW_CNTSEL_SHFT                                 0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FORCE_CORRECT_POL_BMSK                                     0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FORCE_CORRECT_POL_SHFT                                     0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_DEAD_CORRECT_EN_BMSK                                 0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_DEAD_CORRECT_EN_SHFT                                 0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_DEAD_TIME_BMSK                                       0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCOCAL_DEADMAN_CTRL_FBCLK_DEAD_TIME_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_ADDR                                                      (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000108)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_OFFS                                                      (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000108)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_RMSK                                                            0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_BIN_VCOCAL_FORCE_DONE_BMSK                                      0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_BIN_VCOCAL_FORCE_DONE_SHFT                                       0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_VCOCAL_TYPE_SEL_BMSK                                            0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_VCOCAL_TYPE_SEL_SHFT                                             0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_VCOCAL_POS_SLOPE_BMSK                                           0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_VCOCAL_POS_SLOPE_SHFT                                            0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_BYP_VCOCAL_MODE1_BMSK                                            0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_BYP_VCOCAL_MODE1_SHFT                                            0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_BYP_VCOCAL_MODE0_BMSK                                            0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_BYP_VCOCAL_MODE0_SHFT                                            0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_VCO_TUNE_EN_MUX_BMSK                                             0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_VCO_TUNE_EN_MUX_SHFT                                             0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_VCO_TUNE_EN_BMSK                                                 0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_CTRL_VCO_TUNE_EN_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_ADDR                                                       (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000010c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_OFFS                                                       (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000010c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_RMSK                                                              0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_VCO_DEFAULT_FREQ_BMSK                                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_VCO_DEFAULT_FREQ_SHFT                                             0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_MAP_LANE_PS0B_BMSK                                                0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_MAP_LANE_PS0B_SHFT                                                0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_MAP_LANE_PS0A_BMSK                                                0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAP_MAP_LANE_PS0A_SHFT                                                0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE0_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000110)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE0_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000110)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE0_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE0_PLL_VCOTUNE_MODE0_7_0_BMSK                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE0_PLL_VCOTUNE_MODE0_7_0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE0_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000114)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE0_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000114)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE0_RMSK                                                           0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE0_PLL_VCOTUNE_MODE0_9_8_BMSK                                     0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE0_PLL_VCOTUNE_MODE0_9_8_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE1_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000118)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE1_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000118)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE1_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE1_PLL_VCOTUNE_MODE1_7_0_BMSK                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE1_MODE1_PLL_VCOTUNE_MODE1_7_0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE1_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000011c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE1_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000011c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE1_RMSK                                                           0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE1_PLL_VCOTUNE_MODE1_9_8_BMSK                                     0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE2_MODE1_PLL_VCOTUNE_MODE1_9_8_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000120)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000120)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_VCO_TUNE_INITVAL_7_0_BMSK                                   0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL1_VCO_TUNE_INITVAL_7_0_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000124)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000124)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_RMSK                                                         0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_VCO_TUNE_INITVAL_9_8_BMSK                                    0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_INITVAL2_VCO_TUNE_INITVAL_9_8_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000128)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000128)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_RMSK                                                         0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_VCO_TUNE_MINVAL_7_0_BMSK                                     0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL1_VCO_TUNE_MINVAL_7_0_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000012c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000012c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_RMSK                                                          0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_VCO_TUNE_MINVAL_9_8_BMSK                                      0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MINVAL2_VCO_TUNE_MINVAL_9_8_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000130)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000130)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_RMSK                                                         0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_VCO_TUNE_MAXVAL_7_0_BMSK                                     0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL1_VCO_TUNE_MAXVAL_7_0_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000134)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000134)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_RMSK                                                          0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_VCO_TUNE_MAXVAL_9_8_BMSK                                      0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_MAXVAL2_VCO_TUNE_MAXVAL_9_8_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER1_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000138)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER1_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000138)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER1_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER1_PLL_VCOTUNE_TIMER_7_0_BMSK                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER1_PLL_VCOTUNE_TIMER_7_0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER2_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000013c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER2_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000013c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER2_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER2_PLL_VCOTUNE_TIMER_15_8_BMSK                                   0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_TUNE_TIMER2_PLL_VCOTUNE_TIMER_15_8_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_ADDR                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000140)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_OFFS                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000140)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_RMSK                                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_REFGEN_READY_BMSK                                                  0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_REFGEN_READY_SHFT                                                   0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_FREEZEIO_D_BMSK                                                    0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_FREEZEIO_D_SHFT                                                     0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_SWITCH_TO_REFCLK_DONE_BMSK                                         0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_SWITCH_TO_REFCLK_DONE_SHFT                                          0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_SWITCH_TO_CORECLK_DONE_BMSK                                        0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_SWITCH_TO_CORECLK_DONE_SHFT                                         0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_SWITCH_TO_AUXCLK_DONE_BMSK                                          0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_SWITCH_TO_AUXCLK_DONE_SHFT                                          0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_PLL_UNLOCKED_BMSK                                                   0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_PLL_UNLOCKED_SHFT                                                   0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_PLL_LOCKED_BMSK                                                     0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_PLL_LOCKED_SHFT                                                     0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_PLL_FREQ_DONE_BMSK                                                  0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_STATUS_PLL_FREQ_DONE_SHFT                                                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESET_SM_STATUS_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000144)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESET_SM_STATUS_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000144)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESET_SM_STATUS_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESET_SM_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESET_SM_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESET_SM_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESET_SM_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESET_SM_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESET_SM_STATUS_RESETSM_BMSK                                                  0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESET_SM_STATUS_RESETSM_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000148)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000148)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_RMSK                                                      0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_RESTRIM_CODE_BMSK                                         0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_RESTRIM_CODE_STATUS_RESTRIM_CODE_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000014c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000014c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_VCO_CTUNE_BINCODE_7_0_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE1_STATUS_VCO_CTUNE_BINCODE_7_0_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000150)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000150)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_RMSK                                                       0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_VCO_CTUNE_BINCODE_9_8_BMSK                                 0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLLCAL_CODE2_STATUS_VCO_CTUNE_BINCODE_9_8_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_ADDR                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000154)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_OFFS                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000154)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_RMSK                                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_REFCLK_DRV_EN_MUX_BMSK                                             0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_REFCLK_DRV_EN_MUX_SHFT                                              0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_REFCLK_DRV_EN_BMSK                                                 0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_REFCLK_DRV_EN_SHFT                                                  0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_TSYNC_EN_MUX_BMSK                                                  0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_TSYNC_EN_MUX_SHFT                                                   0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_TSYNC_EN_BMSK                                                      0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_TSYNC_EN_SHFT                                                       0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_SYSCLK_CMOS_PAD_SEL_BMSK                                            0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_SYSCLK_CMOS_PAD_SEL_SHFT                                            0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_SYSCLK_TX_SWINGSEL_BMSK                                             0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_SYSCLK_TX_SWINGSEL_SHFT                                             0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_EP_REFCLK_SEL_BMSK                                                  0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CLK_SELECT_EP_REFCLK_SEL_SHFT                                                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_ADDR                                                          (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000158)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_OFFS                                                          (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000158)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_RMSK                                                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_HSCLK_DIVSEL_MODE1_BMSK                                             0xf0
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_HSCLK_DIVSEL_MODE1_SHFT                                              0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_HSCLK_DIVSEL_MODE0_BMSK                                              0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_SEL_HSCLK_DIVSEL_MODE0_SHFT                                              0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000015c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000015c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_HSCLK_SWITCH_DIVSEL_MODE1_BMSK                            0xf0
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_HSCLK_SWITCH_DIVSEL_MODE1_SHFT                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_HSCLK_SWITCH_DIVSEL_MODE0_BMSK                             0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_HSCLK_SWITCH_DIVSEL_MODE0_SHFT                             0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_ADDR                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000160)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_OFFS                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000160)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_RMSK                                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_INTEGLOOP_BINCODE_BMSK                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS_INTEGLOOP_BINCODE_SHFT                                0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_ANALOG_ADDR                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000164)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_ANALOG_OFFS                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000164)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_ANALOG_RMSK                                                                0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_ANALOG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_ANALOG_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_ANALOG_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_ANALOG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_ANALOG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_ANALOG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_ANALOG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_ANALOG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_ANALOG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_ANALOG_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_ANALOG_PLL_ANALOG_BMSK                                                     0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_PLL_ANALOG_PLL_ANALOG_SHFT                                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE0_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000168)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE0_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000168)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE0_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE0_CORE_CLK_DIV_MODE0_BMSK                                     0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE0_CORE_CLK_DIV_MODE0_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE1_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000016c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE1_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000016c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE1_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE1_CORE_CLK_DIV_MODE1_BMSK                                     0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORECLK_DIV_MODE1_CORE_CLK_DIV_MODE1_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SW_RESET_ADDR                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000170)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SW_RESET_OFFS                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000170)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SW_RESET_RMSK                                                                  0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SW_RESET_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SW_RESET_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SW_RESET_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SW_RESET_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SW_RESET_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SW_RESET_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SW_RESET_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SW_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SW_RESET_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SW_RESET_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SW_RESET_SW_RESET_BMSK                                                         0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SW_RESET_SW_RESET_SHFT                                                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_ADDR                                                        (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000174)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_OFFS                                                        (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000174)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_RMSK                                                              0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_CLKS_PLL_DIVSEL_MODE1_BMSK                                        0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_CLKS_PLL_DIVSEL_MODE1_SHFT                                         0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_CLKS_PLL_DIVSEL_MODE0_BMSK                                        0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_CLKS_PLL_DIVSEL_MODE0_SHFT                                         0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_CORECLK_EN_MUX_BMSK                                                0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_CORECLK_EN_MUX_SHFT                                                0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_CORECLK_EN_BMSK                                                    0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_CORECLK_EN_SHFT                                                    0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_AUXCLK_EN_MUX_BMSK                                                 0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_AUXCLK_EN_MUX_SHFT                                                 0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_AUXCLK_EN_BMSK                                                     0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CORE_CLK_EN_AUXCLK_EN_SHFT                                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_C_READY_STATUS_ADDR                                                     (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000178)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_C_READY_STATUS_OFFS                                                     (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000178)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_C_READY_STATUS_RMSK                                                            0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_C_READY_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_C_READY_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_C_READY_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_C_READY_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_C_READY_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_C_READY_STATUS_C_READY_BMSK                                                    0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_C_READY_STATUS_C_READY_SHFT                                                    0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_ADDR                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000017c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_OFFS                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000017c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_RMSK                                                               0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_FORCE_REFGEN_READY_BMSK                                            0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_FORCE_REFGEN_READY_SHFT                                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_PSM_SWITCH_CORECLK_BMSK                                             0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_PSM_SWITCH_CORECLK_SHFT                                             0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_PSM_SWITCH_AUXCLK_BMSK                                              0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_PSM_SWITCH_AUXCLK_SHFT                                              0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_PLL_FBCLK_SEL_BMSK                                                  0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_PLL_FBCLK_SEL_SHFT                                                  0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_CLK_BIAS_REFSEL_BMSK                                                0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_CONFIG_CLK_BIAS_REFSEL_SHFT                                                0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000180)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000180)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_RMSK                                                        0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_PLL_HS_SWITCH_MUX_BMSK                                      0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_PLL_HS_SWITCH_MUX_SHFT                                       0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_PLL_HS_SWITCH_BMSK                                           0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_PLL_HS_SWITCH_SHFT                                           0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_SW_UPDATE_BMSK                                      0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_SW_UPDATE_SHFT                                      0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_SW_SEL_BMSK                                         0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_SW_SEL_SHFT                                         0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_CODE_BMSK                                           0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_RATE_OVERRIDE_CMN_RATE_CODE_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000184)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000184)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_RMSK                                                          0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_PLL_DIGCLK_DIVSEL_MODE1_BMSK                                  0xc
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_PLL_DIGCLK_DIVSEL_MODE1_SHFT                                  0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_PLL_DIGCLK_DIVSEL_MODE0_BMSK                                  0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_SVS_MODE_CLK_SEL_PLL_DIGCLK_DIVSEL_MODE0_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS0_ADDR                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000188)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS0_OFFS                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000188)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS0_RMSK                                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS0_DEBUG_BUS_7_0_BMSK                                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS0_DEBUG_BUS_7_0_SHFT                                                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS1_ADDR                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000018c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS1_OFFS                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000018c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS1_RMSK                                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS1_DEBUG_BUS_15_8_BMSK                                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS1_DEBUG_BUS_15_8_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS2_ADDR                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000190)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS2_OFFS                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000190)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS2_RMSK                                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS2_DEBUG_BUS_23_16_BMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS2_DEBUG_BUS_23_16_SHFT                                                0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS3_ADDR                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000194)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS3_OFFS                                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000194)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS3_RMSK                                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS3_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS3_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS3_DEBUG_BUS_31_24_BMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS3_DEBUG_BUS_31_24_SHFT                                                0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_ADDR                                                      (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x00000198)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_OFFS                                                      (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x00000198)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_RMSK                                                            0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_CLK_DEBUG_SEL_BMSK                                              0xf0
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_CLK_DEBUG_SEL_SHFT                                               0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_DEBUG_BUS_SEL_BMSK                                               0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_DEBUG_BUS_SEL_DEBUG_BUS_SEL_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_ADDR                                                          (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x0000019c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_OFFS                                                          (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x0000019c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_RMSK                                                                0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_DIS_CG_RATE_CHANGE_BMSK                                             0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_DIS_CG_RATE_CHANGE_SHFT                                              0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_DIS_CG_SYSGLITCH_BMSK                                               0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_DIS_CG_SYSGLITCH_SHFT                                                0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_PLL_RESET_MUX_BMSK                                                  0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_PLL_RESET_MUX_SHFT                                                   0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_PLL_RESET_BMSK                                                       0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_PLL_RESET_SHFT                                                       0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_PLL_VREG_READY_MUX_BMSK                                              0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_PLL_VREG_READY_MUX_SHFT                                              0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_PLL_VREG_READY_BMSK                                                  0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_PLL_VREG_READY_SHFT                                                  0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_DISABLE_B2T_INTEGLOOP_CLKGATE_BMSK                                   0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC1_DISABLE_B2T_INTEGLOOP_CLKGATE_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC2_ADDR                                                          (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000001a0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC2_OFFS                                                          (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000001a0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC2_RMSK                                                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC2_RSVD_BMSK                                                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MISC2_RSVD_SHFT                                                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MODE_ADDR                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000001a4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MODE_OFFS                                                           (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000001a4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MODE_RMSK                                                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MODE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MODE_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MODE_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MODE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MODE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MODE_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MODE_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MODE_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MODE_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MODE_CMN_MODE_BMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_CMN_MODE_CMN_MODE_SHFT                                                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000001a8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000001a8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_RMSK                                                        0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_PLL_VREFGEN_REFSEL_BMSK                                     0x60
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_PLL_VREFGEN_REFSEL_SHFT                                      0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_PLL_VAR_DCCTRL_BMSK                                         0x18
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_PLL_VAR_DCCTRL_SHFT                                          0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_CMN_VREG_SEL_BMSK                                            0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_VCO_DC_LEVEL_CTRL_CMN_VREG_SEL_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_ADDR                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000001ac)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_OFFS                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000001ac)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_RMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_BIN_VCOCAL_MEAS_CNT_MODE0_7_0_BMSK                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0_BIN_VCOCAL_MEAS_CNT_MODE0_7_0_SHFT                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_ADDR                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000001b0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_OFFS                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000001b0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_RMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_BIN_VCOCAL_MEAS_CNT_MODE0_15_8_BMSK                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0_BIN_VCOCAL_MEAS_CNT_MODE0_15_8_SHFT                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_ADDR                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000001b4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_OFFS                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000001b4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_RMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_BIN_VCOCAL_MEAS_CNT_MODE1_7_0_BMSK                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1_BIN_VCOCAL_MEAS_CNT_MODE1_7_0_SHFT                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_ADDR                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000001b8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_OFFS                                         (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000001b8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_RMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_BIN_VCOCAL_MEAS_CNT_MODE1_15_8_BMSK                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1_BIN_VCOCAL_MEAS_CNT_MODE1_15_8_SHFT                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_ADDR                                               (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE      + 0x000001bc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_OFFS                                               (AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_EDP_QSERDES_COM_EDP_QMP_PLL_REG_BASE_OFFS + 0x000001bc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_RMSK                                                     0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_BIN_VCOCAL_HSCLK_SEL_MODE1_BMSK                          0xf0
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_BIN_VCOCAL_HSCLK_SEL_MODE1_SHFT                           0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_BIN_VCOCAL_HSCLK_SEL_MODE0_BMSK                           0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_BIN_VCOCAL_HSCLK_SEL_MODE0_SHFT                           0x0

/*----------------------------------------------------------------------------
 * MODULE: AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE
 *--------------------------------------------------------------------------*/

#define AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE                                       (MDSS_BASE      + 0x000c5200)
#define AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS                                  0x000c5200

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000000)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000000)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_RMSK                                                    0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_DISABLE_LPB_TX_CLKGATE_BMSK                             0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_DISABLE_LPB_TX_CLKGATE_SHFT                              0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_TXONLY_CLOCK_EDGE_BMSK                                   0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_TXONLY_CLOCK_EDGE_SHFT                                   0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_GATED_CLK_EN_BMSK                                        0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_GATED_CLK_EN_SHFT                                        0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_CLKBUF_EN_LANE1_BMSK                                     0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_CLKBUF_EN_LANE1_SHFT                                     0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_CLKBUF_EN_LANE0_BMSK                                     0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_CLKBUF_ENABLE_CLKBUF_EN_LANE0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_EMP_POST1_LVL_ADDR                                           (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000004)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_EMP_POST1_LVL_OFFS                                           (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000004)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_EMP_POST1_LVL_RMSK                                                 0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_EMP_POST1_LVL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_EMP_POST1_LVL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_EMP_POST1_LVL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_EMP_POST1_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_EMP_POST1_LVL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_EMP_POST1_LVL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_EMP_POST1_LVL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_EMP_POST1_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_EMP_POST1_LVL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_EMP_POST1_LVL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_EMP_POST1_LVL_EMP_POST1_LVL_BMSK                                   0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_EMP_POST1_LVL_EMP_POST1_LVL_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POST2_EMPH_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000008)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POST2_EMPH_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000008)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POST2_EMPH_RMSK                                                     0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POST2_EMPH_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POST2_EMPH_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POST2_EMPH_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POST2_EMPH_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POST2_EMPH_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POST2_EMPH_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POST2_EMPH_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POST2_EMPH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POST2_EMPH_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POST2_EMPH_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POST2_EMPH_POST2_EMPH_BMSK                                          0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POST2_EMPH_POST2_EMPH_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_ADDR                                         (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000000c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_OFFS                                         (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000000c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_RMSK                                               0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_TX_BOOST_LVL_DN_BMSK                               0x38
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_TX_BOOST_LVL_DN_SHFT                                0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_TX_BOOST_LVL_UP_BMSK                                0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BOOST_LVL_UP_DN_TX_BOOST_LVL_UP_SHFT                                0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_ADDR                                      (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000010)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_OFFS                                      (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000010)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_RMSK                                             0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_TX_IDLE_LVL_BMSK                                 0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_IDLE_LVL_LARGE_AMP_TX_IDLE_LVL_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000014)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000014)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_RMSK                                                       0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_TX_DRV_LVL_BMSK                                            0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_TX_DRV_LVL_SHFT                                             0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_ADDR                                          (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000018)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_OFFS                                          (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000018)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_RMSK                                                0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_TX_LVL_UPDATE_BMSK                                  0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_TX_LVL_UPDATE_SHFT                                   0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_TX_DRV_LVL_OFFSET_BMSK                               0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_DRV_LVL_OFFSET_TX_DRV_LVL_OFFSET_SHFT                               0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_ADDR                                             (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000001c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_OFFS                                             (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000001c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_RMSK                                                    0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_RESET_RSYNC_EN_MUX_BMSK                                 0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_RESET_RSYNC_EN_MUX_SHFT                                 0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_RESET_RSYNC_EN_BMSK                                     0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_RESET_RSYNC_EN_SHFT                                     0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_RESET_TSYNC_EN_MUX_BMSK                                 0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_RESET_TSYNC_EN_MUX_SHFT                                 0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_RESET_TSYNC_EN_BMSK                                     0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_TSYNC_EN_RESET_TSYNC_EN_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000020)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000020)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_RMSK                                                         0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_BOOST_EN_BMSK                                                0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_BOOST_EN_SHFT                                                 0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_SPARE_FOR_LDO_BMSK                                           0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_SPARE_FOR_LDO_SHFT                                            0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_PREEMPH_BMSK                                                 0x3e
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_PREEMPH_SHFT                                                  0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_PRE_EN_BMSK                                                   0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PRE_EMPH_PRE_EN_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_INTERFACE_SELECT_ADDR                                           (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000024)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_INTERFACE_SELECT_OFFS                                           (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000024)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_INTERFACE_SELECT_RMSK                                                  0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_INTERFACE_SELECT_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_INTERFACE_SELECT_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_INTERFACE_SELECT_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_INTERFACE_SELECT_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_INTERFACE_SELECT_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_INTERFACE_SELECT_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_INTERFACE_SELECT_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_INTERFACE_SELECT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_INTERFACE_SELECT_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_INTERFACE_SELECT_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_INTERFACE_SELECT_SEL_10B_8B_BMSK                                       0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_INTERFACE_SELECT_SEL_10B_8B_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000028)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000028)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_RMSK                                                           0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_TX_BAND_MUX_BMSK                                               0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_TX_BAND_MUX_SHFT                                               0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_TX_BAND_BMSK                                                   0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_BAND_TX_BAND_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SLEW_CNTL_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000002c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SLEW_CNTL_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000002c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SLEW_CNTL_RMSK                                                         0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SLEW_CNTL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SLEW_CNTL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SLEW_CNTL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SLEW_CNTL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SLEW_CNTL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SLEW_CNTL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SLEW_CNTL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SLEW_CNTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SLEW_CNTL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SLEW_CNTL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SLEW_CNTL_SLEW_CNTL_BMSK                                               0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SLEW_CNTL_SLEW_CNTL_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000030)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000030)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_RMSK                                                         0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_LPB_DIV10_SEL_DIG_BMSK                                       0x30
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_LPB_DIV10_SEL_DIG_SHFT                                        0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_LPB_CLK_DELAY_DIV10_TX1_BMSK                                  0xc
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_LPB_CLK_DELAY_DIV10_TX1_SHFT                                  0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_LPB_CLK_DELAY_DIV10_TX0_BMSK                                  0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG0_LPB_CLK_DELAY_DIV10_TX0_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000034)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000034)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_RMSK                                                         0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_BIST_RCLK_EN_BMSK                                            0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_BIST_RCLK_EN_SHFT                                             0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_TX_RCLK_LPB_EN_BMSK                                          0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_TX_RCLK_LPB_EN_SHFT                                           0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_SER_LPB_EN_BMSK                                              0x18
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_SER_LPB_EN_SHFT                                               0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_LPB_PATH_SEL_BMSK                                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_LPB_PATH_SEL_SHFT                                             0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_TRAN_LPB_DIV10_SEL_BMSK                                       0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG1_TRAN_LPB_DIV10_SEL_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000038)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000038)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_RMSK                                                         0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_LPB_DIV2_SEL_BMSK                                            0x30
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_LPB_DIV2_SEL_SHFT                                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_LPB_CLK_DELAY_DIV2_TX1_BMSK                                   0xc
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_LPB_CLK_DELAY_DIV2_TX1_SHFT                                   0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_LPB_CLK_DELAY_DIV2_TX0_BMSK                                   0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LPB_CFG2_LPB_CLK_DELAY_DIV2_TX0_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_ADDR                                           (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000003c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_OFFS                                           (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000003c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_RMSK                                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_RES_CODE_TX0_MUX_BMSK                                0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_RES_CODE_TX0_MUX_SHFT                                 0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_RES_CODE_TX0_BMSK                                    0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX_RES_CODE_TX0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_ADDR                                          (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000040)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_OFFS                                          (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000040)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_RMSK                                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_RES_CODE_TX1_MUX_BMSK                               0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_RES_CODE_TX1_MUX_SHFT                                0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_RES_CODE_TX1_BMSK                                   0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_TX1_RES_CODE_TX1_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_ADDR                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000044)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_OFFS                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000044)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_RMSK                                         0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_RES_CODE_LANE_OFFSET_TX0_BMSK                0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX0_RES_CODE_LANE_OFFSET_TX0_SHFT                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_ADDR                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000048)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_OFFS                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000048)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_RMSK                                         0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_RES_CODE_LANE_OFFSET_TX1_BMSK                0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RES_CODE_LANE_OFFSET_TX1_RES_CODE_LANE_OFFSET_TX1_SHFT                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_ADDR                                          (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000004c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_OFFS                                          (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000004c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_RMSK                                                 0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_BMSK                                  0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_SHFT                                  0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_EN_BMSK                                   0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_SERDES_BYP_EN_OUT_SERDES_BYP_EN_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000050)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000050)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_DEBUG_CLK_SEL_BMSK                                      0xf0
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_DEBUG_CLK_SEL_SHFT                                       0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_DEBUGBUS_SEL_BMSK                                        0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS_SEL_DEBUGBUS_SEL_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000054)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000054)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_RMSK                                               0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_TX_EN_LANE1_BMSK                                   0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_TX_EN_LANE1_SHFT                                   0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_TX_EN_LANE0_BMSK                                   0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRANSCEIVER_BIAS_EN_TX_EN_LANE0_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000058)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000058)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_RMSK                                                    0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_MUX_BMSK                                 0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_MUX_SHFT                                  0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_MUX_BMSK                                  0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_MUX_SHFT                                  0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_DRVR_EN_BMSK                                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_DRVR_EN_SHFT                                             0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_BMSK                                      0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_SHFT                                      0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_BMSK                                      0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000005c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000005c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_RMSK                                                        0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_TX_POL_INV_LANE1_BMSK                                       0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_TX_POL_INV_LANE1_SHFT                                       0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_TX_POL_INV_LANE0_BMSK                                       0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TX_POL_INV_TX_POL_INV_LANE0_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_ADDR                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000060)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_OFFS                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000060)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_RMSK                                        0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_PAR_RATE_BMSK                               0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_PAR_RATE_SHFT                               0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_IDLE_EN_BMSK                                0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_PARRATE_REC_DETECT_IDLE_EN_IDLE_EN_SHFT                                0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_1_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000064)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_1_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000064)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_1_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_1_LANE_MODE1_BMSK                                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_1_LANE_MODE1_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_2_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000068)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_2_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000068)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_2_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_2_LANE_MODE2_BMSK                                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_MODE_2_LANE_MODE2_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL1_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000006c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL1_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000006c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL1_RMSK                                                         0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL1_ATB_SEL1_BMSK                                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL1_ATB_SEL1_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL2_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000070)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL2_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000070)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL2_RMSK                                                          0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL2_ATB_SEL2_BMSK                                                 0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_ATB_SEL2_ATB_SEL2_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_ADDR                                            (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000074)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_OFFS                                            (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000074)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_RMSK                                                   0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_RSYNC_MUX_BMSK                                         0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_RSYNC_MUX_SHFT                                         0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_RSYNC_BMSK                                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_RSYNC_SHFT                                             0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_TSYNC_MUX_BMSK                                         0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_TSYNC_MUX_SHFT                                         0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_TSYNC_BMSK                                             0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_RESET_GEN_MUXES_TSYNC_SHFT                                             0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_ADDR                                           (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000078)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_OFFS                                           (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000078)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_RMSK                                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_RSVD_BMSK                                            0xfe
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_RSVD_SHFT                                             0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_EMP_EN_BMSK                                           0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_TRAN_DRVR_EMP_EN_EMP_EN_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_VMODE_CTRL1_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000007c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_VMODE_CTRL1_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000007c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_VMODE_CTRL1_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_VMODE_CTRL1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_VMODE_CTRL1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_VMODE_CTRL1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_VMODE_CTRL1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_VMODE_CTRL1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_VMODE_CTRL1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_VMODE_CTRL1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_VMODE_CTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_VMODE_CTRL1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_VMODE_CTRL1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_VMODE_CTRL1_VMODE_CTRL1_BMSK                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_VMODE_CTRL1_VMODE_CTRL1_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_ADDR                                            (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000080)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_OFFS                                            (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000080)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_RMSK                                                  0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_RSVD_BMSK                                             0xf8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_RSVD_SHFT                                              0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_LANE_PWRDN_B_BMSK                                      0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_LANE_PWRDN_B_SHFT                                      0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_RCLK_OUT_INV_BMSK                                      0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_RCLK_OUT_INV_SHFT                                      0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_TCLK_OUT_INV_BMSK                                      0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LANE_DIG_CONFIG_TCLK_OUT_INV_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000084)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000084)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_LDO_VREG_LVL_BMSK                                          0xc0
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_LDO_VREG_LVL_SHFT                                           0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_LDO_BIAS_SEL_BMSK                                          0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_LDO_BIAS_SEL_SHFT                                           0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_LDO_VREF_SEL_BMSK                                          0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_LDO_VREF_SEL_SHFT                                           0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_LDO_HIGHZ_BMSK                                              0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_LDO_HIGHZ_SHFT                                              0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_LDO_TEST_EN_BMSK                                            0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_LDO_TEST_EN_SHFT                                            0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_LDO_EN_BMSK                                                 0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_LDO_CONFIG_LDO_EN_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DIG_BKUP_CTRL_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000088)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DIG_BKUP_CTRL_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000088)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DIG_BKUP_CTRL_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DIG_BKUP_CTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DIG_BKUP_CTRL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DIG_BKUP_CTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DIG_BKUP_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DIG_BKUP_CTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DIG_BKUP_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DIG_BKUP_CTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DIG_BKUP_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DIG_BKUP_CTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DIG_BKUP_CTRL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DIG_BKUP_CTRL_RSVD_BMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DIG_BKUP_CTRL_RSVD_SHFT                                                0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS0_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000008c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS0_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000008c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS0_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS0_DEBUG_BUS_7_0_BMSK                                         0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS0_DEBUG_BUS_7_0_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS1_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000090)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS1_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000090)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS1_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS1_DEBUG_BUS_15_8_BMSK                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS1_DEBUG_BUS_15_8_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS2_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000094)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS2_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000094)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS2_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS2_DEBUG_BUS_23_16_BMSK                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS2_DEBUG_BUS_23_16_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS3_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x00000098)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS3_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x00000098)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS3_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS3_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS3_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS3_DEBUG_BUS_31_24_BMSK                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_DEBUG_BUS3_DEBUG_BUS_31_24_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_READ_OFFSETCODE_ADDR                                            (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE      + 0x0000009c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_READ_OFFSETCODE_OFFS                                            (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_EDP_LANE_TX0_EDP_LANE_REG_BASE_OFFS + 0x0000009c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_READ_OFFSETCODE_RMSK                                                  0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_READ_OFFSETCODE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_READ_OFFSETCODE_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_READ_OFFSETCODE_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_READ_OFFSETCODE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_READ_OFFSETCODE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_READ_OFFSETCODE_READ_OFFSETCODE_STATUS_BMSK                           0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX0_READ_OFFSETCODE_READ_OFFSETCODE_STATUS_SHFT                            0x0

/*----------------------------------------------------------------------------
 * MODULE: AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE
 *--------------------------------------------------------------------------*/

#define AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE                                       (MDSS_BASE      + 0x000c5600)
#define AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS                                  0x000c5600

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000000)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000000)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_RMSK                                                    0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_DISABLE_LPB_TX_CLKGATE_BMSK                             0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_DISABLE_LPB_TX_CLKGATE_SHFT                              0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_TXONLY_CLOCK_EDGE_BMSK                                   0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_TXONLY_CLOCK_EDGE_SHFT                                   0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_GATED_CLK_EN_BMSK                                        0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_GATED_CLK_EN_SHFT                                        0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_CLKBUF_EN_LANE1_BMSK                                     0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_CLKBUF_EN_LANE1_SHFT                                     0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_CLKBUF_EN_LANE0_BMSK                                     0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_CLKBUF_ENABLE_CLKBUF_EN_LANE0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_EMP_POST1_LVL_ADDR                                           (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000004)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_EMP_POST1_LVL_OFFS                                           (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000004)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_EMP_POST1_LVL_RMSK                                                 0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_EMP_POST1_LVL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_EMP_POST1_LVL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_EMP_POST1_LVL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_EMP_POST1_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_EMP_POST1_LVL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_EMP_POST1_LVL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_EMP_POST1_LVL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_EMP_POST1_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_EMP_POST1_LVL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_EMP_POST1_LVL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_EMP_POST1_LVL_EMP_POST1_LVL_BMSK                                   0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_EMP_POST1_LVL_EMP_POST1_LVL_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POST2_EMPH_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000008)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POST2_EMPH_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000008)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POST2_EMPH_RMSK                                                     0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POST2_EMPH_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POST2_EMPH_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POST2_EMPH_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POST2_EMPH_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POST2_EMPH_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POST2_EMPH_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POST2_EMPH_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POST2_EMPH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POST2_EMPH_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POST2_EMPH_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POST2_EMPH_POST2_EMPH_BMSK                                          0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POST2_EMPH_POST2_EMPH_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_ADDR                                         (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000000c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_OFFS                                         (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000000c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_RMSK                                               0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_TX_BOOST_LVL_DN_BMSK                               0x38
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_TX_BOOST_LVL_DN_SHFT                                0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_TX_BOOST_LVL_UP_BMSK                                0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BOOST_LVL_UP_DN_TX_BOOST_LVL_UP_SHFT                                0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_ADDR                                      (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000010)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_OFFS                                      (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000010)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_RMSK                                             0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_TX_IDLE_LVL_BMSK                                 0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_IDLE_LVL_LARGE_AMP_TX_IDLE_LVL_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000014)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000014)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_RMSK                                                       0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_TX_DRV_LVL_BMSK                                            0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_TX_DRV_LVL_SHFT                                             0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_ADDR                                          (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000018)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_OFFS                                          (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000018)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_RMSK                                                0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_TX_LVL_UPDATE_BMSK                                  0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_TX_LVL_UPDATE_SHFT                                   0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_TX_DRV_LVL_OFFSET_BMSK                               0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_DRV_LVL_OFFSET_TX_DRV_LVL_OFFSET_SHFT                               0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_ADDR                                             (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000001c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_OFFS                                             (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000001c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_RMSK                                                    0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_RESET_RSYNC_EN_MUX_BMSK                                 0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_RESET_RSYNC_EN_MUX_SHFT                                 0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_RESET_RSYNC_EN_BMSK                                     0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_RESET_RSYNC_EN_SHFT                                     0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_RESET_TSYNC_EN_MUX_BMSK                                 0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_RESET_TSYNC_EN_MUX_SHFT                                 0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_RESET_TSYNC_EN_BMSK                                     0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_TSYNC_EN_RESET_TSYNC_EN_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000020)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000020)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_RMSK                                                         0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_BOOST_EN_BMSK                                                0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_BOOST_EN_SHFT                                                 0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_SPARE_FOR_LDO_BMSK                                           0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_SPARE_FOR_LDO_SHFT                                            0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_PREEMPH_BMSK                                                 0x3e
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_PREEMPH_SHFT                                                  0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_PRE_EN_BMSK                                                   0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PRE_EMPH_PRE_EN_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_INTERFACE_SELECT_ADDR                                           (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000024)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_INTERFACE_SELECT_OFFS                                           (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000024)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_INTERFACE_SELECT_RMSK                                                  0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_INTERFACE_SELECT_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_INTERFACE_SELECT_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_INTERFACE_SELECT_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_INTERFACE_SELECT_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_INTERFACE_SELECT_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_INTERFACE_SELECT_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_INTERFACE_SELECT_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_INTERFACE_SELECT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_INTERFACE_SELECT_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_INTERFACE_SELECT_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_INTERFACE_SELECT_SEL_10B_8B_BMSK                                       0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_INTERFACE_SELECT_SEL_10B_8B_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000028)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000028)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_RMSK                                                           0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_TX_BAND_MUX_BMSK                                               0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_TX_BAND_MUX_SHFT                                               0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_TX_BAND_BMSK                                                   0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_BAND_TX_BAND_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SLEW_CNTL_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000002c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SLEW_CNTL_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000002c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SLEW_CNTL_RMSK                                                         0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SLEW_CNTL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SLEW_CNTL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SLEW_CNTL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SLEW_CNTL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SLEW_CNTL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SLEW_CNTL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SLEW_CNTL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SLEW_CNTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SLEW_CNTL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SLEW_CNTL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SLEW_CNTL_SLEW_CNTL_BMSK                                               0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SLEW_CNTL_SLEW_CNTL_SHFT                                               0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000030)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000030)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_RMSK                                                         0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_LPB_DIV10_SEL_DIG_BMSK                                       0x30
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_LPB_DIV10_SEL_DIG_SHFT                                        0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_LPB_CLK_DELAY_DIV10_TX1_BMSK                                  0xc
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_LPB_CLK_DELAY_DIV10_TX1_SHFT                                  0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_LPB_CLK_DELAY_DIV10_TX0_BMSK                                  0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG0_LPB_CLK_DELAY_DIV10_TX0_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000034)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000034)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_RMSK                                                         0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_BIST_RCLK_EN_BMSK                                            0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_BIST_RCLK_EN_SHFT                                             0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_TX_RCLK_LPB_EN_BMSK                                          0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_TX_RCLK_LPB_EN_SHFT                                           0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_SER_LPB_EN_BMSK                                              0x18
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_SER_LPB_EN_SHFT                                               0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_LPB_PATH_SEL_BMSK                                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_LPB_PATH_SEL_SHFT                                             0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_TRAN_LPB_DIV10_SEL_BMSK                                       0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG1_TRAN_LPB_DIV10_SEL_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000038)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000038)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_RMSK                                                         0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_LPB_DIV2_SEL_BMSK                                            0x30
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_LPB_DIV2_SEL_SHFT                                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_LPB_CLK_DELAY_DIV2_TX1_BMSK                                   0xc
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_LPB_CLK_DELAY_DIV2_TX1_SHFT                                   0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_LPB_CLK_DELAY_DIV2_TX0_BMSK                                   0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LPB_CFG2_LPB_CLK_DELAY_DIV2_TX0_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_ADDR                                           (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000003c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_OFFS                                           (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000003c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_RMSK                                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_RES_CODE_TX0_MUX_BMSK                                0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_RES_CODE_TX0_MUX_SHFT                                 0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_RES_CODE_TX0_BMSK                                    0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX_RES_CODE_TX0_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_ADDR                                          (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000040)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_OFFS                                          (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000040)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_RMSK                                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_RES_CODE_TX1_MUX_BMSK                               0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_RES_CODE_TX1_MUX_SHFT                                0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_RES_CODE_TX1_BMSK                                   0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_TX1_RES_CODE_TX1_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_ADDR                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000044)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_OFFS                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000044)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_RMSK                                         0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_RES_CODE_LANE_OFFSET_TX0_BMSK                0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX0_RES_CODE_LANE_OFFSET_TX0_SHFT                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_ADDR                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000048)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_OFFS                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000048)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_RMSK                                         0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_RES_CODE_LANE_OFFSET_TX1_BMSK                0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RES_CODE_LANE_OFFSET_TX1_RES_CODE_LANE_OFFSET_TX1_SHFT                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_ADDR                                          (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000004c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_OFFS                                          (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000004c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_RMSK                                                 0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_BMSK                                  0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_OUT_SHFT                                  0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_EN_BMSK                                   0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_SERDES_BYP_EN_OUT_SERDES_BYP_EN_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000050)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000050)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_DEBUG_CLK_SEL_BMSK                                      0xf0
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_DEBUG_CLK_SEL_SHFT                                       0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_DEBUGBUS_SEL_BMSK                                        0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS_SEL_DEBUGBUS_SEL_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000054)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000054)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_RMSK                                               0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_TX_EN_LANE1_BMSK                                   0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_TX_EN_LANE1_SHFT                                   0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_TX_EN_LANE0_BMSK                                   0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRANSCEIVER_BIAS_EN_TX_EN_LANE0_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000058)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000058)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_RMSK                                                    0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_MUX_BMSK                                 0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_MUX_SHFT                                  0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_MUX_BMSK                                  0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_MUX_SHFT                                  0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_DRVR_EN_BMSK                                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_DRVR_EN_SHFT                                             0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_BMSK                                      0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE1_SHFT                                      0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_BMSK                                      0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_HIGHZ_DRVR_EN_TX_HIGHZ_LANE0_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000005c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000005c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_RMSK                                                        0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_TX_POL_INV_LANE1_BMSK                                       0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_TX_POL_INV_LANE1_SHFT                                       0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_TX_POL_INV_LANE0_BMSK                                       0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TX_POL_INV_TX_POL_INV_LANE0_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_ADDR                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000060)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_OFFS                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000060)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_RMSK                                        0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_PAR_RATE_BMSK                               0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_PAR_RATE_SHFT                               0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_IDLE_EN_BMSK                                0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_PARRATE_REC_DETECT_IDLE_EN_IDLE_EN_SHFT                                0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_1_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000064)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_1_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000064)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_1_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_1_LANE_MODE1_BMSK                                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_1_LANE_MODE1_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_2_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000068)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_2_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000068)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_2_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_2_LANE_MODE2_BMSK                                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_MODE_2_LANE_MODE2_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL1_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000006c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL1_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000006c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL1_RMSK                                                         0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL1_ATB_SEL1_BMSK                                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL1_ATB_SEL1_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL2_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000070)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL2_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000070)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL2_RMSK                                                          0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL2_ATB_SEL2_BMSK                                                 0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_ATB_SEL2_ATB_SEL2_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_ADDR                                            (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000074)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_OFFS                                            (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000074)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_RMSK                                                   0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_RSYNC_MUX_BMSK                                         0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_RSYNC_MUX_SHFT                                         0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_RSYNC_BMSK                                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_RSYNC_SHFT                                             0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_TSYNC_MUX_BMSK                                         0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_TSYNC_MUX_SHFT                                         0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_TSYNC_BMSK                                             0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_RESET_GEN_MUXES_TSYNC_SHFT                                             0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_ADDR                                           (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000078)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_OFFS                                           (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000078)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_RMSK                                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_RSVD_BMSK                                            0xfe
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_RSVD_SHFT                                             0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_EMP_EN_BMSK                                           0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_TRAN_DRVR_EMP_EN_EMP_EN_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_VMODE_CTRL1_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000007c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_VMODE_CTRL1_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000007c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_VMODE_CTRL1_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_VMODE_CTRL1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_VMODE_CTRL1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_VMODE_CTRL1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_VMODE_CTRL1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_VMODE_CTRL1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_VMODE_CTRL1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_VMODE_CTRL1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_VMODE_CTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_VMODE_CTRL1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_VMODE_CTRL1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_VMODE_CTRL1_VMODE_CTRL1_BMSK                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_VMODE_CTRL1_VMODE_CTRL1_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_ADDR                                            (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000080)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_OFFS                                            (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000080)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_RMSK                                                  0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_RSVD_BMSK                                             0xf8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_RSVD_SHFT                                              0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_LANE_PWRDN_B_BMSK                                      0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_LANE_PWRDN_B_SHFT                                      0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_RCLK_OUT_INV_BMSK                                      0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_RCLK_OUT_INV_SHFT                                      0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_TCLK_OUT_INV_BMSK                                      0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LANE_DIG_CONFIG_TCLK_OUT_INV_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000084)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000084)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_LDO_VREG_LVL_BMSK                                          0xc0
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_LDO_VREG_LVL_SHFT                                           0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_LDO_BIAS_SEL_BMSK                                          0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_LDO_BIAS_SEL_SHFT                                           0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_LDO_VREF_SEL_BMSK                                          0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_LDO_VREF_SEL_SHFT                                           0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_LDO_HIGHZ_BMSK                                              0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_LDO_HIGHZ_SHFT                                              0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_LDO_TEST_EN_BMSK                                            0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_LDO_TEST_EN_SHFT                                            0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_LDO_EN_BMSK                                                 0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_LDO_CONFIG_LDO_EN_SHFT                                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DIG_BKUP_CTRL_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000088)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DIG_BKUP_CTRL_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000088)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DIG_BKUP_CTRL_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DIG_BKUP_CTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DIG_BKUP_CTRL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DIG_BKUP_CTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DIG_BKUP_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DIG_BKUP_CTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DIG_BKUP_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DIG_BKUP_CTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DIG_BKUP_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DIG_BKUP_CTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DIG_BKUP_CTRL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DIG_BKUP_CTRL_RSVD_BMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DIG_BKUP_CTRL_RSVD_SHFT                                                0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS0_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000008c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS0_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000008c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS0_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS0_DEBUG_BUS_7_0_BMSK                                         0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS0_DEBUG_BUS_7_0_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS1_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000090)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS1_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000090)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS1_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS1_DEBUG_BUS_15_8_BMSK                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS1_DEBUG_BUS_15_8_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS2_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000094)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS2_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000094)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS2_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS2_DEBUG_BUS_23_16_BMSK                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS2_DEBUG_BUS_23_16_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS3_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x00000098)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS3_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x00000098)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS3_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS3_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS3_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS3_DEBUG_BUS_31_24_BMSK                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_DEBUG_BUS3_DEBUG_BUS_31_24_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_READ_OFFSETCODE_ADDR                                            (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE      + 0x0000009c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_READ_OFFSETCODE_OFFS                                            (AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_EDP_LANE_TX1_EDP_LANE_REG_BASE_OFFS + 0x0000009c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_READ_OFFSETCODE_RMSK                                                  0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_READ_OFFSETCODE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_READ_OFFSETCODE_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_READ_OFFSETCODE_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_READ_OFFSETCODE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_READ_OFFSETCODE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_READ_OFFSETCODE_READ_OFFSETCODE_STATUS_BMSK                           0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_LANE_TX1_READ_OFFSETCODE_READ_OFFSETCODE_STATUS_SHFT                            0x0

/*----------------------------------------------------------------------------
 * MODULE: AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY
 *--------------------------------------------------------------------------*/

#define AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE                                                       (MDSS_BASE      + 0x000c5a00)
#define AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS                                                  0x000c5a00

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID0_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000000)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID0_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000000)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID0_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID0_STEP_7_0_BMSK                                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID0_STEP_7_0_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID1_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000004)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID1_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000004)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID1_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID1_STEP_15_8_BMSK                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID1_STEP_15_8_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID2_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000008)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID2_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000008)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID2_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID2_MINOR_7_0_BMSK                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID2_MINOR_7_0_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID3_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000000c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID3_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000000c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID3_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID3_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID3_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID3_MAJOR_BMSK                                              0xf0
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID3_MAJOR_SHFT                                               0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID3_MINOR_11_8_BMSK                                          0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_REVISION_ID3_MINOR_11_8_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_ADDR                                                       (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000010)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_OFFS                                                       (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000010)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_RMSK                                                             0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_DP_CFG_SPARE_BMSK                                                0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_DP_CFG_SPARE_SHFT                                                 0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_AUX_RESET_BMSK                                                   0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_AUX_RESET_SHFT                                                    0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_CORE_RESET_TSYNC_BMSK                                            0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_CORE_RESET_TSYNC_SHFT                                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_PLL_START_BMSK                                                    0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_PLL_START_SHFT                                                    0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_PLL_RESET_BMSK                                                    0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_PLL_RESET_SHFT                                                    0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_SW_RESET_BMSK                                                     0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_SW_RESET_SHFT                                                     0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_RETIMING_ENABLE_BMSK                                              0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_RETIMING_ENABLE_SHFT                                              0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_ADDR                                                     (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000014)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_OFFS                                                     (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000014)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_RMSK                                                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_C_READY_MUX_BMSK                                               0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_C_READY_MUX_SHFT                                                0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_SW_C_READY_BMSK                                                0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_SW_C_READY_SHFT                                                 0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_TCLK_LINKCLK_SEL_BMSK                                          0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_TCLK_LINKCLK_SEL_SHFT                                           0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_DISABLE_CGC_EN_BMSK                                            0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_DISABLE_CGC_EN_SHFT                                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_RT_BUFFER_LANE3_EN_BMSK                                         0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_RT_BUFFER_LANE3_EN_SHFT                                         0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_RT_BUFFER_LANE2_EN_BMSK                                         0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_RT_BUFFER_LANE2_EN_SHFT                                         0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_RT_BUFFER_LANE1_EN_BMSK                                         0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_RT_BUFFER_LANE1_EN_SHFT                                         0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_RT_BUFFER_LANE0_EN_BMSK                                         0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_1_RT_BUFFER_LANE0_EN_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_ADDR                                                     (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000018)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_OFFS                                                     (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000018)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_RMSK                                                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_DEBUG_CLK_DIV_BMSK                                             0xf0
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_DEBUG_CLK_DIV_SHFT                                              0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_DEBUG_CLK_SEL_BMSK                                              0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_CFG_2_DEBUG_CLK_SEL_SHFT                                              0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000001c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000001c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_SPARE_PWRDN_B_BMSK                                            0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_SPARE_PWRDN_B_SHFT                                             0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_DP_CLAMP_EN_B_BMSK                                            0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_DP_CLAMP_EN_B_SHFT                                             0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_PLL_PWRDN_B_BMSK                                              0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_PLL_PWRDN_B_SHFT                                               0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_LANE_2_3_PWRDN_B_BMSK                                         0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_LANE_2_3_PWRDN_B_SHFT                                          0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_LANE_0_1_PWRDN_B_BMSK                                          0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_LANE_0_1_PWRDN_B_SHFT                                          0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_AUX_PWRDN_B_BMSK                                               0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_AUX_PWRDN_B_SHFT                                               0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_PSR_PWRDN_BMSK                                                 0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_PSR_PWRDN_SHFT                                                 0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_PWRDN_B_BMSK                                                   0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_PD_CTL_PWRDN_B_SHFT                                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_ADDR                                                      (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000020)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_OFFS                                                      (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000020)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_RMSK                                                            0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_REFGEN_REQ_BMSK                                                 0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_REFGEN_REQ_SHFT                                                  0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_RETIME_BUFFER_SIZE_BMSK                                         0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_RETIME_BUFFER_SIZE_SHFT                                          0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_LINK_CLOCK_SEL_MUX_BMSK                                         0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_LINK_CLOCK_SEL_MUX_SHFT                                          0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_LINK_CLOCK_SEL_BMSK                                             0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_LINK_CLOCK_SEL_SHFT                                              0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_PAR_RATE_BMSK                                                    0xc
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_PAR_RATE_SHFT                                                    0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_TX_BAND_BMSK                                                     0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MODE_TX_BAND_SHFT                                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000024)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000024)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_RMSK                                                         0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_AUX_FORCE_TX_EN_BMSK                                         0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_AUX_FORCE_TX_EN_SHFT                                         0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_AUX_BYPASS_BMSK                                              0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_AUX_BYPASS_SHFT                                              0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_RSVD_BMSK                                                    0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG0_RSVD_SHFT                                                    0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG1_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000028)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG1_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000028)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG1_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG1_AUX_DCTRL_7_0_BMSK                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG1_AUX_DCTRL_7_0_SHFT                                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG2_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000002c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG2_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000002c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG2_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG2_AUX_DCTRL_15_8_BMSK                                         0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG2_AUX_DCTRL_15_8_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000030)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000030)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_AUX_FORCE_RX_EN_BMSK                                        0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_AUX_FORCE_RX_EN_SHFT                                         0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_AUX_TX_PRECHARGE_BMSK                                       0x70
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_AUX_TX_PRECHARGE_SHFT                                        0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_AUX_PARALLEL_LBK_BMSK                                        0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_AUX_PARALLEL_LBK_SHFT                                        0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_AUX_BYPASS_MANCH_LBK_BMSK                                    0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_AUX_BYPASS_MANCH_LBK_SHFT                                    0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_AUX_SERIAL_LBK_BMSK                                          0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_AUX_SERIAL_LBK_SHFT                                          0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_AUX_NEAREND_LBK_BMSK                                         0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG3_AUX_NEAREND_LBK_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG4_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000034)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG4_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000034)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG4_RMSK                                                        0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG4_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG4_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG4_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG4_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG4_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG4_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG4_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG4_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG4_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG4_AUX_TX_MANCH_HALFCYC_BMSK                                   0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG4_AUX_TX_MANCH_HALFCYC_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG5_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000038)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG5_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000038)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG5_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG5_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG5_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG5_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG5_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG5_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG5_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG5_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG5_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG5_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG5_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG5_AUX_RX_MANCH_TWOCYC_BMSK                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG5_AUX_RX_MANCH_TWOCYC_SHFT                                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG6_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000003c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG6_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000003c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG6_RMSK                                                        0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG6_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG6_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG6_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG6_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG6_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG6_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG6_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG6_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG6_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG6_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG6_AUX_RX_MANCH_HALFCYC_BMSK                                   0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG6_AUX_RX_MANCH_HALFCYC_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG7_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000040)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG7_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000040)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG7_RMSK                                                         0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG7_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG7_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG7_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG7_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG7_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG7_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG7_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG7_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG7_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG7_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG7_AUX_RX_MANCH_CYCJITTER_BMSK                                  0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG7_AUX_RX_MANCH_CYCJITTER_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000044)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000044)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_AUX_TX_PREAMBLE_BMSK                                        0xf0
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_AUX_TX_PREAMBLE_SHFT                                         0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_AUX_RX_PREAMBLE_BMSK                                         0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG8_AUX_RX_PREAMBLE_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_ADDR                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000048)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_OFFS                                                  (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000048)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_RMSK                                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_OVERRIDE_TWOCYC_BMSK                                        0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_OVERRIDE_TWOCYC_SHFT                                         0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_OVERRIDE_HALFCYC_BMSK                                       0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_OVERRIDE_HALFCYC_SHFT                                        0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_OVERRIDE_AUX_TIMING_BMSK                                    0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_OVERRIDE_AUX_TIMING_SHFT                                     0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_AUX_RX_CFG_SPARE_BMSK                                       0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_AUX_RX_CFG_SPARE_SHFT                                        0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_AUX_RX_ZERO_IDLE_CNT_BMSK                                    0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG9_AUX_RX_ZERO_IDLE_CNT_SHFT                                    0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000004c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000004c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_RMSK                                                       0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_AUX_RX_START_DEBOUNCE_ENA_BMSK                             0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_AUX_RX_START_DEBOUNCE_ENA_SHFT                              0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_AUX_RXOUT_DEBOUNCE_ENA_BMSK                                0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_AUX_RXOUT_DEBOUNCE_ENA_SHFT                                 0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_AUX_DBOUNCE_SPARE_BMSK                                      0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG10_AUX_DBOUNCE_SPARE_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000050)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000050)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_RMSK                                                        0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_DLY_AUX_RX_VALID_BMSK                                       0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_DLY_AUX_RX_VALID_SHFT                                       0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_USE_AUXRX_GEN1_BMSK                                         0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG11_USE_AUXRX_GEN1_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG12_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000054)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG12_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000054)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG12_RMSK                                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG12_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG12_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG12_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG12_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG12_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG12_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG12_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG12_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG12_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG12_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG12_AUX_DCTRL_23_16_BMSK                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_CFG12_AUX_DCTRL_23_16_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000058)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000058)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_RMSK                                              0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_TX_REQ_ERR_MASK_BMSK                          0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_TX_REQ_ERR_MASK_SHFT                           0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_ALIGN_ERR_MASK_BMSK                         0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_ALIGN_ERR_MASK_SHFT                         0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_SYNC_ERR_MASK_BMSK                          0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_SYNC_ERR_MASK_SHFT                          0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_DEC_ERR_MASK_BMSK                           0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_DEC_ERR_MASK_SHFT                           0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_STOP_ERR_MASK_BMSK                          0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_MASK_AUX_RX_STOP_ERR_MASK_SHFT                          0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_ADDR                                       (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000005c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_OFFS                                       (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000005c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_RMSK                                             0x9f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_GLOBE_REQ_CLR_CMD_BMSK                       0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_GLOBE_REQ_CLR_CMD_SHFT                        0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_TX_REQ_ERR_CLR_BMSK                          0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_TX_REQ_ERR_CLR_SHFT                           0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_ALIGN_ERR_CLR_BMSK                         0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_ALIGN_ERR_CLR_SHFT                         0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_SYNC_ERR_CLR_BMSK                          0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_SYNC_ERR_CLR_SHFT                          0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_DEC_ERR_CLR_BMSK                           0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_DEC_ERR_CLR_SHFT                           0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_STOP_ERR_CLR_BMSK                          0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_CLEAR_AUX_RX_STOP_ERR_CLR_SHFT                          0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_ADDR                                              (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000060)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_OFFS                                              (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000060)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_RMSK                                                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_AUX_BIST_MODE_BMSK                                      0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_AUX_BIST_MODE_SHFT                                       0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_AUX_BIST_SEL_BMSK                                       0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_AUX_BIST_SEL_SHFT                                        0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_AUX_TX_PATGEN_EN_BMSK                                   0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_AUX_TX_PATGEN_EN_SHFT                                    0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_AUX_TX_FIXPAT_BMSK                                      0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_AUX_TX_FIXPAT_SHFT                                       0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_EN_BMSK                                  0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_EN_SHFT                                  0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_GEN_SHORT_BMSK                           0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_GEN_SHORT_SHFT                           0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_ERR_EN_BMSK                              0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_ERR_EN_SHFT                              0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_CLR_ERROR_COUNT_BMSK                     0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_CFG_AUX_RX_PRBS_CHK_CLR_ERROR_COUNT_SHFT                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_SEED_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000064)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_SEED_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000064)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_SEED_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_SEED_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_SEED_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_SEED_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_SEED_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_SEED_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_SEED_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_SEED_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_SEED_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_SEED_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_SEED_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_SEED_AUX_BIST_PRBS_SEED_BMSK                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_SEED_AUX_BIST_PRBS_SEED_SHFT                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_POLY_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000068)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_POLY_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000068)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_POLY_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_POLY_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_POLY_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_POLY_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_POLY_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_POLY_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_POLY_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_POLY_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_POLY_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_POLY_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_POLY_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_POLY_AUX_BIST_PRBS_POLY_BMSK                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_PRBS_POLY_AUX_BIST_PRBS_POLY_SHFT                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_ADDR                                   (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000006c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_OFFS                                   (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000006c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_RMSK                                         0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_AUX_TX_PROG_PAT_16B_7_0_BMSK                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB_AUX_TX_PROG_PAT_16B_7_0_SHFT                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_ADDR                                   (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000070)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_OFFS                                   (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000070)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_RMSK                                         0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_AUX_TX_PROG_PAT_16B_15_8_BMSK                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB_AUX_TX_PROG_PAT_16B_15_8_SHFT                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_ADDR                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000074)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_OFFS                                                   (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000074)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_RMSK                                                          0xb
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_FORCE_CLKBUF_EN_BMSK                                          0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_FORCE_CLKBUF_EN_SHFT                                          0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_VCO_DIV_CLK_SEL_BMSK                                          0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_VCO_DIV_VCO_DIV_CLK_SEL_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000078)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000078)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_RMSK                                                      0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_SW_C_EXT_CLKBUF_EN_MUX_BMSK                               0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_SW_C_EXT_CLKBUF_EN_MUX_SHFT                                0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_SW_C_EXT_CLKBUF_EN_BMSK                                   0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_SW_C_EXT_CLKBUF_EN_SHFT                                    0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_SW_TSYNC_DONE_MUX_BMSK                                     0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_SW_TSYNC_DONE_MUX_SHFT                                     0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_SW_TSYNC_DONE_BMSK                                         0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_SW_TSYNC_DONE_SHFT                                         0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_SW_EXT_TSYNC_MUX_BMSK                                      0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_SW_EXT_TSYNC_MUX_SHFT                                      0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_SW_EXT_TSYNC_BMSK                                          0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TSYNC_OVRD_SW_EXT_TSYNC_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_ADDR                                          (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000007c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_OFFS                                          (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000007c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_RMSK                                                 0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_L0_CORE_TXCLK_EN_BMSK                                0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_L0_CORE_TXCLK_EN_SHFT                                0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_L0_CORE_PLL_EN_BMSK                                  0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_LANE_CTL_L0_CORE_PLL_EN_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_ADDR                                         (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000080)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_OFFS                                         (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000080)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_RMSK                                               0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TX_HDR_PRBS_SEL_BMSK                       0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TX_HDR_PRBS_SEL_SHFT                        0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TCLK_SEL_BMSK                              0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TCLK_SEL_SHFT                               0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TX_GEN_EN_BMSK                             0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_TX_GEN_EN_SHFT                              0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_RX_PRBS_CHK_EN_BMSK                         0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_RX_PRBS_CHK_EN_SHFT                         0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_RX_PRBS_GEN_SHORT_BMSK                      0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_RX_PRBS_GEN_SHORT_SHFT                      0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_ERROR_INJECT_BMSK                           0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_ERROR_INJECT_SHFT                           0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_ERROR_CLEAR_BMSK                            0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG0_L0_BIST_ERROR_CLEAR_SHFT                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_ADDR                                         (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000084)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_OFFS                                         (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000084)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_RMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_RX_RESET_PCS_BMSK                          0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_RX_RESET_PCS_SHFT                           0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_TX_RESET_PCS_BMSK                          0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_TX_RESET_PCS_SHFT                           0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_MODE_BMSK                                  0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG1_L0_BIST_MODE_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG2_ADDR                                         (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000088)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG2_OFFS                                         (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000088)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG2_RMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG2_L0_HEADER_PAT_7_0_BMSK                             0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG2_L0_HEADER_PAT_7_0_SHFT                              0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_ADDR                                         (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000008c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_OFFS                                         (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000008c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_RMSK                                                0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_L0_BIST_TX_MASK_BMSK                                0xc
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_L0_BIST_TX_MASK_SHFT                                0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_L0_HEADER_PAT_9_8_BMSK                              0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_CFG3_L0_HEADER_PAT_9_8_SHFT                              0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_ADDR                                   (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000090)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_OFFS                                   (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000090)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_RMSK                                         0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_L0_PRBS_SEED_7_0_BMSK                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0_L0_PRBS_SEED_7_0_SHFT                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_ADDR                                   (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000094)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_OFFS                                   (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000094)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_RMSK                                          0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_L0_PRBS_SEED_9_8_BMSK                         0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1_L0_PRBS_SEED_9_8_SHFT                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_ADDR                                     (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000098)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_OFFS                                     (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000098)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_RMSK                                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_L0_PRBS_POLY_7_0_BMSK                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN0_L0_PRBS_POLY_7_0_SHFT                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_ADDR                                     (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000009c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_OFFS                                     (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000009c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_RMSK                                            0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_L0_PRBS_POLY_9_8_BMSK                           0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_PATTERN1_L0_PRBS_POLY_9_8_SHFT                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_ADDR                                          (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000a0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_OFFS                                          (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000a0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_RMSK                                                 0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_L1_CORE_TXCLK_EN_BMSK                                0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_L1_CORE_TXCLK_EN_SHFT                                0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_L1_CORE_PLL_EN_BMSK                                  0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_LANE_CTL_L1_CORE_PLL_EN_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_ADDR                                         (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000a4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_OFFS                                         (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000a4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_RMSK                                               0x7f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TX_HDR_PRBS_SEL_BMSK                       0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TX_HDR_PRBS_SEL_SHFT                        0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TCLK_SEL_BMSK                              0x20
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TCLK_SEL_SHFT                               0x5
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TX_GEN_EN_BMSK                             0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_TX_GEN_EN_SHFT                              0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_RX_PRBS_CHK_EN_BMSK                         0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_RX_PRBS_CHK_EN_SHFT                         0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_RX_PRBS_GEN_SHORT_BMSK                      0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_RX_PRBS_GEN_SHORT_SHFT                      0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_ERROR_INJECT_BMSK                           0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_ERROR_INJECT_SHFT                           0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_ERROR_CLEAR_BMSK                            0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG0_L1_BIST_ERROR_CLEAR_SHFT                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_ADDR                                         (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000a8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_OFFS                                         (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000a8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_RMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_RX_RESET_PCS_BMSK                          0x80
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_RX_RESET_PCS_SHFT                           0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_TX_RESET_PCS_BMSK                          0x40
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_TX_RESET_PCS_SHFT                           0x6
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_MODE_BMSK                                  0x3f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG1_L1_BIST_MODE_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG2_ADDR                                         (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000ac)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG2_OFFS                                         (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000ac)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG2_RMSK                                               0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG2_L1_HEADER_PAT_7_0_BMSK                             0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG2_L1_HEADER_PAT_7_0_SHFT                              0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_ADDR                                         (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000b0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_OFFS                                         (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000b0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_RMSK                                                0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_L1_BIST_TX_MASK_BMSK                                0xc
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_L1_BIST_TX_MASK_SHFT                                0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_L1_HEADER_PAT_9_8_BMSK                              0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_CFG3_L1_HEADER_PAT_9_8_SHFT                              0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_ADDR                                   (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000b4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_OFFS                                   (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000b4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_RMSK                                         0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_L1_PRBS_SEED_7_0_BMSK                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0_L1_PRBS_SEED_7_0_SHFT                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_ADDR                                   (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000b8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_OFFS                                   (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000b8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_RMSK                                          0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_L1_PRBS_SEED_9_8_BMSK                         0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1_L1_PRBS_SEED_9_8_SHFT                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_ADDR                                     (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000bc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_OFFS                                     (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000bc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_RMSK                                           0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_L1_PRBS_POLY_7_0_BMSK                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN0_L1_PRBS_POLY_7_0_SHFT                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_ADDR                                     (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000c0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_OFFS                                     (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000c0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_RMSK                                            0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_L1_PRBS_POLY_9_8_BMSK                           0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_PATTERN1_L1_PRBS_POLY_9_8_SHFT                           0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_ADDR                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000c4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_OFFS                                                 (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000c4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_RMSK                                                        0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_MISR_CLEAR_BMSK                                             0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_MISR_CLEAR_SHFT                                             0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_MISR_ENABLE_BMSK                                            0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_CTRL_MISR_ENABLE_SHFT                                            0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS_SEL_ADDR                                             (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000c8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS_SEL_OFFS                                             (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000c8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS_SEL_RMSK                                                   0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS_SEL_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS_SEL_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS_SEL_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS_SEL_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS_SEL_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS_SEL_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS_SEL_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS_SEL_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS_SEL_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS_SEL_DEBUG_BUS_SEL_BMSK                                     0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS_SEL_DEBUG_BUS_SEL_SHFT                                      0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE0_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000cc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE0_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000cc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE0_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE0_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE0_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE0_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE0_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE0_EDPPHY_SPARE_7_0_BMSK                                         0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE0_EDPPHY_SPARE_7_0_SHFT                                          0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE1_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000d0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE1_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000d0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE1_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE1_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE1_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE1_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE1_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE1_EDPPHY_SPARE_15_8_BMSK                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE1_EDPPHY_SPARE_15_8_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE2_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000d4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE2_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000d4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE2_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE2_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE2_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE2_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE2_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE2_EDPPHY_SPARE_23_16_BMSK                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE2_EDPPHY_SPARE_23_16_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE3_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000d8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE3_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000d8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE3_RMSK                                                          0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE3_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE3_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE3_OUT(v)      \
        out_dword(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE3_ADDR,v)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE3_ADDR,m,v,HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE3_IN)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE3_EDPPHY_SPARE_31_24_BMSK                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_SPARE3_EDPPHY_SPARE_31_24_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_ADDR                                      (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000dc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_OFFS                                      (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000dc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_RMSK                                            0x1f
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_TX_REQ_ERR_BMSK                             0x10
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_TX_REQ_ERR_SHFT                              0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_ALIGN_ERR_BMSK                            0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_ALIGN_ERR_SHFT                            0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_SYNC_ERR_BMSK                             0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_SYNC_ERR_SHFT                             0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_DEC_ERR_BMSK                              0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_DEC_ERR_SHFT                              0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_STOP_ERR_BMSK                             0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_INTERRUPT_STATUS_AUX_RX_STOP_ERR_SHFT                             0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_STATUS_ADDR                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000e0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_STATUS_OFFS                                                    (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000e0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_STATUS_RMSK                                                           0x7
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_STATUS_C_READY_BMSK                                                   0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_STATUS_C_READY_SHFT                                                   0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_STATUS_PHY_READY_BMSK                                                 0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_STATUS_PHY_READY_SHFT                                                 0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_STATUS_TSYNC_DONE_BMSK                                                0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_STATUS_TSYNC_DONE_SHFT                                                0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS0_ADDR                                          (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000e4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS0_OFFS                                          (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000e4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS0_RMSK                                                 0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS0_AUX_BIST_CHECK_DONE_BMSK                             0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS0_AUX_BIST_CHECK_DONE_SHFT                             0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS1_ADDR                                          (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000e8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS1_OFFS                                          (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000e8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS1_RMSK                                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS1_AUX_BIST_ERROR_COUNT_7_0_BMSK                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS1_AUX_BIST_ERROR_COUNT_7_0_SHFT                        0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS2_ADDR                                          (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000ec)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS2_OFFS                                          (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000ec)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS2_RMSK                                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS2_AUX_BIST_ERROR_COUNT_15_8_BMSK                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_AUX_BIST_STATUS2_AUX_BIST_ERROR_COUNT_15_8_SHFT                       0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_ADDR                                      (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000f0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_OFFS                                      (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000f0)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_RMSK                                             0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_RXCHK_HEADER_SEL_BMSK                    0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_RXCHK_HEADER_SEL_SHFT                    0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_PAT_DATA_NOT_FOUND_BMSK                  0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_PAT_DATA_NOT_FOUND_SHFT                  0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_HEADER_NOT_FOUND_BMSK                    0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_HEADER_NOT_FOUND_SHFT                    0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_CHECK_DONE_BMSK                          0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS0_L0_BIST_CHECK_DONE_SHFT                          0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_ADDR                                      (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000f4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_OFFS                                      (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000f4)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_RMSK                                            0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_L0_BIST_ERROR_COUNT_7_0_BMSK                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS1_L0_BIST_ERROR_COUNT_7_0_SHFT                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_ADDR                                      (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000f8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_OFFS                                      (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000f8)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_RMSK                                            0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_L0_BIST_ERROR_COUNT_15_8_BMSK                   0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_TX1_BIST_STATUS2_L0_BIST_ERROR_COUNT_15_8_SHFT                    0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_ADDR                                      (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x000000fc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_OFFS                                      (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x000000fc)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_RMSK                                             0xf
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_RXCHK_HEADER_SEL_BMSK                    0x8
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_RXCHK_HEADER_SEL_SHFT                    0x3
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_PAT_DATA_NOT_FOUND_BMSK                  0x4
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_PAT_DATA_NOT_FOUND_SHFT                  0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_HEADER_NOT_FOUND_BMSK                    0x2
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_HEADER_NOT_FOUND_SHFT                    0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_CHECK_DONE_BMSK                          0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS0_L1_BIST_CHECK_DONE_SHFT                          0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_ADDR                                      (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000100)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_OFFS                                      (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000100)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_RMSK                                            0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_L1_BIST_ERROR_COUNT_7_0_BMSK                    0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS1_L1_BIST_ERROR_COUNT_7_0_SHFT                     0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_ADDR                                      (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000104)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_OFFS                                      (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000104)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_RMSK                                            0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_L1_BIST_ERROR_COUNT_15_8_BMSK                   0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_TX3_BIST_STATUS2_L1_BIST_ERROR_COUNT_15_8_SHFT                    0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_STATUS_ADDR                                               (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000108)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_STATUS_OFFS                                               (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000108)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_STATUS_RMSK                                                      0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_STATUS_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_STATUS_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_STATUS_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_STATUS_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_STATUS_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_STATUS_MISR_CAPTURED_BMSK                                        0x1
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_MISR_STATUS_MISR_CAPTURED_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS000_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000010c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS000_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000010c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS000_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS000_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS000_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS000_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS000_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS000_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS000_L0_MISR_7_0_BMSK                                  0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS000_L0_MISR_7_0_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS001_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000110)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS001_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000110)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS001_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS001_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS001_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS001_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS001_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS001_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS001_L0_MISR_15_8_BMSK                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS001_L0_MISR_15_8_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS010_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000114)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS010_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000114)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS010_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS010_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS010_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS010_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS010_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS010_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS010_L0_MISR_23_16_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS010_L0_MISR_23_16_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS011_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000118)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS011_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000118)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS011_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS011_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS011_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS011_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS011_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS011_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS011_L0_MISR_31_24_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS011_L0_MISR_31_24_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS100_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000011c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS100_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000011c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS100_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS100_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS100_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS100_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS100_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS100_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS100_L0_MISR_39_32_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS100_L0_MISR_39_32_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS101_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000120)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS101_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000120)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS101_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS101_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS101_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS101_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS101_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS101_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS101_L0_MISR_47_40_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS101_L0_MISR_47_40_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS110_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000124)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS110_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000124)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS110_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS110_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS110_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS110_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS110_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS110_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS110_L0_MISR_55_48_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS110_L0_MISR_55_48_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS111_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000128)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS111_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000128)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS111_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS111_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS111_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS111_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS111_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS111_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS111_L0_MISR_63_56_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX0_MISR_STATUS111_L0_MISR_63_56_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS000_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000012c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS000_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000012c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS000_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS000_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS000_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS000_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS000_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS000_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS000_L1_MISR_7_0_BMSK                                  0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS000_L1_MISR_7_0_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS001_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000130)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS001_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000130)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS001_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS001_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS001_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS001_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS001_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS001_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS001_L1_MISR_15_8_BMSK                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS001_L1_MISR_15_8_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS010_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000134)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS010_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000134)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS010_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS010_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS010_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS010_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS010_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS010_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS010_L1_MISR_23_16_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS010_L1_MISR_23_16_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS011_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000138)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS011_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000138)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS011_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS011_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS011_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS011_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS011_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS011_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS011_L1_MISR_31_24_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS011_L1_MISR_31_24_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS100_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000013c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS100_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000013c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS100_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS100_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS100_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS100_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS100_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS100_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS100_L1_MISR_39_32_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS100_L1_MISR_39_32_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS101_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000140)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS101_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000140)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS101_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS101_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS101_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS101_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS101_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS101_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS101_L1_MISR_47_40_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS101_L1_MISR_47_40_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS110_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000144)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS110_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000144)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS110_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS110_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS110_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS110_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS110_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS110_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS110_L1_MISR_55_48_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS110_L1_MISR_55_48_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS111_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000148)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS111_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000148)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS111_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS111_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS111_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS111_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS111_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS111_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS111_L1_MISR_63_56_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX1_MISR_STATUS111_L1_MISR_63_56_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS000_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000014c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS000_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000014c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS000_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS000_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS000_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS000_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS000_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS000_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS000_L2_MISR_7_0_BMSK                                  0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS000_L2_MISR_7_0_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS001_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000150)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS001_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000150)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS001_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS001_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS001_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS001_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS001_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS001_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS001_L2_MISR_15_8_BMSK                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS001_L2_MISR_15_8_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS010_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000154)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS010_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000154)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS010_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS010_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS010_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS010_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS010_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS010_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS010_L2_MISR_23_16_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS010_L2_MISR_23_16_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS011_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000158)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS011_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000158)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS011_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS011_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS011_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS011_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS011_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS011_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS011_L2_MISR_31_24_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS011_L2_MISR_31_24_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS100_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000015c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS100_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000015c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS100_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS100_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS100_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS100_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS100_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS100_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS100_L2_MISR_39_32_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS100_L2_MISR_39_32_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS101_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000160)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS101_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000160)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS101_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS101_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS101_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS101_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS101_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS101_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS101_L2_MISR_47_40_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS101_L2_MISR_47_40_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS110_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000164)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS110_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000164)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS110_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS110_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS110_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS110_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS110_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS110_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS110_L2_MISR_55_48_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS110_L2_MISR_55_48_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS111_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000168)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS111_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000168)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS111_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS111_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS111_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS111_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS111_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS111_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS111_L2_MISR_63_56_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX2_MISR_STATUS111_L2_MISR_63_56_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS000_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000016c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS000_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000016c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS000_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS000_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS000_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS000_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS000_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS000_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS000_L3_MISR_7_0_BMSK                                  0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS000_L3_MISR_7_0_SHFT                                   0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS001_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000170)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS001_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000170)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS001_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS001_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS001_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS001_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS001_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS001_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS001_L3_MISR_15_8_BMSK                                 0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS001_L3_MISR_15_8_SHFT                                  0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS010_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000174)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS010_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000174)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS010_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS010_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS010_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS010_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS010_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS010_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS010_L3_MISR_23_16_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS010_L3_MISR_23_16_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS011_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000178)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS011_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000178)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS011_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS011_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS011_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS011_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS011_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS011_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS011_L3_MISR_31_24_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS011_L3_MISR_31_24_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS100_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000017c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS100_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000017c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS100_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS100_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS100_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS100_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS100_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS100_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS100_L3_MISR_39_32_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS100_L3_MISR_39_32_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS101_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000180)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS101_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000180)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS101_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS101_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS101_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS101_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS101_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS101_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS101_L3_MISR_47_40_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS101_L3_MISR_47_40_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS110_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000184)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS110_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000184)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS110_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS110_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS110_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS110_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS110_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS110_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS110_L3_MISR_55_48_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS110_L3_MISR_55_48_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS111_ADDR                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000188)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS111_OFFS                                        (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000188)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS111_RMSK                                              0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS111_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS111_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS111_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS111_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS111_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS111_L3_MISR_63_56_BMSK                                0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_TX3_MISR_STATUS111_L3_MISR_63_56_SHFT                                 0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS0_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x0000018c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS0_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x0000018c)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS0_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS0_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS0_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS0_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS0_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS0_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS0_DEBUG_BUS_7_0_BMSK                                        0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS0_DEBUG_BUS_7_0_SHFT                                         0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS1_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000190)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS1_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000190)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS1_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS1_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS1_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS1_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS1_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS1_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS1_DEBUG_BUS_15_8_BMSK                                       0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS1_DEBUG_BUS_15_8_SHFT                                        0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS2_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000194)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS2_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000194)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS2_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS2_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS2_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS2_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS2_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS2_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS2_DEBUG_BUS_23_16_BMSK                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS2_DEBUG_BUS_23_16_SHFT                                       0x0

#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS3_ADDR                                                (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE      + 0x00000198)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS3_OFFS                                                (AHB2EDPPHY_CM_DPPHY2_EDP_EDP_EDP_PHY_REG_BASE_OFFS + 0x00000198)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS3_RMSK                                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS3_IN          \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS3_ADDR, HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS3_RMSK)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS3_INM(m)      \
        in_dword_masked(HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS3_ADDR, m)
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS3_DEBUG_BUS_31_24_BMSK                                      0xff
#define HWIO_AHB2EDPPHY_CM_DPPHY2_EDP_DP_PHY_DEBUG_BUS3_DEBUG_BUS_31_24_SHFT                                       0x0


#endif /* __HAL_DP_PHY_1_2_0_HWIO_H__ */

