/** SMMU IORT Structure for kona_1.0.

This file is automatically generated.
SMMU Base Address and Span information based on Chip Version: kona_v1.0.1_p3q2r18.2.
Interrupt information based on Interrupt Map Version: kona_top.irq.flat v4.2.7.
SMMU SID Mappings based on http://ipcatalog.qualcomm.com/hsr/473 - kona.sid.mapping.xlsx Version 18.0.

Copyright (c) 2019 Qualcomm Technologies, Inc.
All Rights Reserved.
Confidential and Proprietary - Qualcomm Technologies, Inc.
*/

#pragma pack(1)

#include <stdint.h>
#include <stddef.h>
#include "Platform.h"

#define IORT_WORLD_ID_NON_SECURE 0x0
#define IORT_WORLD_ID_SECURE     0x1
#define IORT_WORLD_ID_SHIFT      31

#define IORT_DYNAMIC_MAPPING_NO          0x0
#define IORT_DYNAMIC_MAPPING_YES_DEFAULT 0x0
#define IORT_DYNAMIC_MAPPING_YES         0x1
#define IORT_DYNAMIC_MAPPING_SHIFT       30

#define IORT_TRANSLATION_TYPE_S2_ONLY      0x0
#define IORT_TRANSLATION_TYPE_S2CR_BYPASS  0x1
#define IORT_TRANSLATION_TYPE_SINGLE_STAGE 0x1
#define IORT_TRANSLATION_TYPE_NESTED       0x3
#define IORT_TRANSLATION_TYPE_SHIFT        24

#define IORT_VMID_SHIFT 16

typedef struct _INTERRUPT {
    uint32_t InterruptFlags;
    uint32_t GSIV;
}INTERRUPT;



typedef struct _SIDMAPPING {
    uint32_t InputBase;
    uint32_t NumIDs;
    uint32_t OutputBase;
    uint32_t OutputReference;
    uint32_t Flags;
}SIDMAPPING;



typedef struct _SMMUV2NODE_APPS_MMU500_SMMU_APP{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT64 BaseAddress;
	UINT64 Span;
	UINT32 Flags;
	UINT32 Model;
	UINT32 GlobalIntOffset;
	UINT32 NumContextInterrupts;
	UINT32 ContextIntOffset;
	UINT32 NumPMUInterrupts;
	UINT32 NSGIRPT_GSIV;
	UINT32 NSGIRPT_FLAGS;
	UINT32 NSGCFGIRPT_GSIV;
	UINT32 NSGCFGIRPT_FLAGS;
	INTERRUPT ContextInterrupts[98];
	INTERRUPT PMUInterrupts[10];
	SIDMAPPING SIDMappings[1];
}SMMUV2NODE_APPS_MMU500_SMMU_APP;

#define SMMUV2NODE_APPS_MMU500_SMMU_APP_VAR  {		\
	.Type	=	3,		\
	.Length	=	sizeof(SMMUV2NODE_APPS_MMU500_SMMU_APP),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	1,		\
	.MappingsOffset	=	offsetof(SMMUV2NODE_APPS_MMU500_SMMU_APP,SIDMappings),		\
	.BaseAddress	=	0x15000000,		\
	.Span	=	0x000e0000,		\
	.Flags	=	3,		\
	.Model	=	3,		\
	.GlobalIntOffset	=	offsetof(SMMUV2NODE_APPS_MMU500_SMMU_APP,NSGIRPT_GSIV),		\
	.NumContextInterrupts	=	98,		\
	.ContextIntOffset	=	offsetof(SMMUV2NODE_APPS_MMU500_SMMU_APP,ContextInterrupts),		\
	.NumPMUInterrupts	=	10,		\
	.NSGIRPT_GSIV	=	97,		\
	.NSGIRPT_FLAGS	=	0,		\
	.NSGCFGIRPT_GSIV	=	0,		\
	.NSGCFGIRPT_FLAGS	=	0,		\
	.ContextInterrupts	={		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	129,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	130,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	131,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	132,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	133,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	134,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	135,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	136,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	137,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	138,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	139,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	140,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	141,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	142,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	143,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	144,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	145,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	146,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	147,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	148,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	149,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	150,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	213,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	214,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	215,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	216,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	217,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	218,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	219,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	220,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	221,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	222,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	223,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	224,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	347,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	348,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	349,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	350,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	351,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	352,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	353,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	354,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	355,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	356,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	357,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	358,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	359,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	360,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	361,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	362,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	363,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	364,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	365,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	366,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	367,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	368,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	369,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	370,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	371,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	372,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	373,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	374,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	375,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	376,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	377,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	427,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	428,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	429,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	430,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	431,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	432,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	433,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	434,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	435,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	436,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	437,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	438,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	439,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	440,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	441,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	450,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	451,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	452,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	453,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	454,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	455,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	456,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	457,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	721,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	722,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	723,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	724,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	725,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	726,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	727,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	728,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	0,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	0,		\
		},		\
	},		\
	.PMUInterrupts	={		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	100,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	101,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	102,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	103,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	104,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	105,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	126,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	127,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	128,		\
		},		\
		{		\
		.InterruptFlags	=	0,		\
		.GSIV	=	458,		\
		},		\
	},		\
	.SIDMappings	={		\
		{		\
		.InputBase	=	0x0,		\
		.NumIDs	=	16,		\
		.OutputBase	=	0xA0,		\
		.OutputReference	=	0,		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_DISPLAY{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[12];
}NAMEDNODE_DISPLAY;

#define NAMEDNODE_DISPLAY_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_DISPLAY),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	12,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_DISPLAY,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"\\_SB_.MDP",		\
	.SIDMappings	={		\
		{		\
		.InputBase	=	0x0,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x820,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		{		\
		.InputBase	=	0x1,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x822,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		{		\
		.InputBase	=	0x2,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x821,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		{		\
		.InputBase	=	0x3,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0xC20,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		{		\
		.InputBase	=	0x4,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0xC22,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		{		\
		.InputBase	=	0x5,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0xC21,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},	    \
}

typedef struct _NAMEDNODE_PCIE{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[3];
}NAMEDNODE_PCIE;

#define NAMEDNODE_PCIE_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_PCIE),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	3,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_PCIE,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"\\_SB_.PCI0",		\
	.SIDMappings	={		\
		{		\
		.InputBase	=	0x0,		\
		.NumIDs	=	128,		\
		.OutputBase	=	0x1c00,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		{		\
		.InputBase	=	0x1,		\
		.NumIDs	=	128,		\
		.OutputBase	=	0x1c80,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		{		\
		.InputBase	=	0x3,		\
		.NumIDs	=	128,		\
		.OutputBase	=	0x1d00,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_QUP{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[15];
}NAMEDNODE_QUP;

#define NAMEDNODE_QUP_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_QUP),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	15,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_QUP,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"\\_SB_.QGP0",		\
	.SIDMappings	={		\
		{		\
		.InputBase	=	0x0,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x05b6,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		{		\
		.InputBase	=	0x1,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x05a3,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		{		\
		.InputBase	=	0x2,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x0056,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		{		\
		.InputBase	=	0x3,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x0043,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		{		\
		.InputBase	=	0x4,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x0076,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_SDC{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[2];
}NAMEDNODE_SDC;

#define NAMEDNODE_SDC_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_SDC),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	2,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_SDC,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"\\_SB_.SDC1",		\
	.SIDMappings	={		\
		{		\
		.InputBase	=	0x0,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04a0,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		{		\
		.InputBase	=	0x1,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x00c0,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_UFS{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[2];
}NAMEDNODE_UFS;

#define NAMEDNODE_UFS_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_UFS),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	2,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_UFS,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"\\_SB_.UFS0",		\
	.SIDMappings	={		\
		{		\
		.InputBase	=	0x0,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04e0,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		{		\
		.InputBase	=	0x10,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x00e0,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_USB{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[2];
}NAMEDNODE_USB;

#define NAMEDNODE_USB_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_USB),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	2,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_USB,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"\\_SB_.USB",		\
	.SIDMappings	={		\
		{		\
		.InputBase	=	0x0,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x0000,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		{		\
		.InputBase	=	0x1,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x0020,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_Camera_95BPS{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[2];
}NAMEDNODE_Camera_95BPS;

#define NAMEDNODE_Camera_95BPS_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_Camera_95BPS),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	1,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_Camera_95BPS,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"CAMERA_BPS",		\
	.SIDMappings	={		\
		/* SID Mapping Descriptions:
		   Camera BPS  non-protected stream, Camera BPS  non-protected stream
		*/ \
		{		\
		.InputBase	=	0x03030000,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04002020,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_Camera_95CDM{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[1];
}NAMEDNODE_Camera_95CDM;

#define NAMEDNODE_Camera_95CDM_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_Camera_95CDM),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	1,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_Camera_95CDM,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"CAMERA_CDM",		\
	.SIDMappings	={		\
		/* SID Mapping Descriptions:
		   Camera  CDM non-protected stream, Camera  CDM non-protected stream
		*/ \
		{		\
		.InputBase	=	0x03030000,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x040020c0,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_Camera_95FD{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[1];
}NAMEDNODE_Camera_95FD;

#define NAMEDNODE_Camera_95FD_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_Camera_95FD),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	1,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_Camera_95FD,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"CAMERA_FD",		\
	.SIDMappings	={		\
		/* SID Mapping Descriptions:
		   Camera FD  stream, Camera FD  stream
		*/ \
		{		\
		.InputBase	=	0x03030000,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04002080,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_Camera_95ICP{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[1];
}NAMEDNODE_Camera_95ICP;

#define NAMEDNODE_Camera_95ICP_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_Camera_95ICP),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	1,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_Camera_95ICP,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"CAMERA_ICP",		\
	.SIDMappings	={		\
		/* SID Mapping Descriptions:
		   Camera ICP (CPU) stream, Camera ICP (CPU) stream
		*/ \
		{		\
		.InputBase	=	0x03030000,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x040020e2,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_Camera_95IFE{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[2];
}NAMEDNODE_Camera_95IFE;

#define NAMEDNODE_Camera_95IFE_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_Camera_95IFE),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	1,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_Camera_95IFE,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"CAMERA_IFE",		\
	.SIDMappings	={		\
		/* SID Mapping Descriptions:
		   Camera IFE  non-protected stream, Camera IFE  non-protected stream
		*/ \
		{		\
		.InputBase	=	0x03030000,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04000800,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_Camera_95IFE_95RDI{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[2];
}NAMEDNODE_Camera_95IFE_95RDI;

#define NAMEDNODE_Camera_95IFE_95RDI_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_Camera_95IFE_95RDI),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	1,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_Camera_95IFE_95RDI,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"CAMERA_IFE_RDI",		\
	.SIDMappings	={		\
		/* SID Mapping Descriptions:
		   Camera IFE  non-protected stream, Camera IFE  non-protected stream
		*/ \
		{		\
		.InputBase	=	0x03030000,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04000840,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_Camera_95IPE{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[4];
}NAMEDNODE_Camera_95IPE;

#define NAMEDNODE_Camera_95IPE_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_Camera_95IPE),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	2,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_Camera_95IPE,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"CAMERA_IPE",		\
	.SIDMappings	={		\
		/* SID Mapping Descriptions:
		   Camera IPE  non-protected stream, Camera IPE  non-protected stream
		*/ \
		{		\
		.InputBase	=	0x03030000,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04002060,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   Camera IPE  non-protected stream, Camera IPE  non-protected stream
		*/ \
				{		\
		.InputBase	=	0x03030001,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04002000,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_Camera_95JPEG{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[1];
}NAMEDNODE_Camera_95JPEG;

#define NAMEDNODE_Camera_95JPEG_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_Camera_95JPEG),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	1,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_Camera_95JPEG,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"CAMERA_JPEG",		\
	.SIDMappings	={		\
		/* SID Mapping Descriptions:
		   Camera JPEG  non-protected stream, Camera JPEG  non-protected stream
		*/ \
				{		\
		.InputBase	=	0x03030000,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04002040,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_Camera_95SBI{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[2];
}NAMEDNODE_Camera_95SBI;

#define NAMEDNODE_Camera_95SBI_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_Camera_95SBI),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	1,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_Camera_95SBI,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"CAMERA_SBI",		\
	.SIDMappings	={		\
		/* SID Mapping Descriptions:
		   Camera SBI  non-protected stream, Camera SBI  non-protected stream
		*/ \
				{		\
		.InputBase	=	0x03030000,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x040008a0,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}


typedef struct _NAMEDNODE_Video{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[5];
}NAMEDNODE_Video;

#define NAMEDNODE_Video_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_Video),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	1,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_Video,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"VIDEO",		\
	.SIDMappings	={		\
		/* SID Mapping Descriptions:
		   Video non-protected stream, Video non-protected stream
		*/ \
		{		\
		.InputBase	=	0x03030000,		\
		.NumIDs	=	2,		\
		.OutputBase	=	0x04002100,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_CVP{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[4];
}NAMEDNODE_CVP;

#define NAMEDNODE_CVP_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_CVP),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	1,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_CVP,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"CVP",		\
	.SIDMappings	={		\
		/* SID Mapping Descriptions:
		   CVP non-protected stream, CVP non-protected stream
		*/ \
		{		\
		.InputBase	=	0x03030000,		\
		.NumIDs	=	2,		\
		.OutputBase	=	0x04002120,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}


typedef struct _NAMEDNODE_CRYPTO{
    uint8_t Type;
    uint16_t Length;
    uint8_t Revision;
    uint32_t Reserved;
    uint32_t NumberofMappings;
    uint32_t MappingsOffset;
    uint32_t NodeFlags;
    uint32_t CacheCoherency;
    uint8_t AllocationHints;
    uint16_t Reserved1;
    uint8_t MemAccessFlags;
    uint8_t DeviceMemAddressSize;
    uint8_t DevObjectName[32];
    SIDMAPPING SIDMappings[8];
}NAMEDNODE_CRYPTO;

#define NAMEDNODE_CRYPTO_VAR  { \
    .Type                 = 1, \
    .Length               = sizeof(NAMEDNODE_CRYPTO), \
    .Revision             = 1, \
    .Reserved             = 0, \
    .NumberofMappings     = 8, \
    .MappingsOffset       = offsetof(NAMEDNODE_CRYPTO,SIDMappings), \
    .NodeFlags            = 0, \
    .CacheCoherency       = 0, \
    .AllocationHints      = 0, \
    .Reserved1            = 0, \
    .MemAccessFlags       = 0, \
    .DeviceMemAddressSize = 36, \
    .DevObjectName        = "CRYPTO", \
    .SIDMappings          = { \
        /* SID Mapping Descriptions:
           Crypto engine descriptors for data pipe 4/5, Crypto engine data pipe 4/5
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (2) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x00110584, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
        /* SID Mapping Descriptions:
           Crypto engine descriptors for data pipe 6/7, Crypto engine data pipe 6/7
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (3) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x00110586, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
        /* SID Mapping Descriptions:
           Crypto engine data pipe 2
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (7) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x00000592, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
        /* SID Mapping Descriptions:
           Crypto engine data pipe 3
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (8) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x00000593, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
        /* SID Mapping Descriptions:
           Crypto engine data pipe 8/9
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (9) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x00010598, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
        /* SID Mapping Descriptions:
           Crypto engine data pipe 12, Crypto engine data pipe 13
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (10) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x0001059c, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
        /* SID Mapping Descriptions:
           Crypto engine data pipe 14
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (11) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x0000059e, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
        /* SID Mapping Descriptions:
           Crypto engine data pipe 15
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (12) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x0000059f, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
    }, \
}

typedef struct _NAMEDNODE_ADSP{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[7];
}NAMEDNODE_ADSP;

#define NAMEDNODE_ADSP_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_ADSP),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	7,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_ADSP,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"ADSP",		\
	.SIDMappings	={		\
		/* SID Mapping Descriptions:
		   LPASS ADSP boot image stream
		*/ \
		{		\
		.InputBase	=	0x00060000,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x00001800,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   LPASS ADSP audio
		*/ \
		{		\
		.InputBase	=	0x03030001,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x00001801,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   LPASS ADSP voice print stream
		*/ \
		{		\
		.InputBase	=	0x00ff0002,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x00001802,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   LPASS ADSP Open DSP PD
		*/ \
		{		\
		.InputBase	=	0x03030003,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x00001803,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   LPASS ADSP Open DSP PD
		*/ \
		{		\
		.InputBase	=	0x03030004,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x00001804,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   LPASS ADSP Open DSP PD
		*/ \
		{		\
		.InputBase	=	0x03030005,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x00001805,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   LPASS ADSP USB audio stream
		*/ \
		{		\
		.InputBase	=	0x03030007,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x0000180f,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_Compute{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[11];
}NAMEDNODE_Compute;

#define NAMEDNODE_Compute_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_Compute),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	11,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_Compute,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"COMPUTE",		\
	.SIDMappings	={		\
		/* SID Mapping Descriptions:
		   Compute HCP application streams 1, Compute DMA application streams 1 , Compute DSP application streams 1, Compute HCP application streams 1, Compute DMA application streams 1, Compute DSP application streams 1
		*/ \
		{		\
		.InputBase	=	0x03030000,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04601401,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   Compute HCP application streams 2, Compute DMA application streams 2, Compute DSP application streams 2, Compute HCP application streams 2, Compute DMA application streams 2, Compute DSP application streams 2
		*/ \
		{		\
		.InputBase	=	0x03030001,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04601402,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   Compute HCP application streams 3, Compute DMA application streams 3, Compute DSP application streams 3, Compute HCP application streams 3, Compute DMA application streams 3, Compute DSP application streams 3
		*/ \
		{		\
		.InputBase	=	0x03030002,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04601403,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   Compute HCP application streams 4, Compute DMA application streams 4, Compute DSP application streams 4, Compute HCP application streams 4, Compute DMA application streams 4, Compute DSP application streams 4
		*/ \
		{		\
		.InputBase	=	0x03030003,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04601404,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   Compute HCP application streams 5, Compute DMA application streams 5, Compute DSP application streams 5, Compute HCP application streams 5, Compute DMA application streams 5, Compute DSP application streams 5
		*/ \
		{		\
		.InputBase	=	0x03030004,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04601405,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   Compute HCP application streams 6, Compute DMA application streams 6, Compute DSP application streams 6, Compute HCP application streams 6, Compute DMA application streams 6, Compute DSP application streams 6
		*/ \
		{		\
		.InputBase	=	0x03030005,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04601406,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   Compute HCP application streams 7, Compute DMA application streams 7, Compute DSP application streams 7, Compute HCP application streams 7, Compute DMA application streams 7, Compute DSP application streams 7
		*/ \
		{		\
		.InputBase	=	0x03030006,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04601407,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   Compute HCP application streams 8, Compute DMA application streams 8, Compute DSP application streams 8, Compute HCP application streams 8, Compute DMA application streams 8, Compute DSP application streams 8
		*/ \
		{		\
		.InputBase	=	0x03030007,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04601408,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   Compute HCP content protection pixel (CP-P), Compute DMA content protection pixel (CP-P), Compute DSP content protection pixel (CP-P), Compute HCP content protection pixel (CP-P), Compute DMA content protection pixel (CP-P), Compute DSP content protection pixel (CP-P)
		*/ \
		{		\
		.InputBase	=	0x030a0008,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04601409,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   Compute DSP QuRT stream, Compute DSP QuRT stream
		*/ \
		{		\
		.InputBase	=	0x001e0009,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x04001440,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   Compute Secure Stream, Compute Secure Stream
		*/ \
		{		\
		.InputBase	=	0x002a000a,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x0400144a,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_Sensors_95DSP{
	UINT8 Type;
	UINT16 Length;
	UINT8 Revision;
	UINT32 Reserved;
	UINT32 NumberofMappings;
	UINT32 MappingsOffset;
	UINT32 NodeFlags;
	UINT32 CacheCoherency;
	UINT8 AllocationHints;
	UINT16 Reserved1;
	UINT8 MemAccessFlags;
	UINT8 DeviceMemAddressSize;
	UINT8 DevObjectName[32];
	SIDMAPPING SIDMappings[4];
}NAMEDNODE_Sensors_95DSP;

#define NAMEDNODE_Sensors_95DSP_VAR  {		\
	.Type	=	1,		\
	.Length	=	sizeof(NAMEDNODE_Sensors_95DSP),		\
	.Revision	=	1,		\
	.Reserved	=	0,		\
	.NumberofMappings	=	4,		\
	.MappingsOffset	=	offsetof(NAMEDNODE_Sensors_95DSP,SIDMappings),		\
	.NodeFlags	=	0,		\
	.CacheCoherency	=	0,		\
	.AllocationHints	=	0,		\
	.Reserved1	=	0,		\
	.MemAccessFlags	=	0,		\
	.DeviceMemAddressSize	=	36,		\
	.DevObjectName	=	"SENSORS_DSP",		\
	.SIDMappings	={		\
		/* SID Mapping Descriptions:
		   SSC DSP boot image stream
		*/ \
		{		\
		.InputBase	=	0x00050000,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x00000540,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   SSC DSP user process 1 stream
		*/ \
		{		\
		.InputBase	=	0x03030001,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x00000541,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   SSC DSP user process 2 stream
		*/ \
		{		\
		.InputBase	=	0x03030002,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x00000542,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
		/* SID Mapping Descriptions:
		   SSC DSP user process 3 stream
		*/ \
		{		\
		.InputBase	=	0x03030003,		\
		.NumIDs	=	1,		\
		.OutputBase	=	0x00000543,		\
		.OutputReference	=	offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app),		\
		.Flags	=	0,		\
		},		\
	},		\
}

typedef struct _NAMEDNODE_NDSP{
    uint8_t Type;
    uint16_t Length;
    uint8_t Revision;
    uint32_t Reserved;
    uint32_t NumberofMappings;
    uint32_t MappingsOffset;
    uint32_t NodeFlags;
    uint32_t CacheCoherency;
    uint8_t AllocationHints;
    uint16_t Reserved1;
    uint8_t MemAccessFlags;
    uint8_t DeviceMemAddressSize;
    uint8_t DevObjectName[32];
    SIDMAPPING SIDMappings[3];
}NAMEDNODE_NDSP;

#define NAMEDNODE_NDSP_VAR  { \
    .Type                 = 1, \
    .Length               = sizeof(NAMEDNODE_NDSP), \
    .Revision             = 1, \
    .Reserved             = 0, \
    .NumberofMappings     = 3, \
    .MappingsOffset       = offsetof(NAMEDNODE_NDSP,SIDMappings), \
    .NodeFlags            = 0, \
    .CacheCoherency       = 0, \
    .AllocationHints      = 0, \
    .Reserved1            = 0, \
    .MemAccessFlags       = 0, \
    .DeviceMemAddressSize = 36, \
    .DevObjectName        = "NDSP", \
    .SIDMappings          = { \
        /* SID Mapping Descriptions:
           NPU DMA non-protected stream #1, NPU DMA non-protected stream #1
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (1) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x040010c1, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
        /* SID Mapping Descriptions:
           NPU DMA non-protected stream #2, NPU DMA non-protected stream #2
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (2) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x040010c2, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
        /* SID Mapping Descriptions:
           NPU DRM protected video stream #1, NPU DRM protected video stream #1
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (5) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x040010c5, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
    }, \
}

typedef struct _NAMEDNODE_NPU0{
    uint8_t Type;
    uint16_t Length;
    uint8_t Revision;
    uint32_t Reserved;
    uint32_t NumberofMappings;
    uint32_t MappingsOffset;
    uint32_t NodeFlags;
    uint32_t CacheCoherency;
    uint8_t AllocationHints;
    uint16_t Reserved1;
    uint8_t MemAccessFlags;
    uint8_t DeviceMemAddressSize;
    uint8_t DevObjectName[32];
    SIDMAPPING SIDMappings[3];
}NAMEDNODE_NPU0;

#define NAMEDNODE_NPU0_VAR  { \
    .Type                 = 1, \
    .Length               = sizeof(NAMEDNODE_NPU0), \
    .Revision             = 1, \
    .Reserved             = 0, \
    .NumberofMappings     = 3, \
    .MappingsOffset       = offsetof(NAMEDNODE_NPU0,SIDMappings), \
    .NodeFlags            = 0, \
    .CacheCoherency       = 0, \
    .AllocationHints      = 0, \
    .Reserved1            = 0, \
    .MemAccessFlags       = 0, \
    .DeviceMemAddressSize = 36, \
    .DevObjectName        = "NPU0", \
    .SIDMappings          = { \
        /* SID Mapping Descriptions:
           NPU DMA non-protected stream #1, NPU DMA non-protected stream #1
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (0) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x04001081, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
        /* SID Mapping Descriptions:
           NPU DMA non-protected stream #2, NPU DMA non-protected stream #2
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (1) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x04001082, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
        /* SID Mapping Descriptions:
           NPU DRM protected video stream #1, NPU DRM protected video stream #1
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (4) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x04001085, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
    }, \
}

typedef struct _NAMEDNODE_NPU1{
    uint8_t Type;
    uint16_t Length;
    uint8_t Revision;
    uint32_t Reserved;
    uint32_t NumberofMappings;
    uint32_t MappingsOffset;
    uint32_t NodeFlags;
    uint32_t CacheCoherency;
    uint8_t AllocationHints;
    uint16_t Reserved1;
    uint8_t MemAccessFlags;
    uint8_t DeviceMemAddressSize;
    uint8_t DevObjectName[32];
    SIDMAPPING SIDMappings[3];
}NAMEDNODE_NPU1;

#define NAMEDNODE_NPU1_VAR  { \
    .Type                 = 1, \
    .Length               = sizeof(NAMEDNODE_NPU1), \
    .Revision             = 1, \
    .Reserved             = 0, \
    .NumberofMappings     = 3, \
    .MappingsOffset       = offsetof(NAMEDNODE_NPU1,SIDMappings), \
    .NodeFlags            = 0, \
    .CacheCoherency       = 0, \
    .AllocationHints      = 0, \
    .Reserved1            = 0, \
    .MemAccessFlags       = 0, \
    .DeviceMemAddressSize = 36, \
    .DevObjectName        = "NPU1", \
    .SIDMappings          = { \
        /* SID Mapping Descriptions:
           NPU DMA non-protected stream #1, NPU DMA non-protected stream #1
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (0) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x040010a1, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
        /* SID Mapping Descriptions:
           NPU DMA non-protected stream #2, NPU DMA non-protected stream #2
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (1) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x040010a2, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
        /* SID Mapping Descriptions:
           NPU DRM protected video stream #1, NPU DRM protected video stream #1
        */ \
        {        \
        .InputBase       = (  (IORT_WORLD_ID_NON_SECURE << IORT_WORLD_ID_SHIFT) \
                            | (IORT_DYNAMIC_MAPPING_NO << IORT_DYNAMIC_MAPPING_SHIFT) \
                            | (IORT_TRANSLATION_TYPE_NESTED << IORT_TRANSLATION_TYPE_SHIFT) \
                            | (4) ), \
        .NumIDs          = 1, \
        .OutputBase      = 0x040010a5, \
        .OutputReference = offsetof(IORT,SMMUV2Nodes_apps_mmu500_smmu_app), \
        .Flags           = 0, \
        }, \
    }, \
}
typedef struct _IORT{
	UINT32 Signature;
	UINT32 Length;
	UINT8 Revision;
	UINT8 Checksum;
	UINT8 OEMID[6];
	UINT64 OEMTableID;
	UINT32 OEMRevision;
	UINT32 CreatorID;
	UINT32 CreatorRevision;
	UINT32 NumberofIORTNodes;
	UINT32 IORTNodesOffset;
	UINT32 Reserved;
	SMMUV2NODE_APPS_MMU500_SMMU_APP SMMUV2Nodes_apps_mmu500_smmu_app;
	NAMEDNODE_DISPLAY NamedNodes_display;
	NAMEDNODE_PCIE NamedNodes_pcie;
	NAMEDNODE_QUP NamedNodes_qup;
	NAMEDNODE_SDC NamedNodes_sdc;
	NAMEDNODE_UFS NamedNodes_ufs;
	NAMEDNODE_USB NamedNodes_usb;
	NAMEDNODE_Camera_95BPS NamedNodes_Camera_95BPS;
	NAMEDNODE_Camera_95CDM NamedNodes_Camera_95CDM;
	NAMEDNODE_Camera_95FD NamedNodes_Camera_95FD;
	NAMEDNODE_Camera_95ICP NamedNodes_Camera_95ICP;
	NAMEDNODE_Camera_95IFE NamedNodes_Camera_95IFE;
	NAMEDNODE_Camera_95IFE_95RDI NamedNodes_Camera_95IFE_95RDI;
	NAMEDNODE_Camera_95IPE NamedNodes_Camera_95IPE;
	NAMEDNODE_Camera_95JPEG NamedNodes_Camera_95JPEG;
	NAMEDNODE_Camera_95SBI NamedNodes_Camera_95SBI;
        NAMEDNODE_Video NamedNodes_Video;
        NAMEDNODE_CVP NamedNodes_CVP;
        NAMEDNODE_CRYPTO NamedNodes_CRYPTO;
        NAMEDNODE_ADSP NamedNodes_ADSP;
        NAMEDNODE_Compute NamedNodes_Compute;
        NAMEDNODE_Sensors_95DSP NamedNodes_Sensors_95DSP;
        NAMEDNODE_NDSP NamedNodes_NDSP;
        NAMEDNODE_NPU0 NamedNodes_NPU0;
        NAMEDNODE_NPU1 NamedNodes_NPU1;

}IORT;

IORT IORT_TABLE = {		
	.Signature	=	'TROI',		
	.Length	=	sizeof(IORT),		
	.Revision	=	0,		
	.Checksum	=	0,		
	.OEMID	=	ACPI_OEM_ID,		
	.OEMTableID	=	ACPI_OEM_TABLE_ID,		
	.OEMRevision	=	ACPI_OEM_REVISION,		
	.CreatorID	=	ACPI_CREATOR_ID,		
	.CreatorRevision	=	ACPI_CREATOR_REVISION,		
	.NumberofIORTNodes	=	25,
	.IORTNodesOffset	=	offsetof(IORT,Reserved)+4,		
	.Reserved	=	0,		
	.SMMUV2Nodes_apps_mmu500_smmu_app	=	SMMUV2NODE_APPS_MMU500_SMMU_APP_VAR		,
	.NamedNodes_display	=	NAMEDNODE_DISPLAY_VAR		,
	.NamedNodes_pcie	=	NAMEDNODE_PCIE_VAR		,
	.NamedNodes_qup	=	NAMEDNODE_QUP_VAR		,
	.NamedNodes_sdc	=	NAMEDNODE_SDC_VAR		,
	.NamedNodes_ufs	=	NAMEDNODE_UFS_VAR		,
	.NamedNodes_usb	=	NAMEDNODE_USB_VAR		,
	.NamedNodes_Camera_95BPS	=	NAMEDNODE_Camera_95BPS_VAR		,
	.NamedNodes_Camera_95CDM	=	NAMEDNODE_Camera_95CDM_VAR		,
	.NamedNodes_Camera_95FD	        =	NAMEDNODE_Camera_95FD_VAR		,
	.NamedNodes_Camera_95ICP	=	NAMEDNODE_Camera_95ICP_VAR		,
	.NamedNodes_Camera_95IFE	=	NAMEDNODE_Camera_95IFE_VAR		,
	.NamedNodes_Camera_95IFE_95RDI	=	NAMEDNODE_Camera_95IFE_95RDI_VAR	,
	.NamedNodes_Camera_95IPE	=	NAMEDNODE_Camera_95IPE_VAR		,
	.NamedNodes_Camera_95JPEG	=	NAMEDNODE_Camera_95JPEG_VAR		,
	.NamedNodes_Camera_95SBI	=	NAMEDNODE_Camera_95SBI_VAR		,
        .NamedNodes_Video       	=	NAMEDNODE_Video_VAR		,
        .NamedNodes_CVP	                =	NAMEDNODE_CVP_VAR		,
        .NamedNodes_CRYPTO              =       NAMEDNODE_CRYPTO_VAR            ,
        .NamedNodes_ADSP                =	NAMEDNODE_ADSP_VAR              , 
        .NamedNodes_Compute             =	NAMEDNODE_Compute_VAR		,
        .NamedNodes_Sensors_95DSP       =	NAMEDNODE_Sensors_95DSP_VAR     ,
        .NamedNodes_NDSP                =       NAMEDNODE_NDSP_VAR,
        .NamedNodes_NPU0                =       NAMEDNODE_NPU0_VAR,
        .NamedNodes_NPU1                =       NAMEDNODE_NPU1_VAR,

};

#pragma pack()
