#ifndef __HALBOOTHWIO_H__
#define __HALBOOTHWIO_H__
/*
===========================================================================
*/
/**
  @file HALbootHWIO.h
  @brief Auto-generated HWIO interface include file.

  Reference chip release:
    SM8250 (Kona) [kona_v1.0_p3q1r17.5_MECO]
 
  This file contains HWIO register definitions for the following modules:
    APSS_WDT_TMR1_APSS_WDT
    SECURITY_CONTROL_CORE
    GCC_CLK_CTL_REG
    AOSS_PERIPHERALS
    TCSR_TCSR_REGS
    PSHOLD
    SLP_CNTR
    AOSS_CC_AOSS_CC_REG


  Generation parameters: 
  { u'filename': u'HALbootHWIO.h',
    u'header': u'#include "msmhwiobase.h"',
    u'module-filter-exclude': { },
    u'module-filter-include': { },
    u'modules': [ u'APSS_WDT_TMR1_APSS_WDT',
                  u'SECURITY_CONTROL_CORE',
                  u'GCC_CLK_CTL_REG',
                  u'AOSS_PERIPHERALS',
                  u'TCSR_TCSR_REGS',
                  u'PSHOLD',
                  u'SLP_CNTR',
                  u'AOSS_CC_AOSS_CC_REG']}
*/
/*
  ===========================================================================

  Copyright (c) 2018 Qualcomm Technologies, Inc.
  All Rights Reserved.
  Confidential and Proprietary - Qualcomm Technologies, Inc.

  Export of this technology or software is regulated by the U.S. Government.
  Diversion contrary to U.S. law prohibited.

  All ideas, data and information contained in or disclosed by
  this document are confidential and proprietary information of
  Qualcomm Technologies, Inc. and all rights therein are expressly reserved.
  By accepting this material the recipient agrees that this material
  and the information contained therein are held in confidence and in
  trust and will not be used, copied, reproduced in whole or in part,
  nor its contents revealed in any manner to others without the express
  written permission of Qualcomm Technologies, Inc.

  ===========================================================================

  $Header: //components/rel/boot.xf/3.2/QcomPkg/SocPkg/8250/Include/HALbootHWIO.h#4 $
  $DateTime: 2018/12/12 13:23:46 $
  $Author: pwbldsvc $

  ===========================================================================
*/

#include "msmhwiobase.h"

/*----------------------------------------------------------------------------
 * MODULE: APSS_WDT_TMR1_APSS_WDT
 *--------------------------------------------------------------------------*/

#define APSS_WDT_TMR1_APSS_WDT_REG_BASE                                    (APSS_HM_BASE      + 0x00410000)
#define APSS_WDT_TMR1_APSS_WDT_REG_BASE_SIZE                               0x1000
#define APSS_WDT_TMR1_APSS_WDT_REG_BASE_USED                               0x20

#define HWIO_APSS_WDT_TMR1_WDOG_SECURE_ADDR                                (APSS_WDT_TMR1_APSS_WDT_REG_BASE      + 0x00000000)
#define HWIO_APSS_WDT_TMR1_WDOG_SECURE_RMSK                                       0x1
#define HWIO_APSS_WDT_TMR1_WDOG_SECURE_IN          \
        in_dword(HWIO_APSS_WDT_TMR1_WDOG_SECURE_ADDR)
#define HWIO_APSS_WDT_TMR1_WDOG_SECURE_INM(m)      \
        in_dword_masked(HWIO_APSS_WDT_TMR1_WDOG_SECURE_ADDR, m)
#define HWIO_APSS_WDT_TMR1_WDOG_SECURE_OUT(v)      \
        out_dword(HWIO_APSS_WDT_TMR1_WDOG_SECURE_ADDR,v)
#define HWIO_APSS_WDT_TMR1_WDOG_SECURE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_APSS_WDT_TMR1_WDOG_SECURE_ADDR,m,v,HWIO_APSS_WDT_TMR1_WDOG_SECURE_IN)
#define HWIO_APSS_WDT_TMR1_WDOG_SECURE_WDT_BMSK                                   0x1
#define HWIO_APSS_WDT_TMR1_WDOG_SECURE_WDT_SHFT                                   0x0

#define HWIO_APSS_WDT_TMR1_WDOG_RESET_ADDR                                 (APSS_WDT_TMR1_APSS_WDT_REG_BASE      + 0x00000004)
#define HWIO_APSS_WDT_TMR1_WDOG_RESET_RMSK                                        0x1
#define HWIO_APSS_WDT_TMR1_WDOG_RESET_OUT(v)      \
        out_dword(HWIO_APSS_WDT_TMR1_WDOG_RESET_ADDR,v)
#define HWIO_APSS_WDT_TMR1_WDOG_RESET_RESET_BMSK                                  0x1
#define HWIO_APSS_WDT_TMR1_WDOG_RESET_RESET_SHFT                                  0x0

#define HWIO_APSS_WDT_TMR1_WDOG_CTL_ADDR                                   (APSS_WDT_TMR1_APSS_WDT_REG_BASE      + 0x00000008)
#define HWIO_APSS_WDT_TMR1_WDOG_CTL_RMSK                                          0x3
#define HWIO_APSS_WDT_TMR1_WDOG_CTL_OUT(v)      \
        out_dword(HWIO_APSS_WDT_TMR1_WDOG_CTL_ADDR,v)
#define HWIO_APSS_WDT_TMR1_WDOG_CTL_UNMASKED_INT_ENABLE_BMSK                      0x2
#define HWIO_APSS_WDT_TMR1_WDOG_CTL_UNMASKED_INT_ENABLE_SHFT                      0x1
#define HWIO_APSS_WDT_TMR1_WDOG_CTL_INT_ENABLE_BMSK                               0x1
#define HWIO_APSS_WDT_TMR1_WDOG_CTL_INT_ENABLE_SHFT                               0x0

#define HWIO_APSS_WDT_TMR1_WDOG_STATUS_ADDR                                (APSS_WDT_TMR1_APSS_WDT_REG_BASE      + 0x0000000c)
#define HWIO_APSS_WDT_TMR1_WDOG_STATUS_RMSK                                0x801fffff
#define HWIO_APSS_WDT_TMR1_WDOG_STATUS_IN          \
        in_dword(HWIO_APSS_WDT_TMR1_WDOG_STATUS_ADDR)
#define HWIO_APSS_WDT_TMR1_WDOG_STATUS_INM(m)      \
        in_dword_masked(HWIO_APSS_WDT_TMR1_WDOG_STATUS_ADDR, m)
#define HWIO_APSS_WDT_TMR1_WDOG_STATUS_FROZEN_BMSK                         0x80000000
#define HWIO_APSS_WDT_TMR1_WDOG_STATUS_FROZEN_SHFT                               0x1f
#define HWIO_APSS_WDT_TMR1_WDOG_STATUS_COUNT_BMSK                            0x1ffffe
#define HWIO_APSS_WDT_TMR1_WDOG_STATUS_COUNT_SHFT                                 0x1
#define HWIO_APSS_WDT_TMR1_WDOG_STATUS_EXPIRED_STATUS_BMSK                        0x1
#define HWIO_APSS_WDT_TMR1_WDOG_STATUS_EXPIRED_STATUS_SHFT                        0x0

#define HWIO_APSS_WDT_TMR1_WDOG_BARK_TIME_ADDR                             (APSS_WDT_TMR1_APSS_WDT_REG_BASE      + 0x00000010)
#define HWIO_APSS_WDT_TMR1_WDOG_BARK_TIME_RMSK                                0xfffff
#define HWIO_APSS_WDT_TMR1_WDOG_BARK_TIME_IN          \
        in_dword(HWIO_APSS_WDT_TMR1_WDOG_BARK_TIME_ADDR)
#define HWIO_APSS_WDT_TMR1_WDOG_BARK_TIME_INM(m)      \
        in_dword_masked(HWIO_APSS_WDT_TMR1_WDOG_BARK_TIME_ADDR, m)
#define HWIO_APSS_WDT_TMR1_WDOG_BARK_TIME_OUT(v)      \
        out_dword(HWIO_APSS_WDT_TMR1_WDOG_BARK_TIME_ADDR,v)
#define HWIO_APSS_WDT_TMR1_WDOG_BARK_TIME_OUTM(m,v) \
        out_dword_masked_ns(HWIO_APSS_WDT_TMR1_WDOG_BARK_TIME_ADDR,m,v,HWIO_APSS_WDT_TMR1_WDOG_BARK_TIME_IN)
#define HWIO_APSS_WDT_TMR1_WDOG_BARK_TIME_DATA_BMSK                           0xfffff
#define HWIO_APSS_WDT_TMR1_WDOG_BARK_TIME_DATA_SHFT                               0x0

#define HWIO_APSS_WDT_TMR1_WDOG_BITE_TIME_ADDR                             (APSS_WDT_TMR1_APSS_WDT_REG_BASE      + 0x00000014)
#define HWIO_APSS_WDT_TMR1_WDOG_BITE_TIME_RMSK                                0xfffff
#define HWIO_APSS_WDT_TMR1_WDOG_BITE_TIME_IN          \
        in_dword(HWIO_APSS_WDT_TMR1_WDOG_BITE_TIME_ADDR)
#define HWIO_APSS_WDT_TMR1_WDOG_BITE_TIME_INM(m)      \
        in_dword_masked(HWIO_APSS_WDT_TMR1_WDOG_BITE_TIME_ADDR, m)
#define HWIO_APSS_WDT_TMR1_WDOG_BITE_TIME_OUT(v)      \
        out_dword(HWIO_APSS_WDT_TMR1_WDOG_BITE_TIME_ADDR,v)
#define HWIO_APSS_WDT_TMR1_WDOG_BITE_TIME_OUTM(m,v) \
        out_dword_masked_ns(HWIO_APSS_WDT_TMR1_WDOG_BITE_TIME_ADDR,m,v,HWIO_APSS_WDT_TMR1_WDOG_BITE_TIME_IN)
#define HWIO_APSS_WDT_TMR1_WDOG_BITE_TIME_DATA_BMSK                           0xfffff
#define HWIO_APSS_WDT_TMR1_WDOG_BITE_TIME_DATA_SHFT                               0x0

#define HWIO_APSS_WDT_TMR1_WDOG_TEST_LOAD_STATUS_ADDR                      (APSS_WDT_TMR1_APSS_WDT_REG_BASE      + 0x00000018)
#define HWIO_APSS_WDT_TMR1_WDOG_TEST_LOAD_STATUS_RMSK                             0x1
#define HWIO_APSS_WDT_TMR1_WDOG_TEST_LOAD_STATUS_IN          \
        in_dword(HWIO_APSS_WDT_TMR1_WDOG_TEST_LOAD_STATUS_ADDR)
#define HWIO_APSS_WDT_TMR1_WDOG_TEST_LOAD_STATUS_INM(m)      \
        in_dword_masked(HWIO_APSS_WDT_TMR1_WDOG_TEST_LOAD_STATUS_ADDR, m)
#define HWIO_APSS_WDT_TMR1_WDOG_TEST_LOAD_STATUS_SYNC_STATUS_BMSK                 0x1
#define HWIO_APSS_WDT_TMR1_WDOG_TEST_LOAD_STATUS_SYNC_STATUS_SHFT                 0x0

#define HWIO_APSS_WDT_TMR1_WDOG_TEST_LOAD_ADDR                             (APSS_WDT_TMR1_APSS_WDT_REG_BASE      + 0x0000001c)
#define HWIO_APSS_WDT_TMR1_WDOG_TEST_LOAD_RMSK                                    0x1
#define HWIO_APSS_WDT_TMR1_WDOG_TEST_LOAD_OUT(v)      \
        out_dword(HWIO_APSS_WDT_TMR1_WDOG_TEST_LOAD_ADDR,v)
#define HWIO_APSS_WDT_TMR1_WDOG_TEST_LOAD_LOAD_BMSK                               0x1
#define HWIO_APSS_WDT_TMR1_WDOG_TEST_LOAD_LOAD_SHFT                               0x0

#define HWIO_APSS_WDT_TMR1_WDOG_TEST_ADDR                                  (APSS_WDT_TMR1_APSS_WDT_REG_BASE      + 0x00000020)
#define HWIO_APSS_WDT_TMR1_WDOG_TEST_RMSK                                     0xfffff
#define HWIO_APSS_WDT_TMR1_WDOG_TEST_IN          \
        in_dword(HWIO_APSS_WDT_TMR1_WDOG_TEST_ADDR)
#define HWIO_APSS_WDT_TMR1_WDOG_TEST_INM(m)      \
        in_dword_masked(HWIO_APSS_WDT_TMR1_WDOG_TEST_ADDR, m)
#define HWIO_APSS_WDT_TMR1_WDOG_TEST_OUT(v)      \
        out_dword(HWIO_APSS_WDT_TMR1_WDOG_TEST_ADDR,v)
#define HWIO_APSS_WDT_TMR1_WDOG_TEST_OUTM(m,v) \
        out_dword_masked_ns(HWIO_APSS_WDT_TMR1_WDOG_TEST_ADDR,m,v,HWIO_APSS_WDT_TMR1_WDOG_TEST_IN)
#define HWIO_APSS_WDT_TMR1_WDOG_TEST_LOAD_VALUE_BMSK                          0xfffff
#define HWIO_APSS_WDT_TMR1_WDOG_TEST_LOAD_VALUE_SHFT                              0x0

/*----------------------------------------------------------------------------
 * MODULE: SECURITY_CONTROL_CORE
 *--------------------------------------------------------------------------*/

#define SECURITY_CONTROL_CORE_REG_BASE                                                          (SECURITY_CONTROL_BASE      + 0x00000000)
#define SECURITY_CONTROL_CORE_REG_BASE_SIZE                                                     0x7000
#define SECURITY_CONTROL_CORE_REG_BASE_USED                                                     0x6400

#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_ADDR(n)                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000000 + 0x4 * (n))
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_MAXn                                                            71
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_ADDR(n), HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_RMSK)
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_ADDR(n), mask)
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_CRI_CM_PRIVATE_BMSK                                     0xffffffff
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_CRI_CM_PRIVATE_SHFT                                            0x0

#define HWIO_QFPROM_RAW_LCM_ROW_LSB_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000120)
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_RMSK                                                        0xffffffff
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_LCM_ROW_LSB_ADDR)
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_LCM_ROW_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_LCM_ROW_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_LCM_ROW_LSB_ADDR,m,v,HWIO_QFPROM_RAW_LCM_ROW_LSB_IN)
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_DISABLE_LCM_BMSK                                            0x80000000
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_DISABLE_LCM_SHFT                                                  0x1f
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_DISABLE_LCM_STATE_TRANSITION_BMSK                           0x40000000
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_DISABLE_LCM_STATE_TRANSITION_SHFT                                 0x1e
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_DISABLE_SECURE_PHK_BMSK                                     0x20000000
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_DISABLE_SECURE_PHK_SHFT                                           0x1d
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_RSVD_BMSK                                                   0x1fffffe0
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_RSVD_SHFT                                                          0x5
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_QC_EXTERNAL_BMSK                                                  0x10
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_QC_EXTERNAL_SHFT                                                   0x4
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_QC_INTERNAL_BMSK                                                   0x8
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_QC_INTERNAL_SHFT                                                   0x3
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_QC_FEAT_CONFIG_BMSK                                                0x4
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_QC_FEAT_CONFIG_SHFT                                                0x2
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_HW_TEST_BMSK                                                       0x2
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_HW_TEST_SHFT                                                       0x1
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_SOC_PERSO_BMSK                                                     0x1
#define HWIO_QFPROM_RAW_LCM_ROW_LSB_SOC_PERSO_SHFT                                                     0x0

#define HWIO_QFPROM_RAW_LCM_ROW_MSB_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000124)
#define HWIO_QFPROM_RAW_LCM_ROW_MSB_RMSK                                                        0xffffffff
#define HWIO_QFPROM_RAW_LCM_ROW_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_LCM_ROW_MSB_ADDR)
#define HWIO_QFPROM_RAW_LCM_ROW_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_LCM_ROW_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_LCM_ROW_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_LCM_ROW_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_LCM_ROW_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_LCM_ROW_MSB_ADDR,m,v,HWIO_QFPROM_RAW_LCM_ROW_MSB_IN)
#define HWIO_QFPROM_RAW_LCM_ROW_MSB_RSVD_BMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_LCM_ROW_MSB_RSVD_SHFT                                                          0x0

#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000128 + 0x8 * (n))
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_MAXn                                                    1
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_RSVD_BMSK                                      0xffffffff
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_LSB_RSVD_SHFT                                             0x0

#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000012c + 0x8 * (n))
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_MAXn                                                    1
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_RSVD_BMSK                                      0xffffffff
#define HWIO_QFPROM_RAW_BOOT_PATCH_HASH_ROWn_MSB_RSVD_SHFT                                             0x0

#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n)                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000138 + 0x8 * (n))
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_RMSK                                    0xffffffff
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_MAXn                                             3
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_BMSK                          0xffffffff
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_SHFT                                 0x0

#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n)                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000013c + 0x8 * (n))
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RMSK                                    0xffffffff
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_MAXn                                             3
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RSVD1_BMSK                              0x80000000
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RSVD1_SHFT                                    0x1f
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_FEC_VALUE_BMSK                          0x7f000000
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_FEC_VALUE_SHFT                                0x18
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_BMSK                            0xffffff
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_SHFT                                 0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000158)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_RMSK                                            0x7fffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_BMSK                    0x40000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_SHFT                          0x1e
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_BMSK                              0x20000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_SHFT                                    0x1d
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_BMSK                       0x1fe00000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_SHFT                             0x15
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_BMSK                        0x180000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_SHFT                            0x13
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_BMSK                      0x40000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_SHFT                         0x12
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_BMSK                      0x20000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_SHFT                         0x11
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_BMSK                               0x10000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_SHFT                                  0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_BMSK                               0x8000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_SHFT                                  0xf
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_BMSK                               0x4000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_SHFT                                  0xe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_BMSK                                     0x2000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_SHFT                                        0xd
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_BMSK                                   0x1000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_SHFT                                      0xc
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_BMSK                          0x800
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_SHFT                            0xb
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK                  0x400
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT                    0xa
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_BMSK                                   0x200
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_SHFT                                     0x9
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_BMSK                                   0x100
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_SHFT                                     0x8
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_BMSK                                       0x80
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_SHFT                                        0x7
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_BMSK                             0x40
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_SHFT                              0x6
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EFUSE_CAM_SBI_ENABLE_IF_BMSK                          0x20
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EFUSE_CAM_SBI_ENABLE_IF_SHFT                           0x5
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_BMSK                                    0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_SHFT                                     0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_BMSK                                      0x8
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_SHFT                                      0x3
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_BMSK                            0x7
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_SHFT                            0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000015c)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_RMSK                                            0xe7fffff7
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_BMSK                          0x80000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_SHFT                                0x1f
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_BMSK                          0x40000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_SHFT                                0x1e
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_BMSK                                0x20000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_SHFT                                      0x1d
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_BMSK                                 0x4000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_SHFT                                      0x1a
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK              0x2000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT                   0x19
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_BMSK                  0x1000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_SHFT                       0x18
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_BMSK                  0x800000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_SHFT                      0x17
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_BMSK                            0x400000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_SHFT                                0x16
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_BMSK                       0x200000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_SHFT                           0x15
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_BMSK                                    0x100000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_SHFT                                        0x14
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_BMSK                                0x80000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_SHFT                                   0x13
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_BMSK                             0x7c000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_SHFT                                 0xe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_BMSK                          0x2000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_SHFT                             0xd
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_BMSK                             0x1000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_SHFT                                0xc
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_BMSK                                      0x800
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_SHFT                                        0xb
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_EFUSE_Q6SS_HVX_HALF_BMSK                             0x400
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_EFUSE_Q6SS_HVX_HALF_SHFT                               0xa
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_BMSK                                    0x200
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_SHFT                                      0x9
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_BMSK                                     0x1e0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_SHFT                                       0x5
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_BMSK                           0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_SHFT                            0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_BMSK                                    0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_SHFT                                    0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_BMSK                                    0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_SHFT                                    0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_BMSK                                    0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_SHFT                                    0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000160)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_BMSK                 0xffffc000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_SHFT                        0xe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_BMSK                       0x3c00
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_SHFT                          0xa
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_BMSK                     0x3ff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_SHFT                       0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000164)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_BMSK                        0xc0000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_SHFT                              0x1e
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_BMSK              0x20000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_SHFT                    0x1d
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_BMSK                  0x10000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_SHFT                        0x1c
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_BMSK                        0x8000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_SHFT                             0x1b
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_BMSK                                0x4000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_SHFT                                     0x1a
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_BMSK                      0x2000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_SHFT                           0x19
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_BMSK                                 0x1000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_SHFT                                      0x18
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_BMSK                   0xffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_SHFT                        0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000168)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_RMSK                                            0xfbffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_BMSK             0x80000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_SHFT                   0x1f
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_FUSE_CORTEX_M3_DISABLE_BMSK                     0x40000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_FUSE_CORTEX_M3_DISABLE_SHFT                           0x1e
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_Q_CONFIG_FUSE_BMSK                              0x20000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_Q_CONFIG_FUSE_SHFT                                    0x1d
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_I_MC5_FUSE_BMSK                                 0x10000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_I_MC5_FUSE_SHFT                                       0x1c
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_I_MC4_FUSE_BMSK                                  0x8000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_I_MC4_FUSE_SHFT                                       0x1b
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_BMSK               0x2000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_SHFT                    0x19
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_BMSK               0x1000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_SHFT                    0x18
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_BMSK                0x800000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_SHFT                    0x17
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_BMSK                0x400000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_SHFT                    0x16
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_BMSK                0x200000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_SHFT                    0x15
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_BMSK                 0x100000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_SHFT                     0x14
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_BMSK                         0x80000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_SHFT                            0x13
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_BMSK                         0x40000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_SHFT                            0x12
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_BMSK                    0x20000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_SHFT                       0x11
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_BMSK                    0x10000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_SHFT                       0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_BMSK                     0x8000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_SHFT                        0xf
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_BMSK                     0x4000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_SHFT                        0xe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_BMSK                    0x2000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_SHFT                       0xd
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_BMSK                    0x1000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_SHFT                       0xc
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                  0x800
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                    0xb
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK                   0x400
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT                     0xa
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_BMSK                        0x200
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_SHFT                          0x9
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_BMSK                        0x100
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_SHFT                          0x8
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_BMSK                         0x80
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_SHFT                          0x7
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_BMSK                         0x40
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_SHFT                          0x6
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_BMSK                        0x20
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_SHFT                         0x5
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_BMSK                        0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_SHFT                         0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK                      0x8
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT                      0x3
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK                       0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT                       0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_BMSK                                   0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_SHFT                                   0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_BMSK                                       0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_SHFT                                       0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000016c)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_BMSK                       0xff000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_SHFT                             0x18
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_APSS_KRYO_PP_DISABLE_BMSK                         0x800000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_APSS_KRYO_PP_DISABLE_SHFT                             0x17
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_BMSK                          0x400000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_SHFT                              0x16
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_BMSK                     0x200000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_SHFT                         0x15
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_BMSK                           0x1f8000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_SHFT                                0xf
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_BMSK                         0x4000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_SHFT                            0xe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_BMSK                        0x3fc0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_SHFT                           0x6
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_BMSK                   0x20
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_SHFT                    0x5
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_BMSK                   0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_SHFT                    0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_BMSK                    0x8
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_SHFT                    0x3
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_BMSK                    0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_SHFT                    0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_BMSK                    0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_SHFT                    0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_BMSK                    0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_SHFT                    0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000170)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_RMSK                                              0x7fffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_6_BMSK                       0x400000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_6_SHFT                           0x16
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_5_BMSK                       0x200000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_5_SHFT                           0x15
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_4_BMSK                       0x100000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_4_SHFT                           0x14
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_3_BMSK                        0x80000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_3_SHFT                           0x13
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_2_BMSK                        0x40000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_2_SHFT                           0x12
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_1_BMSK                        0x20000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_1_SHFT                           0x11
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_0_BMSK                        0x10000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_0_SHFT                           0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_BMSK                          0xffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_SHFT                             0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000174)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_RSVD_BMSK                                       0xfffffffe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_RSVD_SHFT                                              0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_DISABLE_SEC_BOOT_GPIO_BMSK                             0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW3_MSB_DISABLE_SEC_BOOT_GPIO_SHFT                             0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000178)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_RSVD_BMSK                                       0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_LSB_RSVD_SHFT                                              0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000017c)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_RSVD_BMSK                                       0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW4_MSB_RSVD_SHFT                                              0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000180)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_RSVD_BMSK                                       0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_LSB_RSVD_SHFT                                              0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000184)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_ADDR)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_RSVD_BMSK                                       0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW5_MSB_RSVD_SHFT                                              0x0

#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000188)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_IN)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_RSVD0_BMSK                                             0xfffffff0
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_RSVD0_SHFT                                                    0x4
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ROOT_CERT_ACTIVATION_LIST_BMSK                                0xf
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ROOT_CERT_ACTIVATION_LIST_SHFT                                0x0

#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000018c)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_IN)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_RSVD1_BMSK                                             0xfffffffe
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_RSVD1_SHFT                                                    0x1
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_CURRENT_UIE_KEY_SEL_BMSK                                      0x1
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_CURRENT_UIE_KEY_SEL_SHFT                                      0x0

#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000190)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_IN)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_RSVD0_BMSK                                             0xfffffff0
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_RSVD0_SHFT                                                    0x4
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ROOT_CERT_REVOCATION_LIST_BMSK                                0xf
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ROOT_CERT_REVOCATION_LIST_SHFT                                0x0

#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000194)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_IN)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_RSVD0_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_RSVD0_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000198)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW0_LSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_RSVD0_BMSK                                                 0xe0000000
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_RSVD0_SHFT                                                       0x1d
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_MACCHIATO_EN_BMSK                                          0x10000000
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_MACCHIATO_EN_SHFT                                                0x1c
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_FEATURE_ID_BMSK                                             0xff00000
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_FEATURE_ID_SHFT                                                  0x14
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_JTAG_ID_BMSK                                                  0xfffff
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_JTAG_ID_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000019c)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW0_MSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_PTE_DATA1_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_PTE_DATA1_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001a0)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW1_LSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_PTE_DATA0_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_PTE_DATA0_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001a4)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW1_MSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_PTE_DATA1_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_PTE_DATA1_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001a8)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_PTE_DATA0_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_PTE_DATA0_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001ac)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_PTE_DATA1_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_PTE_DATA1_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001b0)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW3_LSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_PTE_DATA0_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_PTE_DATA0_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001b4)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW3_MSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_PTE_DATA1_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_PTE_DATA1_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001b8)
#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW4_LSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW4_LSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_PTE_DATA0_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW4_LSB_PTE_DATA0_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001bc)
#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW4_MSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW4_MSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_PTE_DATA1_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW4_MSB_PTE_DATA1_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001c0)
#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW5_LSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW5_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW5_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW5_LSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_PTE_DATA0_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW5_LSB_PTE_DATA0_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001c4)
#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_PTE_ROW5_MSB_ADDR)
#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW5_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW5_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW5_MSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_PTE_DATA1_BMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW5_MSB_PTE_DATA1_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_RD_PERM_LSB_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001c8)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_RMSK                                                        0xffffffff
#define HWIO_QFPROM_RAW_RD_PERM_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_RD_PERM_LSB_ADDR)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_RD_PERM_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_RD_PERM_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_RD_PERM_LSB_ADDR,m,v,HWIO_QFPROM_RAW_RD_PERM_LSB_IN)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG31_BMSK                                        0x80000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG31_SHFT                                              0x1f
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG30_BMSK                                        0x40000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG30_SHFT                                              0x1e
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG29_BMSK                                        0x20000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG29_SHFT                                              0x1d
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG28_BMSK                                        0x10000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG28_SHFT                                              0x1c
#define HWIO_QFPROM_RAW_RD_PERM_LSB_USER_DATA_KEY_BMSK                                           0x8000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_USER_DATA_KEY_SHFT                                                0x1b
#define HWIO_QFPROM_RAW_RD_PERM_LSB_IMAGE_ENCR_KEY1_BMSK                                         0x4000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_IMAGE_ENCR_KEY1_SHFT                                              0x1a
#define HWIO_QFPROM_RAW_RD_PERM_LSB_BOOT_ROM_PATCH_BMSK                                          0x2000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_BOOT_ROM_PATCH_SHFT                                               0x19
#define HWIO_QFPROM_RAW_RD_PERM_LSB_SEC_KEY_DERIVATION_KEY_BMSK                                  0x1000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_SEC_KEY_DERIVATION_KEY_SHFT                                       0x18
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SEC_BOOT_BMSK                                             0x800000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SEC_BOOT_SHFT                                                 0x17
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_IMAGE_ENCR_KEY_BMSK                                       0x400000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_IMAGE_ENCR_KEY_SHFT                                           0x16
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG21_BMSK                                           0x200000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG21_SHFT                                               0x15
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG20_BMSK                                           0x100000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG20_SHFT                                               0x14
#define HWIO_QFPROM_RAW_RD_PERM_LSB_MEM_CONFIG_BMSK                                                0x80000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_MEM_CONFIG_SHFT                                                   0x13
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CALIB_BMSK                                                     0x40000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CALIB_SHFT                                                        0x12
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PK_HASH0_BMSK                                                  0x20000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PK_HASH0_SHFT                                                     0x11
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_5_BMSK                                           0x10000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_5_SHFT                                              0x10
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_4_BMSK                                            0x8000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_4_SHFT                                               0xf
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_3_BMSK                                            0x4000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_3_SHFT                                               0xe
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_2_BMSK                                            0x2000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_2_SHFT                                               0xd
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_1_BMSK                                            0x1000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_1_SHFT                                               0xc
#define HWIO_QFPROM_RAW_RD_PERM_LSB_FEAT_CONFIG_BMSK                                                 0x800
#define HWIO_QFPROM_RAW_RD_PERM_LSB_FEAT_CONFIG_SHFT                                                   0xb
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_CONFIG_BMSK                                                  0x400
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_CONFIG_SHFT                                                    0xa
#define HWIO_QFPROM_RAW_RD_PERM_LSB_FEC_EN_BMSK                                                      0x200
#define HWIO_QFPROM_RAW_RD_PERM_LSB_FEC_EN_SHFT                                                        0x9
#define HWIO_QFPROM_RAW_RD_PERM_LSB_WR_PERM_BMSK                                                     0x100
#define HWIO_QFPROM_RAW_RD_PERM_LSB_WR_PERM_SHFT                                                       0x8
#define HWIO_QFPROM_RAW_RD_PERM_LSB_RD_PERM_BMSK                                                      0x80
#define HWIO_QFPROM_RAW_RD_PERM_LSB_RD_PERM_SHFT                                                       0x7
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PTE_BMSK                                                          0x40
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PTE_SHFT                                                           0x6
#define HWIO_QFPROM_RAW_RD_PERM_LSB_MRC_2_0_BMSK                                                      0x20
#define HWIO_QFPROM_RAW_RD_PERM_LSB_MRC_2_0_SHFT                                                       0x5
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CM_FEAT_CONFIG_BMSK                                               0x10
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CM_FEAT_CONFIG_SHFT                                                0x4
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PRI_KEY_DERIVATION_KEY_BMSK                                        0x8
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PRI_KEY_DERIVATION_KEY_SHFT                                        0x3
#define HWIO_QFPROM_RAW_RD_PERM_LSB_BOOT_PATCH_HASH_BMSK                                               0x4
#define HWIO_QFPROM_RAW_RD_PERM_LSB_BOOT_PATCH_HASH_SHFT                                               0x2
#define HWIO_QFPROM_RAW_RD_PERM_LSB_LCM_BMSK                                                           0x2
#define HWIO_QFPROM_RAW_RD_PERM_LSB_LCM_SHFT                                                           0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CRI_CM_PRIVATE_BMSK                                                0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CRI_CM_PRIVATE_SHFT                                                0x0

#define HWIO_QFPROM_RAW_RD_PERM_MSB_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001cc)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_RMSK                                                        0xffffffff
#define HWIO_QFPROM_RAW_RD_PERM_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_RD_PERM_MSB_ADDR)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_RD_PERM_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_RD_PERM_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_RD_PERM_MSB_ADDR,m,v,HWIO_QFPROM_RAW_RD_PERM_MSB_IN)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_RSVD0_BMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_RD_PERM_MSB_RSVD0_SHFT                                                         0x0

#define HWIO_QFPROM_RAW_WR_PERM_LSB_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001d0)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_RMSK                                                        0xffffffff
#define HWIO_QFPROM_RAW_WR_PERM_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_WR_PERM_LSB_ADDR)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_WR_PERM_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_WR_PERM_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_WR_PERM_LSB_ADDR,m,v,HWIO_QFPROM_RAW_WR_PERM_LSB_IN)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG31_BMSK                                        0x80000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG31_SHFT                                              0x1f
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG30_BMSK                                        0x40000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG30_SHFT                                              0x1e
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG29_BMSK                                        0x20000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG29_SHFT                                              0x1d
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG28_BMSK                                        0x10000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG28_SHFT                                              0x1c
#define HWIO_QFPROM_RAW_WR_PERM_LSB_USER_DATA_KEY_BMSK                                           0x8000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_USER_DATA_KEY_SHFT                                                0x1b
#define HWIO_QFPROM_RAW_WR_PERM_LSB_IMAGE_ENCR_KEY1_BMSK                                         0x4000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_IMAGE_ENCR_KEY1_SHFT                                              0x1a
#define HWIO_QFPROM_RAW_WR_PERM_LSB_BOOT_ROM_PATCH_BMSK                                          0x2000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_BOOT_ROM_PATCH_SHFT                                               0x19
#define HWIO_QFPROM_RAW_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_BMSK                                  0x1000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_SHFT                                       0x18
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SEC_BOOT_BMSK                                             0x800000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SEC_BOOT_SHFT                                                 0x17
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_IMAGE_ENCR_KEY_BMSK                                       0x400000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_IMAGE_ENCR_KEY_SHFT                                           0x16
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG21_BMSK                                           0x200000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG21_SHFT                                               0x15
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG20_BMSK                                           0x100000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG20_SHFT                                               0x14
#define HWIO_QFPROM_RAW_WR_PERM_LSB_MEM_CONFIG_BMSK                                                0x80000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_MEM_CONFIG_SHFT                                                   0x13
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CALIB_BMSK                                                     0x40000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CALIB_SHFT                                                        0x12
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PK_HASH0_BMSK                                                  0x20000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PK_HASH0_SHFT                                                     0x11
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_5_BMSK                                           0x10000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_5_SHFT                                              0x10
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_4_BMSK                                            0x8000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_4_SHFT                                               0xf
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_3_BMSK                                            0x4000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_3_SHFT                                               0xe
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_2_BMSK                                            0x2000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_2_SHFT                                               0xd
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_1_BMSK                                            0x1000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_1_SHFT                                               0xc
#define HWIO_QFPROM_RAW_WR_PERM_LSB_FEAT_CONFIG_BMSK                                                 0x800
#define HWIO_QFPROM_RAW_WR_PERM_LSB_FEAT_CONFIG_SHFT                                                   0xb
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_CONFIG_BMSK                                                  0x400
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_CONFIG_SHFT                                                    0xa
#define HWIO_QFPROM_RAW_WR_PERM_LSB_FEC_EN_BMSK                                                      0x200
#define HWIO_QFPROM_RAW_WR_PERM_LSB_FEC_EN_SHFT                                                        0x9
#define HWIO_QFPROM_RAW_WR_PERM_LSB_WR_PERM_BMSK                                                     0x100
#define HWIO_QFPROM_RAW_WR_PERM_LSB_WR_PERM_SHFT                                                       0x8
#define HWIO_QFPROM_RAW_WR_PERM_LSB_RD_PERM_BMSK                                                      0x80
#define HWIO_QFPROM_RAW_WR_PERM_LSB_RD_PERM_SHFT                                                       0x7
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PTE_BMSK                                                          0x40
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PTE_SHFT                                                           0x6
#define HWIO_QFPROM_RAW_WR_PERM_LSB_MRC_2_0_BMSK                                                      0x20
#define HWIO_QFPROM_RAW_WR_PERM_LSB_MRC_2_0_SHFT                                                       0x5
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CM_FEAT_CONFIG_BMSK                                               0x10
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CM_FEAT_CONFIG_SHFT                                                0x4
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PRI_KEY_DERIVATION_KEY_BMSK                                        0x8
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PRI_KEY_DERIVATION_KEY_SHFT                                        0x3
#define HWIO_QFPROM_RAW_WR_PERM_LSB_BOOT_PATCH_HASH_BMSK                                               0x4
#define HWIO_QFPROM_RAW_WR_PERM_LSB_BOOT_PATCH_HASH_SHFT                                               0x2
#define HWIO_QFPROM_RAW_WR_PERM_LSB_LCM_BMSK                                                           0x2
#define HWIO_QFPROM_RAW_WR_PERM_LSB_LCM_SHFT                                                           0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CRI_CM_PRIVATE_BMSK                                                0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CRI_CM_PRIVATE_SHFT                                                0x0

#define HWIO_QFPROM_RAW_WR_PERM_MSB_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001d4)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_RMSK                                                        0xffffffff
#define HWIO_QFPROM_RAW_WR_PERM_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_WR_PERM_MSB_ADDR)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_WR_PERM_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_WR_PERM_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_WR_PERM_MSB_ADDR,m,v,HWIO_QFPROM_RAW_WR_PERM_MSB_IN)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_RSVD0_BMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_WR_PERM_MSB_RSVD0_SHFT                                                         0x0

#define HWIO_QFPROM_RAW_FEC_EN_LSB_ADDR                                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001d8)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_RMSK                                                         0xffffffff
#define HWIO_QFPROM_RAW_FEC_EN_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEC_EN_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEC_EN_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEC_EN_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEC_EN_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEC_EN_LSB_IN)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION31_FEC_EN_BMSK                                         0x80000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION31_FEC_EN_SHFT                                               0x1f
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION30_FEC_EN_BMSK                                         0x40000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION30_FEC_EN_SHFT                                               0x1e
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION29_FEC_EN_BMSK                                         0x20000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION29_FEC_EN_SHFT                                               0x1d
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION28_FEC_EN_BMSK                                         0x10000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION28_FEC_EN_SHFT                                               0x1c
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION27_FEC_EN_BMSK                                          0x8000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION27_FEC_EN_SHFT                                               0x1b
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION26_FEC_EN_BMSK                                          0x4000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION26_FEC_EN_SHFT                                               0x1a
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION25_FEC_EN_BMSK                                          0x2000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION25_FEC_EN_SHFT                                               0x19
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION24_FEC_EN_BMSK                                          0x1000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION24_FEC_EN_SHFT                                               0x18
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION23_FEC_EN_BMSK                                           0x800000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION23_FEC_EN_SHFT                                               0x17
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION22_FEC_EN_BMSK                                           0x400000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION22_FEC_EN_SHFT                                               0x16
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION21_FEC_EN_BMSK                                           0x200000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION21_FEC_EN_SHFT                                               0x15
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION20_FEC_EN_BMSK                                           0x100000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION20_FEC_EN_SHFT                                               0x14
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION19_FEC_EN_BMSK                                            0x80000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION19_FEC_EN_SHFT                                               0x13
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION18_FEC_EN_BMSK                                            0x40000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION18_FEC_EN_SHFT                                               0x12
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION17_FEC_EN_BMSK                                            0x20000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION17_FEC_EN_SHFT                                               0x11
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION16_FEC_EN_BMSK                                            0x10000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION16_FEC_EN_SHFT                                               0x10
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION15_FEC_EN_BMSK                                             0x8000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION15_FEC_EN_SHFT                                                0xf
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION14_FEC_EN_BMSK                                             0x4000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION14_FEC_EN_SHFT                                                0xe
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION13_FEC_EN_BMSK                                             0x2000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION13_FEC_EN_SHFT                                                0xd
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION12_FEC_EN_BMSK                                             0x1000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION12_FEC_EN_SHFT                                                0xc
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION11_FEC_EN_BMSK                                              0x800
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION11_FEC_EN_SHFT                                                0xb
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION10_FEC_EN_BMSK                                              0x400
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION10_FEC_EN_SHFT                                                0xa
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION9_FEC_EN_BMSK                                               0x200
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION9_FEC_EN_SHFT                                                 0x9
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION8_FEC_EN_BMSK                                               0x100
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION8_FEC_EN_SHFT                                                 0x8
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION7_FEC_EN_BMSK                                                0x80
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION7_FEC_EN_SHFT                                                 0x7
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION6_FEC_EN_BMSK                                                0x40
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION6_FEC_EN_SHFT                                                 0x6
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION5_FEC_EN_BMSK                                                0x20
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION5_FEC_EN_SHFT                                                 0x5
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION4_FEC_EN_BMSK                                                0x10
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION4_FEC_EN_SHFT                                                 0x4
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION3_FEC_EN_BMSK                                                 0x8
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION3_FEC_EN_SHFT                                                 0x3
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION2_FEC_EN_BMSK                                                 0x4
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION2_FEC_EN_SHFT                                                 0x2
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION1_FEC_EN_BMSK                                                 0x2
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION1_FEC_EN_SHFT                                                 0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION0_FEC_EN_BMSK                                                 0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION0_FEC_EN_SHFT                                                 0x0

#define HWIO_QFPROM_RAW_FEC_EN_MSB_ADDR                                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001dc)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_RMSK                                                         0xffffffff
#define HWIO_QFPROM_RAW_FEC_EN_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEC_EN_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEC_EN_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEC_EN_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEC_EN_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEC_EN_MSB_IN)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_RSVD0_BMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_FEC_EN_MSB_RSVD0_SHFT                                                          0x0

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001e0)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                    0x80000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                          0x1f
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_BMSK                     0x40000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_SHFT                           0x1e
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_BMSK                              0x20000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_SHFT                                    0x1d
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_BMSK                           0x10000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_SHFT                                 0x1c
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SP_DISABLE_BMSK                                      0x8000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SP_DISABLE_SHFT                                           0x1b
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_BMSK                                     0x4000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_SHFT                                          0x1a
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_DISABLE_IN_ROM_BMSK                            0x2000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_DISABLE_IN_ROM_SHFT                                 0x19
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_BMSK                 0x1000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_SHFT                      0x18
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_BMSK                0x800000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_SHFT                    0x17
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_BMSK                                   0x400000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_SHFT                                       0x16
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_BMSK                            0x200000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_SHFT                                0x15
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_BMSK                             0x100000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_SHFT                                 0x14
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_IMAGE_ENCRYPTION_ENABLE_BMSK                           0x80000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_IMAGE_ENCRYPTION_ENABLE_SHFT                              0x13
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ROOT_CERT_TOTAL_NUM_BMSK                               0x60000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ROOT_CERT_TOTAL_NUM_SHFT                                  0x11
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_USB_TYPE_C_DISABLE_BMSK                            0x10000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_USB_TYPE_C_DISABLE_SHFT                               0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_LOG_DISABLE_BMSK                                    0x8000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_LOG_DISABLE_SHFT                                       0xf
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_WDOG_EN_BMSK                                            0x4000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_WDOG_EN_SHFT                                               0xe
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_BMSK               0x2000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_SHFT                  0xd
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_FUSE_PROG_DISABLE_BMSK                               0x1000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_FUSE_PROG_DISABLE_SHFT                                  0xc
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SPI_CLK_BOOT_FREQ_BMSK                                   0x800
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SPI_CLK_BOOT_FREQ_SHFT                                     0xb
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_BMSK                           0x400
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_SHFT                             0xa
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_BMSK                                           0x3e0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SHFT                                             0x5
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SDCC_MCLK_BOOT_FREQ_BMSK                                  0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SDCC_MCLK_BOOT_FREQ_SHFT                                   0x4
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_BMSK                                0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_SHFT                                0x3
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_BMSK                                   0x4
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_SHFT                                   0x2
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_BMSK                                          0x2
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_SHFT                                          0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_BMSK                                       0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_SHFT                                       0x0

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001e4)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_RSVD1_BMSK                                          0xffffc000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_RSVD1_SHFT                                                 0xe
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_BMSK                         0x2000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_SHFT                            0xd
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_BMSK                         0x1000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_SHFT                            0xc
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_BMSK                          0x800
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_SHFT                            0xb
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_BMSK                          0x400
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_SHFT                            0xa
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_BMSK                          0x200
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_SHFT                            0x9
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_BMSK                           0x100
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_SHFT                             0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_BMSK                                   0x80
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_SHFT                                    0x7
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_BMSK                                   0x40
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_SHFT                                    0x6
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_BMSK                              0x20
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_SHFT                               0x5
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_BMSK                              0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_SHFT                               0x4
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_BMSK                               0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_SHFT                               0x3
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_BMSK                               0x4
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_SHFT                               0x2
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_BMSK                              0x2
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_SHFT                              0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_BMSK                              0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_SHFT                              0x0

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001e8)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_DISABLE_RSA_BMSK                                    0x80000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_DISABLE_RSA_SHFT                                          0x1f
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_EKU_ENFORCEMENT_EN_BMSK                             0x40000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_EKU_ENFORCEMENT_EN_SHFT                                   0x1e
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD2_BMSK                                          0x3fff0000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD2_SHFT                                                0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_BMSK                                 0x8000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_SHFT                                    0xf
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_BMSK                                 0x4000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_SHFT                                    0xe
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_BMSK                                 0x2000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_SHFT                                    0xd
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_BMSK                                 0x1000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_SHFT                                    0xc
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_BMSK                                               0xf00
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_SHFT                                                 0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_OVERRIDE_BMSK                           0x80
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_OVERRIDE_SHFT                            0x7
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_FIPS_OVERRIDE_BMSK                                     0x40
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_FIPS_OVERRIDE_SHFT                                      0x6
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_MODEM_CRYPTO_FIPS_ENABLE_BMSK                             0x20
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_MODEM_CRYPTO_FIPS_ENABLE_SHFT                              0x5
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_ENABLE_BMSK                             0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_ENABLE_SHFT                              0x4
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_FIPS_ENABLE_BMSK                                        0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_FIPS_ENABLE_SHFT                                        0x3
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_NVM_AR_CONFIG_BMSK                                      0x6
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_NVM_AR_CONFIG_SHFT                                      0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD0_BMSK                                                 0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD0_SHFT                                                 0x0

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001ec)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OEM_PRODUCT_ID_BMSK                                 0xffff0000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OEM_PRODUCT_ID_SHFT                                       0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OEM_HW_ID_BMSK                                          0xffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OEM_HW_ID_SHFT                                             0x0

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001f0)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PERIPH_VID_BMSK                                     0xffff0000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PERIPH_VID_SHFT                                           0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PERIPH_PID_BMSK                                         0xffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PERIPH_PID_SHFT                                            0x0

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001f4)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_RSVD0_BMSK                                          0xffffff00
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_RSVD0_SHFT                                                 0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ANTI_ROLLBACK_FEATURE_EN_BMSK                             0xff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ANTI_ROLLBACK_FEATURE_EN_SHFT                              0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001f8)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_RMSK                                               0x7fffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_BMSK                       0x40000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_SHFT                             0x1e
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_BMSK                                 0x20000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_SHFT                                       0x1d
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_BMSK                          0x1fe00000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_SHFT                                0x15
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_BMSK                           0x180000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_SHFT                               0x13
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_BMSK                         0x40000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_SHFT                            0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_BMSK                         0x20000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_SHFT                            0x11
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_BMSK                                  0x10000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_SHFT                                     0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_BMSK                                  0x8000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_SHFT                                     0xf
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_BMSK                                  0x4000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_SHFT                                     0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_BMSK                                        0x2000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_SHFT                                           0xd
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_BMSK                                      0x1000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_SHFT                                         0xc
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_BMSK                             0x800
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_SHFT                               0xb
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK                     0x400
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT                       0xa
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_BMSK                                      0x200
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_SHFT                                        0x9
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_BMSK                                      0x100
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_SHFT                                        0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_BMSK                                          0x80
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_SHFT                                           0x7
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_BMSK                                0x40
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_SHFT                                 0x6
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EFUSE_CAM_SBI_ENABLE_IF_BMSK                             0x20
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EFUSE_CAM_SBI_ENABLE_IF_SHFT                              0x5
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_BMSK                                       0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_SHFT                                        0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_BMSK                                         0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_SHFT                                         0x3
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_BMSK                               0x7
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_SHFT                               0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001fc)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_RMSK                                               0xe7fffff7
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_BMSK                             0x80000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_SHFT                                   0x1f
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_BMSK                             0x40000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_SHFT                                   0x1e
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_BMSK                                   0x20000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_SHFT                                         0x1d
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_BMSK                                    0x4000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_SHFT                                         0x1a
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK                 0x2000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT                      0x19
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_BMSK                     0x1000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_SHFT                          0x18
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_BMSK                     0x800000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_SHFT                         0x17
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_BMSK                               0x400000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_SHFT                                   0x16
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_BMSK                          0x200000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_SHFT                              0x15
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_BMSK                                       0x100000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_SHFT                                           0x14
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_BMSK                                   0x80000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_SHFT                                      0x13
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_BMSK                                0x7c000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_SHFT                                    0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_BMSK                             0x2000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_SHFT                                0xd
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_BMSK                                0x1000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_SHFT                                   0xc
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_BMSK                                         0x800
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_SHFT                                           0xb
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_EFUSE_Q6SS_HVX_HALF_BMSK                                0x400
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_EFUSE_Q6SS_HVX_HALF_SHFT                                  0xa
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_BMSK                                       0x200
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_SHFT                                         0x9
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_BMSK                                        0x1e0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_SHFT                                          0x5
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_BMSK                              0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_SHFT                               0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_BMSK                                       0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_SHFT                                       0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_BMSK                                       0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_SHFT                                       0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_BMSK                                       0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_SHFT                                       0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000200)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_BMSK                    0xffffc000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_SHFT                           0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_BMSK                          0x3c00
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_SHFT                             0xa
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_BMSK                        0x3ff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_SHFT                          0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000204)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_BMSK                           0xc0000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_SHFT                                 0x1e
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_BMSK                 0x20000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_SHFT                       0x1d
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_BMSK                     0x10000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_SHFT                           0x1c
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_BMSK                           0x8000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_SHFT                                0x1b
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_BMSK                                   0x4000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_SHFT                                        0x1a
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_BMSK                         0x2000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_SHFT                              0x19
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_BMSK                                    0x1000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_SHFT                                         0x18
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_BMSK                      0xffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_SHFT                           0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000208)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_RMSK                                               0xfbffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_BMSK                0x80000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_SHFT                      0x1f
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_FUSE_CORTEX_M3_DISABLE_BMSK                        0x40000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_FUSE_CORTEX_M3_DISABLE_SHFT                              0x1e
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_Q_CONFIG_FUSE_BMSK                                 0x20000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_Q_CONFIG_FUSE_SHFT                                       0x1d
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_I_MC5_FUSE_BMSK                                    0x10000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_I_MC5_FUSE_SHFT                                          0x1c
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_I_MC4_FUSE_BMSK                                     0x8000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_I_MC4_FUSE_SHFT                                          0x1b
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_BMSK                  0x2000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_SHFT                       0x19
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_BMSK                  0x1000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_SHFT                       0x18
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_BMSK                   0x800000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_SHFT                       0x17
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_BMSK                   0x400000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_SHFT                       0x16
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_BMSK                   0x200000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_SHFT                       0x15
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_BMSK                    0x100000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_SHFT                        0x14
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_BMSK                            0x80000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_SHFT                               0x13
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_BMSK                            0x40000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_SHFT                               0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_BMSK                       0x20000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_SHFT                          0x11
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_BMSK                       0x10000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_SHFT                          0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_BMSK                        0x8000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_SHFT                           0xf
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_BMSK                        0x4000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_SHFT                           0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_BMSK                       0x2000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_SHFT                          0xd
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_BMSK                       0x1000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_SHFT                          0xc
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                     0x800
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                       0xb
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK                      0x400
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT                        0xa
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_BMSK                           0x200
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_SHFT                             0x9
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_BMSK                           0x100
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_SHFT                             0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_BMSK                            0x80
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_SHFT                             0x7
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_BMSK                            0x40
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_SHFT                             0x6
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_BMSK                           0x20
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_SHFT                            0x5
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_BMSK                           0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_SHFT                            0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK                         0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT                         0x3
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK                          0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT                          0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_BMSK                                      0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_SHFT                                      0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_BMSK                                          0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_SHFT                                          0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000020c)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_BMSK                          0xff000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_SHFT                                0x18
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_APSS_KRYO_PP_DISABLE_BMSK                            0x800000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_APSS_KRYO_PP_DISABLE_SHFT                                0x17
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_BMSK                             0x400000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_SHFT                                 0x16
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_BMSK                        0x200000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_SHFT                            0x15
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_BMSK                              0x1f8000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_SHFT                                   0xf
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_BMSK                            0x4000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_SHFT                               0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_BMSK                           0x3fc0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_SHFT                              0x6
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_BMSK                      0x20
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_SHFT                       0x5
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_BMSK                      0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_SHFT                       0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_BMSK                       0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_SHFT                       0x3
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_BMSK                       0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_SHFT                       0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_BMSK                       0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_SHFT                       0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_BMSK                       0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_SHFT                       0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000210)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_RMSK                                                 0x7fffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_6_BMSK                          0x400000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_6_SHFT                              0x16
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_5_BMSK                          0x200000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_5_SHFT                              0x15
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_4_BMSK                          0x100000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_4_SHFT                              0x14
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_3_BMSK                           0x80000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_3_SHFT                              0x13
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_2_BMSK                           0x40000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_2_SHFT                              0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_1_BMSK                           0x20000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_1_SHFT                              0x11
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_0_BMSK                           0x10000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_0_SHFT                              0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_BMSK                             0xffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_SHFT                                0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000214)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_RSVD_BMSK                                          0xfffffffe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_RSVD_SHFT                                                 0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_DISABLE_SEC_BOOT_GPIO_BMSK                                0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_DISABLE_SEC_BOOT_GPIO_SHFT                                0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000218)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_RSVD_BMSK                                          0xfffffffe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_RSVD_SHFT                                                 0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_LEGACY_MBNV6_OVERRIDE_BMSK                                0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_LEGACY_MBNV6_OVERRIDE_SHFT                                0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000021c)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_RSVD_BMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_RSVD_SHFT                                                 0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000220)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_RSVD_BMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_LSB_RSVD_SHFT                                                 0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000224)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_RSVD_BMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW5_MSB_RSVD_SHFT                                                 0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000228)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_TAP_GEN_SPARE_INSTR_DISABLE_13_0_BMSK              0xfffc0000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_TAP_GEN_SPARE_INSTR_DISABLE_13_0_SHFT                    0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_TAP_INSTR_DISABLE_BMSK                                0x3ffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_LSB_TAP_INSTR_DISABLE_SHFT                                    0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000022c)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_SEC_TAP_ACCESS_DISABLE_BMSK                        0xfffc0000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_SEC_TAP_ACCESS_DISABLE_SHFT                              0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_TAP_GEN_SPARE_INSTR_DISABLE_31_14_BMSK                0x3ffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW6_MSB_TAP_GEN_SPARE_INSTR_DISABLE_31_14_SHFT                    0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000230)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_MODEM_PBL_PATCH_VERSION_BMSK                       0xfe000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_MODEM_PBL_PATCH_VERSION_SHFT                             0x19
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_APPS_PBL_PATCH_VERSION_BMSK                         0x1fc0000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_APPS_PBL_PATCH_VERSION_SHFT                              0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_APPS_PBL_BOOT_SPEED_BMSK                              0x30000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_APPS_PBL_BOOT_SPEED_SHFT                                 0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_MODEM_PBL_BOOT_BMSK                                    0x8000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_MODEM_PBL_BOOT_SHFT                                       0xf
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_RSVD1_56_14_BMSK                                       0x4000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_RSVD1_56_14_SHFT                                          0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_APPS_BOOT_FROM_ROM_BMSK                                0x2000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_APPS_BOOT_FROM_ROM_SHFT                                   0xd
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ENABLE_DEVICE_IN_TEST_MODE_BMSK                        0x1000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ENABLE_DEVICE_IN_TEST_MODE_SHFT                           0xc
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_QTI_ROOT_SIG_FORMAT_SEL_BMSK                            0x800
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_QTI_ROOT_SIG_FORMAT_SEL_SHFT                              0xb
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_CE_BAM_DISABLE_BMSK                                     0x400
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_CE_BAM_DISABLE_SHFT                                       0xa
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_BMSK                 0x200
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_SHFT                   0x9
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ARM_CE_DISABLE_USAGE_BMSK                               0x100
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_ARM_CE_DISABLE_USAGE_SHFT                                 0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_BOOT_ROM_CFG_BMSK                                        0xff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_LSB_BOOT_ROM_CFG_SHFT                                         0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000234)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_ADDR)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_APPS_BOOT_TRIGGER_DISABLE_BMSK                     0x80000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_APPS_BOOT_TRIGGER_DISABLE_SHFT                           0x1f
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_PBL_QSEE_BOOT_FLOW_DISABLE_BMSK                    0x40000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_PBL_QSEE_BOOT_FLOW_DISABLE_SHFT                          0x1e
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_XBL_SEC_AUTH_DISABLE_BMSK                          0x20000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_XBL_SEC_AUTH_DISABLE_SHFT                                0x1d
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_MSM_PKG_TYPE_BMSK                                  0x10000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_MSM_PKG_TYPE_SHFT                                        0x1c
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_SPSS_CONFIG_MODE_BMSK                               0xc000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_SPSS_CONFIG_MODE_SHFT                                    0x1a
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_PERIPH_DRV_STRENGTH_SETTING_BMSK                    0x3800000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_PERIPH_DRV_STRENGTH_SETTING_SHFT                         0x17
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_RSVD3_56_54_BMSK                                     0x400000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_RSVD3_56_54_SHFT                                         0x16
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_BMSK                                      0x3c0000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_SHFT                                          0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_PLL_CFG_BMSK                                          0x3fff0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_PLL_CFG_SHFT                                              0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_APPS_PBL_PLL_CTRL_BMSK                                    0xf
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW7_MSB_APPS_PBL_PLL_CTRL_SHFT                                    0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000238)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_XBL0_BMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_XBL0_SHFT                                                  0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000023c)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_XBL1_BMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_XBL1_SHFT                                                  0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000240)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_PIL_SUBSYSTEM_31_0_BMSK                             0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_PIL_SUBSYSTEM_31_0_SHFT                                    0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000244)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_XBL_SEC_BMSK                                        0xfe000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_XBL_SEC_SHFT                                              0x19
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_AOP_BMSK                                             0x1fe0000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_AOP_SHFT                                                  0x11
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_TZ_BMSK                                                0x1ffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_TZ_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000248)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_XBL_CONFIG_1_0_BMSK                                 0xc0000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_XBL_CONFIG_1_0_SHFT                                       0x1e
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_TQS_HASH_ACTIVE_BMSK                                0x3e000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_TQS_HASH_ACTIVE_SHFT                                      0x19
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_BMSK                            0x1000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_SHFT                                 0x18
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_PIL_SUBSYSTEM_47_32_BMSK                              0xffff00
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_PIL_SUBSYSTEM_47_32_SHFT                                   0x8
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_SAFESWITCH_BMSK                                           0xff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_SAFESWITCH_SHFT                                            0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000024c)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_XBL_CONFIG_5_2_BMSK                                 0xf0000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_XBL_CONFIG_5_2_SHFT                                       0x1c
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_DEVICE_CFG_BMSK                                      0xffe0000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_DEVICE_CFG_SHFT                                           0x11
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_DEBUG_POLICY_BMSK                                      0x1f000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_DEBUG_POLICY_SHFT                                          0xc
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_HYPERVISOR_BMSK                                          0xfff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_HYPERVISOR_SHFT                                            0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000250)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_MSS_BMSK                                            0xffff0000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_MSS_SHFT                                                  0x10
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_MISC_BMSK                                               0xffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_MISC_SHFT                                                  0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000254)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_SIMLOCK_BMSK                                        0x80000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_SIMLOCK_SHFT                                              0x1f
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_RSVD0_BMSK                                          0x7ffffff0
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_RSVD0_SHFT                                                 0x4
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ROOT_CERT_PK_HASH_INDEX_BMSK                               0xf
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ROOT_CERT_PK_HASH_INDEX_SHFT                               0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000258)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_MISC_BMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_MISC_SHFT                                                  0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000025c)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ADDR)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_RSVD0_BMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_RSVD0_SHFT                                                 0x0

#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_ADDR(n)                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000260 + 0x8 * (n))
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_MAXn                                                           5
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_HASH_DATA0_BMSK                                       0xffffffff
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_HASH_DATA0_SHFT                                              0x0

#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_ADDR(n)                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000264 + 0x8 * (n))
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_MAXn                                                           5
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_HASH_DATA1_BMSK                                       0xffffffff
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_HASH_DATA1_SHFT                                              0x0

#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000290)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW0_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW0_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_USB_PHY0_TUNING_BMSK                                     0xf0000000
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_USB_PHY0_TUNING_SHFT                                           0x1c
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_SPARE_R63_B27_BMSK                                        0x8000000
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_SPARE_R63_B27_SHFT                                             0x1b
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_SPARE_R63_B26_BMSK                                        0x4000000
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_SPARE_R63_B26_SHFT                                             0x1a
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_SPARE_R63_B25_BMSK                                        0x2000000
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_SPARE_R63_B25_SHFT                                             0x19
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_USB2PHY_RCAL_CODE_BMSK                                    0x1e00000
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_USB2PHY_RCAL_CODE_SHFT                                         0x15
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_SPARE_R63_B20_BMSK                                         0x100000
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_SPARE_R63_B20_SHFT                                             0x14
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_SPARE_R63_B19_BMSK                                          0x80000
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_SPARE_R63_B19_SHFT                                             0x13
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_SPARE_R63_B18_BMSK                                          0x40000
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_SPARE_R63_B18_SHFT                                             0x12
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_MSS_Q6SS1_LDO_VREF_TRIM_BMSK                                0x3e000
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_MSS_Q6SS1_LDO_VREF_TRIM_SHFT                                    0xd
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_SPARE_R63_B12_BMSK                                           0x1000
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_SPARE_R63_B12_SHFT                                              0xc
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_TURING_Q6SS1_LDO_VREF_TRIM_BMSK                               0xf80
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_TURING_Q6SS1_LDO_VREF_TRIM_SHFT                                 0x7
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_TURING_Q6SS1_LDO_ENABLE_NOM_BMSK                               0x40
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_TURING_Q6SS1_LDO_ENABLE_NOM_SHFT                                0x6
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_MSS_Q6SS0_LDO_VREF_TRIM_BMSK                                   0x3e
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_MSS_Q6SS0_LDO_VREF_TRIM_SHFT                                    0x1
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_MSS_Q6SS0_LDO_ENABLE_NOM_BMSK                                   0x1
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_MSS_Q6SS0_LDO_ENABLE_NOM_SHFT                                   0x0

#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000294)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW0_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW0_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW0_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_CPR0_TARG_VOLT_SVS3_BMSK                                 0xf8000000
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_CPR0_TARG_VOLT_SVS3_SHFT                                       0x1b
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_CPR0_TARG_VOLT_SVS_BMSK                                   0x7c00000
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_CPR0_TARG_VOLT_SVS_SHFT                                        0x16
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_CPR0_TARG_VOLT_NOM_BMSK                                    0x3e0000
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_CPR0_TARG_VOLT_NOM_SHFT                                        0x11
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_CPR0_TARG_VOLT_SUT_BMSK                                     0x1f000
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_CPR0_TARG_VOLT_SUT_SHFT                                         0xc
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_SPARE_R63_B43_BMSK                                            0x800
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_SPARE_R63_B43_SHFT                                              0xb
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_TURING_Q6SS1_LDO_ENABLE_MINSVS_BMSK                           0x400
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_TURING_Q6SS1_LDO_ENABLE_MINSVS_SHFT                             0xa
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_TURING_Q6SS1_LDO_ENABLE_LOWSVS_BMSK                           0x200
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_TURING_Q6SS1_LDO_ENABLE_LOWSVS_SHFT                             0x9
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_TURING_Q6SS1_LDO_ENABLE_SVS_BMSK                              0x100
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_TURING_Q6SS1_LDO_ENABLE_SVS_SHFT                                0x8
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_TURING_Q6SS1_LDO_ENABLE_SVS_L1_BMSK                            0x80
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_TURING_Q6SS1_LDO_ENABLE_SVS_L1_SHFT                             0x7
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_MSS_Q6SS0_LDO_ENABLE_MINSVS_BMSK                               0x40
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_MSS_Q6SS0_LDO_ENABLE_MINSVS_SHFT                                0x6
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_MSS_Q6SS0_LDO_ENABLE_LOWSVS_BMSK                               0x20
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_MSS_Q6SS0_LDO_ENABLE_LOWSVS_SHFT                                0x5
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_MSS_Q6SS0_LDO_ENABLE_SVS_BMSK                                  0x10
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_MSS_Q6SS0_LDO_ENABLE_SVS_SHFT                                   0x4
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_MSS_Q6SS0_LDO_ENABLE_SVS_L1_BMSK                                0x8
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_MSS_Q6SS0_LDO_ENABLE_SVS_L1_SHFT                                0x3
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_SPARE_R63_B34_BMSK                                              0x4
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_SPARE_R63_B34_SHFT                                              0x2
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_SPARE_R63_B33_BMSK                                              0x2
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_SPARE_R63_B33_SHFT                                              0x1
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_SPARE_R63_B32_BMSK                                              0x1
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_SPARE_R63_B32_SHFT                                              0x0

#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000298)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW1_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW1_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_CPR2_TARG_VOLT_SVS_1_0_BMSK                              0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_CPR2_TARG_VOLT_SVS_1_0_SHFT                                    0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_CPR2_TARG_VOLT_NOM_BMSK                                  0x3e000000
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_CPR2_TARG_VOLT_NOM_SHFT                                        0x19
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_CPR2_TARG_VOLT_SUT_BMSK                                   0x1f00000
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_CPR2_TARG_VOLT_SUT_SHFT                                        0x14
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_CPR1_TARG_VOLT_SVS3_BMSK                                    0xf8000
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_CPR1_TARG_VOLT_SVS3_SHFT                                        0xf
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_CPR1_TARG_VOLT_SVS_BMSK                                      0x7c00
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_CPR1_TARG_VOLT_SVS_SHFT                                         0xa
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_CPR1_TARG_VOLT_NOM_BMSK                                       0x3e0
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_CPR1_TARG_VOLT_NOM_SHFT                                         0x5
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_CPR1_TARG_VOLT_SUT_BMSK                                        0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_CPR1_TARG_VOLT_SUT_SHFT                                         0x0

#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000029c)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW1_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW1_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_SPARE_R64_B63_BMSK                                       0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_SPARE_R64_B63_SHFT                                             0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_REFGEN_NORTH_BGV_TRIM_BMSK                               0x7f800000
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_REFGEN_NORTH_BGV_TRIM_SHFT                                     0x17
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_REFGEN_SOUTH_BGV_TRIM_BMSK                                 0x7f8000
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_REFGEN_SOUTH_BGV_TRIM_SHFT                                      0xf
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_BANDGAP_TRIM_BMSK                                            0x7f00
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_BANDGAP_TRIM_SHFT                                               0x8
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_SPARE_R64_B39_BMSK                                             0x80
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_SPARE_R64_B39_SHFT                                              0x7
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_SPARE_R64_B38_BMSK                                             0x40
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_SPARE_R64_B38_SHFT                                              0x6
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_SPARE_R64_B37_BMSK                                             0x20
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_SPARE_R64_B37_SHFT                                              0x5
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_SPARE_R64_B36_BMSK                                             0x10
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_SPARE_R64_B36_SHFT                                              0x4
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_SPARE_R64_B35_BMSK                                              0x8
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_SPARE_R64_B35_SHFT                                              0x3
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_CPR2_TARG_VOLT_SVS_4_2_BMSK                                     0x7
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_CPR2_TARG_VOLT_SVS_4_2_SHFT                                     0x0

#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002a0)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW2_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_CPR4_TARG_VOLT_TUR_1_0_BMSK                              0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_CPR4_TARG_VOLT_TUR_1_0_SHFT                                    0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_CPR4_TARG_VOLT_SUT_BMSK                                  0x3e000000
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_CPR4_TARG_VOLT_SUT_SHFT                                        0x19
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_CPR3_TARG_VOLT_SVS3_BMSK                                  0x1f00000
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_CPR3_TARG_VOLT_SVS3_SHFT                                       0x14
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_CPR3_TARG_VOLT_SVS_BMSK                                     0xf8000
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_CPR3_TARG_VOLT_SVS_SHFT                                         0xf
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_CPR3_TARG_VOLT_NOM_BMSK                                      0x7c00
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_CPR3_TARG_VOLT_NOM_SHFT                                         0xa
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_CPR3_TARG_VOLT_TUR_BMSK                                       0x3e0
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_CPR3_TARG_VOLT_TUR_SHFT                                         0x5
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_CPR2_TARG_VOLT_SVS3_BMSK                                       0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_CPR2_TARG_VOLT_SVS3_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002a4)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW2_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_CPR6_TARG_VOLT_NOM_3_0_BMSK                              0xf0000000
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_CPR6_TARG_VOLT_NOM_3_0_SHFT                                    0x1c
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_CPR6_TARG_VOLT_TUR_BMSK                                   0xf800000
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_CPR6_TARG_VOLT_TUR_SHFT                                        0x17
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_CPR5_TARG_VOLT_NOM_BMSK                                    0x7c0000
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_CPR5_TARG_VOLT_NOM_SHFT                                        0x12
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_CPR5_TARG_VOLT_TUR_BMSK                                     0x3e000
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_CPR5_TARG_VOLT_TUR_SHFT                                         0xd
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_CPR4_TARG_VOLT_SVSP_BMSK                                     0x1f00
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_CPR4_TARG_VOLT_SVSP_SHFT                                        0x8
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_CPR4_TARG_VOLT_NOM_BMSK                                        0xf8
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_CPR4_TARG_VOLT_NOM_SHFT                                         0x3
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_CPR4_TARG_VOLT_TUR_4_2_BMSK                                     0x7
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_CPR4_TARG_VOLT_TUR_4_2_SHFT                                     0x0

#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002a8)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW3_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW3_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW3_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_AON_TARG_VOLT_0_BMSK                                     0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_AON_TARG_VOLT_0_SHFT                                           0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_CPR10_TARG_VOLT_SVS2_BMSK                                0x7c000000
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_CPR10_TARG_VOLT_SVS2_SHFT                                      0x1a
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_CPR10_TARG_VOLT_SVS_BMSK                                  0x3e00000
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_CPR10_TARG_VOLT_SVS_SHFT                                       0x15
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_CPR10_TARG_VOLT_NOM_BMSK                                   0x1f0000
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_CPR10_TARG_VOLT_NOM_SHFT                                       0x10
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_CPR10_TARG_VOLT_TUR_BMSK                                     0xf800
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_CPR10_TARG_VOLT_TUR_SHFT                                        0xb
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_CPR6_TARG_VOLT_SVS3_BMSK                                      0x7c0
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_CPR6_TARG_VOLT_SVS3_SHFT                                        0x6
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_CPR6_TARG_VOLT_SVS_BMSK                                        0x3e
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_CPR6_TARG_VOLT_SVS_SHFT                                         0x1
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_CPR6_TARG_VOLT_NOM_4_BMSK                                       0x1
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_CPR6_TARG_VOLT_NOM_4_SHFT                                       0x0

#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002ac)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW3_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW3_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW3_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_SVS2_1_0_BMSK                      0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_SVS2_1_0_SHFT                            0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_SVS_BMSK                           0x3c000000
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_SVS_SHFT                                 0x1a
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_NOM_BMSK                            0x3c00000
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_NOM_SHFT                                 0x16
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_TUR_BMSK                             0x3c0000
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_TUR_SHFT                                 0x12
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_SUT_BMSK                              0x3c000
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_SUT_SHFT                                  0xe
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_CPR11_TARG_VOLT_SVS2_BMSK                                    0x3f00
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_CPR11_TARG_VOLT_SVS2_SHFT                                       0x8
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_CPR11_SVS2_ROSEL_BMSK                                          0xf0
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_CPR11_SVS2_ROSEL_SHFT                                           0x4
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_AON_TARG_VOLT_4_1_BMSK                                          0xf
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_AON_TARG_VOLT_4_1_SHFT                                          0x0

#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002b0)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW4_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW4_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_SVS2_1_0_BMSK                      0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_SVS2_1_0_SHFT                            0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_SVS_BMSK                           0x3c000000
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_SVS_SHFT                                 0x1a
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_NOM_BMSK                            0x3c00000
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_NOM_SHFT                                 0x16
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_TUR_BMSK                             0x3c0000
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_TUR_SHFT                                 0x12
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_SUT_BMSK                              0x3c000
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_SUT_SHFT                                  0xe
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR0_AGING_BMSK                                              0x3fc0
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR0_AGING_SHFT                                                 0x6
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR0_TARG_VOLT_OFFSET_SVS3_BMSK                                0x3c
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR0_TARG_VOLT_OFFSET_SVS3_SHFT                                 0x2
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR0_TARG_VOLT_OFFSET_SVS2_3_2_BMSK                             0x3
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR0_TARG_VOLT_OFFSET_SVS2_3_2_SHFT                             0x0

#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002b4)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW4_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW4_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_SVS2_1_0_BMSK                      0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_SVS2_1_0_SHFT                            0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_SVS_BMSK                           0x3c000000
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_SVS_SHFT                                 0x1a
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_NOM_BMSK                            0x3c00000
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_NOM_SHFT                                 0x16
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_TUR_BMSK                             0x3c0000
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_TUR_SHFT                                 0x12
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_SUT_BMSK                              0x3c000
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_SUT_SHFT                                  0xe
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR1_AGING_BMSK                                              0x3fc0
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR1_AGING_SHFT                                                 0x6
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR1_TARG_VOLT_OFFSET_SVS3_BMSK                                0x3c
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR1_TARG_VOLT_OFFSET_SVS3_SHFT                                 0x2
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR1_TARG_VOLT_OFFSET_SVS2_3_2_BMSK                             0x3
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR1_TARG_VOLT_OFFSET_SVS2_3_2_SHFT                             0x0

#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002b8)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW5_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW5_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW5_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW5_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR9_TARG_VOLT_NOM_1_0_BMSK                              0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR9_TARG_VOLT_NOM_1_0_SHFT                                    0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_SVSP_BMSK                          0x3c000000
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_SVSP_SHFT                                0x1a
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_NOM_BMSK                            0x3c00000
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_NOM_SHFT                                 0x16
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_TUR_BMSK                             0x3c0000
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_TUR_SHFT                                 0x12
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_SUT_BMSK                              0x3c000
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_SUT_SHFT                                  0xe
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR2_AGING_BMSK                                              0x3fc0
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR2_AGING_SHFT                                                 0x6
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR2_TARG_VOLT_OFFSET_SVS3_BMSK                                0x3c
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR2_TARG_VOLT_OFFSET_SVS3_SHFT                                 0x2
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR2_TARG_VOLT_OFFSET_SVS2_3_2_BMSK                             0x3
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR2_TARG_VOLT_OFFSET_SVS2_3_2_SHFT                             0x0

#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002bc)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW5_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW5_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW5_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW5_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_AON_AGING_4_0_BMSK                                       0xf8000000
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_AON_AGING_4_0_SHFT                                             0x1b
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_CPR10_AGING_BMSK                                          0x7f80000
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_CPR10_AGING_SHFT                                               0x13
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_CPR10_TARG_VOLT_OFFSET_SVS2_BMSK                            0x78000
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_CPR10_TARG_VOLT_OFFSET_SVS2_SHFT                                0xf
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_CPR10_TARG_VOLT_OFFSET_SVS_BMSK                              0x7800
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_CPR10_TARG_VOLT_OFFSET_SVS_SHFT                                 0xb
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_CPR10_TARG_VOLT_OFFSET_NOM_BMSK                               0x780
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_CPR10_TARG_VOLT_OFFSET_NOM_SHFT                                 0x7
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_CPR10_TARG_VOLT_OFFSET_TUR_BMSK                                0x78
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_CPR10_TARG_VOLT_OFFSET_TUR_SHFT                                 0x3
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_CPR9_TARG_VOLT_NOM_4_2_BMSK                                     0x7
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_CPR9_TARG_VOLT_NOM_4_2_SHFT                                     0x0

#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002c0)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW6_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW6_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW6_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW6_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW6_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR_LDO_RC_1_0_BMSK                                      0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR_LDO_RC_1_0_SHFT                                            0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR8_LDO_TARG_VOLT_SVS3_BMSK                             0x3c000000
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR8_LDO_TARG_VOLT_SVS3_SHFT                                   0x1a
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR8_LDO_TARG_VOLT_SVS_BMSK                               0x3c00000
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR8_LDO_TARG_VOLT_SVS_SHFT                                    0x16
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR8_LDO_TARG_VOLT_NOM_BMSK                                0x3c0000
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR8_LDO_TARG_VOLT_NOM_SHFT                                    0x12
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR7_LDO_TARG_VOLT_SVS3_BMSK                                0x3c000
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR7_LDO_TARG_VOLT_SVS3_SHFT                                    0xe
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR7_LDO_TARG_VOLT_SVS2_BMSK                                 0x3c00
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR7_LDO_TARG_VOLT_SVS2_SHFT                                    0xa
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR7_LDO_TARG_VOLT_SVSP_BMSK                                  0x3c0
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR7_LDO_TARG_VOLT_SVSP_SHFT                                    0x6
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR_GLOBAL_RC_BMSK                                             0x38
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR_GLOBAL_RC_SHFT                                              0x3
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_AON_AGING_7_5_BMSK                                              0x7
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_AON_AGING_7_5_SHFT                                              0x0

#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002c4)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW6_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW6_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW6_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW6_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW6_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR11_TURBO_QUOT_VMIN_0_BMSK                             0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR11_TURBO_QUOT_VMIN_0_SHFT                                   0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR11_TARG_VOLT_SVS_BMSK                                 0x7e000000
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR11_TARG_VOLT_SVS_SHFT                                       0x19
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR11_TARG_VOLT_NOM_BMSK                                  0x1f80000
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR11_TARG_VOLT_NOM_SHFT                                       0x13
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR11_TARG_VOLT_TUR_BMSK                                    0x7e000
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR11_TARG_VOLT_TUR_SHFT                                        0xd
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR11_SVS_ROSEL_BMSK                                         0x1e00
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR11_SVS_ROSEL_SHFT                                            0x9
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR11_NOMINAL_ROSEL_BMSK                                      0x1e0
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR11_NOMINAL_ROSEL_SHFT                                        0x5
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR11_TURBO_ROSEL_BMSK                                         0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR11_TURBO_ROSEL_SHFT                                          0x1
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR_LDO_RC_2_BMSK                                               0x1
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR_LDO_RC_2_SHFT                                               0x0

#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002c8)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW7_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW7_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW7_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW7_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW7_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_CPR11_SVS_QUOT_VMIN_8_0_BMSK                             0xff800000
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_CPR11_SVS_QUOT_VMIN_8_0_SHFT                                   0x17
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_CPR11_NOMINAL_QUOT_VMIN_BMSK                               0x7ff800
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_CPR11_NOMINAL_QUOT_VMIN_SHFT                                    0xb
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_CPR11_TURBO_QUOT_VMIN_11_1_BMSK                               0x7ff
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_CPR11_TURBO_QUOT_VMIN_11_1_SHFT                                 0x0

#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002cc)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW7_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW7_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW7_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW7_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW7_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_CPR11_QUOT_OFFSET_SVS_1_0_BMSK                           0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_CPR11_QUOT_OFFSET_SVS_1_0_SHFT                                 0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_CPR11_QUOT_OFFSET_NOM_BMSK                               0x3f800000
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_CPR11_QUOT_OFFSET_NOM_SHFT                                     0x17
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_CPR11_QUOT_OFFSET_TUR_BMSK                                 0x7f8000
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_CPR11_QUOT_OFFSET_TUR_SHFT                                      0xf
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_CPR11_SVS2_QUOT_VMIN_BMSK                                    0x7ff8
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_CPR11_SVS2_QUOT_VMIN_SHFT                                       0x3
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_CPR11_SVS_QUOT_VMIN_11_9_BMSK                                   0x7
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_CPR11_SVS_QUOT_VMIN_11_9_SHFT                                   0x0

#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002d0)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW8_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW8_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW8_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW8_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW8_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_CPR12_TARG_VOLT_SVS2_0_BMSK                              0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_CPR12_TARG_VOLT_SVS2_0_SHFT                                    0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_CPR12_TARG_VOLT_SVS_BMSK                                 0x7e000000
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_CPR12_TARG_VOLT_SVS_SHFT                                       0x19
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_CPR12_TARG_VOLT_NOM_BMSK                                  0x1f80000
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_CPR12_TARG_VOLT_NOM_SHFT                                       0x13
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_CPR12_TARG_VOLT_TUR_BMSK                                    0x7e000
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_CPR12_TARG_VOLT_TUR_SHFT                                        0xd
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_CPR11_AGING_BMSK                                             0x1fe0
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_CPR11_AGING_SHFT                                                0x5
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_CPR11_QUOT_OFFSET_SVS_6_2_BMSK                                 0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_CPR11_QUOT_OFFSET_SVS_6_2_SHFT                                  0x0

#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002d4)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW8_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW8_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW8_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW8_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW8_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_CPR12_SVS_QUOT_VMIN_2_0_BMSK                             0xe0000000
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_CPR12_SVS_QUOT_VMIN_2_0_SHFT                                   0x1d
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_CPR12_NOMINAL_QUOT_VMIN_BMSK                             0x1ffe0000
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_CPR12_NOMINAL_QUOT_VMIN_SHFT                                   0x11
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_CPR12_TURBO_QUOT_VMIN_BMSK                                  0x1ffe0
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_CPR12_TURBO_QUOT_VMIN_SHFT                                      0x5
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_CPR12_TARG_VOLT_SVS2_5_1_BMSK                                  0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_CPR12_TARG_VOLT_SVS2_5_1_SHFT                                   0x0

#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002d8)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW9_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW9_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW9_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW9_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW9_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_CPR12_QUOT_OFFSET_NOM_2_0_BMSK                           0xe0000000
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_CPR12_QUOT_OFFSET_NOM_2_0_SHFT                                 0x1d
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_CPR12_QUOT_OFFSET_TUR_BMSK                               0x1fe00000
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_CPR12_QUOT_OFFSET_TUR_SHFT                                     0x15
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_CPR12_SVS2_QUOT_VMIN_BMSK                                  0x1ffe00
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_CPR12_SVS2_QUOT_VMIN_SHFT                                       0x9
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_CPR12_SVS_QUOT_VMIN_11_3_BMSK                                 0x1ff
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_CPR12_SVS_QUOT_VMIN_11_3_SHFT                                   0x0

#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002dc)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW9_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW9_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW9_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW9_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW9_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR13_TARG_VOLT_SUT_0_BMSK                               0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR13_TARG_VOLT_SUT_0_SHFT                                     0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR13_SVS2_ROSEL_BMSK                                    0x78000000
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR13_SVS2_ROSEL_SHFT                                          0x1b
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR13_SVS_ROSEL_BMSK                                      0x7800000
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR13_SVS_ROSEL_SHFT                                           0x17
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR13_NOMINAL_ROSEL_BMSK                                   0x780000
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR13_NOMINAL_ROSEL_SHFT                                       0x13
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR13_TURBO_ROSEL_BMSK                                      0x78000
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR13_TURBO_ROSEL_SHFT                                          0xf
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR13_STURBO_ROSEL_BMSK                                      0x7800
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR13_STURBO_ROSEL_SHFT                                         0xb
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR12_QUOT_OFFSET_SVS_BMSK                                    0x7f0
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR12_QUOT_OFFSET_SVS_SHFT                                      0x4
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR12_QUOT_OFFSET_NOM_6_3_BMSK                                  0xf
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR12_QUOT_OFFSET_NOM_6_3_SHFT                                  0x0

#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002e0)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW10_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW10_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW10_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW10_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW10_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_CPR13_SUT_QUOT_VMIN_2_0_BMSK                            0xe0000000
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_CPR13_SUT_QUOT_VMIN_2_0_SHFT                                  0x1d
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_CPR13_TARG_VOLT_SVS2_BMSK                               0x1f800000
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_CPR13_TARG_VOLT_SVS2_SHFT                                     0x17
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_CPR13_TARG_VOLT_SVS_BMSK                                  0x7e0000
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_CPR13_TARG_VOLT_SVS_SHFT                                      0x11
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_CPR13_TARG_VOLT_NOM_BMSK                                   0x1f800
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_CPR13_TARG_VOLT_NOM_SHFT                                       0xb
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_CPR13_TARG_VOLT_TUR_BMSK                                     0x7e0
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_CPR13_TARG_VOLT_TUR_SHFT                                       0x5
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_CPR13_TARG_VOLT_SUT_5_1_BMSK                                  0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_CPR13_TARG_VOLT_SUT_5_1_SHFT                                   0x0

#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002e4)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW10_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW10_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW10_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW10_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW10_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_CPR13_NOMINAL_QUOT_VMIN_10_0_BMSK                       0xffe00000
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_CPR13_NOMINAL_QUOT_VMIN_10_0_SHFT                             0x15
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_CPR13_TURBO_QUOT_VMIN_BMSK                                0x1ffe00
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_CPR13_TURBO_QUOT_VMIN_SHFT                                     0x9
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_CPR13_SUT_QUOT_VMIN_11_3_BMSK                                0x1ff
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_CPR13_SUT_QUOT_VMIN_11_3_SHFT                                  0x0

#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002e8)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW11_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW11_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW11_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW11_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW11_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_CPR13_QUOT_OFFSET_SUT_6_0_BMSK                          0xfe000000
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_CPR13_QUOT_OFFSET_SUT_6_0_SHFT                                0x19
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_CPR13_SVS2_QUOT_VMIN_BMSK                                0x1ffe000
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_CPR13_SVS2_QUOT_VMIN_SHFT                                      0xd
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_CPR13_SVS_QUOT_VMIN_BMSK                                    0x1ffe
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_CPR13_SVS_QUOT_VMIN_SHFT                                       0x1
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_CPR13_NOMINAL_QUOT_VMIN_11_BMSK                                0x1
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_CPR13_NOMINAL_QUOT_VMIN_11_SHFT                                0x0

#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002ec)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW11_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW11_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW11_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW11_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW11_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_CPR14_TARG_VOLT_TUR_0_BMSK                              0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_CPR14_TARG_VOLT_TUR_0_SHFT                                    0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_CPR13_AGING_BMSK                                        0x7f800000
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_CPR13_AGING_SHFT                                              0x17
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_CPR13_QUOT_OFFSET_SVS_BMSK                                0x7f0000
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_CPR13_QUOT_OFFSET_SVS_SHFT                                    0x10
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_CPR13_QUOT_OFFSET_NOM_BMSK                                  0xfe00
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_CPR13_QUOT_OFFSET_NOM_SHFT                                     0x9
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_CPR13_QUOT_OFFSET_TUR_BMSK                                   0x1fe
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_CPR13_QUOT_OFFSET_TUR_SHFT                                     0x1
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_CPR13_QUOT_OFFSET_SUT_7_BMSK                                   0x1
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_CPR13_QUOT_OFFSET_SUT_7_SHFT                                   0x0

#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002f0)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW12_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW12_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW12_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW12_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW12_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_CPR14_TURBO_QUOT_VMIN_8_0_BMSK                          0xff800000
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_CPR14_TURBO_QUOT_VMIN_8_0_SHFT                                0x17
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_CPR14_TARG_VOLT_SVS2_BMSK                                 0x7e0000
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_CPR14_TARG_VOLT_SVS2_SHFT                                     0x11
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_CPR14_TARG_VOLT_SVS_BMSK                                   0x1f800
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_CPR14_TARG_VOLT_SVS_SHFT                                       0xb
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_CPR14_TARG_VOLT_NOM_BMSK                                     0x7e0
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_CPR14_TARG_VOLT_NOM_SHFT                                       0x5
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_CPR14_TARG_VOLT_TUR_5_1_BMSK                                  0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_CPR14_TARG_VOLT_TUR_5_1_SHFT                                   0x0

#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002f4)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW12_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW12_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW12_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW12_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW12_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_CPR14_SVS2_QUOT_VMIN_4_0_BMSK                           0xf8000000
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_CPR14_SVS2_QUOT_VMIN_4_0_SHFT                                 0x1b
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_CPR14_SVS_QUOT_VMIN_BMSK                                 0x7ff8000
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_CPR14_SVS_QUOT_VMIN_SHFT                                       0xf
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_CPR14_NOMINAL_QUOT_VMIN_BMSK                                0x7ff8
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_CPR14_NOMINAL_QUOT_VMIN_SHFT                                   0x3
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_CPR14_TURBO_QUOT_VMIN_11_9_BMSK                                0x7
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_CPR14_TURBO_QUOT_VMIN_11_9_SHFT                                0x0

#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002f8)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW13_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW13_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW13_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW13_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW13_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR_LOCAL_RC_BMSK                                       0xe0000000
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR_LOCAL_RC_SHFT                                             0x1d
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR14_QUOT_OFFSET_SVS_BMSK                              0x1fc00000
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR14_QUOT_OFFSET_SVS_SHFT                                    0x16
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR14_QUOT_OFFSET_NOM_BMSK                                0x3f8000
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR14_QUOT_OFFSET_NOM_SHFT                                     0xf
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR14_QUOT_OFFSET_TUR_BMSK                                  0x7f80
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR14_QUOT_OFFSET_TUR_SHFT                                     0x7
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR14_SVS2_QUOT_VMIN_11_5_BMSK                                0x7f
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_CPR14_SVS2_QUOT_VMIN_11_5_SHFT                                 0x0

#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000002fc)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW13_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW13_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW13_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW13_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW13_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_SPARE_R76_B63_BMSK                                      0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_SPARE_R76_B63_SHFT                                            0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_RESERVED_BMSK                                       0x7f000000
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_RESERVED_SHFT                                             0x18
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_LPI_MX_MODE_DISABLE_BMSK                              0xe00000
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_LPI_MX_MODE_DISABLE_SHFT                                  0x15
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_MX_MODE_DISABLE_BMSK                                  0x1c0000
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_MX_MODE_DISABLE_SHFT                                      0x12
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_MM_MODE_DISABLE_BMSK                                   0x38000
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_MM_MODE_DISABLE_SHFT                                       0xf
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_SSC_CX_MODE_DISABLE_BMSK                                0x7000
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_SSC_CX_MODE_DISABLE_SHFT                                   0xc
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_DDR_MODE_DISABLE_BMSK                                    0xe00
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_DDR_MODE_DISABLE_SHFT                                      0x9
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_GFX_MODE_DISABLE_BMSK                                    0x1c0
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_GFX_MODE_DISABLE_SHFT                                      0x6
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_MSS_MODE_DISABLE_BMSK                                     0x38
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_MSS_MODE_DISABLE_SHFT                                      0x3
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_CX_MODE_DISABLE_BMSK                                       0x7
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_CPR_CX_MODE_DISABLE_SHFT                                       0x0

#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000300)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW14_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW14_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW14_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW14_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW14_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_TSENS1_BASE1_1_0_BMSK                                   0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_TSENS1_BASE1_1_0_SHFT                                         0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_TSENS0_BASE1_BMSK                                       0x3ff00000
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_TSENS0_BASE1_SHFT                                             0x14
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_TSENS1_BASE0_BMSK                                          0xffc00
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_TSENS1_BASE0_SHFT                                              0xa
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_TSENS0_BASE0_BMSK                                            0x3ff
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_TSENS0_BASE0_SHFT                                              0x0

#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000304)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW14_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW14_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW14_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW14_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW14_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_TSENS4_OFFSET_3_0_BMSK                                  0xf0000000
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_TSENS4_OFFSET_3_0_SHFT                                        0x1c
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_TSENS3_OFFSET_BMSK                                       0xf800000
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_TSENS3_OFFSET_SHFT                                            0x17
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_TSENS2_OFFSET_BMSK                                        0x7c0000
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_TSENS2_OFFSET_SHFT                                            0x12
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_TSENS1_OFFSET_BMSK                                         0x3e000
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_TSENS1_OFFSET_SHFT                                             0xd
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_TSENS0_OFFSET_BMSK                                          0x1f00
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_TSENS0_OFFSET_SHFT                                             0x8
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_TSENS1_BASE1_9_2_BMSK                                         0xff
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_TSENS1_BASE1_9_2_SHFT                                          0x0

#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000308)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW15_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW15_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW15_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW15_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW15_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_TSENS11_OFFSET_0_BMSK                                   0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_TSENS11_OFFSET_0_SHFT                                         0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_TSENS10_OFFSET_BMSK                                     0x7c000000
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_TSENS10_OFFSET_SHFT                                           0x1a
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_TSENS9_OFFSET_BMSK                                       0x3e00000
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_TSENS9_OFFSET_SHFT                                            0x15
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_TSENS8_OFFSET_BMSK                                        0x1f0000
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_TSENS8_OFFSET_SHFT                                            0x10
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_TSENS7_OFFSET_BMSK                                          0xf800
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_TSENS7_OFFSET_SHFT                                             0xb
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_TSENS6_OFFSET_BMSK                                           0x7c0
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_TSENS6_OFFSET_SHFT                                             0x6
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_TSENS5_OFFSET_BMSK                                            0x3e
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_TSENS5_OFFSET_SHFT                                             0x1
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_TSENS4_OFFSET_4_BMSK                                           0x1
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_TSENS4_OFFSET_4_SHFT                                           0x0

#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000030c)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW15_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW15_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW15_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW15_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW15_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_TSENS17_OFFSET_2_0_BMSK                                 0xe0000000
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_TSENS17_OFFSET_2_0_SHFT                                       0x1d
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_TSENS16_OFFSET_BMSK                                     0x1f000000
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_TSENS16_OFFSET_SHFT                                           0x18
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_TSENS15_OFFSET_BMSK                                       0xf80000
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_TSENS15_OFFSET_SHFT                                           0x13
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_TSENS14_OFFSET_BMSK                                        0x7c000
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_TSENS14_OFFSET_SHFT                                            0xe
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_TSENS13_OFFSET_BMSK                                         0x3e00
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_TSENS13_OFFSET_SHFT                                            0x9
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_TSENS12_OFFSET_BMSK                                          0x1f0
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_TSENS12_OFFSET_SHFT                                            0x4
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_TSENS11_OFFSET_4_1_BMSK                                        0xf
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_TSENS11_OFFSET_4_1_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000310)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW16_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW16_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW16_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW16_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW16_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_TSENS23_OFFSET_BMSK                                     0xf8000000
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_TSENS23_OFFSET_SHFT                                           0x1b
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_TSENS22_OFFSET_BMSK                                      0x7c00000
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_TSENS22_OFFSET_SHFT                                           0x16
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_TSENS21_OFFSET_BMSK                                       0x3e0000
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_TSENS21_OFFSET_SHFT                                           0x11
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_TSENS20_OFFSET_BMSK                                        0x1f000
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_TSENS20_OFFSET_SHFT                                            0xc
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_TSENS19_OFFSET_BMSK                                          0xf80
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_TSENS19_OFFSET_SHFT                                            0x7
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_TSENS18_OFFSET_BMSK                                           0x7c
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_TSENS18_OFFSET_SHFT                                            0x2
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_TSENS17_OFFSET_4_3_BMSK                                        0x3
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_TSENS17_OFFSET_4_3_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000314)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW16_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW16_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW16_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW16_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW16_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B63_BMSK                                      0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B63_SHFT                                            0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B62_BMSK                                      0x40000000
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B62_SHFT                                            0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B61_BMSK                                      0x20000000
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B61_SHFT                                            0x1d
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B60_BMSK                                      0x10000000
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B60_SHFT                                            0x1c
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B59_BMSK                                       0x8000000
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B59_SHFT                                            0x1b
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B58_BMSK                                       0x4000000
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B58_SHFT                                            0x1a
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B57_BMSK                                       0x2000000
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B57_SHFT                                            0x19
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B56_BMSK                                       0x1000000
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B56_SHFT                                            0x18
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B55_BMSK                                        0x800000
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SPARE_R79_B55_SHFT                                            0x17
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_TSENS_CAL_SEL_BMSK                                        0x700000
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_TSENS_CAL_SEL_SHFT                                            0x14
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_TSENS27_OFFSET_BMSK                                        0xf8000
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_TSENS27_OFFSET_SHFT                                            0xf
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_TSENS26_OFFSET_BMSK                                         0x7c00
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_TSENS26_OFFSET_SHFT                                            0xa
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_TSENS25_OFFSET_BMSK                                          0x3e0
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_TSENS25_OFFSET_SHFT                                            0x5
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_TSENS24_OFFSET_BMSK                                           0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_TSENS24_OFFSET_SHFT                                            0x0

#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000318)
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW17_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW17_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW17_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW17_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW17_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW17_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000031c)
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW17_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW17_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW17_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW17_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW17_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW17_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000320)
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW18_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW18_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW18_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW18_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW18_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW18_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000324)
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW18_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW18_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW18_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW18_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW18_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW18_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000328)
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW19_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW19_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW19_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW19_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW19_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW19_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000032c)
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW19_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW19_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW19_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW19_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW19_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW19_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000330)
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW20_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW20_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW20_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW20_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW20_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW20_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000334)
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW20_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW20_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW20_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW20_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW20_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW20_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000338)
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW21_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW21_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW21_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW21_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW21_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW21_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000033c)
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW21_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW21_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW21_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW21_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW21_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW21_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000340)
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW22_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW22_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW22_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW22_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW22_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW22_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000344)
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW22_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW22_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW22_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW22_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW22_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW22_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000348)
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW23_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW23_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW23_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW23_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW23_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW23_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000034c)
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW23_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW23_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW23_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW23_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW23_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW23_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000350)
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW24_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW24_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW24_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW24_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW24_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW24_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000354)
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW24_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW24_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW24_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW24_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW24_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW24_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000358)
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW25_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW25_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW25_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW25_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW25_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW25_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000035c)
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW25_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW25_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW25_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW25_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW25_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW25_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000360)
#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW26_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW26_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW26_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW26_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW26_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW26_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000364)
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW26_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW26_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW26_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW26_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW26_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW26_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000368)
#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW27_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW27_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW27_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW27_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW27_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW27_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000036c)
#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW27_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW27_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW27_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW27_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW27_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW27_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000370)
#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW28_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW28_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW28_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW28_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW28_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW28_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000374)
#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW28_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW28_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW28_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW28_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW28_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW28_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000378)
#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW29_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW29_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW29_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW29_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW29_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW29_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000037c)
#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW29_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW29_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW29_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW29_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW29_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW29_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000380)
#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW30_LSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW30_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW30_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW30_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW30_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW30_LSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000384)
#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_CALIB_ROW30_MSB_ADDR)
#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW30_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW30_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW30_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW30_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_RSVD_BMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW30_MSB_RSVD_SHFT                                                      0x0

#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_ADDR(n)                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000388 + 0x8 * (n))
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_MAXn                                                        70
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_REDUN_DATA_BMSK                                     0xffffffff
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_REDUN_DATA_SHFT                                            0x0

#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_ADDR(n)                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000038c + 0x8 * (n))
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_MAXn                                                        70
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_REDUN_DATA_BMSK                                     0xffffffff
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_REDUN_DATA_SHFT                                            0x0

#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005c0)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_ADDR)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_ADDR,m,v,HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_IN)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_QC_SPARE_BMSK                                        0xffffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_LSB_QC_SPARE_SHFT                                               0x0

#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005c4)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_ADDR)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_ADDR,m,v,HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_IN)
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_RSVD0_BMSK                                           0x80000000
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_RSVD0_SHFT                                                 0x1f
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_FEC_VALUE_BMSK                                       0x7f000000
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_FEC_VALUE_SHFT                                             0x18
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_QC_SPARE_BMSK                                          0xffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REG20_MSB_QC_SPARE_SHFT                                               0x0

#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005c8)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_ADDR)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_ADDR,m,v,HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_IN)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_QC_SPARE_BMSK                                        0xffffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_LSB_QC_SPARE_SHFT                                               0x0

#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005cc)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_ADDR)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_ADDR,m,v,HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_IN)
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_RSVD0_BMSK                                           0x80000000
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_RSVD0_SHFT                                                 0x1f
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_FEC_VALUE_BMSK                                       0x7f000000
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_FEC_VALUE_SHFT                                             0x18
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_QC_SPARE_BMSK                                          0xffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REG21_MSB_QC_SPARE_SHFT                                               0x0

#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n)                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005d0 + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_RMSK                                        0xffffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_MAXn                                                 1
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_KEY_DATA0_BMSK                              0xffffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_KEY_DATA0_SHFT                                     0x0

#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n)                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005d4 + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RMSK                                        0xffffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_MAXn                                                 1
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RSVD1_BMSK                                  0x80000000
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RSVD1_SHFT                                        0x1f
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_FEC_VALUE_BMSK                              0x7f000000
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_FEC_VALUE_SHFT                                    0x18
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_KEY_DATA1_BMSK                                0xffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_KEY_DATA1_SHFT                                     0x0

#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005e0)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RMSK                                        0xffffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RSVD0_BMSK                                  0xffff0000
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RSVD0_SHFT                                        0x10
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_KEY_DATA0_BMSK                                  0xffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_KEY_DATA0_SHFT                                     0x0

#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005e4)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RMSK                                        0xffffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD1_BMSK                                  0x80000000
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD1_SHFT                                        0x1f
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_FEC_VALUE_BMSK                              0x7f000000
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_FEC_VALUE_SHFT                                    0x18
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD0_BMSK                                    0xffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD0_SHFT                                         0x0

#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_ADDR(n)                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005e8 + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_MAXn                                                       1
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT4_BMSK                                    0xff000000
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT4_SHFT                                          0x18
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT3_BMSK                                      0xff0000
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT3_SHFT                                          0x10
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT2_BMSK                                        0xff00
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT2_SHFT                                           0x8
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT1_BMSK                                          0xff
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT1_SHFT                                           0x0

#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_ADDR(n)                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005ec + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_MAXn                                                       1
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_RSVD1_BMSK                                        0x80000000
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_RSVD1_SHFT                                              0x1f
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_FEC_VALUE_BMSK                                    0x7f000000
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_FEC_VALUE_SHFT                                          0x18
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT7_BMSK                                      0xff0000
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT7_SHFT                                          0x10
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT6_BMSK                                        0xff00
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT6_SHFT                                           0x8
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT5_BMSK                                          0xff
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT5_SHFT                                           0x0

#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n)                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005f8 + 0x8 * (n))
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_RMSK                                    0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_MAXn                                             3
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_BMSK                          0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_SHFT                                 0x0

#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n)                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x000005fc + 0x8 * (n))
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RMSK                                    0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_MAXn                                             3
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RSVD1_BMSK                              0x80000000
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RSVD1_SHFT                                    0x1f
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_FEC_VALUE_BMSK                          0x7f000000
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_FEC_VALUE_SHFT                                0x18
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_BMSK                            0xffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_SHFT                                 0x0

#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000618)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_RMSK                                    0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_IN)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_KEY_DATA0_BMSK                          0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_KEY_DATA0_SHFT                                 0x0

#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000061c)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RMSK                                    0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_IN)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD1_BMSK                              0x80000000
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD1_SHFT                                    0x1f
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_FEC_VALUE_BMSK                          0x7f000000
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_FEC_VALUE_SHFT                                0x18
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_BMSK                                0xffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_SHFT                                     0x0

#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_ADDR(n)                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000620 + 0x8 * (n))
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_MAXn                                                         55
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_PATCH_DATA_BMSK                                      0xffffffff
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_PATCH_DATA_SHFT                                             0x0

#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_ADDR(n)                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000624 + 0x8 * (n))
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_MAXn                                                         55
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RSVD1_BMSK                                           0x80000000
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RSVD1_SHFT                                                 0x1f
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_FEC_VALUE_BMSK                                       0x7f000000
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_FEC_VALUE_SHFT                                             0x18
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RSVD0_BMSK                                             0xfe0000
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RSVD0_SHFT                                                 0x11
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_PATCH_ADDR_BMSK                                         0x1fffe
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_PATCH_ADDR_SHFT                                             0x1
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_PATCH_EN_BMSK                                               0x1
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_PATCH_EN_SHFT                                               0x0

#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000007e0 + 0x8 * (n))
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_MAXn                                                    1
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_KEY_DATA0_BMSK                                 0xffffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_KEY_DATA0_SHFT                                        0x0

#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000007e4 + 0x8 * (n))
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_MAXn                                                    1
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_RSVD1_BMSK                                     0x80000000
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_RSVD1_SHFT                                           0x1f
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_FEC_VALUE_BMSK                                 0x7f000000
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_FEC_VALUE_SHFT                                       0x18
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_KEY_DATA1_BMSK                                   0xffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_KEY_DATA1_SHFT                                        0x0

#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x000007f0)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_RSVD0_BMSK                                     0xffff0000
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_RSVD0_SHFT                                           0x10
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_KEY_DATA0_BMSK                                     0xffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_KEY_DATA0_SHFT                                        0x0

#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x000007f4)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD1_BMSK                                     0x80000000
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD1_SHFT                                           0x1f
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_FEC_VALUE_BMSK                                 0x7f000000
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_FEC_VALUE_SHFT                                       0x18
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD0_BMSK                                       0xffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD0_SHFT                                            0x0

#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_ADDR(n)                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x000007f8 + 0x8 * (n))
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_MAXn                                                      3
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_USER_DATA_KEY_BMSK                               0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_USER_DATA_KEY_SHFT                                      0x0

#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_ADDR(n)                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x000007fc + 0x8 * (n))
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_MAXn                                                      3
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_RSVD1_BMSK                                       0x80000000
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_RSVD1_SHFT                                             0x1f
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_FEC_VALUE_BMSK                                   0x7f000000
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_FEC_VALUE_SHFT                                         0x18
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_USER_DATA_KEY_BMSK                                 0xffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_USER_DATA_KEY_SHFT                                      0x0

#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000818)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_ADDR)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_IN)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_USER_DATA_KEY_BMSK                               0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_USER_DATA_KEY_SHFT                                      0x0

#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000081c)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_ADDR)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_IN)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_RSVD1_BMSK                                       0x80000000
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_RSVD1_SHFT                                             0x1f
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_FEC_VALUE_BMSK                                   0x7f000000
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_FEC_VALUE_SHFT                                         0x18
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_RSVD0_BMSK                                         0xffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_RSVD0_SHFT                                              0x0

#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_ADDR(n)                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000660 + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_MAXn                                                    31
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_OEM_SPARE_BMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_OEM_SPARE_SHFT                                         0x0

#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_ADDR(n)                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000664 + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_MAXn                                                    31
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_OEM_SPARE_BMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_OEM_SPARE_SHFT                                         0x0

#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_ADDR(n)                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000668 + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_MAXn                                                    31
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_OEM_SPARE_BMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_OEM_SPARE_SHFT                                         0x0

#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_ADDR(n)                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000066c + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_MAXn                                                    31
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_OEM_SPARE_BMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_OEM_SPARE_SHFT                                         0x0

#define HWIO_QFPROM_BLOW_TIMER_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000203c)
#define HWIO_QFPROM_BLOW_TIMER_RMSK                                                                  0xfff
#define HWIO_QFPROM_BLOW_TIMER_IN          \
        in_dword(HWIO_QFPROM_BLOW_TIMER_ADDR)
#define HWIO_QFPROM_BLOW_TIMER_INM(m)      \
        in_dword_masked(HWIO_QFPROM_BLOW_TIMER_ADDR, m)
#define HWIO_QFPROM_BLOW_TIMER_OUT(v)      \
        out_dword(HWIO_QFPROM_BLOW_TIMER_ADDR,v)
#define HWIO_QFPROM_BLOW_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_BLOW_TIMER_ADDR,m,v,HWIO_QFPROM_BLOW_TIMER_IN)
#define HWIO_QFPROM_BLOW_TIMER_BLOW_TIMER_BMSK                                                       0xfff
#define HWIO_QFPROM_BLOW_TIMER_BLOW_TIMER_SHFT                                                         0x0

#define HWIO_QFPROM_TEST_CTRL_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002040)
#define HWIO_QFPROM_TEST_CTRL_RMSK                                                                     0xf
#define HWIO_QFPROM_TEST_CTRL_IN          \
        in_dword(HWIO_QFPROM_TEST_CTRL_ADDR)
#define HWIO_QFPROM_TEST_CTRL_INM(m)      \
        in_dword_masked(HWIO_QFPROM_TEST_CTRL_ADDR, m)
#define HWIO_QFPROM_TEST_CTRL_OUT(v)      \
        out_dword(HWIO_QFPROM_TEST_CTRL_ADDR,v)
#define HWIO_QFPROM_TEST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_TEST_CTRL_ADDR,m,v,HWIO_QFPROM_TEST_CTRL_IN)
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_ROM_BMSK                                                         0x8
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_ROM_SHFT                                                         0x3
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_WL_BMSK                                                          0x4
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_WL_SHFT                                                          0x2
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_BL_BMSK                                                          0x2
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_BL_SHFT                                                          0x1
#define HWIO_QFPROM_TEST_CTRL_EN_FUSE_RES_MEAS_BMSK                                                    0x1
#define HWIO_QFPROM_TEST_CTRL_EN_FUSE_RES_MEAS_SHFT                                                    0x0

#define HWIO_QFPROM_ACCEL_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002044)
#define HWIO_QFPROM_ACCEL_RMSK                                                                       0xfff
#define HWIO_QFPROM_ACCEL_IN          \
        in_dword(HWIO_QFPROM_ACCEL_ADDR)
#define HWIO_QFPROM_ACCEL_INM(m)      \
        in_dword_masked(HWIO_QFPROM_ACCEL_ADDR, m)
#define HWIO_QFPROM_ACCEL_OUT(v)      \
        out_dword(HWIO_QFPROM_ACCEL_ADDR,v)
#define HWIO_QFPROM_ACCEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_ACCEL_ADDR,m,v,HWIO_QFPROM_ACCEL_IN)
#define HWIO_QFPROM_ACCEL_QFPROM_GATELAST_BMSK                                                       0x800
#define HWIO_QFPROM_ACCEL_QFPROM_GATELAST_SHFT                                                         0xb
#define HWIO_QFPROM_ACCEL_QFPROM_TRIPPT_SEL_BMSK                                                     0x700
#define HWIO_QFPROM_ACCEL_QFPROM_TRIPPT_SEL_SHFT                                                       0x8
#define HWIO_QFPROM_ACCEL_QFPROM_ACCEL_BMSK                                                           0xff
#define HWIO_QFPROM_ACCEL_QFPROM_ACCEL_SHFT                                                            0x0

#define HWIO_QFPROM_BLOW_STATUS_ADDR                                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002048)
#define HWIO_QFPROM_BLOW_STATUS_RMSK                                                                   0x3
#define HWIO_QFPROM_BLOW_STATUS_IN          \
        in_dword(HWIO_QFPROM_BLOW_STATUS_ADDR)
#define HWIO_QFPROM_BLOW_STATUS_INM(m)      \
        in_dword_masked(HWIO_QFPROM_BLOW_STATUS_ADDR, m)
#define HWIO_QFPROM_BLOW_STATUS_QFPROM_WR_ERR_BMSK                                                     0x2
#define HWIO_QFPROM_BLOW_STATUS_QFPROM_WR_ERR_SHFT                                                     0x1
#define HWIO_QFPROM_BLOW_STATUS_QFPROM_BUSY_BMSK                                                       0x1
#define HWIO_QFPROM_BLOW_STATUS_QFPROM_BUSY_SHFT                                                       0x0

#define HWIO_QFPROM_ROM_ERROR_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000204c)
#define HWIO_QFPROM_ROM_ERROR_RMSK                                                                     0x1
#define HWIO_QFPROM_ROM_ERROR_IN          \
        in_dword(HWIO_QFPROM_ROM_ERROR_ADDR)
#define HWIO_QFPROM_ROM_ERROR_INM(m)      \
        in_dword_masked(HWIO_QFPROM_ROM_ERROR_ADDR, m)
#define HWIO_QFPROM_ROM_ERROR_ERROR_BMSK                                                               0x1
#define HWIO_QFPROM_ROM_ERROR_ERROR_SHFT                                                               0x0

#define HWIO_QFPROM0_MATCH_STATUS_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002050)
#define HWIO_QFPROM0_MATCH_STATUS_RMSK                                                          0xffffffff
#define HWIO_QFPROM0_MATCH_STATUS_IN          \
        in_dword(HWIO_QFPROM0_MATCH_STATUS_ADDR)
#define HWIO_QFPROM0_MATCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_QFPROM0_MATCH_STATUS_ADDR, m)
#define HWIO_QFPROM0_MATCH_STATUS_FLAG_BMSK                                                     0xffffffff
#define HWIO_QFPROM0_MATCH_STATUS_FLAG_SHFT                                                            0x0

#define HWIO_QFPROM1_MATCH_STATUS_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002054)
#define HWIO_QFPROM1_MATCH_STATUS_RMSK                                                          0xffffffff
#define HWIO_QFPROM1_MATCH_STATUS_IN          \
        in_dword(HWIO_QFPROM1_MATCH_STATUS_ADDR)
#define HWIO_QFPROM1_MATCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_QFPROM1_MATCH_STATUS_ADDR, m)
#define HWIO_QFPROM1_MATCH_STATUS_FLAG_BMSK                                                     0xffffffff
#define HWIO_QFPROM1_MATCH_STATUS_FLAG_SHFT                                                            0x0

#define HWIO_FEC_ESR_ADDR                                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002058)
#define HWIO_FEC_ESR_RMSK                                                                           0x2fdf
#define HWIO_FEC_ESR_IN          \
        in_dword(HWIO_FEC_ESR_ADDR)
#define HWIO_FEC_ESR_INM(m)      \
        in_dword_masked(HWIO_FEC_ESR_ADDR, m)
#define HWIO_FEC_ESR_OUT(v)      \
        out_dword(HWIO_FEC_ESR_ADDR,v)
#define HWIO_FEC_ESR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_FEC_ESR_ADDR,m,v,HWIO_FEC_ESR_IN)
#define HWIO_FEC_ESR_CORR_SW_ACC_BMSK                                                               0x2000
#define HWIO_FEC_ESR_CORR_SW_ACC_SHFT                                                                  0xd
#define HWIO_FEC_ESR_CORR_SECURE_CHANNEL_BMSK                                                        0x800
#define HWIO_FEC_ESR_CORR_SECURE_CHANNEL_SHFT                                                          0xb
#define HWIO_FEC_ESR_CORR_BOOT_ROM_BMSK                                                              0x400
#define HWIO_FEC_ESR_CORR_BOOT_ROM_SHFT                                                                0xa
#define HWIO_FEC_ESR_CORR_FUSE_SENSE_BMSK                                                            0x200
#define HWIO_FEC_ESR_CORR_FUSE_SENSE_SHFT                                                              0x9
#define HWIO_FEC_ESR_CORR_MULT_BMSK                                                                  0x100
#define HWIO_FEC_ESR_CORR_MULT_SHFT                                                                    0x8
#define HWIO_FEC_ESR_CORR_SEEN_BMSK                                                                   0x80
#define HWIO_FEC_ESR_CORR_SEEN_SHFT                                                                    0x7
#define HWIO_FEC_ESR_ERR_SW_ACC_BMSK                                                                  0x40
#define HWIO_FEC_ESR_ERR_SW_ACC_SHFT                                                                   0x6
#define HWIO_FEC_ESR_ERR_SECURE_CHANNEL_BMSK                                                          0x10
#define HWIO_FEC_ESR_ERR_SECURE_CHANNEL_SHFT                                                           0x4
#define HWIO_FEC_ESR_ERR_BOOT_ROM_BMSK                                                                 0x8
#define HWIO_FEC_ESR_ERR_BOOT_ROM_SHFT                                                                 0x3
#define HWIO_FEC_ESR_ERR_FUSE_SENSE_BMSK                                                               0x4
#define HWIO_FEC_ESR_ERR_FUSE_SENSE_SHFT                                                               0x2
#define HWIO_FEC_ESR_ERR_MULT_BMSK                                                                     0x2
#define HWIO_FEC_ESR_ERR_MULT_SHFT                                                                     0x1
#define HWIO_FEC_ESR_ERR_SEEN_BMSK                                                                     0x1
#define HWIO_FEC_ESR_ERR_SEEN_SHFT                                                                     0x0

#define HWIO_FEC_EAR_ADDR                                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000205c)
#define HWIO_FEC_EAR_RMSK                                                                       0xffffffff
#define HWIO_FEC_EAR_IN          \
        in_dword(HWIO_FEC_EAR_ADDR)
#define HWIO_FEC_EAR_INM(m)      \
        in_dword_masked(HWIO_FEC_EAR_ADDR, m)
#define HWIO_FEC_EAR_CORR_ADDR_BMSK                                                             0xffff0000
#define HWIO_FEC_EAR_CORR_ADDR_SHFT                                                                   0x10
#define HWIO_FEC_EAR_ERR_ADDR_BMSK                                                                  0xffff
#define HWIO_FEC_EAR_ERR_ADDR_SHFT                                                                     0x0

#define HWIO_QFPROM_BIST_CTRL_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002060)
#define HWIO_QFPROM_BIST_CTRL_RMSK                                                                    0xff
#define HWIO_QFPROM_BIST_CTRL_IN          \
        in_dword(HWIO_QFPROM_BIST_CTRL_ADDR)
#define HWIO_QFPROM_BIST_CTRL_INM(m)      \
        in_dword_masked(HWIO_QFPROM_BIST_CTRL_ADDR, m)
#define HWIO_QFPROM_BIST_CTRL_OUT(v)      \
        out_dword(HWIO_QFPROM_BIST_CTRL_ADDR,v)
#define HWIO_QFPROM_BIST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_BIST_CTRL_ADDR,m,v,HWIO_QFPROM_BIST_CTRL_IN)
#define HWIO_QFPROM_BIST_CTRL_AUTH_REGION_BMSK                                                        0xfc
#define HWIO_QFPROM_BIST_CTRL_AUTH_REGION_SHFT                                                         0x2
#define HWIO_QFPROM_BIST_CTRL_SHA_ENABLE_BMSK                                                          0x2
#define HWIO_QFPROM_BIST_CTRL_SHA_ENABLE_SHFT                                                          0x1
#define HWIO_QFPROM_BIST_CTRL_START_BMSK                                                               0x1
#define HWIO_QFPROM_BIST_CTRL_START_SHFT                                                               0x0

#define HWIO_QFPROM_BIST_ERROR0_ADDR                                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002064)
#define HWIO_QFPROM_BIST_ERROR0_RMSK                                                            0xffffffff
#define HWIO_QFPROM_BIST_ERROR0_IN          \
        in_dword(HWIO_QFPROM_BIST_ERROR0_ADDR)
#define HWIO_QFPROM_BIST_ERROR0_INM(m)      \
        in_dword_masked(HWIO_QFPROM_BIST_ERROR0_ADDR, m)
#define HWIO_QFPROM_BIST_ERROR0_ERROR_BMSK                                                      0xffffffff
#define HWIO_QFPROM_BIST_ERROR0_ERROR_SHFT                                                             0x0

#define HWIO_QFPROM_BIST_ERROR1_ADDR                                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002068)
#define HWIO_QFPROM_BIST_ERROR1_RMSK                                                            0xffffffff
#define HWIO_QFPROM_BIST_ERROR1_IN          \
        in_dword(HWIO_QFPROM_BIST_ERROR1_ADDR)
#define HWIO_QFPROM_BIST_ERROR1_INM(m)      \
        in_dword_masked(HWIO_QFPROM_BIST_ERROR1_ADDR, m)
#define HWIO_QFPROM_BIST_ERROR1_ERROR_BMSK                                                      0xffffffff
#define HWIO_QFPROM_BIST_ERROR1_ERROR_SHFT                                                             0x0

#define HWIO_QFPROM_HASH_SIGNATUREn_ADDR(n)                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000206c + 0x4 * (n))
#define HWIO_QFPROM_HASH_SIGNATUREn_RMSK                                                        0xffffffff
#define HWIO_QFPROM_HASH_SIGNATUREn_MAXn                                                                 7
#define HWIO_QFPROM_HASH_SIGNATUREn_INI(n)        \
        in_dword_masked(HWIO_QFPROM_HASH_SIGNATUREn_ADDR(n), HWIO_QFPROM_HASH_SIGNATUREn_RMSK)
#define HWIO_QFPROM_HASH_SIGNATUREn_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_HASH_SIGNATUREn_ADDR(n), mask)
#define HWIO_QFPROM_HASH_SIGNATUREn_HASH_VALUE_BMSK                                             0xffffffff
#define HWIO_QFPROM_HASH_SIGNATUREn_HASH_VALUE_SHFT                                                    0x0

#define HWIO_HW_KEY_STATUS_ADDR                                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000208c)
#define HWIO_HW_KEY_STATUS_RMSK                                                                      0x7ff
#define HWIO_HW_KEY_STATUS_IN          \
        in_dword(HWIO_HW_KEY_STATUS_ADDR)
#define HWIO_HW_KEY_STATUS_INM(m)      \
        in_dword_masked(HWIO_HW_KEY_STATUS_ADDR, m)
#define HWIO_HW_KEY_STATUS_MSA_SECURE_BMSK                                                           0x400
#define HWIO_HW_KEY_STATUS_MSA_SECURE_SHFT                                                             0xa
#define HWIO_HW_KEY_STATUS_APPS_SECURE_BMSK                                                          0x200
#define HWIO_HW_KEY_STATUS_APPS_SECURE_SHFT                                                            0x9
#define HWIO_HW_KEY_STATUS_KDF_AND_HW_KEY_SHIFT_DONE_BMSK                                            0x100
#define HWIO_HW_KEY_STATUS_KDF_AND_HW_KEY_SHIFT_DONE_SHFT                                              0x8
#define HWIO_HW_KEY_STATUS_HW_KEY_SHIFT_DONE_BMSK                                                     0x80
#define HWIO_HW_KEY_STATUS_HW_KEY_SHIFT_DONE_SHFT                                                      0x7
#define HWIO_HW_KEY_STATUS_FUSE_SENSE_DONE_BMSK                                                       0x40
#define HWIO_HW_KEY_STATUS_FUSE_SENSE_DONE_SHFT                                                        0x6
#define HWIO_HW_KEY_STATUS_CRI_CM_BOOT_DONE_BMSK                                                      0x20
#define HWIO_HW_KEY_STATUS_CRI_CM_BOOT_DONE_SHFT                                                       0x5
#define HWIO_HW_KEY_STATUS_KDF_DONE_BMSK                                                              0x10
#define HWIO_HW_KEY_STATUS_KDF_DONE_SHFT                                                               0x4
#define HWIO_HW_KEY_STATUS_MSA_KEYS_BLOCKED_BMSK                                                       0x8
#define HWIO_HW_KEY_STATUS_MSA_KEYS_BLOCKED_SHFT                                                       0x3
#define HWIO_HW_KEY_STATUS_APPS_KEYS_BLOCKED_BMSK                                                      0x4
#define HWIO_HW_KEY_STATUS_APPS_KEYS_BLOCKED_SHFT                                                      0x2
#define HWIO_HW_KEY_STATUS_SEC_KEY_DERIVATION_KEY_BLOWN_BMSK                                           0x2
#define HWIO_HW_KEY_STATUS_SEC_KEY_DERIVATION_KEY_BLOWN_SHFT                                           0x1
#define HWIO_HW_KEY_STATUS_PRI_KEY_DERIVATION_KEY_BLOWN_BMSK                                           0x1
#define HWIO_HW_KEY_STATUS_PRI_KEY_DERIVATION_KEY_BLOWN_SHFT                                           0x0

#define HWIO_RESET_JDR_STATUS_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002090)
#define HWIO_RESET_JDR_STATUS_RMSK                                                                     0x3
#define HWIO_RESET_JDR_STATUS_IN          \
        in_dword(HWIO_RESET_JDR_STATUS_ADDR)
#define HWIO_RESET_JDR_STATUS_INM(m)      \
        in_dword_masked(HWIO_RESET_JDR_STATUS_ADDR, m)
#define HWIO_RESET_JDR_STATUS_FORCE_RESET_BMSK                                                         0x2
#define HWIO_RESET_JDR_STATUS_FORCE_RESET_SHFT                                                         0x1
#define HWIO_RESET_JDR_STATUS_DISABLE_SYSTEM_RESET_BMSK                                                0x1
#define HWIO_RESET_JDR_STATUS_DISABLE_SYSTEM_RESET_SHFT                                                0x0

#define HWIO_ATPG_JDR_STATUS_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002094)
#define HWIO_ATPG_JDR_STATUS_RMSK                                                                      0x1
#define HWIO_ATPG_JDR_STATUS_IN          \
        in_dword(HWIO_ATPG_JDR_STATUS_ADDR)
#define HWIO_ATPG_JDR_STATUS_INM(m)      \
        in_dword_masked(HWIO_ATPG_JDR_STATUS_ADDR, m)
#define HWIO_ATPG_JDR_STATUS_FUSE_SENSE_ATPG_CTL_BMSK                                                  0x1
#define HWIO_ATPG_JDR_STATUS_FUSE_SENSE_ATPG_CTL_SHFT                                                  0x0

#define HWIO_FEAT_PROV_OUTn_ADDR(n)                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002098 + 0x4 * (n))
#define HWIO_FEAT_PROV_OUTn_RMSK                                                                0xffffffff
#define HWIO_FEAT_PROV_OUTn_MAXn                                                                         3
#define HWIO_FEAT_PROV_OUTn_INI(n)        \
        in_dword_masked(HWIO_FEAT_PROV_OUTn_ADDR(n), HWIO_FEAT_PROV_OUTn_RMSK)
#define HWIO_FEAT_PROV_OUTn_INMI(n,mask)    \
        in_dword_masked(HWIO_FEAT_PROV_OUTn_ADDR(n), mask)
#define HWIO_FEAT_PROV_OUTn_FEAT_PROV_OUT_VALUE_BMSK                                            0xffffffff
#define HWIO_FEAT_PROV_OUTn_FEAT_PROV_OUT_VALUE_SHFT                                                   0x0

#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_ADDR(n)                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000020a8 + 0x4 * (n))
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_RMSK                                                  0xffffffff
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_MAXn                                                           3
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_INI(n)        \
        in_dword_masked(HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_ADDR(n), HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_RMSK)
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_INMI(n,mask)    \
        in_dword_masked(HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_ADDR(n), mask)
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_SEC_CTRL_MISC_CONFIG_STATUS_VALUE_BMSK                0xffffffff
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_SEC_CTRL_MISC_CONFIG_STATUS_VALUE_SHFT                       0x0

#define HWIO_DEBUG_FUSE_STATUS_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000020f0)
#define HWIO_DEBUG_FUSE_STATUS_RMSK                                                             0xffffffff
#define HWIO_DEBUG_FUSE_STATUS_IN          \
        in_dword(HWIO_DEBUG_FUSE_STATUS_ADDR)
#define HWIO_DEBUG_FUSE_STATUS_INM(m)      \
        in_dword_masked(HWIO_DEBUG_FUSE_STATUS_ADDR, m)
#define HWIO_DEBUG_FUSE_STATUS_RSVD0_BMSK                                                       0xff000000
#define HWIO_DEBUG_FUSE_STATUS_RSVD0_SHFT                                                             0x18
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC5_DEBUG_BMSK                                            0x800000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC5_DEBUG_SHFT                                                0x17
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC4_DEBUG_BMSK                                            0x400000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC4_DEBUG_SHFT                                                0x16
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC3_DEBUG_BMSK                                            0x200000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC3_DEBUG_SHFT                                                0x15
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC2_DEBUG_BMSK                                            0x100000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC2_DEBUG_SHFT                                                0x14
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC1_DEBUG_BMSK                                             0x80000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC1_DEBUG_SHFT                                                0x13
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC_DEBUG_BMSK                                              0x40000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC_DEBUG_SHFT                                                 0x12
#define HWIO_DEBUG_FUSE_STATUS_APPS_NIDEN_BMSK                                                     0x20000
#define HWIO_DEBUG_FUSE_STATUS_APPS_NIDEN_SHFT                                                        0x11
#define HWIO_DEBUG_FUSE_STATUS_APPS_DBGEN_BMSK                                                     0x10000
#define HWIO_DEBUG_FUSE_STATUS_APPS_DBGEN_SHFT                                                        0x10
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_QSEE_SPNIDEN_BMSK                                            0x8000
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_QSEE_SPNIDEN_SHFT                                               0xf
#define HWIO_DEBUG_FUSE_STATUS_SHARED_QSEE_SPNIDEN_BMSK                                             0x4000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_QSEE_SPNIDEN_SHFT                                                0xe
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_MSS_NIDEN_BMSK                                               0x2000
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_MSS_NIDEN_SHFT                                                  0xd
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MSS_NIDEN_BMSK                                                0x1000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MSS_NIDEN_SHFT                                                   0xc
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_CP_NIDEN_BMSK                                                 0x800
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_CP_NIDEN_SHFT                                                   0xb
#define HWIO_DEBUG_FUSE_STATUS_SHARED_CP_NIDEN_BMSK                                                  0x400
#define HWIO_DEBUG_FUSE_STATUS_SHARED_CP_NIDEN_SHFT                                                    0xa
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_NS_NIDEN_BMSK                                                 0x200
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_NS_NIDEN_SHFT                                                   0x9
#define HWIO_DEBUG_FUSE_STATUS_SHARED_NS_NIDEN_BMSK                                                  0x100
#define HWIO_DEBUG_FUSE_STATUS_SHARED_NS_NIDEN_SHFT                                                    0x8
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_QSEE_SPIDEN_BMSK                                               0x80
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_QSEE_SPIDEN_SHFT                                                0x7
#define HWIO_DEBUG_FUSE_STATUS_SHARED_QSEE_SPIDEN_BMSK                                                0x40
#define HWIO_DEBUG_FUSE_STATUS_SHARED_QSEE_SPIDEN_SHFT                                                 0x6
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_MSS_DBGEN_BMSK                                                 0x20
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_MSS_DBGEN_SHFT                                                  0x5
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MSS_DBGEN_BMSK                                                  0x10
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MSS_DBGEN_SHFT                                                   0x4
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_CP_DBGEN_BMSK                                                   0x8
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_CP_DBGEN_SHFT                                                   0x3
#define HWIO_DEBUG_FUSE_STATUS_SHARED_CP_DBGEN_BMSK                                                    0x4
#define HWIO_DEBUG_FUSE_STATUS_SHARED_CP_DBGEN_SHFT                                                    0x2
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_NS_DBGEN_BMSK                                                   0x2
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_NS_DBGEN_SHFT                                                   0x1
#define HWIO_DEBUG_FUSE_STATUS_SHARED_NS_DBGEN_BMSK                                                    0x1
#define HWIO_DEBUG_FUSE_STATUS_SHARED_NS_DBGEN_SHFT                                                    0x0

#define HWIO_HW_ATTESTATION_CTRL0_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002100)
#define HWIO_HW_ATTESTATION_CTRL0_RMSK                                                          0x1fffffff
#define HWIO_HW_ATTESTATION_CTRL0_IN          \
        in_dword(HWIO_HW_ATTESTATION_CTRL0_ADDR)
#define HWIO_HW_ATTESTATION_CTRL0_INM(m)      \
        in_dword_masked(HWIO_HW_ATTESTATION_CTRL0_ADDR, m)
#define HWIO_HW_ATTESTATION_CTRL0_OUT(v)      \
        out_dword(HWIO_HW_ATTESTATION_CTRL0_ADDR,v)
#define HWIO_HW_ATTESTATION_CTRL0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_HW_ATTESTATION_CTRL0_ADDR,m,v,HWIO_HW_ATTESTATION_CTRL0_IN)
#define HWIO_HW_ATTESTATION_CTRL0_REGION_BMSK                                                   0x1f800000
#define HWIO_HW_ATTESTATION_CTRL0_REGION_SHFT                                                         0x17
#define HWIO_HW_ATTESTATION_CTRL0_CONTEXT_STRING_BMSK                                             0x7fff80
#define HWIO_HW_ATTESTATION_CTRL0_CONTEXT_STRING_SHFT                                                  0x7
#define HWIO_HW_ATTESTATION_CTRL0_KEY_SELECT_BMSK                                                     0x78
#define HWIO_HW_ATTESTATION_CTRL0_KEY_SELECT_SHFT                                                      0x3
#define HWIO_HW_ATTESTATION_CTRL0_OPERATION_BMSK                                                       0x7
#define HWIO_HW_ATTESTATION_CTRL0_OPERATION_SHFT                                                       0x0

#define HWIO_HW_ATTESTATION_CTRL1_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002104)
#define HWIO_HW_ATTESTATION_CTRL1_RMSK                                                          0xffffffff
#define HWIO_HW_ATTESTATION_CTRL1_IN          \
        in_dword(HWIO_HW_ATTESTATION_CTRL1_ADDR)
#define HWIO_HW_ATTESTATION_CTRL1_INM(m)      \
        in_dword_masked(HWIO_HW_ATTESTATION_CTRL1_ADDR, m)
#define HWIO_HW_ATTESTATION_CTRL1_OUT(v)      \
        out_dword(HWIO_HW_ATTESTATION_CTRL1_ADDR,v)
#define HWIO_HW_ATTESTATION_CTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_HW_ATTESTATION_CTRL1_ADDR,m,v,HWIO_HW_ATTESTATION_CTRL1_IN)
#define HWIO_HW_ATTESTATION_CTRL1_NONCE_BMSK                                                    0xffffffff
#define HWIO_HW_ATTESTATION_CTRL1_NONCE_SHFT                                                           0x0

#define HWIO_HW_ATTESTATION_CMD_ADDR                                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002108)
#define HWIO_HW_ATTESTATION_CMD_RMSK                                                                   0x1
#define HWIO_HW_ATTESTATION_CMD_OUT(v)      \
        out_dword(HWIO_HW_ATTESTATION_CMD_ADDR,v)
#define HWIO_HW_ATTESTATION_CMD_OPERATION_COMMAND_BMSK                                                 0x1
#define HWIO_HW_ATTESTATION_CMD_OPERATION_COMMAND_SHFT                                                 0x0

#define HWIO_HW_ATTESTATION_STATUS_ADDR                                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000210c)
#define HWIO_HW_ATTESTATION_STATUS_RMSK                                                         0xffffffff
#define HWIO_HW_ATTESTATION_STATUS_IN          \
        in_dword(HWIO_HW_ATTESTATION_STATUS_ADDR)
#define HWIO_HW_ATTESTATION_STATUS_INM(m)      \
        in_dword_masked(HWIO_HW_ATTESTATION_STATUS_ADDR, m)
#define HWIO_HW_ATTESTATION_STATUS_STATUS_BMSK                                                  0xffffffff
#define HWIO_HW_ATTESTATION_STATUS_STATUS_SHFT                                                         0x0

#define HWIO_HW_ATTESTATION_ERROR_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002110)
#define HWIO_HW_ATTESTATION_ERROR_RMSK                                                          0xffffffff
#define HWIO_HW_ATTESTATION_ERROR_IN          \
        in_dword(HWIO_HW_ATTESTATION_ERROR_ADDR)
#define HWIO_HW_ATTESTATION_ERROR_INM(m)      \
        in_dword_masked(HWIO_HW_ATTESTATION_ERROR_ADDR, m)
#define HWIO_HW_ATTESTATION_ERROR_ERROR_BMSK                                                    0xffffffff
#define HWIO_HW_ATTESTATION_ERROR_ERROR_SHFT                                                           0x0

#define HWIO_HW_ATTESTATION_RESULTn_ADDR(n)                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002120 + 0x4 * (n))
#define HWIO_HW_ATTESTATION_RESULTn_RMSK                                                        0xffffffff
#define HWIO_HW_ATTESTATION_RESULTn_MAXn                                                                 7
#define HWIO_HW_ATTESTATION_RESULTn_INI(n)        \
        in_dword_masked(HWIO_HW_ATTESTATION_RESULTn_ADDR(n), HWIO_HW_ATTESTATION_RESULTn_RMSK)
#define HWIO_HW_ATTESTATION_RESULTn_INMI(n,mask)    \
        in_dword_masked(HWIO_HW_ATTESTATION_RESULTn_ADDR(n), mask)
#define HWIO_HW_ATTESTATION_RESULTn_RESULT_BMSK                                                 0xffffffff
#define HWIO_HW_ATTESTATION_RESULTn_RESULT_SHFT                                                        0x0

#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_ADDR(n)                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004000 + 0x4 * (n))
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_MAXn                                                           71
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_ADDR(n), HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_RMSK)
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_ADDR(n), mask)
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_CRI_CM_PRIVATE_BMSK                                    0xffffffff
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_CRI_CM_PRIVATE_SHFT                                           0x0

#define HWIO_QFPROM_CORR_LCM_ROW_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004120)
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_LCM_ROW_LSB_ADDR)
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_LCM_ROW_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_DISABLE_LCM_BMSK                                           0x80000000
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_DISABLE_LCM_SHFT                                                 0x1f
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_DISABLE_LCM_STATE_TRANSITION_BMSK                          0x40000000
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_DISABLE_LCM_STATE_TRANSITION_SHFT                                0x1e
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_DISABLE_SECURE_PHK_BMSK                                    0x20000000
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_DISABLE_SECURE_PHK_SHFT                                          0x1d
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_RSVD_BMSK                                                  0x1fffffe0
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_RSVD_SHFT                                                         0x5
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_QC_EXTERNAL_BMSK                                                 0x10
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_QC_EXTERNAL_SHFT                                                  0x4
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_QC_INTERNAL_BMSK                                                  0x8
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_QC_INTERNAL_SHFT                                                  0x3
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_QC_FEAT_CONFIG_BMSK                                               0x4
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_QC_FEAT_CONFIG_SHFT                                               0x2
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_HW_TEST_BMSK                                                      0x2
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_HW_TEST_SHFT                                                      0x1
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_SOC_PERSO_BMSK                                                    0x1
#define HWIO_QFPROM_CORR_LCM_ROW_LSB_SOC_PERSO_SHFT                                                    0x0

#define HWIO_QFPROM_CORR_LCM_ROW_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004124)
#define HWIO_QFPROM_CORR_LCM_ROW_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_CORR_LCM_ROW_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_LCM_ROW_MSB_ADDR)
#define HWIO_QFPROM_CORR_LCM_ROW_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_LCM_ROW_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_LCM_ROW_MSB_RSVD_BMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_LCM_ROW_MSB_RSVD_SHFT                                                         0x0

#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_ADDR(n)                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004128 + 0x8 * (n))
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_MAXn                                                   1
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_RSVD_BMSK                                     0xffffffff
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_LSB_RSVD_SHFT                                            0x0

#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_ADDR(n)                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000412c + 0x8 * (n))
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_MAXn                                                   1
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_RSVD_BMSK                                     0xffffffff
#define HWIO_QFPROM_CORR_BOOT_PATCH_HASH_ROWn_MSB_RSVD_SHFT                                            0x0

#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n)                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004138 + 0x8 * (n))
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_RMSK                                   0xffffffff
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_MAXn                                            3
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_BMSK                         0xffffffff
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_SHFT                                0x0

#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n)                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000413c + 0x8 * (n))
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RMSK                                     0xffffff
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_MAXn                                            3
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_BMSK                           0xffffff
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_SHFT                                0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004158)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_RMSK                                           0x7fffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_BMSK                   0x40000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_SHFT                         0x1e
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_BMSK                             0x20000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_SHFT                                   0x1d
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_BMSK                      0x1fe00000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_SHFT                            0x15
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_BMSK                       0x180000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_SHFT                           0x13
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_BMSK                     0x40000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_SHFT                        0x12
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_BMSK                     0x20000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_SHFT                        0x11
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_BMSK                              0x10000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_SHFT                                 0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_BMSK                              0x8000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_SHFT                                 0xf
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_BMSK                              0x4000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_SHFT                                 0xe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_BMSK                                    0x2000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_SHFT                                       0xd
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_BMSK                                  0x1000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_SHFT                                     0xc
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_BMSK                         0x800
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_SHFT                           0xb
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK                 0x400
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT                   0xa
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_BMSK                                  0x200
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_SHFT                                    0x9
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_BMSK                                  0x100
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_SHFT                                    0x8
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_BMSK                                      0x80
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_SHFT                                       0x7
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_BMSK                            0x40
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_SHFT                             0x6
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EFUSE_CAM_SBI_ENABLE_IF_BMSK                         0x20
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EFUSE_CAM_SBI_ENABLE_IF_SHFT                          0x5
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_BMSK                                   0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_SHFT                                    0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_BMSK                                     0x8
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_SHFT                                     0x3
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_BMSK                           0x7
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_SHFT                           0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000415c)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_RMSK                                           0xe7fffff7
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_BMSK                         0x80000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_SHFT                               0x1f
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_BMSK                         0x40000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_SHFT                               0x1e
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_BMSK                               0x20000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_SHFT                                     0x1d
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_BMSK                                0x4000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_SHFT                                     0x1a
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK             0x2000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT                  0x19
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_BMSK                 0x1000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_SHFT                      0x18
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_BMSK                 0x800000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_SHFT                     0x17
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_BMSK                           0x400000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_SHFT                               0x16
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_BMSK                      0x200000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_SHFT                          0x15
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_BMSK                                   0x100000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_SHFT                                       0x14
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_BMSK                               0x80000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_SHFT                                  0x13
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_BMSK                            0x7c000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_SHFT                                0xe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_BMSK                         0x2000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_SHFT                            0xd
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_BMSK                            0x1000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_SHFT                               0xc
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_BMSK                                     0x800
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_SHFT                                       0xb
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_EFUSE_Q6SS_HVX_HALF_BMSK                            0x400
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_EFUSE_Q6SS_HVX_HALF_SHFT                              0xa
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_BMSK                                   0x200
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_SHFT                                     0x9
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_BMSK                                    0x1e0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_SHFT                                      0x5
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_BMSK                          0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_SHFT                           0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_BMSK                                   0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_SHFT                                   0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_BMSK                                   0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_SHFT                                   0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_BMSK                                   0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_SHFT                                   0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004160)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_BMSK                0xffffc000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_SHFT                       0xe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_BMSK                      0x3c00
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_SHFT                         0xa
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_BMSK                    0x3ff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_SHFT                      0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004164)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_BMSK                       0xc0000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_SHFT                             0x1e
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_BMSK             0x20000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_SHFT                   0x1d
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_BMSK                 0x10000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_SHFT                       0x1c
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_BMSK                       0x8000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_SHFT                            0x1b
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_BMSK                               0x4000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_SHFT                                    0x1a
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_BMSK                     0x2000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_SHFT                          0x19
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_BMSK                                0x1000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_SHFT                                     0x18
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_BMSK                  0xffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_SHFT                       0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004168)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_RMSK                                           0xfbffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_BMSK            0x80000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_SHFT                  0x1f
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_FUSE_CORTEX_M3_DISABLE_BMSK                    0x40000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_FUSE_CORTEX_M3_DISABLE_SHFT                          0x1e
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_Q_CONFIG_FUSE_BMSK                             0x20000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_Q_CONFIG_FUSE_SHFT                                   0x1d
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_I_MC5_FUSE_BMSK                                0x10000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_I_MC5_FUSE_SHFT                                      0x1c
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_I_MC4_FUSE_BMSK                                 0x8000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_I_MC4_FUSE_SHFT                                      0x1b
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_BMSK              0x2000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_SHFT                   0x19
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_BMSK              0x1000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_SHFT                   0x18
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_BMSK               0x800000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_SHFT                   0x17
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_BMSK               0x400000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_SHFT                   0x16
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_BMSK               0x200000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_SHFT                   0x15
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_BMSK                0x100000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_SHFT                    0x14
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_BMSK                        0x80000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_SHFT                           0x13
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_BMSK                        0x40000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_SHFT                           0x12
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_BMSK                   0x20000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_SHFT                      0x11
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_BMSK                   0x10000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_SHFT                      0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_BMSK                    0x8000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_SHFT                       0xf
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_BMSK                    0x4000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_SHFT                       0xe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_BMSK                   0x2000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_SHFT                      0xd
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_BMSK                   0x1000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_SHFT                      0xc
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                 0x800
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                   0xb
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK                  0x400
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT                    0xa
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_BMSK                       0x200
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_SHFT                         0x9
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_BMSK                       0x100
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_SHFT                         0x8
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_BMSK                        0x80
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_SHFT                         0x7
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_BMSK                        0x40
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_SHFT                         0x6
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_BMSK                       0x20
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_SHFT                        0x5
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_BMSK                       0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_SHFT                        0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK                     0x8
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT                     0x3
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK                      0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT                      0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_BMSK                                  0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_SHFT                                  0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_BMSK                                      0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_SHFT                                      0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000416c)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_BMSK                      0xff000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_SHFT                            0x18
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_APSS_KRYO_PP_DISABLE_BMSK                        0x800000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_APSS_KRYO_PP_DISABLE_SHFT                            0x17
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_BMSK                         0x400000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_SHFT                             0x16
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_BMSK                    0x200000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_SHFT                        0x15
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_BMSK                          0x1f8000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_SHFT                               0xf
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_BMSK                        0x4000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_SHFT                           0xe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_BMSK                       0x3fc0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_SHFT                          0x6
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_BMSK                  0x20
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_SHFT                   0x5
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_BMSK                  0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_SHFT                   0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_BMSK                   0x8
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_SHFT                   0x3
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_BMSK                   0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_SHFT                   0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_BMSK                   0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_SHFT                   0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_BMSK                   0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_SHFT                   0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004170)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_RMSK                                             0x7fffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_6_BMSK                      0x400000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_6_SHFT                          0x16
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_5_BMSK                      0x200000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_5_SHFT                          0x15
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_4_BMSK                      0x100000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_4_SHFT                          0x14
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_3_BMSK                       0x80000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_3_SHFT                          0x13
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_2_BMSK                       0x40000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_2_SHFT                          0x12
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_1_BMSK                       0x20000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_1_SHFT                          0x11
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_0_BMSK                       0x10000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_0_SHFT                          0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_BMSK                         0xffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_SHFT                            0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004174)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_RSVD_BMSK                                      0xfffffffe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_RSVD_SHFT                                             0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_DISABLE_SEC_BOOT_GPIO_BMSK                            0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW3_MSB_DISABLE_SEC_BOOT_GPIO_SHFT                            0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004178)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_RSVD_BMSK                                      0xfffffffe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_RSVD_SHFT                                             0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_LEGACY_MBNV6_OVERRIDE_BMSK                            0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_LSB_LEGACY_MBNV6_OVERRIDE_SHFT                            0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000417c)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_RSVD_BMSK                                      0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW4_MSB_RSVD_SHFT                                             0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004180)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_RSVD_BMSK                                      0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_LSB_RSVD_SHFT                                             0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004184)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_ADDR)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_RSVD_BMSK                                      0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW5_MSB_RSVD_SHFT                                             0x0

#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004188)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ADDR)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_RSVD0_BMSK                                            0xfffffff0
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_RSVD0_SHFT                                                   0x4
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ROOT_CERT_ACTIVATION_LIST_BMSK                               0xf
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ROOT_CERT_ACTIVATION_LIST_SHFT                               0x0

#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000418c)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_ADDR)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_RSVD1_BMSK                                            0xfffffffe
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_RSVD1_SHFT                                                   0x1
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_CURRENT_UIE_KEY_SEL_BMSK                                     0x1
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_CURRENT_UIE_KEY_SEL_SHFT                                     0x0

#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004190)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ADDR)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_RSVD0_BMSK                                            0xfffffff0
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_RSVD0_SHFT                                                   0x4
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ROOT_CERT_REVOCATION_LIST_BMSK                               0xf
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ROOT_CERT_REVOCATION_LIST_SHFT                               0x0

#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004194)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_ADDR)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_RSVD0_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_RSVD0_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004198)
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW0_LSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_RSVD0_BMSK                                                0xe0000000
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_RSVD0_SHFT                                                      0x1d
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_MACCHIATO_EN_BMSK                                         0x10000000
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_MACCHIATO_EN_SHFT                                               0x1c
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_FEATURE_ID_BMSK                                            0xff00000
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_FEATURE_ID_SHFT                                                 0x14
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_JTAG_ID_BMSK                                                 0xfffff
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_JTAG_ID_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000419c)
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW0_MSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_PTE_DATA1_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_PTE_DATA1_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041a0)
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW1_LSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_PTE_DATA0_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_PTE_DATA0_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041a4)
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW1_MSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_PTE_DATA1_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_PTE_DATA1_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041a8)
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW2_LSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_PTE_DATA0_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_PTE_DATA0_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041ac)
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW2_MSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_PTE_DATA1_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_PTE_DATA1_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041b0)
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW3_LSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_PTE_DATA0_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_PTE_DATA0_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041b4)
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW3_MSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_PTE_DATA1_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_PTE_DATA1_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW4_LSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041b8)
#define HWIO_QFPROM_CORR_PTE_ROW4_LSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW4_LSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW4_LSB_PTE_DATA0_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW4_LSB_PTE_DATA0_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW4_MSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041bc)
#define HWIO_QFPROM_CORR_PTE_ROW4_MSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW4_MSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW4_MSB_PTE_DATA1_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW4_MSB_PTE_DATA1_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW5_LSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041c0)
#define HWIO_QFPROM_CORR_PTE_ROW5_LSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW5_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW5_LSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW5_LSB_PTE_DATA0_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW5_LSB_PTE_DATA0_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW5_MSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041c4)
#define HWIO_QFPROM_CORR_PTE_ROW5_MSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW5_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_PTE_ROW5_MSB_ADDR)
#define HWIO_QFPROM_CORR_PTE_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW5_MSB_PTE_DATA1_BMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW5_MSB_PTE_DATA1_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_RD_PERM_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041c8)
#define HWIO_QFPROM_CORR_RD_PERM_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_CORR_RD_PERM_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_RD_PERM_LSB_ADDR)
#define HWIO_QFPROM_CORR_RD_PERM_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_RD_PERM_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG31_BMSK                                       0x80000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG31_SHFT                                             0x1f
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG30_BMSK                                       0x40000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG30_SHFT                                             0x1e
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG29_BMSK                                       0x20000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG29_SHFT                                             0x1d
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG28_BMSK                                       0x10000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG28_SHFT                                             0x1c
#define HWIO_QFPROM_CORR_RD_PERM_LSB_USER_DATA_KEY_BMSK                                          0x8000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_USER_DATA_KEY_SHFT                                               0x1b
#define HWIO_QFPROM_CORR_RD_PERM_LSB_IMAGE_ENCR_KEY1_BMSK                                        0x4000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_IMAGE_ENCR_KEY1_SHFT                                             0x1a
#define HWIO_QFPROM_CORR_RD_PERM_LSB_BOOT_ROM_PATCH_BMSK                                         0x2000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_BOOT_ROM_PATCH_SHFT                                              0x19
#define HWIO_QFPROM_CORR_RD_PERM_LSB_SEC_KEY_DERIVATION_KEY_BMSK                                 0x1000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_SEC_KEY_DERIVATION_KEY_SHFT                                      0x18
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SEC_BOOT_BMSK                                            0x800000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SEC_BOOT_SHFT                                                0x17
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_IMAGE_ENCR_KEY_BMSK                                      0x400000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_IMAGE_ENCR_KEY_SHFT                                          0x16
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG21_BMSK                                          0x200000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG21_SHFT                                              0x15
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG20_BMSK                                          0x100000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG20_SHFT                                              0x14
#define HWIO_QFPROM_CORR_RD_PERM_LSB_MEM_CONFIG_BMSK                                               0x80000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_MEM_CONFIG_SHFT                                                  0x13
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CALIB_BMSK                                                    0x40000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CALIB_SHFT                                                       0x12
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PK_HASH0_BMSK                                                 0x20000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PK_HASH0_SHFT                                                    0x11
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_5_BMSK                                          0x10000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_5_SHFT                                             0x10
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_4_BMSK                                           0x8000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_4_SHFT                                              0xf
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_3_BMSK                                           0x4000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_3_SHFT                                              0xe
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_2_BMSK                                           0x2000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_2_SHFT                                              0xd
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_1_BMSK                                           0x1000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_1_SHFT                                              0xc
#define HWIO_QFPROM_CORR_RD_PERM_LSB_FEAT_CONFIG_BMSK                                                0x800
#define HWIO_QFPROM_CORR_RD_PERM_LSB_FEAT_CONFIG_SHFT                                                  0xb
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_CONFIG_BMSK                                                 0x400
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_CONFIG_SHFT                                                   0xa
#define HWIO_QFPROM_CORR_RD_PERM_LSB_FEC_EN_BMSK                                                     0x200
#define HWIO_QFPROM_CORR_RD_PERM_LSB_FEC_EN_SHFT                                                       0x9
#define HWIO_QFPROM_CORR_RD_PERM_LSB_WR_PERM_BMSK                                                    0x100
#define HWIO_QFPROM_CORR_RD_PERM_LSB_WR_PERM_SHFT                                                      0x8
#define HWIO_QFPROM_CORR_RD_PERM_LSB_RD_PERM_BMSK                                                     0x80
#define HWIO_QFPROM_CORR_RD_PERM_LSB_RD_PERM_SHFT                                                      0x7
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PTE_BMSK                                                         0x40
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PTE_SHFT                                                          0x6
#define HWIO_QFPROM_CORR_RD_PERM_LSB_MRC_2_0_BMSK                                                     0x20
#define HWIO_QFPROM_CORR_RD_PERM_LSB_MRC_2_0_SHFT                                                      0x5
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CM_FEAT_CONFIG_BMSK                                              0x10
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CM_FEAT_CONFIG_SHFT                                               0x4
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PRI_KEY_DERIVATION_KEY_BMSK                                       0x8
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PRI_KEY_DERIVATION_KEY_SHFT                                       0x3
#define HWIO_QFPROM_CORR_RD_PERM_LSB_BOOT_PATCH_HASH_BMSK                                              0x4
#define HWIO_QFPROM_CORR_RD_PERM_LSB_BOOT_PATCH_HASH_SHFT                                              0x2
#define HWIO_QFPROM_CORR_RD_PERM_LSB_LCM_BMSK                                                          0x2
#define HWIO_QFPROM_CORR_RD_PERM_LSB_LCM_SHFT                                                          0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CRI_CM_PRIVATE_BMSK                                               0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CRI_CM_PRIVATE_SHFT                                               0x0

#define HWIO_QFPROM_CORR_RD_PERM_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041cc)
#define HWIO_QFPROM_CORR_RD_PERM_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_CORR_RD_PERM_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_RD_PERM_MSB_ADDR)
#define HWIO_QFPROM_CORR_RD_PERM_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_RD_PERM_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_RD_PERM_MSB_RSVD0_BMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_RD_PERM_MSB_RSVD0_SHFT                                                        0x0

#define HWIO_QFPROM_CORR_WR_PERM_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041d0)
#define HWIO_QFPROM_CORR_WR_PERM_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_CORR_WR_PERM_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_WR_PERM_LSB_ADDR)
#define HWIO_QFPROM_CORR_WR_PERM_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_WR_PERM_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG31_BMSK                                       0x80000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG31_SHFT                                             0x1f
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG30_BMSK                                       0x40000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG30_SHFT                                             0x1e
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG29_BMSK                                       0x20000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG29_SHFT                                             0x1d
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG28_BMSK                                       0x10000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG28_SHFT                                             0x1c
#define HWIO_QFPROM_CORR_WR_PERM_LSB_USER_DATA_KEY_BMSK                                          0x8000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_USER_DATA_KEY_SHFT                                               0x1b
#define HWIO_QFPROM_CORR_WR_PERM_LSB_IMAGE_ENCR_KEY1_BMSK                                        0x4000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_IMAGE_ENCR_KEY1_SHFT                                             0x1a
#define HWIO_QFPROM_CORR_WR_PERM_LSB_BOOT_ROM_PATCH_BMSK                                         0x2000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_BOOT_ROM_PATCH_SHFT                                              0x19
#define HWIO_QFPROM_CORR_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_BMSK                                 0x1000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_SHFT                                      0x18
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SEC_BOOT_BMSK                                            0x800000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SEC_BOOT_SHFT                                                0x17
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_IMAGE_ENCR_KEY_BMSK                                      0x400000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_IMAGE_ENCR_KEY_SHFT                                          0x16
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG21_BMSK                                          0x200000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG21_SHFT                                              0x15
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG20_BMSK                                          0x100000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG20_SHFT                                              0x14
#define HWIO_QFPROM_CORR_WR_PERM_LSB_MEM_CONFIG_BMSK                                               0x80000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_MEM_CONFIG_SHFT                                                  0x13
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CALIB_BMSK                                                    0x40000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CALIB_SHFT                                                       0x12
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PK_HASH0_BMSK                                                 0x20000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PK_HASH0_SHFT                                                    0x11
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_5_BMSK                                          0x10000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_5_SHFT                                             0x10
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_4_BMSK                                           0x8000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_4_SHFT                                              0xf
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_3_BMSK                                           0x4000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_3_SHFT                                              0xe
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_2_BMSK                                           0x2000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_2_SHFT                                              0xd
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_1_BMSK                                           0x1000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_1_SHFT                                              0xc
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_CONFIG_BMSK                                                 0x800
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_CONFIG_SHFT                                                   0xb
#define HWIO_QFPROM_CORR_WR_PERM_LSB_FEAT_CONFIG_BMSK                                                0x400
#define HWIO_QFPROM_CORR_WR_PERM_LSB_FEAT_CONFIG_SHFT                                                  0xa
#define HWIO_QFPROM_CORR_WR_PERM_LSB_FEC_EN_BMSK                                                     0x200
#define HWIO_QFPROM_CORR_WR_PERM_LSB_FEC_EN_SHFT                                                       0x9
#define HWIO_QFPROM_CORR_WR_PERM_LSB_WR_PERM_BMSK                                                    0x100
#define HWIO_QFPROM_CORR_WR_PERM_LSB_WR_PERM_SHFT                                                      0x8
#define HWIO_QFPROM_CORR_WR_PERM_LSB_RD_PERM_BMSK                                                     0x80
#define HWIO_QFPROM_CORR_WR_PERM_LSB_RD_PERM_SHFT                                                      0x7
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PTE_BMSK                                                         0x40
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PTE_SHFT                                                          0x6
#define HWIO_QFPROM_CORR_WR_PERM_LSB_MRC_2_0_BMSK                                                     0x20
#define HWIO_QFPROM_CORR_WR_PERM_LSB_MRC_2_0_SHFT                                                      0x5
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CM_FEAT_CONFIG_BMSK                                              0x10
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CM_FEAT_CONFIG_SHFT                                               0x4
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PRI_KEY_DERIVATION_KEY_BMSK                                       0x8
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PRI_KEY_DERIVATION_KEY_SHFT                                       0x3
#define HWIO_QFPROM_CORR_WR_PERM_LSB_BOOT_PATCH_HASH_BMSK                                              0x4
#define HWIO_QFPROM_CORR_WR_PERM_LSB_BOOT_PATCH_HASH_SHFT                                              0x2
#define HWIO_QFPROM_CORR_WR_PERM_LSB_LCM_BMSK                                                          0x2
#define HWIO_QFPROM_CORR_WR_PERM_LSB_LCM_SHFT                                                          0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CRI_CM_PRIVATE_BMSK                                               0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CRI_CM_PRIVATE_SHFT                                               0x0

#define HWIO_QFPROM_CORR_WR_PERM_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041d4)
#define HWIO_QFPROM_CORR_WR_PERM_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_CORR_WR_PERM_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_WR_PERM_MSB_ADDR)
#define HWIO_QFPROM_CORR_WR_PERM_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_WR_PERM_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_WR_PERM_MSB_RSVD0_BMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_WR_PERM_MSB_RSVD0_SHFT                                                        0x0

#define HWIO_QFPROM_CORR_FEC_EN_LSB_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041d8)
#define HWIO_QFPROM_CORR_FEC_EN_LSB_RMSK                                                        0xffffffff
#define HWIO_QFPROM_CORR_FEC_EN_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEC_EN_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEC_EN_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEC_EN_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION31_FEC_EN_BMSK                                        0x80000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION31_FEC_EN_SHFT                                              0x1f
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION30_FEC_EN_BMSK                                        0x40000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION30_FEC_EN_SHFT                                              0x1e
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION29_FEC_EN_BMSK                                        0x20000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION29_FEC_EN_SHFT                                              0x1d
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION28_FEC_EN_BMSK                                        0x10000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION28_FEC_EN_SHFT                                              0x1c
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION27_FEC_EN_BMSK                                         0x8000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION27_FEC_EN_SHFT                                              0x1b
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION26_FEC_EN_BMSK                                         0x4000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION26_FEC_EN_SHFT                                              0x1a
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION25_FEC_EN_BMSK                                         0x2000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION25_FEC_EN_SHFT                                              0x19
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION24_FEC_EN_BMSK                                         0x1000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION24_FEC_EN_SHFT                                              0x18
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION23_FEC_EN_BMSK                                          0x800000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION23_FEC_EN_SHFT                                              0x17
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION22_FEC_EN_BMSK                                          0x400000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION22_FEC_EN_SHFT                                              0x16
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION21_FEC_EN_BMSK                                          0x200000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION21_FEC_EN_SHFT                                              0x15
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION20_FEC_EN_BMSK                                          0x100000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION20_FEC_EN_SHFT                                              0x14
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION19_FEC_EN_BMSK                                           0x80000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION19_FEC_EN_SHFT                                              0x13
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION18_FEC_EN_BMSK                                           0x40000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION18_FEC_EN_SHFT                                              0x12
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION17_FEC_EN_BMSK                                           0x20000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION17_FEC_EN_SHFT                                              0x11
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION16_FEC_EN_BMSK                                           0x10000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION16_FEC_EN_SHFT                                              0x10
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION15_FEC_EN_BMSK                                            0x8000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION15_FEC_EN_SHFT                                               0xf
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION14_FEC_EN_BMSK                                            0x4000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION14_FEC_EN_SHFT                                               0xe
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION13_FEC_EN_BMSK                                            0x2000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION13_FEC_EN_SHFT                                               0xd
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION12_FEC_EN_BMSK                                            0x1000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION12_FEC_EN_SHFT                                               0xc
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION11_FEC_EN_BMSK                                             0x800
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION11_FEC_EN_SHFT                                               0xb
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION10_FEC_EN_BMSK                                             0x400
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION10_FEC_EN_SHFT                                               0xa
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION9_FEC_EN_BMSK                                              0x200
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION9_FEC_EN_SHFT                                                0x9
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION8_FEC_EN_BMSK                                              0x100
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION8_FEC_EN_SHFT                                                0x8
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION7_FEC_EN_BMSK                                               0x80
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION7_FEC_EN_SHFT                                                0x7
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION6_FEC_EN_BMSK                                               0x40
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION6_FEC_EN_SHFT                                                0x6
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION5_FEC_EN_BMSK                                               0x20
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION5_FEC_EN_SHFT                                                0x5
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION4_FEC_EN_BMSK                                               0x10
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION4_FEC_EN_SHFT                                                0x4
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION3_FEC_EN_BMSK                                                0x8
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION3_FEC_EN_SHFT                                                0x3
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION2_FEC_EN_BMSK                                                0x4
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION2_FEC_EN_SHFT                                                0x2
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION1_FEC_EN_BMSK                                                0x2
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION1_FEC_EN_SHFT                                                0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION0_FEC_EN_BMSK                                                0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION0_FEC_EN_SHFT                                                0x0

#define HWIO_QFPROM_CORR_FEC_EN_MSB_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041dc)
#define HWIO_QFPROM_CORR_FEC_EN_MSB_RMSK                                                        0xffffffff
#define HWIO_QFPROM_CORR_FEC_EN_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEC_EN_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEC_EN_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEC_EN_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEC_EN_MSB_RSVD0_BMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_FEC_EN_MSB_RSVD0_SHFT                                                         0x0

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041e0)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_IN)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                   0x80000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                         0x1f
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_BMSK                    0x40000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_SHFT                          0x1e
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_BMSK                             0x20000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_SHFT                                   0x1d
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_BMSK                          0x10000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_SHFT                                0x1c
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SP_DISABLE_BMSK                                     0x8000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SP_DISABLE_SHFT                                          0x1b
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_BMSK                                    0x4000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_SHFT                                         0x1a
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_DISABLE_IN_ROM_BMSK                           0x2000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_DISABLE_IN_ROM_SHFT                                0x19
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_BMSK                0x1000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_SHFT                     0x18
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_BMSK               0x800000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_SHFT                   0x17
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_BMSK                                  0x400000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_SHFT                                      0x16
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_BMSK                           0x200000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_SHFT                               0x15
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_BMSK                            0x100000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_SHFT                                0x14
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_IMAGE_ENCRYPTION_ENABLE_BMSK                          0x80000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_IMAGE_ENCRYPTION_ENABLE_SHFT                             0x13
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ROOT_CERT_TOTAL_NUM_BMSK                              0x60000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ROOT_CERT_TOTAL_NUM_SHFT                                 0x11
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_USB_TYPE_C_DISABLE_BMSK                           0x10000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_USB_TYPE_C_DISABLE_SHFT                              0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_LOG_DISABLE_BMSK                                   0x8000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_LOG_DISABLE_SHFT                                      0xf
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_WDOG_EN_BMSK                                           0x4000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_WDOG_EN_SHFT                                              0xe
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_BMSK              0x2000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_SHFT                 0xd
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_FUSE_PROG_DISABLE_BMSK                              0x1000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_FUSE_PROG_DISABLE_SHFT                                 0xc
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SPI_CLK_BOOT_FREQ_BMSK                                  0x800
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SPI_CLK_BOOT_FREQ_SHFT                                    0xb
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_BMSK                          0x400
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_SHFT                            0xa
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_BMSK                                          0x3e0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SHFT                                            0x5
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SDCC_MCLK_BOOT_FREQ_BMSK                                 0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SDCC_MCLK_BOOT_FREQ_SHFT                                  0x4
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_BMSK                               0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_SHFT                               0x3
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_BMSK                                  0x4
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_SHFT                                  0x2
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_BMSK                                         0x2
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_SHFT                                         0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_BMSK                                      0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_SHFT                                      0x0

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041e4)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_ADDR)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_RSVD1_BMSK                                         0xffffc000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_RSVD1_SHFT                                                0xe
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_BMSK                        0x2000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_SHFT                           0xd
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_BMSK                        0x1000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_SHFT                           0xc
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_BMSK                         0x800
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_SHFT                           0xb
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_BMSK                         0x400
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_SHFT                           0xa
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_BMSK                         0x200
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_SHFT                           0x9
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_BMSK                          0x100
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_SHFT                            0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_BMSK                                  0x80
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_SHFT                                   0x7
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_BMSK                                  0x40
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_SHFT                                   0x6
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_BMSK                             0x20
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_SHFT                              0x5
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_BMSK                             0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_SHFT                              0x4
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_BMSK                              0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_SHFT                              0x3
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_BMSK                              0x4
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_SHFT                              0x2
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_BMSK                             0x2
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_SHFT                             0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_BMSK                             0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_SHFT                             0x0

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041e8)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_ADDR)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_DISABLE_RSA_BMSK                                   0x80000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_DISABLE_RSA_SHFT                                         0x1f
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_EKU_ENFORCEMENT_EN_BMSK                            0x40000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_EKU_ENFORCEMENT_EN_SHFT                                  0x1e
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD2_BMSK                                         0x3fff0000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD2_SHFT                                               0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_BMSK                                0x8000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_SHFT                                   0xf
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_BMSK                                0x4000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_SHFT                                   0xe
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_BMSK                                0x2000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_SHFT                                   0xd
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_BMSK                                0x1000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_SHFT                                   0xc
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_BMSK                                              0xf00
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_SHFT                                                0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_OVERRIDE_BMSK                          0x80
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_OVERRIDE_SHFT                           0x7
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_FIPS_OVERRIDE_BMSK                                    0x40
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_FIPS_OVERRIDE_SHFT                                     0x6
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_MODEM_CRYPTO_FIPS_ENABLE_BMSK                            0x20
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_MODEM_CRYPTO_FIPS_ENABLE_SHFT                             0x5
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_ENABLE_BMSK                            0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_ENABLE_SHFT                             0x4
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_FIPS_ENABLE_BMSK                                       0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_FIPS_ENABLE_SHFT                                       0x3
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_NVM_AR_CONFIG_BMSK                                     0x6
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_NVM_AR_CONFIG_SHFT                                     0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD0_BMSK                                                0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD0_SHFT                                                0x0

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041ec)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_ADDR)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OEM_PRODUCT_ID_BMSK                                0xffff0000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OEM_PRODUCT_ID_SHFT                                      0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OEM_HW_ID_BMSK                                         0xffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OEM_HW_ID_SHFT                                            0x0

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041f0)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_ADDR)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PERIPH_VID_BMSK                                    0xffff0000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PERIPH_VID_SHFT                                          0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PERIPH_PID_BMSK                                        0xffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PERIPH_PID_SHFT                                           0x0

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041f4)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ADDR)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_RSVD0_BMSK                                         0xffffff00
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_RSVD0_SHFT                                                0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ANTI_ROLLBACK_FEATURE_EN_BMSK                            0xff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ANTI_ROLLBACK_FEATURE_EN_SHFT                             0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041f8)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_RMSK                                              0x7fffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_BMSK                      0x40000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_SHFT                            0x1e
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_BMSK                                0x20000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_SHFT                                      0x1d
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_BMSK                         0x1fe00000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_SHFT                               0x15
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_BMSK                          0x180000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_SHFT                              0x13
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_BMSK                        0x40000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_SHFT                           0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_BMSK                        0x20000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_SHFT                           0x11
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_BMSK                                 0x10000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_SHFT                                    0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_BMSK                                 0x8000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_SHFT                                    0xf
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_BMSK                                 0x4000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_SHFT                                    0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_BMSK                                       0x2000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_SHFT                                          0xd
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_BMSK                                     0x1000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_SHFT                                        0xc
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_BMSK                            0x800
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_SHFT                              0xb
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK                    0x400
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT                      0xa
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_BMSK                                     0x200
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_SHFT                                       0x9
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_BMSK                                     0x100
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_SHFT                                       0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_BMSK                                         0x80
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_SHFT                                          0x7
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_BMSK                               0x40
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_SHFT                                0x6
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EFUSE_CAM_SBI_ENABLE_IF_BMSK                            0x20
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EFUSE_CAM_SBI_ENABLE_IF_SHFT                             0x5
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_BMSK                                      0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_SHFT                                       0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_BMSK                                        0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_SHFT                                        0x3
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_BMSK                              0x7
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_SHFT                              0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041fc)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_RMSK                                              0xe7fffff7
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_BMSK                            0x80000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_SHFT                                  0x1f
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_BMSK                            0x40000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_SHFT                                  0x1e
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_BMSK                                  0x20000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_SHFT                                        0x1d
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_BMSK                                   0x4000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_SHFT                                        0x1a
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK                0x2000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT                     0x19
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_BMSK                    0x1000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_SHFT                         0x18
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_BMSK                    0x800000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_SHFT                        0x17
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_BMSK                              0x400000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_SHFT                                  0x16
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_BMSK                         0x200000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_SHFT                             0x15
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_BMSK                                      0x100000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_SHFT                                          0x14
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_BMSK                                  0x80000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_SHFT                                     0x13
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_BMSK                               0x7c000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_SHFT                                   0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_BMSK                            0x2000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_SHFT                               0xd
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_BMSK                               0x1000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_SHFT                                  0xc
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_BMSK                                        0x800
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_SHFT                                          0xb
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_EFUSE_Q6SS_HVX_HALF_BMSK                               0x400
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_EFUSE_Q6SS_HVX_HALF_SHFT                                 0xa
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_BMSK                                      0x200
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_SHFT                                        0x9
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_BMSK                                       0x1e0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_SHFT                                         0x5
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_BMSK                             0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_SHFT                              0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_BMSK                                      0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_SHFT                                      0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_BMSK                                      0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_SHFT                                      0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_BMSK                                      0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_SHFT                                      0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004200)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_BMSK                   0xffffc000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_SHFT                          0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_BMSK                         0x3c00
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_SHFT                            0xa
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_BMSK                       0x3ff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_SHFT                         0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004204)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_BMSK                          0xc0000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_SHFT                                0x1e
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_BMSK                0x20000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_SEC_CTRL_GCC_NPU_FUSE_DISABLE_SHFT                      0x1d
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_BMSK                    0x10000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_SHFT                          0x1c
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_BMSK                          0x8000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_AUTOMOTIVE_BIT_POWER_SHFT                               0x1b
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_BMSK                                  0x4000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_EMAC_DISABLE_SHFT                                       0x1a
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_BMSK                        0x2000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_SHFT                             0x19
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_BMSK                                   0x1000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_SHFT                                        0x18
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_BMSK                     0xffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_SHFT                          0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004208)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_RMSK                                              0xfbffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_BMSK               0x80000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_SHFT                     0x1f
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_FUSE_CORTEX_M3_DISABLE_BMSK                       0x40000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_FUSE_CORTEX_M3_DISABLE_SHFT                             0x1e
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_Q_CONFIG_FUSE_BMSK                                0x20000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_Q_CONFIG_FUSE_SHFT                                      0x1d
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_I_MC5_FUSE_BMSK                                   0x10000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_I_MC5_FUSE_SHFT                                         0x1c
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_I_MC4_FUSE_BMSK                                    0x8000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_I_MC4_FUSE_SHFT                                         0x1b
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_BMSK                 0x2000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_SHFT                      0x19
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_BMSK                 0x1000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_SHFT                      0x18
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_BMSK                  0x800000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_SHFT                      0x17
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_BMSK                  0x400000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_SHFT                      0x16
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_BMSK                  0x200000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_SHFT                      0x15
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_BMSK                   0x100000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MISC_DEBUG_DISABLE_SHFT                       0x14
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_BMSK                           0x80000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_SHFT                              0x13
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_BMSK                           0x40000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_SHFT                              0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_BMSK                      0x20000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_SHFT                         0x11
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_BMSK                      0x10000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_SHFT                         0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_BMSK                       0x8000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_SHFT                          0xf
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_BMSK                       0x4000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_SHFT                          0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_BMSK                      0x2000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_SHFT                         0xd
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_BMSK                      0x1000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_SHFT                         0xc
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                    0x800
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                      0xb
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK                     0x400
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT                       0xa
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_BMSK                          0x200
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_SHFT                            0x9
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_BMSK                          0x100
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_SHFT                            0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_BMSK                           0x80
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_SHFT                            0x7
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_BMSK                           0x40
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_SHFT                            0x6
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_BMSK                          0x20
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_SHFT                           0x5
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_BMSK                          0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_SHFT                           0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK                        0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT                        0x3
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK                         0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT                         0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_BMSK                                     0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_SHFT                                     0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_BMSK                                         0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_SHFT                                         0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000420c)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_BMSK                         0xff000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_SHFT                               0x18
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_APSS_KRYO_PP_DISABLE_BMSK                           0x800000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_APSS_KRYO_PP_DISABLE_SHFT                               0x17
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_BMSK                            0x400000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_SHFT                                0x16
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_BMSK                       0x200000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_SHFT                           0x15
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_BMSK                             0x1f8000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_SHFT                                  0xf
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_BMSK                           0x4000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_SHFT                              0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_BMSK                          0x3fc0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_SHFT                             0x6
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_BMSK                     0x20
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_SHFT                      0x5
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_BMSK                     0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_SHFT                      0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_BMSK                      0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_SHFT                      0x3
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_BMSK                      0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_SHFT                      0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_BMSK                      0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_SHFT                      0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_BMSK                      0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_SHFT                      0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004210)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_RMSK                                                0x7fffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_6_BMSK                         0x400000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_6_SHFT                             0x16
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_5_BMSK                         0x200000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_5_SHFT                             0x15
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_4_BMSK                         0x100000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_4_SHFT                             0x14
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_3_BMSK                          0x80000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_3_SHFT                             0x13
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_2_BMSK                          0x40000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_2_SHFT                             0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_1_BMSK                          0x20000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_1_SHFT                             0x11
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_0_BMSK                          0x10000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ACCU_RED_DEC_END_VAL_0_SHFT                             0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_BMSK                            0xffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_SHFT                               0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004214)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_RSVD_BMSK                                         0xfffffffe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_RSVD_SHFT                                                0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_DISABLE_SEC_BOOT_GPIO_BMSK                               0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_DISABLE_SEC_BOOT_GPIO_SHFT                               0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004218)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_RSVD_BMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_RSVD_SHFT                                                0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000421c)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_RSVD_BMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_RSVD_SHFT                                                0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004220)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_RSVD_BMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_LSB_RSVD_SHFT                                                0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004224)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_RSVD_BMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW5_MSB_RSVD_SHFT                                                0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004228)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_TAP_GEN_SPARE_INSTR_DISABLE_13_0_BMSK             0xfffc0000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_TAP_GEN_SPARE_INSTR_DISABLE_13_0_SHFT                   0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_TAP_INSTR_DISABLE_BMSK                               0x3ffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_LSB_TAP_INSTR_DISABLE_SHFT                                   0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000422c)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_SEC_TAP_ACCESS_DISABLE_BMSK                       0xfffc0000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_SEC_TAP_ACCESS_DISABLE_SHFT                             0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_TAP_GEN_SPARE_INSTR_DISABLE_31_14_BMSK               0x3ffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW6_MSB_TAP_GEN_SPARE_INSTR_DISABLE_31_14_SHFT                   0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004230)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_MODEM_PBL_PATCH_VERSION_BMSK                      0xfe000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_MODEM_PBL_PATCH_VERSION_SHFT                            0x19
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_APPS_PBL_PATCH_VERSION_BMSK                        0x1fc0000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_APPS_PBL_PATCH_VERSION_SHFT                             0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_APPS_PBL_BOOT_SPEED_BMSK                             0x30000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_APPS_PBL_BOOT_SPEED_SHFT                                0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_MODEM_PBL_BOOT_BMSK                                   0x8000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_MODEM_PBL_BOOT_SHFT                                      0xf
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_RSVD1_56_14_BMSK                                      0x4000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_RSVD1_56_14_SHFT                                         0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_APPS_BOOT_FROM_ROM_BMSK                               0x2000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_APPS_BOOT_FROM_ROM_SHFT                                  0xd
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_ENABLE_DEVICE_IN_TEST_MODE_BMSK                       0x1000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_ENABLE_DEVICE_IN_TEST_MODE_SHFT                          0xc
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_QTI_ROOT_SIG_FORMAT_SEL_BMSK                           0x800
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_QTI_ROOT_SIG_FORMAT_SEL_SHFT                             0xb
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_CE_BAM_DISABLE_BMSK                                    0x400
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_CE_BAM_DISABLE_SHFT                                      0xa
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_BMSK                0x200
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_SHFT                  0x9
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_ARM_CE_DISABLE_USAGE_BMSK                              0x100
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_ARM_CE_DISABLE_USAGE_SHFT                                0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_BOOT_ROM_CFG_BMSK                                       0xff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_LSB_BOOT_ROM_CFG_SHFT                                        0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004234)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_ADDR)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_APPS_BOOT_TRIGGER_DISABLE_BMSK                    0x80000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_APPS_BOOT_TRIGGER_DISABLE_SHFT                          0x1f
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_PBL_QSEE_BOOT_FLOW_DISABLE_BMSK                   0x40000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_PBL_QSEE_BOOT_FLOW_DISABLE_SHFT                         0x1e
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_XBL_SEC_AUTH_DISABLE_BMSK                         0x20000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_XBL_SEC_AUTH_DISABLE_SHFT                               0x1d
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_MSM_PKG_TYPE_BMSK                                 0x10000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_MSM_PKG_TYPE_SHFT                                       0x1c
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_SPSS_CONFIG_MODE_BMSK                              0xc000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_SPSS_CONFIG_MODE_SHFT                                   0x1a
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_PERIPH_DRV_STRENGTH_SETTING_BMSK                   0x3800000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_PERIPH_DRV_STRENGTH_SETTING_SHFT                        0x17
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_RSVD3_56_54_BMSK                                    0x400000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_RSVD3_56_54_SHFT                                        0x16
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_BMSK                                     0x3c0000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_FOUNDRY_ID_SHFT                                         0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_PLL_CFG_BMSK                                         0x3fff0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_PLL_CFG_SHFT                                             0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_APPS_PBL_PLL_CTRL_BMSK                                   0xf
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW7_MSB_APPS_PBL_PLL_CTRL_SHFT                                   0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004238)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_XBL0_BMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_XBL0_SHFT                                                 0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000423c)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_XBL1_BMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_XBL1_SHFT                                                 0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004240)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_PIL_SUBSYSTEM_31_0_BMSK                            0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_PIL_SUBSYSTEM_31_0_SHFT                                   0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004244)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_XBL_SEC_BMSK                                       0xfe000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_XBL_SEC_SHFT                                             0x19
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_AOP_BMSK                                            0x1fe0000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_AOP_SHFT                                                 0x11
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_TZ_BMSK                                               0x1ffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_TZ_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004248)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_XBL_CONFIG_1_0_BMSK                                0xc0000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_XBL_CONFIG_1_0_SHFT                                      0x1e
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_TQS_HASH_ACTIVE_BMSK                               0x3e000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_TQS_HASH_ACTIVE_SHFT                                     0x19
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_BMSK                           0x1000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_SHFT                                0x18
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_PIL_SUBSYSTEM_47_32_BMSK                             0xffff00
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_PIL_SUBSYSTEM_47_32_SHFT                                  0x8
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_SAFESWITCH_BMSK                                          0xff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_SAFESWITCH_SHFT                                           0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000424c)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_XBL_CONFIG_5_2_BMSK                                0xf0000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_XBL_CONFIG_5_2_SHFT                                      0x1c
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_DEVICE_CFG_BMSK                                     0xffe0000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_DEVICE_CFG_SHFT                                          0x11
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_DEBUG_POLICY_BMSK                                     0x1f000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_DEBUG_POLICY_SHFT                                         0xc
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_HYPERVISOR_BMSK                                         0xfff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_HYPERVISOR_SHFT                                           0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004250)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_MSS_BMSK                                           0xffff0000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_MSS_SHFT                                                 0x10
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_MISC_BMSK                                              0xffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_MISC_SHFT                                                 0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004254)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_SIMLOCK_BMSK                                       0x80000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_SIMLOCK_SHFT                                             0x1f
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_RSVD0_BMSK                                         0x7ffffff0
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_RSVD0_SHFT                                                0x4
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ROOT_CERT_PK_HASH_INDEX_BMSK                              0xf
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ROOT_CERT_PK_HASH_INDEX_SHFT                              0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004258)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_MISC_BMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_MISC_SHFT                                                 0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_ADDR                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000425c)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_ADDR)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_RSVD0_BMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_RSVD0_SHFT                                                0x0

#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_ADDR(n)                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004260 + 0x8 * (n))
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_MAXn                                                          5
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_HASH_DATA0_BMSK                                      0xffffffff
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_HASH_DATA0_SHFT                                             0x0

#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_ADDR(n)                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004264 + 0x8 * (n))
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_MAXn                                                          5
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_HASH_DATA1_BMSK                                      0xffffffff
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_HASH_DATA1_SHFT                                             0x0

#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004290)
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW0_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_USB_PHY0_TUNING_BMSK                                    0xf0000000
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_USB_PHY0_TUNING_SHFT                                          0x1c
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_SPARE_R63_B27_BMSK                                       0x8000000
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_SPARE_R63_B27_SHFT                                            0x1b
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_SPARE_R63_B26_BMSK                                       0x4000000
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_SPARE_R63_B26_SHFT                                            0x1a
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_SPARE_R63_B25_BMSK                                       0x2000000
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_SPARE_R63_B25_SHFT                                            0x19
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_USB2PHY_RCAL_CODE_BMSK                                   0x1e00000
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_USB2PHY_RCAL_CODE_SHFT                                        0x15
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_SPARE_R63_B20_BMSK                                        0x100000
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_SPARE_R63_B20_SHFT                                            0x14
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_SPARE_R63_B19_BMSK                                         0x80000
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_SPARE_R63_B19_SHFT                                            0x13
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_SPARE_R63_B18_BMSK                                         0x40000
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_SPARE_R63_B18_SHFT                                            0x12
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_MSS_Q6SS1_LDO_VREF_TRIM_BMSK                               0x3e000
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_MSS_Q6SS1_LDO_VREF_TRIM_SHFT                                   0xd
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_SPARE_R63_B12_BMSK                                          0x1000
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_SPARE_R63_B12_SHFT                                             0xc
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_TURING_Q6SS1_LDO_VREF_TRIM_BMSK                              0xf80
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_TURING_Q6SS1_LDO_VREF_TRIM_SHFT                                0x7
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_TURING_Q6SS1_LDO_ENABLE_NOM_BMSK                              0x40
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_TURING_Q6SS1_LDO_ENABLE_NOM_SHFT                               0x6
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_MSS_Q6SS0_LDO_VREF_TRIM_BMSK                                  0x3e
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_MSS_Q6SS0_LDO_VREF_TRIM_SHFT                                   0x1
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_MSS_Q6SS0_LDO_ENABLE_NOM_BMSK                                  0x1
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_MSS_Q6SS0_LDO_ENABLE_NOM_SHFT                                  0x0

#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004294)
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW0_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_CPR0_TARG_VOLT_SVS3_BMSK                                0xf8000000
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_CPR0_TARG_VOLT_SVS3_SHFT                                      0x1b
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_CPR0_TARG_VOLT_SVS_BMSK                                  0x7c00000
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_CPR0_TARG_VOLT_SVS_SHFT                                       0x16
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_CPR0_TARG_VOLT_NOM_BMSK                                   0x3e0000
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_CPR0_TARG_VOLT_NOM_SHFT                                       0x11
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_CPR0_TARG_VOLT_SUT_BMSK                                    0x1f000
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_CPR0_TARG_VOLT_SUT_SHFT                                        0xc
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_SPARE_R63_B43_BMSK                                           0x800
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_SPARE_R63_B43_SHFT                                             0xb
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_TURING_Q6SS1_LDO_ENABLE_MINSVS_BMSK                          0x400
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_TURING_Q6SS1_LDO_ENABLE_MINSVS_SHFT                            0xa
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_TURING_Q6SS1_LDO_ENABLE_LOWSVS_BMSK                          0x200
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_TURING_Q6SS1_LDO_ENABLE_LOWSVS_SHFT                            0x9
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_TURING_Q6SS1_LDO_ENABLE_SVS_BMSK                             0x100
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_TURING_Q6SS1_LDO_ENABLE_SVS_SHFT                               0x8
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_TURING_Q6SS1_LDO_ENABLE_SVS_L1_BMSK                           0x80
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_TURING_Q6SS1_LDO_ENABLE_SVS_L1_SHFT                            0x7
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_MSS_Q6SS0_LDO_ENABLE_MINSVS_BMSK                              0x40
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_MSS_Q6SS0_LDO_ENABLE_MINSVS_SHFT                               0x6
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_MSS_Q6SS0_LDO_ENABLE_LOWSVS_BMSK                              0x20
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_MSS_Q6SS0_LDO_ENABLE_LOWSVS_SHFT                               0x5
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_MSS_Q6SS0_LDO_ENABLE_SVS_BMSK                                 0x10
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_MSS_Q6SS0_LDO_ENABLE_SVS_SHFT                                  0x4
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_MSS_Q6SS0_LDO_ENABLE_SVS_L1_BMSK                               0x8
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_MSS_Q6SS0_LDO_ENABLE_SVS_L1_SHFT                               0x3
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_SPARE_R63_B34_BMSK                                             0x4
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_SPARE_R63_B34_SHFT                                             0x2
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_SPARE_R63_B33_BMSK                                             0x2
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_SPARE_R63_B33_SHFT                                             0x1
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_SPARE_R63_B32_BMSK                                             0x1
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_SPARE_R63_B32_SHFT                                             0x0

#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004298)
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW1_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_CPR2_TARG_VOLT_SVS_1_0_BMSK                             0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_CPR2_TARG_VOLT_SVS_1_0_SHFT                                   0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_CPR2_TARG_VOLT_NOM_BMSK                                 0x3e000000
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_CPR2_TARG_VOLT_NOM_SHFT                                       0x19
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_CPR2_TARG_VOLT_SUT_BMSK                                  0x1f00000
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_CPR2_TARG_VOLT_SUT_SHFT                                       0x14
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_CPR1_TARG_VOLT_SVS3_BMSK                                   0xf8000
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_CPR1_TARG_VOLT_SVS3_SHFT                                       0xf
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_CPR1_TARG_VOLT_SVS_BMSK                                     0x7c00
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_CPR1_TARG_VOLT_SVS_SHFT                                        0xa
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_CPR1_TARG_VOLT_NOM_BMSK                                      0x3e0
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_CPR1_TARG_VOLT_NOM_SHFT                                        0x5
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_CPR1_TARG_VOLT_SUT_BMSK                                       0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_CPR1_TARG_VOLT_SUT_SHFT                                        0x0

#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000429c)
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW1_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_SPARE_R64_B63_BMSK                                      0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_SPARE_R64_B63_SHFT                                            0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_REFGEN_NORTH_BGV_TRIM_BMSK                              0x7f800000
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_REFGEN_NORTH_BGV_TRIM_SHFT                                    0x17
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_REFGEN_SOUTH_BGV_TRIM_BMSK                                0x7f8000
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_REFGEN_SOUTH_BGV_TRIM_SHFT                                     0xf
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_BANDGAP_TRIM_BMSK                                           0x7f00
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_BANDGAP_TRIM_SHFT                                              0x8
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_SPARE_R64_B39_BMSK                                            0x80
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_SPARE_R64_B39_SHFT                                             0x7
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_SPARE_R64_B38_BMSK                                            0x40
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_SPARE_R64_B38_SHFT                                             0x6
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_SPARE_R64_B37_BMSK                                            0x20
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_SPARE_R64_B37_SHFT                                             0x5
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_SPARE_R64_B36_BMSK                                            0x10
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_SPARE_R64_B36_SHFT                                             0x4
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_SPARE_R64_B35_BMSK                                             0x8
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_SPARE_R64_B35_SHFT                                             0x3
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_CPR2_TARG_VOLT_SVS_4_2_BMSK                                    0x7
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_CPR2_TARG_VOLT_SVS_4_2_SHFT                                    0x0

#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042a0)
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW2_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_CPR4_TARG_VOLT_TUR_1_0_BMSK                             0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_CPR4_TARG_VOLT_TUR_1_0_SHFT                                   0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_CPR4_TARG_VOLT_SUT_BMSK                                 0x3e000000
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_CPR4_TARG_VOLT_SUT_SHFT                                       0x19
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_CPR3_TARG_VOLT_SVS3_BMSK                                 0x1f00000
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_CPR3_TARG_VOLT_SVS3_SHFT                                      0x14
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_CPR3_TARG_VOLT_SVS_BMSK                                    0xf8000
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_CPR3_TARG_VOLT_SVS_SHFT                                        0xf
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_CPR3_TARG_VOLT_NOM_BMSK                                     0x7c00
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_CPR3_TARG_VOLT_NOM_SHFT                                        0xa
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_CPR3_TARG_VOLT_TUR_BMSK                                      0x3e0
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_CPR3_TARG_VOLT_TUR_SHFT                                        0x5
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_CPR2_TARG_VOLT_SVS3_BMSK                                      0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_CPR2_TARG_VOLT_SVS3_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042a4)
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW2_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_CPR6_TARG_VOLT_NOM_3_0_BMSK                             0xf0000000
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_CPR6_TARG_VOLT_NOM_3_0_SHFT                                   0x1c
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_CPR6_TARG_VOLT_TUR_BMSK                                  0xf800000
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_CPR6_TARG_VOLT_TUR_SHFT                                       0x17
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_CPR5_TARG_VOLT_NOM_BMSK                                   0x7c0000
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_CPR5_TARG_VOLT_NOM_SHFT                                       0x12
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_CPR5_TARG_VOLT_TUR_BMSK                                    0x3e000
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_CPR5_TARG_VOLT_TUR_SHFT                                        0xd
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_CPR4_TARG_VOLT_SVSP_BMSK                                    0x1f00
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_CPR4_TARG_VOLT_SVSP_SHFT                                       0x8
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_CPR4_TARG_VOLT_NOM_BMSK                                       0xf8
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_CPR4_TARG_VOLT_NOM_SHFT                                        0x3
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_CPR4_TARG_VOLT_TUR_4_2_BMSK                                    0x7
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_CPR4_TARG_VOLT_TUR_4_2_SHFT                                    0x0

#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042a8)
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW3_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_AON_TARG_VOLT_0_BMSK                                    0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_AON_TARG_VOLT_0_SHFT                                          0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_CPR10_TARG_VOLT_SVS2_BMSK                               0x7c000000
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_CPR10_TARG_VOLT_SVS2_SHFT                                     0x1a
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_CPR10_TARG_VOLT_SVS_BMSK                                 0x3e00000
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_CPR10_TARG_VOLT_SVS_SHFT                                      0x15
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_CPR10_TARG_VOLT_NOM_BMSK                                  0x1f0000
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_CPR10_TARG_VOLT_NOM_SHFT                                      0x10
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_CPR10_TARG_VOLT_TUR_BMSK                                    0xf800
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_CPR10_TARG_VOLT_TUR_SHFT                                       0xb
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_CPR6_TARG_VOLT_SVS3_BMSK                                     0x7c0
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_CPR6_TARG_VOLT_SVS3_SHFT                                       0x6
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_CPR6_TARG_VOLT_SVS_BMSK                                       0x3e
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_CPR6_TARG_VOLT_SVS_SHFT                                        0x1
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_CPR6_TARG_VOLT_NOM_4_BMSK                                      0x1
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_CPR6_TARG_VOLT_NOM_4_SHFT                                      0x0

#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042ac)
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW3_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_SVS2_1_0_BMSK                     0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_SVS2_1_0_SHFT                           0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_SVS_BMSK                          0x3c000000
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_SVS_SHFT                                0x1a
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_NOM_BMSK                           0x3c00000
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_NOM_SHFT                                0x16
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_TUR_BMSK                            0x3c0000
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_TUR_SHFT                                0x12
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_SUT_BMSK                             0x3c000
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_CPR0_TARG_VOLT_OFFSET_SUT_SHFT                                 0xe
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_CPR11_TARG_VOLT_SVS2_BMSK                                   0x3f00
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_CPR11_TARG_VOLT_SVS2_SHFT                                      0x8
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_CPR11_SVS2_ROSEL_BMSK                                         0xf0
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_CPR11_SVS2_ROSEL_SHFT                                          0x4
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_AON_TARG_VOLT_4_1_BMSK                                         0xf
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_AON_TARG_VOLT_4_1_SHFT                                         0x0

#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042b0)
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW4_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_SVS2_1_0_BMSK                     0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_SVS2_1_0_SHFT                           0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_SVS_BMSK                          0x3c000000
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_SVS_SHFT                                0x1a
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_NOM_BMSK                           0x3c00000
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_NOM_SHFT                                0x16
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_TUR_BMSK                            0x3c0000
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_TUR_SHFT                                0x12
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_SUT_BMSK                             0x3c000
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR1_TARG_VOLT_OFFSET_SUT_SHFT                                 0xe
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR0_AGING_BMSK                                             0x3fc0
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR0_AGING_SHFT                                                0x6
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR0_TARG_VOLT_OFFSET_SVS3_BMSK                               0x3c
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR0_TARG_VOLT_OFFSET_SVS3_SHFT                                0x2
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR0_TARG_VOLT_OFFSET_SVS2_3_2_BMSK                            0x3
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR0_TARG_VOLT_OFFSET_SVS2_3_2_SHFT                            0x0

#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042b4)
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW4_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_SVS2_1_0_BMSK                     0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_SVS2_1_0_SHFT                           0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_SVS_BMSK                          0x3c000000
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_SVS_SHFT                                0x1a
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_NOM_BMSK                           0x3c00000
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_NOM_SHFT                                0x16
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_TUR_BMSK                            0x3c0000
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_TUR_SHFT                                0x12
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_SUT_BMSK                             0x3c000
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR2_TARG_VOLT_OFFSET_SUT_SHFT                                 0xe
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR1_AGING_BMSK                                             0x3fc0
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR1_AGING_SHFT                                                0x6
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR1_TARG_VOLT_OFFSET_SVS3_BMSK                               0x3c
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR1_TARG_VOLT_OFFSET_SVS3_SHFT                                0x2
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR1_TARG_VOLT_OFFSET_SVS2_3_2_BMSK                            0x3
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR1_TARG_VOLT_OFFSET_SVS2_3_2_SHFT                            0x0

#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042b8)
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW5_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR9_TARG_VOLT_NOM_1_0_BMSK                             0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR9_TARG_VOLT_NOM_1_0_SHFT                                   0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_SVSP_BMSK                         0x3c000000
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_SVSP_SHFT                               0x1a
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_NOM_BMSK                           0x3c00000
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_NOM_SHFT                                0x16
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_TUR_BMSK                            0x3c0000
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_TUR_SHFT                                0x12
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_SUT_BMSK                             0x3c000
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_SUT_SHFT                                 0xe
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR2_AGING_BMSK                                             0x3fc0
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR2_AGING_SHFT                                                0x6
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR2_TARG_VOLT_OFFSET_SVS3_BMSK                               0x3c
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR2_TARG_VOLT_OFFSET_SVS3_SHFT                                0x2
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR2_TARG_VOLT_OFFSET_SVS2_3_2_BMSK                            0x3
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR2_TARG_VOLT_OFFSET_SVS2_3_2_SHFT                            0x0

#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042bc)
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW5_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_AON_AGING_4_0_BMSK                                      0xf8000000
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_AON_AGING_4_0_SHFT                                            0x1b
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_CPR10_AGING_BMSK                                         0x7f80000
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_CPR10_AGING_SHFT                                              0x13
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_CPR10_TARG_VOLT_OFFSET_SVS2_BMSK                           0x78000
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_CPR10_TARG_VOLT_OFFSET_SVS2_SHFT                               0xf
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_CPR10_TARG_VOLT_OFFSET_SVS_BMSK                             0x7800
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_CPR10_TARG_VOLT_OFFSET_SVS_SHFT                                0xb
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_CPR10_TARG_VOLT_OFFSET_NOM_BMSK                              0x780
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_CPR10_TARG_VOLT_OFFSET_NOM_SHFT                                0x7
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_CPR10_TARG_VOLT_OFFSET_TUR_BMSK                               0x78
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_CPR10_TARG_VOLT_OFFSET_TUR_SHFT                                0x3
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_CPR9_TARG_VOLT_NOM_4_2_BMSK                                    0x7
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_CPR9_TARG_VOLT_NOM_4_2_SHFT                                    0x0

#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042c0)
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW6_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW6_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR_LDO_RC_1_0_BMSK                                     0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR_LDO_RC_1_0_SHFT                                           0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR8_LDO_TARG_VOLT_SVS3_BMSK                            0x3c000000
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR8_LDO_TARG_VOLT_SVS3_SHFT                                  0x1a
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR8_LDO_TARG_VOLT_SVS_BMSK                              0x3c00000
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR8_LDO_TARG_VOLT_SVS_SHFT                                   0x16
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR8_LDO_TARG_VOLT_NOM_BMSK                               0x3c0000
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR8_LDO_TARG_VOLT_NOM_SHFT                                   0x12
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR7_LDO_TARG_VOLT_SVS3_BMSK                               0x3c000
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR7_LDO_TARG_VOLT_SVS3_SHFT                                   0xe
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR7_LDO_TARG_VOLT_SVS2_BMSK                                0x3c00
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR7_LDO_TARG_VOLT_SVS2_SHFT                                   0xa
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR7_LDO_TARG_VOLT_SVSP_BMSK                                 0x3c0
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR7_LDO_TARG_VOLT_SVSP_SHFT                                   0x6
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR_GLOBAL_RC_BMSK                                            0x38
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR_GLOBAL_RC_SHFT                                             0x3
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_AON_AGING_7_5_BMSK                                             0x7
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_AON_AGING_7_5_SHFT                                             0x0

#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042c4)
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW6_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW6_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR11_TURBO_QUOT_VMIN_0_BMSK                            0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR11_TURBO_QUOT_VMIN_0_SHFT                                  0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR11_TARG_VOLT_SVS_BMSK                                0x7e000000
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR11_TARG_VOLT_SVS_SHFT                                      0x19
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR11_TARG_VOLT_NOM_BMSK                                 0x1f80000
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR11_TARG_VOLT_NOM_SHFT                                      0x13
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR11_TARG_VOLT_TUR_BMSK                                   0x7e000
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR11_TARG_VOLT_TUR_SHFT                                       0xd
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR11_SVS_ROSEL_BMSK                                        0x1e00
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR11_SVS_ROSEL_SHFT                                           0x9
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR11_NOMINAL_ROSEL_BMSK                                     0x1e0
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR11_NOMINAL_ROSEL_SHFT                                       0x5
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR11_TURBO_ROSEL_BMSK                                        0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR11_TURBO_ROSEL_SHFT                                         0x1
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR_LDO_RC_2_BMSK                                              0x1
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR_LDO_RC_2_SHFT                                              0x0

#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042c8)
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW7_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW7_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_CPR11_SVS_QUOT_VMIN_8_0_BMSK                            0xff800000
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_CPR11_SVS_QUOT_VMIN_8_0_SHFT                                  0x17
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_CPR11_NOMINAL_QUOT_VMIN_BMSK                              0x7ff800
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_CPR11_NOMINAL_QUOT_VMIN_SHFT                                   0xb
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_CPR11_TURBO_QUOT_VMIN_11_1_BMSK                              0x7ff
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_CPR11_TURBO_QUOT_VMIN_11_1_SHFT                                0x0

#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042cc)
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW7_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW7_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_CPR11_QUOT_OFFSET_SVS_1_0_BMSK                          0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_CPR11_QUOT_OFFSET_SVS_1_0_SHFT                                0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_CPR11_QUOT_OFFSET_NOM_BMSK                              0x3f800000
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_CPR11_QUOT_OFFSET_NOM_SHFT                                    0x17
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_CPR11_QUOT_OFFSET_TUR_BMSK                                0x7f8000
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_CPR11_QUOT_OFFSET_TUR_SHFT                                     0xf
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_CPR11_SVS2_QUOT_VMIN_BMSK                                   0x7ff8
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_CPR11_SVS2_QUOT_VMIN_SHFT                                      0x3
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_CPR11_SVS_QUOT_VMIN_11_9_BMSK                                  0x7
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_CPR11_SVS_QUOT_VMIN_11_9_SHFT                                  0x0

#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042d0)
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW8_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW8_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_CPR12_TARG_VOLT_SVS2_0_BMSK                             0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_CPR12_TARG_VOLT_SVS2_0_SHFT                                   0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_CPR12_TARG_VOLT_SVS_BMSK                                0x7e000000
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_CPR12_TARG_VOLT_SVS_SHFT                                      0x19
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_CPR12_TARG_VOLT_NOM_BMSK                                 0x1f80000
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_CPR12_TARG_VOLT_NOM_SHFT                                      0x13
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_CPR12_TARG_VOLT_TUR_BMSK                                   0x7e000
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_CPR12_TARG_VOLT_TUR_SHFT                                       0xd
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_CPR11_AGING_BMSK                                            0x1fe0
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_CPR11_AGING_SHFT                                               0x5
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_CPR11_QUOT_OFFSET_SVS_6_2_BMSK                                0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_CPR11_QUOT_OFFSET_SVS_6_2_SHFT                                 0x0

#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042d4)
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW8_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW8_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_CPR12_SVS_QUOT_VMIN_2_0_BMSK                            0xe0000000
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_CPR12_SVS_QUOT_VMIN_2_0_SHFT                                  0x1d
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_CPR12_NOMINAL_QUOT_VMIN_BMSK                            0x1ffe0000
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_CPR12_NOMINAL_QUOT_VMIN_SHFT                                  0x11
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_CPR12_TURBO_QUOT_VMIN_BMSK                                 0x1ffe0
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_CPR12_TURBO_QUOT_VMIN_SHFT                                     0x5
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_CPR12_TARG_VOLT_SVS2_5_1_BMSK                                 0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_CPR12_TARG_VOLT_SVS2_5_1_SHFT                                  0x0

#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042d8)
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW9_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW9_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_CPR12_QUOT_OFFSET_NOM_2_0_BMSK                          0xe0000000
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_CPR12_QUOT_OFFSET_NOM_2_0_SHFT                                0x1d
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_CPR12_QUOT_OFFSET_TUR_BMSK                              0x1fe00000
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_CPR12_QUOT_OFFSET_TUR_SHFT                                    0x15
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_CPR12_SVS2_QUOT_VMIN_BMSK                                 0x1ffe00
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_CPR12_SVS2_QUOT_VMIN_SHFT                                      0x9
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_CPR12_SVS_QUOT_VMIN_11_3_BMSK                                0x1ff
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_CPR12_SVS_QUOT_VMIN_11_3_SHFT                                  0x0

#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042dc)
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW9_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW9_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR13_TARG_VOLT_SUT_0_BMSK                              0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR13_TARG_VOLT_SUT_0_SHFT                                    0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR13_SVS2_ROSEL_BMSK                                   0x78000000
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR13_SVS2_ROSEL_SHFT                                         0x1b
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR13_SVS_ROSEL_BMSK                                     0x7800000
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR13_SVS_ROSEL_SHFT                                          0x17
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR13_NOMINAL_ROSEL_BMSK                                  0x780000
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR13_NOMINAL_ROSEL_SHFT                                      0x13
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR13_TURBO_ROSEL_BMSK                                     0x78000
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR13_TURBO_ROSEL_SHFT                                         0xf
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR13_STURBO_ROSEL_BMSK                                     0x7800
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR13_STURBO_ROSEL_SHFT                                        0xb
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR12_QUOT_OFFSET_SVS_BMSK                                   0x7f0
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR12_QUOT_OFFSET_SVS_SHFT                                     0x4
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR12_QUOT_OFFSET_NOM_6_3_BMSK                                 0xf
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR12_QUOT_OFFSET_NOM_6_3_SHFT                                 0x0

#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042e0)
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW10_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW10_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_CPR13_SUT_QUOT_VMIN_2_0_BMSK                           0xe0000000
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_CPR13_SUT_QUOT_VMIN_2_0_SHFT                                 0x1d
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_CPR13_TARG_VOLT_SVS2_BMSK                              0x1f800000
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_CPR13_TARG_VOLT_SVS2_SHFT                                    0x17
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_CPR13_TARG_VOLT_SVS_BMSK                                 0x7e0000
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_CPR13_TARG_VOLT_SVS_SHFT                                     0x11
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_CPR13_TARG_VOLT_NOM_BMSK                                  0x1f800
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_CPR13_TARG_VOLT_NOM_SHFT                                      0xb
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_CPR13_TARG_VOLT_TUR_BMSK                                    0x7e0
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_CPR13_TARG_VOLT_TUR_SHFT                                      0x5
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_CPR13_TARG_VOLT_SUT_5_1_BMSK                                 0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_CPR13_TARG_VOLT_SUT_5_1_SHFT                                  0x0

#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042e4)
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW10_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW10_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_CPR13_NOMINAL_QUOT_VMIN_10_0_BMSK                      0xffe00000
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_CPR13_NOMINAL_QUOT_VMIN_10_0_SHFT                            0x15
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_CPR13_TURBO_QUOT_VMIN_BMSK                               0x1ffe00
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_CPR13_TURBO_QUOT_VMIN_SHFT                                    0x9
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_CPR13_SUT_QUOT_VMIN_11_3_BMSK                               0x1ff
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_CPR13_SUT_QUOT_VMIN_11_3_SHFT                                 0x0

#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042e8)
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW11_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW11_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_CPR13_QUOT_OFFSET_SUT_6_0_BMSK                         0xfe000000
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_CPR13_QUOT_OFFSET_SUT_6_0_SHFT                               0x19
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_CPR13_SVS2_QUOT_VMIN_BMSK                               0x1ffe000
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_CPR13_SVS2_QUOT_VMIN_SHFT                                     0xd
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_CPR13_SVS_QUOT_VMIN_BMSK                                   0x1ffe
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_CPR13_SVS_QUOT_VMIN_SHFT                                      0x1
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_CPR13_NOMINAL_QUOT_VMIN_11_BMSK                               0x1
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_CPR13_NOMINAL_QUOT_VMIN_11_SHFT                               0x0

#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042ec)
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW11_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW11_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_CPR14_TARG_VOLT_TUR_0_BMSK                             0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_CPR14_TARG_VOLT_TUR_0_SHFT                                   0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_CPR13_AGING_BMSK                                       0x7f800000
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_CPR13_AGING_SHFT                                             0x17
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_CPR13_QUOT_OFFSET_SVS_BMSK                               0x7f0000
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_CPR13_QUOT_OFFSET_SVS_SHFT                                   0x10
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_CPR13_QUOT_OFFSET_NOM_BMSK                                 0xfe00
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_CPR13_QUOT_OFFSET_NOM_SHFT                                    0x9
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_CPR13_QUOT_OFFSET_TUR_BMSK                                  0x1fe
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_CPR13_QUOT_OFFSET_TUR_SHFT                                    0x1
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_CPR13_QUOT_OFFSET_SUT_7_BMSK                                  0x1
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_CPR13_QUOT_OFFSET_SUT_7_SHFT                                  0x0

#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042f0)
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW12_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW12_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_CPR14_TURBO_QUOT_VMIN_8_0_BMSK                         0xff800000
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_CPR14_TURBO_QUOT_VMIN_8_0_SHFT                               0x17
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_CPR14_TARG_VOLT_SVS2_BMSK                                0x7e0000
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_CPR14_TARG_VOLT_SVS2_SHFT                                    0x11
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_CPR14_TARG_VOLT_SVS_BMSK                                  0x1f800
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_CPR14_TARG_VOLT_SVS_SHFT                                      0xb
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_CPR14_TARG_VOLT_NOM_BMSK                                    0x7e0
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_CPR14_TARG_VOLT_NOM_SHFT                                      0x5
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_CPR14_TARG_VOLT_TUR_5_1_BMSK                                 0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_CPR14_TARG_VOLT_TUR_5_1_SHFT                                  0x0

#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042f4)
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW12_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW12_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_CPR14_SVS2_QUOT_VMIN_4_0_BMSK                          0xf8000000
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_CPR14_SVS2_QUOT_VMIN_4_0_SHFT                                0x1b
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_CPR14_SVS_QUOT_VMIN_BMSK                                0x7ff8000
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_CPR14_SVS_QUOT_VMIN_SHFT                                      0xf
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_CPR14_NOMINAL_QUOT_VMIN_BMSK                               0x7ff8
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_CPR14_NOMINAL_QUOT_VMIN_SHFT                                  0x3
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_CPR14_TURBO_QUOT_VMIN_11_9_BMSK                               0x7
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_CPR14_TURBO_QUOT_VMIN_11_9_SHFT                               0x0

#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042f8)
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW13_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW13_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR_LOCAL_RC_BMSK                                      0xe0000000
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR_LOCAL_RC_SHFT                                            0x1d
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR14_QUOT_OFFSET_SVS_BMSK                             0x1fc00000
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR14_QUOT_OFFSET_SVS_SHFT                                   0x16
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR14_QUOT_OFFSET_NOM_BMSK                               0x3f8000
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR14_QUOT_OFFSET_NOM_SHFT                                    0xf
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR14_QUOT_OFFSET_TUR_BMSK                                 0x7f80
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR14_QUOT_OFFSET_TUR_SHFT                                    0x7
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR14_SVS2_QUOT_VMIN_11_5_BMSK                               0x7f
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_CPR14_SVS2_QUOT_VMIN_11_5_SHFT                                0x0

#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000042fc)
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW13_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW13_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_SPARE_R76_B63_BMSK                                     0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_SPARE_R76_B63_SHFT                                           0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_RESERVED_BMSK                                      0x7f000000
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_RESERVED_SHFT                                            0x18
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_LPI_MX_MODE_DISABLE_BMSK                             0xe00000
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_LPI_MX_MODE_DISABLE_SHFT                                 0x15
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_MX_MODE_DISABLE_BMSK                                 0x1c0000
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_MX_MODE_DISABLE_SHFT                                     0x12
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_MM_MODE_DISABLE_BMSK                                  0x38000
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_MM_MODE_DISABLE_SHFT                                      0xf
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_SSC_CX_MODE_DISABLE_BMSK                               0x7000
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_SSC_CX_MODE_DISABLE_SHFT                                  0xc
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_DDR_MODE_DISABLE_BMSK                                   0xe00
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_DDR_MODE_DISABLE_SHFT                                     0x9
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_GFX_MODE_DISABLE_BMSK                                   0x1c0
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_GFX_MODE_DISABLE_SHFT                                     0x6
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_MSS_MODE_DISABLE_BMSK                                    0x38
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_MSS_MODE_DISABLE_SHFT                                     0x3
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_CX_MODE_DISABLE_BMSK                                      0x7
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_CPR_CX_MODE_DISABLE_SHFT                                      0x0

#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004300)
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW14_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW14_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_TSENS1_BASE1_1_0_BMSK                                  0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_TSENS1_BASE1_1_0_SHFT                                        0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_TSENS0_BASE1_BMSK                                      0x3ff00000
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_TSENS0_BASE1_SHFT                                            0x14
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_TSENS1_BASE0_BMSK                                         0xffc00
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_TSENS1_BASE0_SHFT                                             0xa
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_TSENS0_BASE0_BMSK                                           0x3ff
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_TSENS0_BASE0_SHFT                                             0x0

#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004304)
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW14_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW14_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_TSENS4_OFFSET_3_0_BMSK                                 0xf0000000
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_TSENS4_OFFSET_3_0_SHFT                                       0x1c
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_TSENS3_OFFSET_BMSK                                      0xf800000
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_TSENS3_OFFSET_SHFT                                           0x17
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_TSENS2_OFFSET_BMSK                                       0x7c0000
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_TSENS2_OFFSET_SHFT                                           0x12
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_TSENS1_OFFSET_BMSK                                        0x3e000
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_TSENS1_OFFSET_SHFT                                            0xd
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_TSENS0_OFFSET_BMSK                                         0x1f00
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_TSENS0_OFFSET_SHFT                                            0x8
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_TSENS1_BASE1_9_2_BMSK                                        0xff
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_TSENS1_BASE1_9_2_SHFT                                         0x0

#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004308)
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW15_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW15_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_TSENS11_OFFSET_0_BMSK                                  0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_TSENS11_OFFSET_0_SHFT                                        0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_TSENS10_OFFSET_BMSK                                    0x7c000000
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_TSENS10_OFFSET_SHFT                                          0x1a
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_TSENS9_OFFSET_BMSK                                      0x3e00000
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_TSENS9_OFFSET_SHFT                                           0x15
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_TSENS8_OFFSET_BMSK                                       0x1f0000
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_TSENS8_OFFSET_SHFT                                           0x10
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_TSENS7_OFFSET_BMSK                                         0xf800
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_TSENS7_OFFSET_SHFT                                            0xb
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_TSENS6_OFFSET_BMSK                                          0x7c0
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_TSENS6_OFFSET_SHFT                                            0x6
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_TSENS5_OFFSET_BMSK                                           0x3e
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_TSENS5_OFFSET_SHFT                                            0x1
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_TSENS4_OFFSET_4_BMSK                                          0x1
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_TSENS4_OFFSET_4_SHFT                                          0x0

#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000430c)
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW15_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW15_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_TSENS17_OFFSET_2_0_BMSK                                0xe0000000
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_TSENS17_OFFSET_2_0_SHFT                                      0x1d
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_TSENS16_OFFSET_BMSK                                    0x1f000000
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_TSENS16_OFFSET_SHFT                                          0x18
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_TSENS15_OFFSET_BMSK                                      0xf80000
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_TSENS15_OFFSET_SHFT                                          0x13
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_TSENS14_OFFSET_BMSK                                       0x7c000
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_TSENS14_OFFSET_SHFT                                           0xe
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_TSENS13_OFFSET_BMSK                                        0x3e00
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_TSENS13_OFFSET_SHFT                                           0x9
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_TSENS12_OFFSET_BMSK                                         0x1f0
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_TSENS12_OFFSET_SHFT                                           0x4
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_TSENS11_OFFSET_4_1_BMSK                                       0xf
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_TSENS11_OFFSET_4_1_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004310)
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW16_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW16_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_TSENS23_OFFSET_BMSK                                    0xf8000000
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_TSENS23_OFFSET_SHFT                                          0x1b
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_TSENS22_OFFSET_BMSK                                     0x7c00000
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_TSENS22_OFFSET_SHFT                                          0x16
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_TSENS21_OFFSET_BMSK                                      0x3e0000
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_TSENS21_OFFSET_SHFT                                          0x11
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_TSENS20_OFFSET_BMSK                                       0x1f000
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_TSENS20_OFFSET_SHFT                                           0xc
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_TSENS19_OFFSET_BMSK                                         0xf80
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_TSENS19_OFFSET_SHFT                                           0x7
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_TSENS18_OFFSET_BMSK                                          0x7c
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_TSENS18_OFFSET_SHFT                                           0x2
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_TSENS17_OFFSET_4_3_BMSK                                       0x3
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_TSENS17_OFFSET_4_3_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004314)
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW16_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW16_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B63_BMSK                                     0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B63_SHFT                                           0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B62_BMSK                                     0x40000000
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B62_SHFT                                           0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B61_BMSK                                     0x20000000
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B61_SHFT                                           0x1d
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B60_BMSK                                     0x10000000
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B60_SHFT                                           0x1c
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B59_BMSK                                      0x8000000
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B59_SHFT                                           0x1b
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B58_BMSK                                      0x4000000
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B58_SHFT                                           0x1a
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B57_BMSK                                      0x2000000
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B57_SHFT                                           0x19
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B56_BMSK                                      0x1000000
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B56_SHFT                                           0x18
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B55_BMSK                                       0x800000
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SPARE_R79_B55_SHFT                                           0x17
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_TSENS_CAL_SEL_BMSK                                       0x700000
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_TSENS_CAL_SEL_SHFT                                           0x14
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_TSENS27_OFFSET_BMSK                                       0xf8000
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_TSENS27_OFFSET_SHFT                                           0xf
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_TSENS26_OFFSET_BMSK                                        0x7c00
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_TSENS26_OFFSET_SHFT                                           0xa
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_TSENS25_OFFSET_BMSK                                         0x3e0
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_TSENS25_OFFSET_SHFT                                           0x5
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_TSENS24_OFFSET_BMSK                                          0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_TSENS24_OFFSET_SHFT                                           0x0

#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004318)
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW17_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW17_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW17_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000431c)
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW17_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW17_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW17_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004320)
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW18_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW18_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW18_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004324)
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW18_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW18_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW18_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004328)
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW19_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW19_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW19_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000432c)
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW19_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW19_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW19_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004330)
#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW20_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW20_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW20_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004334)
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW20_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW20_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW20_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004338)
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW21_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW21_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW21_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000433c)
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW21_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW21_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW21_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004340)
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW22_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW22_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW22_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004344)
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW22_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW22_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW22_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004348)
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW23_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW23_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW23_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000434c)
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW23_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW23_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW23_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004350)
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW24_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW24_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW24_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004354)
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW24_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW24_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW24_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004358)
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW25_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW25_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW25_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000435c)
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW25_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW25_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW25_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW26_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004360)
#define HWIO_QFPROM_CORR_CALIB_ROW26_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW26_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW26_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW26_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW26_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW26_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW26_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW26_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004364)
#define HWIO_QFPROM_CORR_CALIB_ROW26_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW26_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW26_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW26_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW26_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW26_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW26_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW27_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004368)
#define HWIO_QFPROM_CORR_CALIB_ROW27_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW27_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW27_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW27_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW27_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW27_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW27_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW27_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000436c)
#define HWIO_QFPROM_CORR_CALIB_ROW27_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW27_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW27_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW27_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW27_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW27_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW27_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW28_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004370)
#define HWIO_QFPROM_CORR_CALIB_ROW28_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW28_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW28_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW28_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW28_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW28_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW28_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW28_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004374)
#define HWIO_QFPROM_CORR_CALIB_ROW28_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW28_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW28_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW28_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW28_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW28_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW28_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW29_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004378)
#define HWIO_QFPROM_CORR_CALIB_ROW29_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW29_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW29_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW29_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW29_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW29_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW29_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW29_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000437c)
#define HWIO_QFPROM_CORR_CALIB_ROW29_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW29_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW29_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW29_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW29_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW29_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW29_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW30_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004380)
#define HWIO_QFPROM_CORR_CALIB_ROW30_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW30_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW30_LSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW30_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW30_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW30_LSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW30_LSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW30_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004384)
#define HWIO_QFPROM_CORR_CALIB_ROW30_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW30_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_CALIB_ROW30_MSB_ADDR)
#define HWIO_QFPROM_CORR_CALIB_ROW30_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW30_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW30_MSB_RSVD_BMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW30_MSB_RSVD_SHFT                                                     0x0

#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_ADDR(n)                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004388 + 0x8 * (n))
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_MAXn                                                       70
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_REDUN_DATA_BMSK                                    0xffffffff
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_REDUN_DATA_SHFT                                           0x0

#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_ADDR(n)                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000438c + 0x8 * (n))
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_MAXn                                                       70
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_REDUN_DATA_BMSK                                    0xffffffff
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_REDUN_DATA_SHFT                                           0x0

#define HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045c0)
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_ADDR)
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_QC_SPARE_BMSK                                       0xffffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_LSB_QC_SPARE_SHFT                                              0x0

#define HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045c4)
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_RMSK                                                  0xffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_ADDR)
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_QC_SPARE_BMSK                                         0xffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REG20_MSB_QC_SPARE_SHFT                                              0x0

#define HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045c8)
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_ADDR)
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_QC_SPARE_BMSK                                       0xffffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_LSB_QC_SPARE_SHFT                                              0x0

#define HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045cc)
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_RMSK                                                  0xffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_ADDR)
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_QC_SPARE_BMSK                                         0xffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REG21_MSB_QC_SPARE_SHFT                                              0x0

#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n)                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045d0 + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_RMSK                                       0xffffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_MAXn                                                1
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_KEY_DATA0_BMSK                             0xffffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_KEY_DATA0_SHFT                                    0x0

#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n)                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045d4 + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RMSK                                         0xffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_MAXn                                                1
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_KEY_DATA1_BMSK                               0xffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_KEY_DATA1_SHFT                                    0x0

#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045e0)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RMSK                                       0xffffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RSVD0_BMSK                                 0xffff0000
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RSVD0_SHFT                                       0x10
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_KEY_DATA0_BMSK                                 0xffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_KEY_DATA0_SHFT                                    0x0

#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045e4)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RMSK                                         0xffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD0_BMSK                                   0xffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD0_SHFT                                        0x0

#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_ADDR(n)                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045e8 + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_MAXn                                                      1
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT4_BMSK                                   0xff000000
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT4_SHFT                                         0x18
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT3_BMSK                                     0xff0000
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT3_SHFT                                         0x10
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT2_BMSK                                       0xff00
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT2_SHFT                                          0x8
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT1_BMSK                                         0xff
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT1_SHFT                                          0x0

#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_ADDR(n)                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045ec + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_RMSK                                               0xffffff
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_MAXn                                                      1
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT7_BMSK                                     0xff0000
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT7_SHFT                                         0x10
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT6_BMSK                                       0xff00
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT6_SHFT                                          0x8
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT5_BMSK                                         0xff
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT5_SHFT                                          0x0

#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n)                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045f8 + 0x8 * (n))
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_RMSK                                   0xffffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_MAXn                                            3
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_BMSK                         0xffffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_SHFT                                0x0

#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n)                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000045fc + 0x8 * (n))
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RMSK                                     0xffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_MAXn                                            3
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_BMSK                           0xffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_SHFT                                0x0

#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004618)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_RMSK                                   0xffffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_KEY_DATA0_BMSK                         0xffffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_KEY_DATA0_SHFT                                0x0

#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000461c)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RMSK                                     0xffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_BMSK                               0xffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_SHFT                                    0x0

#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_ADDR(n)                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004620 + 0x8 * (n))
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_MAXn                                                        55
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_PATCH_DATA_BMSK                                     0xffffffff
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_PATCH_DATA_SHFT                                            0x0

#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_ADDR(n)                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004624 + 0x8 * (n))
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_RMSK                                                  0xffffff
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_MAXn                                                        55
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_RSVD0_BMSK                                            0xfe0000
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_RSVD0_SHFT                                                0x11
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_PATCH_ADDR_BMSK                                        0x1fffe
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_PATCH_ADDR_SHFT                                            0x1
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_PATCH_EN_BMSK                                              0x1
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_PATCH_EN_SHFT                                              0x0

#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n)                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000047e0 + 0x8 * (n))
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_MAXn                                                   1
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_KEY_DATA0_BMSK                                0xffffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_KEY_DATA0_SHFT                                       0x0

#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n)                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x000047e4 + 0x8 * (n))
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_RMSK                                            0xffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_MAXn                                                   1
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_KEY_DATA1_BMSK                                  0xffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_KEY_DATA1_SHFT                                       0x0

#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x000047f0)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_RSVD0_BMSK                                    0xffff0000
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_RSVD0_SHFT                                          0x10
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_KEY_DATA0_BMSK                                    0xffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_KEY_DATA0_SHFT                                       0x0

#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x000047f4)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_RMSK                                            0xffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD0_BMSK                                      0xffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD0_SHFT                                           0x0

#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_ADDR(n)                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x000047f8 + 0x8 * (n))
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_MAXn                                                     3
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_USER_DATA_KEY_BMSK                              0xffffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_USER_DATA_KEY_SHFT                                     0x0

#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_ADDR(n)                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x000047fc + 0x8 * (n))
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_RMSK                                              0xffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_MAXn                                                     3
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_USER_DATA_KEY_BMSK                                0xffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_USER_DATA_KEY_SHFT                                     0x0

#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004818)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_IN          \
        in_dword(HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_ADDR)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_USER_DATA_KEY_BMSK                              0xffffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_USER_DATA_KEY_SHFT                                     0x0

#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000481c)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_RMSK                                              0xffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_IN          \
        in_dword(HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_ADDR)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_RSVD0_BMSK                                        0xffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_RSVD0_SHFT                                             0x0

#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004660 + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_MAXn                                                   31
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_OEM_SPARE_BMSK                                 0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_OEM_SPARE_SHFT                                        0x0

#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004664 + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_MAXn                                                   31
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_OEM_SPARE_BMSK                                 0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_OEM_SPARE_SHFT                                        0x0

#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004668 + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_MAXn                                                   31
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_OEM_SPARE_BMSK                                 0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_OEM_SPARE_SHFT                                        0x0

#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000466c + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_MAXn                                                   31
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_OEM_SPARE_BMSK                                 0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_OEM_SPARE_SHFT                                        0x0

#define HWIO_SEC_CTRL_HW_VERSION_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006000)
#define HWIO_SEC_CTRL_HW_VERSION_RMSK                                                           0xffffffff
#define HWIO_SEC_CTRL_HW_VERSION_IN          \
        in_dword(HWIO_SEC_CTRL_HW_VERSION_ADDR)
#define HWIO_SEC_CTRL_HW_VERSION_INM(m)      \
        in_dword_masked(HWIO_SEC_CTRL_HW_VERSION_ADDR, m)
#define HWIO_SEC_CTRL_HW_VERSION_MAJOR_BMSK                                                     0xf0000000
#define HWIO_SEC_CTRL_HW_VERSION_MAJOR_SHFT                                                           0x1c
#define HWIO_SEC_CTRL_HW_VERSION_MINOR_BMSK                                                      0xfff0000
#define HWIO_SEC_CTRL_HW_VERSION_MINOR_SHFT                                                           0x10
#define HWIO_SEC_CTRL_HW_VERSION_STEP_BMSK                                                          0xffff
#define HWIO_SEC_CTRL_HW_VERSION_STEP_SHFT                                                             0x0

#define HWIO_FEATURE_CONFIG0_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006004)
#define HWIO_FEATURE_CONFIG0_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG0_IN          \
        in_dword(HWIO_FEATURE_CONFIG0_ADDR)
#define HWIO_FEATURE_CONFIG0_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG0_ADDR, m)
#define HWIO_FEATURE_CONFIG0_RSVD1_BMSK                                                         0x80000000
#define HWIO_FEATURE_CONFIG0_RSVD1_SHFT                                                               0x1f
#define HWIO_FEATURE_CONFIG0_TURING_Q6SS_HVX_DISABLE_BMSK                                       0x40000000
#define HWIO_FEATURE_CONFIG0_TURING_Q6SS_HVX_DISABLE_SHFT                                             0x1e
#define HWIO_FEATURE_CONFIG0_QC_SP_DISABLE_BMSK                                                 0x20000000
#define HWIO_FEATURE_CONFIG0_QC_SP_DISABLE_SHFT                                                       0x1d
#define HWIO_FEATURE_CONFIG0_GFX3D_FREQ_LIMIT_VAL_BMSK                                          0x1fe00000
#define HWIO_FEATURE_CONFIG0_GFX3D_FREQ_LIMIT_VAL_SHFT                                                0x15
#define HWIO_FEATURE_CONFIG0_MDSS_RESOLUTION_LIMIT_BMSK                                           0x180000
#define HWIO_FEATURE_CONFIG0_MDSS_RESOLUTION_LIMIT_SHFT                                               0x13
#define HWIO_FEATURE_CONFIG0_IRIS_HEVC_ENCODE_DISABLE_BMSK                                         0x40000
#define HWIO_FEATURE_CONFIG0_IRIS_HEVC_ENCODE_DISABLE_SHFT                                            0x12
#define HWIO_FEATURE_CONFIG0_IRIS_HEVC_DECODE_DISABLE_BMSK                                         0x20000
#define HWIO_FEATURE_CONFIG0_IRIS_HEVC_DECODE_DISABLE_SHFT                                            0x11
#define HWIO_FEATURE_CONFIG0_IRIS_4K_DISABLE_BMSK                                                  0x10000
#define HWIO_FEATURE_CONFIG0_IRIS_4K_DISABLE_SHFT                                                     0x10
#define HWIO_FEATURE_CONFIG0_IRIS_CVP_DISABLE_BMSK                                                  0x8000
#define HWIO_FEATURE_CONFIG0_IRIS_CVP_DISABLE_SHFT                                                     0xf
#define HWIO_FEATURE_CONFIG0_IRIS_DISABLE_VPX_BMSK                                                  0x4000
#define HWIO_FEATURE_CONFIG0_IRIS_DISABLE_VPX_SHFT                                                     0xe
#define HWIO_FEATURE_CONFIG0_DP_DISABLE_BMSK                                                        0x2000
#define HWIO_FEATURE_CONFIG0_DP_DISABLE_SHFT                                                           0xd
#define HWIO_FEATURE_CONFIG0_HDCP_DISABLE_BMSK                                                      0x1000
#define HWIO_FEATURE_CONFIG0_HDCP_DISABLE_SHFT                                                         0xc
#define HWIO_FEATURE_CONFIG0_MDP_APICAL_LTC_DISABLE_BMSK                                             0x800
#define HWIO_FEATURE_CONFIG0_MDP_APICAL_LTC_DISABLE_SHFT                                               0xb
#define HWIO_FEATURE_CONFIG0_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK                                     0x400
#define HWIO_FEATURE_CONFIG0_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT                                       0xa
#define HWIO_FEATURE_CONFIG0_DSI_1_DISABLE_BMSK                                                      0x200
#define HWIO_FEATURE_CONFIG0_DSI_1_DISABLE_SHFT                                                        0x9
#define HWIO_FEATURE_CONFIG0_DSI_0_DISABLE_BMSK                                                      0x100
#define HWIO_FEATURE_CONFIG0_DSI_0_DISABLE_SHFT                                                        0x8
#define HWIO_FEATURE_CONFIG0_FD_DISABLE_BMSK                                                          0x80
#define HWIO_FEATURE_CONFIG0_FD_DISABLE_SHFT                                                           0x7
#define HWIO_FEATURE_CONFIG0_CSID_DPCM_14_DISABLE_BMSK                                                0x40
#define HWIO_FEATURE_CONFIG0_CSID_DPCM_14_DISABLE_SHFT                                                 0x6
#define HWIO_FEATURE_CONFIG0_EFUSE_CAM_SBI_ENABLE_IF_BMSK                                             0x20
#define HWIO_FEATURE_CONFIG0_EFUSE_CAM_SBI_ENABLE_IF_SHFT                                              0x5
#define HWIO_FEATURE_CONFIG0_EUD_PORT1_SEL_BMSK                                                       0x10
#define HWIO_FEATURE_CONFIG0_EUD_PORT1_SEL_SHFT                                                        0x4
#define HWIO_FEATURE_CONFIG0_EUD_IGNR_CSR_BMSK                                                         0x8
#define HWIO_FEATURE_CONFIG0_EUD_IGNR_CSR_SHFT                                                         0x3
#define HWIO_FEATURE_CONFIG0_BOOT_ROM_PATCH_DISABLE_BMSK                                               0x7
#define HWIO_FEATURE_CONFIG0_BOOT_ROM_PATCH_DISABLE_SHFT                                               0x0

#define HWIO_FEATURE_CONFIG1_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006008)
#define HWIO_FEATURE_CONFIG1_RMSK                                                               0xe7fffff7
#define HWIO_FEATURE_CONFIG1_IN          \
        in_dword(HWIO_FEATURE_CONFIG1_ADDR)
#define HWIO_FEATURE_CONFIG1_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG1_ADDR, m)
#define HWIO_FEATURE_CONFIG1_ICE_FORCE_HW_KEY1_BMSK                                             0x80000000
#define HWIO_FEATURE_CONFIG1_ICE_FORCE_HW_KEY1_SHFT                                                   0x1f
#define HWIO_FEATURE_CONFIG1_ICE_FORCE_HW_KEY0_BMSK                                             0x40000000
#define HWIO_FEATURE_CONFIG1_ICE_FORCE_HW_KEY0_SHFT                                                   0x1e
#define HWIO_FEATURE_CONFIG1_ICE_DISABLE_BMSK                                                   0x20000000
#define HWIO_FEATURE_CONFIG1_ICE_DISABLE_SHFT                                                         0x1d
#define HWIO_FEATURE_CONFIG1_SSC_DISABLE_BMSK                                                    0x4000000
#define HWIO_FEATURE_CONFIG1_SSC_DISABLE_SHFT                                                         0x1a
#define HWIO_FEATURE_CONFIG1_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK                                 0x2000000
#define HWIO_FEATURE_CONFIG1_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT                                      0x19
#define HWIO_FEATURE_CONFIG1_SSC_SW_ISLAND_MODE_DISABLE_BMSK                                     0x1000000
#define HWIO_FEATURE_CONFIG1_SSC_SW_ISLAND_MODE_DISABLE_SHFT                                          0x18
#define HWIO_FEATURE_CONFIG1_TCSR_SW_OVERRIDE_SOC_HW_VER_BMSK                                     0x800000
#define HWIO_FEATURE_CONFIG1_TCSR_SW_OVERRIDE_SOC_HW_VER_SHFT                                         0x17
#define HWIO_FEATURE_CONFIG1_APS_RESET_DISABLE_BMSK                                               0x400000
#define HWIO_FEATURE_CONFIG1_APS_RESET_DISABLE_SHFT                                                   0x16
#define HWIO_FEATURE_CONFIG1_IRIS_MULTIPIPE_DISABLE_BMSK                                          0x200000
#define HWIO_FEATURE_CONFIG1_IRIS_MULTIPIPE_DISABLE_SHFT                                              0x15
#define HWIO_FEATURE_CONFIG1_DOLBY_BIT_BMSK                                                       0x100000
#define HWIO_FEATURE_CONFIG1_DOLBY_BIT_SHFT                                                           0x14
#define HWIO_FEATURE_CONFIG1_QC_UDK_DISABLE_BMSK                                                   0x80000
#define HWIO_FEATURE_CONFIG1_QC_UDK_DISABLE_SHFT                                                      0x13
#define HWIO_FEATURE_CONFIG1_STACKED_MEMORY_ID_BMSK                                                0x7c000
#define HWIO_FEATURE_CONFIG1_STACKED_MEMORY_ID_SHFT                                                    0xe
#define HWIO_FEATURE_CONFIG1_PRNG_TESTMODE_DISABLE_BMSK                                             0x2000
#define HWIO_FEATURE_CONFIG1_PRNG_TESTMODE_DISABLE_SHFT                                                0xd
#define HWIO_FEATURE_CONFIG1_MDSS_Q_CONFIG_FUSE_BMSK                                                0x1000
#define HWIO_FEATURE_CONFIG1_MDSS_Q_CONFIG_FUSE_SHFT                                                   0xc
#define HWIO_FEATURE_CONFIG1_MOCHA_PART_BMSK                                                         0x800
#define HWIO_FEATURE_CONFIG1_MOCHA_PART_SHFT                                                           0xb
#define HWIO_FEATURE_CONFIG1_EFUSE_Q6SS_HVX_HALF_BMSK                                                0x400
#define HWIO_FEATURE_CONFIG1_EFUSE_Q6SS_HVX_HALF_SHFT                                                  0xa
#define HWIO_FEATURE_CONFIG1_SMMU_DISABLE_BMSK                                                       0x200
#define HWIO_FEATURE_CONFIG1_SMMU_DISABLE_SHFT                                                         0x9
#define HWIO_FEATURE_CONFIG1_VENDOR_LOCK_BMSK                                                        0x1e0
#define HWIO_FEATURE_CONFIG1_VENDOR_LOCK_SHFT                                                          0x5
#define HWIO_FEATURE_CONFIG1_CM_FEAT_CONFIG_DISABLE_BMSK                                              0x10
#define HWIO_FEATURE_CONFIG1_CM_FEAT_CONFIG_DISABLE_SHFT                                               0x4
#define HWIO_FEATURE_CONFIG1_PCIE_2_DISABLE_BMSK                                                       0x4
#define HWIO_FEATURE_CONFIG1_PCIE_2_DISABLE_SHFT                                                       0x2
#define HWIO_FEATURE_CONFIG1_PCIE_1_DISABLE_BMSK                                                       0x2
#define HWIO_FEATURE_CONFIG1_PCIE_1_DISABLE_SHFT                                                       0x1
#define HWIO_FEATURE_CONFIG1_PCIE_0_DISABLE_BMSK                                                       0x1
#define HWIO_FEATURE_CONFIG1_PCIE_0_DISABLE_SHFT                                                       0x0

#define HWIO_FEATURE_CONFIG2_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000600c)
#define HWIO_FEATURE_CONFIG2_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG2_IN          \
        in_dword(HWIO_FEATURE_CONFIG2_ADDR)
#define HWIO_FEATURE_CONFIG2_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG2_ADDR, m)
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_HARD_BMSK                                    0xffffc000
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_HARD_SHFT                                           0xe
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_IU_BMSK                                          0x3c00
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_IU_SHFT                                             0xa
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_SPARE_BMSK                                        0x3ff
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_SPARE_SHFT                                          0x0

#define HWIO_FEATURE_CONFIG3_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006010)
#define HWIO_FEATURE_CONFIG3_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG3_IN          \
        in_dword(HWIO_FEATURE_CONFIG3_ADDR)
#define HWIO_FEATURE_CONFIG3_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG3_ADDR, m)
#define HWIO_FEATURE_CONFIG3_APSS_PDXWRPNTRDELAY_BMSK                                           0xc0000000
#define HWIO_FEATURE_CONFIG3_APSS_PDXWRPNTRDELAY_SHFT                                                 0x1e
#define HWIO_FEATURE_CONFIG3_SEC_CTRL_GCC_NPU_FUSE_DISABLE_BMSK                                 0x20000000
#define HWIO_FEATURE_CONFIG3_SEC_CTRL_GCC_NPU_FUSE_DISABLE_SHFT                                       0x1d
#define HWIO_FEATURE_CONFIG3_AUTOMOTIVE_BIT_FUNCTIONAL_BMSK                                     0x10000000
#define HWIO_FEATURE_CONFIG3_AUTOMOTIVE_BIT_FUNCTIONAL_SHFT                                           0x1c
#define HWIO_FEATURE_CONFIG3_AUTOMOTIVE_BIT_POWER_BMSK                                           0x8000000
#define HWIO_FEATURE_CONFIG3_AUTOMOTIVE_BIT_POWER_SHFT                                                0x1b
#define HWIO_FEATURE_CONFIG3_EMAC_DISABLE_BMSK                                                   0x4000000
#define HWIO_FEATURE_CONFIG3_EMAC_DISABLE_SHFT                                                        0x1a
#define HWIO_FEATURE_CONFIG3_MODEM_TCM_BOOT_DISABLE_BMSK                                         0x2000000
#define HWIO_FEATURE_CONFIG3_MODEM_TCM_BOOT_DISABLE_SHFT                                              0x19
#define HWIO_FEATURE_CONFIG3_NAV_DISABLE_BMSK                                                    0x1000000
#define HWIO_FEATURE_CONFIG3_NAV_DISABLE_SHFT                                                         0x18
#define HWIO_FEATURE_CONFIG3_MODEM_FEATURE_DISABLE_SOFT_BMSK                                      0xffffff
#define HWIO_FEATURE_CONFIG3_MODEM_FEATURE_DISABLE_SOFT_SHFT                                           0x0

#define HWIO_FEATURE_CONFIG4_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006014)
#define HWIO_FEATURE_CONFIG4_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG4_IN          \
        in_dword(HWIO_FEATURE_CONFIG4_ADDR)
#define HWIO_FEATURE_CONFIG4_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG4_ADDR, m)
#define HWIO_FEATURE_CONFIG4_P2S_ACCU_RED_DEC_END_VAL_FUSE0_BMSK                                0x80000000
#define HWIO_FEATURE_CONFIG4_P2S_ACCU_RED_DEC_END_VAL_FUSE0_SHFT                                      0x1f
#define HWIO_FEATURE_CONFIG4_FUSE_CORTEX_M3_DISABLE_BMSK                                        0x40000000
#define HWIO_FEATURE_CONFIG4_FUSE_CORTEX_M3_DISABLE_SHFT                                              0x1e
#define HWIO_FEATURE_CONFIG4_Q_CONFIG_FUSE_BMSK                                                 0x20000000
#define HWIO_FEATURE_CONFIG4_Q_CONFIG_FUSE_SHFT                                                       0x1d
#define HWIO_FEATURE_CONFIG4_I_MC5_FUSE_BMSK                                                    0x10000000
#define HWIO_FEATURE_CONFIG4_I_MC5_FUSE_SHFT                                                          0x1c
#define HWIO_FEATURE_CONFIG4_I_MC4_FUSE_BMSK                                                     0x8000000
#define HWIO_FEATURE_CONFIG4_I_MC4_FUSE_SHFT                                                          0x1b
#define HWIO_FEATURE_CONFIG4_RSVD_BMSK                                                           0x4000000
#define HWIO_FEATURE_CONFIG4_RSVD_SHFT                                                                0x1a
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC5_DEBUG_DISABLE_BMSK                                  0x2000000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC5_DEBUG_DISABLE_SHFT                                       0x19
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC4_DEBUG_DISABLE_BMSK                                  0x1000000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC4_DEBUG_DISABLE_SHFT                                       0x18
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC3_DEBUG_DISABLE_BMSK                                   0x800000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC3_DEBUG_DISABLE_SHFT                                       0x17
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC2_DEBUG_DISABLE_BMSK                                   0x400000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC2_DEBUG_DISABLE_SHFT                                       0x16
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC1_DEBUG_DISABLE_BMSK                                   0x200000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC1_DEBUG_DISABLE_SHFT                                       0x15
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC_DEBUG_DISABLE_BMSK                                    0x100000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MISC_DEBUG_DISABLE_SHFT                                        0x14
#define HWIO_FEATURE_CONFIG4_QC_APPS_NIDEN_DISABLE_BMSK                                            0x80000
#define HWIO_FEATURE_CONFIG4_QC_APPS_NIDEN_DISABLE_SHFT                                               0x13
#define HWIO_FEATURE_CONFIG4_QC_APPS_DBGEN_DISABLE_BMSK                                            0x40000
#define HWIO_FEATURE_CONFIG4_QC_APPS_DBGEN_DISABLE_SHFT                                               0x12
#define HWIO_FEATURE_CONFIG4_QC_SHARED_NS_NIDEN_DISABLE_BMSK                                       0x20000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_NS_NIDEN_DISABLE_SHFT                                          0x11
#define HWIO_FEATURE_CONFIG4_QC_SHARED_NS_DBGEN_DISABLE_BMSK                                       0x10000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_NS_DBGEN_DISABLE_SHFT                                          0x10
#define HWIO_FEATURE_CONFIG4_QC_SHARED_CP_NIDEN_DISABLE_BMSK                                        0x8000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_CP_NIDEN_DISABLE_SHFT                                           0xf
#define HWIO_FEATURE_CONFIG4_QC_SHARED_CP_DBGEN_DISABLE_BMSK                                        0x4000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_CP_DBGEN_DISABLE_SHFT                                           0xe
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MSS_NIDEN_DISABLE_BMSK                                       0x2000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MSS_NIDEN_DISABLE_SHFT                                          0xd
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MSS_DBGEN_DISABLE_BMSK                                       0x1000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MSS_DBGEN_DISABLE_SHFT                                          0xc
#define HWIO_FEATURE_CONFIG4_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                                     0x800
#define HWIO_FEATURE_CONFIG4_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                                       0xb
#define HWIO_FEATURE_CONFIG4_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK                                      0x400
#define HWIO_FEATURE_CONFIG4_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT                                        0xa
#define HWIO_FEATURE_CONFIG4_PRIVATE_NS_NIDEN_DISABLE_BMSK                                           0x200
#define HWIO_FEATURE_CONFIG4_PRIVATE_NS_NIDEN_DISABLE_SHFT                                             0x9
#define HWIO_FEATURE_CONFIG4_PRIVATE_NS_DBGEN_DISABLE_BMSK                                           0x100
#define HWIO_FEATURE_CONFIG4_PRIVATE_NS_DBGEN_DISABLE_SHFT                                             0x8
#define HWIO_FEATURE_CONFIG4_PRIVATE_CP_NIDEN_DISABLE_BMSK                                            0x80
#define HWIO_FEATURE_CONFIG4_PRIVATE_CP_NIDEN_DISABLE_SHFT                                             0x7
#define HWIO_FEATURE_CONFIG4_PRIVATE_CP_DBGEN_DISABLE_BMSK                                            0x40
#define HWIO_FEATURE_CONFIG4_PRIVATE_CP_DBGEN_DISABLE_SHFT                                             0x6
#define HWIO_FEATURE_CONFIG4_PRIVATE_MSS_NIDEN_DISABLE_BMSK                                           0x20
#define HWIO_FEATURE_CONFIG4_PRIVATE_MSS_NIDEN_DISABLE_SHFT                                            0x5
#define HWIO_FEATURE_CONFIG4_PRIVATE_MSS_DBGEN_DISABLE_BMSK                                           0x10
#define HWIO_FEATURE_CONFIG4_PRIVATE_MSS_DBGEN_DISABLE_SHFT                                            0x4
#define HWIO_FEATURE_CONFIG4_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK                                         0x8
#define HWIO_FEATURE_CONFIG4_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT                                         0x3
#define HWIO_FEATURE_CONFIG4_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK                                          0x4
#define HWIO_FEATURE_CONFIG4_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT                                          0x2
#define HWIO_FEATURE_CONFIG4_SM_BIST_DISABLE_BMSK                                                      0x2
#define HWIO_FEATURE_CONFIG4_SM_BIST_DISABLE_SHFT                                                      0x1
#define HWIO_FEATURE_CONFIG4_TIC_DISABLE_BMSK                                                          0x1
#define HWIO_FEATURE_CONFIG4_TIC_DISABLE_SHFT                                                          0x0

#define HWIO_FEATURE_CONFIG5_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006018)
#define HWIO_FEATURE_CONFIG5_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG5_IN          \
        in_dword(HWIO_FEATURE_CONFIG5_ADDR)
#define HWIO_FEATURE_CONFIG5_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG5_ADDR, m)
#define HWIO_FEATURE_CONFIG5_SYS_CFG_APC1PLL_LVAL_BMSK                                          0xff000000
#define HWIO_FEATURE_CONFIG5_SYS_CFG_APC1PLL_LVAL_SHFT                                                0x18
#define HWIO_FEATURE_CONFIG5_APSS_KRYO_PP_DISABLE_BMSK                                            0x800000
#define HWIO_FEATURE_CONFIG5_APSS_KRYO_PP_DISABLE_SHFT                                                0x17
#define HWIO_FEATURE_CONFIG5_SYS_CFG_L3_SIZE_RED_BMSK                                             0x400000
#define HWIO_FEATURE_CONFIG5_SYS_CFG_L3_SIZE_RED_SHFT                                                 0x16
#define HWIO_FEATURE_CONFIG5_AUTO_CCI_RCG_CFG_DISABLE_BMSK                                        0x200000
#define HWIO_FEATURE_CONFIG5_AUTO_CCI_RCG_CFG_DISABLE_SHFT                                            0x15
#define HWIO_FEATURE_CONFIG5_APPS_BOOT_FSM_FUSE_BMSK                                              0x1f8000
#define HWIO_FEATURE_CONFIG5_APPS_BOOT_FSM_FUSE_SHFT                                                   0xf
#define HWIO_FEATURE_CONFIG5_SYS_APCSCFGAPMBOOTONMX_BMSK                                            0x4000
#define HWIO_FEATURE_CONFIG5_SYS_APCSCFGAPMBOOTONMX_SHFT                                               0xe
#define HWIO_FEATURE_CONFIG5_SYS_APCCCFGCPUPRESENT_N_BMSK                                           0x3fc0
#define HWIO_FEATURE_CONFIG5_SYS_APCCCFGCPUPRESENT_N_SHFT                                              0x6
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE6_BMSK                                      0x20
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE6_SHFT                                       0x5
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE5_BMSK                                      0x10
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE5_SHFT                                       0x4
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE4_BMSK                                       0x8
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE4_SHFT                                       0x3
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE3_BMSK                                       0x4
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE3_SHFT                                       0x2
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE2_BMSK                                       0x2
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE2_SHFT                                       0x1
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE1_BMSK                                       0x1
#define HWIO_FEATURE_CONFIG5_P2S_ACCU_RED_DEC_END_VAL_FUSE1_SHFT                                       0x0

#define HWIO_FEATURE_CONFIG6_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000601c)
#define HWIO_FEATURE_CONFIG6_RMSK                                                               0x807fffff
#define HWIO_FEATURE_CONFIG6_IN          \
        in_dword(HWIO_FEATURE_CONFIG6_ADDR)
#define HWIO_FEATURE_CONFIG6_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG6_ADDR, m)
#define HWIO_FEATURE_CONFIG6_RSVD1_BMSK                                                         0x80000000
#define HWIO_FEATURE_CONFIG6_RSVD1_SHFT                                                               0x1f
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_6_BMSK                                          0x400000
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_6_SHFT                                              0x16
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_5_BMSK                                          0x200000
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_5_SHFT                                              0x15
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_4_BMSK                                          0x100000
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_4_SHFT                                              0x14
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_3_BMSK                                           0x80000
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_3_SHFT                                              0x13
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_2_BMSK                                           0x40000
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_2_SHFT                                              0x12
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_1_BMSK                                           0x20000
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_1_SHFT                                              0x11
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_0_BMSK                                           0x10000
#define HWIO_FEATURE_CONFIG6_ACCU_RED_DEC_END_VAL_0_SHFT                                              0x10
#define HWIO_FEATURE_CONFIG6_TURING_Q6SS_PLL_L_MAX_BMSK                                             0xffff
#define HWIO_FEATURE_CONFIG6_TURING_Q6SS_PLL_L_MAX_SHFT                                                0x0

#define HWIO_FEATURE_CONFIG7_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006020)
#define HWIO_FEATURE_CONFIG7_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG7_IN          \
        in_dword(HWIO_FEATURE_CONFIG7_ADDR)
#define HWIO_FEATURE_CONFIG7_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG7_ADDR, m)
#define HWIO_FEATURE_CONFIG7_RSVD_BMSK                                                          0xfffffffe
#define HWIO_FEATURE_CONFIG7_RSVD_SHFT                                                                 0x1
#define HWIO_FEATURE_CONFIG7_DISABLE_SEC_BOOT_GPIO_BMSK                                                0x1
#define HWIO_FEATURE_CONFIG7_DISABLE_SEC_BOOT_GPIO_SHFT                                                0x0

#define HWIO_FEATURE_CONFIG8_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006024)
#define HWIO_FEATURE_CONFIG8_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG8_IN          \
        in_dword(HWIO_FEATURE_CONFIG8_ADDR)
#define HWIO_FEATURE_CONFIG8_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG8_ADDR, m)
#define HWIO_FEATURE_CONFIG8_RSVD_BMSK                                                          0xfffffffe
#define HWIO_FEATURE_CONFIG8_RSVD_SHFT                                                                 0x1
#define HWIO_FEATURE_CONFIG8_LEGACY_MBNV6_OVERRIDE_BMSK                                                0x1
#define HWIO_FEATURE_CONFIG8_LEGACY_MBNV6_OVERRIDE_SHFT                                                0x0

#define HWIO_FEATURE_CONFIG9_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006028)
#define HWIO_FEATURE_CONFIG9_RMSK                                                               0xffffffff
#define HWIO_FEATURE_CONFIG9_IN          \
        in_dword(HWIO_FEATURE_CONFIG9_ADDR)
#define HWIO_FEATURE_CONFIG9_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG9_ADDR, m)
#define HWIO_FEATURE_CONFIG9_RSVD_BMSK                                                          0xffffffff
#define HWIO_FEATURE_CONFIG9_RSVD_SHFT                                                                 0x0

#define HWIO_FEATURE_CONFIG10_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000602c)
#define HWIO_FEATURE_CONFIG10_RMSK                                                              0xffffffff
#define HWIO_FEATURE_CONFIG10_IN          \
        in_dword(HWIO_FEATURE_CONFIG10_ADDR)
#define HWIO_FEATURE_CONFIG10_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG10_ADDR, m)
#define HWIO_FEATURE_CONFIG10_RSVD1_BMSK                                                        0xffffffff
#define HWIO_FEATURE_CONFIG10_RSVD1_SHFT                                                               0x0

#define HWIO_FEATURE_CONFIG11_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006030)
#define HWIO_FEATURE_CONFIG11_RMSK                                                              0xffffffff
#define HWIO_FEATURE_CONFIG11_IN          \
        in_dword(HWIO_FEATURE_CONFIG11_ADDR)
#define HWIO_FEATURE_CONFIG11_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG11_ADDR, m)
#define HWIO_FEATURE_CONFIG11_RSVD1_BMSK                                                        0xffffffff
#define HWIO_FEATURE_CONFIG11_RSVD1_SHFT                                                               0x0

#define HWIO_FEATURE_CONFIG12_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006034)
#define HWIO_FEATURE_CONFIG12_RMSK                                                              0xffffffff
#define HWIO_FEATURE_CONFIG12_IN          \
        in_dword(HWIO_FEATURE_CONFIG12_ADDR)
#define HWIO_FEATURE_CONFIG12_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG12_ADDR, m)
#define HWIO_FEATURE_CONFIG12_TAP_GEN_SPARE_INSTR_DISABLE_13_0_BMSK                             0xfffc0000
#define HWIO_FEATURE_CONFIG12_TAP_GEN_SPARE_INSTR_DISABLE_13_0_SHFT                                   0x12
#define HWIO_FEATURE_CONFIG12_TAP_INSTR_DISABLE_BMSK                                               0x3ffff
#define HWIO_FEATURE_CONFIG12_TAP_INSTR_DISABLE_SHFT                                                   0x0

#define HWIO_FEATURE_CONFIG13_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006038)
#define HWIO_FEATURE_CONFIG13_RMSK                                                              0xffffffff
#define HWIO_FEATURE_CONFIG13_IN          \
        in_dword(HWIO_FEATURE_CONFIG13_ADDR)
#define HWIO_FEATURE_CONFIG13_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG13_ADDR, m)
#define HWIO_FEATURE_CONFIG13_SEC_TAP_ACCESS_DISABLE_BMSK                                       0xfffc0000
#define HWIO_FEATURE_CONFIG13_SEC_TAP_ACCESS_DISABLE_SHFT                                             0x12
#define HWIO_FEATURE_CONFIG13_TAP_GEN_SPARE_INSTR_DISABLE_31_14_BMSK                               0x3ffff
#define HWIO_FEATURE_CONFIG13_TAP_GEN_SPARE_INSTR_DISABLE_31_14_SHFT                                   0x0

#define HWIO_FEATURE_CONFIG14_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000603c)
#define HWIO_FEATURE_CONFIG14_RMSK                                                              0xffffffff
#define HWIO_FEATURE_CONFIG14_IN          \
        in_dword(HWIO_FEATURE_CONFIG14_ADDR)
#define HWIO_FEATURE_CONFIG14_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG14_ADDR, m)
#define HWIO_FEATURE_CONFIG14_MODEM_PBL_PATCH_VERSION_BMSK                                      0xfe000000
#define HWIO_FEATURE_CONFIG14_MODEM_PBL_PATCH_VERSION_SHFT                                            0x19
#define HWIO_FEATURE_CONFIG14_APPS_PBL_PATCH_VERSION_BMSK                                        0x1fc0000
#define HWIO_FEATURE_CONFIG14_APPS_PBL_PATCH_VERSION_SHFT                                             0x12
#define HWIO_FEATURE_CONFIG14_APPS_PBL_BOOT_SPEED_BMSK                                             0x30000
#define HWIO_FEATURE_CONFIG14_APPS_PBL_BOOT_SPEED_SHFT                                                0x10
#define HWIO_FEATURE_CONFIG14_MODEM_PBL_BOOT_BMSK                                                   0x8000
#define HWIO_FEATURE_CONFIG14_MODEM_PBL_BOOT_SHFT                                                      0xf
#define HWIO_FEATURE_CONFIG14_RSVD1_56_14_BMSK                                                      0x4000
#define HWIO_FEATURE_CONFIG14_RSVD1_56_14_SHFT                                                         0xe
#define HWIO_FEATURE_CONFIG14_APPS_BOOT_FROM_ROM_BMSK                                               0x2000
#define HWIO_FEATURE_CONFIG14_APPS_BOOT_FROM_ROM_SHFT                                                  0xd
#define HWIO_FEATURE_CONFIG14_ENABLE_DEVICE_IN_TEST_MODE_BMSK                                       0x1000
#define HWIO_FEATURE_CONFIG14_ENABLE_DEVICE_IN_TEST_MODE_SHFT                                          0xc
#define HWIO_FEATURE_CONFIG14_QTI_ROOT_SIG_FORMAT_SEL_BMSK                                           0x800
#define HWIO_FEATURE_CONFIG14_QTI_ROOT_SIG_FORMAT_SEL_SHFT                                             0xb
#define HWIO_FEATURE_CONFIG14_CE_BAM_DISABLE_BMSK                                                    0x400
#define HWIO_FEATURE_CONFIG14_CE_BAM_DISABLE_SHFT                                                      0xa
#define HWIO_FEATURE_CONFIG14_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_BMSK                                0x200
#define HWIO_FEATURE_CONFIG14_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_SHFT                                  0x9
#define HWIO_FEATURE_CONFIG14_ARM_CE_DISABLE_USAGE_BMSK                                              0x100
#define HWIO_FEATURE_CONFIG14_ARM_CE_DISABLE_USAGE_SHFT                                                0x8
#define HWIO_FEATURE_CONFIG14_BOOT_ROM_CFG_BMSK                                                       0xff
#define HWIO_FEATURE_CONFIG14_BOOT_ROM_CFG_SHFT                                                        0x0

#define HWIO_FEATURE_CONFIG15_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006040)
#define HWIO_FEATURE_CONFIG15_RMSK                                                              0xffffffff
#define HWIO_FEATURE_CONFIG15_IN          \
        in_dword(HWIO_FEATURE_CONFIG15_ADDR)
#define HWIO_FEATURE_CONFIG15_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG15_ADDR, m)
#define HWIO_FEATURE_CONFIG15_APPS_BOOT_TRIGGER_DISABLE_BMSK                                    0x80000000
#define HWIO_FEATURE_CONFIG15_APPS_BOOT_TRIGGER_DISABLE_SHFT                                          0x1f
#define HWIO_FEATURE_CONFIG15_PBL_QSEE_BOOT_FLOW_DISABLE_BMSK                                   0x40000000
#define HWIO_FEATURE_CONFIG15_PBL_QSEE_BOOT_FLOW_DISABLE_SHFT                                         0x1e
#define HWIO_FEATURE_CONFIG15_XBL_SEC_AUTH_DISABLE_BMSK                                         0x20000000
#define HWIO_FEATURE_CONFIG15_XBL_SEC_AUTH_DISABLE_SHFT                                               0x1d
#define HWIO_FEATURE_CONFIG15_MSM_PKG_TYPE_BMSK                                                 0x10000000
#define HWIO_FEATURE_CONFIG15_MSM_PKG_TYPE_SHFT                                                       0x1c
#define HWIO_FEATURE_CONFIG15_SPSS_CONFIG_MODE_BMSK                                              0xc000000
#define HWIO_FEATURE_CONFIG15_SPSS_CONFIG_MODE_SHFT                                                   0x1a
#define HWIO_FEATURE_CONFIG15_PERIPH_DRV_STRENGTH_SETTING_BMSK                                   0x3800000
#define HWIO_FEATURE_CONFIG15_PERIPH_DRV_STRENGTH_SETTING_SHFT                                        0x17
#define HWIO_FEATURE_CONFIG15_RSVD3_56_54_BMSK                                                    0x400000
#define HWIO_FEATURE_CONFIG15_RSVD3_56_54_SHFT                                                        0x16
#define HWIO_FEATURE_CONFIG15_FOUNDRY_ID_BMSK                                                     0x3c0000
#define HWIO_FEATURE_CONFIG15_FOUNDRY_ID_SHFT                                                         0x12
#define HWIO_FEATURE_CONFIG15_PLL_CFG_BMSK                                                         0x3fff0
#define HWIO_FEATURE_CONFIG15_PLL_CFG_SHFT                                                             0x4
#define HWIO_FEATURE_CONFIG15_APPS_PBL_PLL_CTRL_BMSK                                                   0xf
#define HWIO_FEATURE_CONFIG15_APPS_PBL_PLL_CTRL_SHFT                                                   0x0

#define HWIO_OEM_CONFIG0_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006044)
#define HWIO_OEM_CONFIG0_RMSK                                                                   0xffffffff
#define HWIO_OEM_CONFIG0_IN          \
        in_dword(HWIO_OEM_CONFIG0_ADDR)
#define HWIO_OEM_CONFIG0_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG0_ADDR, m)
#define HWIO_OEM_CONFIG0_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                                       0x80000000
#define HWIO_OEM_CONFIG0_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                                             0x1f
#define HWIO_OEM_CONFIG0_SHARED_QSEE_SPIDEN_DISABLE_BMSK                                        0x40000000
#define HWIO_OEM_CONFIG0_SHARED_QSEE_SPIDEN_DISABLE_SHFT                                              0x1e
#define HWIO_OEM_CONFIG0_ALL_DEBUG_DISABLE_BMSK                                                 0x20000000
#define HWIO_OEM_CONFIG0_ALL_DEBUG_DISABLE_SHFT                                                       0x1d
#define HWIO_OEM_CONFIG0_DEBUG_POLICY_DISABLE_BMSK                                              0x10000000
#define HWIO_OEM_CONFIG0_DEBUG_POLICY_DISABLE_SHFT                                                    0x1c
#define HWIO_OEM_CONFIG0_SP_DISABLE_BMSK                                                         0x8000000
#define HWIO_OEM_CONFIG0_SP_DISABLE_SHFT                                                              0x1b
#define HWIO_OEM_CONFIG0_UDK_DISABLE_BMSK                                                        0x4000000
#define HWIO_OEM_CONFIG0_UDK_DISABLE_SHFT                                                             0x1a
#define HWIO_OEM_CONFIG0_DEBUG_DISABLE_IN_ROM_BMSK                                               0x2000000
#define HWIO_OEM_CONFIG0_DEBUG_DISABLE_IN_ROM_SHFT                                                    0x19
#define HWIO_OEM_CONFIG0_MSS_HASH_INTEGRITY_CHECK_ENABLE_BMSK                                    0x1000000
#define HWIO_OEM_CONFIG0_MSS_HASH_INTEGRITY_CHECK_ENABLE_SHFT                                         0x18
#define HWIO_OEM_CONFIG0_APPS_HASH_INTEGRITY_CHECK_DISABLE_BMSK                                   0x800000
#define HWIO_OEM_CONFIG0_APPS_HASH_INTEGRITY_CHECK_DISABLE_SHFT                                       0x17
#define HWIO_OEM_CONFIG0_USB_SS_DISABLE_BMSK                                                      0x400000
#define HWIO_OEM_CONFIG0_USB_SS_DISABLE_SHFT                                                          0x16
#define HWIO_OEM_CONFIG0_SW_ROT_USE_SERIAL_NUM_BMSK                                               0x200000
#define HWIO_OEM_CONFIG0_SW_ROT_USE_SERIAL_NUM_SHFT                                                   0x15
#define HWIO_OEM_CONFIG0_DISABLE_ROT_TRANSFER_BMSK                                                0x100000
#define HWIO_OEM_CONFIG0_DISABLE_ROT_TRANSFER_SHFT                                                    0x14
#define HWIO_OEM_CONFIG0_IMAGE_ENCRYPTION_ENABLE_BMSK                                              0x80000
#define HWIO_OEM_CONFIG0_IMAGE_ENCRYPTION_ENABLE_SHFT                                                 0x13
#define HWIO_OEM_CONFIG0_ROOT_CERT_TOTAL_NUM_BMSK                                                  0x60000
#define HWIO_OEM_CONFIG0_ROOT_CERT_TOTAL_NUM_SHFT                                                     0x11
#define HWIO_OEM_CONFIG0_PBL_USB_TYPE_C_DISABLE_BMSK                                               0x10000
#define HWIO_OEM_CONFIG0_PBL_USB_TYPE_C_DISABLE_SHFT                                                  0x10
#define HWIO_OEM_CONFIG0_PBL_LOG_DISABLE_BMSK                                                       0x8000
#define HWIO_OEM_CONFIG0_PBL_LOG_DISABLE_SHFT                                                          0xf
#define HWIO_OEM_CONFIG0_WDOG_EN_BMSK                                                               0x4000
#define HWIO_OEM_CONFIG0_WDOG_EN_SHFT                                                                  0xe
#define HWIO_OEM_CONFIG0_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_BMSK                                  0x2000
#define HWIO_OEM_CONFIG0_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_SHFT                                     0xd
#define HWIO_OEM_CONFIG0_SW_FUSE_PROG_DISABLE_BMSK                                                  0x1000
#define HWIO_OEM_CONFIG0_SW_FUSE_PROG_DISABLE_SHFT                                                     0xc
#define HWIO_OEM_CONFIG0_SPI_CLK_BOOT_FREQ_BMSK                                                      0x800
#define HWIO_OEM_CONFIG0_SPI_CLK_BOOT_FREQ_SHFT                                                        0xb
#define HWIO_OEM_CONFIG0_PBL_QSPI_BOOT_EDL_ENABLED_BMSK                                              0x400
#define HWIO_OEM_CONFIG0_PBL_QSPI_BOOT_EDL_ENABLED_SHFT                                                0xa
#define HWIO_OEM_CONFIG0_FAST_BOOT_BMSK                                                              0x3e0
#define HWIO_OEM_CONFIG0_FAST_BOOT_SHFT                                                                0x5
#define HWIO_OEM_CONFIG0_SDCC_MCLK_BOOT_FREQ_BMSK                                                     0x10
#define HWIO_OEM_CONFIG0_SDCC_MCLK_BOOT_FREQ_SHFT                                                      0x4
#define HWIO_OEM_CONFIG0_FORCE_USB_BOOT_DISABLE_BMSK                                                   0x8
#define HWIO_OEM_CONFIG0_FORCE_USB_BOOT_DISABLE_SHFT                                                   0x3
#define HWIO_OEM_CONFIG0_FORCE_DLOAD_DISABLE_BMSK                                                      0x4
#define HWIO_OEM_CONFIG0_FORCE_DLOAD_DISABLE_SHFT                                                      0x2
#define HWIO_OEM_CONFIG0_ENUM_TIMEOUT_BMSK                                                             0x2
#define HWIO_OEM_CONFIG0_ENUM_TIMEOUT_SHFT                                                             0x1
#define HWIO_OEM_CONFIG0_E_DLOAD_DISABLE_BMSK                                                          0x1
#define HWIO_OEM_CONFIG0_E_DLOAD_DISABLE_SHFT                                                          0x0

#define HWIO_OEM_CONFIG1_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006048)
#define HWIO_OEM_CONFIG1_RMSK                                                                   0xffffffff
#define HWIO_OEM_CONFIG1_IN          \
        in_dword(HWIO_OEM_CONFIG1_ADDR)
#define HWIO_OEM_CONFIG1_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG1_ADDR, m)
#define HWIO_OEM_CONFIG1_RSVD1_BMSK                                                             0xffffc000
#define HWIO_OEM_CONFIG1_RSVD1_SHFT                                                                    0xe
#define HWIO_OEM_CONFIG1_SHARED_MISC5_DEBUG_DISABLE_BMSK                                            0x2000
#define HWIO_OEM_CONFIG1_SHARED_MISC5_DEBUG_DISABLE_SHFT                                               0xd
#define HWIO_OEM_CONFIG1_SHARED_MISC4_DEBUG_DISABLE_BMSK                                            0x1000
#define HWIO_OEM_CONFIG1_SHARED_MISC4_DEBUG_DISABLE_SHFT                                               0xc
#define HWIO_OEM_CONFIG1_SHARED_MISC3_DEBUG_DISABLE_BMSK                                             0x800
#define HWIO_OEM_CONFIG1_SHARED_MISC3_DEBUG_DISABLE_SHFT                                               0xb
#define HWIO_OEM_CONFIG1_SHARED_MISC2_DEBUG_DISABLE_BMSK                                             0x400
#define HWIO_OEM_CONFIG1_SHARED_MISC2_DEBUG_DISABLE_SHFT                                               0xa
#define HWIO_OEM_CONFIG1_SHARED_MISC1_DEBUG_DISABLE_BMSK                                             0x200
#define HWIO_OEM_CONFIG1_SHARED_MISC1_DEBUG_DISABLE_SHFT                                               0x9
#define HWIO_OEM_CONFIG1_SHARED_MISC_DEBUG_DISABLE_BMSK                                              0x100
#define HWIO_OEM_CONFIG1_SHARED_MISC_DEBUG_DISABLE_SHFT                                                0x8
#define HWIO_OEM_CONFIG1_APPS_NIDEN_DISABLE_BMSK                                                      0x80
#define HWIO_OEM_CONFIG1_APPS_NIDEN_DISABLE_SHFT                                                       0x7
#define HWIO_OEM_CONFIG1_APPS_DBGEN_DISABLE_BMSK                                                      0x40
#define HWIO_OEM_CONFIG1_APPS_DBGEN_DISABLE_SHFT                                                       0x6
#define HWIO_OEM_CONFIG1_SHARED_NS_NIDEN_DISABLE_BMSK                                                 0x20
#define HWIO_OEM_CONFIG1_SHARED_NS_NIDEN_DISABLE_SHFT                                                  0x5
#define HWIO_OEM_CONFIG1_SHARED_NS_DBGEN_DISABLE_BMSK                                                 0x10
#define HWIO_OEM_CONFIG1_SHARED_NS_DBGEN_DISABLE_SHFT                                                  0x4
#define HWIO_OEM_CONFIG1_SHARED_CP_NIDEN_DISABLE_BMSK                                                  0x8
#define HWIO_OEM_CONFIG1_SHARED_CP_NIDEN_DISABLE_SHFT                                                  0x3
#define HWIO_OEM_CONFIG1_SHARED_CP_DBGEN_DISABLE_BMSK                                                  0x4
#define HWIO_OEM_CONFIG1_SHARED_CP_DBGEN_DISABLE_SHFT                                                  0x2
#define HWIO_OEM_CONFIG1_SHARED_MSS_NIDEN_DISABLE_BMSK                                                 0x2
#define HWIO_OEM_CONFIG1_SHARED_MSS_NIDEN_DISABLE_SHFT                                                 0x1
#define HWIO_OEM_CONFIG1_SHARED_MSS_DBGEN_DISABLE_BMSK                                                 0x1
#define HWIO_OEM_CONFIG1_SHARED_MSS_DBGEN_DISABLE_SHFT                                                 0x0

#define HWIO_OEM_CONFIG2_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000604c)
#define HWIO_OEM_CONFIG2_RMSK                                                                   0xffffffff
#define HWIO_OEM_CONFIG2_IN          \
        in_dword(HWIO_OEM_CONFIG2_ADDR)
#define HWIO_OEM_CONFIG2_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG2_ADDR, m)
#define HWIO_OEM_CONFIG2_DISABLE_RSA_BMSK                                                       0x80000000
#define HWIO_OEM_CONFIG2_DISABLE_RSA_SHFT                                                             0x1f
#define HWIO_OEM_CONFIG2_EKU_ENFORCEMENT_EN_BMSK                                                0x40000000
#define HWIO_OEM_CONFIG2_EKU_ENFORCEMENT_EN_SHFT                                                      0x1e
#define HWIO_OEM_CONFIG2_RSVD2_BMSK                                                             0x3fff0000
#define HWIO_OEM_CONFIG2_RSVD2_SHFT                                                                   0x10
#define HWIO_OEM_CONFIG2_SPARE_REG31_SECURE_BMSK                                                    0x8000
#define HWIO_OEM_CONFIG2_SPARE_REG31_SECURE_SHFT                                                       0xf
#define HWIO_OEM_CONFIG2_SPARE_REG30_SECURE_BMSK                                                    0x4000
#define HWIO_OEM_CONFIG2_SPARE_REG30_SECURE_SHFT                                                       0xe
#define HWIO_OEM_CONFIG2_SPARE_REG29_SECURE_BMSK                                                    0x2000
#define HWIO_OEM_CONFIG2_SPARE_REG29_SECURE_SHFT                                                       0xd
#define HWIO_OEM_CONFIG2_SPARE_REG28_SECURE_BMSK                                                    0x1000
#define HWIO_OEM_CONFIG2_SPARE_REG28_SECURE_SHFT                                                       0xc
#define HWIO_OEM_CONFIG2_RSVD1_BMSK                                                                  0xf00
#define HWIO_OEM_CONFIG2_RSVD1_SHFT                                                                    0x8
#define HWIO_OEM_CONFIG2_TZ_SW_CRYPTO_FIPS_OVERRIDE_BMSK                                              0x80
#define HWIO_OEM_CONFIG2_TZ_SW_CRYPTO_FIPS_OVERRIDE_SHFT                                               0x7
#define HWIO_OEM_CONFIG2_SP_FIPS_OVERRIDE_BMSK                                                        0x40
#define HWIO_OEM_CONFIG2_SP_FIPS_OVERRIDE_SHFT                                                         0x6
#define HWIO_OEM_CONFIG2_MODEM_CRYPTO_FIPS_ENABLE_BMSK                                                0x20
#define HWIO_OEM_CONFIG2_MODEM_CRYPTO_FIPS_ENABLE_SHFT                                                 0x5
#define HWIO_OEM_CONFIG2_TZ_SW_CRYPTO_FIPS_ENABLE_BMSK                                                0x10
#define HWIO_OEM_CONFIG2_TZ_SW_CRYPTO_FIPS_ENABLE_SHFT                                                 0x4
#define HWIO_OEM_CONFIG2_SP_FIPS_ENABLE_BMSK                                                           0x8
#define HWIO_OEM_CONFIG2_SP_FIPS_ENABLE_SHFT                                                           0x3
#define HWIO_OEM_CONFIG2_SP_NVM_AR_CONFIG_BMSK                                                         0x6
#define HWIO_OEM_CONFIG2_SP_NVM_AR_CONFIG_SHFT                                                         0x1
#define HWIO_OEM_CONFIG2_RSVD0_BMSK                                                                    0x1
#define HWIO_OEM_CONFIG2_RSVD0_SHFT                                                                    0x0

#define HWIO_OEM_CONFIG3_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006050)
#define HWIO_OEM_CONFIG3_RMSK                                                                   0xffffffff
#define HWIO_OEM_CONFIG3_IN          \
        in_dword(HWIO_OEM_CONFIG3_ADDR)
#define HWIO_OEM_CONFIG3_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG3_ADDR, m)
#define HWIO_OEM_CONFIG3_OEM_PRODUCT_ID_BMSK                                                    0xffff0000
#define HWIO_OEM_CONFIG3_OEM_PRODUCT_ID_SHFT                                                          0x10
#define HWIO_OEM_CONFIG3_OEM_HW_ID_BMSK                                                             0xffff
#define HWIO_OEM_CONFIG3_OEM_HW_ID_SHFT                                                                0x0

#define HWIO_OEM_CONFIG4_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006054)
#define HWIO_OEM_CONFIG4_RMSK                                                                   0xffffffff
#define HWIO_OEM_CONFIG4_IN          \
        in_dword(HWIO_OEM_CONFIG4_ADDR)
#define HWIO_OEM_CONFIG4_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG4_ADDR, m)
#define HWIO_OEM_CONFIG4_PERIPH_VID_BMSK                                                        0xffff0000
#define HWIO_OEM_CONFIG4_PERIPH_VID_SHFT                                                              0x10
#define HWIO_OEM_CONFIG4_PERIPH_PID_BMSK                                                            0xffff
#define HWIO_OEM_CONFIG4_PERIPH_PID_SHFT                                                               0x0

#define HWIO_OEM_CONFIG5_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006058)
#define HWIO_OEM_CONFIG5_RMSK                                                                   0xffffffff
#define HWIO_OEM_CONFIG5_IN          \
        in_dword(HWIO_OEM_CONFIG5_ADDR)
#define HWIO_OEM_CONFIG5_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG5_ADDR, m)
#define HWIO_OEM_CONFIG5_RSVD0_BMSK                                                             0xffffff00
#define HWIO_OEM_CONFIG5_RSVD0_SHFT                                                                    0x8
#define HWIO_OEM_CONFIG5_ANTI_ROLLBACK_FEATURE_EN_BMSK                                                0xff
#define HWIO_OEM_CONFIG5_ANTI_ROLLBACK_FEATURE_EN_SHFT                                                 0x0

#define HWIO_BOOT_CONFIG_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006070)
#define HWIO_BOOT_CONFIG_RMSK                                                                        0x1ff
#define HWIO_BOOT_CONFIG_IN          \
        in_dword(HWIO_BOOT_CONFIG_ADDR)
#define HWIO_BOOT_CONFIG_INM(m)      \
        in_dword_masked(HWIO_BOOT_CONFIG_ADDR, m)
#define HWIO_BOOT_CONFIG_APPS_PBL_BOOT_SPEED_BMSK                                                    0x180
#define HWIO_BOOT_CONFIG_APPS_PBL_BOOT_SPEED_SHFT                                                      0x7
#define HWIO_BOOT_CONFIG_APPS_BOOT_FROM_ROM_BMSK                                                      0x40
#define HWIO_BOOT_CONFIG_APPS_BOOT_FROM_ROM_SHFT                                                       0x6
#define HWIO_BOOT_CONFIG_FAST_BOOT_BMSK                                                               0x3e
#define HWIO_BOOT_CONFIG_FAST_BOOT_SHFT                                                                0x1
#define HWIO_BOOT_CONFIG_WDOG_EN_BMSK                                                                  0x1
#define HWIO_BOOT_CONFIG_WDOG_EN_SHFT                                                                  0x0

#define HWIO_SECURE_BOOTn_ADDR(n)                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006078 + 0x4 * (n))
#define HWIO_SECURE_BOOTn_RMSK                                                                       0x1ff
#define HWIO_SECURE_BOOTn_MAXn                                                                          14
#define HWIO_SECURE_BOOTn_INI(n)        \
        in_dword_masked(HWIO_SECURE_BOOTn_ADDR(n), HWIO_SECURE_BOOTn_RMSK)
#define HWIO_SECURE_BOOTn_INMI(n,mask)    \
        in_dword_masked(HWIO_SECURE_BOOTn_ADDR(n), mask)
#define HWIO_SECURE_BOOTn_FUSE_SRC_BMSK                                                              0x100
#define HWIO_SECURE_BOOTn_FUSE_SRC_SHFT                                                                0x8
#define HWIO_SECURE_BOOTn_RSVD_7_BMSK                                                                 0x80
#define HWIO_SECURE_BOOTn_RSVD_7_SHFT                                                                  0x7
#define HWIO_SECURE_BOOTn_USE_SERIAL_NUM_BMSK                                                         0x40
#define HWIO_SECURE_BOOTn_USE_SERIAL_NUM_SHFT                                                          0x6
#define HWIO_SECURE_BOOTn_AUTH_EN_BMSK                                                                0x20
#define HWIO_SECURE_BOOTn_AUTH_EN_SHFT                                                                 0x5
#define HWIO_SECURE_BOOTn_PK_HASH_IN_FUSE_BMSK                                                        0x10
#define HWIO_SECURE_BOOTn_PK_HASH_IN_FUSE_SHFT                                                         0x4
#define HWIO_SECURE_BOOTn_ROM_PK_HASH_INDEX_BMSK                                                       0xf
#define HWIO_SECURE_BOOTn_ROM_PK_HASH_INDEX_SHFT                                                       0x0

#define HWIO_QSEE_INV_OVERRIDE_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060c0)
#define HWIO_QSEE_INV_OVERRIDE_RMSK                                                             0xffffffff
#define HWIO_QSEE_INV_OVERRIDE_IN          \
        in_dword(HWIO_QSEE_INV_OVERRIDE_ADDR)
#define HWIO_QSEE_INV_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_QSEE_INV_OVERRIDE_ADDR, m)
#define HWIO_QSEE_INV_OVERRIDE_OUT(v)      \
        out_dword(HWIO_QSEE_INV_OVERRIDE_ADDR,v)
#define HWIO_QSEE_INV_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QSEE_INV_OVERRIDE_ADDR,m,v,HWIO_QSEE_INV_OVERRIDE_IN)
#define HWIO_QSEE_INV_OVERRIDE_RSVD_31_1_BMSK                                                   0xfffffffe
#define HWIO_QSEE_INV_OVERRIDE_RSVD_31_1_SHFT                                                          0x1
#define HWIO_QSEE_INV_OVERRIDE_SHARED_QSEE_SPIDEN_DISABLE_BMSK                                         0x1
#define HWIO_QSEE_INV_OVERRIDE_SHARED_QSEE_SPIDEN_DISABLE_SHFT                                         0x0

#define HWIO_QSEE_NI_OVERRIDE_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060c4)
#define HWIO_QSEE_NI_OVERRIDE_RMSK                                                              0xffffffff
#define HWIO_QSEE_NI_OVERRIDE_IN          \
        in_dword(HWIO_QSEE_NI_OVERRIDE_ADDR)
#define HWIO_QSEE_NI_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_QSEE_NI_OVERRIDE_ADDR, m)
#define HWIO_QSEE_NI_OVERRIDE_OUT(v)      \
        out_dword(HWIO_QSEE_NI_OVERRIDE_ADDR,v)
#define HWIO_QSEE_NI_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QSEE_NI_OVERRIDE_ADDR,m,v,HWIO_QSEE_NI_OVERRIDE_IN)
#define HWIO_QSEE_NI_OVERRIDE_RSVD_31_1_BMSK                                                    0xfffffffe
#define HWIO_QSEE_NI_OVERRIDE_RSVD_31_1_SHFT                                                           0x1
#define HWIO_QSEE_NI_OVERRIDE_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                                         0x1
#define HWIO_QSEE_NI_OVERRIDE_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                                         0x0

#define HWIO_MSS_INV_OVERRIDE_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060c8)
#define HWIO_MSS_INV_OVERRIDE_RMSK                                                              0xffffffff
#define HWIO_MSS_INV_OVERRIDE_IN          \
        in_dword(HWIO_MSS_INV_OVERRIDE_ADDR)
#define HWIO_MSS_INV_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_MSS_INV_OVERRIDE_ADDR, m)
#define HWIO_MSS_INV_OVERRIDE_OUT(v)      \
        out_dword(HWIO_MSS_INV_OVERRIDE_ADDR,v)
#define HWIO_MSS_INV_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MSS_INV_OVERRIDE_ADDR,m,v,HWIO_MSS_INV_OVERRIDE_IN)
#define HWIO_MSS_INV_OVERRIDE_RSVD_31_1_BMSK                                                    0xfffffffe
#define HWIO_MSS_INV_OVERRIDE_RSVD_31_1_SHFT                                                           0x1
#define HWIO_MSS_INV_OVERRIDE_SHARED_MSS_DBGEN_DISABLE_BMSK                                            0x1
#define HWIO_MSS_INV_OVERRIDE_SHARED_MSS_DBGEN_DISABLE_SHFT                                            0x0

#define HWIO_MSS_NI_OVERRIDE_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060cc)
#define HWIO_MSS_NI_OVERRIDE_RMSK                                                               0xffffffff
#define HWIO_MSS_NI_OVERRIDE_IN          \
        in_dword(HWIO_MSS_NI_OVERRIDE_ADDR)
#define HWIO_MSS_NI_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_MSS_NI_OVERRIDE_ADDR, m)
#define HWIO_MSS_NI_OVERRIDE_OUT(v)      \
        out_dword(HWIO_MSS_NI_OVERRIDE_ADDR,v)
#define HWIO_MSS_NI_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MSS_NI_OVERRIDE_ADDR,m,v,HWIO_MSS_NI_OVERRIDE_IN)
#define HWIO_MSS_NI_OVERRIDE_RSVD_31_1_BMSK                                                     0xfffffffe
#define HWIO_MSS_NI_OVERRIDE_RSVD_31_1_SHFT                                                            0x1
#define HWIO_MSS_NI_OVERRIDE_SHARED_MSS_NIDEN_DISABLE_BMSK                                             0x1
#define HWIO_MSS_NI_OVERRIDE_SHARED_MSS_NIDEN_DISABLE_SHFT                                             0x0

#define HWIO_CP_INV_OVERRIDE_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060d0)
#define HWIO_CP_INV_OVERRIDE_RMSK                                                               0xffffffff
#define HWIO_CP_INV_OVERRIDE_IN          \
        in_dword(HWIO_CP_INV_OVERRIDE_ADDR)
#define HWIO_CP_INV_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_CP_INV_OVERRIDE_ADDR, m)
#define HWIO_CP_INV_OVERRIDE_OUT(v)      \
        out_dword(HWIO_CP_INV_OVERRIDE_ADDR,v)
#define HWIO_CP_INV_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CP_INV_OVERRIDE_ADDR,m,v,HWIO_CP_INV_OVERRIDE_IN)
#define HWIO_CP_INV_OVERRIDE_RSVD_31_1_BMSK                                                     0xfffffffe
#define HWIO_CP_INV_OVERRIDE_RSVD_31_1_SHFT                                                            0x1
#define HWIO_CP_INV_OVERRIDE_SHARED_CP_DBGEN_DISABLE_BMSK                                              0x1
#define HWIO_CP_INV_OVERRIDE_SHARED_CP_DBGEN_DISABLE_SHFT                                              0x0

#define HWIO_CP_NI_OVERRIDE_ADDR                                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060d4)
#define HWIO_CP_NI_OVERRIDE_RMSK                                                                0xffffffff
#define HWIO_CP_NI_OVERRIDE_IN          \
        in_dword(HWIO_CP_NI_OVERRIDE_ADDR)
#define HWIO_CP_NI_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_CP_NI_OVERRIDE_ADDR, m)
#define HWIO_CP_NI_OVERRIDE_OUT(v)      \
        out_dword(HWIO_CP_NI_OVERRIDE_ADDR,v)
#define HWIO_CP_NI_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CP_NI_OVERRIDE_ADDR,m,v,HWIO_CP_NI_OVERRIDE_IN)
#define HWIO_CP_NI_OVERRIDE_RSVD_31_1_BMSK                                                      0xfffffffe
#define HWIO_CP_NI_OVERRIDE_RSVD_31_1_SHFT                                                             0x1
#define HWIO_CP_NI_OVERRIDE_SHARED_CP_NIDEN_DISABLE_BMSK                                               0x1
#define HWIO_CP_NI_OVERRIDE_SHARED_CP_NIDEN_DISABLE_SHFT                                               0x0

#define HWIO_NS_INV_OVERRIDE_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060d8)
#define HWIO_NS_INV_OVERRIDE_RMSK                                                               0xffffffff
#define HWIO_NS_INV_OVERRIDE_IN          \
        in_dword(HWIO_NS_INV_OVERRIDE_ADDR)
#define HWIO_NS_INV_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_NS_INV_OVERRIDE_ADDR, m)
#define HWIO_NS_INV_OVERRIDE_OUT(v)      \
        out_dword(HWIO_NS_INV_OVERRIDE_ADDR,v)
#define HWIO_NS_INV_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_NS_INV_OVERRIDE_ADDR,m,v,HWIO_NS_INV_OVERRIDE_IN)
#define HWIO_NS_INV_OVERRIDE_RSVD_31_5_BMSK                                                     0xffffffe0
#define HWIO_NS_INV_OVERRIDE_RSVD_31_5_SHFT                                                            0x5
#define HWIO_NS_INV_OVERRIDE_APPS_DBGEN_DISABLE_BMSK                                                  0x10
#define HWIO_NS_INV_OVERRIDE_APPS_DBGEN_DISABLE_SHFT                                                   0x4
#define HWIO_NS_INV_OVERRIDE_RSVD_3_1_BMSK                                                             0xe
#define HWIO_NS_INV_OVERRIDE_RSVD_3_1_SHFT                                                             0x1
#define HWIO_NS_INV_OVERRIDE_SHARED_NS_DBGEN_DISABLE_BMSK                                              0x1
#define HWIO_NS_INV_OVERRIDE_SHARED_NS_DBGEN_DISABLE_SHFT                                              0x0

#define HWIO_NS_NI_OVERRIDE_ADDR                                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060dc)
#define HWIO_NS_NI_OVERRIDE_RMSK                                                                0xffffffff
#define HWIO_NS_NI_OVERRIDE_IN          \
        in_dword(HWIO_NS_NI_OVERRIDE_ADDR)
#define HWIO_NS_NI_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_NS_NI_OVERRIDE_ADDR, m)
#define HWIO_NS_NI_OVERRIDE_OUT(v)      \
        out_dword(HWIO_NS_NI_OVERRIDE_ADDR,v)
#define HWIO_NS_NI_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_NS_NI_OVERRIDE_ADDR,m,v,HWIO_NS_NI_OVERRIDE_IN)
#define HWIO_NS_NI_OVERRIDE_RSVD_31_5_BMSK                                                      0xffffffe0
#define HWIO_NS_NI_OVERRIDE_RSVD_31_5_SHFT                                                             0x5
#define HWIO_NS_NI_OVERRIDE_APPS_NIDEN_DISABLE_BMSK                                                   0x10
#define HWIO_NS_NI_OVERRIDE_APPS_NIDEN_DISABLE_SHFT                                                    0x4
#define HWIO_NS_NI_OVERRIDE_RSVD_3_1_BMSK                                                              0xe
#define HWIO_NS_NI_OVERRIDE_RSVD_3_1_SHFT                                                              0x1
#define HWIO_NS_NI_OVERRIDE_SHARED_NS_NIDEN_DISABLE_BMSK                                               0x1
#define HWIO_NS_NI_OVERRIDE_SHARED_NS_NIDEN_DISABLE_SHFT                                               0x0

#define HWIO_MISC_DEBUG_OVERRIDE_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060e0)
#define HWIO_MISC_DEBUG_OVERRIDE_RMSK                                                           0xffffffff
#define HWIO_MISC_DEBUG_OVERRIDE_IN          \
        in_dword(HWIO_MISC_DEBUG_OVERRIDE_ADDR)
#define HWIO_MISC_DEBUG_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_MISC_DEBUG_OVERRIDE_ADDR, m)
#define HWIO_MISC_DEBUG_OVERRIDE_OUT(v)      \
        out_dword(HWIO_MISC_DEBUG_OVERRIDE_ADDR,v)
#define HWIO_MISC_DEBUG_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MISC_DEBUG_OVERRIDE_ADDR,m,v,HWIO_MISC_DEBUG_OVERRIDE_IN)
#define HWIO_MISC_DEBUG_OVERRIDE_RSVD_31_6_BMSK                                                 0xffffffc0
#define HWIO_MISC_DEBUG_OVERRIDE_RSVD_31_6_SHFT                                                        0x6
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC5_DEBUG_DISABLE_BMSK                                      0x20
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC5_DEBUG_DISABLE_SHFT                                       0x5
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC4_DEBUG_DISABLE_BMSK                                      0x10
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC4_DEBUG_DISABLE_SHFT                                       0x4
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC3_DEBUG_DISABLE_BMSK                                       0x8
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC3_DEBUG_DISABLE_SHFT                                       0x3
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC2_DEBUG_DISABLE_BMSK                                       0x4
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC2_DEBUG_DISABLE_SHFT                                       0x2
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC1_DEBUG_DISABLE_BMSK                                       0x2
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC1_DEBUG_DISABLE_SHFT                                       0x1
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC_DEBUG_DISABLE_BMSK                                        0x1
#define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC_DEBUG_DISABLE_SHFT                                        0x0

#define HWIO_CAPT_SEC_GPIO_ADDR                                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006100)
#define HWIO_CAPT_SEC_GPIO_RMSK                                                                     0x1fff
#define HWIO_CAPT_SEC_GPIO_IN          \
        in_dword(HWIO_CAPT_SEC_GPIO_ADDR)
#define HWIO_CAPT_SEC_GPIO_INM(m)      \
        in_dword_masked(HWIO_CAPT_SEC_GPIO_ADDR, m)
#define HWIO_CAPT_SEC_GPIO_OUT(v)      \
        out_dword(HWIO_CAPT_SEC_GPIO_ADDR,v)
#define HWIO_CAPT_SEC_GPIO_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CAPT_SEC_GPIO_ADDR,m,v,HWIO_CAPT_SEC_GPIO_IN)
#define HWIO_CAPT_SEC_GPIO_FORCE_USB_BOOT_GPIO_BMSK                                                 0x1000
#define HWIO_CAPT_SEC_GPIO_FORCE_USB_BOOT_GPIO_SHFT                                                    0xc
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_AP_AUTH_EN_BMSK                                          0x800
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_AP_AUTH_EN_SHFT                                            0xb
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_AP_PK_HASH_IN_FUSE_BMSK                                  0x400
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_AP_PK_HASH_IN_FUSE_SHFT                                    0xa
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_ALL_USE_SERIAL_NUM_BMSK                                  0x200
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_ALL_USE_SERIAL_NUM_SHFT                                    0x9
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_PK_HASH_INDEX_SRC_BMSK                                   0x100
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_PK_HASH_INDEX_SRC_SHFT                                     0x8
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_APPS_PBL_BOOT_SPEED_BMSK                                  0xc0
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_APPS_PBL_BOOT_SPEED_SHFT                                   0x6
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_APPS_BOOT_FROM_ROM_BMSK                                   0x20
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_APPS_BOOT_FROM_ROM_SHFT                                    0x5
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_FAST_BOOT_BMSK                                            0x1e
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_FAST_BOOT_SHFT                                             0x1
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_WDOG_DISABLE_BMSK                                          0x1
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_WDOG_DISABLE_SHFT                                          0x0

#define HWIO_APP_PROC_CFG_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006110)
#define HWIO_APP_PROC_CFG_RMSK                                                                     0xfffff
#define HWIO_APP_PROC_CFG_IN          \
        in_dword(HWIO_APP_PROC_CFG_ADDR)
#define HWIO_APP_PROC_CFG_INM(m)      \
        in_dword_masked(HWIO_APP_PROC_CFG_ADDR, m)
#define HWIO_APP_PROC_CFG_OUT(v)      \
        out_dword(HWIO_APP_PROC_CFG_ADDR,v)
#define HWIO_APP_PROC_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_APP_PROC_CFG_ADDR,m,v,HWIO_APP_PROC_CFG_IN)
#define HWIO_APP_PROC_CFG_SPARE0_BMSK                                                              0xc0000
#define HWIO_APP_PROC_CFG_SPARE0_SHFT                                                                 0x12
#define HWIO_APP_PROC_CFG_SPARE1_BMSK                                                              0x30000
#define HWIO_APP_PROC_CFG_SPARE1_SHFT                                                                 0x10
#define HWIO_APP_PROC_CFG_APPS_CFG_MISC2_BMSK                                                       0xf000
#define HWIO_APP_PROC_CFG_APPS_CFG_MISC2_SHFT                                                          0xc
#define HWIO_APP_PROC_CFG_APPS_CFG_MISC1_BMSK                                                        0xf00
#define HWIO_APP_PROC_CFG_APPS_CFG_MISC1_SHFT                                                          0x8
#define HWIO_APP_PROC_CFG_APPS_CFG_MISC0_BMSK                                                         0xc0
#define HWIO_APP_PROC_CFG_APPS_CFG_MISC0_SHFT                                                          0x6
#define HWIO_APP_PROC_CFG_APPS_CP15_DISABLE_BMSK                                                      0x20
#define HWIO_APP_PROC_CFG_APPS_CP15_DISABLE_SHFT                                                       0x5
#define HWIO_APP_PROC_CFG_APPS_CFG_NMFI_BMSK                                                          0x10
#define HWIO_APP_PROC_CFG_APPS_CFG_NMFI_SHFT                                                           0x4
#define HWIO_APP_PROC_CFG_SHARED_QSEE_SPNIDEN_BMSK                                                     0x8
#define HWIO_APP_PROC_CFG_SHARED_QSEE_SPNIDEN_SHFT                                                     0x3
#define HWIO_APP_PROC_CFG_SHARED_CP_NIDEN_BMSK                                                         0x4
#define HWIO_APP_PROC_CFG_SHARED_CP_NIDEN_SHFT                                                         0x2
#define HWIO_APP_PROC_CFG_SHARED_NS_NIDEN_BMSK                                                         0x2
#define HWIO_APP_PROC_CFG_SHARED_NS_NIDEN_SHFT                                                         0x1
#define HWIO_APP_PROC_CFG_APPS_NIDEN_BMSK                                                              0x1
#define HWIO_APP_PROC_CFG_APPS_NIDEN_SHFT                                                              0x0

#define HWIO_MSS_PROC_CFG_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006114)
#define HWIO_MSS_PROC_CFG_RMSK                                                                         0x1
#define HWIO_MSS_PROC_CFG_IN          \
        in_dword(HWIO_MSS_PROC_CFG_ADDR)
#define HWIO_MSS_PROC_CFG_INM(m)      \
        in_dword_masked(HWIO_MSS_PROC_CFG_ADDR, m)
#define HWIO_MSS_PROC_CFG_OUT(v)      \
        out_dword(HWIO_MSS_PROC_CFG_ADDR,v)
#define HWIO_MSS_PROC_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MSS_PROC_CFG_ADDR,m,v,HWIO_MSS_PROC_CFG_IN)
#define HWIO_MSS_PROC_CFG_SHARED_MSS_NIDEN_BMSK                                                        0x1
#define HWIO_MSS_PROC_CFG_SHARED_MSS_NIDEN_SHFT                                                        0x0

#define HWIO_QFPROM_CLK_CTL_ADDR                                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006118)
#define HWIO_QFPROM_CLK_CTL_RMSK                                                                       0x1
#define HWIO_QFPROM_CLK_CTL_IN          \
        in_dword(HWIO_QFPROM_CLK_CTL_ADDR)
#define HWIO_QFPROM_CLK_CTL_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CLK_CTL_ADDR, m)
#define HWIO_QFPROM_CLK_CTL_OUT(v)      \
        out_dword(HWIO_QFPROM_CLK_CTL_ADDR,v)
#define HWIO_QFPROM_CLK_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_CLK_CTL_ADDR,m,v,HWIO_QFPROM_CLK_CTL_IN)
#define HWIO_QFPROM_CLK_CTL_CLK_HALT_BMSK                                                              0x1
#define HWIO_QFPROM_CLK_CTL_CLK_HALT_SHFT                                                              0x0

#define HWIO_JTAG_ID_ADDR                                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006130)
#define HWIO_JTAG_ID_RMSK                                                                       0xffffffff
#define HWIO_JTAG_ID_IN          \
        in_dword(HWIO_JTAG_ID_ADDR)
#define HWIO_JTAG_ID_INM(m)      \
        in_dword_masked(HWIO_JTAG_ID_ADDR, m)
#define HWIO_JTAG_ID_JTAG_ID_BMSK                                                               0xffffffff
#define HWIO_JTAG_ID_JTAG_ID_SHFT                                                                      0x0

#define HWIO_SERIAL_NUM_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006134)
#define HWIO_SERIAL_NUM_RMSK                                                                    0xffffffff
#define HWIO_SERIAL_NUM_IN          \
        in_dword(HWIO_SERIAL_NUM_ADDR)
#define HWIO_SERIAL_NUM_INM(m)      \
        in_dword_masked(HWIO_SERIAL_NUM_ADDR, m)
#define HWIO_SERIAL_NUM_SERIAL_NUM_BMSK                                                         0xffffffff
#define HWIO_SERIAL_NUM_SERIAL_NUM_SHFT                                                                0x0

#define HWIO_OEM_ID_ADDR                                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006138)
#define HWIO_OEM_ID_RMSK                                                                        0xffffffff
#define HWIO_OEM_ID_IN          \
        in_dword(HWIO_OEM_ID_ADDR)
#define HWIO_OEM_ID_INM(m)      \
        in_dword_masked(HWIO_OEM_ID_ADDR, m)
#define HWIO_OEM_ID_OEM_ID_BMSK                                                                 0xffff0000
#define HWIO_OEM_ID_OEM_ID_SHFT                                                                       0x10
#define HWIO_OEM_ID_OEM_PRODUCT_ID_BMSK                                                             0xffff
#define HWIO_OEM_ID_OEM_PRODUCT_ID_SHFT                                                                0x0

#define HWIO_TEST_BUS_SEL_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000613c)
#define HWIO_TEST_BUS_SEL_RMSK                                                                         0x7
#define HWIO_TEST_BUS_SEL_IN          \
        in_dword(HWIO_TEST_BUS_SEL_ADDR)
#define HWIO_TEST_BUS_SEL_INM(m)      \
        in_dword_masked(HWIO_TEST_BUS_SEL_ADDR, m)
#define HWIO_TEST_BUS_SEL_OUT(v)      \
        out_dword(HWIO_TEST_BUS_SEL_ADDR,v)
#define HWIO_TEST_BUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TEST_BUS_SEL_ADDR,m,v,HWIO_TEST_BUS_SEL_IN)
#define HWIO_TEST_BUS_SEL_TEST_EN_BMSK                                                                 0x4
#define HWIO_TEST_BUS_SEL_TEST_EN_SHFT                                                                 0x2
#define HWIO_TEST_BUS_SEL_TEST_SELECT_BMSK                                                             0x3
#define HWIO_TEST_BUS_SEL_TEST_SELECT_SHFT                                                             0x0

#define HWIO_SPDM_DYN_SECURE_MODE_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006140)
#define HWIO_SPDM_DYN_SECURE_MODE_RMSK                                                                 0x1
#define HWIO_SPDM_DYN_SECURE_MODE_IN          \
        in_dword(HWIO_SPDM_DYN_SECURE_MODE_ADDR)
#define HWIO_SPDM_DYN_SECURE_MODE_INM(m)      \
        in_dword_masked(HWIO_SPDM_DYN_SECURE_MODE_ADDR, m)
#define HWIO_SPDM_DYN_SECURE_MODE_OUT(v)      \
        out_dword(HWIO_SPDM_DYN_SECURE_MODE_ADDR,v)
#define HWIO_SPDM_DYN_SECURE_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SPDM_DYN_SECURE_MODE_ADDR,m,v,HWIO_SPDM_DYN_SECURE_MODE_IN)
#define HWIO_SPDM_DYN_SECURE_MODE_SECURE_MODE_BMSK                                                     0x1
#define HWIO_SPDM_DYN_SECURE_MODE_SECURE_MODE_SHFT                                                     0x0

#define HWIO_CHIP_ID_ADDR                                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006144)
#define HWIO_CHIP_ID_RMSK                                                                           0xffff
#define HWIO_CHIP_ID_IN          \
        in_dword(HWIO_CHIP_ID_ADDR)
#define HWIO_CHIP_ID_INM(m)      \
        in_dword_masked(HWIO_CHIP_ID_ADDR, m)
#define HWIO_CHIP_ID_CHIP_ID_BMSK                                                                   0xffff
#define HWIO_CHIP_ID_CHIP_ID_SHFT                                                                      0x0

#define HWIO_OEM_IMAGE_ENCR_KEYn_ADDR(n)                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006150 + 0x4 * (n))
#define HWIO_OEM_IMAGE_ENCR_KEYn_RMSK                                                           0xffffffff
#define HWIO_OEM_IMAGE_ENCR_KEYn_MAXn                                                                    3
#define HWIO_OEM_IMAGE_ENCR_KEYn_INI(n)        \
        in_dword_masked(HWIO_OEM_IMAGE_ENCR_KEYn_ADDR(n), HWIO_OEM_IMAGE_ENCR_KEYn_RMSK)
#define HWIO_OEM_IMAGE_ENCR_KEYn_INMI(n,mask)    \
        in_dword_masked(HWIO_OEM_IMAGE_ENCR_KEYn_ADDR(n), mask)
#define HWIO_OEM_IMAGE_ENCR_KEYn_KEY_DATA0_BMSK                                                 0xffffffff
#define HWIO_OEM_IMAGE_ENCR_KEYn_KEY_DATA0_SHFT                                                        0x0

#define HWIO_IMAGE_ENCR_KEY1_0_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006160)
#define HWIO_IMAGE_ENCR_KEY1_0_RMSK                                                             0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_0_IN          \
        in_dword(HWIO_IMAGE_ENCR_KEY1_0_ADDR)
#define HWIO_IMAGE_ENCR_KEY1_0_INM(m)      \
        in_dword_masked(HWIO_IMAGE_ENCR_KEY1_0_ADDR, m)
#define HWIO_IMAGE_ENCR_KEY1_0_KEY_DATA0_BMSK                                                   0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_0_KEY_DATA0_SHFT                                                          0x0

#define HWIO_IMAGE_ENCR_KEY1_1_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006164)
#define HWIO_IMAGE_ENCR_KEY1_1_RMSK                                                             0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_1_IN          \
        in_dword(HWIO_IMAGE_ENCR_KEY1_1_ADDR)
#define HWIO_IMAGE_ENCR_KEY1_1_INM(m)      \
        in_dword_masked(HWIO_IMAGE_ENCR_KEY1_1_ADDR, m)
#define HWIO_IMAGE_ENCR_KEY1_1_KEY_DATA0_BMSK                                                   0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_1_KEY_DATA0_SHFT                                                          0x0

#define HWIO_IMAGE_ENCR_KEY1_2_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006168)
#define HWIO_IMAGE_ENCR_KEY1_2_RMSK                                                             0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_2_IN          \
        in_dword(HWIO_IMAGE_ENCR_KEY1_2_ADDR)
#define HWIO_IMAGE_ENCR_KEY1_2_INM(m)      \
        in_dword_masked(HWIO_IMAGE_ENCR_KEY1_2_ADDR, m)
#define HWIO_IMAGE_ENCR_KEY1_2_KEY_DATA0_BMSK                                                   0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_2_KEY_DATA0_SHFT                                                          0x0

#define HWIO_IMAGE_ENCR_KEY1_3_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000616c)
#define HWIO_IMAGE_ENCR_KEY1_3_RMSK                                                             0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_3_IN          \
        in_dword(HWIO_IMAGE_ENCR_KEY1_3_ADDR)
#define HWIO_IMAGE_ENCR_KEY1_3_INM(m)      \
        in_dword_masked(HWIO_IMAGE_ENCR_KEY1_3_ADDR, m)
#define HWIO_IMAGE_ENCR_KEY1_3_KEY_DATA0_BMSK                                                   0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_3_KEY_DATA0_SHFT                                                          0x0

#define HWIO_PK_HASH0_0_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006190)
#define HWIO_PK_HASH0_0_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_0_IN          \
        in_dword(HWIO_PK_HASH0_0_ADDR)
#define HWIO_PK_HASH0_0_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_0_ADDR, m)
#define HWIO_PK_HASH0_0_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_0_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_1_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006194)
#define HWIO_PK_HASH0_1_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_1_IN          \
        in_dword(HWIO_PK_HASH0_1_ADDR)
#define HWIO_PK_HASH0_1_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_1_ADDR, m)
#define HWIO_PK_HASH0_1_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_1_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_2_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006198)
#define HWIO_PK_HASH0_2_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_2_IN          \
        in_dword(HWIO_PK_HASH0_2_ADDR)
#define HWIO_PK_HASH0_2_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_2_ADDR, m)
#define HWIO_PK_HASH0_2_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_2_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_3_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000619c)
#define HWIO_PK_HASH0_3_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_3_IN          \
        in_dword(HWIO_PK_HASH0_3_ADDR)
#define HWIO_PK_HASH0_3_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_3_ADDR, m)
#define HWIO_PK_HASH0_3_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_3_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_4_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061a0)
#define HWIO_PK_HASH0_4_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_4_IN          \
        in_dword(HWIO_PK_HASH0_4_ADDR)
#define HWIO_PK_HASH0_4_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_4_ADDR, m)
#define HWIO_PK_HASH0_4_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_4_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_5_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061a4)
#define HWIO_PK_HASH0_5_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_5_IN          \
        in_dword(HWIO_PK_HASH0_5_ADDR)
#define HWIO_PK_HASH0_5_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_5_ADDR, m)
#define HWIO_PK_HASH0_5_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_5_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_6_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061a8)
#define HWIO_PK_HASH0_6_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_6_IN          \
        in_dword(HWIO_PK_HASH0_6_ADDR)
#define HWIO_PK_HASH0_6_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_6_ADDR, m)
#define HWIO_PK_HASH0_6_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_6_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_7_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061ac)
#define HWIO_PK_HASH0_7_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_7_IN          \
        in_dword(HWIO_PK_HASH0_7_ADDR)
#define HWIO_PK_HASH0_7_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_7_ADDR, m)
#define HWIO_PK_HASH0_7_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_7_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_8_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061b0)
#define HWIO_PK_HASH0_8_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_8_IN          \
        in_dword(HWIO_PK_HASH0_8_ADDR)
#define HWIO_PK_HASH0_8_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_8_ADDR, m)
#define HWIO_PK_HASH0_8_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_8_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_9_ADDR                                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061b4)
#define HWIO_PK_HASH0_9_RMSK                                                                    0xffffffff
#define HWIO_PK_HASH0_9_IN          \
        in_dword(HWIO_PK_HASH0_9_ADDR)
#define HWIO_PK_HASH0_9_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_9_ADDR, m)
#define HWIO_PK_HASH0_9_HASH_DATA0_BMSK                                                         0xffffffff
#define HWIO_PK_HASH0_9_HASH_DATA0_SHFT                                                                0x0

#define HWIO_PK_HASH0_10_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061b8)
#define HWIO_PK_HASH0_10_RMSK                                                                   0xffffffff
#define HWIO_PK_HASH0_10_IN          \
        in_dword(HWIO_PK_HASH0_10_ADDR)
#define HWIO_PK_HASH0_10_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_10_ADDR, m)
#define HWIO_PK_HASH0_10_HASH_DATA0_BMSK                                                        0xffffffff
#define HWIO_PK_HASH0_10_HASH_DATA0_SHFT                                                               0x0

#define HWIO_PK_HASH0_11_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061bc)
#define HWIO_PK_HASH0_11_RMSK                                                                   0xffffffff
#define HWIO_PK_HASH0_11_IN          \
        in_dword(HWIO_PK_HASH0_11_ADDR)
#define HWIO_PK_HASH0_11_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_11_ADDR, m)
#define HWIO_PK_HASH0_11_HASH_DATA0_BMSK                                                        0xffffffff
#define HWIO_PK_HASH0_11_HASH_DATA0_SHFT                                                               0x0

#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061f0)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_RMSK                                              0xffffffff
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_IN          \
        in_dword(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_INM(m)      \
        in_dword_masked(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR, m)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_OUT(v)      \
        out_dword(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR,v)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR,m,v,HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_IN)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION31_STICKY_BIT_BMSK                          0x80000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION31_STICKY_BIT_SHFT                                0x1f
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION30_STICKY_BIT_BMSK                          0x40000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION30_STICKY_BIT_SHFT                                0x1e
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION29_STICKY_BIT_BMSK                          0x20000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION29_STICKY_BIT_SHFT                                0x1d
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION28_STICKY_BIT_BMSK                          0x10000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION28_STICKY_BIT_SHFT                                0x1c
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION27_STICKY_BIT_BMSK                           0x8000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION27_STICKY_BIT_SHFT                                0x1b
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION26_STICKY_BIT_BMSK                           0x4000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION26_STICKY_BIT_SHFT                                0x1a
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION25_STICKY_BIT_BMSK                           0x2000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION25_STICKY_BIT_SHFT                                0x19
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION24_STICKY_BIT_BMSK                           0x1000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION24_STICKY_BIT_SHFT                                0x18
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION23_STICKY_BIT_BMSK                            0x800000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION23_STICKY_BIT_SHFT                                0x17
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION22_STICKY_BIT_BMSK                            0x400000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION22_STICKY_BIT_SHFT                                0x16
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION21_STICKY_BIT_BMSK                            0x200000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION21_STICKY_BIT_SHFT                                0x15
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION20_STICKY_BIT_BMSK                            0x100000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION20_STICKY_BIT_SHFT                                0x14
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION19_STICKY_BIT_BMSK                             0x80000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION19_STICKY_BIT_SHFT                                0x13
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION18_STICKY_BIT_BMSK                             0x40000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION18_STICKY_BIT_SHFT                                0x12
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION17_STICKY_BIT_BMSK                             0x20000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION17_STICKY_BIT_SHFT                                0x11
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION16_STICKY_BIT_BMSK                             0x10000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION16_STICKY_BIT_SHFT                                0x10
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION15_STICKY_BIT_BMSK                              0x8000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION15_STICKY_BIT_SHFT                                 0xf
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION14_STICKY_BIT_BMSK                              0x4000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION14_STICKY_BIT_SHFT                                 0xe
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION13_STICKY_BIT_BMSK                              0x2000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION13_STICKY_BIT_SHFT                                 0xd
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION12_STICKY_BIT_BMSK                              0x1000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION12_STICKY_BIT_SHFT                                 0xc
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION11_STICKY_BIT_BMSK                               0x800
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION11_STICKY_BIT_SHFT                                 0xb
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION10_STICKY_BIT_BMSK                               0x400
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION10_STICKY_BIT_SHFT                                 0xa
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION9_STICKY_BIT_BMSK                                0x200
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION9_STICKY_BIT_SHFT                                  0x9
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION8_STICKY_BIT_BMSK                                0x100
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION8_STICKY_BIT_SHFT                                  0x8
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION7_STICKY_BIT_BMSK                                 0x80
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION7_STICKY_BIT_SHFT                                  0x7
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION6_STICKY_BIT_BMSK                                 0x40
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION6_STICKY_BIT_SHFT                                  0x6
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION5_STICKY_BIT_BMSK                                 0x20
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION5_STICKY_BIT_SHFT                                  0x5
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION4_STICKY_BIT_BMSK                                 0x10
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION4_STICKY_BIT_SHFT                                  0x4
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION3_STICKY_BIT_BMSK                                  0x8
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION3_STICKY_BIT_SHFT                                  0x3
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION2_STICKY_BIT_BMSK                                  0x4
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION2_STICKY_BIT_SHFT                                  0x2
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION1_STICKY_BIT_BMSK                                  0x2
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION1_STICKY_BIT_SHFT                                  0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION0_STICKY_BIT_BMSK                                  0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION0_STICKY_BIT_SHFT                                  0x0

#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061f4)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_RMSK                                              0xffffffff
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_IN          \
        in_dword(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_INM(m)      \
        in_dword_masked(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR, m)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_OUT(v)      \
        out_dword(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR,v)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR,m,v,HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_IN)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_RSVD0_BMSK                                        0xffffffff
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_RSVD0_SHFT                                               0x0

#define HWIO_ANTI_ROLLBACK_1_0_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006200)
#define HWIO_ANTI_ROLLBACK_1_0_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_1_0_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_1_0_ADDR)
#define HWIO_ANTI_ROLLBACK_1_0_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_1_0_ADDR, m)
#define HWIO_ANTI_ROLLBACK_1_0_XBL0_BMSK                                                        0xffffffff
#define HWIO_ANTI_ROLLBACK_1_0_XBL0_SHFT                                                               0x0

#define HWIO_ANTI_ROLLBACK_1_1_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006204)
#define HWIO_ANTI_ROLLBACK_1_1_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_1_1_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_1_1_ADDR)
#define HWIO_ANTI_ROLLBACK_1_1_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_1_1_ADDR, m)
#define HWIO_ANTI_ROLLBACK_1_1_XBL1_BMSK                                                        0xffffffff
#define HWIO_ANTI_ROLLBACK_1_1_XBL1_SHFT                                                               0x0

#define HWIO_ANTI_ROLLBACK_2_0_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006208)
#define HWIO_ANTI_ROLLBACK_2_0_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_2_0_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_2_0_ADDR)
#define HWIO_ANTI_ROLLBACK_2_0_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_2_0_ADDR, m)
#define HWIO_ANTI_ROLLBACK_2_0_PIL_SUBSYSTEM_31_0_BMSK                                          0xffffffff
#define HWIO_ANTI_ROLLBACK_2_0_PIL_SUBSYSTEM_31_0_SHFT                                                 0x0

#define HWIO_ANTI_ROLLBACK_2_1_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000620c)
#define HWIO_ANTI_ROLLBACK_2_1_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_2_1_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_2_1_ADDR)
#define HWIO_ANTI_ROLLBACK_2_1_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_2_1_ADDR, m)
#define HWIO_ANTI_ROLLBACK_2_1_XBL_SEC_BMSK                                                     0xfe000000
#define HWIO_ANTI_ROLLBACK_2_1_XBL_SEC_SHFT                                                           0x19
#define HWIO_ANTI_ROLLBACK_2_1_AOP_BMSK                                                          0x1fe0000
#define HWIO_ANTI_ROLLBACK_2_1_AOP_SHFT                                                               0x11
#define HWIO_ANTI_ROLLBACK_2_1_TZ_BMSK                                                             0x1ffff
#define HWIO_ANTI_ROLLBACK_2_1_TZ_SHFT                                                                 0x0

#define HWIO_ANTI_ROLLBACK_3_0_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006210)
#define HWIO_ANTI_ROLLBACK_3_0_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_3_0_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_3_0_ADDR)
#define HWIO_ANTI_ROLLBACK_3_0_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_3_0_ADDR, m)
#define HWIO_ANTI_ROLLBACK_3_0_RSVD1_BMSK                                                       0xc0000000
#define HWIO_ANTI_ROLLBACK_3_0_RSVD1_SHFT                                                             0x1e
#define HWIO_ANTI_ROLLBACK_3_0_TQS_HASH_ACTIVE_BMSK                                             0x3e000000
#define HWIO_ANTI_ROLLBACK_3_0_TQS_HASH_ACTIVE_SHFT                                                   0x19
#define HWIO_ANTI_ROLLBACK_3_0_RPMB_KEY_PROVISIONED_BMSK                                         0x1000000
#define HWIO_ANTI_ROLLBACK_3_0_RPMB_KEY_PROVISIONED_SHFT                                              0x18
#define HWIO_ANTI_ROLLBACK_3_0_PIL_SUBSYSTEM_47_32_BMSK                                           0xffff00
#define HWIO_ANTI_ROLLBACK_3_0_PIL_SUBSYSTEM_47_32_SHFT                                                0x8
#define HWIO_ANTI_ROLLBACK_3_0_SAFESWITCH_BMSK                                                        0xff
#define HWIO_ANTI_ROLLBACK_3_0_SAFESWITCH_SHFT                                                         0x0

#define HWIO_ANTI_ROLLBACK_3_1_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006214)
#define HWIO_ANTI_ROLLBACK_3_1_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_3_1_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_3_1_ADDR)
#define HWIO_ANTI_ROLLBACK_3_1_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_3_1_ADDR, m)
#define HWIO_ANTI_ROLLBACK_3_1_RSVD1_BMSK                                                       0xf0000000
#define HWIO_ANTI_ROLLBACK_3_1_RSVD1_SHFT                                                             0x1c
#define HWIO_ANTI_ROLLBACK_3_1_DEVICE_CFG_BMSK                                                   0xffe0000
#define HWIO_ANTI_ROLLBACK_3_1_DEVICE_CFG_SHFT                                                        0x11
#define HWIO_ANTI_ROLLBACK_3_1_DEBUG_POLICY_BMSK                                                   0x1f000
#define HWIO_ANTI_ROLLBACK_3_1_DEBUG_POLICY_SHFT                                                       0xc
#define HWIO_ANTI_ROLLBACK_3_1_HYPERVISOR_BMSK                                                       0xfff
#define HWIO_ANTI_ROLLBACK_3_1_HYPERVISOR_SHFT                                                         0x0

#define HWIO_ANTI_ROLLBACK_4_0_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006218)
#define HWIO_ANTI_ROLLBACK_4_0_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_4_0_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_4_0_ADDR)
#define HWIO_ANTI_ROLLBACK_4_0_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_4_0_ADDR, m)
#define HWIO_ANTI_ROLLBACK_4_0_MSS_BMSK                                                         0xffff0000
#define HWIO_ANTI_ROLLBACK_4_0_MSS_SHFT                                                               0x10
#define HWIO_ANTI_ROLLBACK_4_0_MISC_BMSK                                                            0xffff
#define HWIO_ANTI_ROLLBACK_4_0_MISC_SHFT                                                               0x0

#define HWIO_ANTI_ROLLBACK_4_1_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000621c)
#define HWIO_ANTI_ROLLBACK_4_1_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_4_1_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_4_1_ADDR)
#define HWIO_ANTI_ROLLBACK_4_1_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_4_1_ADDR, m)
#define HWIO_ANTI_ROLLBACK_4_1_SIMLOCK_BMSK                                                     0x80000000
#define HWIO_ANTI_ROLLBACK_4_1_SIMLOCK_SHFT                                                           0x1f
#define HWIO_ANTI_ROLLBACK_4_1_RSVD0_BMSK                                                       0x7ffffff0
#define HWIO_ANTI_ROLLBACK_4_1_RSVD0_SHFT                                                              0x4
#define HWIO_ANTI_ROLLBACK_4_1_ROOT_CERT_PK_HASH_INDEX_BMSK                                            0xf
#define HWIO_ANTI_ROLLBACK_4_1_ROOT_CERT_PK_HASH_INDEX_SHFT                                            0x0

#define HWIO_ANTI_ROLLBACK_5_0_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006220)
#define HWIO_ANTI_ROLLBACK_5_0_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_5_0_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_5_0_ADDR)
#define HWIO_ANTI_ROLLBACK_5_0_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_5_0_ADDR, m)
#define HWIO_ANTI_ROLLBACK_5_0_MISC_BMSK                                                        0xffffffff
#define HWIO_ANTI_ROLLBACK_5_0_MISC_SHFT                                                               0x0

#define HWIO_ANTI_ROLLBACK_5_1_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006224)
#define HWIO_ANTI_ROLLBACK_5_1_RMSK                                                             0xffffffff
#define HWIO_ANTI_ROLLBACK_5_1_IN          \
        in_dword(HWIO_ANTI_ROLLBACK_5_1_ADDR)
#define HWIO_ANTI_ROLLBACK_5_1_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_5_1_ADDR, m)
#define HWIO_ANTI_ROLLBACK_5_1_MISC_BMSK                                                        0xffffffff
#define HWIO_ANTI_ROLLBACK_5_1_MISC_SHFT                                                               0x0

#define HWIO_MRC_2_0_0_ADDR                                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006250)
#define HWIO_MRC_2_0_0_RMSK                                                                     0xffffffff
#define HWIO_MRC_2_0_0_IN          \
        in_dword(HWIO_MRC_2_0_0_ADDR)
#define HWIO_MRC_2_0_0_INM(m)      \
        in_dword_masked(HWIO_MRC_2_0_0_ADDR, m)
#define HWIO_MRC_2_0_0_RSVD0_BMSK                                                               0xfffffff0
#define HWIO_MRC_2_0_0_RSVD0_SHFT                                                                      0x4
#define HWIO_MRC_2_0_0_ROOT_CERT_ACTIVATION_LIST_BMSK                                                  0xf
#define HWIO_MRC_2_0_0_ROOT_CERT_ACTIVATION_LIST_SHFT                                                  0x0

#define HWIO_MRC_2_0_1_ADDR                                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006254)
#define HWIO_MRC_2_0_1_RMSK                                                                     0xffffffff
#define HWIO_MRC_2_0_1_IN          \
        in_dword(HWIO_MRC_2_0_1_ADDR)
#define HWIO_MRC_2_0_1_INM(m)      \
        in_dword_masked(HWIO_MRC_2_0_1_ADDR, m)
#define HWIO_MRC_2_0_1_RSVD1_BMSK                                                               0xfffffffe
#define HWIO_MRC_2_0_1_RSVD1_SHFT                                                                      0x1
#define HWIO_MRC_2_0_1_CURRENT_UIE_KEY_SEL_BMSK                                                        0x1
#define HWIO_MRC_2_0_1_CURRENT_UIE_KEY_SEL_SHFT                                                        0x0

#define HWIO_MRC_2_0_2_ADDR                                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006258)
#define HWIO_MRC_2_0_2_RMSK                                                                     0xffffffff
#define HWIO_MRC_2_0_2_IN          \
        in_dword(HWIO_MRC_2_0_2_ADDR)
#define HWIO_MRC_2_0_2_INM(m)      \
        in_dword_masked(HWIO_MRC_2_0_2_ADDR, m)
#define HWIO_MRC_2_0_2_RSVD0_BMSK                                                               0xfffffff0
#define HWIO_MRC_2_0_2_RSVD0_SHFT                                                                      0x4
#define HWIO_MRC_2_0_2_ROOT_CERT_REVOCATION_LIST_BMSK                                                  0xf
#define HWIO_MRC_2_0_2_ROOT_CERT_REVOCATION_LIST_SHFT                                                  0x0

#define HWIO_MRC_2_0_3_ADDR                                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000625c)
#define HWIO_MRC_2_0_3_RMSK                                                                     0xffffffff
#define HWIO_MRC_2_0_3_IN          \
        in_dword(HWIO_MRC_2_0_3_ADDR)
#define HWIO_MRC_2_0_3_INM(m)      \
        in_dword_masked(HWIO_MRC_2_0_3_ADDR, m)
#define HWIO_MRC_2_0_3_RSVD0_BMSK                                                               0xffffffff
#define HWIO_MRC_2_0_3_RSVD0_SHFT                                                                      0x0

#define HWIO_CRYPTO_LIB_VERSION_ADDR                                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006300)
#define HWIO_CRYPTO_LIB_VERSION_RMSK                                                            0xffffffff
#define HWIO_CRYPTO_LIB_VERSION_IN          \
        in_dword(HWIO_CRYPTO_LIB_VERSION_ADDR)
#define HWIO_CRYPTO_LIB_VERSION_INM(m)      \
        in_dword_masked(HWIO_CRYPTO_LIB_VERSION_ADDR, m)
#define HWIO_CRYPTO_LIB_VERSION_VERSION_BMSK                                                    0xffffffff
#define HWIO_CRYPTO_LIB_VERSION_VERSION_SHFT                                                           0x0

#define HWIO_LCM_0_ADDR                                                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006304)
#define HWIO_LCM_0_RMSK                                                                         0xffffffff
#define HWIO_LCM_0_IN          \
        in_dword(HWIO_LCM_0_ADDR)
#define HWIO_LCM_0_INM(m)      \
        in_dword_masked(HWIO_LCM_0_ADDR, m)
#define HWIO_LCM_0_DISABLE_LCM_BMSK                                                             0x80000000
#define HWIO_LCM_0_DISABLE_LCM_SHFT                                                                   0x1f
#define HWIO_LCM_0_DISABLE_LCM_STATE_TRANSITION_BMSK                                            0x40000000
#define HWIO_LCM_0_DISABLE_LCM_STATE_TRANSITION_SHFT                                                  0x1e
#define HWIO_LCM_0_DISABLE_SECURE_PHK_BMSK                                                      0x20000000
#define HWIO_LCM_0_DISABLE_SECURE_PHK_SHFT                                                            0x1d
#define HWIO_LCM_0_RSVD_BMSK                                                                    0x1fffff00
#define HWIO_LCM_0_RSVD_SHFT                                                                           0x8
#define HWIO_LCM_0_DEBUG_STATE_BMSK                                                                   0x80
#define HWIO_LCM_0_DEBUG_STATE_SHFT                                                                    0x7
#define HWIO_LCM_0_ILLEGAL_STATE_BMSK                                                                 0x40
#define HWIO_LCM_0_ILLEGAL_STATE_SHFT                                                                  0x6
#define HWIO_LCM_0_QC_EXTERNAL_BMSK                                                                   0x20
#define HWIO_LCM_0_QC_EXTERNAL_SHFT                                                                    0x5
#define HWIO_LCM_0_QC_INTERNAL_BMSK                                                                   0x10
#define HWIO_LCM_0_QC_INTERNAL_SHFT                                                                    0x4
#define HWIO_LCM_0_QC_FEAT_CONFIG_BMSK                                                                 0x8
#define HWIO_LCM_0_QC_FEAT_CONFIG_SHFT                                                                 0x3
#define HWIO_LCM_0_HW_TEST_BMSK                                                                        0x4
#define HWIO_LCM_0_HW_TEST_SHFT                                                                        0x2
#define HWIO_LCM_0_SOC_PERSO_BMSK                                                                      0x2
#define HWIO_LCM_0_SOC_PERSO_SHFT                                                                      0x1
#define HWIO_LCM_0_BLANK_BMSK                                                                          0x1
#define HWIO_LCM_0_BLANK_SHFT                                                                          0x0

#define HWIO_LCM_1_ADDR                                                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006308)
#define HWIO_LCM_1_RMSK                                                                         0xffffffff
#define HWIO_LCM_1_IN          \
        in_dword(HWIO_LCM_1_ADDR)
#define HWIO_LCM_1_INM(m)      \
        in_dword_masked(HWIO_LCM_1_ADDR, m)
#define HWIO_LCM_1_LCM_DATA1_BMSK                                                               0xffffffff
#define HWIO_LCM_1_LCM_DATA1_SHFT                                                                      0x0

#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006400)
#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_RMSK                                                    0xffffffff
#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_IN          \
        in_dword(HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDR)
#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_INM(m)      \
        in_dword_masked(HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDR, m)
#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_OUT(v)      \
        out_dword(HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDR,v)
#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDR,m,v,HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_IN)
#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDRESS_BMSK                                            0xffffffff
#define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDRESS_SHFT                                                   0x0

/*----------------------------------------------------------------------------
 * MODULE: GCC_CLK_CTL_REG
 *--------------------------------------------------------------------------*/

#define GCC_CLK_CTL_REG_REG_BASE                                                                   (CLK_CTL_BASE      + 0x00000000)
#define GCC_CLK_CTL_REG_REG_BASE_SIZE                                                              0x1f0000
#define GCC_CLK_CTL_REG_REG_BASE_USED                                                              0x9c100

#define HWIO_GCC_GPLL0_MODE_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00000000)
#define HWIO_GCC_GPLL0_MODE_RMSK                                                                   0xffffffff
#define HWIO_GCC_GPLL0_MODE_IN          \
        in_dword(HWIO_GCC_GPLL0_MODE_ADDR)
#define HWIO_GCC_GPLL0_MODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_MODE_ADDR, m)
#define HWIO_GCC_GPLL0_MODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_MODE_ADDR,v)
#define HWIO_GCC_GPLL0_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_MODE_ADDR,m,v,HWIO_GCC_GPLL0_MODE_IN)
#define HWIO_GCC_GPLL0_MODE_PLL_LOCK_DET_BMSK                                                      0x80000000
#define HWIO_GCC_GPLL0_MODE_PLL_LOCK_DET_SHFT                                                            0x1f
#define HWIO_GCC_GPLL0_MODE_PLL_ACTIVE_FLAG_BMSK                                                   0x40000000
#define HWIO_GCC_GPLL0_MODE_PLL_ACTIVE_FLAG_SHFT                                                         0x1e
#define HWIO_GCC_GPLL0_MODE_PLL_ACK_LATCH_BMSK                                                     0x20000000
#define HWIO_GCC_GPLL0_MODE_PLL_ACK_LATCH_SHFT                                                           0x1d
#define HWIO_GCC_GPLL0_MODE_PLL_LOCK_DET_FINE_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL0_MODE_PLL_LOCK_DET_FINE_SHFT                                                       0x1c
#define HWIO_GCC_GPLL0_MODE_PCAL_DONE_BMSK                                                          0x8000000
#define HWIO_GCC_GPLL0_MODE_PCAL_DONE_SHFT                                                               0x1b
#define HWIO_GCC_GPLL0_MODE_RESERVE_BITS26_25_BMSK                                                  0x6000000
#define HWIO_GCC_GPLL0_MODE_RESERVE_BITS26_25_SHFT                                                       0x19
#define HWIO_GCC_GPLL0_MODE_FSM_LEGACY_MODE_BMSK                                                    0x1000000
#define HWIO_GCC_GPLL0_MODE_FSM_LEGACY_MODE_SHFT                                                         0x18
#define HWIO_GCC_GPLL0_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_BMSK                                          0x800000
#define HWIO_GCC_GPLL0_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_SHFT                                              0x17
#define HWIO_GCC_GPLL0_MODE_PLL_UPDATE_BMSK                                                          0x400000
#define HWIO_GCC_GPLL0_MODE_PLL_UPDATE_SHFT                                                              0x16
#define HWIO_GCC_GPLL0_MODE_PLL_VOTE_FSM_RESET_BMSK                                                  0x200000
#define HWIO_GCC_GPLL0_MODE_PLL_VOTE_FSM_RESET_SHFT                                                      0x15
#define HWIO_GCC_GPLL0_MODE_PLL_VOTE_FSM_ENA_BMSK                                                    0x100000
#define HWIO_GCC_GPLL0_MODE_PLL_VOTE_FSM_ENA_SHFT                                                        0x14
#define HWIO_GCC_GPLL0_MODE_PLL_BIAS_COUNT_BMSK                                                       0xfc000
#define HWIO_GCC_GPLL0_MODE_PLL_BIAS_COUNT_SHFT                                                           0xe
#define HWIO_GCC_GPLL0_MODE_PLL_LOCK_COUNT_BMSK                                                        0x3f00
#define HWIO_GCC_GPLL0_MODE_PLL_LOCK_COUNT_SHFT                                                           0x8
#define HWIO_GCC_GPLL0_MODE_RESERVE_BIT7_BMSK                                                            0x80
#define HWIO_GCC_GPLL0_MODE_RESERVE_BIT7_SHFT                                                             0x7
#define HWIO_GCC_GPLL0_MODE_OUT_TEST_HW_CTL_BMSK                                                         0x40
#define HWIO_GCC_GPLL0_MODE_OUT_TEST_HW_CTL_SHFT                                                          0x6
#define HWIO_GCC_GPLL0_MODE_OUT_ODD_HW_CTL_BMSK                                                          0x20
#define HWIO_GCC_GPLL0_MODE_OUT_ODD_HW_CTL_SHFT                                                           0x5
#define HWIO_GCC_GPLL0_MODE_OUT_EVEN_HW_CTL_BMSK                                                         0x10
#define HWIO_GCC_GPLL0_MODE_OUT_EVEN_HW_CTL_SHFT                                                          0x4
#define HWIO_GCC_GPLL0_MODE_OUT_MAIN_HW_CTL_BMSK                                                          0x8
#define HWIO_GCC_GPLL0_MODE_OUT_MAIN_HW_CTL_SHFT                                                          0x3
#define HWIO_GCC_GPLL0_MODE_PLL_RESET_N_BMSK                                                              0x4
#define HWIO_GCC_GPLL0_MODE_PLL_RESET_N_SHFT                                                              0x2
#define HWIO_GCC_GPLL0_MODE_RESERVE_BIT1_BMSK                                                             0x2
#define HWIO_GCC_GPLL0_MODE_RESERVE_BIT1_SHFT                                                             0x1
#define HWIO_GCC_GPLL0_MODE_PLL_OUTCTRL_BMSK                                                              0x1
#define HWIO_GCC_GPLL0_MODE_PLL_OUTCTRL_SHFT                                                              0x0

#define HWIO_GCC_GPLL0_L_VAL_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00000004)
#define HWIO_GCC_GPLL0_L_VAL_RMSK                                                                      0xffff
#define HWIO_GCC_GPLL0_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL0_L_VAL_ADDR)
#define HWIO_GCC_GPLL0_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL0_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL0_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_L_VAL_ADDR,m,v,HWIO_GCC_GPLL0_L_VAL_IN)
#define HWIO_GCC_GPLL0_L_VAL_PLL_L_BMSK                                                                0xffff
#define HWIO_GCC_GPLL0_L_VAL_PLL_L_SHFT                                                                   0x0

#define HWIO_GCC_GPLL0_CAL_L_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00000008)
#define HWIO_GCC_GPLL0_CAL_L_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL0_CAL_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL0_CAL_L_VAL_ADDR)
#define HWIO_GCC_GPLL0_CAL_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_CAL_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL0_CAL_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_CAL_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL0_CAL_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_CAL_L_VAL_ADDR,m,v,HWIO_GCC_GPLL0_CAL_L_VAL_IN)
#define HWIO_GCC_GPLL0_CAL_L_VAL_PLL_CAL_L_BMSK                                                        0xffff
#define HWIO_GCC_GPLL0_CAL_L_VAL_PLL_CAL_L_SHFT                                                           0x0

#define HWIO_GCC_GPLL0_USER_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0000000c)
#define HWIO_GCC_GPLL0_USER_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL0_USER_CTL_IN          \
        in_dword(HWIO_GCC_GPLL0_USER_CTL_ADDR)
#define HWIO_GCC_GPLL0_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_USER_CTL_ADDR, m)
#define HWIO_GCC_GPLL0_USER_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_USER_CTL_ADDR,v)
#define HWIO_GCC_GPLL0_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_USER_CTL_ADDR,m,v,HWIO_GCC_GPLL0_USER_CTL_IN)
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT31_BMSK                                                 0x80000000
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT31_SHFT                                                       0x1f
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT30_BMSK                                                 0x40000000
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT30_SHFT                                                       0x1e
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT29_BMSK                                                 0x20000000
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT29_SHFT                                                       0x1d
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT28_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT28_SHFT                                                       0x1c
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT27_BMSK                                                  0x8000000
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT27_SHFT                                                       0x1b
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT26_BMSK                                                  0x4000000
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT26_SHFT                                                       0x1a
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT25_BMSK                                                  0x2000000
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT25_SHFT                                                       0x19
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT24_BMSK                                                  0x1000000
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT24_SHFT                                                       0x18
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT23_BMSK                                                   0x800000
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT23_SHFT                                                       0x17
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT22_BMSK                                                   0x400000
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT22_SHFT                                                       0x16
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT21_BMSK                                                   0x200000
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT21_SHFT                                                       0x15
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT20_BMSK                                                   0x100000
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT20_SHFT                                                       0x14
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL0_USER_CTL_PRE_DIV_RATIO_BMSK                                                    0x70000
#define HWIO_GCC_GPLL0_USER_CTL_PRE_DIV_RATIO_SHFT                                                       0x10
#define HWIO_GCC_GPLL0_USER_CTL_POST_DIV_RATIO_ODD_BMSK                                                0xf000
#define HWIO_GCC_GPLL0_USER_CTL_POST_DIV_RATIO_ODD_SHFT                                                   0xc
#define HWIO_GCC_GPLL0_USER_CTL_POST_DIV_RATIO_EVEN_BMSK                                                0xf00
#define HWIO_GCC_GPLL0_USER_CTL_POST_DIV_RATIO_EVEN_SHFT                                                  0x8
#define HWIO_GCC_GPLL0_USER_CTL_OUT_CLK_POLARITY_BMSK                                                    0x80
#define HWIO_GCC_GPLL0_USER_CTL_OUT_CLK_POLARITY_SHFT                                                     0x7
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT6_BMSK                                                        0x40
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT6_SHFT                                                         0x6
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT5_BMSK                                                        0x20
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT5_SHFT                                                         0x5
#define HWIO_GCC_GPLL0_USER_CTL_PLLOUT_TEST_BMSK                                                         0x10
#define HWIO_GCC_GPLL0_USER_CTL_PLLOUT_TEST_SHFT                                                          0x4
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT3_BMSK                                                         0x8
#define HWIO_GCC_GPLL0_USER_CTL_RESERVE_BIT3_SHFT                                                         0x3
#define HWIO_GCC_GPLL0_USER_CTL_PLLOUT_ODD_BMSK                                                           0x4
#define HWIO_GCC_GPLL0_USER_CTL_PLLOUT_ODD_SHFT                                                           0x2
#define HWIO_GCC_GPLL0_USER_CTL_PLLOUT_EVEN_BMSK                                                          0x2
#define HWIO_GCC_GPLL0_USER_CTL_PLLOUT_EVEN_SHFT                                                          0x1
#define HWIO_GCC_GPLL0_USER_CTL_PLLOUT_MAIN_BMSK                                                          0x1
#define HWIO_GCC_GPLL0_USER_CTL_PLLOUT_MAIN_SHFT                                                          0x0

#define HWIO_GCC_GPLL0_USER_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00000010)
#define HWIO_GCC_GPLL0_USER_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL0_USER_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL0_USER_CTL_U_ADDR)
#define HWIO_GCC_GPLL0_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_USER_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL0_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_USER_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL0_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_USER_CTL_U_ADDR,m,v,HWIO_GCC_GPLL0_USER_CTL_U_IN)
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT63_BMSK                                               0x80000000
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT63_SHFT                                                     0x1f
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT62_BMSK                                               0x40000000
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT62_SHFT                                                     0x1e
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT61_BMSK                                               0x20000000
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT61_SHFT                                                     0x1d
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT60_BMSK                                               0x10000000
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT60_SHFT                                                     0x1c
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT59_BMSK                                                0x8000000
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT59_SHFT                                                     0x1b
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT58_BMSK                                                0x4000000
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT58_SHFT                                                     0x1a
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT57_BMSK                                                0x2000000
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT57_SHFT                                                     0x19
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT56_BMSK                                                0x1000000
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT56_SHFT                                                     0x18
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT55_BMSK                                                 0x800000
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT55_SHFT                                                     0x17
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT54_BMSK                                                 0x400000
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT54_SHFT                                                     0x16
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT53_BMSK                                                 0x200000
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT53_SHFT                                                     0x15
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT52_BMSK                                                 0x100000
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT52_SHFT                                                     0x14
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT51_BMSK                                                  0x80000
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT51_SHFT                                                     0x13
#define HWIO_GCC_GPLL0_USER_CTL_U_LOCK_DETECTOR_SELECTION_BMSK                                        0x40000
#define HWIO_GCC_GPLL0_USER_CTL_U_LOCK_DETECTOR_SELECTION_SHFT                                           0x12
#define HWIO_GCC_GPLL0_USER_CTL_U_TYPE_2_MODE_SELECTION_BMSK                                          0x20000
#define HWIO_GCC_GPLL0_USER_CTL_U_TYPE_2_MODE_SELECTION_SHFT                                             0x11
#define HWIO_GCC_GPLL0_USER_CTL_U_BANG_BANG_MODE_SELECTION_BMSK                                       0x10000
#define HWIO_GCC_GPLL0_USER_CTL_U_BANG_BANG_MODE_SELECTION_SHFT                                          0x10
#define HWIO_GCC_GPLL0_USER_CTL_U_FRAC_FORMAT_SEL_BMSK                                                 0x8000
#define HWIO_GCC_GPLL0_USER_CTL_U_FRAC_FORMAT_SEL_SHFT                                                    0xf
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT46_BMSK                                                   0x4000
#define HWIO_GCC_GPLL0_USER_CTL_U_RESERVE_BIT46_SHFT                                                      0xe
#define HWIO_GCC_GPLL0_USER_CTL_U_REF_CLK_AT_OUT_BMSK                                                  0x2000
#define HWIO_GCC_GPLL0_USER_CTL_U_REF_CLK_AT_OUT_SHFT                                                     0xd
#define HWIO_GCC_GPLL0_USER_CTL_U_SCALE_FREQ_ON_RESTART_BMSK                                           0x1800
#define HWIO_GCC_GPLL0_USER_CTL_U_SCALE_FREQ_ON_RESTART_SHFT                                              0xb
#define HWIO_GCC_GPLL0_USER_CTL_U_LATCH_INTERFACE_BYPASS_BMSK                                           0x400
#define HWIO_GCC_GPLL0_USER_CTL_U_LATCH_INTERFACE_BYPASS_SHFT                                             0xa
#define HWIO_GCC_GPLL0_USER_CTL_U_STATUS_REGISTER_BMSK                                                  0x3e0
#define HWIO_GCC_GPLL0_USER_CTL_U_STATUS_REGISTER_SHFT                                                    0x5
#define HWIO_GCC_GPLL0_USER_CTL_U_WRITE_STATE_EN_BMSK                                                    0x10
#define HWIO_GCC_GPLL0_USER_CTL_U_WRITE_STATE_EN_SHFT                                                     0x4
#define HWIO_GCC_GPLL0_USER_CTL_U_CALIB_CTRL_BMSK                                                         0xe
#define HWIO_GCC_GPLL0_USER_CTL_U_CALIB_CTRL_SHFT                                                         0x1
#define HWIO_GCC_GPLL0_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_BMSK                                             0x1
#define HWIO_GCC_GPLL0_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_SHFT                                             0x0

#define HWIO_GCC_GPLL0_USER_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00000014)
#define HWIO_GCC_GPLL0_USER_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL0_USER_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL0_USER_CTL_U1_ADDR)
#define HWIO_GCC_GPLL0_USER_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_USER_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL0_USER_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_USER_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL0_USER_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_USER_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL0_USER_CTL_U1_IN)
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT93_BMSK                                              0x20000000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT93_SHFT                                                    0x1d
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT92_BMSK                                              0x10000000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT92_SHFT                                                    0x1c
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT86_BMSK                                                0x400000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT86_SHFT                                                    0x16
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT82_BMSK                                                 0x40000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT82_SHFT                                                    0x12
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT81_BMSK                                                 0x20000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT81_SHFT                                                    0x11
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT80_BMSK                                                 0x10000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT80_SHFT                                                    0x10
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT79_BMSK                                                  0x8000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT79_SHFT                                                     0xf
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT78_BMSK                                                  0x4000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT78_SHFT                                                     0xe
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT77_BMSK                                                  0x2000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT77_SHFT                                                     0xd
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT71_BMSK                                                    0x80
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT71_SHFT                                                     0x7
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT70_BMSK                                                    0x40
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT70_SHFT                                                     0x6
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT69_BMSK                                                    0x20
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT69_SHFT                                                     0x5
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT65_BMSK                                                     0x2
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT65_SHFT                                                     0x1
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT64_BMSK                                                     0x1
#define HWIO_GCC_GPLL0_USER_CTL_U1_RESERVE_BIT64_SHFT                                                     0x0

#define HWIO_GCC_GPLL0_CONFIG_CTL_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00000018)
#define HWIO_GCC_GPLL0_CONFIG_CTL_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL0_CONFIG_CTL_IN          \
        in_dword(HWIO_GCC_GPLL0_CONFIG_CTL_ADDR)
#define HWIO_GCC_GPLL0_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_CONFIG_CTL_ADDR, m)
#define HWIO_GCC_GPLL0_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_CONFIG_CTL_ADDR,v)
#define HWIO_GCC_GPLL0_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_CONFIG_CTL_ADDR,m,v,HWIO_GCC_GPLL0_CONFIG_CTL_IN)
#define HWIO_GCC_GPLL0_CONFIG_CTL_FINE_LDC_THRESHOLD_BMSK                                          0xfc000000
#define HWIO_GCC_GPLL0_CONFIG_CTL_FINE_LDC_THRESHOLD_SHFT                                                0x1a
#define HWIO_GCC_GPLL0_CONFIG_CTL_COARSE_LDC_THRESHOLD_BMSK                                         0x3c00000
#define HWIO_GCC_GPLL0_CONFIG_CTL_COARSE_LDC_THRESHOLD_SHFT                                              0x16
#define HWIO_GCC_GPLL0_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_BMSK                                 0x3c0000
#define HWIO_GCC_GPLL0_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_SHFT                                     0x12
#define HWIO_GCC_GPLL0_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_BMSK                                  0x3c000
#define HWIO_GCC_GPLL0_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_SHFT                                      0xe
#define HWIO_GCC_GPLL0_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_BMSK                                         0x3800
#define HWIO_GCC_GPLL0_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_SHFT                                            0xb
#define HWIO_GCC_GPLL0_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_BMSK                                        0x700
#define HWIO_GCC_GPLL0_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_SHFT                                          0x8
#define HWIO_GCC_GPLL0_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_BMSK                                              0xf0
#define HWIO_GCC_GPLL0_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_SHFT                                               0x4
#define HWIO_GCC_GPLL0_CONFIG_CTL_FWD_GAIN_KFN_BMSK                                                       0xf
#define HWIO_GCC_GPLL0_CONFIG_CTL_FWD_GAIN_KFN_SHFT                                                       0x0

#define HWIO_GCC_GPLL0_CONFIG_CTL_U_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000001c)
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_RMSK                                                           0xffffffff
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL0_CONFIG_CTL_U_ADDR)
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_CONFIG_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_CONFIG_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_CONFIG_CTL_U_ADDR,m,v,HWIO_GCC_GPLL0_CONFIG_CTL_U_IN)
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_BIST_CFG_BMSK                                                  0xffff0000
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_BIST_CFG_SHFT                                                        0x10
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_BMSK                                       0xc000
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_SHFT                                          0xe
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_OSC_SETTLING_TIME_BMSK                                             0x3000
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_OSC_SETTLING_TIME_SHFT                                                0xc
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_BMSK                                            0xc00
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_SHFT                                              0xa
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_CASC_CURRENT_CTL_B_BMSK                                             0x380
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_CASC_CURRENT_CTL_B_SHFT                                               0x7
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_BMSK                                     0x40
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_SHFT                                      0x6
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_BMSK                                            0x30
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_SHFT                                             0x4
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_LDET_THRESH_SCALE_BMSK                                                0x8
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_LDET_THRESH_SCALE_SHFT                                                0x3
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_DCO_STARTUP_CONFIG_BMSK                                               0x6
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_DCO_STARTUP_CONFIG_SHFT                                               0x1
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_BMSK                                          0x1
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_SHFT                                          0x0

#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00000020)
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_RMSK                                                          0xffffffff
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL0_CONFIG_CTL_U1_ADDR)
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_CONFIG_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_CONFIG_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_CONFIG_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL0_CONFIG_CTL_U1_IN)
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BB_CAL_THRESHOLD_BMSK                                         0xc0000000
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BB_CAL_THRESHOLD_SHFT                                               0x1e
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_PCODE_OFFSET_BMSK                                             0x38000000
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_PCODE_OFFSET_SHFT                                                   0x1b
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_COUNTER_BLANK_BMSK                                             0x4000000
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_COUNTER_BLANK_SHFT                                                  0x1a
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BB_RESYNC_EDGE_BMSK                                            0x2000000
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BB_RESYNC_EDGE_SHFT                                                 0x19
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BB_RESYNC_SEL_BMSK                                             0x1000000
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BB_RESYNC_SEL_SHFT                                                  0x18
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_BMSK                                        0xc00000
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_SHFT                                            0x16
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BB_LOCK_THRESH_BMSK                                             0x380000
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BB_LOCK_THRESH_SHFT                                                 0x13
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_RESERVE_BIT82_BMSK                                               0x40000
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_RESERVE_BIT82_SHFT                                                  0x12
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_BMSK                                          0x30000
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_SHFT                                             0x10
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_BMSK                                            0xc000
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_SHFT                                               0xe
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BB_CAL_EN_BMSK                                                    0x2000
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BB_CAL_EN_SHFT                                                       0xd
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_BMSK                                      0x1800
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_SHFT                                         0xb
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BBMODE_INT_GAIN_BMSK                                               0x780
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BBMODE_INT_GAIN_SHFT                                                 0x7
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BBMODE_PROP_GAIN_BMSK                                               0x78
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_BBMODE_PROP_GAIN_SHFT                                                0x3
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_TDC_SELECTION_BMSK                                                   0x4
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_TDC_SELECTION_SHFT                                                   0x2
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_RESERVE_BIT65_BMSK                                                   0x2
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_RESERVE_BIT65_SHFT                                                   0x1
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_FORCE_DSM_ON_BMSK                                                    0x1
#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_FORCE_DSM_ON_SHFT                                                    0x0

#define HWIO_GCC_GPLL0_TEST_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00000024)
#define HWIO_GCC_GPLL0_TEST_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL0_TEST_CTL_IN          \
        in_dword(HWIO_GCC_GPLL0_TEST_CTL_ADDR)
#define HWIO_GCC_GPLL0_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_TEST_CTL_ADDR, m)
#define HWIO_GCC_GPLL0_TEST_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_TEST_CTL_ADDR,v)
#define HWIO_GCC_GPLL0_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_TEST_CTL_ADDR,m,v,HWIO_GCC_GPLL0_TEST_CTL_IN)
#define HWIO_GCC_GPLL0_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_BMSK                                       0xc0000000
#define HWIO_GCC_GPLL0_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_SHFT                                             0x1e
#define HWIO_GCC_GPLL0_TEST_CTL_BYPASS_FIRST_ORDER_DSM_BMSK                                        0x20000000
#define HWIO_GCC_GPLL0_TEST_CTL_BYPASS_FIRST_ORDER_DSM_SHFT                                              0x1d
#define HWIO_GCC_GPLL0_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_BMSK                                   0x18000000
#define HWIO_GCC_GPLL0_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_SHFT                                         0x1b
#define HWIO_GCC_GPLL0_TEST_CTL_GLITCH_PREVENTION_DIS_BMSK                                          0x4000000
#define HWIO_GCC_GPLL0_TEST_CTL_GLITCH_PREVENTION_DIS_SHFT                                               0x1a
#define HWIO_GCC_GPLL0_TEST_CTL_ATEST_ISCALE_BMSK                                                   0x3000000
#define HWIO_GCC_GPLL0_TEST_CTL_ATEST_ISCALE_SHFT                                                        0x18
#define HWIO_GCC_GPLL0_TEST_CTL_PLL_TEST_OUT_SEL_BMSK                                                0xf00000
#define HWIO_GCC_GPLL0_TEST_CTL_PLL_TEST_OUT_SEL_SHFT                                                    0x14
#define HWIO_GCC_GPLL0_TEST_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL0_TEST_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL0_TEST_CTL_DIV2_NMO_EN_BMSK                                                      0x40000
#define HWIO_GCC_GPLL0_TEST_CTL_DIV2_NMO_EN_SHFT                                                         0x12
#define HWIO_GCC_GPLL0_TEST_CTL_NMO_OSC_SEL_BMSK                                                      0x30000
#define HWIO_GCC_GPLL0_TEST_CTL_NMO_OSC_SEL_SHFT                                                         0x10
#define HWIO_GCC_GPLL0_TEST_CTL_NOISE_MAG_BMSK                                                         0xe000
#define HWIO_GCC_GPLL0_TEST_CTL_NOISE_MAG_SHFT                                                            0xd
#define HWIO_GCC_GPLL0_TEST_CTL_NOISE_GEN_EN_BMSK                                                      0x1000
#define HWIO_GCC_GPLL0_TEST_CTL_NOISE_GEN_EN_SHFT                                                         0xc
#define HWIO_GCC_GPLL0_TEST_CTL_DISABLE_DCAPS_BMSK                                                      0x800
#define HWIO_GCC_GPLL0_TEST_CTL_DISABLE_DCAPS_SHFT                                                        0xb
#define HWIO_GCC_GPLL0_TEST_CTL_RESERVE_BIT10_BMSK                                                      0x400
#define HWIO_GCC_GPLL0_TEST_CTL_RESERVE_BIT10_SHFT                                                        0xa
#define HWIO_GCC_GPLL0_TEST_CTL_RESERVE_BIT9_BMSK                                                       0x200
#define HWIO_GCC_GPLL0_TEST_CTL_RESERVE_BIT9_SHFT                                                         0x9
#define HWIO_GCC_GPLL0_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_BMSK                                            0x100
#define HWIO_GCC_GPLL0_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_SHFT                                              0x8
#define HWIO_GCC_GPLL0_TEST_CTL_EN_VDD_TEST_BMSK                                                         0x80
#define HWIO_GCC_GPLL0_TEST_CTL_EN_VDD_TEST_SHFT                                                          0x7
#define HWIO_GCC_GPLL0_TEST_CTL_EN_VREG_TEST_BMSK                                                        0x40
#define HWIO_GCC_GPLL0_TEST_CTL_EN_VREG_TEST_SHFT                                                         0x6
#define HWIO_GCC_GPLL0_TEST_CTL_EN_VREF_TEST_BMSK                                                        0x20
#define HWIO_GCC_GPLL0_TEST_CTL_EN_VREF_TEST_SHFT                                                         0x5
#define HWIO_GCC_GPLL0_TEST_CTL_EN_VDCO_TEST_BMSK                                                        0x10
#define HWIO_GCC_GPLL0_TEST_CTL_EN_VDCO_TEST_SHFT                                                         0x4
#define HWIO_GCC_GPLL0_TEST_CTL_BYPASS_ATEST_BUFFER_BMSK                                                  0x8
#define HWIO_GCC_GPLL0_TEST_CTL_BYPASS_ATEST_BUFFER_SHFT                                                  0x3
#define HWIO_GCC_GPLL0_TEST_CTL_EN_IVCO_TEST_BMSK                                                         0x4
#define HWIO_GCC_GPLL0_TEST_CTL_EN_IVCO_TEST_SHFT                                                         0x2
#define HWIO_GCC_GPLL0_TEST_CTL_ATEST1_EN_BMSK                                                            0x2
#define HWIO_GCC_GPLL0_TEST_CTL_ATEST1_EN_SHFT                                                            0x1
#define HWIO_GCC_GPLL0_TEST_CTL_ATEST0_EN_BMSK                                                            0x1
#define HWIO_GCC_GPLL0_TEST_CTL_ATEST0_EN_SHFT                                                            0x0

#define HWIO_GCC_GPLL0_TEST_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00000028)
#define HWIO_GCC_GPLL0_TEST_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL0_TEST_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL0_TEST_CTL_U_ADDR)
#define HWIO_GCC_GPLL0_TEST_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_TEST_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL0_TEST_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_TEST_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL0_TEST_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_TEST_CTL_U_ADDR,m,v,HWIO_GCC_GPLL0_TEST_CTL_U_IN)
#define HWIO_GCC_GPLL0_TEST_CTL_U_CASC_DAC_FCW_LSBS_BMSK                                           0xe0000000
#define HWIO_GCC_GPLL0_TEST_CTL_U_CASC_DAC_FCW_LSBS_SHFT                                                 0x1d
#define HWIO_GCC_GPLL0_TEST_CTL_U_OVERRIDE_CASC_DAC_BMSK                                           0x10000000
#define HWIO_GCC_GPLL0_TEST_CTL_U_OVERRIDE_CASC_DAC_SHFT                                                 0x1c
#define HWIO_GCC_GPLL0_TEST_CTL_U_COMP_COARSE_FCW_BMSK                                              0xe000000
#define HWIO_GCC_GPLL0_TEST_CTL_U_COMP_COARSE_FCW_SHFT                                                   0x19
#define HWIO_GCC_GPLL0_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_BMSK                                     0x1800000
#define HWIO_GCC_GPLL0_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_SHFT                                          0x17
#define HWIO_GCC_GPLL0_TEST_CTL_U_FINE_FCW_BMSK                                                      0x7e0000
#define HWIO_GCC_GPLL0_TEST_CTL_U_FINE_FCW_SHFT                                                          0x11
#define HWIO_GCC_GPLL0_TEST_CTL_U_OVERRIDE_FINE_FCW_BMSK                                              0x10000
#define HWIO_GCC_GPLL0_TEST_CTL_U_OVERRIDE_FINE_FCW_SHFT                                                 0x10
#define HWIO_GCC_GPLL0_TEST_CTL_U_REG_COARSE_FCW_BMSK                                                  0xfe00
#define HWIO_GCC_GPLL0_TEST_CTL_U_REG_COARSE_FCW_SHFT                                                     0x9
#define HWIO_GCC_GPLL0_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_BMSK                                          0x100
#define HWIO_GCC_GPLL0_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_SHFT                                            0x8
#define HWIO_GCC_GPLL0_TEST_CTL_U_PROCESS_CALIB_WORD_BMSK                                                0xe0
#define HWIO_GCC_GPLL0_TEST_CTL_U_PROCESS_CALIB_WORD_SHFT                                                 0x5
#define HWIO_GCC_GPLL0_TEST_CTL_U_OVERRIDE_CALIB_WORD_BMSK                                               0x10
#define HWIO_GCC_GPLL0_TEST_CTL_U_OVERRIDE_CALIB_WORD_SHFT                                                0x4
#define HWIO_GCC_GPLL0_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_BMSK                                             0x8
#define HWIO_GCC_GPLL0_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_SHFT                                             0x3
#define HWIO_GCC_GPLL0_TEST_CTL_U_DISABLE_LFSR_BMSK                                                       0x4
#define HWIO_GCC_GPLL0_TEST_CTL_U_DISABLE_LFSR_SHFT                                                       0x2
#define HWIO_GCC_GPLL0_TEST_CTL_U_SKIP_FINE_TUNE_BMSK                                                     0x2
#define HWIO_GCC_GPLL0_TEST_CTL_U_SKIP_FINE_TUNE_SHFT                                                     0x1
#define HWIO_GCC_GPLL0_TEST_CTL_U_SKIP_FAST_LOCK_BMSK                                                     0x1
#define HWIO_GCC_GPLL0_TEST_CTL_U_SKIP_FAST_LOCK_SHFT                                                     0x0

#define HWIO_GCC_GPLL0_TEST_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000002c)
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL0_TEST_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL0_TEST_CTL_U1_ADDR)
#define HWIO_GCC_GPLL0_TEST_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_TEST_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL0_TEST_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_TEST_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL0_TEST_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_TEST_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL0_TEST_CTL_U1_IN)
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL0_TEST_CTL_U1_FLL_COUNT_DISABLE_BMSK                                          0x20000000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_FLL_COUNT_DISABLE_SHFT                                                0x1d
#define HWIO_GCC_GPLL0_TEST_CTL_U1_FLL_COUNT_IN_DIV2_BMSK                                          0x10000000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_FLL_COUNT_IN_DIV2_SHFT                                                0x1c
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL0_TEST_CTL_U1_SILENCE_REF_OUTBUF_BMSK                                           0x400000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_SILENCE_REF_OUTBUF_SHFT                                               0x16
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL0_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_BMSK                                         0x40000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_SHFT                                            0x12
#define HWIO_GCC_GPLL0_TEST_CTL_U1_REF_CLK_SEL_BMSK                                                   0x20000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_REF_CLK_SEL_SHFT                                                      0x11
#define HWIO_GCC_GPLL0_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_BMSK                                     0x10000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_SHFT                                        0x10
#define HWIO_GCC_GPLL0_TEST_CTL_U1_DIS_AMP_STARTUP_BMSK                                                0x8000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_DIS_AMP_STARTUP_SHFT                                                   0xf
#define HWIO_GCC_GPLL0_TEST_CTL_U1_DISABLE_CLAMP_BMSK                                                  0x4000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_DISABLE_CLAMP_SHFT                                                     0xe
#define HWIO_GCC_GPLL0_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_BMSK                                        0x2000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_SHFT                                           0xd
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL0_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_BMSK                                          0x80
#define HWIO_GCC_GPLL0_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_SHFT                                           0x7
#define HWIO_GCC_GPLL0_TEST_CTL_U1_ENABLE_TRAINING_SEQ_BMSK                                              0x40
#define HWIO_GCC_GPLL0_TEST_CTL_U1_ENABLE_TRAINING_SEQ_SHFT                                               0x6
#define HWIO_GCC_GPLL0_TEST_CTL_U1_STATUS_REG_EN_BMSK                                                    0x20
#define HWIO_GCC_GPLL0_TEST_CTL_U1_STATUS_REG_EN_SHFT                                                     0x5
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL0_TEST_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL0_TEST_CTL_U1_CASC_DAC_FCW_MSBS_BMSK                                                 0x3
#define HWIO_GCC_GPLL0_TEST_CTL_U1_CASC_DAC_FCW_MSBS_SHFT                                                 0x0

#define HWIO_GCC_GPLL0_STATUS_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00000030)
#define HWIO_GCC_GPLL0_STATUS_RMSK                                                                 0xffffffff
#define HWIO_GCC_GPLL0_STATUS_IN          \
        in_dword(HWIO_GCC_GPLL0_STATUS_ADDR)
#define HWIO_GCC_GPLL0_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_STATUS_ADDR, m)
#define HWIO_GCC_GPLL0_STATUS_STATUS_31_0_BMSK                                                     0xffffffff
#define HWIO_GCC_GPLL0_STATUS_STATUS_31_0_SHFT                                                            0x0

#define HWIO_GCC_GPLL0_FREQ_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00000034)
#define HWIO_GCC_GPLL0_FREQ_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL0_FREQ_CTL_IN          \
        in_dword(HWIO_GCC_GPLL0_FREQ_CTL_ADDR)
#define HWIO_GCC_GPLL0_FREQ_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_FREQ_CTL_ADDR, m)
#define HWIO_GCC_GPLL0_FREQ_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_FREQ_CTL_ADDR,v)
#define HWIO_GCC_GPLL0_FREQ_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_FREQ_CTL_ADDR,m,v,HWIO_GCC_GPLL0_FREQ_CTL_IN)
#define HWIO_GCC_GPLL0_FREQ_CTL_FREQUENCY_CTL_WORD_BMSK                                            0xffffffff
#define HWIO_GCC_GPLL0_FREQ_CTL_FREQUENCY_CTL_WORD_SHFT                                                   0x0

#define HWIO_GCC_GPLL0_OPMODE_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00000038)
#define HWIO_GCC_GPLL0_OPMODE_RMSK                                                                        0x7
#define HWIO_GCC_GPLL0_OPMODE_IN          \
        in_dword(HWIO_GCC_GPLL0_OPMODE_ADDR)
#define HWIO_GCC_GPLL0_OPMODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OPMODE_ADDR, m)
#define HWIO_GCC_GPLL0_OPMODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OPMODE_ADDR,v)
#define HWIO_GCC_GPLL0_OPMODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OPMODE_ADDR,m,v,HWIO_GCC_GPLL0_OPMODE_IN)
#define HWIO_GCC_GPLL0_OPMODE_PLL_OPMODE_BMSK                                                             0x7
#define HWIO_GCC_GPLL0_OPMODE_PLL_OPMODE_SHFT                                                             0x0

#define HWIO_GCC_GPLL0_STATE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0000003c)
#define HWIO_GCC_GPLL0_STATE_RMSK                                                                         0x7
#define HWIO_GCC_GPLL0_STATE_IN          \
        in_dword(HWIO_GCC_GPLL0_STATE_ADDR)
#define HWIO_GCC_GPLL0_STATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_STATE_ADDR, m)
#define HWIO_GCC_GPLL0_STATE_PLL_STATE_BMSK                                                               0x7
#define HWIO_GCC_GPLL0_STATE_PLL_STATE_SHFT                                                               0x0

#define HWIO_GCC_GPLL0_ALPHA_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00000040)
#define HWIO_GCC_GPLL0_ALPHA_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL0_ALPHA_VAL_IN          \
        in_dword(HWIO_GCC_GPLL0_ALPHA_VAL_ADDR)
#define HWIO_GCC_GPLL0_ALPHA_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_ALPHA_VAL_ADDR, m)
#define HWIO_GCC_GPLL0_ALPHA_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_ALPHA_VAL_ADDR,v)
#define HWIO_GCC_GPLL0_ALPHA_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_ALPHA_VAL_ADDR,m,v,HWIO_GCC_GPLL0_ALPHA_VAL_IN)
#define HWIO_GCC_GPLL0_ALPHA_VAL_PLL_ALPHA_VAL_BMSK                                                    0xffff
#define HWIO_GCC_GPLL0_ALPHA_VAL_PLL_ALPHA_VAL_SHFT                                                       0x0

#define HWIO_GCC_GPLL0_SPARE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00000044)
#define HWIO_GCC_GPLL0_SPARE_RMSK                                                                        0xff
#define HWIO_GCC_GPLL0_SPARE_IN          \
        in_dword(HWIO_GCC_GPLL0_SPARE_ADDR)
#define HWIO_GCC_GPLL0_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_SPARE_ADDR, m)
#define HWIO_GCC_GPLL0_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_SPARE_ADDR,v)
#define HWIO_GCC_GPLL0_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_SPARE_ADDR,m,v,HWIO_GCC_GPLL0_SPARE_IN)
#define HWIO_GCC_GPLL0_SPARE_SPARE_OUTPUTS_BMSK                                                          0xf0
#define HWIO_GCC_GPLL0_SPARE_SPARE_OUTPUTS_SHFT                                                           0x4
#define HWIO_GCC_GPLL0_SPARE_SPARE_INPUTS_BMSK                                                            0xf
#define HWIO_GCC_GPLL0_SPARE_SPARE_INPUTS_SHFT                                                            0x0

#define HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00000048)
#define HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_RMSK                                                              0xff
#define HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_IN          \
        in_dword(HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_ADDR)
#define HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_ADDR, m)
#define HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_ADDR,v)
#define HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_ADDR,m,v,HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_IN)
#define HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_BMSK                                              0xff
#define HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_SHFT                                               0x0

#define HWIO_GCC_GPLL0_SSC_NUM_STEPS_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000004c)
#define HWIO_GCC_GPLL0_SSC_NUM_STEPS_RMSK                                                                 0xf
#define HWIO_GCC_GPLL0_SSC_NUM_STEPS_IN          \
        in_dword(HWIO_GCC_GPLL0_SSC_NUM_STEPS_ADDR)
#define HWIO_GCC_GPLL0_SSC_NUM_STEPS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_SSC_NUM_STEPS_ADDR, m)
#define HWIO_GCC_GPLL0_SSC_NUM_STEPS_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_SSC_NUM_STEPS_ADDR,v)
#define HWIO_GCC_GPLL0_SSC_NUM_STEPS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_SSC_NUM_STEPS_ADDR,m,v,HWIO_GCC_GPLL0_SSC_NUM_STEPS_IN)
#define HWIO_GCC_GPLL0_SSC_NUM_STEPS_SSC_NUM_STEPS_BMSK                                                   0xf
#define HWIO_GCC_GPLL0_SSC_NUM_STEPS_SSC_NUM_STEPS_SHFT                                                   0x0

#define HWIO_GCC_GPLL0_SSC_UPDATE_RATE_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00000050)
#define HWIO_GCC_GPLL0_SSC_UPDATE_RATE_RMSK                                                               0xf
#define HWIO_GCC_GPLL0_SSC_UPDATE_RATE_IN          \
        in_dword(HWIO_GCC_GPLL0_SSC_UPDATE_RATE_ADDR)
#define HWIO_GCC_GPLL0_SSC_UPDATE_RATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_SSC_UPDATE_RATE_ADDR, m)
#define HWIO_GCC_GPLL0_SSC_UPDATE_RATE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_SSC_UPDATE_RATE_ADDR,v)
#define HWIO_GCC_GPLL0_SSC_UPDATE_RATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_SSC_UPDATE_RATE_ADDR,m,v,HWIO_GCC_GPLL0_SSC_UPDATE_RATE_IN)
#define HWIO_GCC_GPLL0_SSC_UPDATE_RATE_SSC_UPDATE_RATE_BMSK                                               0xf
#define HWIO_GCC_GPLL0_SSC_UPDATE_RATE_SSC_UPDATE_RATE_SHFT                                               0x0

#define HWIO_GCC_GPLL1_MODE_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00001000)
#define HWIO_GCC_GPLL1_MODE_RMSK                                                                   0xffffffff
#define HWIO_GCC_GPLL1_MODE_IN          \
        in_dword(HWIO_GCC_GPLL1_MODE_ADDR)
#define HWIO_GCC_GPLL1_MODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_MODE_ADDR, m)
#define HWIO_GCC_GPLL1_MODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_MODE_ADDR,v)
#define HWIO_GCC_GPLL1_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_MODE_ADDR,m,v,HWIO_GCC_GPLL1_MODE_IN)
#define HWIO_GCC_GPLL1_MODE_PLL_LOCK_DET_BMSK                                                      0x80000000
#define HWIO_GCC_GPLL1_MODE_PLL_LOCK_DET_SHFT                                                            0x1f
#define HWIO_GCC_GPLL1_MODE_PLL_ACTIVE_FLAG_BMSK                                                   0x40000000
#define HWIO_GCC_GPLL1_MODE_PLL_ACTIVE_FLAG_SHFT                                                         0x1e
#define HWIO_GCC_GPLL1_MODE_PLL_ACK_LATCH_BMSK                                                     0x20000000
#define HWIO_GCC_GPLL1_MODE_PLL_ACK_LATCH_SHFT                                                           0x1d
#define HWIO_GCC_GPLL1_MODE_PLL_LOCK_DET_FINE_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL1_MODE_PLL_LOCK_DET_FINE_SHFT                                                       0x1c
#define HWIO_GCC_GPLL1_MODE_PCAL_DONE_BMSK                                                          0x8000000
#define HWIO_GCC_GPLL1_MODE_PCAL_DONE_SHFT                                                               0x1b
#define HWIO_GCC_GPLL1_MODE_RESERVE_BITS26_25_BMSK                                                  0x6000000
#define HWIO_GCC_GPLL1_MODE_RESERVE_BITS26_25_SHFT                                                       0x19
#define HWIO_GCC_GPLL1_MODE_FSM_LEGACY_MODE_BMSK                                                    0x1000000
#define HWIO_GCC_GPLL1_MODE_FSM_LEGACY_MODE_SHFT                                                         0x18
#define HWIO_GCC_GPLL1_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_BMSK                                          0x800000
#define HWIO_GCC_GPLL1_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_SHFT                                              0x17
#define HWIO_GCC_GPLL1_MODE_PLL_UPDATE_BMSK                                                          0x400000
#define HWIO_GCC_GPLL1_MODE_PLL_UPDATE_SHFT                                                              0x16
#define HWIO_GCC_GPLL1_MODE_PLL_VOTE_FSM_RESET_BMSK                                                  0x200000
#define HWIO_GCC_GPLL1_MODE_PLL_VOTE_FSM_RESET_SHFT                                                      0x15
#define HWIO_GCC_GPLL1_MODE_PLL_VOTE_FSM_ENA_BMSK                                                    0x100000
#define HWIO_GCC_GPLL1_MODE_PLL_VOTE_FSM_ENA_SHFT                                                        0x14
#define HWIO_GCC_GPLL1_MODE_PLL_BIAS_COUNT_BMSK                                                       0xfc000
#define HWIO_GCC_GPLL1_MODE_PLL_BIAS_COUNT_SHFT                                                           0xe
#define HWIO_GCC_GPLL1_MODE_PLL_LOCK_COUNT_BMSK                                                        0x3f00
#define HWIO_GCC_GPLL1_MODE_PLL_LOCK_COUNT_SHFT                                                           0x8
#define HWIO_GCC_GPLL1_MODE_RESERVE_BIT7_BMSK                                                            0x80
#define HWIO_GCC_GPLL1_MODE_RESERVE_BIT7_SHFT                                                             0x7
#define HWIO_GCC_GPLL1_MODE_OUT_TEST_HW_CTL_BMSK                                                         0x40
#define HWIO_GCC_GPLL1_MODE_OUT_TEST_HW_CTL_SHFT                                                          0x6
#define HWIO_GCC_GPLL1_MODE_OUT_ODD_HW_CTL_BMSK                                                          0x20
#define HWIO_GCC_GPLL1_MODE_OUT_ODD_HW_CTL_SHFT                                                           0x5
#define HWIO_GCC_GPLL1_MODE_OUT_EVEN_HW_CTL_BMSK                                                         0x10
#define HWIO_GCC_GPLL1_MODE_OUT_EVEN_HW_CTL_SHFT                                                          0x4
#define HWIO_GCC_GPLL1_MODE_OUT_MAIN_HW_CTL_BMSK                                                          0x8
#define HWIO_GCC_GPLL1_MODE_OUT_MAIN_HW_CTL_SHFT                                                          0x3
#define HWIO_GCC_GPLL1_MODE_PLL_RESET_N_BMSK                                                              0x4
#define HWIO_GCC_GPLL1_MODE_PLL_RESET_N_SHFT                                                              0x2
#define HWIO_GCC_GPLL1_MODE_RESERVE_BIT1_BMSK                                                             0x2
#define HWIO_GCC_GPLL1_MODE_RESERVE_BIT1_SHFT                                                             0x1
#define HWIO_GCC_GPLL1_MODE_PLL_OUTCTRL_BMSK                                                              0x1
#define HWIO_GCC_GPLL1_MODE_PLL_OUTCTRL_SHFT                                                              0x0

#define HWIO_GCC_GPLL1_L_VAL_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00001004)
#define HWIO_GCC_GPLL1_L_VAL_RMSK                                                                      0xffff
#define HWIO_GCC_GPLL1_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL1_L_VAL_ADDR)
#define HWIO_GCC_GPLL1_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL1_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL1_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_L_VAL_ADDR,m,v,HWIO_GCC_GPLL1_L_VAL_IN)
#define HWIO_GCC_GPLL1_L_VAL_PLL_L_BMSK                                                                0xffff
#define HWIO_GCC_GPLL1_L_VAL_PLL_L_SHFT                                                                   0x0

#define HWIO_GCC_GPLL1_CAL_L_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00001008)
#define HWIO_GCC_GPLL1_CAL_L_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL1_CAL_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL1_CAL_L_VAL_ADDR)
#define HWIO_GCC_GPLL1_CAL_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_CAL_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL1_CAL_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_CAL_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL1_CAL_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_CAL_L_VAL_ADDR,m,v,HWIO_GCC_GPLL1_CAL_L_VAL_IN)
#define HWIO_GCC_GPLL1_CAL_L_VAL_PLL_CAL_L_BMSK                                                        0xffff
#define HWIO_GCC_GPLL1_CAL_L_VAL_PLL_CAL_L_SHFT                                                           0x0

#define HWIO_GCC_GPLL1_USER_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0000100c)
#define HWIO_GCC_GPLL1_USER_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL1_USER_CTL_IN          \
        in_dword(HWIO_GCC_GPLL1_USER_CTL_ADDR)
#define HWIO_GCC_GPLL1_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_USER_CTL_ADDR, m)
#define HWIO_GCC_GPLL1_USER_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_USER_CTL_ADDR,v)
#define HWIO_GCC_GPLL1_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_USER_CTL_ADDR,m,v,HWIO_GCC_GPLL1_USER_CTL_IN)
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT31_BMSK                                                 0x80000000
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT31_SHFT                                                       0x1f
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT30_BMSK                                                 0x40000000
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT30_SHFT                                                       0x1e
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT29_BMSK                                                 0x20000000
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT29_SHFT                                                       0x1d
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT28_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT28_SHFT                                                       0x1c
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT27_BMSK                                                  0x8000000
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT27_SHFT                                                       0x1b
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT26_BMSK                                                  0x4000000
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT26_SHFT                                                       0x1a
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT25_BMSK                                                  0x2000000
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT25_SHFT                                                       0x19
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT24_BMSK                                                  0x1000000
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT24_SHFT                                                       0x18
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT23_BMSK                                                   0x800000
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT23_SHFT                                                       0x17
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT22_BMSK                                                   0x400000
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT22_SHFT                                                       0x16
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT21_BMSK                                                   0x200000
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT21_SHFT                                                       0x15
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT20_BMSK                                                   0x100000
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT20_SHFT                                                       0x14
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL1_USER_CTL_PRE_DIV_RATIO_BMSK                                                    0x70000
#define HWIO_GCC_GPLL1_USER_CTL_PRE_DIV_RATIO_SHFT                                                       0x10
#define HWIO_GCC_GPLL1_USER_CTL_POST_DIV_RATIO_ODD_BMSK                                                0xf000
#define HWIO_GCC_GPLL1_USER_CTL_POST_DIV_RATIO_ODD_SHFT                                                   0xc
#define HWIO_GCC_GPLL1_USER_CTL_POST_DIV_RATIO_EVEN_BMSK                                                0xf00
#define HWIO_GCC_GPLL1_USER_CTL_POST_DIV_RATIO_EVEN_SHFT                                                  0x8
#define HWIO_GCC_GPLL1_USER_CTL_OUT_CLK_POLARITY_BMSK                                                    0x80
#define HWIO_GCC_GPLL1_USER_CTL_OUT_CLK_POLARITY_SHFT                                                     0x7
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT6_BMSK                                                        0x40
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT6_SHFT                                                         0x6
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT5_BMSK                                                        0x20
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT5_SHFT                                                         0x5
#define HWIO_GCC_GPLL1_USER_CTL_PLLOUT_TEST_BMSK                                                         0x10
#define HWIO_GCC_GPLL1_USER_CTL_PLLOUT_TEST_SHFT                                                          0x4
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT3_BMSK                                                         0x8
#define HWIO_GCC_GPLL1_USER_CTL_RESERVE_BIT3_SHFT                                                         0x3
#define HWIO_GCC_GPLL1_USER_CTL_PLLOUT_ODD_BMSK                                                           0x4
#define HWIO_GCC_GPLL1_USER_CTL_PLLOUT_ODD_SHFT                                                           0x2
#define HWIO_GCC_GPLL1_USER_CTL_PLLOUT_EVEN_BMSK                                                          0x2
#define HWIO_GCC_GPLL1_USER_CTL_PLLOUT_EVEN_SHFT                                                          0x1
#define HWIO_GCC_GPLL1_USER_CTL_PLLOUT_MAIN_BMSK                                                          0x1
#define HWIO_GCC_GPLL1_USER_CTL_PLLOUT_MAIN_SHFT                                                          0x0

#define HWIO_GCC_GPLL1_USER_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00001010)
#define HWIO_GCC_GPLL1_USER_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL1_USER_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL1_USER_CTL_U_ADDR)
#define HWIO_GCC_GPLL1_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_USER_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL1_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_USER_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL1_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_USER_CTL_U_ADDR,m,v,HWIO_GCC_GPLL1_USER_CTL_U_IN)
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT63_BMSK                                               0x80000000
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT63_SHFT                                                     0x1f
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT62_BMSK                                               0x40000000
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT62_SHFT                                                     0x1e
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT61_BMSK                                               0x20000000
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT61_SHFT                                                     0x1d
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT60_BMSK                                               0x10000000
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT60_SHFT                                                     0x1c
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT59_BMSK                                                0x8000000
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT59_SHFT                                                     0x1b
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT58_BMSK                                                0x4000000
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT58_SHFT                                                     0x1a
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT57_BMSK                                                0x2000000
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT57_SHFT                                                     0x19
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT56_BMSK                                                0x1000000
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT56_SHFT                                                     0x18
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT55_BMSK                                                 0x800000
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT55_SHFT                                                     0x17
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT54_BMSK                                                 0x400000
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT54_SHFT                                                     0x16
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT53_BMSK                                                 0x200000
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT53_SHFT                                                     0x15
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT52_BMSK                                                 0x100000
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT52_SHFT                                                     0x14
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT51_BMSK                                                  0x80000
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT51_SHFT                                                     0x13
#define HWIO_GCC_GPLL1_USER_CTL_U_LOCK_DETECTOR_SELECTION_BMSK                                        0x40000
#define HWIO_GCC_GPLL1_USER_CTL_U_LOCK_DETECTOR_SELECTION_SHFT                                           0x12
#define HWIO_GCC_GPLL1_USER_CTL_U_TYPE_2_MODE_SELECTION_BMSK                                          0x20000
#define HWIO_GCC_GPLL1_USER_CTL_U_TYPE_2_MODE_SELECTION_SHFT                                             0x11
#define HWIO_GCC_GPLL1_USER_CTL_U_BANG_BANG_MODE_SELECTION_BMSK                                       0x10000
#define HWIO_GCC_GPLL1_USER_CTL_U_BANG_BANG_MODE_SELECTION_SHFT                                          0x10
#define HWIO_GCC_GPLL1_USER_CTL_U_FRAC_FORMAT_SEL_BMSK                                                 0x8000
#define HWIO_GCC_GPLL1_USER_CTL_U_FRAC_FORMAT_SEL_SHFT                                                    0xf
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT46_BMSK                                                   0x4000
#define HWIO_GCC_GPLL1_USER_CTL_U_RESERVE_BIT46_SHFT                                                      0xe
#define HWIO_GCC_GPLL1_USER_CTL_U_REF_CLK_AT_OUT_BMSK                                                  0x2000
#define HWIO_GCC_GPLL1_USER_CTL_U_REF_CLK_AT_OUT_SHFT                                                     0xd
#define HWIO_GCC_GPLL1_USER_CTL_U_SCALE_FREQ_ON_RESTART_BMSK                                           0x1800
#define HWIO_GCC_GPLL1_USER_CTL_U_SCALE_FREQ_ON_RESTART_SHFT                                              0xb
#define HWIO_GCC_GPLL1_USER_CTL_U_LATCH_INTERFACE_BYPASS_BMSK                                           0x400
#define HWIO_GCC_GPLL1_USER_CTL_U_LATCH_INTERFACE_BYPASS_SHFT                                             0xa
#define HWIO_GCC_GPLL1_USER_CTL_U_STATUS_REGISTER_BMSK                                                  0x3e0
#define HWIO_GCC_GPLL1_USER_CTL_U_STATUS_REGISTER_SHFT                                                    0x5
#define HWIO_GCC_GPLL1_USER_CTL_U_WRITE_STATE_EN_BMSK                                                    0x10
#define HWIO_GCC_GPLL1_USER_CTL_U_WRITE_STATE_EN_SHFT                                                     0x4
#define HWIO_GCC_GPLL1_USER_CTL_U_CALIB_CTRL_BMSK                                                         0xe
#define HWIO_GCC_GPLL1_USER_CTL_U_CALIB_CTRL_SHFT                                                         0x1
#define HWIO_GCC_GPLL1_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_BMSK                                             0x1
#define HWIO_GCC_GPLL1_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_SHFT                                             0x0

#define HWIO_GCC_GPLL1_USER_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00001014)
#define HWIO_GCC_GPLL1_USER_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL1_USER_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL1_USER_CTL_U1_ADDR)
#define HWIO_GCC_GPLL1_USER_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_USER_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL1_USER_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_USER_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL1_USER_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_USER_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL1_USER_CTL_U1_IN)
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT93_BMSK                                              0x20000000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT93_SHFT                                                    0x1d
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT92_BMSK                                              0x10000000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT92_SHFT                                                    0x1c
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT86_BMSK                                                0x400000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT86_SHFT                                                    0x16
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT82_BMSK                                                 0x40000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT82_SHFT                                                    0x12
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT81_BMSK                                                 0x20000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT81_SHFT                                                    0x11
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT80_BMSK                                                 0x10000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT80_SHFT                                                    0x10
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT79_BMSK                                                  0x8000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT79_SHFT                                                     0xf
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT78_BMSK                                                  0x4000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT78_SHFT                                                     0xe
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT77_BMSK                                                  0x2000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT77_SHFT                                                     0xd
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT71_BMSK                                                    0x80
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT71_SHFT                                                     0x7
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT70_BMSK                                                    0x40
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT70_SHFT                                                     0x6
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT69_BMSK                                                    0x20
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT69_SHFT                                                     0x5
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT65_BMSK                                                     0x2
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT65_SHFT                                                     0x1
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT64_BMSK                                                     0x1
#define HWIO_GCC_GPLL1_USER_CTL_U1_RESERVE_BIT64_SHFT                                                     0x0

#define HWIO_GCC_GPLL1_CONFIG_CTL_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00001018)
#define HWIO_GCC_GPLL1_CONFIG_CTL_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL1_CONFIG_CTL_IN          \
        in_dword(HWIO_GCC_GPLL1_CONFIG_CTL_ADDR)
#define HWIO_GCC_GPLL1_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_CONFIG_CTL_ADDR, m)
#define HWIO_GCC_GPLL1_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_CONFIG_CTL_ADDR,v)
#define HWIO_GCC_GPLL1_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_CONFIG_CTL_ADDR,m,v,HWIO_GCC_GPLL1_CONFIG_CTL_IN)
#define HWIO_GCC_GPLL1_CONFIG_CTL_FINE_LDC_THRESHOLD_BMSK                                          0xfc000000
#define HWIO_GCC_GPLL1_CONFIG_CTL_FINE_LDC_THRESHOLD_SHFT                                                0x1a
#define HWIO_GCC_GPLL1_CONFIG_CTL_COARSE_LDC_THRESHOLD_BMSK                                         0x3c00000
#define HWIO_GCC_GPLL1_CONFIG_CTL_COARSE_LDC_THRESHOLD_SHFT                                              0x16
#define HWIO_GCC_GPLL1_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_BMSK                                 0x3c0000
#define HWIO_GCC_GPLL1_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_SHFT                                     0x12
#define HWIO_GCC_GPLL1_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_BMSK                                  0x3c000
#define HWIO_GCC_GPLL1_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_SHFT                                      0xe
#define HWIO_GCC_GPLL1_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_BMSK                                         0x3800
#define HWIO_GCC_GPLL1_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_SHFT                                            0xb
#define HWIO_GCC_GPLL1_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_BMSK                                        0x700
#define HWIO_GCC_GPLL1_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_SHFT                                          0x8
#define HWIO_GCC_GPLL1_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_BMSK                                              0xf0
#define HWIO_GCC_GPLL1_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_SHFT                                               0x4
#define HWIO_GCC_GPLL1_CONFIG_CTL_FWD_GAIN_KFN_BMSK                                                       0xf
#define HWIO_GCC_GPLL1_CONFIG_CTL_FWD_GAIN_KFN_SHFT                                                       0x0

#define HWIO_GCC_GPLL1_CONFIG_CTL_U_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000101c)
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_RMSK                                                           0xffffffff
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL1_CONFIG_CTL_U_ADDR)
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_CONFIG_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_CONFIG_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_CONFIG_CTL_U_ADDR,m,v,HWIO_GCC_GPLL1_CONFIG_CTL_U_IN)
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_BIST_CFG_BMSK                                                  0xffff0000
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_BIST_CFG_SHFT                                                        0x10
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_BMSK                                       0xc000
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_SHFT                                          0xe
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_OSC_SETTLING_TIME_BMSK                                             0x3000
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_OSC_SETTLING_TIME_SHFT                                                0xc
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_BMSK                                            0xc00
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_SHFT                                              0xa
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_CASC_CURRENT_CTL_B_BMSK                                             0x380
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_CASC_CURRENT_CTL_B_SHFT                                               0x7
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_BMSK                                     0x40
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_SHFT                                      0x6
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_BMSK                                            0x30
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_SHFT                                             0x4
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_LDET_THRESH_SCALE_BMSK                                                0x8
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_LDET_THRESH_SCALE_SHFT                                                0x3
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_DCO_STARTUP_CONFIG_BMSK                                               0x6
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_DCO_STARTUP_CONFIG_SHFT                                               0x1
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_BMSK                                          0x1
#define HWIO_GCC_GPLL1_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_SHFT                                          0x0

#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00001020)
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_RMSK                                                          0xffffffff
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL1_CONFIG_CTL_U1_ADDR)
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_CONFIG_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_CONFIG_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_CONFIG_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL1_CONFIG_CTL_U1_IN)
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BB_CAL_THRESHOLD_BMSK                                         0xc0000000
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BB_CAL_THRESHOLD_SHFT                                               0x1e
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_PCODE_OFFSET_BMSK                                             0x38000000
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_PCODE_OFFSET_SHFT                                                   0x1b
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_COUNTER_BLANK_BMSK                                             0x4000000
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_COUNTER_BLANK_SHFT                                                  0x1a
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BB_RESYNC_EDGE_BMSK                                            0x2000000
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BB_RESYNC_EDGE_SHFT                                                 0x19
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BB_RESYNC_SEL_BMSK                                             0x1000000
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BB_RESYNC_SEL_SHFT                                                  0x18
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_BMSK                                        0xc00000
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_SHFT                                            0x16
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BB_LOCK_THRESH_BMSK                                             0x380000
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BB_LOCK_THRESH_SHFT                                                 0x13
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_RESERVE_BIT82_BMSK                                               0x40000
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_RESERVE_BIT82_SHFT                                                  0x12
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_BMSK                                          0x30000
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_SHFT                                             0x10
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_BMSK                                            0xc000
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_SHFT                                               0xe
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BB_CAL_EN_BMSK                                                    0x2000
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BB_CAL_EN_SHFT                                                       0xd
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_BMSK                                      0x1800
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_SHFT                                         0xb
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BBMODE_INT_GAIN_BMSK                                               0x780
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BBMODE_INT_GAIN_SHFT                                                 0x7
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BBMODE_PROP_GAIN_BMSK                                               0x78
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_BBMODE_PROP_GAIN_SHFT                                                0x3
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_TDC_SELECTION_BMSK                                                   0x4
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_TDC_SELECTION_SHFT                                                   0x2
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_RESERVE_BIT65_BMSK                                                   0x2
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_RESERVE_BIT65_SHFT                                                   0x1
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_FORCE_DSM_ON_BMSK                                                    0x1
#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_FORCE_DSM_ON_SHFT                                                    0x0

#define HWIO_GCC_GPLL1_TEST_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00001024)
#define HWIO_GCC_GPLL1_TEST_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL1_TEST_CTL_IN          \
        in_dword(HWIO_GCC_GPLL1_TEST_CTL_ADDR)
#define HWIO_GCC_GPLL1_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_TEST_CTL_ADDR, m)
#define HWIO_GCC_GPLL1_TEST_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_TEST_CTL_ADDR,v)
#define HWIO_GCC_GPLL1_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_TEST_CTL_ADDR,m,v,HWIO_GCC_GPLL1_TEST_CTL_IN)
#define HWIO_GCC_GPLL1_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_BMSK                                       0xc0000000
#define HWIO_GCC_GPLL1_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_SHFT                                             0x1e
#define HWIO_GCC_GPLL1_TEST_CTL_BYPASS_FIRST_ORDER_DSM_BMSK                                        0x20000000
#define HWIO_GCC_GPLL1_TEST_CTL_BYPASS_FIRST_ORDER_DSM_SHFT                                              0x1d
#define HWIO_GCC_GPLL1_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_BMSK                                   0x18000000
#define HWIO_GCC_GPLL1_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_SHFT                                         0x1b
#define HWIO_GCC_GPLL1_TEST_CTL_GLITCH_PREVENTION_DIS_BMSK                                          0x4000000
#define HWIO_GCC_GPLL1_TEST_CTL_GLITCH_PREVENTION_DIS_SHFT                                               0x1a
#define HWIO_GCC_GPLL1_TEST_CTL_ATEST_ISCALE_BMSK                                                   0x3000000
#define HWIO_GCC_GPLL1_TEST_CTL_ATEST_ISCALE_SHFT                                                        0x18
#define HWIO_GCC_GPLL1_TEST_CTL_PLL_TEST_OUT_SEL_BMSK                                                0xf00000
#define HWIO_GCC_GPLL1_TEST_CTL_PLL_TEST_OUT_SEL_SHFT                                                    0x14
#define HWIO_GCC_GPLL1_TEST_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL1_TEST_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL1_TEST_CTL_DIV2_NMO_EN_BMSK                                                      0x40000
#define HWIO_GCC_GPLL1_TEST_CTL_DIV2_NMO_EN_SHFT                                                         0x12
#define HWIO_GCC_GPLL1_TEST_CTL_NMO_OSC_SEL_BMSK                                                      0x30000
#define HWIO_GCC_GPLL1_TEST_CTL_NMO_OSC_SEL_SHFT                                                         0x10
#define HWIO_GCC_GPLL1_TEST_CTL_NOISE_MAG_BMSK                                                         0xe000
#define HWIO_GCC_GPLL1_TEST_CTL_NOISE_MAG_SHFT                                                            0xd
#define HWIO_GCC_GPLL1_TEST_CTL_NOISE_GEN_EN_BMSK                                                      0x1000
#define HWIO_GCC_GPLL1_TEST_CTL_NOISE_GEN_EN_SHFT                                                         0xc
#define HWIO_GCC_GPLL1_TEST_CTL_DISABLE_DCAPS_BMSK                                                      0x800
#define HWIO_GCC_GPLL1_TEST_CTL_DISABLE_DCAPS_SHFT                                                        0xb
#define HWIO_GCC_GPLL1_TEST_CTL_RESERVE_BIT10_BMSK                                                      0x400
#define HWIO_GCC_GPLL1_TEST_CTL_RESERVE_BIT10_SHFT                                                        0xa
#define HWIO_GCC_GPLL1_TEST_CTL_RESERVE_BIT9_BMSK                                                       0x200
#define HWIO_GCC_GPLL1_TEST_CTL_RESERVE_BIT9_SHFT                                                         0x9
#define HWIO_GCC_GPLL1_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_BMSK                                            0x100
#define HWIO_GCC_GPLL1_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_SHFT                                              0x8
#define HWIO_GCC_GPLL1_TEST_CTL_EN_VDD_TEST_BMSK                                                         0x80
#define HWIO_GCC_GPLL1_TEST_CTL_EN_VDD_TEST_SHFT                                                          0x7
#define HWIO_GCC_GPLL1_TEST_CTL_EN_VREG_TEST_BMSK                                                        0x40
#define HWIO_GCC_GPLL1_TEST_CTL_EN_VREG_TEST_SHFT                                                         0x6
#define HWIO_GCC_GPLL1_TEST_CTL_EN_VREF_TEST_BMSK                                                        0x20
#define HWIO_GCC_GPLL1_TEST_CTL_EN_VREF_TEST_SHFT                                                         0x5
#define HWIO_GCC_GPLL1_TEST_CTL_EN_VDCO_TEST_BMSK                                                        0x10
#define HWIO_GCC_GPLL1_TEST_CTL_EN_VDCO_TEST_SHFT                                                         0x4
#define HWIO_GCC_GPLL1_TEST_CTL_BYPASS_ATEST_BUFFER_BMSK                                                  0x8
#define HWIO_GCC_GPLL1_TEST_CTL_BYPASS_ATEST_BUFFER_SHFT                                                  0x3
#define HWIO_GCC_GPLL1_TEST_CTL_EN_IVCO_TEST_BMSK                                                         0x4
#define HWIO_GCC_GPLL1_TEST_CTL_EN_IVCO_TEST_SHFT                                                         0x2
#define HWIO_GCC_GPLL1_TEST_CTL_ATEST1_EN_BMSK                                                            0x2
#define HWIO_GCC_GPLL1_TEST_CTL_ATEST1_EN_SHFT                                                            0x1
#define HWIO_GCC_GPLL1_TEST_CTL_ATEST0_EN_BMSK                                                            0x1
#define HWIO_GCC_GPLL1_TEST_CTL_ATEST0_EN_SHFT                                                            0x0

#define HWIO_GCC_GPLL1_TEST_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00001028)
#define HWIO_GCC_GPLL1_TEST_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL1_TEST_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL1_TEST_CTL_U_ADDR)
#define HWIO_GCC_GPLL1_TEST_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_TEST_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL1_TEST_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_TEST_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL1_TEST_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_TEST_CTL_U_ADDR,m,v,HWIO_GCC_GPLL1_TEST_CTL_U_IN)
#define HWIO_GCC_GPLL1_TEST_CTL_U_CASC_DAC_FCW_LSBS_BMSK                                           0xe0000000
#define HWIO_GCC_GPLL1_TEST_CTL_U_CASC_DAC_FCW_LSBS_SHFT                                                 0x1d
#define HWIO_GCC_GPLL1_TEST_CTL_U_OVERRIDE_CASC_DAC_BMSK                                           0x10000000
#define HWIO_GCC_GPLL1_TEST_CTL_U_OVERRIDE_CASC_DAC_SHFT                                                 0x1c
#define HWIO_GCC_GPLL1_TEST_CTL_U_COMP_COARSE_FCW_BMSK                                              0xe000000
#define HWIO_GCC_GPLL1_TEST_CTL_U_COMP_COARSE_FCW_SHFT                                                   0x19
#define HWIO_GCC_GPLL1_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_BMSK                                     0x1800000
#define HWIO_GCC_GPLL1_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_SHFT                                          0x17
#define HWIO_GCC_GPLL1_TEST_CTL_U_FINE_FCW_BMSK                                                      0x7e0000
#define HWIO_GCC_GPLL1_TEST_CTL_U_FINE_FCW_SHFT                                                          0x11
#define HWIO_GCC_GPLL1_TEST_CTL_U_OVERRIDE_FINE_FCW_BMSK                                              0x10000
#define HWIO_GCC_GPLL1_TEST_CTL_U_OVERRIDE_FINE_FCW_SHFT                                                 0x10
#define HWIO_GCC_GPLL1_TEST_CTL_U_REG_COARSE_FCW_BMSK                                                  0xfe00
#define HWIO_GCC_GPLL1_TEST_CTL_U_REG_COARSE_FCW_SHFT                                                     0x9
#define HWIO_GCC_GPLL1_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_BMSK                                          0x100
#define HWIO_GCC_GPLL1_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_SHFT                                            0x8
#define HWIO_GCC_GPLL1_TEST_CTL_U_PROCESS_CALIB_WORD_BMSK                                                0xe0
#define HWIO_GCC_GPLL1_TEST_CTL_U_PROCESS_CALIB_WORD_SHFT                                                 0x5
#define HWIO_GCC_GPLL1_TEST_CTL_U_OVERRIDE_CALIB_WORD_BMSK                                               0x10
#define HWIO_GCC_GPLL1_TEST_CTL_U_OVERRIDE_CALIB_WORD_SHFT                                                0x4
#define HWIO_GCC_GPLL1_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_BMSK                                             0x8
#define HWIO_GCC_GPLL1_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_SHFT                                             0x3
#define HWIO_GCC_GPLL1_TEST_CTL_U_DISABLE_LFSR_BMSK                                                       0x4
#define HWIO_GCC_GPLL1_TEST_CTL_U_DISABLE_LFSR_SHFT                                                       0x2
#define HWIO_GCC_GPLL1_TEST_CTL_U_SKIP_FINE_TUNE_BMSK                                                     0x2
#define HWIO_GCC_GPLL1_TEST_CTL_U_SKIP_FINE_TUNE_SHFT                                                     0x1
#define HWIO_GCC_GPLL1_TEST_CTL_U_SKIP_FAST_LOCK_BMSK                                                     0x1
#define HWIO_GCC_GPLL1_TEST_CTL_U_SKIP_FAST_LOCK_SHFT                                                     0x0

#define HWIO_GCC_GPLL1_TEST_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000102c)
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL1_TEST_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL1_TEST_CTL_U1_ADDR)
#define HWIO_GCC_GPLL1_TEST_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_TEST_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL1_TEST_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_TEST_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL1_TEST_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_TEST_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL1_TEST_CTL_U1_IN)
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL1_TEST_CTL_U1_FLL_COUNT_DISABLE_BMSK                                          0x20000000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_FLL_COUNT_DISABLE_SHFT                                                0x1d
#define HWIO_GCC_GPLL1_TEST_CTL_U1_FLL_COUNT_IN_DIV2_BMSK                                          0x10000000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_FLL_COUNT_IN_DIV2_SHFT                                                0x1c
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL1_TEST_CTL_U1_SILENCE_REF_OUTBUF_BMSK                                           0x400000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_SILENCE_REF_OUTBUF_SHFT                                               0x16
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL1_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_BMSK                                         0x40000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_SHFT                                            0x12
#define HWIO_GCC_GPLL1_TEST_CTL_U1_REF_CLK_SEL_BMSK                                                   0x20000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_REF_CLK_SEL_SHFT                                                      0x11
#define HWIO_GCC_GPLL1_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_BMSK                                     0x10000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_SHFT                                        0x10
#define HWIO_GCC_GPLL1_TEST_CTL_U1_DIS_AMP_STARTUP_BMSK                                                0x8000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_DIS_AMP_STARTUP_SHFT                                                   0xf
#define HWIO_GCC_GPLL1_TEST_CTL_U1_DISABLE_CLAMP_BMSK                                                  0x4000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_DISABLE_CLAMP_SHFT                                                     0xe
#define HWIO_GCC_GPLL1_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_BMSK                                        0x2000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_SHFT                                           0xd
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL1_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_BMSK                                          0x80
#define HWIO_GCC_GPLL1_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_SHFT                                           0x7
#define HWIO_GCC_GPLL1_TEST_CTL_U1_ENABLE_TRAINING_SEQ_BMSK                                              0x40
#define HWIO_GCC_GPLL1_TEST_CTL_U1_ENABLE_TRAINING_SEQ_SHFT                                               0x6
#define HWIO_GCC_GPLL1_TEST_CTL_U1_STATUS_REG_EN_BMSK                                                    0x20
#define HWIO_GCC_GPLL1_TEST_CTL_U1_STATUS_REG_EN_SHFT                                                     0x5
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL1_TEST_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL1_TEST_CTL_U1_CASC_DAC_FCW_MSBS_BMSK                                                 0x3
#define HWIO_GCC_GPLL1_TEST_CTL_U1_CASC_DAC_FCW_MSBS_SHFT                                                 0x0

#define HWIO_GCC_GPLL1_STATUS_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00001030)
#define HWIO_GCC_GPLL1_STATUS_RMSK                                                                 0xffffffff
#define HWIO_GCC_GPLL1_STATUS_IN          \
        in_dword(HWIO_GCC_GPLL1_STATUS_ADDR)
#define HWIO_GCC_GPLL1_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_STATUS_ADDR, m)
#define HWIO_GCC_GPLL1_STATUS_STATUS_31_0_BMSK                                                     0xffffffff
#define HWIO_GCC_GPLL1_STATUS_STATUS_31_0_SHFT                                                            0x0

#define HWIO_GCC_GPLL1_FREQ_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00001034)
#define HWIO_GCC_GPLL1_FREQ_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL1_FREQ_CTL_IN          \
        in_dword(HWIO_GCC_GPLL1_FREQ_CTL_ADDR)
#define HWIO_GCC_GPLL1_FREQ_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_FREQ_CTL_ADDR, m)
#define HWIO_GCC_GPLL1_FREQ_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_FREQ_CTL_ADDR,v)
#define HWIO_GCC_GPLL1_FREQ_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_FREQ_CTL_ADDR,m,v,HWIO_GCC_GPLL1_FREQ_CTL_IN)
#define HWIO_GCC_GPLL1_FREQ_CTL_FREQUENCY_CTL_WORD_BMSK                                            0xffffffff
#define HWIO_GCC_GPLL1_FREQ_CTL_FREQUENCY_CTL_WORD_SHFT                                                   0x0

#define HWIO_GCC_GPLL1_OPMODE_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00001038)
#define HWIO_GCC_GPLL1_OPMODE_RMSK                                                                        0x7
#define HWIO_GCC_GPLL1_OPMODE_IN          \
        in_dword(HWIO_GCC_GPLL1_OPMODE_ADDR)
#define HWIO_GCC_GPLL1_OPMODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_OPMODE_ADDR, m)
#define HWIO_GCC_GPLL1_OPMODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_OPMODE_ADDR,v)
#define HWIO_GCC_GPLL1_OPMODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_OPMODE_ADDR,m,v,HWIO_GCC_GPLL1_OPMODE_IN)
#define HWIO_GCC_GPLL1_OPMODE_PLL_OPMODE_BMSK                                                             0x7
#define HWIO_GCC_GPLL1_OPMODE_PLL_OPMODE_SHFT                                                             0x0

#define HWIO_GCC_GPLL1_STATE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0000103c)
#define HWIO_GCC_GPLL1_STATE_RMSK                                                                         0x7
#define HWIO_GCC_GPLL1_STATE_IN          \
        in_dword(HWIO_GCC_GPLL1_STATE_ADDR)
#define HWIO_GCC_GPLL1_STATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_STATE_ADDR, m)
#define HWIO_GCC_GPLL1_STATE_PLL_STATE_BMSK                                                               0x7
#define HWIO_GCC_GPLL1_STATE_PLL_STATE_SHFT                                                               0x0

#define HWIO_GCC_GPLL1_ALPHA_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00001040)
#define HWIO_GCC_GPLL1_ALPHA_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL1_ALPHA_VAL_IN          \
        in_dword(HWIO_GCC_GPLL1_ALPHA_VAL_ADDR)
#define HWIO_GCC_GPLL1_ALPHA_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_ALPHA_VAL_ADDR, m)
#define HWIO_GCC_GPLL1_ALPHA_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_ALPHA_VAL_ADDR,v)
#define HWIO_GCC_GPLL1_ALPHA_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_ALPHA_VAL_ADDR,m,v,HWIO_GCC_GPLL1_ALPHA_VAL_IN)
#define HWIO_GCC_GPLL1_ALPHA_VAL_PLL_ALPHA_VAL_BMSK                                                    0xffff
#define HWIO_GCC_GPLL1_ALPHA_VAL_PLL_ALPHA_VAL_SHFT                                                       0x0

#define HWIO_GCC_GPLL1_SPARE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00001044)
#define HWIO_GCC_GPLL1_SPARE_RMSK                                                                        0xff
#define HWIO_GCC_GPLL1_SPARE_IN          \
        in_dword(HWIO_GCC_GPLL1_SPARE_ADDR)
#define HWIO_GCC_GPLL1_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_SPARE_ADDR, m)
#define HWIO_GCC_GPLL1_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_SPARE_ADDR,v)
#define HWIO_GCC_GPLL1_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_SPARE_ADDR,m,v,HWIO_GCC_GPLL1_SPARE_IN)
#define HWIO_GCC_GPLL1_SPARE_SPARE_OUTPUTS_BMSK                                                          0xf0
#define HWIO_GCC_GPLL1_SPARE_SPARE_OUTPUTS_SHFT                                                           0x4
#define HWIO_GCC_GPLL1_SPARE_SPARE_INPUTS_BMSK                                                            0xf
#define HWIO_GCC_GPLL1_SPARE_SPARE_INPUTS_SHFT                                                            0x0

#define HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00001048)
#define HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_RMSK                                                              0xff
#define HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_IN          \
        in_dword(HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_ADDR)
#define HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_ADDR, m)
#define HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_ADDR,v)
#define HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_ADDR,m,v,HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_IN)
#define HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_BMSK                                              0xff
#define HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_SHFT                                               0x0

#define HWIO_GCC_GPLL1_SSC_NUM_STEPS_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000104c)
#define HWIO_GCC_GPLL1_SSC_NUM_STEPS_RMSK                                                                 0xf
#define HWIO_GCC_GPLL1_SSC_NUM_STEPS_IN          \
        in_dword(HWIO_GCC_GPLL1_SSC_NUM_STEPS_ADDR)
#define HWIO_GCC_GPLL1_SSC_NUM_STEPS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_SSC_NUM_STEPS_ADDR, m)
#define HWIO_GCC_GPLL1_SSC_NUM_STEPS_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_SSC_NUM_STEPS_ADDR,v)
#define HWIO_GCC_GPLL1_SSC_NUM_STEPS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_SSC_NUM_STEPS_ADDR,m,v,HWIO_GCC_GPLL1_SSC_NUM_STEPS_IN)
#define HWIO_GCC_GPLL1_SSC_NUM_STEPS_SSC_NUM_STEPS_BMSK                                                   0xf
#define HWIO_GCC_GPLL1_SSC_NUM_STEPS_SSC_NUM_STEPS_SHFT                                                   0x0

#define HWIO_GCC_GPLL1_SSC_UPDATE_RATE_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00001050)
#define HWIO_GCC_GPLL1_SSC_UPDATE_RATE_RMSK                                                               0xf
#define HWIO_GCC_GPLL1_SSC_UPDATE_RATE_IN          \
        in_dword(HWIO_GCC_GPLL1_SSC_UPDATE_RATE_ADDR)
#define HWIO_GCC_GPLL1_SSC_UPDATE_RATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL1_SSC_UPDATE_RATE_ADDR, m)
#define HWIO_GCC_GPLL1_SSC_UPDATE_RATE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL1_SSC_UPDATE_RATE_ADDR,v)
#define HWIO_GCC_GPLL1_SSC_UPDATE_RATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL1_SSC_UPDATE_RATE_ADDR,m,v,HWIO_GCC_GPLL1_SSC_UPDATE_RATE_IN)
#define HWIO_GCC_GPLL1_SSC_UPDATE_RATE_SSC_UPDATE_RATE_BMSK                                               0xf
#define HWIO_GCC_GPLL1_SSC_UPDATE_RATE_SSC_UPDATE_RATE_SHFT                                               0x0

#define HWIO_GCC_GPLL2_MODE_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00002000)
#define HWIO_GCC_GPLL2_MODE_RMSK                                                                   0xffffffff
#define HWIO_GCC_GPLL2_MODE_IN          \
        in_dword(HWIO_GCC_GPLL2_MODE_ADDR)
#define HWIO_GCC_GPLL2_MODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_MODE_ADDR, m)
#define HWIO_GCC_GPLL2_MODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_MODE_ADDR,v)
#define HWIO_GCC_GPLL2_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_MODE_ADDR,m,v,HWIO_GCC_GPLL2_MODE_IN)
#define HWIO_GCC_GPLL2_MODE_PLL_LOCK_DET_BMSK                                                      0x80000000
#define HWIO_GCC_GPLL2_MODE_PLL_LOCK_DET_SHFT                                                            0x1f
#define HWIO_GCC_GPLL2_MODE_PLL_ACTIVE_FLAG_BMSK                                                   0x40000000
#define HWIO_GCC_GPLL2_MODE_PLL_ACTIVE_FLAG_SHFT                                                         0x1e
#define HWIO_GCC_GPLL2_MODE_PLL_ACK_LATCH_BMSK                                                     0x20000000
#define HWIO_GCC_GPLL2_MODE_PLL_ACK_LATCH_SHFT                                                           0x1d
#define HWIO_GCC_GPLL2_MODE_PLL_LOCK_DET_FINE_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL2_MODE_PLL_LOCK_DET_FINE_SHFT                                                       0x1c
#define HWIO_GCC_GPLL2_MODE_PCAL_DONE_BMSK                                                          0x8000000
#define HWIO_GCC_GPLL2_MODE_PCAL_DONE_SHFT                                                               0x1b
#define HWIO_GCC_GPLL2_MODE_RESERVE_BITS26_25_BMSK                                                  0x6000000
#define HWIO_GCC_GPLL2_MODE_RESERVE_BITS26_25_SHFT                                                       0x19
#define HWIO_GCC_GPLL2_MODE_FSM_LEGACY_MODE_BMSK                                                    0x1000000
#define HWIO_GCC_GPLL2_MODE_FSM_LEGACY_MODE_SHFT                                                         0x18
#define HWIO_GCC_GPLL2_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_BMSK                                          0x800000
#define HWIO_GCC_GPLL2_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_SHFT                                              0x17
#define HWIO_GCC_GPLL2_MODE_PLL_UPDATE_BMSK                                                          0x400000
#define HWIO_GCC_GPLL2_MODE_PLL_UPDATE_SHFT                                                              0x16
#define HWIO_GCC_GPLL2_MODE_PLL_VOTE_FSM_RESET_BMSK                                                  0x200000
#define HWIO_GCC_GPLL2_MODE_PLL_VOTE_FSM_RESET_SHFT                                                      0x15
#define HWIO_GCC_GPLL2_MODE_PLL_VOTE_FSM_ENA_BMSK                                                    0x100000
#define HWIO_GCC_GPLL2_MODE_PLL_VOTE_FSM_ENA_SHFT                                                        0x14
#define HWIO_GCC_GPLL2_MODE_PLL_BIAS_COUNT_BMSK                                                       0xfc000
#define HWIO_GCC_GPLL2_MODE_PLL_BIAS_COUNT_SHFT                                                           0xe
#define HWIO_GCC_GPLL2_MODE_PLL_LOCK_COUNT_BMSK                                                        0x3f00
#define HWIO_GCC_GPLL2_MODE_PLL_LOCK_COUNT_SHFT                                                           0x8
#define HWIO_GCC_GPLL2_MODE_RESERVE_BIT7_BMSK                                                            0x80
#define HWIO_GCC_GPLL2_MODE_RESERVE_BIT7_SHFT                                                             0x7
#define HWIO_GCC_GPLL2_MODE_OUT_TEST_HW_CTL_BMSK                                                         0x40
#define HWIO_GCC_GPLL2_MODE_OUT_TEST_HW_CTL_SHFT                                                          0x6
#define HWIO_GCC_GPLL2_MODE_OUT_ODD_HW_CTL_BMSK                                                          0x20
#define HWIO_GCC_GPLL2_MODE_OUT_ODD_HW_CTL_SHFT                                                           0x5
#define HWIO_GCC_GPLL2_MODE_OUT_EVEN_HW_CTL_BMSK                                                         0x10
#define HWIO_GCC_GPLL2_MODE_OUT_EVEN_HW_CTL_SHFT                                                          0x4
#define HWIO_GCC_GPLL2_MODE_OUT_MAIN_HW_CTL_BMSK                                                          0x8
#define HWIO_GCC_GPLL2_MODE_OUT_MAIN_HW_CTL_SHFT                                                          0x3
#define HWIO_GCC_GPLL2_MODE_PLL_RESET_N_BMSK                                                              0x4
#define HWIO_GCC_GPLL2_MODE_PLL_RESET_N_SHFT                                                              0x2
#define HWIO_GCC_GPLL2_MODE_RESERVE_BIT1_BMSK                                                             0x2
#define HWIO_GCC_GPLL2_MODE_RESERVE_BIT1_SHFT                                                             0x1
#define HWIO_GCC_GPLL2_MODE_PLL_OUTCTRL_BMSK                                                              0x1
#define HWIO_GCC_GPLL2_MODE_PLL_OUTCTRL_SHFT                                                              0x0

#define HWIO_GCC_GPLL2_L_VAL_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00002004)
#define HWIO_GCC_GPLL2_L_VAL_RMSK                                                                      0xffff
#define HWIO_GCC_GPLL2_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL2_L_VAL_ADDR)
#define HWIO_GCC_GPLL2_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL2_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL2_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_L_VAL_ADDR,m,v,HWIO_GCC_GPLL2_L_VAL_IN)
#define HWIO_GCC_GPLL2_L_VAL_PLL_L_BMSK                                                                0xffff
#define HWIO_GCC_GPLL2_L_VAL_PLL_L_SHFT                                                                   0x0

#define HWIO_GCC_GPLL2_CAL_L_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00002008)
#define HWIO_GCC_GPLL2_CAL_L_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL2_CAL_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL2_CAL_L_VAL_ADDR)
#define HWIO_GCC_GPLL2_CAL_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_CAL_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL2_CAL_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_CAL_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL2_CAL_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_CAL_L_VAL_ADDR,m,v,HWIO_GCC_GPLL2_CAL_L_VAL_IN)
#define HWIO_GCC_GPLL2_CAL_L_VAL_PLL_CAL_L_BMSK                                                        0xffff
#define HWIO_GCC_GPLL2_CAL_L_VAL_PLL_CAL_L_SHFT                                                           0x0

#define HWIO_GCC_GPLL2_USER_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0000200c)
#define HWIO_GCC_GPLL2_USER_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL2_USER_CTL_IN          \
        in_dword(HWIO_GCC_GPLL2_USER_CTL_ADDR)
#define HWIO_GCC_GPLL2_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_USER_CTL_ADDR, m)
#define HWIO_GCC_GPLL2_USER_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_USER_CTL_ADDR,v)
#define HWIO_GCC_GPLL2_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_USER_CTL_ADDR,m,v,HWIO_GCC_GPLL2_USER_CTL_IN)
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT31_BMSK                                                 0x80000000
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT31_SHFT                                                       0x1f
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT30_BMSK                                                 0x40000000
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT30_SHFT                                                       0x1e
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT29_BMSK                                                 0x20000000
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT29_SHFT                                                       0x1d
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT28_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT28_SHFT                                                       0x1c
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT27_BMSK                                                  0x8000000
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT27_SHFT                                                       0x1b
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT26_BMSK                                                  0x4000000
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT26_SHFT                                                       0x1a
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT25_BMSK                                                  0x2000000
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT25_SHFT                                                       0x19
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT24_BMSK                                                  0x1000000
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT24_SHFT                                                       0x18
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT23_BMSK                                                   0x800000
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT23_SHFT                                                       0x17
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT22_BMSK                                                   0x400000
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT22_SHFT                                                       0x16
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT21_BMSK                                                   0x200000
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT21_SHFT                                                       0x15
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT20_BMSK                                                   0x100000
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT20_SHFT                                                       0x14
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL2_USER_CTL_PRE_DIV_RATIO_BMSK                                                    0x70000
#define HWIO_GCC_GPLL2_USER_CTL_PRE_DIV_RATIO_SHFT                                                       0x10
#define HWIO_GCC_GPLL2_USER_CTL_POST_DIV_RATIO_ODD_BMSK                                                0xf000
#define HWIO_GCC_GPLL2_USER_CTL_POST_DIV_RATIO_ODD_SHFT                                                   0xc
#define HWIO_GCC_GPLL2_USER_CTL_POST_DIV_RATIO_EVEN_BMSK                                                0xf00
#define HWIO_GCC_GPLL2_USER_CTL_POST_DIV_RATIO_EVEN_SHFT                                                  0x8
#define HWIO_GCC_GPLL2_USER_CTL_OUT_CLK_POLARITY_BMSK                                                    0x80
#define HWIO_GCC_GPLL2_USER_CTL_OUT_CLK_POLARITY_SHFT                                                     0x7
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT6_BMSK                                                        0x40
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT6_SHFT                                                         0x6
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT5_BMSK                                                        0x20
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT5_SHFT                                                         0x5
#define HWIO_GCC_GPLL2_USER_CTL_PLLOUT_TEST_BMSK                                                         0x10
#define HWIO_GCC_GPLL2_USER_CTL_PLLOUT_TEST_SHFT                                                          0x4
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT3_BMSK                                                         0x8
#define HWIO_GCC_GPLL2_USER_CTL_RESERVE_BIT3_SHFT                                                         0x3
#define HWIO_GCC_GPLL2_USER_CTL_PLLOUT_ODD_BMSK                                                           0x4
#define HWIO_GCC_GPLL2_USER_CTL_PLLOUT_ODD_SHFT                                                           0x2
#define HWIO_GCC_GPLL2_USER_CTL_PLLOUT_EVEN_BMSK                                                          0x2
#define HWIO_GCC_GPLL2_USER_CTL_PLLOUT_EVEN_SHFT                                                          0x1
#define HWIO_GCC_GPLL2_USER_CTL_PLLOUT_MAIN_BMSK                                                          0x1
#define HWIO_GCC_GPLL2_USER_CTL_PLLOUT_MAIN_SHFT                                                          0x0

#define HWIO_GCC_GPLL2_USER_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00002010)
#define HWIO_GCC_GPLL2_USER_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL2_USER_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL2_USER_CTL_U_ADDR)
#define HWIO_GCC_GPLL2_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_USER_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL2_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_USER_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL2_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_USER_CTL_U_ADDR,m,v,HWIO_GCC_GPLL2_USER_CTL_U_IN)
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT63_BMSK                                               0x80000000
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT63_SHFT                                                     0x1f
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT62_BMSK                                               0x40000000
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT62_SHFT                                                     0x1e
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT61_BMSK                                               0x20000000
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT61_SHFT                                                     0x1d
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT60_BMSK                                               0x10000000
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT60_SHFT                                                     0x1c
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT59_BMSK                                                0x8000000
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT59_SHFT                                                     0x1b
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT58_BMSK                                                0x4000000
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT58_SHFT                                                     0x1a
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT57_BMSK                                                0x2000000
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT57_SHFT                                                     0x19
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT56_BMSK                                                0x1000000
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT56_SHFT                                                     0x18
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT55_BMSK                                                 0x800000
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT55_SHFT                                                     0x17
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT54_BMSK                                                 0x400000
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT54_SHFT                                                     0x16
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT53_BMSK                                                 0x200000
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT53_SHFT                                                     0x15
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT52_BMSK                                                 0x100000
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT52_SHFT                                                     0x14
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT51_BMSK                                                  0x80000
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT51_SHFT                                                     0x13
#define HWIO_GCC_GPLL2_USER_CTL_U_LOCK_DETECTOR_SELECTION_BMSK                                        0x40000
#define HWIO_GCC_GPLL2_USER_CTL_U_LOCK_DETECTOR_SELECTION_SHFT                                           0x12
#define HWIO_GCC_GPLL2_USER_CTL_U_TYPE_2_MODE_SELECTION_BMSK                                          0x20000
#define HWIO_GCC_GPLL2_USER_CTL_U_TYPE_2_MODE_SELECTION_SHFT                                             0x11
#define HWIO_GCC_GPLL2_USER_CTL_U_BANG_BANG_MODE_SELECTION_BMSK                                       0x10000
#define HWIO_GCC_GPLL2_USER_CTL_U_BANG_BANG_MODE_SELECTION_SHFT                                          0x10
#define HWIO_GCC_GPLL2_USER_CTL_U_FRAC_FORMAT_SEL_BMSK                                                 0x8000
#define HWIO_GCC_GPLL2_USER_CTL_U_FRAC_FORMAT_SEL_SHFT                                                    0xf
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT46_BMSK                                                   0x4000
#define HWIO_GCC_GPLL2_USER_CTL_U_RESERVE_BIT46_SHFT                                                      0xe
#define HWIO_GCC_GPLL2_USER_CTL_U_REF_CLK_AT_OUT_BMSK                                                  0x2000
#define HWIO_GCC_GPLL2_USER_CTL_U_REF_CLK_AT_OUT_SHFT                                                     0xd
#define HWIO_GCC_GPLL2_USER_CTL_U_SCALE_FREQ_ON_RESTART_BMSK                                           0x1800
#define HWIO_GCC_GPLL2_USER_CTL_U_SCALE_FREQ_ON_RESTART_SHFT                                              0xb
#define HWIO_GCC_GPLL2_USER_CTL_U_LATCH_INTERFACE_BYPASS_BMSK                                           0x400
#define HWIO_GCC_GPLL2_USER_CTL_U_LATCH_INTERFACE_BYPASS_SHFT                                             0xa
#define HWIO_GCC_GPLL2_USER_CTL_U_STATUS_REGISTER_BMSK                                                  0x3e0
#define HWIO_GCC_GPLL2_USER_CTL_U_STATUS_REGISTER_SHFT                                                    0x5
#define HWIO_GCC_GPLL2_USER_CTL_U_WRITE_STATE_EN_BMSK                                                    0x10
#define HWIO_GCC_GPLL2_USER_CTL_U_WRITE_STATE_EN_SHFT                                                     0x4
#define HWIO_GCC_GPLL2_USER_CTL_U_CALIB_CTRL_BMSK                                                         0xe
#define HWIO_GCC_GPLL2_USER_CTL_U_CALIB_CTRL_SHFT                                                         0x1
#define HWIO_GCC_GPLL2_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_BMSK                                             0x1
#define HWIO_GCC_GPLL2_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_SHFT                                             0x0

#define HWIO_GCC_GPLL2_USER_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00002014)
#define HWIO_GCC_GPLL2_USER_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL2_USER_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL2_USER_CTL_U1_ADDR)
#define HWIO_GCC_GPLL2_USER_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_USER_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL2_USER_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_USER_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL2_USER_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_USER_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL2_USER_CTL_U1_IN)
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT93_BMSK                                              0x20000000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT93_SHFT                                                    0x1d
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT92_BMSK                                              0x10000000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT92_SHFT                                                    0x1c
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT86_BMSK                                                0x400000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT86_SHFT                                                    0x16
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT82_BMSK                                                 0x40000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT82_SHFT                                                    0x12
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT81_BMSK                                                 0x20000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT81_SHFT                                                    0x11
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT80_BMSK                                                 0x10000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT80_SHFT                                                    0x10
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT79_BMSK                                                  0x8000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT79_SHFT                                                     0xf
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT78_BMSK                                                  0x4000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT78_SHFT                                                     0xe
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT77_BMSK                                                  0x2000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT77_SHFT                                                     0xd
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT71_BMSK                                                    0x80
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT71_SHFT                                                     0x7
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT70_BMSK                                                    0x40
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT70_SHFT                                                     0x6
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT69_BMSK                                                    0x20
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT69_SHFT                                                     0x5
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT65_BMSK                                                     0x2
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT65_SHFT                                                     0x1
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT64_BMSK                                                     0x1
#define HWIO_GCC_GPLL2_USER_CTL_U1_RESERVE_BIT64_SHFT                                                     0x0

#define HWIO_GCC_GPLL2_CONFIG_CTL_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00002018)
#define HWIO_GCC_GPLL2_CONFIG_CTL_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL2_CONFIG_CTL_IN          \
        in_dword(HWIO_GCC_GPLL2_CONFIG_CTL_ADDR)
#define HWIO_GCC_GPLL2_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_CONFIG_CTL_ADDR, m)
#define HWIO_GCC_GPLL2_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_CONFIG_CTL_ADDR,v)
#define HWIO_GCC_GPLL2_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_CONFIG_CTL_ADDR,m,v,HWIO_GCC_GPLL2_CONFIG_CTL_IN)
#define HWIO_GCC_GPLL2_CONFIG_CTL_FINE_LDC_THRESHOLD_BMSK                                          0xfc000000
#define HWIO_GCC_GPLL2_CONFIG_CTL_FINE_LDC_THRESHOLD_SHFT                                                0x1a
#define HWIO_GCC_GPLL2_CONFIG_CTL_COARSE_LDC_THRESHOLD_BMSK                                         0x3c00000
#define HWIO_GCC_GPLL2_CONFIG_CTL_COARSE_LDC_THRESHOLD_SHFT                                              0x16
#define HWIO_GCC_GPLL2_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_BMSK                                 0x3c0000
#define HWIO_GCC_GPLL2_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_SHFT                                     0x12
#define HWIO_GCC_GPLL2_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_BMSK                                  0x3c000
#define HWIO_GCC_GPLL2_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_SHFT                                      0xe
#define HWIO_GCC_GPLL2_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_BMSK                                         0x3800
#define HWIO_GCC_GPLL2_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_SHFT                                            0xb
#define HWIO_GCC_GPLL2_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_BMSK                                        0x700
#define HWIO_GCC_GPLL2_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_SHFT                                          0x8
#define HWIO_GCC_GPLL2_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_BMSK                                              0xf0
#define HWIO_GCC_GPLL2_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_SHFT                                               0x4
#define HWIO_GCC_GPLL2_CONFIG_CTL_FWD_GAIN_KFN_BMSK                                                       0xf
#define HWIO_GCC_GPLL2_CONFIG_CTL_FWD_GAIN_KFN_SHFT                                                       0x0

#define HWIO_GCC_GPLL2_CONFIG_CTL_U_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000201c)
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_RMSK                                                           0xffffffff
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL2_CONFIG_CTL_U_ADDR)
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_CONFIG_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_CONFIG_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_CONFIG_CTL_U_ADDR,m,v,HWIO_GCC_GPLL2_CONFIG_CTL_U_IN)
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_BIST_CFG_BMSK                                                  0xffff0000
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_BIST_CFG_SHFT                                                        0x10
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_BMSK                                       0xc000
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_SHFT                                          0xe
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_OSC_SETTLING_TIME_BMSK                                             0x3000
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_OSC_SETTLING_TIME_SHFT                                                0xc
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_BMSK                                            0xc00
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_SHFT                                              0xa
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_CASC_CURRENT_CTL_B_BMSK                                             0x380
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_CASC_CURRENT_CTL_B_SHFT                                               0x7
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_BMSK                                     0x40
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_SHFT                                      0x6
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_BMSK                                            0x30
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_SHFT                                             0x4
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_LDET_THRESH_SCALE_BMSK                                                0x8
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_LDET_THRESH_SCALE_SHFT                                                0x3
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_DCO_STARTUP_CONFIG_BMSK                                               0x6
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_DCO_STARTUP_CONFIG_SHFT                                               0x1
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_BMSK                                          0x1
#define HWIO_GCC_GPLL2_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_SHFT                                          0x0

#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00002020)
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_RMSK                                                          0xffffffff
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL2_CONFIG_CTL_U1_ADDR)
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_CONFIG_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_CONFIG_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_CONFIG_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL2_CONFIG_CTL_U1_IN)
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BB_CAL_THRESHOLD_BMSK                                         0xc0000000
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BB_CAL_THRESHOLD_SHFT                                               0x1e
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_PCODE_OFFSET_BMSK                                             0x38000000
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_PCODE_OFFSET_SHFT                                                   0x1b
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_COUNTER_BLANK_BMSK                                             0x4000000
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_COUNTER_BLANK_SHFT                                                  0x1a
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BB_RESYNC_EDGE_BMSK                                            0x2000000
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BB_RESYNC_EDGE_SHFT                                                 0x19
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BB_RESYNC_SEL_BMSK                                             0x1000000
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BB_RESYNC_SEL_SHFT                                                  0x18
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_BMSK                                        0xc00000
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_SHFT                                            0x16
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BB_LOCK_THRESH_BMSK                                             0x380000
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BB_LOCK_THRESH_SHFT                                                 0x13
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_RESERVE_BIT82_BMSK                                               0x40000
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_RESERVE_BIT82_SHFT                                                  0x12
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_BMSK                                          0x30000
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_SHFT                                             0x10
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_BMSK                                            0xc000
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_SHFT                                               0xe
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BB_CAL_EN_BMSK                                                    0x2000
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BB_CAL_EN_SHFT                                                       0xd
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_BMSK                                      0x1800
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_SHFT                                         0xb
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BBMODE_INT_GAIN_BMSK                                               0x780
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BBMODE_INT_GAIN_SHFT                                                 0x7
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BBMODE_PROP_GAIN_BMSK                                               0x78
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_BBMODE_PROP_GAIN_SHFT                                                0x3
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_TDC_SELECTION_BMSK                                                   0x4
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_TDC_SELECTION_SHFT                                                   0x2
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_RESERVE_BIT65_BMSK                                                   0x2
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_RESERVE_BIT65_SHFT                                                   0x1
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_FORCE_DSM_ON_BMSK                                                    0x1
#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_FORCE_DSM_ON_SHFT                                                    0x0

#define HWIO_GCC_GPLL2_TEST_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00002024)
#define HWIO_GCC_GPLL2_TEST_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL2_TEST_CTL_IN          \
        in_dword(HWIO_GCC_GPLL2_TEST_CTL_ADDR)
#define HWIO_GCC_GPLL2_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_TEST_CTL_ADDR, m)
#define HWIO_GCC_GPLL2_TEST_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_TEST_CTL_ADDR,v)
#define HWIO_GCC_GPLL2_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_TEST_CTL_ADDR,m,v,HWIO_GCC_GPLL2_TEST_CTL_IN)
#define HWIO_GCC_GPLL2_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_BMSK                                       0xc0000000
#define HWIO_GCC_GPLL2_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_SHFT                                             0x1e
#define HWIO_GCC_GPLL2_TEST_CTL_BYPASS_FIRST_ORDER_DSM_BMSK                                        0x20000000
#define HWIO_GCC_GPLL2_TEST_CTL_BYPASS_FIRST_ORDER_DSM_SHFT                                              0x1d
#define HWIO_GCC_GPLL2_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_BMSK                                   0x18000000
#define HWIO_GCC_GPLL2_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_SHFT                                         0x1b
#define HWIO_GCC_GPLL2_TEST_CTL_GLITCH_PREVENTION_DIS_BMSK                                          0x4000000
#define HWIO_GCC_GPLL2_TEST_CTL_GLITCH_PREVENTION_DIS_SHFT                                               0x1a
#define HWIO_GCC_GPLL2_TEST_CTL_ATEST_ISCALE_BMSK                                                   0x3000000
#define HWIO_GCC_GPLL2_TEST_CTL_ATEST_ISCALE_SHFT                                                        0x18
#define HWIO_GCC_GPLL2_TEST_CTL_PLL_TEST_OUT_SEL_BMSK                                                0xf00000
#define HWIO_GCC_GPLL2_TEST_CTL_PLL_TEST_OUT_SEL_SHFT                                                    0x14
#define HWIO_GCC_GPLL2_TEST_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL2_TEST_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL2_TEST_CTL_DIV2_NMO_EN_BMSK                                                      0x40000
#define HWIO_GCC_GPLL2_TEST_CTL_DIV2_NMO_EN_SHFT                                                         0x12
#define HWIO_GCC_GPLL2_TEST_CTL_NMO_OSC_SEL_BMSK                                                      0x30000
#define HWIO_GCC_GPLL2_TEST_CTL_NMO_OSC_SEL_SHFT                                                         0x10
#define HWIO_GCC_GPLL2_TEST_CTL_NOISE_MAG_BMSK                                                         0xe000
#define HWIO_GCC_GPLL2_TEST_CTL_NOISE_MAG_SHFT                                                            0xd
#define HWIO_GCC_GPLL2_TEST_CTL_NOISE_GEN_EN_BMSK                                                      0x1000
#define HWIO_GCC_GPLL2_TEST_CTL_NOISE_GEN_EN_SHFT                                                         0xc
#define HWIO_GCC_GPLL2_TEST_CTL_DISABLE_DCAPS_BMSK                                                      0x800
#define HWIO_GCC_GPLL2_TEST_CTL_DISABLE_DCAPS_SHFT                                                        0xb
#define HWIO_GCC_GPLL2_TEST_CTL_RESERVE_BIT10_BMSK                                                      0x400
#define HWIO_GCC_GPLL2_TEST_CTL_RESERVE_BIT10_SHFT                                                        0xa
#define HWIO_GCC_GPLL2_TEST_CTL_RESERVE_BIT9_BMSK                                                       0x200
#define HWIO_GCC_GPLL2_TEST_CTL_RESERVE_BIT9_SHFT                                                         0x9
#define HWIO_GCC_GPLL2_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_BMSK                                            0x100
#define HWIO_GCC_GPLL2_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_SHFT                                              0x8
#define HWIO_GCC_GPLL2_TEST_CTL_EN_VDD_TEST_BMSK                                                         0x80
#define HWIO_GCC_GPLL2_TEST_CTL_EN_VDD_TEST_SHFT                                                          0x7
#define HWIO_GCC_GPLL2_TEST_CTL_EN_VREG_TEST_BMSK                                                        0x40
#define HWIO_GCC_GPLL2_TEST_CTL_EN_VREG_TEST_SHFT                                                         0x6
#define HWIO_GCC_GPLL2_TEST_CTL_EN_VREF_TEST_BMSK                                                        0x20
#define HWIO_GCC_GPLL2_TEST_CTL_EN_VREF_TEST_SHFT                                                         0x5
#define HWIO_GCC_GPLL2_TEST_CTL_EN_VDCO_TEST_BMSK                                                        0x10
#define HWIO_GCC_GPLL2_TEST_CTL_EN_VDCO_TEST_SHFT                                                         0x4
#define HWIO_GCC_GPLL2_TEST_CTL_BYPASS_ATEST_BUFFER_BMSK                                                  0x8
#define HWIO_GCC_GPLL2_TEST_CTL_BYPASS_ATEST_BUFFER_SHFT                                                  0x3
#define HWIO_GCC_GPLL2_TEST_CTL_EN_IVCO_TEST_BMSK                                                         0x4
#define HWIO_GCC_GPLL2_TEST_CTL_EN_IVCO_TEST_SHFT                                                         0x2
#define HWIO_GCC_GPLL2_TEST_CTL_ATEST1_EN_BMSK                                                            0x2
#define HWIO_GCC_GPLL2_TEST_CTL_ATEST1_EN_SHFT                                                            0x1
#define HWIO_GCC_GPLL2_TEST_CTL_ATEST0_EN_BMSK                                                            0x1
#define HWIO_GCC_GPLL2_TEST_CTL_ATEST0_EN_SHFT                                                            0x0

#define HWIO_GCC_GPLL2_TEST_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00002028)
#define HWIO_GCC_GPLL2_TEST_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL2_TEST_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL2_TEST_CTL_U_ADDR)
#define HWIO_GCC_GPLL2_TEST_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_TEST_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL2_TEST_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_TEST_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL2_TEST_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_TEST_CTL_U_ADDR,m,v,HWIO_GCC_GPLL2_TEST_CTL_U_IN)
#define HWIO_GCC_GPLL2_TEST_CTL_U_CASC_DAC_FCW_LSBS_BMSK                                           0xe0000000
#define HWIO_GCC_GPLL2_TEST_CTL_U_CASC_DAC_FCW_LSBS_SHFT                                                 0x1d
#define HWIO_GCC_GPLL2_TEST_CTL_U_OVERRIDE_CASC_DAC_BMSK                                           0x10000000
#define HWIO_GCC_GPLL2_TEST_CTL_U_OVERRIDE_CASC_DAC_SHFT                                                 0x1c
#define HWIO_GCC_GPLL2_TEST_CTL_U_COMP_COARSE_FCW_BMSK                                              0xe000000
#define HWIO_GCC_GPLL2_TEST_CTL_U_COMP_COARSE_FCW_SHFT                                                   0x19
#define HWIO_GCC_GPLL2_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_BMSK                                     0x1800000
#define HWIO_GCC_GPLL2_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_SHFT                                          0x17
#define HWIO_GCC_GPLL2_TEST_CTL_U_FINE_FCW_BMSK                                                      0x7e0000
#define HWIO_GCC_GPLL2_TEST_CTL_U_FINE_FCW_SHFT                                                          0x11
#define HWIO_GCC_GPLL2_TEST_CTL_U_OVERRIDE_FINE_FCW_BMSK                                              0x10000
#define HWIO_GCC_GPLL2_TEST_CTL_U_OVERRIDE_FINE_FCW_SHFT                                                 0x10
#define HWIO_GCC_GPLL2_TEST_CTL_U_REG_COARSE_FCW_BMSK                                                  0xfe00
#define HWIO_GCC_GPLL2_TEST_CTL_U_REG_COARSE_FCW_SHFT                                                     0x9
#define HWIO_GCC_GPLL2_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_BMSK                                          0x100
#define HWIO_GCC_GPLL2_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_SHFT                                            0x8
#define HWIO_GCC_GPLL2_TEST_CTL_U_PROCESS_CALIB_WORD_BMSK                                                0xe0
#define HWIO_GCC_GPLL2_TEST_CTL_U_PROCESS_CALIB_WORD_SHFT                                                 0x5
#define HWIO_GCC_GPLL2_TEST_CTL_U_OVERRIDE_CALIB_WORD_BMSK                                               0x10
#define HWIO_GCC_GPLL2_TEST_CTL_U_OVERRIDE_CALIB_WORD_SHFT                                                0x4
#define HWIO_GCC_GPLL2_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_BMSK                                             0x8
#define HWIO_GCC_GPLL2_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_SHFT                                             0x3
#define HWIO_GCC_GPLL2_TEST_CTL_U_DISABLE_LFSR_BMSK                                                       0x4
#define HWIO_GCC_GPLL2_TEST_CTL_U_DISABLE_LFSR_SHFT                                                       0x2
#define HWIO_GCC_GPLL2_TEST_CTL_U_SKIP_FINE_TUNE_BMSK                                                     0x2
#define HWIO_GCC_GPLL2_TEST_CTL_U_SKIP_FINE_TUNE_SHFT                                                     0x1
#define HWIO_GCC_GPLL2_TEST_CTL_U_SKIP_FAST_LOCK_BMSK                                                     0x1
#define HWIO_GCC_GPLL2_TEST_CTL_U_SKIP_FAST_LOCK_SHFT                                                     0x0

#define HWIO_GCC_GPLL2_TEST_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000202c)
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL2_TEST_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL2_TEST_CTL_U1_ADDR)
#define HWIO_GCC_GPLL2_TEST_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_TEST_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL2_TEST_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_TEST_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL2_TEST_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_TEST_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL2_TEST_CTL_U1_IN)
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL2_TEST_CTL_U1_FLL_COUNT_DISABLE_BMSK                                          0x20000000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_FLL_COUNT_DISABLE_SHFT                                                0x1d
#define HWIO_GCC_GPLL2_TEST_CTL_U1_FLL_COUNT_IN_DIV2_BMSK                                          0x10000000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_FLL_COUNT_IN_DIV2_SHFT                                                0x1c
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL2_TEST_CTL_U1_SILENCE_REF_OUTBUF_BMSK                                           0x400000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_SILENCE_REF_OUTBUF_SHFT                                               0x16
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL2_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_BMSK                                         0x40000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_SHFT                                            0x12
#define HWIO_GCC_GPLL2_TEST_CTL_U1_REF_CLK_SEL_BMSK                                                   0x20000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_REF_CLK_SEL_SHFT                                                      0x11
#define HWIO_GCC_GPLL2_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_BMSK                                     0x10000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_SHFT                                        0x10
#define HWIO_GCC_GPLL2_TEST_CTL_U1_DIS_AMP_STARTUP_BMSK                                                0x8000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_DIS_AMP_STARTUP_SHFT                                                   0xf
#define HWIO_GCC_GPLL2_TEST_CTL_U1_DISABLE_CLAMP_BMSK                                                  0x4000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_DISABLE_CLAMP_SHFT                                                     0xe
#define HWIO_GCC_GPLL2_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_BMSK                                        0x2000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_SHFT                                           0xd
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL2_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_BMSK                                          0x80
#define HWIO_GCC_GPLL2_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_SHFT                                           0x7
#define HWIO_GCC_GPLL2_TEST_CTL_U1_ENABLE_TRAINING_SEQ_BMSK                                              0x40
#define HWIO_GCC_GPLL2_TEST_CTL_U1_ENABLE_TRAINING_SEQ_SHFT                                               0x6
#define HWIO_GCC_GPLL2_TEST_CTL_U1_STATUS_REG_EN_BMSK                                                    0x20
#define HWIO_GCC_GPLL2_TEST_CTL_U1_STATUS_REG_EN_SHFT                                                     0x5
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL2_TEST_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL2_TEST_CTL_U1_CASC_DAC_FCW_MSBS_BMSK                                                 0x3
#define HWIO_GCC_GPLL2_TEST_CTL_U1_CASC_DAC_FCW_MSBS_SHFT                                                 0x0

#define HWIO_GCC_GPLL2_STATUS_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00002030)
#define HWIO_GCC_GPLL2_STATUS_RMSK                                                                 0xffffffff
#define HWIO_GCC_GPLL2_STATUS_IN          \
        in_dword(HWIO_GCC_GPLL2_STATUS_ADDR)
#define HWIO_GCC_GPLL2_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_STATUS_ADDR, m)
#define HWIO_GCC_GPLL2_STATUS_STATUS_31_0_BMSK                                                     0xffffffff
#define HWIO_GCC_GPLL2_STATUS_STATUS_31_0_SHFT                                                            0x0

#define HWIO_GCC_GPLL2_FREQ_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00002034)
#define HWIO_GCC_GPLL2_FREQ_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL2_FREQ_CTL_IN          \
        in_dword(HWIO_GCC_GPLL2_FREQ_CTL_ADDR)
#define HWIO_GCC_GPLL2_FREQ_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_FREQ_CTL_ADDR, m)
#define HWIO_GCC_GPLL2_FREQ_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_FREQ_CTL_ADDR,v)
#define HWIO_GCC_GPLL2_FREQ_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_FREQ_CTL_ADDR,m,v,HWIO_GCC_GPLL2_FREQ_CTL_IN)
#define HWIO_GCC_GPLL2_FREQ_CTL_FREQUENCY_CTL_WORD_BMSK                                            0xffffffff
#define HWIO_GCC_GPLL2_FREQ_CTL_FREQUENCY_CTL_WORD_SHFT                                                   0x0

#define HWIO_GCC_GPLL2_OPMODE_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00002038)
#define HWIO_GCC_GPLL2_OPMODE_RMSK                                                                        0x7
#define HWIO_GCC_GPLL2_OPMODE_IN          \
        in_dword(HWIO_GCC_GPLL2_OPMODE_ADDR)
#define HWIO_GCC_GPLL2_OPMODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_OPMODE_ADDR, m)
#define HWIO_GCC_GPLL2_OPMODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_OPMODE_ADDR,v)
#define HWIO_GCC_GPLL2_OPMODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_OPMODE_ADDR,m,v,HWIO_GCC_GPLL2_OPMODE_IN)
#define HWIO_GCC_GPLL2_OPMODE_PLL_OPMODE_BMSK                                                             0x7
#define HWIO_GCC_GPLL2_OPMODE_PLL_OPMODE_SHFT                                                             0x0

#define HWIO_GCC_GPLL2_STATE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0000203c)
#define HWIO_GCC_GPLL2_STATE_RMSK                                                                         0x7
#define HWIO_GCC_GPLL2_STATE_IN          \
        in_dword(HWIO_GCC_GPLL2_STATE_ADDR)
#define HWIO_GCC_GPLL2_STATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_STATE_ADDR, m)
#define HWIO_GCC_GPLL2_STATE_PLL_STATE_BMSK                                                               0x7
#define HWIO_GCC_GPLL2_STATE_PLL_STATE_SHFT                                                               0x0

#define HWIO_GCC_GPLL2_ALPHA_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00002040)
#define HWIO_GCC_GPLL2_ALPHA_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL2_ALPHA_VAL_IN          \
        in_dword(HWIO_GCC_GPLL2_ALPHA_VAL_ADDR)
#define HWIO_GCC_GPLL2_ALPHA_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_ALPHA_VAL_ADDR, m)
#define HWIO_GCC_GPLL2_ALPHA_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_ALPHA_VAL_ADDR,v)
#define HWIO_GCC_GPLL2_ALPHA_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_ALPHA_VAL_ADDR,m,v,HWIO_GCC_GPLL2_ALPHA_VAL_IN)
#define HWIO_GCC_GPLL2_ALPHA_VAL_PLL_ALPHA_VAL_BMSK                                                    0xffff
#define HWIO_GCC_GPLL2_ALPHA_VAL_PLL_ALPHA_VAL_SHFT                                                       0x0

#define HWIO_GCC_GPLL2_SPARE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00002044)
#define HWIO_GCC_GPLL2_SPARE_RMSK                                                                        0xff
#define HWIO_GCC_GPLL2_SPARE_IN          \
        in_dword(HWIO_GCC_GPLL2_SPARE_ADDR)
#define HWIO_GCC_GPLL2_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_SPARE_ADDR, m)
#define HWIO_GCC_GPLL2_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_SPARE_ADDR,v)
#define HWIO_GCC_GPLL2_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_SPARE_ADDR,m,v,HWIO_GCC_GPLL2_SPARE_IN)
#define HWIO_GCC_GPLL2_SPARE_SPARE_OUTPUTS_BMSK                                                          0xf0
#define HWIO_GCC_GPLL2_SPARE_SPARE_OUTPUTS_SHFT                                                           0x4
#define HWIO_GCC_GPLL2_SPARE_SPARE_INPUTS_BMSK                                                            0xf
#define HWIO_GCC_GPLL2_SPARE_SPARE_INPUTS_SHFT                                                            0x0

#define HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00002048)
#define HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_RMSK                                                              0xff
#define HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_IN          \
        in_dword(HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_ADDR)
#define HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_ADDR, m)
#define HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_ADDR,v)
#define HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_ADDR,m,v,HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_IN)
#define HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_BMSK                                              0xff
#define HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_SHFT                                               0x0

#define HWIO_GCC_GPLL2_SSC_NUM_STEPS_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000204c)
#define HWIO_GCC_GPLL2_SSC_NUM_STEPS_RMSK                                                                 0xf
#define HWIO_GCC_GPLL2_SSC_NUM_STEPS_IN          \
        in_dword(HWIO_GCC_GPLL2_SSC_NUM_STEPS_ADDR)
#define HWIO_GCC_GPLL2_SSC_NUM_STEPS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_SSC_NUM_STEPS_ADDR, m)
#define HWIO_GCC_GPLL2_SSC_NUM_STEPS_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_SSC_NUM_STEPS_ADDR,v)
#define HWIO_GCC_GPLL2_SSC_NUM_STEPS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_SSC_NUM_STEPS_ADDR,m,v,HWIO_GCC_GPLL2_SSC_NUM_STEPS_IN)
#define HWIO_GCC_GPLL2_SSC_NUM_STEPS_SSC_NUM_STEPS_BMSK                                                   0xf
#define HWIO_GCC_GPLL2_SSC_NUM_STEPS_SSC_NUM_STEPS_SHFT                                                   0x0

#define HWIO_GCC_GPLL2_SSC_UPDATE_RATE_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00002050)
#define HWIO_GCC_GPLL2_SSC_UPDATE_RATE_RMSK                                                               0xf
#define HWIO_GCC_GPLL2_SSC_UPDATE_RATE_IN          \
        in_dword(HWIO_GCC_GPLL2_SSC_UPDATE_RATE_ADDR)
#define HWIO_GCC_GPLL2_SSC_UPDATE_RATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL2_SSC_UPDATE_RATE_ADDR, m)
#define HWIO_GCC_GPLL2_SSC_UPDATE_RATE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL2_SSC_UPDATE_RATE_ADDR,v)
#define HWIO_GCC_GPLL2_SSC_UPDATE_RATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL2_SSC_UPDATE_RATE_ADDR,m,v,HWIO_GCC_GPLL2_SSC_UPDATE_RATE_IN)
#define HWIO_GCC_GPLL2_SSC_UPDATE_RATE_SSC_UPDATE_RATE_BMSK                                               0xf
#define HWIO_GCC_GPLL2_SSC_UPDATE_RATE_SSC_UPDATE_RATE_SHFT                                               0x0

#define HWIO_GCC_GPLL3_MODE_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00003000)
#define HWIO_GCC_GPLL3_MODE_RMSK                                                                   0xffffffff
#define HWIO_GCC_GPLL3_MODE_IN          \
        in_dword(HWIO_GCC_GPLL3_MODE_ADDR)
#define HWIO_GCC_GPLL3_MODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_MODE_ADDR, m)
#define HWIO_GCC_GPLL3_MODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_MODE_ADDR,v)
#define HWIO_GCC_GPLL3_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_MODE_ADDR,m,v,HWIO_GCC_GPLL3_MODE_IN)
#define HWIO_GCC_GPLL3_MODE_PLL_LOCK_DET_BMSK                                                      0x80000000
#define HWIO_GCC_GPLL3_MODE_PLL_LOCK_DET_SHFT                                                            0x1f
#define HWIO_GCC_GPLL3_MODE_PLL_ACTIVE_FLAG_BMSK                                                   0x40000000
#define HWIO_GCC_GPLL3_MODE_PLL_ACTIVE_FLAG_SHFT                                                         0x1e
#define HWIO_GCC_GPLL3_MODE_PLL_ACK_LATCH_BMSK                                                     0x20000000
#define HWIO_GCC_GPLL3_MODE_PLL_ACK_LATCH_SHFT                                                           0x1d
#define HWIO_GCC_GPLL3_MODE_PLL_LOCK_DET_FINE_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL3_MODE_PLL_LOCK_DET_FINE_SHFT                                                       0x1c
#define HWIO_GCC_GPLL3_MODE_PCAL_DONE_BMSK                                                          0x8000000
#define HWIO_GCC_GPLL3_MODE_PCAL_DONE_SHFT                                                               0x1b
#define HWIO_GCC_GPLL3_MODE_RESERVE_BITS26_25_BMSK                                                  0x6000000
#define HWIO_GCC_GPLL3_MODE_RESERVE_BITS26_25_SHFT                                                       0x19
#define HWIO_GCC_GPLL3_MODE_FSM_LEGACY_MODE_BMSK                                                    0x1000000
#define HWIO_GCC_GPLL3_MODE_FSM_LEGACY_MODE_SHFT                                                         0x18
#define HWIO_GCC_GPLL3_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_BMSK                                          0x800000
#define HWIO_GCC_GPLL3_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_SHFT                                              0x17
#define HWIO_GCC_GPLL3_MODE_PLL_UPDATE_BMSK                                                          0x400000
#define HWIO_GCC_GPLL3_MODE_PLL_UPDATE_SHFT                                                              0x16
#define HWIO_GCC_GPLL3_MODE_PLL_VOTE_FSM_RESET_BMSK                                                  0x200000
#define HWIO_GCC_GPLL3_MODE_PLL_VOTE_FSM_RESET_SHFT                                                      0x15
#define HWIO_GCC_GPLL3_MODE_PLL_VOTE_FSM_ENA_BMSK                                                    0x100000
#define HWIO_GCC_GPLL3_MODE_PLL_VOTE_FSM_ENA_SHFT                                                        0x14
#define HWIO_GCC_GPLL3_MODE_PLL_BIAS_COUNT_BMSK                                                       0xfc000
#define HWIO_GCC_GPLL3_MODE_PLL_BIAS_COUNT_SHFT                                                           0xe
#define HWIO_GCC_GPLL3_MODE_PLL_LOCK_COUNT_BMSK                                                        0x3f00
#define HWIO_GCC_GPLL3_MODE_PLL_LOCK_COUNT_SHFT                                                           0x8
#define HWIO_GCC_GPLL3_MODE_RESERVE_BIT7_BMSK                                                            0x80
#define HWIO_GCC_GPLL3_MODE_RESERVE_BIT7_SHFT                                                             0x7
#define HWIO_GCC_GPLL3_MODE_OUT_TEST_HW_CTL_BMSK                                                         0x40
#define HWIO_GCC_GPLL3_MODE_OUT_TEST_HW_CTL_SHFT                                                          0x6
#define HWIO_GCC_GPLL3_MODE_OUT_ODD_HW_CTL_BMSK                                                          0x20
#define HWIO_GCC_GPLL3_MODE_OUT_ODD_HW_CTL_SHFT                                                           0x5
#define HWIO_GCC_GPLL3_MODE_OUT_EVEN_HW_CTL_BMSK                                                         0x10
#define HWIO_GCC_GPLL3_MODE_OUT_EVEN_HW_CTL_SHFT                                                          0x4
#define HWIO_GCC_GPLL3_MODE_OUT_MAIN_HW_CTL_BMSK                                                          0x8
#define HWIO_GCC_GPLL3_MODE_OUT_MAIN_HW_CTL_SHFT                                                          0x3
#define HWIO_GCC_GPLL3_MODE_PLL_RESET_N_BMSK                                                              0x4
#define HWIO_GCC_GPLL3_MODE_PLL_RESET_N_SHFT                                                              0x2
#define HWIO_GCC_GPLL3_MODE_RESERVE_BIT1_BMSK                                                             0x2
#define HWIO_GCC_GPLL3_MODE_RESERVE_BIT1_SHFT                                                             0x1
#define HWIO_GCC_GPLL3_MODE_PLL_OUTCTRL_BMSK                                                              0x1
#define HWIO_GCC_GPLL3_MODE_PLL_OUTCTRL_SHFT                                                              0x0

#define HWIO_GCC_GPLL3_L_VAL_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00003004)
#define HWIO_GCC_GPLL3_L_VAL_RMSK                                                                      0xffff
#define HWIO_GCC_GPLL3_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL3_L_VAL_ADDR)
#define HWIO_GCC_GPLL3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_L_VAL_ADDR,m,v,HWIO_GCC_GPLL3_L_VAL_IN)
#define HWIO_GCC_GPLL3_L_VAL_PLL_L_BMSK                                                                0xffff
#define HWIO_GCC_GPLL3_L_VAL_PLL_L_SHFT                                                                   0x0

#define HWIO_GCC_GPLL3_CAL_L_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00003008)
#define HWIO_GCC_GPLL3_CAL_L_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL3_CAL_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL3_CAL_L_VAL_ADDR)
#define HWIO_GCC_GPLL3_CAL_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_CAL_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL3_CAL_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_CAL_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL3_CAL_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_CAL_L_VAL_ADDR,m,v,HWIO_GCC_GPLL3_CAL_L_VAL_IN)
#define HWIO_GCC_GPLL3_CAL_L_VAL_PLL_CAL_L_BMSK                                                        0xffff
#define HWIO_GCC_GPLL3_CAL_L_VAL_PLL_CAL_L_SHFT                                                           0x0

#define HWIO_GCC_GPLL3_USER_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0000300c)
#define HWIO_GCC_GPLL3_USER_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL3_USER_CTL_IN          \
        in_dword(HWIO_GCC_GPLL3_USER_CTL_ADDR)
#define HWIO_GCC_GPLL3_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_USER_CTL_ADDR, m)
#define HWIO_GCC_GPLL3_USER_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_USER_CTL_ADDR,v)
#define HWIO_GCC_GPLL3_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_USER_CTL_ADDR,m,v,HWIO_GCC_GPLL3_USER_CTL_IN)
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT31_BMSK                                                 0x80000000
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT31_SHFT                                                       0x1f
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT30_BMSK                                                 0x40000000
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT30_SHFT                                                       0x1e
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT29_BMSK                                                 0x20000000
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT29_SHFT                                                       0x1d
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT28_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT28_SHFT                                                       0x1c
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT27_BMSK                                                  0x8000000
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT27_SHFT                                                       0x1b
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT26_BMSK                                                  0x4000000
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT26_SHFT                                                       0x1a
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT25_BMSK                                                  0x2000000
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT25_SHFT                                                       0x19
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT24_BMSK                                                  0x1000000
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT24_SHFT                                                       0x18
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT23_BMSK                                                   0x800000
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT23_SHFT                                                       0x17
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT22_BMSK                                                   0x400000
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT22_SHFT                                                       0x16
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT21_BMSK                                                   0x200000
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT21_SHFT                                                       0x15
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT20_BMSK                                                   0x100000
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT20_SHFT                                                       0x14
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL3_USER_CTL_PRE_DIV_RATIO_BMSK                                                    0x70000
#define HWIO_GCC_GPLL3_USER_CTL_PRE_DIV_RATIO_SHFT                                                       0x10
#define HWIO_GCC_GPLL3_USER_CTL_POST_DIV_RATIO_ODD_BMSK                                                0xf000
#define HWIO_GCC_GPLL3_USER_CTL_POST_DIV_RATIO_ODD_SHFT                                                   0xc
#define HWIO_GCC_GPLL3_USER_CTL_POST_DIV_RATIO_EVEN_BMSK                                                0xf00
#define HWIO_GCC_GPLL3_USER_CTL_POST_DIV_RATIO_EVEN_SHFT                                                  0x8
#define HWIO_GCC_GPLL3_USER_CTL_OUT_CLK_POLARITY_BMSK                                                    0x80
#define HWIO_GCC_GPLL3_USER_CTL_OUT_CLK_POLARITY_SHFT                                                     0x7
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT6_BMSK                                                        0x40
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT6_SHFT                                                         0x6
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT5_BMSK                                                        0x20
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT5_SHFT                                                         0x5
#define HWIO_GCC_GPLL3_USER_CTL_PLLOUT_TEST_BMSK                                                         0x10
#define HWIO_GCC_GPLL3_USER_CTL_PLLOUT_TEST_SHFT                                                          0x4
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT3_BMSK                                                         0x8
#define HWIO_GCC_GPLL3_USER_CTL_RESERVE_BIT3_SHFT                                                         0x3
#define HWIO_GCC_GPLL3_USER_CTL_PLLOUT_ODD_BMSK                                                           0x4
#define HWIO_GCC_GPLL3_USER_CTL_PLLOUT_ODD_SHFT                                                           0x2
#define HWIO_GCC_GPLL3_USER_CTL_PLLOUT_EVEN_BMSK                                                          0x2
#define HWIO_GCC_GPLL3_USER_CTL_PLLOUT_EVEN_SHFT                                                          0x1
#define HWIO_GCC_GPLL3_USER_CTL_PLLOUT_MAIN_BMSK                                                          0x1
#define HWIO_GCC_GPLL3_USER_CTL_PLLOUT_MAIN_SHFT                                                          0x0

#define HWIO_GCC_GPLL3_USER_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00003010)
#define HWIO_GCC_GPLL3_USER_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL3_USER_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL3_USER_CTL_U_ADDR)
#define HWIO_GCC_GPLL3_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_USER_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL3_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_USER_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL3_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_USER_CTL_U_ADDR,m,v,HWIO_GCC_GPLL3_USER_CTL_U_IN)
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT63_BMSK                                               0x80000000
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT63_SHFT                                                     0x1f
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT62_BMSK                                               0x40000000
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT62_SHFT                                                     0x1e
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT61_BMSK                                               0x20000000
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT61_SHFT                                                     0x1d
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT60_BMSK                                               0x10000000
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT60_SHFT                                                     0x1c
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT59_BMSK                                                0x8000000
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT59_SHFT                                                     0x1b
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT58_BMSK                                                0x4000000
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT58_SHFT                                                     0x1a
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT57_BMSK                                                0x2000000
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT57_SHFT                                                     0x19
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT56_BMSK                                                0x1000000
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT56_SHFT                                                     0x18
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT55_BMSK                                                 0x800000
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT55_SHFT                                                     0x17
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT54_BMSK                                                 0x400000
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT54_SHFT                                                     0x16
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT53_BMSK                                                 0x200000
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT53_SHFT                                                     0x15
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT52_BMSK                                                 0x100000
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT52_SHFT                                                     0x14
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT51_BMSK                                                  0x80000
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT51_SHFT                                                     0x13
#define HWIO_GCC_GPLL3_USER_CTL_U_LOCK_DETECTOR_SELECTION_BMSK                                        0x40000
#define HWIO_GCC_GPLL3_USER_CTL_U_LOCK_DETECTOR_SELECTION_SHFT                                           0x12
#define HWIO_GCC_GPLL3_USER_CTL_U_TYPE_2_MODE_SELECTION_BMSK                                          0x20000
#define HWIO_GCC_GPLL3_USER_CTL_U_TYPE_2_MODE_SELECTION_SHFT                                             0x11
#define HWIO_GCC_GPLL3_USER_CTL_U_BANG_BANG_MODE_SELECTION_BMSK                                       0x10000
#define HWIO_GCC_GPLL3_USER_CTL_U_BANG_BANG_MODE_SELECTION_SHFT                                          0x10
#define HWIO_GCC_GPLL3_USER_CTL_U_FRAC_FORMAT_SEL_BMSK                                                 0x8000
#define HWIO_GCC_GPLL3_USER_CTL_U_FRAC_FORMAT_SEL_SHFT                                                    0xf
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT46_BMSK                                                   0x4000
#define HWIO_GCC_GPLL3_USER_CTL_U_RESERVE_BIT46_SHFT                                                      0xe
#define HWIO_GCC_GPLL3_USER_CTL_U_REF_CLK_AT_OUT_BMSK                                                  0x2000
#define HWIO_GCC_GPLL3_USER_CTL_U_REF_CLK_AT_OUT_SHFT                                                     0xd
#define HWIO_GCC_GPLL3_USER_CTL_U_SCALE_FREQ_ON_RESTART_BMSK                                           0x1800
#define HWIO_GCC_GPLL3_USER_CTL_U_SCALE_FREQ_ON_RESTART_SHFT                                              0xb
#define HWIO_GCC_GPLL3_USER_CTL_U_LATCH_INTERFACE_BYPASS_BMSK                                           0x400
#define HWIO_GCC_GPLL3_USER_CTL_U_LATCH_INTERFACE_BYPASS_SHFT                                             0xa
#define HWIO_GCC_GPLL3_USER_CTL_U_STATUS_REGISTER_BMSK                                                  0x3e0
#define HWIO_GCC_GPLL3_USER_CTL_U_STATUS_REGISTER_SHFT                                                    0x5
#define HWIO_GCC_GPLL3_USER_CTL_U_WRITE_STATE_EN_BMSK                                                    0x10
#define HWIO_GCC_GPLL3_USER_CTL_U_WRITE_STATE_EN_SHFT                                                     0x4
#define HWIO_GCC_GPLL3_USER_CTL_U_CALIB_CTRL_BMSK                                                         0xe
#define HWIO_GCC_GPLL3_USER_CTL_U_CALIB_CTRL_SHFT                                                         0x1
#define HWIO_GCC_GPLL3_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_BMSK                                             0x1
#define HWIO_GCC_GPLL3_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_SHFT                                             0x0

#define HWIO_GCC_GPLL3_USER_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00003014)
#define HWIO_GCC_GPLL3_USER_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL3_USER_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL3_USER_CTL_U1_ADDR)
#define HWIO_GCC_GPLL3_USER_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_USER_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL3_USER_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_USER_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL3_USER_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_USER_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL3_USER_CTL_U1_IN)
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT93_BMSK                                              0x20000000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT93_SHFT                                                    0x1d
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT92_BMSK                                              0x10000000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT92_SHFT                                                    0x1c
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT86_BMSK                                                0x400000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT86_SHFT                                                    0x16
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT82_BMSK                                                 0x40000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT82_SHFT                                                    0x12
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT81_BMSK                                                 0x20000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT81_SHFT                                                    0x11
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT80_BMSK                                                 0x10000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT80_SHFT                                                    0x10
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT79_BMSK                                                  0x8000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT79_SHFT                                                     0xf
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT78_BMSK                                                  0x4000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT78_SHFT                                                     0xe
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT77_BMSK                                                  0x2000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT77_SHFT                                                     0xd
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT71_BMSK                                                    0x80
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT71_SHFT                                                     0x7
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT70_BMSK                                                    0x40
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT70_SHFT                                                     0x6
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT69_BMSK                                                    0x20
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT69_SHFT                                                     0x5
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT65_BMSK                                                     0x2
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT65_SHFT                                                     0x1
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT64_BMSK                                                     0x1
#define HWIO_GCC_GPLL3_USER_CTL_U1_RESERVE_BIT64_SHFT                                                     0x0

#define HWIO_GCC_GPLL3_CONFIG_CTL_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00003018)
#define HWIO_GCC_GPLL3_CONFIG_CTL_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL3_CONFIG_CTL_IN          \
        in_dword(HWIO_GCC_GPLL3_CONFIG_CTL_ADDR)
#define HWIO_GCC_GPLL3_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_CONFIG_CTL_ADDR, m)
#define HWIO_GCC_GPLL3_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_CONFIG_CTL_ADDR,v)
#define HWIO_GCC_GPLL3_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_CONFIG_CTL_ADDR,m,v,HWIO_GCC_GPLL3_CONFIG_CTL_IN)
#define HWIO_GCC_GPLL3_CONFIG_CTL_FINE_LDC_THRESHOLD_BMSK                                          0xfc000000
#define HWIO_GCC_GPLL3_CONFIG_CTL_FINE_LDC_THRESHOLD_SHFT                                                0x1a
#define HWIO_GCC_GPLL3_CONFIG_CTL_COARSE_LDC_THRESHOLD_BMSK                                         0x3c00000
#define HWIO_GCC_GPLL3_CONFIG_CTL_COARSE_LDC_THRESHOLD_SHFT                                              0x16
#define HWIO_GCC_GPLL3_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_BMSK                                 0x3c0000
#define HWIO_GCC_GPLL3_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_SHFT                                     0x12
#define HWIO_GCC_GPLL3_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_BMSK                                  0x3c000
#define HWIO_GCC_GPLL3_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_SHFT                                      0xe
#define HWIO_GCC_GPLL3_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_BMSK                                         0x3800
#define HWIO_GCC_GPLL3_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_SHFT                                            0xb
#define HWIO_GCC_GPLL3_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_BMSK                                        0x700
#define HWIO_GCC_GPLL3_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_SHFT                                          0x8
#define HWIO_GCC_GPLL3_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_BMSK                                              0xf0
#define HWIO_GCC_GPLL3_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_SHFT                                               0x4
#define HWIO_GCC_GPLL3_CONFIG_CTL_FWD_GAIN_KFN_BMSK                                                       0xf
#define HWIO_GCC_GPLL3_CONFIG_CTL_FWD_GAIN_KFN_SHFT                                                       0x0

#define HWIO_GCC_GPLL3_CONFIG_CTL_U_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000301c)
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_RMSK                                                           0xffffffff
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL3_CONFIG_CTL_U_ADDR)
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_CONFIG_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_CONFIG_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_CONFIG_CTL_U_ADDR,m,v,HWIO_GCC_GPLL3_CONFIG_CTL_U_IN)
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_BIST_CFG_BMSK                                                  0xffff0000
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_BIST_CFG_SHFT                                                        0x10
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_BMSK                                       0xc000
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_SHFT                                          0xe
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_OSC_SETTLING_TIME_BMSK                                             0x3000
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_OSC_SETTLING_TIME_SHFT                                                0xc
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_BMSK                                            0xc00
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_SHFT                                              0xa
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_CASC_CURRENT_CTL_B_BMSK                                             0x380
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_CASC_CURRENT_CTL_B_SHFT                                               0x7
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_BMSK                                     0x40
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_SHFT                                      0x6
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_BMSK                                            0x30
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_SHFT                                             0x4
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_LDET_THRESH_SCALE_BMSK                                                0x8
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_LDET_THRESH_SCALE_SHFT                                                0x3
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_DCO_STARTUP_CONFIG_BMSK                                               0x6
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_DCO_STARTUP_CONFIG_SHFT                                               0x1
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_BMSK                                          0x1
#define HWIO_GCC_GPLL3_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_SHFT                                          0x0

#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00003020)
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_RMSK                                                          0xffffffff
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL3_CONFIG_CTL_U1_ADDR)
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_CONFIG_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_CONFIG_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_CONFIG_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL3_CONFIG_CTL_U1_IN)
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BB_CAL_THRESHOLD_BMSK                                         0xc0000000
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BB_CAL_THRESHOLD_SHFT                                               0x1e
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_PCODE_OFFSET_BMSK                                             0x38000000
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_PCODE_OFFSET_SHFT                                                   0x1b
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_COUNTER_BLANK_BMSK                                             0x4000000
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_COUNTER_BLANK_SHFT                                                  0x1a
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BB_RESYNC_EDGE_BMSK                                            0x2000000
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BB_RESYNC_EDGE_SHFT                                                 0x19
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BB_RESYNC_SEL_BMSK                                             0x1000000
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BB_RESYNC_SEL_SHFT                                                  0x18
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_BMSK                                        0xc00000
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_SHFT                                            0x16
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BB_LOCK_THRESH_BMSK                                             0x380000
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BB_LOCK_THRESH_SHFT                                                 0x13
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_RESERVE_BIT82_BMSK                                               0x40000
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_RESERVE_BIT82_SHFT                                                  0x12
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_BMSK                                          0x30000
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_SHFT                                             0x10
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_BMSK                                            0xc000
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_SHFT                                               0xe
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BB_CAL_EN_BMSK                                                    0x2000
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BB_CAL_EN_SHFT                                                       0xd
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_BMSK                                      0x1800
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_SHFT                                         0xb
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BBMODE_INT_GAIN_BMSK                                               0x780
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BBMODE_INT_GAIN_SHFT                                                 0x7
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BBMODE_PROP_GAIN_BMSK                                               0x78
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_BBMODE_PROP_GAIN_SHFT                                                0x3
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_TDC_SELECTION_BMSK                                                   0x4
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_TDC_SELECTION_SHFT                                                   0x2
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_RESERVE_BIT65_BMSK                                                   0x2
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_RESERVE_BIT65_SHFT                                                   0x1
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_FORCE_DSM_ON_BMSK                                                    0x1
#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_FORCE_DSM_ON_SHFT                                                    0x0

#define HWIO_GCC_GPLL3_TEST_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00003024)
#define HWIO_GCC_GPLL3_TEST_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL3_TEST_CTL_IN          \
        in_dword(HWIO_GCC_GPLL3_TEST_CTL_ADDR)
#define HWIO_GCC_GPLL3_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_TEST_CTL_ADDR, m)
#define HWIO_GCC_GPLL3_TEST_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_TEST_CTL_ADDR,v)
#define HWIO_GCC_GPLL3_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_TEST_CTL_ADDR,m,v,HWIO_GCC_GPLL3_TEST_CTL_IN)
#define HWIO_GCC_GPLL3_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_BMSK                                       0xc0000000
#define HWIO_GCC_GPLL3_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_SHFT                                             0x1e
#define HWIO_GCC_GPLL3_TEST_CTL_BYPASS_FIRST_ORDER_DSM_BMSK                                        0x20000000
#define HWIO_GCC_GPLL3_TEST_CTL_BYPASS_FIRST_ORDER_DSM_SHFT                                              0x1d
#define HWIO_GCC_GPLL3_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_BMSK                                   0x18000000
#define HWIO_GCC_GPLL3_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_SHFT                                         0x1b
#define HWIO_GCC_GPLL3_TEST_CTL_GLITCH_PREVENTION_DIS_BMSK                                          0x4000000
#define HWIO_GCC_GPLL3_TEST_CTL_GLITCH_PREVENTION_DIS_SHFT                                               0x1a
#define HWIO_GCC_GPLL3_TEST_CTL_ATEST_ISCALE_BMSK                                                   0x3000000
#define HWIO_GCC_GPLL3_TEST_CTL_ATEST_ISCALE_SHFT                                                        0x18
#define HWIO_GCC_GPLL3_TEST_CTL_PLL_TEST_OUT_SEL_BMSK                                                0xf00000
#define HWIO_GCC_GPLL3_TEST_CTL_PLL_TEST_OUT_SEL_SHFT                                                    0x14
#define HWIO_GCC_GPLL3_TEST_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL3_TEST_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL3_TEST_CTL_DIV2_NMO_EN_BMSK                                                      0x40000
#define HWIO_GCC_GPLL3_TEST_CTL_DIV2_NMO_EN_SHFT                                                         0x12
#define HWIO_GCC_GPLL3_TEST_CTL_NMO_OSC_SEL_BMSK                                                      0x30000
#define HWIO_GCC_GPLL3_TEST_CTL_NMO_OSC_SEL_SHFT                                                         0x10
#define HWIO_GCC_GPLL3_TEST_CTL_NOISE_MAG_BMSK                                                         0xe000
#define HWIO_GCC_GPLL3_TEST_CTL_NOISE_MAG_SHFT                                                            0xd
#define HWIO_GCC_GPLL3_TEST_CTL_NOISE_GEN_EN_BMSK                                                      0x1000
#define HWIO_GCC_GPLL3_TEST_CTL_NOISE_GEN_EN_SHFT                                                         0xc
#define HWIO_GCC_GPLL3_TEST_CTL_DISABLE_DCAPS_BMSK                                                      0x800
#define HWIO_GCC_GPLL3_TEST_CTL_DISABLE_DCAPS_SHFT                                                        0xb
#define HWIO_GCC_GPLL3_TEST_CTL_RESERVE_BIT10_BMSK                                                      0x400
#define HWIO_GCC_GPLL3_TEST_CTL_RESERVE_BIT10_SHFT                                                        0xa
#define HWIO_GCC_GPLL3_TEST_CTL_RESERVE_BIT9_BMSK                                                       0x200
#define HWIO_GCC_GPLL3_TEST_CTL_RESERVE_BIT9_SHFT                                                         0x9
#define HWIO_GCC_GPLL3_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_BMSK                                            0x100
#define HWIO_GCC_GPLL3_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_SHFT                                              0x8
#define HWIO_GCC_GPLL3_TEST_CTL_EN_VDD_TEST_BMSK                                                         0x80
#define HWIO_GCC_GPLL3_TEST_CTL_EN_VDD_TEST_SHFT                                                          0x7
#define HWIO_GCC_GPLL3_TEST_CTL_EN_VREG_TEST_BMSK                                                        0x40
#define HWIO_GCC_GPLL3_TEST_CTL_EN_VREG_TEST_SHFT                                                         0x6
#define HWIO_GCC_GPLL3_TEST_CTL_EN_VREF_TEST_BMSK                                                        0x20
#define HWIO_GCC_GPLL3_TEST_CTL_EN_VREF_TEST_SHFT                                                         0x5
#define HWIO_GCC_GPLL3_TEST_CTL_EN_VDCO_TEST_BMSK                                                        0x10
#define HWIO_GCC_GPLL3_TEST_CTL_EN_VDCO_TEST_SHFT                                                         0x4
#define HWIO_GCC_GPLL3_TEST_CTL_BYPASS_ATEST_BUFFER_BMSK                                                  0x8
#define HWIO_GCC_GPLL3_TEST_CTL_BYPASS_ATEST_BUFFER_SHFT                                                  0x3
#define HWIO_GCC_GPLL3_TEST_CTL_EN_IVCO_TEST_BMSK                                                         0x4
#define HWIO_GCC_GPLL3_TEST_CTL_EN_IVCO_TEST_SHFT                                                         0x2
#define HWIO_GCC_GPLL3_TEST_CTL_ATEST1_EN_BMSK                                                            0x2
#define HWIO_GCC_GPLL3_TEST_CTL_ATEST1_EN_SHFT                                                            0x1
#define HWIO_GCC_GPLL3_TEST_CTL_ATEST0_EN_BMSK                                                            0x1
#define HWIO_GCC_GPLL3_TEST_CTL_ATEST0_EN_SHFT                                                            0x0

#define HWIO_GCC_GPLL3_TEST_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00003028)
#define HWIO_GCC_GPLL3_TEST_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL3_TEST_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL3_TEST_CTL_U_ADDR)
#define HWIO_GCC_GPLL3_TEST_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_TEST_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL3_TEST_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_TEST_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL3_TEST_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_TEST_CTL_U_ADDR,m,v,HWIO_GCC_GPLL3_TEST_CTL_U_IN)
#define HWIO_GCC_GPLL3_TEST_CTL_U_CASC_DAC_FCW_LSBS_BMSK                                           0xe0000000
#define HWIO_GCC_GPLL3_TEST_CTL_U_CASC_DAC_FCW_LSBS_SHFT                                                 0x1d
#define HWIO_GCC_GPLL3_TEST_CTL_U_OVERRIDE_CASC_DAC_BMSK                                           0x10000000
#define HWIO_GCC_GPLL3_TEST_CTL_U_OVERRIDE_CASC_DAC_SHFT                                                 0x1c
#define HWIO_GCC_GPLL3_TEST_CTL_U_COMP_COARSE_FCW_BMSK                                              0xe000000
#define HWIO_GCC_GPLL3_TEST_CTL_U_COMP_COARSE_FCW_SHFT                                                   0x19
#define HWIO_GCC_GPLL3_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_BMSK                                     0x1800000
#define HWIO_GCC_GPLL3_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_SHFT                                          0x17
#define HWIO_GCC_GPLL3_TEST_CTL_U_FINE_FCW_BMSK                                                      0x7e0000
#define HWIO_GCC_GPLL3_TEST_CTL_U_FINE_FCW_SHFT                                                          0x11
#define HWIO_GCC_GPLL3_TEST_CTL_U_OVERRIDE_FINE_FCW_BMSK                                              0x10000
#define HWIO_GCC_GPLL3_TEST_CTL_U_OVERRIDE_FINE_FCW_SHFT                                                 0x10
#define HWIO_GCC_GPLL3_TEST_CTL_U_REG_COARSE_FCW_BMSK                                                  0xfe00
#define HWIO_GCC_GPLL3_TEST_CTL_U_REG_COARSE_FCW_SHFT                                                     0x9
#define HWIO_GCC_GPLL3_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_BMSK                                          0x100
#define HWIO_GCC_GPLL3_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_SHFT                                            0x8
#define HWIO_GCC_GPLL3_TEST_CTL_U_PROCESS_CALIB_WORD_BMSK                                                0xe0
#define HWIO_GCC_GPLL3_TEST_CTL_U_PROCESS_CALIB_WORD_SHFT                                                 0x5
#define HWIO_GCC_GPLL3_TEST_CTL_U_OVERRIDE_CALIB_WORD_BMSK                                               0x10
#define HWIO_GCC_GPLL3_TEST_CTL_U_OVERRIDE_CALIB_WORD_SHFT                                                0x4
#define HWIO_GCC_GPLL3_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_BMSK                                             0x8
#define HWIO_GCC_GPLL3_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_SHFT                                             0x3
#define HWIO_GCC_GPLL3_TEST_CTL_U_DISABLE_LFSR_BMSK                                                       0x4
#define HWIO_GCC_GPLL3_TEST_CTL_U_DISABLE_LFSR_SHFT                                                       0x2
#define HWIO_GCC_GPLL3_TEST_CTL_U_SKIP_FINE_TUNE_BMSK                                                     0x2
#define HWIO_GCC_GPLL3_TEST_CTL_U_SKIP_FINE_TUNE_SHFT                                                     0x1
#define HWIO_GCC_GPLL3_TEST_CTL_U_SKIP_FAST_LOCK_BMSK                                                     0x1
#define HWIO_GCC_GPLL3_TEST_CTL_U_SKIP_FAST_LOCK_SHFT                                                     0x0

#define HWIO_GCC_GPLL3_TEST_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000302c)
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL3_TEST_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL3_TEST_CTL_U1_ADDR)
#define HWIO_GCC_GPLL3_TEST_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_TEST_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL3_TEST_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_TEST_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL3_TEST_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_TEST_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL3_TEST_CTL_U1_IN)
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL3_TEST_CTL_U1_FLL_COUNT_DISABLE_BMSK                                          0x20000000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_FLL_COUNT_DISABLE_SHFT                                                0x1d
#define HWIO_GCC_GPLL3_TEST_CTL_U1_FLL_COUNT_IN_DIV2_BMSK                                          0x10000000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_FLL_COUNT_IN_DIV2_SHFT                                                0x1c
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL3_TEST_CTL_U1_SILENCE_REF_OUTBUF_BMSK                                           0x400000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_SILENCE_REF_OUTBUF_SHFT                                               0x16
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL3_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_BMSK                                         0x40000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_SHFT                                            0x12
#define HWIO_GCC_GPLL3_TEST_CTL_U1_REF_CLK_SEL_BMSK                                                   0x20000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_REF_CLK_SEL_SHFT                                                      0x11
#define HWIO_GCC_GPLL3_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_BMSK                                     0x10000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_SHFT                                        0x10
#define HWIO_GCC_GPLL3_TEST_CTL_U1_DIS_AMP_STARTUP_BMSK                                                0x8000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_DIS_AMP_STARTUP_SHFT                                                   0xf
#define HWIO_GCC_GPLL3_TEST_CTL_U1_DISABLE_CLAMP_BMSK                                                  0x4000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_DISABLE_CLAMP_SHFT                                                     0xe
#define HWIO_GCC_GPLL3_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_BMSK                                        0x2000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_SHFT                                           0xd
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL3_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_BMSK                                          0x80
#define HWIO_GCC_GPLL3_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_SHFT                                           0x7
#define HWIO_GCC_GPLL3_TEST_CTL_U1_ENABLE_TRAINING_SEQ_BMSK                                              0x40
#define HWIO_GCC_GPLL3_TEST_CTL_U1_ENABLE_TRAINING_SEQ_SHFT                                               0x6
#define HWIO_GCC_GPLL3_TEST_CTL_U1_STATUS_REG_EN_BMSK                                                    0x20
#define HWIO_GCC_GPLL3_TEST_CTL_U1_STATUS_REG_EN_SHFT                                                     0x5
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL3_TEST_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL3_TEST_CTL_U1_CASC_DAC_FCW_MSBS_BMSK                                                 0x3
#define HWIO_GCC_GPLL3_TEST_CTL_U1_CASC_DAC_FCW_MSBS_SHFT                                                 0x0

#define HWIO_GCC_GPLL3_STATUS_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00003030)
#define HWIO_GCC_GPLL3_STATUS_RMSK                                                                 0xffffffff
#define HWIO_GCC_GPLL3_STATUS_IN          \
        in_dword(HWIO_GCC_GPLL3_STATUS_ADDR)
#define HWIO_GCC_GPLL3_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_STATUS_ADDR, m)
#define HWIO_GCC_GPLL3_STATUS_STATUS_31_0_BMSK                                                     0xffffffff
#define HWIO_GCC_GPLL3_STATUS_STATUS_31_0_SHFT                                                            0x0

#define HWIO_GCC_GPLL3_FREQ_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00003034)
#define HWIO_GCC_GPLL3_FREQ_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL3_FREQ_CTL_IN          \
        in_dword(HWIO_GCC_GPLL3_FREQ_CTL_ADDR)
#define HWIO_GCC_GPLL3_FREQ_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_FREQ_CTL_ADDR, m)
#define HWIO_GCC_GPLL3_FREQ_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_FREQ_CTL_ADDR,v)
#define HWIO_GCC_GPLL3_FREQ_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_FREQ_CTL_ADDR,m,v,HWIO_GCC_GPLL3_FREQ_CTL_IN)
#define HWIO_GCC_GPLL3_FREQ_CTL_FREQUENCY_CTL_WORD_BMSK                                            0xffffffff
#define HWIO_GCC_GPLL3_FREQ_CTL_FREQUENCY_CTL_WORD_SHFT                                                   0x0

#define HWIO_GCC_GPLL3_OPMODE_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00003038)
#define HWIO_GCC_GPLL3_OPMODE_RMSK                                                                        0x7
#define HWIO_GCC_GPLL3_OPMODE_IN          \
        in_dword(HWIO_GCC_GPLL3_OPMODE_ADDR)
#define HWIO_GCC_GPLL3_OPMODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_OPMODE_ADDR, m)
#define HWIO_GCC_GPLL3_OPMODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_OPMODE_ADDR,v)
#define HWIO_GCC_GPLL3_OPMODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_OPMODE_ADDR,m,v,HWIO_GCC_GPLL3_OPMODE_IN)
#define HWIO_GCC_GPLL3_OPMODE_PLL_OPMODE_BMSK                                                             0x7
#define HWIO_GCC_GPLL3_OPMODE_PLL_OPMODE_SHFT                                                             0x0

#define HWIO_GCC_GPLL3_STATE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0000303c)
#define HWIO_GCC_GPLL3_STATE_RMSK                                                                         0x7
#define HWIO_GCC_GPLL3_STATE_IN          \
        in_dword(HWIO_GCC_GPLL3_STATE_ADDR)
#define HWIO_GCC_GPLL3_STATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_STATE_ADDR, m)
#define HWIO_GCC_GPLL3_STATE_PLL_STATE_BMSK                                                               0x7
#define HWIO_GCC_GPLL3_STATE_PLL_STATE_SHFT                                                               0x0

#define HWIO_GCC_GPLL3_ALPHA_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00003040)
#define HWIO_GCC_GPLL3_ALPHA_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL3_ALPHA_VAL_IN          \
        in_dword(HWIO_GCC_GPLL3_ALPHA_VAL_ADDR)
#define HWIO_GCC_GPLL3_ALPHA_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_ALPHA_VAL_ADDR, m)
#define HWIO_GCC_GPLL3_ALPHA_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_ALPHA_VAL_ADDR,v)
#define HWIO_GCC_GPLL3_ALPHA_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_ALPHA_VAL_ADDR,m,v,HWIO_GCC_GPLL3_ALPHA_VAL_IN)
#define HWIO_GCC_GPLL3_ALPHA_VAL_PLL_ALPHA_VAL_BMSK                                                    0xffff
#define HWIO_GCC_GPLL3_ALPHA_VAL_PLL_ALPHA_VAL_SHFT                                                       0x0

#define HWIO_GCC_GPLL3_SPARE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00003044)
#define HWIO_GCC_GPLL3_SPARE_RMSK                                                                        0xff
#define HWIO_GCC_GPLL3_SPARE_IN          \
        in_dword(HWIO_GCC_GPLL3_SPARE_ADDR)
#define HWIO_GCC_GPLL3_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_SPARE_ADDR, m)
#define HWIO_GCC_GPLL3_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_SPARE_ADDR,v)
#define HWIO_GCC_GPLL3_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_SPARE_ADDR,m,v,HWIO_GCC_GPLL3_SPARE_IN)
#define HWIO_GCC_GPLL3_SPARE_SPARE_OUTPUTS_BMSK                                                          0xf0
#define HWIO_GCC_GPLL3_SPARE_SPARE_OUTPUTS_SHFT                                                           0x4
#define HWIO_GCC_GPLL3_SPARE_SPARE_INPUTS_BMSK                                                            0xf
#define HWIO_GCC_GPLL3_SPARE_SPARE_INPUTS_SHFT                                                            0x0

#define HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00003048)
#define HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_RMSK                                                              0xff
#define HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_IN          \
        in_dword(HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_ADDR)
#define HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_ADDR, m)
#define HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_ADDR,v)
#define HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_ADDR,m,v,HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_IN)
#define HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_BMSK                                              0xff
#define HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_SHFT                                               0x0

#define HWIO_GCC_GPLL3_SSC_NUM_STEPS_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000304c)
#define HWIO_GCC_GPLL3_SSC_NUM_STEPS_RMSK                                                                 0xf
#define HWIO_GCC_GPLL3_SSC_NUM_STEPS_IN          \
        in_dword(HWIO_GCC_GPLL3_SSC_NUM_STEPS_ADDR)
#define HWIO_GCC_GPLL3_SSC_NUM_STEPS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_SSC_NUM_STEPS_ADDR, m)
#define HWIO_GCC_GPLL3_SSC_NUM_STEPS_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_SSC_NUM_STEPS_ADDR,v)
#define HWIO_GCC_GPLL3_SSC_NUM_STEPS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_SSC_NUM_STEPS_ADDR,m,v,HWIO_GCC_GPLL3_SSC_NUM_STEPS_IN)
#define HWIO_GCC_GPLL3_SSC_NUM_STEPS_SSC_NUM_STEPS_BMSK                                                   0xf
#define HWIO_GCC_GPLL3_SSC_NUM_STEPS_SSC_NUM_STEPS_SHFT                                                   0x0

#define HWIO_GCC_GPLL3_SSC_UPDATE_RATE_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00003050)
#define HWIO_GCC_GPLL3_SSC_UPDATE_RATE_RMSK                                                               0xf
#define HWIO_GCC_GPLL3_SSC_UPDATE_RATE_IN          \
        in_dword(HWIO_GCC_GPLL3_SSC_UPDATE_RATE_ADDR)
#define HWIO_GCC_GPLL3_SSC_UPDATE_RATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL3_SSC_UPDATE_RATE_ADDR, m)
#define HWIO_GCC_GPLL3_SSC_UPDATE_RATE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL3_SSC_UPDATE_RATE_ADDR,v)
#define HWIO_GCC_GPLL3_SSC_UPDATE_RATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL3_SSC_UPDATE_RATE_ADDR,m,v,HWIO_GCC_GPLL3_SSC_UPDATE_RATE_IN)
#define HWIO_GCC_GPLL3_SSC_UPDATE_RATE_SSC_UPDATE_RATE_BMSK                                               0xf
#define HWIO_GCC_GPLL3_SSC_UPDATE_RATE_SSC_UPDATE_RATE_SHFT                                               0x0

#define HWIO_GCC_GPLL4_MODE_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00076000)
#define HWIO_GCC_GPLL4_MODE_RMSK                                                                   0xffffffff
#define HWIO_GCC_GPLL4_MODE_IN          \
        in_dword(HWIO_GCC_GPLL4_MODE_ADDR)
#define HWIO_GCC_GPLL4_MODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_MODE_ADDR, m)
#define HWIO_GCC_GPLL4_MODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_MODE_ADDR,v)
#define HWIO_GCC_GPLL4_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_MODE_ADDR,m,v,HWIO_GCC_GPLL4_MODE_IN)
#define HWIO_GCC_GPLL4_MODE_PLL_LOCK_DET_BMSK                                                      0x80000000
#define HWIO_GCC_GPLL4_MODE_PLL_LOCK_DET_SHFT                                                            0x1f
#define HWIO_GCC_GPLL4_MODE_PLL_ACTIVE_FLAG_BMSK                                                   0x40000000
#define HWIO_GCC_GPLL4_MODE_PLL_ACTIVE_FLAG_SHFT                                                         0x1e
#define HWIO_GCC_GPLL4_MODE_PLL_ACK_LATCH_BMSK                                                     0x20000000
#define HWIO_GCC_GPLL4_MODE_PLL_ACK_LATCH_SHFT                                                           0x1d
#define HWIO_GCC_GPLL4_MODE_PLL_LOCK_DET_FINE_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL4_MODE_PLL_LOCK_DET_FINE_SHFT                                                       0x1c
#define HWIO_GCC_GPLL4_MODE_PCAL_DONE_BMSK                                                          0x8000000
#define HWIO_GCC_GPLL4_MODE_PCAL_DONE_SHFT                                                               0x1b
#define HWIO_GCC_GPLL4_MODE_RESERVE_BITS26_25_BMSK                                                  0x6000000
#define HWIO_GCC_GPLL4_MODE_RESERVE_BITS26_25_SHFT                                                       0x19
#define HWIO_GCC_GPLL4_MODE_FSM_LEGACY_MODE_BMSK                                                    0x1000000
#define HWIO_GCC_GPLL4_MODE_FSM_LEGACY_MODE_SHFT                                                         0x18
#define HWIO_GCC_GPLL4_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_BMSK                                          0x800000
#define HWIO_GCC_GPLL4_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_SHFT                                              0x17
#define HWIO_GCC_GPLL4_MODE_PLL_UPDATE_BMSK                                                          0x400000
#define HWIO_GCC_GPLL4_MODE_PLL_UPDATE_SHFT                                                              0x16
#define HWIO_GCC_GPLL4_MODE_PLL_VOTE_FSM_RESET_BMSK                                                  0x200000
#define HWIO_GCC_GPLL4_MODE_PLL_VOTE_FSM_RESET_SHFT                                                      0x15
#define HWIO_GCC_GPLL4_MODE_PLL_VOTE_FSM_ENA_BMSK                                                    0x100000
#define HWIO_GCC_GPLL4_MODE_PLL_VOTE_FSM_ENA_SHFT                                                        0x14
#define HWIO_GCC_GPLL4_MODE_PLL_BIAS_COUNT_BMSK                                                       0xfc000
#define HWIO_GCC_GPLL4_MODE_PLL_BIAS_COUNT_SHFT                                                           0xe
#define HWIO_GCC_GPLL4_MODE_PLL_LOCK_COUNT_BMSK                                                        0x3f00
#define HWIO_GCC_GPLL4_MODE_PLL_LOCK_COUNT_SHFT                                                           0x8
#define HWIO_GCC_GPLL4_MODE_RESERVE_BIT7_BMSK                                                            0x80
#define HWIO_GCC_GPLL4_MODE_RESERVE_BIT7_SHFT                                                             0x7
#define HWIO_GCC_GPLL4_MODE_OUT_TEST_HW_CTL_BMSK                                                         0x40
#define HWIO_GCC_GPLL4_MODE_OUT_TEST_HW_CTL_SHFT                                                          0x6
#define HWIO_GCC_GPLL4_MODE_OUT_ODD_HW_CTL_BMSK                                                          0x20
#define HWIO_GCC_GPLL4_MODE_OUT_ODD_HW_CTL_SHFT                                                           0x5
#define HWIO_GCC_GPLL4_MODE_OUT_EVEN_HW_CTL_BMSK                                                         0x10
#define HWIO_GCC_GPLL4_MODE_OUT_EVEN_HW_CTL_SHFT                                                          0x4
#define HWIO_GCC_GPLL4_MODE_OUT_MAIN_HW_CTL_BMSK                                                          0x8
#define HWIO_GCC_GPLL4_MODE_OUT_MAIN_HW_CTL_SHFT                                                          0x3
#define HWIO_GCC_GPLL4_MODE_PLL_RESET_N_BMSK                                                              0x4
#define HWIO_GCC_GPLL4_MODE_PLL_RESET_N_SHFT                                                              0x2
#define HWIO_GCC_GPLL4_MODE_RESERVE_BIT1_BMSK                                                             0x2
#define HWIO_GCC_GPLL4_MODE_RESERVE_BIT1_SHFT                                                             0x1
#define HWIO_GCC_GPLL4_MODE_PLL_OUTCTRL_BMSK                                                              0x1
#define HWIO_GCC_GPLL4_MODE_PLL_OUTCTRL_SHFT                                                              0x0

#define HWIO_GCC_GPLL4_L_VAL_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00076004)
#define HWIO_GCC_GPLL4_L_VAL_RMSK                                                                      0xffff
#define HWIO_GCC_GPLL4_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL4_L_VAL_ADDR)
#define HWIO_GCC_GPLL4_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL4_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL4_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_L_VAL_ADDR,m,v,HWIO_GCC_GPLL4_L_VAL_IN)
#define HWIO_GCC_GPLL4_L_VAL_PLL_L_BMSK                                                                0xffff
#define HWIO_GCC_GPLL4_L_VAL_PLL_L_SHFT                                                                   0x0

#define HWIO_GCC_GPLL4_CAL_L_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00076008)
#define HWIO_GCC_GPLL4_CAL_L_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL4_CAL_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL4_CAL_L_VAL_ADDR)
#define HWIO_GCC_GPLL4_CAL_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_CAL_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL4_CAL_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_CAL_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL4_CAL_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_CAL_L_VAL_ADDR,m,v,HWIO_GCC_GPLL4_CAL_L_VAL_IN)
#define HWIO_GCC_GPLL4_CAL_L_VAL_PLL_CAL_L_BMSK                                                        0xffff
#define HWIO_GCC_GPLL4_CAL_L_VAL_PLL_CAL_L_SHFT                                                           0x0

#define HWIO_GCC_GPLL4_USER_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007600c)
#define HWIO_GCC_GPLL4_USER_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL4_USER_CTL_IN          \
        in_dword(HWIO_GCC_GPLL4_USER_CTL_ADDR)
#define HWIO_GCC_GPLL4_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_USER_CTL_ADDR, m)
#define HWIO_GCC_GPLL4_USER_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_USER_CTL_ADDR,v)
#define HWIO_GCC_GPLL4_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_USER_CTL_ADDR,m,v,HWIO_GCC_GPLL4_USER_CTL_IN)
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT31_BMSK                                                 0x80000000
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT31_SHFT                                                       0x1f
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT30_BMSK                                                 0x40000000
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT30_SHFT                                                       0x1e
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT29_BMSK                                                 0x20000000
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT29_SHFT                                                       0x1d
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT28_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT28_SHFT                                                       0x1c
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT27_BMSK                                                  0x8000000
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT27_SHFT                                                       0x1b
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT26_BMSK                                                  0x4000000
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT26_SHFT                                                       0x1a
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT25_BMSK                                                  0x2000000
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT25_SHFT                                                       0x19
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT24_BMSK                                                  0x1000000
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT24_SHFT                                                       0x18
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT23_BMSK                                                   0x800000
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT23_SHFT                                                       0x17
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT22_BMSK                                                   0x400000
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT22_SHFT                                                       0x16
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT21_BMSK                                                   0x200000
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT21_SHFT                                                       0x15
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT20_BMSK                                                   0x100000
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT20_SHFT                                                       0x14
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL4_USER_CTL_PRE_DIV_RATIO_BMSK                                                    0x70000
#define HWIO_GCC_GPLL4_USER_CTL_PRE_DIV_RATIO_SHFT                                                       0x10
#define HWIO_GCC_GPLL4_USER_CTL_POST_DIV_RATIO_ODD_BMSK                                                0xf000
#define HWIO_GCC_GPLL4_USER_CTL_POST_DIV_RATIO_ODD_SHFT                                                   0xc
#define HWIO_GCC_GPLL4_USER_CTL_POST_DIV_RATIO_EVEN_BMSK                                                0xf00
#define HWIO_GCC_GPLL4_USER_CTL_POST_DIV_RATIO_EVEN_SHFT                                                  0x8
#define HWIO_GCC_GPLL4_USER_CTL_OUT_CLK_POLARITY_BMSK                                                    0x80
#define HWIO_GCC_GPLL4_USER_CTL_OUT_CLK_POLARITY_SHFT                                                     0x7
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT6_BMSK                                                        0x40
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT6_SHFT                                                         0x6
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT5_BMSK                                                        0x20
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT5_SHFT                                                         0x5
#define HWIO_GCC_GPLL4_USER_CTL_PLLOUT_TEST_BMSK                                                         0x10
#define HWIO_GCC_GPLL4_USER_CTL_PLLOUT_TEST_SHFT                                                          0x4
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT3_BMSK                                                         0x8
#define HWIO_GCC_GPLL4_USER_CTL_RESERVE_BIT3_SHFT                                                         0x3
#define HWIO_GCC_GPLL4_USER_CTL_PLLOUT_ODD_BMSK                                                           0x4
#define HWIO_GCC_GPLL4_USER_CTL_PLLOUT_ODD_SHFT                                                           0x2
#define HWIO_GCC_GPLL4_USER_CTL_PLLOUT_EVEN_BMSK                                                          0x2
#define HWIO_GCC_GPLL4_USER_CTL_PLLOUT_EVEN_SHFT                                                          0x1
#define HWIO_GCC_GPLL4_USER_CTL_PLLOUT_MAIN_BMSK                                                          0x1
#define HWIO_GCC_GPLL4_USER_CTL_PLLOUT_MAIN_SHFT                                                          0x0

#define HWIO_GCC_GPLL4_USER_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00076010)
#define HWIO_GCC_GPLL4_USER_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL4_USER_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL4_USER_CTL_U_ADDR)
#define HWIO_GCC_GPLL4_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_USER_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL4_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_USER_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL4_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_USER_CTL_U_ADDR,m,v,HWIO_GCC_GPLL4_USER_CTL_U_IN)
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT63_BMSK                                               0x80000000
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT63_SHFT                                                     0x1f
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT62_BMSK                                               0x40000000
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT62_SHFT                                                     0x1e
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT61_BMSK                                               0x20000000
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT61_SHFT                                                     0x1d
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT60_BMSK                                               0x10000000
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT60_SHFT                                                     0x1c
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT59_BMSK                                                0x8000000
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT59_SHFT                                                     0x1b
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT58_BMSK                                                0x4000000
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT58_SHFT                                                     0x1a
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT57_BMSK                                                0x2000000
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT57_SHFT                                                     0x19
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT56_BMSK                                                0x1000000
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT56_SHFT                                                     0x18
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT55_BMSK                                                 0x800000
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT55_SHFT                                                     0x17
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT54_BMSK                                                 0x400000
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT54_SHFT                                                     0x16
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT53_BMSK                                                 0x200000
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT53_SHFT                                                     0x15
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT52_BMSK                                                 0x100000
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT52_SHFT                                                     0x14
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT51_BMSK                                                  0x80000
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT51_SHFT                                                     0x13
#define HWIO_GCC_GPLL4_USER_CTL_U_LOCK_DETECTOR_SELECTION_BMSK                                        0x40000
#define HWIO_GCC_GPLL4_USER_CTL_U_LOCK_DETECTOR_SELECTION_SHFT                                           0x12
#define HWIO_GCC_GPLL4_USER_CTL_U_TYPE_2_MODE_SELECTION_BMSK                                          0x20000
#define HWIO_GCC_GPLL4_USER_CTL_U_TYPE_2_MODE_SELECTION_SHFT                                             0x11
#define HWIO_GCC_GPLL4_USER_CTL_U_BANG_BANG_MODE_SELECTION_BMSK                                       0x10000
#define HWIO_GCC_GPLL4_USER_CTL_U_BANG_BANG_MODE_SELECTION_SHFT                                          0x10
#define HWIO_GCC_GPLL4_USER_CTL_U_FRAC_FORMAT_SEL_BMSK                                                 0x8000
#define HWIO_GCC_GPLL4_USER_CTL_U_FRAC_FORMAT_SEL_SHFT                                                    0xf
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT46_BMSK                                                   0x4000
#define HWIO_GCC_GPLL4_USER_CTL_U_RESERVE_BIT46_SHFT                                                      0xe
#define HWIO_GCC_GPLL4_USER_CTL_U_REF_CLK_AT_OUT_BMSK                                                  0x2000
#define HWIO_GCC_GPLL4_USER_CTL_U_REF_CLK_AT_OUT_SHFT                                                     0xd
#define HWIO_GCC_GPLL4_USER_CTL_U_SCALE_FREQ_ON_RESTART_BMSK                                           0x1800
#define HWIO_GCC_GPLL4_USER_CTL_U_SCALE_FREQ_ON_RESTART_SHFT                                              0xb
#define HWIO_GCC_GPLL4_USER_CTL_U_LATCH_INTERFACE_BYPASS_BMSK                                           0x400
#define HWIO_GCC_GPLL4_USER_CTL_U_LATCH_INTERFACE_BYPASS_SHFT                                             0xa
#define HWIO_GCC_GPLL4_USER_CTL_U_STATUS_REGISTER_BMSK                                                  0x3e0
#define HWIO_GCC_GPLL4_USER_CTL_U_STATUS_REGISTER_SHFT                                                    0x5
#define HWIO_GCC_GPLL4_USER_CTL_U_WRITE_STATE_EN_BMSK                                                    0x10
#define HWIO_GCC_GPLL4_USER_CTL_U_WRITE_STATE_EN_SHFT                                                     0x4
#define HWIO_GCC_GPLL4_USER_CTL_U_CALIB_CTRL_BMSK                                                         0xe
#define HWIO_GCC_GPLL4_USER_CTL_U_CALIB_CTRL_SHFT                                                         0x1
#define HWIO_GCC_GPLL4_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_BMSK                                             0x1
#define HWIO_GCC_GPLL4_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_SHFT                                             0x0

#define HWIO_GCC_GPLL4_USER_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00076014)
#define HWIO_GCC_GPLL4_USER_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL4_USER_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL4_USER_CTL_U1_ADDR)
#define HWIO_GCC_GPLL4_USER_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_USER_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL4_USER_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_USER_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL4_USER_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_USER_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL4_USER_CTL_U1_IN)
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT93_BMSK                                              0x20000000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT93_SHFT                                                    0x1d
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT92_BMSK                                              0x10000000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT92_SHFT                                                    0x1c
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT86_BMSK                                                0x400000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT86_SHFT                                                    0x16
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT82_BMSK                                                 0x40000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT82_SHFT                                                    0x12
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT81_BMSK                                                 0x20000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT81_SHFT                                                    0x11
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT80_BMSK                                                 0x10000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT80_SHFT                                                    0x10
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT79_BMSK                                                  0x8000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT79_SHFT                                                     0xf
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT78_BMSK                                                  0x4000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT78_SHFT                                                     0xe
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT77_BMSK                                                  0x2000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT77_SHFT                                                     0xd
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT71_BMSK                                                    0x80
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT71_SHFT                                                     0x7
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT70_BMSK                                                    0x40
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT70_SHFT                                                     0x6
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT69_BMSK                                                    0x20
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT69_SHFT                                                     0x5
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT65_BMSK                                                     0x2
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT65_SHFT                                                     0x1
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT64_BMSK                                                     0x1
#define HWIO_GCC_GPLL4_USER_CTL_U1_RESERVE_BIT64_SHFT                                                     0x0

#define HWIO_GCC_GPLL4_CONFIG_CTL_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00076018)
#define HWIO_GCC_GPLL4_CONFIG_CTL_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL4_CONFIG_CTL_IN          \
        in_dword(HWIO_GCC_GPLL4_CONFIG_CTL_ADDR)
#define HWIO_GCC_GPLL4_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_CONFIG_CTL_ADDR, m)
#define HWIO_GCC_GPLL4_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_CONFIG_CTL_ADDR,v)
#define HWIO_GCC_GPLL4_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_CONFIG_CTL_ADDR,m,v,HWIO_GCC_GPLL4_CONFIG_CTL_IN)
#define HWIO_GCC_GPLL4_CONFIG_CTL_FINE_LDC_THRESHOLD_BMSK                                          0xfc000000
#define HWIO_GCC_GPLL4_CONFIG_CTL_FINE_LDC_THRESHOLD_SHFT                                                0x1a
#define HWIO_GCC_GPLL4_CONFIG_CTL_COARSE_LDC_THRESHOLD_BMSK                                         0x3c00000
#define HWIO_GCC_GPLL4_CONFIG_CTL_COARSE_LDC_THRESHOLD_SHFT                                              0x16
#define HWIO_GCC_GPLL4_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_BMSK                                 0x3c0000
#define HWIO_GCC_GPLL4_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_SHFT                                     0x12
#define HWIO_GCC_GPLL4_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_BMSK                                  0x3c000
#define HWIO_GCC_GPLL4_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_SHFT                                      0xe
#define HWIO_GCC_GPLL4_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_BMSK                                         0x3800
#define HWIO_GCC_GPLL4_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_SHFT                                            0xb
#define HWIO_GCC_GPLL4_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_BMSK                                        0x700
#define HWIO_GCC_GPLL4_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_SHFT                                          0x8
#define HWIO_GCC_GPLL4_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_BMSK                                              0xf0
#define HWIO_GCC_GPLL4_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_SHFT                                               0x4
#define HWIO_GCC_GPLL4_CONFIG_CTL_FWD_GAIN_KFN_BMSK                                                       0xf
#define HWIO_GCC_GPLL4_CONFIG_CTL_FWD_GAIN_KFN_SHFT                                                       0x0

#define HWIO_GCC_GPLL4_CONFIG_CTL_U_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0007601c)
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_RMSK                                                           0xffffffff
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL4_CONFIG_CTL_U_ADDR)
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_CONFIG_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_CONFIG_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_CONFIG_CTL_U_ADDR,m,v,HWIO_GCC_GPLL4_CONFIG_CTL_U_IN)
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_BIST_CFG_BMSK                                                  0xffff0000
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_BIST_CFG_SHFT                                                        0x10
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_BMSK                                       0xc000
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_SHFT                                          0xe
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_OSC_SETTLING_TIME_BMSK                                             0x3000
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_OSC_SETTLING_TIME_SHFT                                                0xc
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_BMSK                                            0xc00
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_SHFT                                              0xa
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_CASC_CURRENT_CTL_B_BMSK                                             0x380
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_CASC_CURRENT_CTL_B_SHFT                                               0x7
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_BMSK                                     0x40
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_SHFT                                      0x6
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_BMSK                                            0x30
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_SHFT                                             0x4
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_LDET_THRESH_SCALE_BMSK                                                0x8
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_LDET_THRESH_SCALE_SHFT                                                0x3
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_DCO_STARTUP_CONFIG_BMSK                                               0x6
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_DCO_STARTUP_CONFIG_SHFT                                               0x1
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_BMSK                                          0x1
#define HWIO_GCC_GPLL4_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_SHFT                                          0x0

#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00076020)
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_RMSK                                                          0xffffffff
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL4_CONFIG_CTL_U1_ADDR)
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_CONFIG_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_CONFIG_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_CONFIG_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL4_CONFIG_CTL_U1_IN)
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BB_CAL_THRESHOLD_BMSK                                         0xc0000000
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BB_CAL_THRESHOLD_SHFT                                               0x1e
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_PCODE_OFFSET_BMSK                                             0x38000000
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_PCODE_OFFSET_SHFT                                                   0x1b
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_COUNTER_BLANK_BMSK                                             0x4000000
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_COUNTER_BLANK_SHFT                                                  0x1a
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BB_RESYNC_EDGE_BMSK                                            0x2000000
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BB_RESYNC_EDGE_SHFT                                                 0x19
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BB_RESYNC_SEL_BMSK                                             0x1000000
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BB_RESYNC_SEL_SHFT                                                  0x18
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_BMSK                                        0xc00000
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_SHFT                                            0x16
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BB_LOCK_THRESH_BMSK                                             0x380000
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BB_LOCK_THRESH_SHFT                                                 0x13
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_RESERVE_BIT82_BMSK                                               0x40000
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_RESERVE_BIT82_SHFT                                                  0x12
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_BMSK                                          0x30000
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_SHFT                                             0x10
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_BMSK                                            0xc000
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_SHFT                                               0xe
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BB_CAL_EN_BMSK                                                    0x2000
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BB_CAL_EN_SHFT                                                       0xd
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_BMSK                                      0x1800
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_SHFT                                         0xb
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BBMODE_INT_GAIN_BMSK                                               0x780
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BBMODE_INT_GAIN_SHFT                                                 0x7
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BBMODE_PROP_GAIN_BMSK                                               0x78
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_BBMODE_PROP_GAIN_SHFT                                                0x3
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_TDC_SELECTION_BMSK                                                   0x4
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_TDC_SELECTION_SHFT                                                   0x2
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_RESERVE_BIT65_BMSK                                                   0x2
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_RESERVE_BIT65_SHFT                                                   0x1
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_FORCE_DSM_ON_BMSK                                                    0x1
#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_FORCE_DSM_ON_SHFT                                                    0x0

#define HWIO_GCC_GPLL4_TEST_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00076024)
#define HWIO_GCC_GPLL4_TEST_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL4_TEST_CTL_IN          \
        in_dword(HWIO_GCC_GPLL4_TEST_CTL_ADDR)
#define HWIO_GCC_GPLL4_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_TEST_CTL_ADDR, m)
#define HWIO_GCC_GPLL4_TEST_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_TEST_CTL_ADDR,v)
#define HWIO_GCC_GPLL4_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_TEST_CTL_ADDR,m,v,HWIO_GCC_GPLL4_TEST_CTL_IN)
#define HWIO_GCC_GPLL4_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_BMSK                                       0xc0000000
#define HWIO_GCC_GPLL4_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_SHFT                                             0x1e
#define HWIO_GCC_GPLL4_TEST_CTL_BYPASS_FIRST_ORDER_DSM_BMSK                                        0x20000000
#define HWIO_GCC_GPLL4_TEST_CTL_BYPASS_FIRST_ORDER_DSM_SHFT                                              0x1d
#define HWIO_GCC_GPLL4_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_BMSK                                   0x18000000
#define HWIO_GCC_GPLL4_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_SHFT                                         0x1b
#define HWIO_GCC_GPLL4_TEST_CTL_GLITCH_PREVENTION_DIS_BMSK                                          0x4000000
#define HWIO_GCC_GPLL4_TEST_CTL_GLITCH_PREVENTION_DIS_SHFT                                               0x1a
#define HWIO_GCC_GPLL4_TEST_CTL_ATEST_ISCALE_BMSK                                                   0x3000000
#define HWIO_GCC_GPLL4_TEST_CTL_ATEST_ISCALE_SHFT                                                        0x18
#define HWIO_GCC_GPLL4_TEST_CTL_PLL_TEST_OUT_SEL_BMSK                                                0xf00000
#define HWIO_GCC_GPLL4_TEST_CTL_PLL_TEST_OUT_SEL_SHFT                                                    0x14
#define HWIO_GCC_GPLL4_TEST_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL4_TEST_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL4_TEST_CTL_DIV2_NMO_EN_BMSK                                                      0x40000
#define HWIO_GCC_GPLL4_TEST_CTL_DIV2_NMO_EN_SHFT                                                         0x12
#define HWIO_GCC_GPLL4_TEST_CTL_NMO_OSC_SEL_BMSK                                                      0x30000
#define HWIO_GCC_GPLL4_TEST_CTL_NMO_OSC_SEL_SHFT                                                         0x10
#define HWIO_GCC_GPLL4_TEST_CTL_NOISE_MAG_BMSK                                                         0xe000
#define HWIO_GCC_GPLL4_TEST_CTL_NOISE_MAG_SHFT                                                            0xd
#define HWIO_GCC_GPLL4_TEST_CTL_NOISE_GEN_EN_BMSK                                                      0x1000
#define HWIO_GCC_GPLL4_TEST_CTL_NOISE_GEN_EN_SHFT                                                         0xc
#define HWIO_GCC_GPLL4_TEST_CTL_DISABLE_DCAPS_BMSK                                                      0x800
#define HWIO_GCC_GPLL4_TEST_CTL_DISABLE_DCAPS_SHFT                                                        0xb
#define HWIO_GCC_GPLL4_TEST_CTL_RESERVE_BIT10_BMSK                                                      0x400
#define HWIO_GCC_GPLL4_TEST_CTL_RESERVE_BIT10_SHFT                                                        0xa
#define HWIO_GCC_GPLL4_TEST_CTL_RESERVE_BIT9_BMSK                                                       0x200
#define HWIO_GCC_GPLL4_TEST_CTL_RESERVE_BIT9_SHFT                                                         0x9
#define HWIO_GCC_GPLL4_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_BMSK                                            0x100
#define HWIO_GCC_GPLL4_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_SHFT                                              0x8
#define HWIO_GCC_GPLL4_TEST_CTL_EN_VDD_TEST_BMSK                                                         0x80
#define HWIO_GCC_GPLL4_TEST_CTL_EN_VDD_TEST_SHFT                                                          0x7
#define HWIO_GCC_GPLL4_TEST_CTL_EN_VREG_TEST_BMSK                                                        0x40
#define HWIO_GCC_GPLL4_TEST_CTL_EN_VREG_TEST_SHFT                                                         0x6
#define HWIO_GCC_GPLL4_TEST_CTL_EN_VREF_TEST_BMSK                                                        0x20
#define HWIO_GCC_GPLL4_TEST_CTL_EN_VREF_TEST_SHFT                                                         0x5
#define HWIO_GCC_GPLL4_TEST_CTL_EN_VDCO_TEST_BMSK                                                        0x10
#define HWIO_GCC_GPLL4_TEST_CTL_EN_VDCO_TEST_SHFT                                                         0x4
#define HWIO_GCC_GPLL4_TEST_CTL_BYPASS_ATEST_BUFFER_BMSK                                                  0x8
#define HWIO_GCC_GPLL4_TEST_CTL_BYPASS_ATEST_BUFFER_SHFT                                                  0x3
#define HWIO_GCC_GPLL4_TEST_CTL_EN_IVCO_TEST_BMSK                                                         0x4
#define HWIO_GCC_GPLL4_TEST_CTL_EN_IVCO_TEST_SHFT                                                         0x2
#define HWIO_GCC_GPLL4_TEST_CTL_ATEST1_EN_BMSK                                                            0x2
#define HWIO_GCC_GPLL4_TEST_CTL_ATEST1_EN_SHFT                                                            0x1
#define HWIO_GCC_GPLL4_TEST_CTL_ATEST0_EN_BMSK                                                            0x1
#define HWIO_GCC_GPLL4_TEST_CTL_ATEST0_EN_SHFT                                                            0x0

#define HWIO_GCC_GPLL4_TEST_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00076028)
#define HWIO_GCC_GPLL4_TEST_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL4_TEST_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL4_TEST_CTL_U_ADDR)
#define HWIO_GCC_GPLL4_TEST_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_TEST_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL4_TEST_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_TEST_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL4_TEST_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_TEST_CTL_U_ADDR,m,v,HWIO_GCC_GPLL4_TEST_CTL_U_IN)
#define HWIO_GCC_GPLL4_TEST_CTL_U_CASC_DAC_FCW_LSBS_BMSK                                           0xe0000000
#define HWIO_GCC_GPLL4_TEST_CTL_U_CASC_DAC_FCW_LSBS_SHFT                                                 0x1d
#define HWIO_GCC_GPLL4_TEST_CTL_U_OVERRIDE_CASC_DAC_BMSK                                           0x10000000
#define HWIO_GCC_GPLL4_TEST_CTL_U_OVERRIDE_CASC_DAC_SHFT                                                 0x1c
#define HWIO_GCC_GPLL4_TEST_CTL_U_COMP_COARSE_FCW_BMSK                                              0xe000000
#define HWIO_GCC_GPLL4_TEST_CTL_U_COMP_COARSE_FCW_SHFT                                                   0x19
#define HWIO_GCC_GPLL4_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_BMSK                                     0x1800000
#define HWIO_GCC_GPLL4_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_SHFT                                          0x17
#define HWIO_GCC_GPLL4_TEST_CTL_U_FINE_FCW_BMSK                                                      0x7e0000
#define HWIO_GCC_GPLL4_TEST_CTL_U_FINE_FCW_SHFT                                                          0x11
#define HWIO_GCC_GPLL4_TEST_CTL_U_OVERRIDE_FINE_FCW_BMSK                                              0x10000
#define HWIO_GCC_GPLL4_TEST_CTL_U_OVERRIDE_FINE_FCW_SHFT                                                 0x10
#define HWIO_GCC_GPLL4_TEST_CTL_U_REG_COARSE_FCW_BMSK                                                  0xfe00
#define HWIO_GCC_GPLL4_TEST_CTL_U_REG_COARSE_FCW_SHFT                                                     0x9
#define HWIO_GCC_GPLL4_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_BMSK                                          0x100
#define HWIO_GCC_GPLL4_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_SHFT                                            0x8
#define HWIO_GCC_GPLL4_TEST_CTL_U_PROCESS_CALIB_WORD_BMSK                                                0xe0
#define HWIO_GCC_GPLL4_TEST_CTL_U_PROCESS_CALIB_WORD_SHFT                                                 0x5
#define HWIO_GCC_GPLL4_TEST_CTL_U_OVERRIDE_CALIB_WORD_BMSK                                               0x10
#define HWIO_GCC_GPLL4_TEST_CTL_U_OVERRIDE_CALIB_WORD_SHFT                                                0x4
#define HWIO_GCC_GPLL4_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_BMSK                                             0x8
#define HWIO_GCC_GPLL4_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_SHFT                                             0x3
#define HWIO_GCC_GPLL4_TEST_CTL_U_DISABLE_LFSR_BMSK                                                       0x4
#define HWIO_GCC_GPLL4_TEST_CTL_U_DISABLE_LFSR_SHFT                                                       0x2
#define HWIO_GCC_GPLL4_TEST_CTL_U_SKIP_FINE_TUNE_BMSK                                                     0x2
#define HWIO_GCC_GPLL4_TEST_CTL_U_SKIP_FINE_TUNE_SHFT                                                     0x1
#define HWIO_GCC_GPLL4_TEST_CTL_U_SKIP_FAST_LOCK_BMSK                                                     0x1
#define HWIO_GCC_GPLL4_TEST_CTL_U_SKIP_FAST_LOCK_SHFT                                                     0x0

#define HWIO_GCC_GPLL4_TEST_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0007602c)
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL4_TEST_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL4_TEST_CTL_U1_ADDR)
#define HWIO_GCC_GPLL4_TEST_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_TEST_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL4_TEST_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_TEST_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL4_TEST_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_TEST_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL4_TEST_CTL_U1_IN)
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL4_TEST_CTL_U1_FLL_COUNT_DISABLE_BMSK                                          0x20000000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_FLL_COUNT_DISABLE_SHFT                                                0x1d
#define HWIO_GCC_GPLL4_TEST_CTL_U1_FLL_COUNT_IN_DIV2_BMSK                                          0x10000000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_FLL_COUNT_IN_DIV2_SHFT                                                0x1c
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL4_TEST_CTL_U1_SILENCE_REF_OUTBUF_BMSK                                           0x400000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_SILENCE_REF_OUTBUF_SHFT                                               0x16
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL4_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_BMSK                                         0x40000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_SHFT                                            0x12
#define HWIO_GCC_GPLL4_TEST_CTL_U1_REF_CLK_SEL_BMSK                                                   0x20000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_REF_CLK_SEL_SHFT                                                      0x11
#define HWIO_GCC_GPLL4_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_BMSK                                     0x10000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_SHFT                                        0x10
#define HWIO_GCC_GPLL4_TEST_CTL_U1_DIS_AMP_STARTUP_BMSK                                                0x8000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_DIS_AMP_STARTUP_SHFT                                                   0xf
#define HWIO_GCC_GPLL4_TEST_CTL_U1_DISABLE_CLAMP_BMSK                                                  0x4000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_DISABLE_CLAMP_SHFT                                                     0xe
#define HWIO_GCC_GPLL4_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_BMSK                                        0x2000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_SHFT                                           0xd
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL4_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_BMSK                                          0x80
#define HWIO_GCC_GPLL4_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_SHFT                                           0x7
#define HWIO_GCC_GPLL4_TEST_CTL_U1_ENABLE_TRAINING_SEQ_BMSK                                              0x40
#define HWIO_GCC_GPLL4_TEST_CTL_U1_ENABLE_TRAINING_SEQ_SHFT                                               0x6
#define HWIO_GCC_GPLL4_TEST_CTL_U1_STATUS_REG_EN_BMSK                                                    0x20
#define HWIO_GCC_GPLL4_TEST_CTL_U1_STATUS_REG_EN_SHFT                                                     0x5
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL4_TEST_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL4_TEST_CTL_U1_CASC_DAC_FCW_MSBS_BMSK                                                 0x3
#define HWIO_GCC_GPLL4_TEST_CTL_U1_CASC_DAC_FCW_MSBS_SHFT                                                 0x0

#define HWIO_GCC_GPLL4_STATUS_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00076030)
#define HWIO_GCC_GPLL4_STATUS_RMSK                                                                 0xffffffff
#define HWIO_GCC_GPLL4_STATUS_IN          \
        in_dword(HWIO_GCC_GPLL4_STATUS_ADDR)
#define HWIO_GCC_GPLL4_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_STATUS_ADDR, m)
#define HWIO_GCC_GPLL4_STATUS_STATUS_31_0_BMSK                                                     0xffffffff
#define HWIO_GCC_GPLL4_STATUS_STATUS_31_0_SHFT                                                            0x0

#define HWIO_GCC_GPLL4_FREQ_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00076034)
#define HWIO_GCC_GPLL4_FREQ_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL4_FREQ_CTL_IN          \
        in_dword(HWIO_GCC_GPLL4_FREQ_CTL_ADDR)
#define HWIO_GCC_GPLL4_FREQ_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_FREQ_CTL_ADDR, m)
#define HWIO_GCC_GPLL4_FREQ_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_FREQ_CTL_ADDR,v)
#define HWIO_GCC_GPLL4_FREQ_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_FREQ_CTL_ADDR,m,v,HWIO_GCC_GPLL4_FREQ_CTL_IN)
#define HWIO_GCC_GPLL4_FREQ_CTL_FREQUENCY_CTL_WORD_BMSK                                            0xffffffff
#define HWIO_GCC_GPLL4_FREQ_CTL_FREQUENCY_CTL_WORD_SHFT                                                   0x0

#define HWIO_GCC_GPLL4_OPMODE_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00076038)
#define HWIO_GCC_GPLL4_OPMODE_RMSK                                                                        0x7
#define HWIO_GCC_GPLL4_OPMODE_IN          \
        in_dword(HWIO_GCC_GPLL4_OPMODE_ADDR)
#define HWIO_GCC_GPLL4_OPMODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_OPMODE_ADDR, m)
#define HWIO_GCC_GPLL4_OPMODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_OPMODE_ADDR,v)
#define HWIO_GCC_GPLL4_OPMODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_OPMODE_ADDR,m,v,HWIO_GCC_GPLL4_OPMODE_IN)
#define HWIO_GCC_GPLL4_OPMODE_PLL_OPMODE_BMSK                                                             0x7
#define HWIO_GCC_GPLL4_OPMODE_PLL_OPMODE_SHFT                                                             0x0

#define HWIO_GCC_GPLL4_STATE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0007603c)
#define HWIO_GCC_GPLL4_STATE_RMSK                                                                         0x7
#define HWIO_GCC_GPLL4_STATE_IN          \
        in_dword(HWIO_GCC_GPLL4_STATE_ADDR)
#define HWIO_GCC_GPLL4_STATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_STATE_ADDR, m)
#define HWIO_GCC_GPLL4_STATE_PLL_STATE_BMSK                                                               0x7
#define HWIO_GCC_GPLL4_STATE_PLL_STATE_SHFT                                                               0x0

#define HWIO_GCC_GPLL4_ALPHA_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00076040)
#define HWIO_GCC_GPLL4_ALPHA_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL4_ALPHA_VAL_IN          \
        in_dword(HWIO_GCC_GPLL4_ALPHA_VAL_ADDR)
#define HWIO_GCC_GPLL4_ALPHA_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_ALPHA_VAL_ADDR, m)
#define HWIO_GCC_GPLL4_ALPHA_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_ALPHA_VAL_ADDR,v)
#define HWIO_GCC_GPLL4_ALPHA_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_ALPHA_VAL_ADDR,m,v,HWIO_GCC_GPLL4_ALPHA_VAL_IN)
#define HWIO_GCC_GPLL4_ALPHA_VAL_PLL_ALPHA_VAL_BMSK                                                    0xffff
#define HWIO_GCC_GPLL4_ALPHA_VAL_PLL_ALPHA_VAL_SHFT                                                       0x0

#define HWIO_GCC_GPLL4_SPARE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00076044)
#define HWIO_GCC_GPLL4_SPARE_RMSK                                                                        0xff
#define HWIO_GCC_GPLL4_SPARE_IN          \
        in_dword(HWIO_GCC_GPLL4_SPARE_ADDR)
#define HWIO_GCC_GPLL4_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_SPARE_ADDR, m)
#define HWIO_GCC_GPLL4_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_SPARE_ADDR,v)
#define HWIO_GCC_GPLL4_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_SPARE_ADDR,m,v,HWIO_GCC_GPLL4_SPARE_IN)
#define HWIO_GCC_GPLL4_SPARE_SPARE_OUTPUTS_BMSK                                                          0xf0
#define HWIO_GCC_GPLL4_SPARE_SPARE_OUTPUTS_SHFT                                                           0x4
#define HWIO_GCC_GPLL4_SPARE_SPARE_INPUTS_BMSK                                                            0xf
#define HWIO_GCC_GPLL4_SPARE_SPARE_INPUTS_SHFT                                                            0x0

#define HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00076048)
#define HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_RMSK                                                              0xff
#define HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_IN          \
        in_dword(HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_ADDR)
#define HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_ADDR, m)
#define HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_ADDR,v)
#define HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_ADDR,m,v,HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_IN)
#define HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_BMSK                                              0xff
#define HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_SHFT                                               0x0

#define HWIO_GCC_GPLL4_SSC_NUM_STEPS_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0007604c)
#define HWIO_GCC_GPLL4_SSC_NUM_STEPS_RMSK                                                                 0xf
#define HWIO_GCC_GPLL4_SSC_NUM_STEPS_IN          \
        in_dword(HWIO_GCC_GPLL4_SSC_NUM_STEPS_ADDR)
#define HWIO_GCC_GPLL4_SSC_NUM_STEPS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_SSC_NUM_STEPS_ADDR, m)
#define HWIO_GCC_GPLL4_SSC_NUM_STEPS_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_SSC_NUM_STEPS_ADDR,v)
#define HWIO_GCC_GPLL4_SSC_NUM_STEPS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_SSC_NUM_STEPS_ADDR,m,v,HWIO_GCC_GPLL4_SSC_NUM_STEPS_IN)
#define HWIO_GCC_GPLL4_SSC_NUM_STEPS_SSC_NUM_STEPS_BMSK                                                   0xf
#define HWIO_GCC_GPLL4_SSC_NUM_STEPS_SSC_NUM_STEPS_SHFT                                                   0x0

#define HWIO_GCC_GPLL4_SSC_UPDATE_RATE_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00076050)
#define HWIO_GCC_GPLL4_SSC_UPDATE_RATE_RMSK                                                               0xf
#define HWIO_GCC_GPLL4_SSC_UPDATE_RATE_IN          \
        in_dword(HWIO_GCC_GPLL4_SSC_UPDATE_RATE_ADDR)
#define HWIO_GCC_GPLL4_SSC_UPDATE_RATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL4_SSC_UPDATE_RATE_ADDR, m)
#define HWIO_GCC_GPLL4_SSC_UPDATE_RATE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL4_SSC_UPDATE_RATE_ADDR,v)
#define HWIO_GCC_GPLL4_SSC_UPDATE_RATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL4_SSC_UPDATE_RATE_ADDR,m,v,HWIO_GCC_GPLL4_SSC_UPDATE_RATE_IN)
#define HWIO_GCC_GPLL4_SSC_UPDATE_RATE_SSC_UPDATE_RATE_BMSK                                               0xf
#define HWIO_GCC_GPLL4_SSC_UPDATE_RATE_SSC_UPDATE_RATE_SHFT                                               0x0

#define HWIO_GCC_GPLL5_MODE_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00074000)
#define HWIO_GCC_GPLL5_MODE_RMSK                                                                   0xffffffff
#define HWIO_GCC_GPLL5_MODE_IN          \
        in_dword(HWIO_GCC_GPLL5_MODE_ADDR)
#define HWIO_GCC_GPLL5_MODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_MODE_ADDR, m)
#define HWIO_GCC_GPLL5_MODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_MODE_ADDR,v)
#define HWIO_GCC_GPLL5_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_MODE_ADDR,m,v,HWIO_GCC_GPLL5_MODE_IN)
#define HWIO_GCC_GPLL5_MODE_PLL_LOCK_DET_BMSK                                                      0x80000000
#define HWIO_GCC_GPLL5_MODE_PLL_LOCK_DET_SHFT                                                            0x1f
#define HWIO_GCC_GPLL5_MODE_PLL_ACTIVE_FLAG_BMSK                                                   0x40000000
#define HWIO_GCC_GPLL5_MODE_PLL_ACTIVE_FLAG_SHFT                                                         0x1e
#define HWIO_GCC_GPLL5_MODE_PLL_ACK_LATCH_BMSK                                                     0x20000000
#define HWIO_GCC_GPLL5_MODE_PLL_ACK_LATCH_SHFT                                                           0x1d
#define HWIO_GCC_GPLL5_MODE_PLL_LOCK_DET_FINE_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL5_MODE_PLL_LOCK_DET_FINE_SHFT                                                       0x1c
#define HWIO_GCC_GPLL5_MODE_PCAL_DONE_BMSK                                                          0x8000000
#define HWIO_GCC_GPLL5_MODE_PCAL_DONE_SHFT                                                               0x1b
#define HWIO_GCC_GPLL5_MODE_RESERVE_BITS26_25_BMSK                                                  0x6000000
#define HWIO_GCC_GPLL5_MODE_RESERVE_BITS26_25_SHFT                                                       0x19
#define HWIO_GCC_GPLL5_MODE_FSM_LEGACY_MODE_BMSK                                                    0x1000000
#define HWIO_GCC_GPLL5_MODE_FSM_LEGACY_MODE_SHFT                                                         0x18
#define HWIO_GCC_GPLL5_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_BMSK                                          0x800000
#define HWIO_GCC_GPLL5_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_SHFT                                              0x17
#define HWIO_GCC_GPLL5_MODE_PLL_UPDATE_BMSK                                                          0x400000
#define HWIO_GCC_GPLL5_MODE_PLL_UPDATE_SHFT                                                              0x16
#define HWIO_GCC_GPLL5_MODE_PLL_VOTE_FSM_RESET_BMSK                                                  0x200000
#define HWIO_GCC_GPLL5_MODE_PLL_VOTE_FSM_RESET_SHFT                                                      0x15
#define HWIO_GCC_GPLL5_MODE_PLL_VOTE_FSM_ENA_BMSK                                                    0x100000
#define HWIO_GCC_GPLL5_MODE_PLL_VOTE_FSM_ENA_SHFT                                                        0x14
#define HWIO_GCC_GPLL5_MODE_PLL_BIAS_COUNT_BMSK                                                       0xfc000
#define HWIO_GCC_GPLL5_MODE_PLL_BIAS_COUNT_SHFT                                                           0xe
#define HWIO_GCC_GPLL5_MODE_PLL_LOCK_COUNT_BMSK                                                        0x3f00
#define HWIO_GCC_GPLL5_MODE_PLL_LOCK_COUNT_SHFT                                                           0x8
#define HWIO_GCC_GPLL5_MODE_RESERVE_BIT7_BMSK                                                            0x80
#define HWIO_GCC_GPLL5_MODE_RESERVE_BIT7_SHFT                                                             0x7
#define HWIO_GCC_GPLL5_MODE_OUT_TEST_HW_CTL_BMSK                                                         0x40
#define HWIO_GCC_GPLL5_MODE_OUT_TEST_HW_CTL_SHFT                                                          0x6
#define HWIO_GCC_GPLL5_MODE_OUT_ODD_HW_CTL_BMSK                                                          0x20
#define HWIO_GCC_GPLL5_MODE_OUT_ODD_HW_CTL_SHFT                                                           0x5
#define HWIO_GCC_GPLL5_MODE_OUT_EVEN_HW_CTL_BMSK                                                         0x10
#define HWIO_GCC_GPLL5_MODE_OUT_EVEN_HW_CTL_SHFT                                                          0x4
#define HWIO_GCC_GPLL5_MODE_OUT_MAIN_HW_CTL_BMSK                                                          0x8
#define HWIO_GCC_GPLL5_MODE_OUT_MAIN_HW_CTL_SHFT                                                          0x3
#define HWIO_GCC_GPLL5_MODE_PLL_RESET_N_BMSK                                                              0x4
#define HWIO_GCC_GPLL5_MODE_PLL_RESET_N_SHFT                                                              0x2
#define HWIO_GCC_GPLL5_MODE_RESERVE_BIT1_BMSK                                                             0x2
#define HWIO_GCC_GPLL5_MODE_RESERVE_BIT1_SHFT                                                             0x1
#define HWIO_GCC_GPLL5_MODE_PLL_OUTCTRL_BMSK                                                              0x1
#define HWIO_GCC_GPLL5_MODE_PLL_OUTCTRL_SHFT                                                              0x0

#define HWIO_GCC_GPLL5_L_VAL_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00074004)
#define HWIO_GCC_GPLL5_L_VAL_RMSK                                                                      0xffff
#define HWIO_GCC_GPLL5_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL5_L_VAL_ADDR)
#define HWIO_GCC_GPLL5_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL5_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL5_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_L_VAL_ADDR,m,v,HWIO_GCC_GPLL5_L_VAL_IN)
#define HWIO_GCC_GPLL5_L_VAL_PLL_L_BMSK                                                                0xffff
#define HWIO_GCC_GPLL5_L_VAL_PLL_L_SHFT                                                                   0x0

#define HWIO_GCC_GPLL5_CAL_L_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00074008)
#define HWIO_GCC_GPLL5_CAL_L_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL5_CAL_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL5_CAL_L_VAL_ADDR)
#define HWIO_GCC_GPLL5_CAL_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_CAL_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL5_CAL_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_CAL_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL5_CAL_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_CAL_L_VAL_ADDR,m,v,HWIO_GCC_GPLL5_CAL_L_VAL_IN)
#define HWIO_GCC_GPLL5_CAL_L_VAL_PLL_CAL_L_BMSK                                                        0xffff
#define HWIO_GCC_GPLL5_CAL_L_VAL_PLL_CAL_L_SHFT                                                           0x0

#define HWIO_GCC_GPLL5_USER_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007400c)
#define HWIO_GCC_GPLL5_USER_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL5_USER_CTL_IN          \
        in_dword(HWIO_GCC_GPLL5_USER_CTL_ADDR)
#define HWIO_GCC_GPLL5_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_USER_CTL_ADDR, m)
#define HWIO_GCC_GPLL5_USER_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_USER_CTL_ADDR,v)
#define HWIO_GCC_GPLL5_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_USER_CTL_ADDR,m,v,HWIO_GCC_GPLL5_USER_CTL_IN)
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT31_BMSK                                                 0x80000000
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT31_SHFT                                                       0x1f
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT30_BMSK                                                 0x40000000
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT30_SHFT                                                       0x1e
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT29_BMSK                                                 0x20000000
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT29_SHFT                                                       0x1d
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT28_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT28_SHFT                                                       0x1c
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT27_BMSK                                                  0x8000000
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT27_SHFT                                                       0x1b
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT26_BMSK                                                  0x4000000
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT26_SHFT                                                       0x1a
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT25_BMSK                                                  0x2000000
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT25_SHFT                                                       0x19
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT24_BMSK                                                  0x1000000
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT24_SHFT                                                       0x18
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT23_BMSK                                                   0x800000
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT23_SHFT                                                       0x17
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT22_BMSK                                                   0x400000
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT22_SHFT                                                       0x16
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT21_BMSK                                                   0x200000
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT21_SHFT                                                       0x15
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT20_BMSK                                                   0x100000
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT20_SHFT                                                       0x14
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL5_USER_CTL_PRE_DIV_RATIO_BMSK                                                    0x70000
#define HWIO_GCC_GPLL5_USER_CTL_PRE_DIV_RATIO_SHFT                                                       0x10
#define HWIO_GCC_GPLL5_USER_CTL_POST_DIV_RATIO_ODD_BMSK                                                0xf000
#define HWIO_GCC_GPLL5_USER_CTL_POST_DIV_RATIO_ODD_SHFT                                                   0xc
#define HWIO_GCC_GPLL5_USER_CTL_POST_DIV_RATIO_EVEN_BMSK                                                0xf00
#define HWIO_GCC_GPLL5_USER_CTL_POST_DIV_RATIO_EVEN_SHFT                                                  0x8
#define HWIO_GCC_GPLL5_USER_CTL_OUT_CLK_POLARITY_BMSK                                                    0x80
#define HWIO_GCC_GPLL5_USER_CTL_OUT_CLK_POLARITY_SHFT                                                     0x7
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT6_BMSK                                                        0x40
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT6_SHFT                                                         0x6
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT5_BMSK                                                        0x20
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT5_SHFT                                                         0x5
#define HWIO_GCC_GPLL5_USER_CTL_PLLOUT_TEST_BMSK                                                         0x10
#define HWIO_GCC_GPLL5_USER_CTL_PLLOUT_TEST_SHFT                                                          0x4
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT3_BMSK                                                         0x8
#define HWIO_GCC_GPLL5_USER_CTL_RESERVE_BIT3_SHFT                                                         0x3
#define HWIO_GCC_GPLL5_USER_CTL_PLLOUT_ODD_BMSK                                                           0x4
#define HWIO_GCC_GPLL5_USER_CTL_PLLOUT_ODD_SHFT                                                           0x2
#define HWIO_GCC_GPLL5_USER_CTL_PLLOUT_EVEN_BMSK                                                          0x2
#define HWIO_GCC_GPLL5_USER_CTL_PLLOUT_EVEN_SHFT                                                          0x1
#define HWIO_GCC_GPLL5_USER_CTL_PLLOUT_MAIN_BMSK                                                          0x1
#define HWIO_GCC_GPLL5_USER_CTL_PLLOUT_MAIN_SHFT                                                          0x0

#define HWIO_GCC_GPLL5_USER_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00074010)
#define HWIO_GCC_GPLL5_USER_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL5_USER_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL5_USER_CTL_U_ADDR)
#define HWIO_GCC_GPLL5_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_USER_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL5_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_USER_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL5_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_USER_CTL_U_ADDR,m,v,HWIO_GCC_GPLL5_USER_CTL_U_IN)
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT63_BMSK                                               0x80000000
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT63_SHFT                                                     0x1f
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT62_BMSK                                               0x40000000
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT62_SHFT                                                     0x1e
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT61_BMSK                                               0x20000000
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT61_SHFT                                                     0x1d
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT60_BMSK                                               0x10000000
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT60_SHFT                                                     0x1c
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT59_BMSK                                                0x8000000
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT59_SHFT                                                     0x1b
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT58_BMSK                                                0x4000000
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT58_SHFT                                                     0x1a
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT57_BMSK                                                0x2000000
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT57_SHFT                                                     0x19
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT56_BMSK                                                0x1000000
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT56_SHFT                                                     0x18
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT55_BMSK                                                 0x800000
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT55_SHFT                                                     0x17
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT54_BMSK                                                 0x400000
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT54_SHFT                                                     0x16
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT53_BMSK                                                 0x200000
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT53_SHFT                                                     0x15
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT52_BMSK                                                 0x100000
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT52_SHFT                                                     0x14
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT51_BMSK                                                  0x80000
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT51_SHFT                                                     0x13
#define HWIO_GCC_GPLL5_USER_CTL_U_LOCK_DETECTOR_SELECTION_BMSK                                        0x40000
#define HWIO_GCC_GPLL5_USER_CTL_U_LOCK_DETECTOR_SELECTION_SHFT                                           0x12
#define HWIO_GCC_GPLL5_USER_CTL_U_TYPE_2_MODE_SELECTION_BMSK                                          0x20000
#define HWIO_GCC_GPLL5_USER_CTL_U_TYPE_2_MODE_SELECTION_SHFT                                             0x11
#define HWIO_GCC_GPLL5_USER_CTL_U_BANG_BANG_MODE_SELECTION_BMSK                                       0x10000
#define HWIO_GCC_GPLL5_USER_CTL_U_BANG_BANG_MODE_SELECTION_SHFT                                          0x10
#define HWIO_GCC_GPLL5_USER_CTL_U_FRAC_FORMAT_SEL_BMSK                                                 0x8000
#define HWIO_GCC_GPLL5_USER_CTL_U_FRAC_FORMAT_SEL_SHFT                                                    0xf
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT46_BMSK                                                   0x4000
#define HWIO_GCC_GPLL5_USER_CTL_U_RESERVE_BIT46_SHFT                                                      0xe
#define HWIO_GCC_GPLL5_USER_CTL_U_REF_CLK_AT_OUT_BMSK                                                  0x2000
#define HWIO_GCC_GPLL5_USER_CTL_U_REF_CLK_AT_OUT_SHFT                                                     0xd
#define HWIO_GCC_GPLL5_USER_CTL_U_SCALE_FREQ_ON_RESTART_BMSK                                           0x1800
#define HWIO_GCC_GPLL5_USER_CTL_U_SCALE_FREQ_ON_RESTART_SHFT                                              0xb
#define HWIO_GCC_GPLL5_USER_CTL_U_LATCH_INTERFACE_BYPASS_BMSK                                           0x400
#define HWIO_GCC_GPLL5_USER_CTL_U_LATCH_INTERFACE_BYPASS_SHFT                                             0xa
#define HWIO_GCC_GPLL5_USER_CTL_U_STATUS_REGISTER_BMSK                                                  0x3e0
#define HWIO_GCC_GPLL5_USER_CTL_U_STATUS_REGISTER_SHFT                                                    0x5
#define HWIO_GCC_GPLL5_USER_CTL_U_WRITE_STATE_EN_BMSK                                                    0x10
#define HWIO_GCC_GPLL5_USER_CTL_U_WRITE_STATE_EN_SHFT                                                     0x4
#define HWIO_GCC_GPLL5_USER_CTL_U_CALIB_CTRL_BMSK                                                         0xe
#define HWIO_GCC_GPLL5_USER_CTL_U_CALIB_CTRL_SHFT                                                         0x1
#define HWIO_GCC_GPLL5_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_BMSK                                             0x1
#define HWIO_GCC_GPLL5_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_SHFT                                             0x0

#define HWIO_GCC_GPLL5_USER_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00074014)
#define HWIO_GCC_GPLL5_USER_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL5_USER_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL5_USER_CTL_U1_ADDR)
#define HWIO_GCC_GPLL5_USER_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_USER_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL5_USER_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_USER_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL5_USER_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_USER_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL5_USER_CTL_U1_IN)
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT93_BMSK                                              0x20000000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT93_SHFT                                                    0x1d
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT92_BMSK                                              0x10000000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT92_SHFT                                                    0x1c
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT86_BMSK                                                0x400000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT86_SHFT                                                    0x16
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT82_BMSK                                                 0x40000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT82_SHFT                                                    0x12
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT81_BMSK                                                 0x20000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT81_SHFT                                                    0x11
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT80_BMSK                                                 0x10000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT80_SHFT                                                    0x10
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT79_BMSK                                                  0x8000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT79_SHFT                                                     0xf
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT78_BMSK                                                  0x4000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT78_SHFT                                                     0xe
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT77_BMSK                                                  0x2000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT77_SHFT                                                     0xd
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT71_BMSK                                                    0x80
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT71_SHFT                                                     0x7
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT70_BMSK                                                    0x40
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT70_SHFT                                                     0x6
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT69_BMSK                                                    0x20
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT69_SHFT                                                     0x5
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT65_BMSK                                                     0x2
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT65_SHFT                                                     0x1
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT64_BMSK                                                     0x1
#define HWIO_GCC_GPLL5_USER_CTL_U1_RESERVE_BIT64_SHFT                                                     0x0

#define HWIO_GCC_GPLL5_CONFIG_CTL_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00074018)
#define HWIO_GCC_GPLL5_CONFIG_CTL_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL5_CONFIG_CTL_IN          \
        in_dword(HWIO_GCC_GPLL5_CONFIG_CTL_ADDR)
#define HWIO_GCC_GPLL5_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_CONFIG_CTL_ADDR, m)
#define HWIO_GCC_GPLL5_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_CONFIG_CTL_ADDR,v)
#define HWIO_GCC_GPLL5_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_CONFIG_CTL_ADDR,m,v,HWIO_GCC_GPLL5_CONFIG_CTL_IN)
#define HWIO_GCC_GPLL5_CONFIG_CTL_FINE_LDC_THRESHOLD_BMSK                                          0xfc000000
#define HWIO_GCC_GPLL5_CONFIG_CTL_FINE_LDC_THRESHOLD_SHFT                                                0x1a
#define HWIO_GCC_GPLL5_CONFIG_CTL_COARSE_LDC_THRESHOLD_BMSK                                         0x3c00000
#define HWIO_GCC_GPLL5_CONFIG_CTL_COARSE_LDC_THRESHOLD_SHFT                                              0x16
#define HWIO_GCC_GPLL5_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_BMSK                                 0x3c0000
#define HWIO_GCC_GPLL5_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_SHFT                                     0x12
#define HWIO_GCC_GPLL5_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_BMSK                                  0x3c000
#define HWIO_GCC_GPLL5_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_SHFT                                      0xe
#define HWIO_GCC_GPLL5_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_BMSK                                         0x3800
#define HWIO_GCC_GPLL5_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_SHFT                                            0xb
#define HWIO_GCC_GPLL5_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_BMSK                                        0x700
#define HWIO_GCC_GPLL5_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_SHFT                                          0x8
#define HWIO_GCC_GPLL5_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_BMSK                                              0xf0
#define HWIO_GCC_GPLL5_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_SHFT                                               0x4
#define HWIO_GCC_GPLL5_CONFIG_CTL_FWD_GAIN_KFN_BMSK                                                       0xf
#define HWIO_GCC_GPLL5_CONFIG_CTL_FWD_GAIN_KFN_SHFT                                                       0x0

#define HWIO_GCC_GPLL5_CONFIG_CTL_U_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0007401c)
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_RMSK                                                           0xffffffff
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL5_CONFIG_CTL_U_ADDR)
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_CONFIG_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_CONFIG_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_CONFIG_CTL_U_ADDR,m,v,HWIO_GCC_GPLL5_CONFIG_CTL_U_IN)
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_BIST_CFG_BMSK                                                  0xffff0000
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_BIST_CFG_SHFT                                                        0x10
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_BMSK                                       0xc000
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_SHFT                                          0xe
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_OSC_SETTLING_TIME_BMSK                                             0x3000
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_OSC_SETTLING_TIME_SHFT                                                0xc
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_BMSK                                            0xc00
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_SHFT                                              0xa
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_CASC_CURRENT_CTL_B_BMSK                                             0x380
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_CASC_CURRENT_CTL_B_SHFT                                               0x7
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_BMSK                                     0x40
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_SHFT                                      0x6
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_BMSK                                            0x30
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_SHFT                                             0x4
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_LDET_THRESH_SCALE_BMSK                                                0x8
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_LDET_THRESH_SCALE_SHFT                                                0x3
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_DCO_STARTUP_CONFIG_BMSK                                               0x6
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_DCO_STARTUP_CONFIG_SHFT                                               0x1
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_BMSK                                          0x1
#define HWIO_GCC_GPLL5_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_SHFT                                          0x0

#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00074020)
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_RMSK                                                          0xffffffff
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL5_CONFIG_CTL_U1_ADDR)
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_CONFIG_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_CONFIG_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_CONFIG_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL5_CONFIG_CTL_U1_IN)
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BB_CAL_THRESHOLD_BMSK                                         0xc0000000
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BB_CAL_THRESHOLD_SHFT                                               0x1e
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_PCODE_OFFSET_BMSK                                             0x38000000
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_PCODE_OFFSET_SHFT                                                   0x1b
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_COUNTER_BLANK_BMSK                                             0x4000000
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_COUNTER_BLANK_SHFT                                                  0x1a
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BB_RESYNC_EDGE_BMSK                                            0x2000000
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BB_RESYNC_EDGE_SHFT                                                 0x19
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BB_RESYNC_SEL_BMSK                                             0x1000000
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BB_RESYNC_SEL_SHFT                                                  0x18
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_BMSK                                        0xc00000
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_SHFT                                            0x16
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BB_LOCK_THRESH_BMSK                                             0x380000
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BB_LOCK_THRESH_SHFT                                                 0x13
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_RESERVE_BIT82_BMSK                                               0x40000
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_RESERVE_BIT82_SHFT                                                  0x12
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_BMSK                                          0x30000
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_SHFT                                             0x10
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_BMSK                                            0xc000
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_SHFT                                               0xe
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BB_CAL_EN_BMSK                                                    0x2000
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BB_CAL_EN_SHFT                                                       0xd
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_BMSK                                      0x1800
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_SHFT                                         0xb
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BBMODE_INT_GAIN_BMSK                                               0x780
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BBMODE_INT_GAIN_SHFT                                                 0x7
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BBMODE_PROP_GAIN_BMSK                                               0x78
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_BBMODE_PROP_GAIN_SHFT                                                0x3
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_TDC_SELECTION_BMSK                                                   0x4
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_TDC_SELECTION_SHFT                                                   0x2
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_RESERVE_BIT65_BMSK                                                   0x2
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_RESERVE_BIT65_SHFT                                                   0x1
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_FORCE_DSM_ON_BMSK                                                    0x1
#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_FORCE_DSM_ON_SHFT                                                    0x0

#define HWIO_GCC_GPLL5_TEST_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00074024)
#define HWIO_GCC_GPLL5_TEST_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL5_TEST_CTL_IN          \
        in_dword(HWIO_GCC_GPLL5_TEST_CTL_ADDR)
#define HWIO_GCC_GPLL5_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_TEST_CTL_ADDR, m)
#define HWIO_GCC_GPLL5_TEST_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_TEST_CTL_ADDR,v)
#define HWIO_GCC_GPLL5_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_TEST_CTL_ADDR,m,v,HWIO_GCC_GPLL5_TEST_CTL_IN)
#define HWIO_GCC_GPLL5_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_BMSK                                       0xc0000000
#define HWIO_GCC_GPLL5_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_SHFT                                             0x1e
#define HWIO_GCC_GPLL5_TEST_CTL_BYPASS_FIRST_ORDER_DSM_BMSK                                        0x20000000
#define HWIO_GCC_GPLL5_TEST_CTL_BYPASS_FIRST_ORDER_DSM_SHFT                                              0x1d
#define HWIO_GCC_GPLL5_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_BMSK                                   0x18000000
#define HWIO_GCC_GPLL5_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_SHFT                                         0x1b
#define HWIO_GCC_GPLL5_TEST_CTL_GLITCH_PREVENTION_DIS_BMSK                                          0x4000000
#define HWIO_GCC_GPLL5_TEST_CTL_GLITCH_PREVENTION_DIS_SHFT                                               0x1a
#define HWIO_GCC_GPLL5_TEST_CTL_ATEST_ISCALE_BMSK                                                   0x3000000
#define HWIO_GCC_GPLL5_TEST_CTL_ATEST_ISCALE_SHFT                                                        0x18
#define HWIO_GCC_GPLL5_TEST_CTL_PLL_TEST_OUT_SEL_BMSK                                                0xf00000
#define HWIO_GCC_GPLL5_TEST_CTL_PLL_TEST_OUT_SEL_SHFT                                                    0x14
#define HWIO_GCC_GPLL5_TEST_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL5_TEST_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL5_TEST_CTL_DIV2_NMO_EN_BMSK                                                      0x40000
#define HWIO_GCC_GPLL5_TEST_CTL_DIV2_NMO_EN_SHFT                                                         0x12
#define HWIO_GCC_GPLL5_TEST_CTL_NMO_OSC_SEL_BMSK                                                      0x30000
#define HWIO_GCC_GPLL5_TEST_CTL_NMO_OSC_SEL_SHFT                                                         0x10
#define HWIO_GCC_GPLL5_TEST_CTL_NOISE_MAG_BMSK                                                         0xe000
#define HWIO_GCC_GPLL5_TEST_CTL_NOISE_MAG_SHFT                                                            0xd
#define HWIO_GCC_GPLL5_TEST_CTL_NOISE_GEN_EN_BMSK                                                      0x1000
#define HWIO_GCC_GPLL5_TEST_CTL_NOISE_GEN_EN_SHFT                                                         0xc
#define HWIO_GCC_GPLL5_TEST_CTL_DISABLE_DCAPS_BMSK                                                      0x800
#define HWIO_GCC_GPLL5_TEST_CTL_DISABLE_DCAPS_SHFT                                                        0xb
#define HWIO_GCC_GPLL5_TEST_CTL_RESERVE_BIT10_BMSK                                                      0x400
#define HWIO_GCC_GPLL5_TEST_CTL_RESERVE_BIT10_SHFT                                                        0xa
#define HWIO_GCC_GPLL5_TEST_CTL_RESERVE_BIT9_BMSK                                                       0x200
#define HWIO_GCC_GPLL5_TEST_CTL_RESERVE_BIT9_SHFT                                                         0x9
#define HWIO_GCC_GPLL5_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_BMSK                                            0x100
#define HWIO_GCC_GPLL5_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_SHFT                                              0x8
#define HWIO_GCC_GPLL5_TEST_CTL_EN_VDD_TEST_BMSK                                                         0x80
#define HWIO_GCC_GPLL5_TEST_CTL_EN_VDD_TEST_SHFT                                                          0x7
#define HWIO_GCC_GPLL5_TEST_CTL_EN_VREG_TEST_BMSK                                                        0x40
#define HWIO_GCC_GPLL5_TEST_CTL_EN_VREG_TEST_SHFT                                                         0x6
#define HWIO_GCC_GPLL5_TEST_CTL_EN_VREF_TEST_BMSK                                                        0x20
#define HWIO_GCC_GPLL5_TEST_CTL_EN_VREF_TEST_SHFT                                                         0x5
#define HWIO_GCC_GPLL5_TEST_CTL_EN_VDCO_TEST_BMSK                                                        0x10
#define HWIO_GCC_GPLL5_TEST_CTL_EN_VDCO_TEST_SHFT                                                         0x4
#define HWIO_GCC_GPLL5_TEST_CTL_BYPASS_ATEST_BUFFER_BMSK                                                  0x8
#define HWIO_GCC_GPLL5_TEST_CTL_BYPASS_ATEST_BUFFER_SHFT                                                  0x3
#define HWIO_GCC_GPLL5_TEST_CTL_EN_IVCO_TEST_BMSK                                                         0x4
#define HWIO_GCC_GPLL5_TEST_CTL_EN_IVCO_TEST_SHFT                                                         0x2
#define HWIO_GCC_GPLL5_TEST_CTL_ATEST1_EN_BMSK                                                            0x2
#define HWIO_GCC_GPLL5_TEST_CTL_ATEST1_EN_SHFT                                                            0x1
#define HWIO_GCC_GPLL5_TEST_CTL_ATEST0_EN_BMSK                                                            0x1
#define HWIO_GCC_GPLL5_TEST_CTL_ATEST0_EN_SHFT                                                            0x0

#define HWIO_GCC_GPLL5_TEST_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00074028)
#define HWIO_GCC_GPLL5_TEST_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL5_TEST_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL5_TEST_CTL_U_ADDR)
#define HWIO_GCC_GPLL5_TEST_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_TEST_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL5_TEST_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_TEST_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL5_TEST_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_TEST_CTL_U_ADDR,m,v,HWIO_GCC_GPLL5_TEST_CTL_U_IN)
#define HWIO_GCC_GPLL5_TEST_CTL_U_CASC_DAC_FCW_LSBS_BMSK                                           0xe0000000
#define HWIO_GCC_GPLL5_TEST_CTL_U_CASC_DAC_FCW_LSBS_SHFT                                                 0x1d
#define HWIO_GCC_GPLL5_TEST_CTL_U_OVERRIDE_CASC_DAC_BMSK                                           0x10000000
#define HWIO_GCC_GPLL5_TEST_CTL_U_OVERRIDE_CASC_DAC_SHFT                                                 0x1c
#define HWIO_GCC_GPLL5_TEST_CTL_U_COMP_COARSE_FCW_BMSK                                              0xe000000
#define HWIO_GCC_GPLL5_TEST_CTL_U_COMP_COARSE_FCW_SHFT                                                   0x19
#define HWIO_GCC_GPLL5_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_BMSK                                     0x1800000
#define HWIO_GCC_GPLL5_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_SHFT                                          0x17
#define HWIO_GCC_GPLL5_TEST_CTL_U_FINE_FCW_BMSK                                                      0x7e0000
#define HWIO_GCC_GPLL5_TEST_CTL_U_FINE_FCW_SHFT                                                          0x11
#define HWIO_GCC_GPLL5_TEST_CTL_U_OVERRIDE_FINE_FCW_BMSK                                              0x10000
#define HWIO_GCC_GPLL5_TEST_CTL_U_OVERRIDE_FINE_FCW_SHFT                                                 0x10
#define HWIO_GCC_GPLL5_TEST_CTL_U_REG_COARSE_FCW_BMSK                                                  0xfe00
#define HWIO_GCC_GPLL5_TEST_CTL_U_REG_COARSE_FCW_SHFT                                                     0x9
#define HWIO_GCC_GPLL5_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_BMSK                                          0x100
#define HWIO_GCC_GPLL5_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_SHFT                                            0x8
#define HWIO_GCC_GPLL5_TEST_CTL_U_PROCESS_CALIB_WORD_BMSK                                                0xe0
#define HWIO_GCC_GPLL5_TEST_CTL_U_PROCESS_CALIB_WORD_SHFT                                                 0x5
#define HWIO_GCC_GPLL5_TEST_CTL_U_OVERRIDE_CALIB_WORD_BMSK                                               0x10
#define HWIO_GCC_GPLL5_TEST_CTL_U_OVERRIDE_CALIB_WORD_SHFT                                                0x4
#define HWIO_GCC_GPLL5_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_BMSK                                             0x8
#define HWIO_GCC_GPLL5_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_SHFT                                             0x3
#define HWIO_GCC_GPLL5_TEST_CTL_U_DISABLE_LFSR_BMSK                                                       0x4
#define HWIO_GCC_GPLL5_TEST_CTL_U_DISABLE_LFSR_SHFT                                                       0x2
#define HWIO_GCC_GPLL5_TEST_CTL_U_SKIP_FINE_TUNE_BMSK                                                     0x2
#define HWIO_GCC_GPLL5_TEST_CTL_U_SKIP_FINE_TUNE_SHFT                                                     0x1
#define HWIO_GCC_GPLL5_TEST_CTL_U_SKIP_FAST_LOCK_BMSK                                                     0x1
#define HWIO_GCC_GPLL5_TEST_CTL_U_SKIP_FAST_LOCK_SHFT                                                     0x0

#define HWIO_GCC_GPLL5_TEST_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0007402c)
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL5_TEST_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL5_TEST_CTL_U1_ADDR)
#define HWIO_GCC_GPLL5_TEST_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_TEST_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL5_TEST_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_TEST_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL5_TEST_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_TEST_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL5_TEST_CTL_U1_IN)
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL5_TEST_CTL_U1_FLL_COUNT_DISABLE_BMSK                                          0x20000000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_FLL_COUNT_DISABLE_SHFT                                                0x1d
#define HWIO_GCC_GPLL5_TEST_CTL_U1_FLL_COUNT_IN_DIV2_BMSK                                          0x10000000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_FLL_COUNT_IN_DIV2_SHFT                                                0x1c
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL5_TEST_CTL_U1_SILENCE_REF_OUTBUF_BMSK                                           0x400000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_SILENCE_REF_OUTBUF_SHFT                                               0x16
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL5_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_BMSK                                         0x40000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_SHFT                                            0x12
#define HWIO_GCC_GPLL5_TEST_CTL_U1_REF_CLK_SEL_BMSK                                                   0x20000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_REF_CLK_SEL_SHFT                                                      0x11
#define HWIO_GCC_GPLL5_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_BMSK                                     0x10000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_SHFT                                        0x10
#define HWIO_GCC_GPLL5_TEST_CTL_U1_DIS_AMP_STARTUP_BMSK                                                0x8000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_DIS_AMP_STARTUP_SHFT                                                   0xf
#define HWIO_GCC_GPLL5_TEST_CTL_U1_DISABLE_CLAMP_BMSK                                                  0x4000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_DISABLE_CLAMP_SHFT                                                     0xe
#define HWIO_GCC_GPLL5_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_BMSK                                        0x2000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_SHFT                                           0xd
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL5_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_BMSK                                          0x80
#define HWIO_GCC_GPLL5_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_SHFT                                           0x7
#define HWIO_GCC_GPLL5_TEST_CTL_U1_ENABLE_TRAINING_SEQ_BMSK                                              0x40
#define HWIO_GCC_GPLL5_TEST_CTL_U1_ENABLE_TRAINING_SEQ_SHFT                                               0x6
#define HWIO_GCC_GPLL5_TEST_CTL_U1_STATUS_REG_EN_BMSK                                                    0x20
#define HWIO_GCC_GPLL5_TEST_CTL_U1_STATUS_REG_EN_SHFT                                                     0x5
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL5_TEST_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL5_TEST_CTL_U1_CASC_DAC_FCW_MSBS_BMSK                                                 0x3
#define HWIO_GCC_GPLL5_TEST_CTL_U1_CASC_DAC_FCW_MSBS_SHFT                                                 0x0

#define HWIO_GCC_GPLL5_STATUS_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00074030)
#define HWIO_GCC_GPLL5_STATUS_RMSK                                                                 0xffffffff
#define HWIO_GCC_GPLL5_STATUS_IN          \
        in_dword(HWIO_GCC_GPLL5_STATUS_ADDR)
#define HWIO_GCC_GPLL5_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_STATUS_ADDR, m)
#define HWIO_GCC_GPLL5_STATUS_STATUS_31_0_BMSK                                                     0xffffffff
#define HWIO_GCC_GPLL5_STATUS_STATUS_31_0_SHFT                                                            0x0

#define HWIO_GCC_GPLL5_FREQ_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00074034)
#define HWIO_GCC_GPLL5_FREQ_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL5_FREQ_CTL_IN          \
        in_dword(HWIO_GCC_GPLL5_FREQ_CTL_ADDR)
#define HWIO_GCC_GPLL5_FREQ_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_FREQ_CTL_ADDR, m)
#define HWIO_GCC_GPLL5_FREQ_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_FREQ_CTL_ADDR,v)
#define HWIO_GCC_GPLL5_FREQ_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_FREQ_CTL_ADDR,m,v,HWIO_GCC_GPLL5_FREQ_CTL_IN)
#define HWIO_GCC_GPLL5_FREQ_CTL_FREQUENCY_CTL_WORD_BMSK                                            0xffffffff
#define HWIO_GCC_GPLL5_FREQ_CTL_FREQUENCY_CTL_WORD_SHFT                                                   0x0

#define HWIO_GCC_GPLL5_OPMODE_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00074038)
#define HWIO_GCC_GPLL5_OPMODE_RMSK                                                                        0x7
#define HWIO_GCC_GPLL5_OPMODE_IN          \
        in_dword(HWIO_GCC_GPLL5_OPMODE_ADDR)
#define HWIO_GCC_GPLL5_OPMODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_OPMODE_ADDR, m)
#define HWIO_GCC_GPLL5_OPMODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_OPMODE_ADDR,v)
#define HWIO_GCC_GPLL5_OPMODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_OPMODE_ADDR,m,v,HWIO_GCC_GPLL5_OPMODE_IN)
#define HWIO_GCC_GPLL5_OPMODE_PLL_OPMODE_BMSK                                                             0x7
#define HWIO_GCC_GPLL5_OPMODE_PLL_OPMODE_SHFT                                                             0x0

#define HWIO_GCC_GPLL5_STATE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0007403c)
#define HWIO_GCC_GPLL5_STATE_RMSK                                                                         0x7
#define HWIO_GCC_GPLL5_STATE_IN          \
        in_dword(HWIO_GCC_GPLL5_STATE_ADDR)
#define HWIO_GCC_GPLL5_STATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_STATE_ADDR, m)
#define HWIO_GCC_GPLL5_STATE_PLL_STATE_BMSK                                                               0x7
#define HWIO_GCC_GPLL5_STATE_PLL_STATE_SHFT                                                               0x0

#define HWIO_GCC_GPLL5_ALPHA_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00074040)
#define HWIO_GCC_GPLL5_ALPHA_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL5_ALPHA_VAL_IN          \
        in_dword(HWIO_GCC_GPLL5_ALPHA_VAL_ADDR)
#define HWIO_GCC_GPLL5_ALPHA_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_ALPHA_VAL_ADDR, m)
#define HWIO_GCC_GPLL5_ALPHA_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_ALPHA_VAL_ADDR,v)
#define HWIO_GCC_GPLL5_ALPHA_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_ALPHA_VAL_ADDR,m,v,HWIO_GCC_GPLL5_ALPHA_VAL_IN)
#define HWIO_GCC_GPLL5_ALPHA_VAL_PLL_ALPHA_VAL_BMSK                                                    0xffff
#define HWIO_GCC_GPLL5_ALPHA_VAL_PLL_ALPHA_VAL_SHFT                                                       0x0

#define HWIO_GCC_GPLL5_SPARE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00074044)
#define HWIO_GCC_GPLL5_SPARE_RMSK                                                                        0xff
#define HWIO_GCC_GPLL5_SPARE_IN          \
        in_dword(HWIO_GCC_GPLL5_SPARE_ADDR)
#define HWIO_GCC_GPLL5_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_SPARE_ADDR, m)
#define HWIO_GCC_GPLL5_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_SPARE_ADDR,v)
#define HWIO_GCC_GPLL5_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_SPARE_ADDR,m,v,HWIO_GCC_GPLL5_SPARE_IN)
#define HWIO_GCC_GPLL5_SPARE_SPARE_OUTPUTS_BMSK                                                          0xf0
#define HWIO_GCC_GPLL5_SPARE_SPARE_OUTPUTS_SHFT                                                           0x4
#define HWIO_GCC_GPLL5_SPARE_SPARE_INPUTS_BMSK                                                            0xf
#define HWIO_GCC_GPLL5_SPARE_SPARE_INPUTS_SHFT                                                            0x0

#define HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00074048)
#define HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_RMSK                                                              0xff
#define HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_IN          \
        in_dword(HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_ADDR)
#define HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_ADDR, m)
#define HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_ADDR,v)
#define HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_ADDR,m,v,HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_IN)
#define HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_BMSK                                              0xff
#define HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_SHFT                                               0x0

#define HWIO_GCC_GPLL5_SSC_NUM_STEPS_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0007404c)
#define HWIO_GCC_GPLL5_SSC_NUM_STEPS_RMSK                                                                 0xf
#define HWIO_GCC_GPLL5_SSC_NUM_STEPS_IN          \
        in_dword(HWIO_GCC_GPLL5_SSC_NUM_STEPS_ADDR)
#define HWIO_GCC_GPLL5_SSC_NUM_STEPS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_SSC_NUM_STEPS_ADDR, m)
#define HWIO_GCC_GPLL5_SSC_NUM_STEPS_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_SSC_NUM_STEPS_ADDR,v)
#define HWIO_GCC_GPLL5_SSC_NUM_STEPS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_SSC_NUM_STEPS_ADDR,m,v,HWIO_GCC_GPLL5_SSC_NUM_STEPS_IN)
#define HWIO_GCC_GPLL5_SSC_NUM_STEPS_SSC_NUM_STEPS_BMSK                                                   0xf
#define HWIO_GCC_GPLL5_SSC_NUM_STEPS_SSC_NUM_STEPS_SHFT                                                   0x0

#define HWIO_GCC_GPLL5_SSC_UPDATE_RATE_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00074050)
#define HWIO_GCC_GPLL5_SSC_UPDATE_RATE_RMSK                                                               0xf
#define HWIO_GCC_GPLL5_SSC_UPDATE_RATE_IN          \
        in_dword(HWIO_GCC_GPLL5_SSC_UPDATE_RATE_ADDR)
#define HWIO_GCC_GPLL5_SSC_UPDATE_RATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL5_SSC_UPDATE_RATE_ADDR, m)
#define HWIO_GCC_GPLL5_SSC_UPDATE_RATE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL5_SSC_UPDATE_RATE_ADDR,v)
#define HWIO_GCC_GPLL5_SSC_UPDATE_RATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL5_SSC_UPDATE_RATE_ADDR,m,v,HWIO_GCC_GPLL5_SSC_UPDATE_RATE_IN)
#define HWIO_GCC_GPLL5_SSC_UPDATE_RATE_SSC_UPDATE_RATE_BMSK                                               0xf
#define HWIO_GCC_GPLL5_SSC_UPDATE_RATE_SSC_UPDATE_RATE_SHFT                                               0x0

#define HWIO_GCC_GPLL6_MODE_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00013000)
#define HWIO_GCC_GPLL6_MODE_RMSK                                                                   0xffffffff
#define HWIO_GCC_GPLL6_MODE_IN          \
        in_dword(HWIO_GCC_GPLL6_MODE_ADDR)
#define HWIO_GCC_GPLL6_MODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_MODE_ADDR, m)
#define HWIO_GCC_GPLL6_MODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_MODE_ADDR,v)
#define HWIO_GCC_GPLL6_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_MODE_ADDR,m,v,HWIO_GCC_GPLL6_MODE_IN)
#define HWIO_GCC_GPLL6_MODE_PLL_LOCK_DET_BMSK                                                      0x80000000
#define HWIO_GCC_GPLL6_MODE_PLL_LOCK_DET_SHFT                                                            0x1f
#define HWIO_GCC_GPLL6_MODE_PLL_ACTIVE_FLAG_BMSK                                                   0x40000000
#define HWIO_GCC_GPLL6_MODE_PLL_ACTIVE_FLAG_SHFT                                                         0x1e
#define HWIO_GCC_GPLL6_MODE_PLL_ACK_LATCH_BMSK                                                     0x20000000
#define HWIO_GCC_GPLL6_MODE_PLL_ACK_LATCH_SHFT                                                           0x1d
#define HWIO_GCC_GPLL6_MODE_PLL_LOCK_DET_FINE_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL6_MODE_PLL_LOCK_DET_FINE_SHFT                                                       0x1c
#define HWIO_GCC_GPLL6_MODE_PCAL_DONE_BMSK                                                          0x8000000
#define HWIO_GCC_GPLL6_MODE_PCAL_DONE_SHFT                                                               0x1b
#define HWIO_GCC_GPLL6_MODE_RESERVE_BITS26_25_BMSK                                                  0x6000000
#define HWIO_GCC_GPLL6_MODE_RESERVE_BITS26_25_SHFT                                                       0x19
#define HWIO_GCC_GPLL6_MODE_FSM_LEGACY_MODE_BMSK                                                    0x1000000
#define HWIO_GCC_GPLL6_MODE_FSM_LEGACY_MODE_SHFT                                                         0x18
#define HWIO_GCC_GPLL6_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_BMSK                                          0x800000
#define HWIO_GCC_GPLL6_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_SHFT                                              0x17
#define HWIO_GCC_GPLL6_MODE_PLL_UPDATE_BMSK                                                          0x400000
#define HWIO_GCC_GPLL6_MODE_PLL_UPDATE_SHFT                                                              0x16
#define HWIO_GCC_GPLL6_MODE_PLL_VOTE_FSM_RESET_BMSK                                                  0x200000
#define HWIO_GCC_GPLL6_MODE_PLL_VOTE_FSM_RESET_SHFT                                                      0x15
#define HWIO_GCC_GPLL6_MODE_PLL_VOTE_FSM_ENA_BMSK                                                    0x100000
#define HWIO_GCC_GPLL6_MODE_PLL_VOTE_FSM_ENA_SHFT                                                        0x14
#define HWIO_GCC_GPLL6_MODE_PLL_BIAS_COUNT_BMSK                                                       0xfc000
#define HWIO_GCC_GPLL6_MODE_PLL_BIAS_COUNT_SHFT                                                           0xe
#define HWIO_GCC_GPLL6_MODE_PLL_LOCK_COUNT_BMSK                                                        0x3f00
#define HWIO_GCC_GPLL6_MODE_PLL_LOCK_COUNT_SHFT                                                           0x8
#define HWIO_GCC_GPLL6_MODE_RESERVE_BIT7_BMSK                                                            0x80
#define HWIO_GCC_GPLL6_MODE_RESERVE_BIT7_SHFT                                                             0x7
#define HWIO_GCC_GPLL6_MODE_OUT_TEST_HW_CTL_BMSK                                                         0x40
#define HWIO_GCC_GPLL6_MODE_OUT_TEST_HW_CTL_SHFT                                                          0x6
#define HWIO_GCC_GPLL6_MODE_OUT_ODD_HW_CTL_BMSK                                                          0x20
#define HWIO_GCC_GPLL6_MODE_OUT_ODD_HW_CTL_SHFT                                                           0x5
#define HWIO_GCC_GPLL6_MODE_OUT_EVEN_HW_CTL_BMSK                                                         0x10
#define HWIO_GCC_GPLL6_MODE_OUT_EVEN_HW_CTL_SHFT                                                          0x4
#define HWIO_GCC_GPLL6_MODE_OUT_MAIN_HW_CTL_BMSK                                                          0x8
#define HWIO_GCC_GPLL6_MODE_OUT_MAIN_HW_CTL_SHFT                                                          0x3
#define HWIO_GCC_GPLL6_MODE_PLL_RESET_N_BMSK                                                              0x4
#define HWIO_GCC_GPLL6_MODE_PLL_RESET_N_SHFT                                                              0x2
#define HWIO_GCC_GPLL6_MODE_RESERVE_BIT1_BMSK                                                             0x2
#define HWIO_GCC_GPLL6_MODE_RESERVE_BIT1_SHFT                                                             0x1
#define HWIO_GCC_GPLL6_MODE_PLL_OUTCTRL_BMSK                                                              0x1
#define HWIO_GCC_GPLL6_MODE_PLL_OUTCTRL_SHFT                                                              0x0

#define HWIO_GCC_GPLL6_L_VAL_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00013004)
#define HWIO_GCC_GPLL6_L_VAL_RMSK                                                                      0xffff
#define HWIO_GCC_GPLL6_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL6_L_VAL_ADDR)
#define HWIO_GCC_GPLL6_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL6_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL6_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_L_VAL_ADDR,m,v,HWIO_GCC_GPLL6_L_VAL_IN)
#define HWIO_GCC_GPLL6_L_VAL_PLL_L_BMSK                                                                0xffff
#define HWIO_GCC_GPLL6_L_VAL_PLL_L_SHFT                                                                   0x0

#define HWIO_GCC_GPLL6_CAL_L_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00013008)
#define HWIO_GCC_GPLL6_CAL_L_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL6_CAL_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL6_CAL_L_VAL_ADDR)
#define HWIO_GCC_GPLL6_CAL_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_CAL_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL6_CAL_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_CAL_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL6_CAL_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_CAL_L_VAL_ADDR,m,v,HWIO_GCC_GPLL6_CAL_L_VAL_IN)
#define HWIO_GCC_GPLL6_CAL_L_VAL_PLL_CAL_L_BMSK                                                        0xffff
#define HWIO_GCC_GPLL6_CAL_L_VAL_PLL_CAL_L_SHFT                                                           0x0

#define HWIO_GCC_GPLL6_USER_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0001300c)
#define HWIO_GCC_GPLL6_USER_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL6_USER_CTL_IN          \
        in_dword(HWIO_GCC_GPLL6_USER_CTL_ADDR)
#define HWIO_GCC_GPLL6_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_USER_CTL_ADDR, m)
#define HWIO_GCC_GPLL6_USER_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_USER_CTL_ADDR,v)
#define HWIO_GCC_GPLL6_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_USER_CTL_ADDR,m,v,HWIO_GCC_GPLL6_USER_CTL_IN)
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT31_BMSK                                                 0x80000000
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT31_SHFT                                                       0x1f
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT30_BMSK                                                 0x40000000
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT30_SHFT                                                       0x1e
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT29_BMSK                                                 0x20000000
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT29_SHFT                                                       0x1d
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT28_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT28_SHFT                                                       0x1c
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT27_BMSK                                                  0x8000000
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT27_SHFT                                                       0x1b
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT26_BMSK                                                  0x4000000
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT26_SHFT                                                       0x1a
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT25_BMSK                                                  0x2000000
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT25_SHFT                                                       0x19
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT24_BMSK                                                  0x1000000
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT24_SHFT                                                       0x18
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT23_BMSK                                                   0x800000
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT23_SHFT                                                       0x17
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT22_BMSK                                                   0x400000
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT22_SHFT                                                       0x16
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT21_BMSK                                                   0x200000
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT21_SHFT                                                       0x15
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT20_BMSK                                                   0x100000
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT20_SHFT                                                       0x14
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL6_USER_CTL_PRE_DIV_RATIO_BMSK                                                    0x70000
#define HWIO_GCC_GPLL6_USER_CTL_PRE_DIV_RATIO_SHFT                                                       0x10
#define HWIO_GCC_GPLL6_USER_CTL_POST_DIV_RATIO_ODD_BMSK                                                0xf000
#define HWIO_GCC_GPLL6_USER_CTL_POST_DIV_RATIO_ODD_SHFT                                                   0xc
#define HWIO_GCC_GPLL6_USER_CTL_POST_DIV_RATIO_EVEN_BMSK                                                0xf00
#define HWIO_GCC_GPLL6_USER_CTL_POST_DIV_RATIO_EVEN_SHFT                                                  0x8
#define HWIO_GCC_GPLL6_USER_CTL_OUT_CLK_POLARITY_BMSK                                                    0x80
#define HWIO_GCC_GPLL6_USER_CTL_OUT_CLK_POLARITY_SHFT                                                     0x7
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT6_BMSK                                                        0x40
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT6_SHFT                                                         0x6
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT5_BMSK                                                        0x20
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT5_SHFT                                                         0x5
#define HWIO_GCC_GPLL6_USER_CTL_PLLOUT_TEST_BMSK                                                         0x10
#define HWIO_GCC_GPLL6_USER_CTL_PLLOUT_TEST_SHFT                                                          0x4
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT3_BMSK                                                         0x8
#define HWIO_GCC_GPLL6_USER_CTL_RESERVE_BIT3_SHFT                                                         0x3
#define HWIO_GCC_GPLL6_USER_CTL_PLLOUT_ODD_BMSK                                                           0x4
#define HWIO_GCC_GPLL6_USER_CTL_PLLOUT_ODD_SHFT                                                           0x2
#define HWIO_GCC_GPLL6_USER_CTL_PLLOUT_EVEN_BMSK                                                          0x2
#define HWIO_GCC_GPLL6_USER_CTL_PLLOUT_EVEN_SHFT                                                          0x1
#define HWIO_GCC_GPLL6_USER_CTL_PLLOUT_MAIN_BMSK                                                          0x1
#define HWIO_GCC_GPLL6_USER_CTL_PLLOUT_MAIN_SHFT                                                          0x0

#define HWIO_GCC_GPLL6_USER_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00013010)
#define HWIO_GCC_GPLL6_USER_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL6_USER_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL6_USER_CTL_U_ADDR)
#define HWIO_GCC_GPLL6_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_USER_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL6_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_USER_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL6_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_USER_CTL_U_ADDR,m,v,HWIO_GCC_GPLL6_USER_CTL_U_IN)
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT63_BMSK                                               0x80000000
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT63_SHFT                                                     0x1f
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT62_BMSK                                               0x40000000
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT62_SHFT                                                     0x1e
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT61_BMSK                                               0x20000000
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT61_SHFT                                                     0x1d
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT60_BMSK                                               0x10000000
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT60_SHFT                                                     0x1c
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT59_BMSK                                                0x8000000
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT59_SHFT                                                     0x1b
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT58_BMSK                                                0x4000000
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT58_SHFT                                                     0x1a
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT57_BMSK                                                0x2000000
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT57_SHFT                                                     0x19
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT56_BMSK                                                0x1000000
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT56_SHFT                                                     0x18
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT55_BMSK                                                 0x800000
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT55_SHFT                                                     0x17
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT54_BMSK                                                 0x400000
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT54_SHFT                                                     0x16
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT53_BMSK                                                 0x200000
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT53_SHFT                                                     0x15
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT52_BMSK                                                 0x100000
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT52_SHFT                                                     0x14
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT51_BMSK                                                  0x80000
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT51_SHFT                                                     0x13
#define HWIO_GCC_GPLL6_USER_CTL_U_LOCK_DETECTOR_SELECTION_BMSK                                        0x40000
#define HWIO_GCC_GPLL6_USER_CTL_U_LOCK_DETECTOR_SELECTION_SHFT                                           0x12
#define HWIO_GCC_GPLL6_USER_CTL_U_TYPE_2_MODE_SELECTION_BMSK                                          0x20000
#define HWIO_GCC_GPLL6_USER_CTL_U_TYPE_2_MODE_SELECTION_SHFT                                             0x11
#define HWIO_GCC_GPLL6_USER_CTL_U_BANG_BANG_MODE_SELECTION_BMSK                                       0x10000
#define HWIO_GCC_GPLL6_USER_CTL_U_BANG_BANG_MODE_SELECTION_SHFT                                          0x10
#define HWIO_GCC_GPLL6_USER_CTL_U_FRAC_FORMAT_SEL_BMSK                                                 0x8000
#define HWIO_GCC_GPLL6_USER_CTL_U_FRAC_FORMAT_SEL_SHFT                                                    0xf
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT46_BMSK                                                   0x4000
#define HWIO_GCC_GPLL6_USER_CTL_U_RESERVE_BIT46_SHFT                                                      0xe
#define HWIO_GCC_GPLL6_USER_CTL_U_REF_CLK_AT_OUT_BMSK                                                  0x2000
#define HWIO_GCC_GPLL6_USER_CTL_U_REF_CLK_AT_OUT_SHFT                                                     0xd
#define HWIO_GCC_GPLL6_USER_CTL_U_SCALE_FREQ_ON_RESTART_BMSK                                           0x1800
#define HWIO_GCC_GPLL6_USER_CTL_U_SCALE_FREQ_ON_RESTART_SHFT                                              0xb
#define HWIO_GCC_GPLL6_USER_CTL_U_LATCH_INTERFACE_BYPASS_BMSK                                           0x400
#define HWIO_GCC_GPLL6_USER_CTL_U_LATCH_INTERFACE_BYPASS_SHFT                                             0xa
#define HWIO_GCC_GPLL6_USER_CTL_U_STATUS_REGISTER_BMSK                                                  0x3e0
#define HWIO_GCC_GPLL6_USER_CTL_U_STATUS_REGISTER_SHFT                                                    0x5
#define HWIO_GCC_GPLL6_USER_CTL_U_WRITE_STATE_EN_BMSK                                                    0x10
#define HWIO_GCC_GPLL6_USER_CTL_U_WRITE_STATE_EN_SHFT                                                     0x4
#define HWIO_GCC_GPLL6_USER_CTL_U_CALIB_CTRL_BMSK                                                         0xe
#define HWIO_GCC_GPLL6_USER_CTL_U_CALIB_CTRL_SHFT                                                         0x1
#define HWIO_GCC_GPLL6_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_BMSK                                             0x1
#define HWIO_GCC_GPLL6_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_SHFT                                             0x0

#define HWIO_GCC_GPLL6_USER_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00013014)
#define HWIO_GCC_GPLL6_USER_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL6_USER_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL6_USER_CTL_U1_ADDR)
#define HWIO_GCC_GPLL6_USER_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_USER_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL6_USER_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_USER_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL6_USER_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_USER_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL6_USER_CTL_U1_IN)
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT93_BMSK                                              0x20000000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT93_SHFT                                                    0x1d
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT92_BMSK                                              0x10000000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT92_SHFT                                                    0x1c
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT86_BMSK                                                0x400000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT86_SHFT                                                    0x16
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT82_BMSK                                                 0x40000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT82_SHFT                                                    0x12
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT81_BMSK                                                 0x20000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT81_SHFT                                                    0x11
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT80_BMSK                                                 0x10000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT80_SHFT                                                    0x10
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT79_BMSK                                                  0x8000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT79_SHFT                                                     0xf
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT78_BMSK                                                  0x4000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT78_SHFT                                                     0xe
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT77_BMSK                                                  0x2000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT77_SHFT                                                     0xd
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT71_BMSK                                                    0x80
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT71_SHFT                                                     0x7
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT70_BMSK                                                    0x40
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT70_SHFT                                                     0x6
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT69_BMSK                                                    0x20
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT69_SHFT                                                     0x5
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT65_BMSK                                                     0x2
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT65_SHFT                                                     0x1
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT64_BMSK                                                     0x1
#define HWIO_GCC_GPLL6_USER_CTL_U1_RESERVE_BIT64_SHFT                                                     0x0

#define HWIO_GCC_GPLL6_CONFIG_CTL_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00013018)
#define HWIO_GCC_GPLL6_CONFIG_CTL_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL6_CONFIG_CTL_IN          \
        in_dword(HWIO_GCC_GPLL6_CONFIG_CTL_ADDR)
#define HWIO_GCC_GPLL6_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_CONFIG_CTL_ADDR, m)
#define HWIO_GCC_GPLL6_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_CONFIG_CTL_ADDR,v)
#define HWIO_GCC_GPLL6_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_CONFIG_CTL_ADDR,m,v,HWIO_GCC_GPLL6_CONFIG_CTL_IN)
#define HWIO_GCC_GPLL6_CONFIG_CTL_FINE_LDC_THRESHOLD_BMSK                                          0xfc000000
#define HWIO_GCC_GPLL6_CONFIG_CTL_FINE_LDC_THRESHOLD_SHFT                                                0x1a
#define HWIO_GCC_GPLL6_CONFIG_CTL_COARSE_LDC_THRESHOLD_BMSK                                         0x3c00000
#define HWIO_GCC_GPLL6_CONFIG_CTL_COARSE_LDC_THRESHOLD_SHFT                                              0x16
#define HWIO_GCC_GPLL6_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_BMSK                                 0x3c0000
#define HWIO_GCC_GPLL6_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_SHFT                                     0x12
#define HWIO_GCC_GPLL6_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_BMSK                                  0x3c000
#define HWIO_GCC_GPLL6_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_SHFT                                      0xe
#define HWIO_GCC_GPLL6_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_BMSK                                         0x3800
#define HWIO_GCC_GPLL6_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_SHFT                                            0xb
#define HWIO_GCC_GPLL6_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_BMSK                                        0x700
#define HWIO_GCC_GPLL6_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_SHFT                                          0x8
#define HWIO_GCC_GPLL6_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_BMSK                                              0xf0
#define HWIO_GCC_GPLL6_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_SHFT                                               0x4
#define HWIO_GCC_GPLL6_CONFIG_CTL_FWD_GAIN_KFN_BMSK                                                       0xf
#define HWIO_GCC_GPLL6_CONFIG_CTL_FWD_GAIN_KFN_SHFT                                                       0x0

#define HWIO_GCC_GPLL6_CONFIG_CTL_U_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0001301c)
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_RMSK                                                           0xffffffff
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL6_CONFIG_CTL_U_ADDR)
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_CONFIG_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_CONFIG_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_CONFIG_CTL_U_ADDR,m,v,HWIO_GCC_GPLL6_CONFIG_CTL_U_IN)
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_BIST_CFG_BMSK                                                  0xffff0000
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_BIST_CFG_SHFT                                                        0x10
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_BMSK                                       0xc000
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_SHFT                                          0xe
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_OSC_SETTLING_TIME_BMSK                                             0x3000
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_OSC_SETTLING_TIME_SHFT                                                0xc
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_BMSK                                            0xc00
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_SHFT                                              0xa
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_CASC_CURRENT_CTL_B_BMSK                                             0x380
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_CASC_CURRENT_CTL_B_SHFT                                               0x7
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_BMSK                                     0x40
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_SHFT                                      0x6
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_BMSK                                            0x30
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_SHFT                                             0x4
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_LDET_THRESH_SCALE_BMSK                                                0x8
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_LDET_THRESH_SCALE_SHFT                                                0x3
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_DCO_STARTUP_CONFIG_BMSK                                               0x6
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_DCO_STARTUP_CONFIG_SHFT                                               0x1
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_BMSK                                          0x1
#define HWIO_GCC_GPLL6_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_SHFT                                          0x0

#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00013020)
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_RMSK                                                          0xffffffff
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL6_CONFIG_CTL_U1_ADDR)
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_CONFIG_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_CONFIG_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_CONFIG_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL6_CONFIG_CTL_U1_IN)
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BB_CAL_THRESHOLD_BMSK                                         0xc0000000
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BB_CAL_THRESHOLD_SHFT                                               0x1e
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_PCODE_OFFSET_BMSK                                             0x38000000
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_PCODE_OFFSET_SHFT                                                   0x1b
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_COUNTER_BLANK_BMSK                                             0x4000000
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_COUNTER_BLANK_SHFT                                                  0x1a
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BB_RESYNC_EDGE_BMSK                                            0x2000000
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BB_RESYNC_EDGE_SHFT                                                 0x19
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BB_RESYNC_SEL_BMSK                                             0x1000000
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BB_RESYNC_SEL_SHFT                                                  0x18
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_BMSK                                        0xc00000
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_SHFT                                            0x16
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BB_LOCK_THRESH_BMSK                                             0x380000
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BB_LOCK_THRESH_SHFT                                                 0x13
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_RESERVE_BIT82_BMSK                                               0x40000
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_RESERVE_BIT82_SHFT                                                  0x12
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_BMSK                                          0x30000
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_SHFT                                             0x10
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_BMSK                                            0xc000
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_SHFT                                               0xe
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BB_CAL_EN_BMSK                                                    0x2000
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BB_CAL_EN_SHFT                                                       0xd
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_BMSK                                      0x1800
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_SHFT                                         0xb
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BBMODE_INT_GAIN_BMSK                                               0x780
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BBMODE_INT_GAIN_SHFT                                                 0x7
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BBMODE_PROP_GAIN_BMSK                                               0x78
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_BBMODE_PROP_GAIN_SHFT                                                0x3
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_TDC_SELECTION_BMSK                                                   0x4
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_TDC_SELECTION_SHFT                                                   0x2
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_RESERVE_BIT65_BMSK                                                   0x2
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_RESERVE_BIT65_SHFT                                                   0x1
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_FORCE_DSM_ON_BMSK                                                    0x1
#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_FORCE_DSM_ON_SHFT                                                    0x0

#define HWIO_GCC_GPLL6_TEST_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00013024)
#define HWIO_GCC_GPLL6_TEST_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL6_TEST_CTL_IN          \
        in_dword(HWIO_GCC_GPLL6_TEST_CTL_ADDR)
#define HWIO_GCC_GPLL6_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_TEST_CTL_ADDR, m)
#define HWIO_GCC_GPLL6_TEST_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_TEST_CTL_ADDR,v)
#define HWIO_GCC_GPLL6_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_TEST_CTL_ADDR,m,v,HWIO_GCC_GPLL6_TEST_CTL_IN)
#define HWIO_GCC_GPLL6_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_BMSK                                       0xc0000000
#define HWIO_GCC_GPLL6_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_SHFT                                             0x1e
#define HWIO_GCC_GPLL6_TEST_CTL_BYPASS_FIRST_ORDER_DSM_BMSK                                        0x20000000
#define HWIO_GCC_GPLL6_TEST_CTL_BYPASS_FIRST_ORDER_DSM_SHFT                                              0x1d
#define HWIO_GCC_GPLL6_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_BMSK                                   0x18000000
#define HWIO_GCC_GPLL6_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_SHFT                                         0x1b
#define HWIO_GCC_GPLL6_TEST_CTL_GLITCH_PREVENTION_DIS_BMSK                                          0x4000000
#define HWIO_GCC_GPLL6_TEST_CTL_GLITCH_PREVENTION_DIS_SHFT                                               0x1a
#define HWIO_GCC_GPLL6_TEST_CTL_ATEST_ISCALE_BMSK                                                   0x3000000
#define HWIO_GCC_GPLL6_TEST_CTL_ATEST_ISCALE_SHFT                                                        0x18
#define HWIO_GCC_GPLL6_TEST_CTL_PLL_TEST_OUT_SEL_BMSK                                                0xf00000
#define HWIO_GCC_GPLL6_TEST_CTL_PLL_TEST_OUT_SEL_SHFT                                                    0x14
#define HWIO_GCC_GPLL6_TEST_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL6_TEST_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL6_TEST_CTL_DIV2_NMO_EN_BMSK                                                      0x40000
#define HWIO_GCC_GPLL6_TEST_CTL_DIV2_NMO_EN_SHFT                                                         0x12
#define HWIO_GCC_GPLL6_TEST_CTL_NMO_OSC_SEL_BMSK                                                      0x30000
#define HWIO_GCC_GPLL6_TEST_CTL_NMO_OSC_SEL_SHFT                                                         0x10
#define HWIO_GCC_GPLL6_TEST_CTL_NOISE_MAG_BMSK                                                         0xe000
#define HWIO_GCC_GPLL6_TEST_CTL_NOISE_MAG_SHFT                                                            0xd
#define HWIO_GCC_GPLL6_TEST_CTL_NOISE_GEN_EN_BMSK                                                      0x1000
#define HWIO_GCC_GPLL6_TEST_CTL_NOISE_GEN_EN_SHFT                                                         0xc
#define HWIO_GCC_GPLL6_TEST_CTL_DISABLE_DCAPS_BMSK                                                      0x800
#define HWIO_GCC_GPLL6_TEST_CTL_DISABLE_DCAPS_SHFT                                                        0xb
#define HWIO_GCC_GPLL6_TEST_CTL_RESERVE_BIT10_BMSK                                                      0x400
#define HWIO_GCC_GPLL6_TEST_CTL_RESERVE_BIT10_SHFT                                                        0xa
#define HWIO_GCC_GPLL6_TEST_CTL_RESERVE_BIT9_BMSK                                                       0x200
#define HWIO_GCC_GPLL6_TEST_CTL_RESERVE_BIT9_SHFT                                                         0x9
#define HWIO_GCC_GPLL6_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_BMSK                                            0x100
#define HWIO_GCC_GPLL6_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_SHFT                                              0x8
#define HWIO_GCC_GPLL6_TEST_CTL_EN_VDD_TEST_BMSK                                                         0x80
#define HWIO_GCC_GPLL6_TEST_CTL_EN_VDD_TEST_SHFT                                                          0x7
#define HWIO_GCC_GPLL6_TEST_CTL_EN_VREG_TEST_BMSK                                                        0x40
#define HWIO_GCC_GPLL6_TEST_CTL_EN_VREG_TEST_SHFT                                                         0x6
#define HWIO_GCC_GPLL6_TEST_CTL_EN_VREF_TEST_BMSK                                                        0x20
#define HWIO_GCC_GPLL6_TEST_CTL_EN_VREF_TEST_SHFT                                                         0x5
#define HWIO_GCC_GPLL6_TEST_CTL_EN_VDCO_TEST_BMSK                                                        0x10
#define HWIO_GCC_GPLL6_TEST_CTL_EN_VDCO_TEST_SHFT                                                         0x4
#define HWIO_GCC_GPLL6_TEST_CTL_BYPASS_ATEST_BUFFER_BMSK                                                  0x8
#define HWIO_GCC_GPLL6_TEST_CTL_BYPASS_ATEST_BUFFER_SHFT                                                  0x3
#define HWIO_GCC_GPLL6_TEST_CTL_EN_IVCO_TEST_BMSK                                                         0x4
#define HWIO_GCC_GPLL6_TEST_CTL_EN_IVCO_TEST_SHFT                                                         0x2
#define HWIO_GCC_GPLL6_TEST_CTL_ATEST1_EN_BMSK                                                            0x2
#define HWIO_GCC_GPLL6_TEST_CTL_ATEST1_EN_SHFT                                                            0x1
#define HWIO_GCC_GPLL6_TEST_CTL_ATEST0_EN_BMSK                                                            0x1
#define HWIO_GCC_GPLL6_TEST_CTL_ATEST0_EN_SHFT                                                            0x0

#define HWIO_GCC_GPLL6_TEST_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00013028)
#define HWIO_GCC_GPLL6_TEST_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL6_TEST_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL6_TEST_CTL_U_ADDR)
#define HWIO_GCC_GPLL6_TEST_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_TEST_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL6_TEST_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_TEST_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL6_TEST_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_TEST_CTL_U_ADDR,m,v,HWIO_GCC_GPLL6_TEST_CTL_U_IN)
#define HWIO_GCC_GPLL6_TEST_CTL_U_CASC_DAC_FCW_LSBS_BMSK                                           0xe0000000
#define HWIO_GCC_GPLL6_TEST_CTL_U_CASC_DAC_FCW_LSBS_SHFT                                                 0x1d
#define HWIO_GCC_GPLL6_TEST_CTL_U_OVERRIDE_CASC_DAC_BMSK                                           0x10000000
#define HWIO_GCC_GPLL6_TEST_CTL_U_OVERRIDE_CASC_DAC_SHFT                                                 0x1c
#define HWIO_GCC_GPLL6_TEST_CTL_U_COMP_COARSE_FCW_BMSK                                              0xe000000
#define HWIO_GCC_GPLL6_TEST_CTL_U_COMP_COARSE_FCW_SHFT                                                   0x19
#define HWIO_GCC_GPLL6_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_BMSK                                     0x1800000
#define HWIO_GCC_GPLL6_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_SHFT                                          0x17
#define HWIO_GCC_GPLL6_TEST_CTL_U_FINE_FCW_BMSK                                                      0x7e0000
#define HWIO_GCC_GPLL6_TEST_CTL_U_FINE_FCW_SHFT                                                          0x11
#define HWIO_GCC_GPLL6_TEST_CTL_U_OVERRIDE_FINE_FCW_BMSK                                              0x10000
#define HWIO_GCC_GPLL6_TEST_CTL_U_OVERRIDE_FINE_FCW_SHFT                                                 0x10
#define HWIO_GCC_GPLL6_TEST_CTL_U_REG_COARSE_FCW_BMSK                                                  0xfe00
#define HWIO_GCC_GPLL6_TEST_CTL_U_REG_COARSE_FCW_SHFT                                                     0x9
#define HWIO_GCC_GPLL6_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_BMSK                                          0x100
#define HWIO_GCC_GPLL6_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_SHFT                                            0x8
#define HWIO_GCC_GPLL6_TEST_CTL_U_PROCESS_CALIB_WORD_BMSK                                                0xe0
#define HWIO_GCC_GPLL6_TEST_CTL_U_PROCESS_CALIB_WORD_SHFT                                                 0x5
#define HWIO_GCC_GPLL6_TEST_CTL_U_OVERRIDE_CALIB_WORD_BMSK                                               0x10
#define HWIO_GCC_GPLL6_TEST_CTL_U_OVERRIDE_CALIB_WORD_SHFT                                                0x4
#define HWIO_GCC_GPLL6_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_BMSK                                             0x8
#define HWIO_GCC_GPLL6_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_SHFT                                             0x3
#define HWIO_GCC_GPLL6_TEST_CTL_U_DISABLE_LFSR_BMSK                                                       0x4
#define HWIO_GCC_GPLL6_TEST_CTL_U_DISABLE_LFSR_SHFT                                                       0x2
#define HWIO_GCC_GPLL6_TEST_CTL_U_SKIP_FINE_TUNE_BMSK                                                     0x2
#define HWIO_GCC_GPLL6_TEST_CTL_U_SKIP_FINE_TUNE_SHFT                                                     0x1
#define HWIO_GCC_GPLL6_TEST_CTL_U_SKIP_FAST_LOCK_BMSK                                                     0x1
#define HWIO_GCC_GPLL6_TEST_CTL_U_SKIP_FAST_LOCK_SHFT                                                     0x0

#define HWIO_GCC_GPLL6_TEST_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0001302c)
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL6_TEST_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL6_TEST_CTL_U1_ADDR)
#define HWIO_GCC_GPLL6_TEST_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_TEST_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL6_TEST_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_TEST_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL6_TEST_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_TEST_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL6_TEST_CTL_U1_IN)
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL6_TEST_CTL_U1_FLL_COUNT_DISABLE_BMSK                                          0x20000000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_FLL_COUNT_DISABLE_SHFT                                                0x1d
#define HWIO_GCC_GPLL6_TEST_CTL_U1_FLL_COUNT_IN_DIV2_BMSK                                          0x10000000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_FLL_COUNT_IN_DIV2_SHFT                                                0x1c
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL6_TEST_CTL_U1_SILENCE_REF_OUTBUF_BMSK                                           0x400000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_SILENCE_REF_OUTBUF_SHFT                                               0x16
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL6_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_BMSK                                         0x40000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_SHFT                                            0x12
#define HWIO_GCC_GPLL6_TEST_CTL_U1_REF_CLK_SEL_BMSK                                                   0x20000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_REF_CLK_SEL_SHFT                                                      0x11
#define HWIO_GCC_GPLL6_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_BMSK                                     0x10000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_SHFT                                        0x10
#define HWIO_GCC_GPLL6_TEST_CTL_U1_DIS_AMP_STARTUP_BMSK                                                0x8000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_DIS_AMP_STARTUP_SHFT                                                   0xf
#define HWIO_GCC_GPLL6_TEST_CTL_U1_DISABLE_CLAMP_BMSK                                                  0x4000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_DISABLE_CLAMP_SHFT                                                     0xe
#define HWIO_GCC_GPLL6_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_BMSK                                        0x2000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_SHFT                                           0xd
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL6_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_BMSK                                          0x80
#define HWIO_GCC_GPLL6_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_SHFT                                           0x7
#define HWIO_GCC_GPLL6_TEST_CTL_U1_ENABLE_TRAINING_SEQ_BMSK                                              0x40
#define HWIO_GCC_GPLL6_TEST_CTL_U1_ENABLE_TRAINING_SEQ_SHFT                                               0x6
#define HWIO_GCC_GPLL6_TEST_CTL_U1_STATUS_REG_EN_BMSK                                                    0x20
#define HWIO_GCC_GPLL6_TEST_CTL_U1_STATUS_REG_EN_SHFT                                                     0x5
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL6_TEST_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL6_TEST_CTL_U1_CASC_DAC_FCW_MSBS_BMSK                                                 0x3
#define HWIO_GCC_GPLL6_TEST_CTL_U1_CASC_DAC_FCW_MSBS_SHFT                                                 0x0

#define HWIO_GCC_GPLL6_STATUS_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00013030)
#define HWIO_GCC_GPLL6_STATUS_RMSK                                                                 0xffffffff
#define HWIO_GCC_GPLL6_STATUS_IN          \
        in_dword(HWIO_GCC_GPLL6_STATUS_ADDR)
#define HWIO_GCC_GPLL6_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_STATUS_ADDR, m)
#define HWIO_GCC_GPLL6_STATUS_STATUS_31_0_BMSK                                                     0xffffffff
#define HWIO_GCC_GPLL6_STATUS_STATUS_31_0_SHFT                                                            0x0

#define HWIO_GCC_GPLL6_FREQ_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00013034)
#define HWIO_GCC_GPLL6_FREQ_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL6_FREQ_CTL_IN          \
        in_dword(HWIO_GCC_GPLL6_FREQ_CTL_ADDR)
#define HWIO_GCC_GPLL6_FREQ_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_FREQ_CTL_ADDR, m)
#define HWIO_GCC_GPLL6_FREQ_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_FREQ_CTL_ADDR,v)
#define HWIO_GCC_GPLL6_FREQ_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_FREQ_CTL_ADDR,m,v,HWIO_GCC_GPLL6_FREQ_CTL_IN)
#define HWIO_GCC_GPLL6_FREQ_CTL_FREQUENCY_CTL_WORD_BMSK                                            0xffffffff
#define HWIO_GCC_GPLL6_FREQ_CTL_FREQUENCY_CTL_WORD_SHFT                                                   0x0

#define HWIO_GCC_GPLL6_OPMODE_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00013038)
#define HWIO_GCC_GPLL6_OPMODE_RMSK                                                                        0x7
#define HWIO_GCC_GPLL6_OPMODE_IN          \
        in_dword(HWIO_GCC_GPLL6_OPMODE_ADDR)
#define HWIO_GCC_GPLL6_OPMODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_OPMODE_ADDR, m)
#define HWIO_GCC_GPLL6_OPMODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_OPMODE_ADDR,v)
#define HWIO_GCC_GPLL6_OPMODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_OPMODE_ADDR,m,v,HWIO_GCC_GPLL6_OPMODE_IN)
#define HWIO_GCC_GPLL6_OPMODE_PLL_OPMODE_BMSK                                                             0x7
#define HWIO_GCC_GPLL6_OPMODE_PLL_OPMODE_SHFT                                                             0x0

#define HWIO_GCC_GPLL6_STATE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001303c)
#define HWIO_GCC_GPLL6_STATE_RMSK                                                                         0x7
#define HWIO_GCC_GPLL6_STATE_IN          \
        in_dword(HWIO_GCC_GPLL6_STATE_ADDR)
#define HWIO_GCC_GPLL6_STATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_STATE_ADDR, m)
#define HWIO_GCC_GPLL6_STATE_PLL_STATE_BMSK                                                               0x7
#define HWIO_GCC_GPLL6_STATE_PLL_STATE_SHFT                                                               0x0

#define HWIO_GCC_GPLL6_ALPHA_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00013040)
#define HWIO_GCC_GPLL6_ALPHA_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL6_ALPHA_VAL_IN          \
        in_dword(HWIO_GCC_GPLL6_ALPHA_VAL_ADDR)
#define HWIO_GCC_GPLL6_ALPHA_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_ALPHA_VAL_ADDR, m)
#define HWIO_GCC_GPLL6_ALPHA_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_ALPHA_VAL_ADDR,v)
#define HWIO_GCC_GPLL6_ALPHA_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_ALPHA_VAL_ADDR,m,v,HWIO_GCC_GPLL6_ALPHA_VAL_IN)
#define HWIO_GCC_GPLL6_ALPHA_VAL_PLL_ALPHA_VAL_BMSK                                                    0xffff
#define HWIO_GCC_GPLL6_ALPHA_VAL_PLL_ALPHA_VAL_SHFT                                                       0x0

#define HWIO_GCC_GPLL6_SPARE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00013044)
#define HWIO_GCC_GPLL6_SPARE_RMSK                                                                        0xff
#define HWIO_GCC_GPLL6_SPARE_IN          \
        in_dword(HWIO_GCC_GPLL6_SPARE_ADDR)
#define HWIO_GCC_GPLL6_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_SPARE_ADDR, m)
#define HWIO_GCC_GPLL6_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_SPARE_ADDR,v)
#define HWIO_GCC_GPLL6_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_SPARE_ADDR,m,v,HWIO_GCC_GPLL6_SPARE_IN)
#define HWIO_GCC_GPLL6_SPARE_SPARE_OUTPUTS_BMSK                                                          0xf0
#define HWIO_GCC_GPLL6_SPARE_SPARE_OUTPUTS_SHFT                                                           0x4
#define HWIO_GCC_GPLL6_SPARE_SPARE_INPUTS_BMSK                                                            0xf
#define HWIO_GCC_GPLL6_SPARE_SPARE_INPUTS_SHFT                                                            0x0

#define HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00013048)
#define HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_RMSK                                                              0xff
#define HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_IN          \
        in_dword(HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_ADDR)
#define HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_ADDR, m)
#define HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_ADDR,v)
#define HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_ADDR,m,v,HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_IN)
#define HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_BMSK                                              0xff
#define HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_SHFT                                               0x0

#define HWIO_GCC_GPLL6_SSC_NUM_STEPS_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001304c)
#define HWIO_GCC_GPLL6_SSC_NUM_STEPS_RMSK                                                                 0xf
#define HWIO_GCC_GPLL6_SSC_NUM_STEPS_IN          \
        in_dword(HWIO_GCC_GPLL6_SSC_NUM_STEPS_ADDR)
#define HWIO_GCC_GPLL6_SSC_NUM_STEPS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_SSC_NUM_STEPS_ADDR, m)
#define HWIO_GCC_GPLL6_SSC_NUM_STEPS_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_SSC_NUM_STEPS_ADDR,v)
#define HWIO_GCC_GPLL6_SSC_NUM_STEPS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_SSC_NUM_STEPS_ADDR,m,v,HWIO_GCC_GPLL6_SSC_NUM_STEPS_IN)
#define HWIO_GCC_GPLL6_SSC_NUM_STEPS_SSC_NUM_STEPS_BMSK                                                   0xf
#define HWIO_GCC_GPLL6_SSC_NUM_STEPS_SSC_NUM_STEPS_SHFT                                                   0x0

#define HWIO_GCC_GPLL6_SSC_UPDATE_RATE_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00013050)
#define HWIO_GCC_GPLL6_SSC_UPDATE_RATE_RMSK                                                               0xf
#define HWIO_GCC_GPLL6_SSC_UPDATE_RATE_IN          \
        in_dword(HWIO_GCC_GPLL6_SSC_UPDATE_RATE_ADDR)
#define HWIO_GCC_GPLL6_SSC_UPDATE_RATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL6_SSC_UPDATE_RATE_ADDR, m)
#define HWIO_GCC_GPLL6_SSC_UPDATE_RATE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL6_SSC_UPDATE_RATE_ADDR,v)
#define HWIO_GCC_GPLL6_SSC_UPDATE_RATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL6_SSC_UPDATE_RATE_ADDR,m,v,HWIO_GCC_GPLL6_SSC_UPDATE_RATE_IN)
#define HWIO_GCC_GPLL6_SSC_UPDATE_RATE_SSC_UPDATE_RATE_BMSK                                               0xf
#define HWIO_GCC_GPLL6_SSC_UPDATE_RATE_SSC_UPDATE_RATE_SHFT                                               0x0

#define HWIO_GCC_GPLL7_MODE_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a000)
#define HWIO_GCC_GPLL7_MODE_RMSK                                                                   0xffffffff
#define HWIO_GCC_GPLL7_MODE_IN          \
        in_dword(HWIO_GCC_GPLL7_MODE_ADDR)
#define HWIO_GCC_GPLL7_MODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_MODE_ADDR, m)
#define HWIO_GCC_GPLL7_MODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_MODE_ADDR,v)
#define HWIO_GCC_GPLL7_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_MODE_ADDR,m,v,HWIO_GCC_GPLL7_MODE_IN)
#define HWIO_GCC_GPLL7_MODE_PLL_LOCK_DET_BMSK                                                      0x80000000
#define HWIO_GCC_GPLL7_MODE_PLL_LOCK_DET_SHFT                                                            0x1f
#define HWIO_GCC_GPLL7_MODE_PLL_ACTIVE_FLAG_BMSK                                                   0x40000000
#define HWIO_GCC_GPLL7_MODE_PLL_ACTIVE_FLAG_SHFT                                                         0x1e
#define HWIO_GCC_GPLL7_MODE_PLL_ACK_LATCH_BMSK                                                     0x20000000
#define HWIO_GCC_GPLL7_MODE_PLL_ACK_LATCH_SHFT                                                           0x1d
#define HWIO_GCC_GPLL7_MODE_PLL_LOCK_DET_FINE_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL7_MODE_PLL_LOCK_DET_FINE_SHFT                                                       0x1c
#define HWIO_GCC_GPLL7_MODE_PCAL_DONE_BMSK                                                          0x8000000
#define HWIO_GCC_GPLL7_MODE_PCAL_DONE_SHFT                                                               0x1b
#define HWIO_GCC_GPLL7_MODE_RESERVE_BITS26_25_BMSK                                                  0x6000000
#define HWIO_GCC_GPLL7_MODE_RESERVE_BITS26_25_SHFT                                                       0x19
#define HWIO_GCC_GPLL7_MODE_FSM_LEGACY_MODE_BMSK                                                    0x1000000
#define HWIO_GCC_GPLL7_MODE_FSM_LEGACY_MODE_SHFT                                                         0x18
#define HWIO_GCC_GPLL7_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_BMSK                                          0x800000
#define HWIO_GCC_GPLL7_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_SHFT                                              0x17
#define HWIO_GCC_GPLL7_MODE_PLL_UPDATE_BMSK                                                          0x400000
#define HWIO_GCC_GPLL7_MODE_PLL_UPDATE_SHFT                                                              0x16
#define HWIO_GCC_GPLL7_MODE_PLL_VOTE_FSM_RESET_BMSK                                                  0x200000
#define HWIO_GCC_GPLL7_MODE_PLL_VOTE_FSM_RESET_SHFT                                                      0x15
#define HWIO_GCC_GPLL7_MODE_PLL_VOTE_FSM_ENA_BMSK                                                    0x100000
#define HWIO_GCC_GPLL7_MODE_PLL_VOTE_FSM_ENA_SHFT                                                        0x14
#define HWIO_GCC_GPLL7_MODE_PLL_BIAS_COUNT_BMSK                                                       0xfc000
#define HWIO_GCC_GPLL7_MODE_PLL_BIAS_COUNT_SHFT                                                           0xe
#define HWIO_GCC_GPLL7_MODE_PLL_LOCK_COUNT_BMSK                                                        0x3f00
#define HWIO_GCC_GPLL7_MODE_PLL_LOCK_COUNT_SHFT                                                           0x8
#define HWIO_GCC_GPLL7_MODE_RESERVE_BIT7_BMSK                                                            0x80
#define HWIO_GCC_GPLL7_MODE_RESERVE_BIT7_SHFT                                                             0x7
#define HWIO_GCC_GPLL7_MODE_OUT_TEST_HW_CTL_BMSK                                                         0x40
#define HWIO_GCC_GPLL7_MODE_OUT_TEST_HW_CTL_SHFT                                                          0x6
#define HWIO_GCC_GPLL7_MODE_OUT_ODD_HW_CTL_BMSK                                                          0x20
#define HWIO_GCC_GPLL7_MODE_OUT_ODD_HW_CTL_SHFT                                                           0x5
#define HWIO_GCC_GPLL7_MODE_OUT_EVEN_HW_CTL_BMSK                                                         0x10
#define HWIO_GCC_GPLL7_MODE_OUT_EVEN_HW_CTL_SHFT                                                          0x4
#define HWIO_GCC_GPLL7_MODE_OUT_MAIN_HW_CTL_BMSK                                                          0x8
#define HWIO_GCC_GPLL7_MODE_OUT_MAIN_HW_CTL_SHFT                                                          0x3
#define HWIO_GCC_GPLL7_MODE_PLL_RESET_N_BMSK                                                              0x4
#define HWIO_GCC_GPLL7_MODE_PLL_RESET_N_SHFT                                                              0x2
#define HWIO_GCC_GPLL7_MODE_RESERVE_BIT1_BMSK                                                             0x2
#define HWIO_GCC_GPLL7_MODE_RESERVE_BIT1_SHFT                                                             0x1
#define HWIO_GCC_GPLL7_MODE_PLL_OUTCTRL_BMSK                                                              0x1
#define HWIO_GCC_GPLL7_MODE_PLL_OUTCTRL_SHFT                                                              0x0

#define HWIO_GCC_GPLL7_L_VAL_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a004)
#define HWIO_GCC_GPLL7_L_VAL_RMSK                                                                      0xffff
#define HWIO_GCC_GPLL7_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL7_L_VAL_ADDR)
#define HWIO_GCC_GPLL7_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL7_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL7_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_L_VAL_ADDR,m,v,HWIO_GCC_GPLL7_L_VAL_IN)
#define HWIO_GCC_GPLL7_L_VAL_PLL_L_BMSK                                                                0xffff
#define HWIO_GCC_GPLL7_L_VAL_PLL_L_SHFT                                                                   0x0

#define HWIO_GCC_GPLL7_CAL_L_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a008)
#define HWIO_GCC_GPLL7_CAL_L_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL7_CAL_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL7_CAL_L_VAL_ADDR)
#define HWIO_GCC_GPLL7_CAL_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_CAL_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL7_CAL_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_CAL_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL7_CAL_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_CAL_L_VAL_ADDR,m,v,HWIO_GCC_GPLL7_CAL_L_VAL_IN)
#define HWIO_GCC_GPLL7_CAL_L_VAL_PLL_CAL_L_BMSK                                                        0xffff
#define HWIO_GCC_GPLL7_CAL_L_VAL_PLL_CAL_L_SHFT                                                           0x0

#define HWIO_GCC_GPLL7_USER_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a00c)
#define HWIO_GCC_GPLL7_USER_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL7_USER_CTL_IN          \
        in_dword(HWIO_GCC_GPLL7_USER_CTL_ADDR)
#define HWIO_GCC_GPLL7_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_USER_CTL_ADDR, m)
#define HWIO_GCC_GPLL7_USER_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_USER_CTL_ADDR,v)
#define HWIO_GCC_GPLL7_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_USER_CTL_ADDR,m,v,HWIO_GCC_GPLL7_USER_CTL_IN)
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT31_BMSK                                                 0x80000000
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT31_SHFT                                                       0x1f
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT30_BMSK                                                 0x40000000
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT30_SHFT                                                       0x1e
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT29_BMSK                                                 0x20000000
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT29_SHFT                                                       0x1d
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT28_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT28_SHFT                                                       0x1c
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT27_BMSK                                                  0x8000000
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT27_SHFT                                                       0x1b
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT26_BMSK                                                  0x4000000
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT26_SHFT                                                       0x1a
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT25_BMSK                                                  0x2000000
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT25_SHFT                                                       0x19
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT24_BMSK                                                  0x1000000
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT24_SHFT                                                       0x18
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT23_BMSK                                                   0x800000
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT23_SHFT                                                       0x17
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT22_BMSK                                                   0x400000
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT22_SHFT                                                       0x16
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT21_BMSK                                                   0x200000
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT21_SHFT                                                       0x15
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT20_BMSK                                                   0x100000
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT20_SHFT                                                       0x14
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL7_USER_CTL_PRE_DIV_RATIO_BMSK                                                    0x70000
#define HWIO_GCC_GPLL7_USER_CTL_PRE_DIV_RATIO_SHFT                                                       0x10
#define HWIO_GCC_GPLL7_USER_CTL_POST_DIV_RATIO_ODD_BMSK                                                0xf000
#define HWIO_GCC_GPLL7_USER_CTL_POST_DIV_RATIO_ODD_SHFT                                                   0xc
#define HWIO_GCC_GPLL7_USER_CTL_POST_DIV_RATIO_EVEN_BMSK                                                0xf00
#define HWIO_GCC_GPLL7_USER_CTL_POST_DIV_RATIO_EVEN_SHFT                                                  0x8
#define HWIO_GCC_GPLL7_USER_CTL_OUT_CLK_POLARITY_BMSK                                                    0x80
#define HWIO_GCC_GPLL7_USER_CTL_OUT_CLK_POLARITY_SHFT                                                     0x7
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT6_BMSK                                                        0x40
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT6_SHFT                                                         0x6
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT5_BMSK                                                        0x20
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT5_SHFT                                                         0x5
#define HWIO_GCC_GPLL7_USER_CTL_PLLOUT_TEST_BMSK                                                         0x10
#define HWIO_GCC_GPLL7_USER_CTL_PLLOUT_TEST_SHFT                                                          0x4
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT3_BMSK                                                         0x8
#define HWIO_GCC_GPLL7_USER_CTL_RESERVE_BIT3_SHFT                                                         0x3
#define HWIO_GCC_GPLL7_USER_CTL_PLLOUT_ODD_BMSK                                                           0x4
#define HWIO_GCC_GPLL7_USER_CTL_PLLOUT_ODD_SHFT                                                           0x2
#define HWIO_GCC_GPLL7_USER_CTL_PLLOUT_EVEN_BMSK                                                          0x2
#define HWIO_GCC_GPLL7_USER_CTL_PLLOUT_EVEN_SHFT                                                          0x1
#define HWIO_GCC_GPLL7_USER_CTL_PLLOUT_MAIN_BMSK                                                          0x1
#define HWIO_GCC_GPLL7_USER_CTL_PLLOUT_MAIN_SHFT                                                          0x0

#define HWIO_GCC_GPLL7_USER_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a010)
#define HWIO_GCC_GPLL7_USER_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL7_USER_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL7_USER_CTL_U_ADDR)
#define HWIO_GCC_GPLL7_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_USER_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL7_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_USER_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL7_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_USER_CTL_U_ADDR,m,v,HWIO_GCC_GPLL7_USER_CTL_U_IN)
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT63_BMSK                                               0x80000000
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT63_SHFT                                                     0x1f
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT62_BMSK                                               0x40000000
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT62_SHFT                                                     0x1e
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT61_BMSK                                               0x20000000
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT61_SHFT                                                     0x1d
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT60_BMSK                                               0x10000000
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT60_SHFT                                                     0x1c
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT59_BMSK                                                0x8000000
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT59_SHFT                                                     0x1b
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT58_BMSK                                                0x4000000
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT58_SHFT                                                     0x1a
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT57_BMSK                                                0x2000000
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT57_SHFT                                                     0x19
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT56_BMSK                                                0x1000000
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT56_SHFT                                                     0x18
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT55_BMSK                                                 0x800000
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT55_SHFT                                                     0x17
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT54_BMSK                                                 0x400000
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT54_SHFT                                                     0x16
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT53_BMSK                                                 0x200000
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT53_SHFT                                                     0x15
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT52_BMSK                                                 0x100000
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT52_SHFT                                                     0x14
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT51_BMSK                                                  0x80000
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT51_SHFT                                                     0x13
#define HWIO_GCC_GPLL7_USER_CTL_U_LOCK_DETECTOR_SELECTION_BMSK                                        0x40000
#define HWIO_GCC_GPLL7_USER_CTL_U_LOCK_DETECTOR_SELECTION_SHFT                                           0x12
#define HWIO_GCC_GPLL7_USER_CTL_U_TYPE_2_MODE_SELECTION_BMSK                                          0x20000
#define HWIO_GCC_GPLL7_USER_CTL_U_TYPE_2_MODE_SELECTION_SHFT                                             0x11
#define HWIO_GCC_GPLL7_USER_CTL_U_BANG_BANG_MODE_SELECTION_BMSK                                       0x10000
#define HWIO_GCC_GPLL7_USER_CTL_U_BANG_BANG_MODE_SELECTION_SHFT                                          0x10
#define HWIO_GCC_GPLL7_USER_CTL_U_FRAC_FORMAT_SEL_BMSK                                                 0x8000
#define HWIO_GCC_GPLL7_USER_CTL_U_FRAC_FORMAT_SEL_SHFT                                                    0xf
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT46_BMSK                                                   0x4000
#define HWIO_GCC_GPLL7_USER_CTL_U_RESERVE_BIT46_SHFT                                                      0xe
#define HWIO_GCC_GPLL7_USER_CTL_U_REF_CLK_AT_OUT_BMSK                                                  0x2000
#define HWIO_GCC_GPLL7_USER_CTL_U_REF_CLK_AT_OUT_SHFT                                                     0xd
#define HWIO_GCC_GPLL7_USER_CTL_U_SCALE_FREQ_ON_RESTART_BMSK                                           0x1800
#define HWIO_GCC_GPLL7_USER_CTL_U_SCALE_FREQ_ON_RESTART_SHFT                                              0xb
#define HWIO_GCC_GPLL7_USER_CTL_U_LATCH_INTERFACE_BYPASS_BMSK                                           0x400
#define HWIO_GCC_GPLL7_USER_CTL_U_LATCH_INTERFACE_BYPASS_SHFT                                             0xa
#define HWIO_GCC_GPLL7_USER_CTL_U_STATUS_REGISTER_BMSK                                                  0x3e0
#define HWIO_GCC_GPLL7_USER_CTL_U_STATUS_REGISTER_SHFT                                                    0x5
#define HWIO_GCC_GPLL7_USER_CTL_U_WRITE_STATE_EN_BMSK                                                    0x10
#define HWIO_GCC_GPLL7_USER_CTL_U_WRITE_STATE_EN_SHFT                                                     0x4
#define HWIO_GCC_GPLL7_USER_CTL_U_CALIB_CTRL_BMSK                                                         0xe
#define HWIO_GCC_GPLL7_USER_CTL_U_CALIB_CTRL_SHFT                                                         0x1
#define HWIO_GCC_GPLL7_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_BMSK                                             0x1
#define HWIO_GCC_GPLL7_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_SHFT                                             0x0

#define HWIO_GCC_GPLL7_USER_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a014)
#define HWIO_GCC_GPLL7_USER_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL7_USER_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL7_USER_CTL_U1_ADDR)
#define HWIO_GCC_GPLL7_USER_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_USER_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL7_USER_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_USER_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL7_USER_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_USER_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL7_USER_CTL_U1_IN)
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT93_BMSK                                              0x20000000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT93_SHFT                                                    0x1d
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT92_BMSK                                              0x10000000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT92_SHFT                                                    0x1c
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT86_BMSK                                                0x400000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT86_SHFT                                                    0x16
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT82_BMSK                                                 0x40000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT82_SHFT                                                    0x12
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT81_BMSK                                                 0x20000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT81_SHFT                                                    0x11
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT80_BMSK                                                 0x10000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT80_SHFT                                                    0x10
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT79_BMSK                                                  0x8000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT79_SHFT                                                     0xf
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT78_BMSK                                                  0x4000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT78_SHFT                                                     0xe
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT77_BMSK                                                  0x2000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT77_SHFT                                                     0xd
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT71_BMSK                                                    0x80
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT71_SHFT                                                     0x7
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT70_BMSK                                                    0x40
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT70_SHFT                                                     0x6
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT69_BMSK                                                    0x20
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT69_SHFT                                                     0x5
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT65_BMSK                                                     0x2
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT65_SHFT                                                     0x1
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT64_BMSK                                                     0x1
#define HWIO_GCC_GPLL7_USER_CTL_U1_RESERVE_BIT64_SHFT                                                     0x0

#define HWIO_GCC_GPLL7_CONFIG_CTL_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a018)
#define HWIO_GCC_GPLL7_CONFIG_CTL_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL7_CONFIG_CTL_IN          \
        in_dword(HWIO_GCC_GPLL7_CONFIG_CTL_ADDR)
#define HWIO_GCC_GPLL7_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_CONFIG_CTL_ADDR, m)
#define HWIO_GCC_GPLL7_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_CONFIG_CTL_ADDR,v)
#define HWIO_GCC_GPLL7_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_CONFIG_CTL_ADDR,m,v,HWIO_GCC_GPLL7_CONFIG_CTL_IN)
#define HWIO_GCC_GPLL7_CONFIG_CTL_FINE_LDC_THRESHOLD_BMSK                                          0xfc000000
#define HWIO_GCC_GPLL7_CONFIG_CTL_FINE_LDC_THRESHOLD_SHFT                                                0x1a
#define HWIO_GCC_GPLL7_CONFIG_CTL_COARSE_LDC_THRESHOLD_BMSK                                         0x3c00000
#define HWIO_GCC_GPLL7_CONFIG_CTL_COARSE_LDC_THRESHOLD_SHFT                                              0x16
#define HWIO_GCC_GPLL7_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_BMSK                                 0x3c0000
#define HWIO_GCC_GPLL7_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_SHFT                                     0x12
#define HWIO_GCC_GPLL7_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_BMSK                                  0x3c000
#define HWIO_GCC_GPLL7_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_SHFT                                      0xe
#define HWIO_GCC_GPLL7_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_BMSK                                         0x3800
#define HWIO_GCC_GPLL7_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_SHFT                                            0xb
#define HWIO_GCC_GPLL7_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_BMSK                                        0x700
#define HWIO_GCC_GPLL7_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_SHFT                                          0x8
#define HWIO_GCC_GPLL7_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_BMSK                                              0xf0
#define HWIO_GCC_GPLL7_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_SHFT                                               0x4
#define HWIO_GCC_GPLL7_CONFIG_CTL_FWD_GAIN_KFN_BMSK                                                       0xf
#define HWIO_GCC_GPLL7_CONFIG_CTL_FWD_GAIN_KFN_SHFT                                                       0x0

#define HWIO_GCC_GPLL7_CONFIG_CTL_U_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a01c)
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_RMSK                                                           0xffffffff
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL7_CONFIG_CTL_U_ADDR)
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_CONFIG_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_CONFIG_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_CONFIG_CTL_U_ADDR,m,v,HWIO_GCC_GPLL7_CONFIG_CTL_U_IN)
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_BIST_CFG_BMSK                                                  0xffff0000
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_BIST_CFG_SHFT                                                        0x10
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_BMSK                                       0xc000
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_SHFT                                          0xe
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_OSC_SETTLING_TIME_BMSK                                             0x3000
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_OSC_SETTLING_TIME_SHFT                                                0xc
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_BMSK                                            0xc00
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_SHFT                                              0xa
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_CASC_CURRENT_CTL_B_BMSK                                             0x380
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_CASC_CURRENT_CTL_B_SHFT                                               0x7
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_BMSK                                     0x40
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_SHFT                                      0x6
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_BMSK                                            0x30
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_SHFT                                             0x4
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_LDET_THRESH_SCALE_BMSK                                                0x8
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_LDET_THRESH_SCALE_SHFT                                                0x3
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_DCO_STARTUP_CONFIG_BMSK                                               0x6
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_DCO_STARTUP_CONFIG_SHFT                                               0x1
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_BMSK                                          0x1
#define HWIO_GCC_GPLL7_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_SHFT                                          0x0

#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a020)
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_RMSK                                                          0xffffffff
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL7_CONFIG_CTL_U1_ADDR)
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_CONFIG_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_CONFIG_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_CONFIG_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL7_CONFIG_CTL_U1_IN)
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BB_CAL_THRESHOLD_BMSK                                         0xc0000000
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BB_CAL_THRESHOLD_SHFT                                               0x1e
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_PCODE_OFFSET_BMSK                                             0x38000000
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_PCODE_OFFSET_SHFT                                                   0x1b
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_COUNTER_BLANK_BMSK                                             0x4000000
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_COUNTER_BLANK_SHFT                                                  0x1a
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BB_RESYNC_EDGE_BMSK                                            0x2000000
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BB_RESYNC_EDGE_SHFT                                                 0x19
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BB_RESYNC_SEL_BMSK                                             0x1000000
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BB_RESYNC_SEL_SHFT                                                  0x18
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_BMSK                                        0xc00000
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_SHFT                                            0x16
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BB_LOCK_THRESH_BMSK                                             0x380000
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BB_LOCK_THRESH_SHFT                                                 0x13
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_RESERVE_BIT82_BMSK                                               0x40000
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_RESERVE_BIT82_SHFT                                                  0x12
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_BMSK                                          0x30000
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_SHFT                                             0x10
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_BMSK                                            0xc000
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_SHFT                                               0xe
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BB_CAL_EN_BMSK                                                    0x2000
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BB_CAL_EN_SHFT                                                       0xd
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_BMSK                                      0x1800
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_SHFT                                         0xb
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BBMODE_INT_GAIN_BMSK                                               0x780
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BBMODE_INT_GAIN_SHFT                                                 0x7
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BBMODE_PROP_GAIN_BMSK                                               0x78
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_BBMODE_PROP_GAIN_SHFT                                                0x3
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_TDC_SELECTION_BMSK                                                   0x4
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_TDC_SELECTION_SHFT                                                   0x2
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_RESERVE_BIT65_BMSK                                                   0x2
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_RESERVE_BIT65_SHFT                                                   0x1
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_FORCE_DSM_ON_BMSK                                                    0x1
#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_FORCE_DSM_ON_SHFT                                                    0x0

#define HWIO_GCC_GPLL7_TEST_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a024)
#define HWIO_GCC_GPLL7_TEST_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL7_TEST_CTL_IN          \
        in_dword(HWIO_GCC_GPLL7_TEST_CTL_ADDR)
#define HWIO_GCC_GPLL7_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_TEST_CTL_ADDR, m)
#define HWIO_GCC_GPLL7_TEST_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_TEST_CTL_ADDR,v)
#define HWIO_GCC_GPLL7_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_TEST_CTL_ADDR,m,v,HWIO_GCC_GPLL7_TEST_CTL_IN)
#define HWIO_GCC_GPLL7_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_BMSK                                       0xc0000000
#define HWIO_GCC_GPLL7_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_SHFT                                             0x1e
#define HWIO_GCC_GPLL7_TEST_CTL_BYPASS_FIRST_ORDER_DSM_BMSK                                        0x20000000
#define HWIO_GCC_GPLL7_TEST_CTL_BYPASS_FIRST_ORDER_DSM_SHFT                                              0x1d
#define HWIO_GCC_GPLL7_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_BMSK                                   0x18000000
#define HWIO_GCC_GPLL7_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_SHFT                                         0x1b
#define HWIO_GCC_GPLL7_TEST_CTL_GLITCH_PREVENTION_DIS_BMSK                                          0x4000000
#define HWIO_GCC_GPLL7_TEST_CTL_GLITCH_PREVENTION_DIS_SHFT                                               0x1a
#define HWIO_GCC_GPLL7_TEST_CTL_ATEST_ISCALE_BMSK                                                   0x3000000
#define HWIO_GCC_GPLL7_TEST_CTL_ATEST_ISCALE_SHFT                                                        0x18
#define HWIO_GCC_GPLL7_TEST_CTL_PLL_TEST_OUT_SEL_BMSK                                                0xf00000
#define HWIO_GCC_GPLL7_TEST_CTL_PLL_TEST_OUT_SEL_SHFT                                                    0x14
#define HWIO_GCC_GPLL7_TEST_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL7_TEST_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL7_TEST_CTL_DIV2_NMO_EN_BMSK                                                      0x40000
#define HWIO_GCC_GPLL7_TEST_CTL_DIV2_NMO_EN_SHFT                                                         0x12
#define HWIO_GCC_GPLL7_TEST_CTL_NMO_OSC_SEL_BMSK                                                      0x30000
#define HWIO_GCC_GPLL7_TEST_CTL_NMO_OSC_SEL_SHFT                                                         0x10
#define HWIO_GCC_GPLL7_TEST_CTL_NOISE_MAG_BMSK                                                         0xe000
#define HWIO_GCC_GPLL7_TEST_CTL_NOISE_MAG_SHFT                                                            0xd
#define HWIO_GCC_GPLL7_TEST_CTL_NOISE_GEN_EN_BMSK                                                      0x1000
#define HWIO_GCC_GPLL7_TEST_CTL_NOISE_GEN_EN_SHFT                                                         0xc
#define HWIO_GCC_GPLL7_TEST_CTL_DISABLE_DCAPS_BMSK                                                      0x800
#define HWIO_GCC_GPLL7_TEST_CTL_DISABLE_DCAPS_SHFT                                                        0xb
#define HWIO_GCC_GPLL7_TEST_CTL_RESERVE_BIT10_BMSK                                                      0x400
#define HWIO_GCC_GPLL7_TEST_CTL_RESERVE_BIT10_SHFT                                                        0xa
#define HWIO_GCC_GPLL7_TEST_CTL_RESERVE_BIT9_BMSK                                                       0x200
#define HWIO_GCC_GPLL7_TEST_CTL_RESERVE_BIT9_SHFT                                                         0x9
#define HWIO_GCC_GPLL7_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_BMSK                                            0x100
#define HWIO_GCC_GPLL7_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_SHFT                                              0x8
#define HWIO_GCC_GPLL7_TEST_CTL_EN_VDD_TEST_BMSK                                                         0x80
#define HWIO_GCC_GPLL7_TEST_CTL_EN_VDD_TEST_SHFT                                                          0x7
#define HWIO_GCC_GPLL7_TEST_CTL_EN_VREG_TEST_BMSK                                                        0x40
#define HWIO_GCC_GPLL7_TEST_CTL_EN_VREG_TEST_SHFT                                                         0x6
#define HWIO_GCC_GPLL7_TEST_CTL_EN_VREF_TEST_BMSK                                                        0x20
#define HWIO_GCC_GPLL7_TEST_CTL_EN_VREF_TEST_SHFT                                                         0x5
#define HWIO_GCC_GPLL7_TEST_CTL_EN_VDCO_TEST_BMSK                                                        0x10
#define HWIO_GCC_GPLL7_TEST_CTL_EN_VDCO_TEST_SHFT                                                         0x4
#define HWIO_GCC_GPLL7_TEST_CTL_BYPASS_ATEST_BUFFER_BMSK                                                  0x8
#define HWIO_GCC_GPLL7_TEST_CTL_BYPASS_ATEST_BUFFER_SHFT                                                  0x3
#define HWIO_GCC_GPLL7_TEST_CTL_EN_IVCO_TEST_BMSK                                                         0x4
#define HWIO_GCC_GPLL7_TEST_CTL_EN_IVCO_TEST_SHFT                                                         0x2
#define HWIO_GCC_GPLL7_TEST_CTL_ATEST1_EN_BMSK                                                            0x2
#define HWIO_GCC_GPLL7_TEST_CTL_ATEST1_EN_SHFT                                                            0x1
#define HWIO_GCC_GPLL7_TEST_CTL_ATEST0_EN_BMSK                                                            0x1
#define HWIO_GCC_GPLL7_TEST_CTL_ATEST0_EN_SHFT                                                            0x0

#define HWIO_GCC_GPLL7_TEST_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a028)
#define HWIO_GCC_GPLL7_TEST_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL7_TEST_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL7_TEST_CTL_U_ADDR)
#define HWIO_GCC_GPLL7_TEST_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_TEST_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL7_TEST_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_TEST_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL7_TEST_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_TEST_CTL_U_ADDR,m,v,HWIO_GCC_GPLL7_TEST_CTL_U_IN)
#define HWIO_GCC_GPLL7_TEST_CTL_U_CASC_DAC_FCW_LSBS_BMSK                                           0xe0000000
#define HWIO_GCC_GPLL7_TEST_CTL_U_CASC_DAC_FCW_LSBS_SHFT                                                 0x1d
#define HWIO_GCC_GPLL7_TEST_CTL_U_OVERRIDE_CASC_DAC_BMSK                                           0x10000000
#define HWIO_GCC_GPLL7_TEST_CTL_U_OVERRIDE_CASC_DAC_SHFT                                                 0x1c
#define HWIO_GCC_GPLL7_TEST_CTL_U_COMP_COARSE_FCW_BMSK                                              0xe000000
#define HWIO_GCC_GPLL7_TEST_CTL_U_COMP_COARSE_FCW_SHFT                                                   0x19
#define HWIO_GCC_GPLL7_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_BMSK                                     0x1800000
#define HWIO_GCC_GPLL7_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_SHFT                                          0x17
#define HWIO_GCC_GPLL7_TEST_CTL_U_FINE_FCW_BMSK                                                      0x7e0000
#define HWIO_GCC_GPLL7_TEST_CTL_U_FINE_FCW_SHFT                                                          0x11
#define HWIO_GCC_GPLL7_TEST_CTL_U_OVERRIDE_FINE_FCW_BMSK                                              0x10000
#define HWIO_GCC_GPLL7_TEST_CTL_U_OVERRIDE_FINE_FCW_SHFT                                                 0x10
#define HWIO_GCC_GPLL7_TEST_CTL_U_REG_COARSE_FCW_BMSK                                                  0xfe00
#define HWIO_GCC_GPLL7_TEST_CTL_U_REG_COARSE_FCW_SHFT                                                     0x9
#define HWIO_GCC_GPLL7_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_BMSK                                          0x100
#define HWIO_GCC_GPLL7_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_SHFT                                            0x8
#define HWIO_GCC_GPLL7_TEST_CTL_U_PROCESS_CALIB_WORD_BMSK                                                0xe0
#define HWIO_GCC_GPLL7_TEST_CTL_U_PROCESS_CALIB_WORD_SHFT                                                 0x5
#define HWIO_GCC_GPLL7_TEST_CTL_U_OVERRIDE_CALIB_WORD_BMSK                                               0x10
#define HWIO_GCC_GPLL7_TEST_CTL_U_OVERRIDE_CALIB_WORD_SHFT                                                0x4
#define HWIO_GCC_GPLL7_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_BMSK                                             0x8
#define HWIO_GCC_GPLL7_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_SHFT                                             0x3
#define HWIO_GCC_GPLL7_TEST_CTL_U_DISABLE_LFSR_BMSK                                                       0x4
#define HWIO_GCC_GPLL7_TEST_CTL_U_DISABLE_LFSR_SHFT                                                       0x2
#define HWIO_GCC_GPLL7_TEST_CTL_U_SKIP_FINE_TUNE_BMSK                                                     0x2
#define HWIO_GCC_GPLL7_TEST_CTL_U_SKIP_FINE_TUNE_SHFT                                                     0x1
#define HWIO_GCC_GPLL7_TEST_CTL_U_SKIP_FAST_LOCK_BMSK                                                     0x1
#define HWIO_GCC_GPLL7_TEST_CTL_U_SKIP_FAST_LOCK_SHFT                                                     0x0

#define HWIO_GCC_GPLL7_TEST_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a02c)
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL7_TEST_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL7_TEST_CTL_U1_ADDR)
#define HWIO_GCC_GPLL7_TEST_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_TEST_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL7_TEST_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_TEST_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL7_TEST_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_TEST_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL7_TEST_CTL_U1_IN)
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL7_TEST_CTL_U1_FLL_COUNT_DISABLE_BMSK                                          0x20000000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_FLL_COUNT_DISABLE_SHFT                                                0x1d
#define HWIO_GCC_GPLL7_TEST_CTL_U1_FLL_COUNT_IN_DIV2_BMSK                                          0x10000000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_FLL_COUNT_IN_DIV2_SHFT                                                0x1c
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL7_TEST_CTL_U1_SILENCE_REF_OUTBUF_BMSK                                           0x400000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_SILENCE_REF_OUTBUF_SHFT                                               0x16
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL7_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_BMSK                                         0x40000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_SHFT                                            0x12
#define HWIO_GCC_GPLL7_TEST_CTL_U1_REF_CLK_SEL_BMSK                                                   0x20000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_REF_CLK_SEL_SHFT                                                      0x11
#define HWIO_GCC_GPLL7_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_BMSK                                     0x10000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_SHFT                                        0x10
#define HWIO_GCC_GPLL7_TEST_CTL_U1_DIS_AMP_STARTUP_BMSK                                                0x8000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_DIS_AMP_STARTUP_SHFT                                                   0xf
#define HWIO_GCC_GPLL7_TEST_CTL_U1_DISABLE_CLAMP_BMSK                                                  0x4000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_DISABLE_CLAMP_SHFT                                                     0xe
#define HWIO_GCC_GPLL7_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_BMSK                                        0x2000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_SHFT                                           0xd
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL7_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_BMSK                                          0x80
#define HWIO_GCC_GPLL7_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_SHFT                                           0x7
#define HWIO_GCC_GPLL7_TEST_CTL_U1_ENABLE_TRAINING_SEQ_BMSK                                              0x40
#define HWIO_GCC_GPLL7_TEST_CTL_U1_ENABLE_TRAINING_SEQ_SHFT                                               0x6
#define HWIO_GCC_GPLL7_TEST_CTL_U1_STATUS_REG_EN_BMSK                                                    0x20
#define HWIO_GCC_GPLL7_TEST_CTL_U1_STATUS_REG_EN_SHFT                                                     0x5
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL7_TEST_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL7_TEST_CTL_U1_CASC_DAC_FCW_MSBS_BMSK                                                 0x3
#define HWIO_GCC_GPLL7_TEST_CTL_U1_CASC_DAC_FCW_MSBS_SHFT                                                 0x0

#define HWIO_GCC_GPLL7_STATUS_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a030)
#define HWIO_GCC_GPLL7_STATUS_RMSK                                                                 0xffffffff
#define HWIO_GCC_GPLL7_STATUS_IN          \
        in_dword(HWIO_GCC_GPLL7_STATUS_ADDR)
#define HWIO_GCC_GPLL7_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_STATUS_ADDR, m)
#define HWIO_GCC_GPLL7_STATUS_STATUS_31_0_BMSK                                                     0xffffffff
#define HWIO_GCC_GPLL7_STATUS_STATUS_31_0_SHFT                                                            0x0

#define HWIO_GCC_GPLL7_FREQ_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a034)
#define HWIO_GCC_GPLL7_FREQ_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL7_FREQ_CTL_IN          \
        in_dword(HWIO_GCC_GPLL7_FREQ_CTL_ADDR)
#define HWIO_GCC_GPLL7_FREQ_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_FREQ_CTL_ADDR, m)
#define HWIO_GCC_GPLL7_FREQ_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_FREQ_CTL_ADDR,v)
#define HWIO_GCC_GPLL7_FREQ_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_FREQ_CTL_ADDR,m,v,HWIO_GCC_GPLL7_FREQ_CTL_IN)
#define HWIO_GCC_GPLL7_FREQ_CTL_FREQUENCY_CTL_WORD_BMSK                                            0xffffffff
#define HWIO_GCC_GPLL7_FREQ_CTL_FREQUENCY_CTL_WORD_SHFT                                                   0x0

#define HWIO_GCC_GPLL7_OPMODE_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a038)
#define HWIO_GCC_GPLL7_OPMODE_RMSK                                                                        0x7
#define HWIO_GCC_GPLL7_OPMODE_IN          \
        in_dword(HWIO_GCC_GPLL7_OPMODE_ADDR)
#define HWIO_GCC_GPLL7_OPMODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_OPMODE_ADDR, m)
#define HWIO_GCC_GPLL7_OPMODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_OPMODE_ADDR,v)
#define HWIO_GCC_GPLL7_OPMODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_OPMODE_ADDR,m,v,HWIO_GCC_GPLL7_OPMODE_IN)
#define HWIO_GCC_GPLL7_OPMODE_PLL_OPMODE_BMSK                                                             0x7
#define HWIO_GCC_GPLL7_OPMODE_PLL_OPMODE_SHFT                                                             0x0

#define HWIO_GCC_GPLL7_STATE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a03c)
#define HWIO_GCC_GPLL7_STATE_RMSK                                                                         0x7
#define HWIO_GCC_GPLL7_STATE_IN          \
        in_dword(HWIO_GCC_GPLL7_STATE_ADDR)
#define HWIO_GCC_GPLL7_STATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_STATE_ADDR, m)
#define HWIO_GCC_GPLL7_STATE_PLL_STATE_BMSK                                                               0x7
#define HWIO_GCC_GPLL7_STATE_PLL_STATE_SHFT                                                               0x0

#define HWIO_GCC_GPLL7_ALPHA_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a040)
#define HWIO_GCC_GPLL7_ALPHA_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL7_ALPHA_VAL_IN          \
        in_dword(HWIO_GCC_GPLL7_ALPHA_VAL_ADDR)
#define HWIO_GCC_GPLL7_ALPHA_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_ALPHA_VAL_ADDR, m)
#define HWIO_GCC_GPLL7_ALPHA_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_ALPHA_VAL_ADDR,v)
#define HWIO_GCC_GPLL7_ALPHA_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_ALPHA_VAL_ADDR,m,v,HWIO_GCC_GPLL7_ALPHA_VAL_IN)
#define HWIO_GCC_GPLL7_ALPHA_VAL_PLL_ALPHA_VAL_BMSK                                                    0xffff
#define HWIO_GCC_GPLL7_ALPHA_VAL_PLL_ALPHA_VAL_SHFT                                                       0x0

#define HWIO_GCC_GPLL7_SPARE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a044)
#define HWIO_GCC_GPLL7_SPARE_RMSK                                                                        0xff
#define HWIO_GCC_GPLL7_SPARE_IN          \
        in_dword(HWIO_GCC_GPLL7_SPARE_ADDR)
#define HWIO_GCC_GPLL7_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_SPARE_ADDR, m)
#define HWIO_GCC_GPLL7_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_SPARE_ADDR,v)
#define HWIO_GCC_GPLL7_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_SPARE_ADDR,m,v,HWIO_GCC_GPLL7_SPARE_IN)
#define HWIO_GCC_GPLL7_SPARE_SPARE_OUTPUTS_BMSK                                                          0xf0
#define HWIO_GCC_GPLL7_SPARE_SPARE_OUTPUTS_SHFT                                                           0x4
#define HWIO_GCC_GPLL7_SPARE_SPARE_INPUTS_BMSK                                                            0xf
#define HWIO_GCC_GPLL7_SPARE_SPARE_INPUTS_SHFT                                                            0x0

#define HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a048)
#define HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_RMSK                                                              0xff
#define HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_IN          \
        in_dword(HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_ADDR)
#define HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_ADDR, m)
#define HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_ADDR,v)
#define HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_ADDR,m,v,HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_IN)
#define HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_BMSK                                              0xff
#define HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_SHFT                                               0x0

#define HWIO_GCC_GPLL7_SSC_NUM_STEPS_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a04c)
#define HWIO_GCC_GPLL7_SSC_NUM_STEPS_RMSK                                                                 0xf
#define HWIO_GCC_GPLL7_SSC_NUM_STEPS_IN          \
        in_dword(HWIO_GCC_GPLL7_SSC_NUM_STEPS_ADDR)
#define HWIO_GCC_GPLL7_SSC_NUM_STEPS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_SSC_NUM_STEPS_ADDR, m)
#define HWIO_GCC_GPLL7_SSC_NUM_STEPS_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_SSC_NUM_STEPS_ADDR,v)
#define HWIO_GCC_GPLL7_SSC_NUM_STEPS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_SSC_NUM_STEPS_ADDR,m,v,HWIO_GCC_GPLL7_SSC_NUM_STEPS_IN)
#define HWIO_GCC_GPLL7_SSC_NUM_STEPS_SSC_NUM_STEPS_BMSK                                                   0xf
#define HWIO_GCC_GPLL7_SSC_NUM_STEPS_SSC_NUM_STEPS_SHFT                                                   0x0

#define HWIO_GCC_GPLL7_SSC_UPDATE_RATE_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0001a050)
#define HWIO_GCC_GPLL7_SSC_UPDATE_RATE_RMSK                                                               0xf
#define HWIO_GCC_GPLL7_SSC_UPDATE_RATE_IN          \
        in_dword(HWIO_GCC_GPLL7_SSC_UPDATE_RATE_ADDR)
#define HWIO_GCC_GPLL7_SSC_UPDATE_RATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL7_SSC_UPDATE_RATE_ADDR, m)
#define HWIO_GCC_GPLL7_SSC_UPDATE_RATE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL7_SSC_UPDATE_RATE_ADDR,v)
#define HWIO_GCC_GPLL7_SSC_UPDATE_RATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL7_SSC_UPDATE_RATE_ADDR,m,v,HWIO_GCC_GPLL7_SSC_UPDATE_RATE_IN)
#define HWIO_GCC_GPLL7_SSC_UPDATE_RATE_SSC_UPDATE_RATE_BMSK                                               0xf
#define HWIO_GCC_GPLL7_SSC_UPDATE_RATE_SSC_UPDATE_RATE_SHFT                                               0x0

#define HWIO_GCC_GPLL8_MODE_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b000)
#define HWIO_GCC_GPLL8_MODE_RMSK                                                                   0xffffffff
#define HWIO_GCC_GPLL8_MODE_IN          \
        in_dword(HWIO_GCC_GPLL8_MODE_ADDR)
#define HWIO_GCC_GPLL8_MODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_MODE_ADDR, m)
#define HWIO_GCC_GPLL8_MODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_MODE_ADDR,v)
#define HWIO_GCC_GPLL8_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_MODE_ADDR,m,v,HWIO_GCC_GPLL8_MODE_IN)
#define HWIO_GCC_GPLL8_MODE_PLL_LOCK_DET_BMSK                                                      0x80000000
#define HWIO_GCC_GPLL8_MODE_PLL_LOCK_DET_SHFT                                                            0x1f
#define HWIO_GCC_GPLL8_MODE_PLL_ACTIVE_FLAG_BMSK                                                   0x40000000
#define HWIO_GCC_GPLL8_MODE_PLL_ACTIVE_FLAG_SHFT                                                         0x1e
#define HWIO_GCC_GPLL8_MODE_PLL_ACK_LATCH_BMSK                                                     0x20000000
#define HWIO_GCC_GPLL8_MODE_PLL_ACK_LATCH_SHFT                                                           0x1d
#define HWIO_GCC_GPLL8_MODE_PLL_LOCK_DET_FINE_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL8_MODE_PLL_LOCK_DET_FINE_SHFT                                                       0x1c
#define HWIO_GCC_GPLL8_MODE_PCAL_DONE_BMSK                                                          0x8000000
#define HWIO_GCC_GPLL8_MODE_PCAL_DONE_SHFT                                                               0x1b
#define HWIO_GCC_GPLL8_MODE_RESERVE_BITS26_25_BMSK                                                  0x6000000
#define HWIO_GCC_GPLL8_MODE_RESERVE_BITS26_25_SHFT                                                       0x19
#define HWIO_GCC_GPLL8_MODE_FSM_LEGACY_MODE_BMSK                                                    0x1000000
#define HWIO_GCC_GPLL8_MODE_FSM_LEGACY_MODE_SHFT                                                         0x18
#define HWIO_GCC_GPLL8_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_BMSK                                          0x800000
#define HWIO_GCC_GPLL8_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_SHFT                                              0x17
#define HWIO_GCC_GPLL8_MODE_PLL_UPDATE_BMSK                                                          0x400000
#define HWIO_GCC_GPLL8_MODE_PLL_UPDATE_SHFT                                                              0x16
#define HWIO_GCC_GPLL8_MODE_PLL_VOTE_FSM_RESET_BMSK                                                  0x200000
#define HWIO_GCC_GPLL8_MODE_PLL_VOTE_FSM_RESET_SHFT                                                      0x15
#define HWIO_GCC_GPLL8_MODE_PLL_VOTE_FSM_ENA_BMSK                                                    0x100000
#define HWIO_GCC_GPLL8_MODE_PLL_VOTE_FSM_ENA_SHFT                                                        0x14
#define HWIO_GCC_GPLL8_MODE_PLL_BIAS_COUNT_BMSK                                                       0xfc000
#define HWIO_GCC_GPLL8_MODE_PLL_BIAS_COUNT_SHFT                                                           0xe
#define HWIO_GCC_GPLL8_MODE_PLL_LOCK_COUNT_BMSK                                                        0x3f00
#define HWIO_GCC_GPLL8_MODE_PLL_LOCK_COUNT_SHFT                                                           0x8
#define HWIO_GCC_GPLL8_MODE_RESERVE_BIT7_BMSK                                                            0x80
#define HWIO_GCC_GPLL8_MODE_RESERVE_BIT7_SHFT                                                             0x7
#define HWIO_GCC_GPLL8_MODE_OUT_TEST_HW_CTL_BMSK                                                         0x40
#define HWIO_GCC_GPLL8_MODE_OUT_TEST_HW_CTL_SHFT                                                          0x6
#define HWIO_GCC_GPLL8_MODE_OUT_ODD_HW_CTL_BMSK                                                          0x20
#define HWIO_GCC_GPLL8_MODE_OUT_ODD_HW_CTL_SHFT                                                           0x5
#define HWIO_GCC_GPLL8_MODE_OUT_EVEN_HW_CTL_BMSK                                                         0x10
#define HWIO_GCC_GPLL8_MODE_OUT_EVEN_HW_CTL_SHFT                                                          0x4
#define HWIO_GCC_GPLL8_MODE_OUT_MAIN_HW_CTL_BMSK                                                          0x8
#define HWIO_GCC_GPLL8_MODE_OUT_MAIN_HW_CTL_SHFT                                                          0x3
#define HWIO_GCC_GPLL8_MODE_PLL_RESET_N_BMSK                                                              0x4
#define HWIO_GCC_GPLL8_MODE_PLL_RESET_N_SHFT                                                              0x2
#define HWIO_GCC_GPLL8_MODE_RESERVE_BIT1_BMSK                                                             0x2
#define HWIO_GCC_GPLL8_MODE_RESERVE_BIT1_SHFT                                                             0x1
#define HWIO_GCC_GPLL8_MODE_PLL_OUTCTRL_BMSK                                                              0x1
#define HWIO_GCC_GPLL8_MODE_PLL_OUTCTRL_SHFT                                                              0x0

#define HWIO_GCC_GPLL8_L_VAL_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b004)
#define HWIO_GCC_GPLL8_L_VAL_RMSK                                                                      0xffff
#define HWIO_GCC_GPLL8_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL8_L_VAL_ADDR)
#define HWIO_GCC_GPLL8_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL8_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL8_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_L_VAL_ADDR,m,v,HWIO_GCC_GPLL8_L_VAL_IN)
#define HWIO_GCC_GPLL8_L_VAL_PLL_L_BMSK                                                                0xffff
#define HWIO_GCC_GPLL8_L_VAL_PLL_L_SHFT                                                                   0x0

#define HWIO_GCC_GPLL8_CAL_L_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b008)
#define HWIO_GCC_GPLL8_CAL_L_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL8_CAL_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL8_CAL_L_VAL_ADDR)
#define HWIO_GCC_GPLL8_CAL_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_CAL_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL8_CAL_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_CAL_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL8_CAL_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_CAL_L_VAL_ADDR,m,v,HWIO_GCC_GPLL8_CAL_L_VAL_IN)
#define HWIO_GCC_GPLL8_CAL_L_VAL_PLL_CAL_L_BMSK                                                        0xffff
#define HWIO_GCC_GPLL8_CAL_L_VAL_PLL_CAL_L_SHFT                                                           0x0

#define HWIO_GCC_GPLL8_USER_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b00c)
#define HWIO_GCC_GPLL8_USER_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL8_USER_CTL_IN          \
        in_dword(HWIO_GCC_GPLL8_USER_CTL_ADDR)
#define HWIO_GCC_GPLL8_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_USER_CTL_ADDR, m)
#define HWIO_GCC_GPLL8_USER_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_USER_CTL_ADDR,v)
#define HWIO_GCC_GPLL8_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_USER_CTL_ADDR,m,v,HWIO_GCC_GPLL8_USER_CTL_IN)
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT31_BMSK                                                 0x80000000
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT31_SHFT                                                       0x1f
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT30_BMSK                                                 0x40000000
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT30_SHFT                                                       0x1e
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT29_BMSK                                                 0x20000000
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT29_SHFT                                                       0x1d
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT28_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT28_SHFT                                                       0x1c
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT27_BMSK                                                  0x8000000
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT27_SHFT                                                       0x1b
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT26_BMSK                                                  0x4000000
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT26_SHFT                                                       0x1a
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT25_BMSK                                                  0x2000000
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT25_SHFT                                                       0x19
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT24_BMSK                                                  0x1000000
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT24_SHFT                                                       0x18
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT23_BMSK                                                   0x800000
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT23_SHFT                                                       0x17
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT22_BMSK                                                   0x400000
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT22_SHFT                                                       0x16
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT21_BMSK                                                   0x200000
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT21_SHFT                                                       0x15
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT20_BMSK                                                   0x100000
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT20_SHFT                                                       0x14
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL8_USER_CTL_PRE_DIV_RATIO_BMSK                                                    0x70000
#define HWIO_GCC_GPLL8_USER_CTL_PRE_DIV_RATIO_SHFT                                                       0x10
#define HWIO_GCC_GPLL8_USER_CTL_POST_DIV_RATIO_ODD_BMSK                                                0xf000
#define HWIO_GCC_GPLL8_USER_CTL_POST_DIV_RATIO_ODD_SHFT                                                   0xc
#define HWIO_GCC_GPLL8_USER_CTL_POST_DIV_RATIO_EVEN_BMSK                                                0xf00
#define HWIO_GCC_GPLL8_USER_CTL_POST_DIV_RATIO_EVEN_SHFT                                                  0x8
#define HWIO_GCC_GPLL8_USER_CTL_OUT_CLK_POLARITY_BMSK                                                    0x80
#define HWIO_GCC_GPLL8_USER_CTL_OUT_CLK_POLARITY_SHFT                                                     0x7
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT6_BMSK                                                        0x40
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT6_SHFT                                                         0x6
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT5_BMSK                                                        0x20
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT5_SHFT                                                         0x5
#define HWIO_GCC_GPLL8_USER_CTL_PLLOUT_TEST_BMSK                                                         0x10
#define HWIO_GCC_GPLL8_USER_CTL_PLLOUT_TEST_SHFT                                                          0x4
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT3_BMSK                                                         0x8
#define HWIO_GCC_GPLL8_USER_CTL_RESERVE_BIT3_SHFT                                                         0x3
#define HWIO_GCC_GPLL8_USER_CTL_PLLOUT_ODD_BMSK                                                           0x4
#define HWIO_GCC_GPLL8_USER_CTL_PLLOUT_ODD_SHFT                                                           0x2
#define HWIO_GCC_GPLL8_USER_CTL_PLLOUT_EVEN_BMSK                                                          0x2
#define HWIO_GCC_GPLL8_USER_CTL_PLLOUT_EVEN_SHFT                                                          0x1
#define HWIO_GCC_GPLL8_USER_CTL_PLLOUT_MAIN_BMSK                                                          0x1
#define HWIO_GCC_GPLL8_USER_CTL_PLLOUT_MAIN_SHFT                                                          0x0

#define HWIO_GCC_GPLL8_USER_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b010)
#define HWIO_GCC_GPLL8_USER_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL8_USER_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL8_USER_CTL_U_ADDR)
#define HWIO_GCC_GPLL8_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_USER_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL8_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_USER_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL8_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_USER_CTL_U_ADDR,m,v,HWIO_GCC_GPLL8_USER_CTL_U_IN)
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT63_BMSK                                               0x80000000
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT63_SHFT                                                     0x1f
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT62_BMSK                                               0x40000000
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT62_SHFT                                                     0x1e
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT61_BMSK                                               0x20000000
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT61_SHFT                                                     0x1d
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT60_BMSK                                               0x10000000
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT60_SHFT                                                     0x1c
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT59_BMSK                                                0x8000000
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT59_SHFT                                                     0x1b
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT58_BMSK                                                0x4000000
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT58_SHFT                                                     0x1a
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT57_BMSK                                                0x2000000
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT57_SHFT                                                     0x19
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT56_BMSK                                                0x1000000
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT56_SHFT                                                     0x18
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT55_BMSK                                                 0x800000
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT55_SHFT                                                     0x17
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT54_BMSK                                                 0x400000
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT54_SHFT                                                     0x16
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT53_BMSK                                                 0x200000
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT53_SHFT                                                     0x15
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT52_BMSK                                                 0x100000
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT52_SHFT                                                     0x14
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT51_BMSK                                                  0x80000
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT51_SHFT                                                     0x13
#define HWIO_GCC_GPLL8_USER_CTL_U_LOCK_DETECTOR_SELECTION_BMSK                                        0x40000
#define HWIO_GCC_GPLL8_USER_CTL_U_LOCK_DETECTOR_SELECTION_SHFT                                           0x12
#define HWIO_GCC_GPLL8_USER_CTL_U_TYPE_2_MODE_SELECTION_BMSK                                          0x20000
#define HWIO_GCC_GPLL8_USER_CTL_U_TYPE_2_MODE_SELECTION_SHFT                                             0x11
#define HWIO_GCC_GPLL8_USER_CTL_U_BANG_BANG_MODE_SELECTION_BMSK                                       0x10000
#define HWIO_GCC_GPLL8_USER_CTL_U_BANG_BANG_MODE_SELECTION_SHFT                                          0x10
#define HWIO_GCC_GPLL8_USER_CTL_U_FRAC_FORMAT_SEL_BMSK                                                 0x8000
#define HWIO_GCC_GPLL8_USER_CTL_U_FRAC_FORMAT_SEL_SHFT                                                    0xf
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT46_BMSK                                                   0x4000
#define HWIO_GCC_GPLL8_USER_CTL_U_RESERVE_BIT46_SHFT                                                      0xe
#define HWIO_GCC_GPLL8_USER_CTL_U_REF_CLK_AT_OUT_BMSK                                                  0x2000
#define HWIO_GCC_GPLL8_USER_CTL_U_REF_CLK_AT_OUT_SHFT                                                     0xd
#define HWIO_GCC_GPLL8_USER_CTL_U_SCALE_FREQ_ON_RESTART_BMSK                                           0x1800
#define HWIO_GCC_GPLL8_USER_CTL_U_SCALE_FREQ_ON_RESTART_SHFT                                              0xb
#define HWIO_GCC_GPLL8_USER_CTL_U_LATCH_INTERFACE_BYPASS_BMSK                                           0x400
#define HWIO_GCC_GPLL8_USER_CTL_U_LATCH_INTERFACE_BYPASS_SHFT                                             0xa
#define HWIO_GCC_GPLL8_USER_CTL_U_STATUS_REGISTER_BMSK                                                  0x3e0
#define HWIO_GCC_GPLL8_USER_CTL_U_STATUS_REGISTER_SHFT                                                    0x5
#define HWIO_GCC_GPLL8_USER_CTL_U_WRITE_STATE_EN_BMSK                                                    0x10
#define HWIO_GCC_GPLL8_USER_CTL_U_WRITE_STATE_EN_SHFT                                                     0x4
#define HWIO_GCC_GPLL8_USER_CTL_U_CALIB_CTRL_BMSK                                                         0xe
#define HWIO_GCC_GPLL8_USER_CTL_U_CALIB_CTRL_SHFT                                                         0x1
#define HWIO_GCC_GPLL8_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_BMSK                                             0x1
#define HWIO_GCC_GPLL8_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_SHFT                                             0x0

#define HWIO_GCC_GPLL8_USER_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b014)
#define HWIO_GCC_GPLL8_USER_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL8_USER_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL8_USER_CTL_U1_ADDR)
#define HWIO_GCC_GPLL8_USER_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_USER_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL8_USER_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_USER_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL8_USER_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_USER_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL8_USER_CTL_U1_IN)
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT93_BMSK                                              0x20000000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT93_SHFT                                                    0x1d
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT92_BMSK                                              0x10000000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT92_SHFT                                                    0x1c
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT86_BMSK                                                0x400000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT86_SHFT                                                    0x16
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT82_BMSK                                                 0x40000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT82_SHFT                                                    0x12
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT81_BMSK                                                 0x20000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT81_SHFT                                                    0x11
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT80_BMSK                                                 0x10000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT80_SHFT                                                    0x10
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT79_BMSK                                                  0x8000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT79_SHFT                                                     0xf
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT78_BMSK                                                  0x4000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT78_SHFT                                                     0xe
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT77_BMSK                                                  0x2000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT77_SHFT                                                     0xd
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT71_BMSK                                                    0x80
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT71_SHFT                                                     0x7
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT70_BMSK                                                    0x40
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT70_SHFT                                                     0x6
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT69_BMSK                                                    0x20
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT69_SHFT                                                     0x5
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT65_BMSK                                                     0x2
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT65_SHFT                                                     0x1
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT64_BMSK                                                     0x1
#define HWIO_GCC_GPLL8_USER_CTL_U1_RESERVE_BIT64_SHFT                                                     0x0

#define HWIO_GCC_GPLL8_CONFIG_CTL_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b018)
#define HWIO_GCC_GPLL8_CONFIG_CTL_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL8_CONFIG_CTL_IN          \
        in_dword(HWIO_GCC_GPLL8_CONFIG_CTL_ADDR)
#define HWIO_GCC_GPLL8_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_CONFIG_CTL_ADDR, m)
#define HWIO_GCC_GPLL8_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_CONFIG_CTL_ADDR,v)
#define HWIO_GCC_GPLL8_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_CONFIG_CTL_ADDR,m,v,HWIO_GCC_GPLL8_CONFIG_CTL_IN)
#define HWIO_GCC_GPLL8_CONFIG_CTL_FINE_LDC_THRESHOLD_BMSK                                          0xfc000000
#define HWIO_GCC_GPLL8_CONFIG_CTL_FINE_LDC_THRESHOLD_SHFT                                                0x1a
#define HWIO_GCC_GPLL8_CONFIG_CTL_COARSE_LDC_THRESHOLD_BMSK                                         0x3c00000
#define HWIO_GCC_GPLL8_CONFIG_CTL_COARSE_LDC_THRESHOLD_SHFT                                              0x16
#define HWIO_GCC_GPLL8_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_BMSK                                 0x3c0000
#define HWIO_GCC_GPLL8_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_SHFT                                     0x12
#define HWIO_GCC_GPLL8_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_BMSK                                  0x3c000
#define HWIO_GCC_GPLL8_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_SHFT                                      0xe
#define HWIO_GCC_GPLL8_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_BMSK                                         0x3800
#define HWIO_GCC_GPLL8_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_SHFT                                            0xb
#define HWIO_GCC_GPLL8_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_BMSK                                        0x700
#define HWIO_GCC_GPLL8_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_SHFT                                          0x8
#define HWIO_GCC_GPLL8_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_BMSK                                              0xf0
#define HWIO_GCC_GPLL8_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_SHFT                                               0x4
#define HWIO_GCC_GPLL8_CONFIG_CTL_FWD_GAIN_KFN_BMSK                                                       0xf
#define HWIO_GCC_GPLL8_CONFIG_CTL_FWD_GAIN_KFN_SHFT                                                       0x0

#define HWIO_GCC_GPLL8_CONFIG_CTL_U_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b01c)
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_RMSK                                                           0xffffffff
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL8_CONFIG_CTL_U_ADDR)
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_CONFIG_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_CONFIG_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_CONFIG_CTL_U_ADDR,m,v,HWIO_GCC_GPLL8_CONFIG_CTL_U_IN)
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_BIST_CFG_BMSK                                                  0xffff0000
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_BIST_CFG_SHFT                                                        0x10
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_BMSK                                       0xc000
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_SHFT                                          0xe
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_OSC_SETTLING_TIME_BMSK                                             0x3000
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_OSC_SETTLING_TIME_SHFT                                                0xc
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_BMSK                                            0xc00
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_SHFT                                              0xa
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_CASC_CURRENT_CTL_B_BMSK                                             0x380
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_CASC_CURRENT_CTL_B_SHFT                                               0x7
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_BMSK                                     0x40
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_SHFT                                      0x6
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_BMSK                                            0x30
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_SHFT                                             0x4
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_LDET_THRESH_SCALE_BMSK                                                0x8
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_LDET_THRESH_SCALE_SHFT                                                0x3
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_DCO_STARTUP_CONFIG_BMSK                                               0x6
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_DCO_STARTUP_CONFIG_SHFT                                               0x1
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_BMSK                                          0x1
#define HWIO_GCC_GPLL8_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_SHFT                                          0x0

#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b020)
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_RMSK                                                          0xffffffff
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL8_CONFIG_CTL_U1_ADDR)
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_CONFIG_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_CONFIG_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_CONFIG_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL8_CONFIG_CTL_U1_IN)
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BB_CAL_THRESHOLD_BMSK                                         0xc0000000
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BB_CAL_THRESHOLD_SHFT                                               0x1e
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_PCODE_OFFSET_BMSK                                             0x38000000
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_PCODE_OFFSET_SHFT                                                   0x1b
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_COUNTER_BLANK_BMSK                                             0x4000000
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_COUNTER_BLANK_SHFT                                                  0x1a
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BB_RESYNC_EDGE_BMSK                                            0x2000000
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BB_RESYNC_EDGE_SHFT                                                 0x19
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BB_RESYNC_SEL_BMSK                                             0x1000000
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BB_RESYNC_SEL_SHFT                                                  0x18
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_BMSK                                        0xc00000
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_SHFT                                            0x16
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BB_LOCK_THRESH_BMSK                                             0x380000
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BB_LOCK_THRESH_SHFT                                                 0x13
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_RESERVE_BIT82_BMSK                                               0x40000
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_RESERVE_BIT82_SHFT                                                  0x12
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_BMSK                                          0x30000
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_SHFT                                             0x10
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_BMSK                                            0xc000
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_SHFT                                               0xe
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BB_CAL_EN_BMSK                                                    0x2000
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BB_CAL_EN_SHFT                                                       0xd
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_BMSK                                      0x1800
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_SHFT                                         0xb
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BBMODE_INT_GAIN_BMSK                                               0x780
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BBMODE_INT_GAIN_SHFT                                                 0x7
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BBMODE_PROP_GAIN_BMSK                                               0x78
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_BBMODE_PROP_GAIN_SHFT                                                0x3
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_TDC_SELECTION_BMSK                                                   0x4
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_TDC_SELECTION_SHFT                                                   0x2
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_RESERVE_BIT65_BMSK                                                   0x2
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_RESERVE_BIT65_SHFT                                                   0x1
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_FORCE_DSM_ON_BMSK                                                    0x1
#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_FORCE_DSM_ON_SHFT                                                    0x0

#define HWIO_GCC_GPLL8_TEST_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b024)
#define HWIO_GCC_GPLL8_TEST_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL8_TEST_CTL_IN          \
        in_dword(HWIO_GCC_GPLL8_TEST_CTL_ADDR)
#define HWIO_GCC_GPLL8_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_TEST_CTL_ADDR, m)
#define HWIO_GCC_GPLL8_TEST_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_TEST_CTL_ADDR,v)
#define HWIO_GCC_GPLL8_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_TEST_CTL_ADDR,m,v,HWIO_GCC_GPLL8_TEST_CTL_IN)
#define HWIO_GCC_GPLL8_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_BMSK                                       0xc0000000
#define HWIO_GCC_GPLL8_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_SHFT                                             0x1e
#define HWIO_GCC_GPLL8_TEST_CTL_BYPASS_FIRST_ORDER_DSM_BMSK                                        0x20000000
#define HWIO_GCC_GPLL8_TEST_CTL_BYPASS_FIRST_ORDER_DSM_SHFT                                              0x1d
#define HWIO_GCC_GPLL8_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_BMSK                                   0x18000000
#define HWIO_GCC_GPLL8_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_SHFT                                         0x1b
#define HWIO_GCC_GPLL8_TEST_CTL_GLITCH_PREVENTION_DIS_BMSK                                          0x4000000
#define HWIO_GCC_GPLL8_TEST_CTL_GLITCH_PREVENTION_DIS_SHFT                                               0x1a
#define HWIO_GCC_GPLL8_TEST_CTL_ATEST_ISCALE_BMSK                                                   0x3000000
#define HWIO_GCC_GPLL8_TEST_CTL_ATEST_ISCALE_SHFT                                                        0x18
#define HWIO_GCC_GPLL8_TEST_CTL_PLL_TEST_OUT_SEL_BMSK                                                0xf00000
#define HWIO_GCC_GPLL8_TEST_CTL_PLL_TEST_OUT_SEL_SHFT                                                    0x14
#define HWIO_GCC_GPLL8_TEST_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL8_TEST_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL8_TEST_CTL_DIV2_NMO_EN_BMSK                                                      0x40000
#define HWIO_GCC_GPLL8_TEST_CTL_DIV2_NMO_EN_SHFT                                                         0x12
#define HWIO_GCC_GPLL8_TEST_CTL_NMO_OSC_SEL_BMSK                                                      0x30000
#define HWIO_GCC_GPLL8_TEST_CTL_NMO_OSC_SEL_SHFT                                                         0x10
#define HWIO_GCC_GPLL8_TEST_CTL_NOISE_MAG_BMSK                                                         0xe000
#define HWIO_GCC_GPLL8_TEST_CTL_NOISE_MAG_SHFT                                                            0xd
#define HWIO_GCC_GPLL8_TEST_CTL_NOISE_GEN_EN_BMSK                                                      0x1000
#define HWIO_GCC_GPLL8_TEST_CTL_NOISE_GEN_EN_SHFT                                                         0xc
#define HWIO_GCC_GPLL8_TEST_CTL_DISABLE_DCAPS_BMSK                                                      0x800
#define HWIO_GCC_GPLL8_TEST_CTL_DISABLE_DCAPS_SHFT                                                        0xb
#define HWIO_GCC_GPLL8_TEST_CTL_RESERVE_BIT10_BMSK                                                      0x400
#define HWIO_GCC_GPLL8_TEST_CTL_RESERVE_BIT10_SHFT                                                        0xa
#define HWIO_GCC_GPLL8_TEST_CTL_RESERVE_BIT9_BMSK                                                       0x200
#define HWIO_GCC_GPLL8_TEST_CTL_RESERVE_BIT9_SHFT                                                         0x9
#define HWIO_GCC_GPLL8_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_BMSK                                            0x100
#define HWIO_GCC_GPLL8_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_SHFT                                              0x8
#define HWIO_GCC_GPLL8_TEST_CTL_EN_VDD_TEST_BMSK                                                         0x80
#define HWIO_GCC_GPLL8_TEST_CTL_EN_VDD_TEST_SHFT                                                          0x7
#define HWIO_GCC_GPLL8_TEST_CTL_EN_VREG_TEST_BMSK                                                        0x40
#define HWIO_GCC_GPLL8_TEST_CTL_EN_VREG_TEST_SHFT                                                         0x6
#define HWIO_GCC_GPLL8_TEST_CTL_EN_VREF_TEST_BMSK                                                        0x20
#define HWIO_GCC_GPLL8_TEST_CTL_EN_VREF_TEST_SHFT                                                         0x5
#define HWIO_GCC_GPLL8_TEST_CTL_EN_VDCO_TEST_BMSK                                                        0x10
#define HWIO_GCC_GPLL8_TEST_CTL_EN_VDCO_TEST_SHFT                                                         0x4
#define HWIO_GCC_GPLL8_TEST_CTL_BYPASS_ATEST_BUFFER_BMSK                                                  0x8
#define HWIO_GCC_GPLL8_TEST_CTL_BYPASS_ATEST_BUFFER_SHFT                                                  0x3
#define HWIO_GCC_GPLL8_TEST_CTL_EN_IVCO_TEST_BMSK                                                         0x4
#define HWIO_GCC_GPLL8_TEST_CTL_EN_IVCO_TEST_SHFT                                                         0x2
#define HWIO_GCC_GPLL8_TEST_CTL_ATEST1_EN_BMSK                                                            0x2
#define HWIO_GCC_GPLL8_TEST_CTL_ATEST1_EN_SHFT                                                            0x1
#define HWIO_GCC_GPLL8_TEST_CTL_ATEST0_EN_BMSK                                                            0x1
#define HWIO_GCC_GPLL8_TEST_CTL_ATEST0_EN_SHFT                                                            0x0

#define HWIO_GCC_GPLL8_TEST_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b028)
#define HWIO_GCC_GPLL8_TEST_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL8_TEST_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL8_TEST_CTL_U_ADDR)
#define HWIO_GCC_GPLL8_TEST_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_TEST_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL8_TEST_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_TEST_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL8_TEST_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_TEST_CTL_U_ADDR,m,v,HWIO_GCC_GPLL8_TEST_CTL_U_IN)
#define HWIO_GCC_GPLL8_TEST_CTL_U_CASC_DAC_FCW_LSBS_BMSK                                           0xe0000000
#define HWIO_GCC_GPLL8_TEST_CTL_U_CASC_DAC_FCW_LSBS_SHFT                                                 0x1d
#define HWIO_GCC_GPLL8_TEST_CTL_U_OVERRIDE_CASC_DAC_BMSK                                           0x10000000
#define HWIO_GCC_GPLL8_TEST_CTL_U_OVERRIDE_CASC_DAC_SHFT                                                 0x1c
#define HWIO_GCC_GPLL8_TEST_CTL_U_COMP_COARSE_FCW_BMSK                                              0xe000000
#define HWIO_GCC_GPLL8_TEST_CTL_U_COMP_COARSE_FCW_SHFT                                                   0x19
#define HWIO_GCC_GPLL8_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_BMSK                                     0x1800000
#define HWIO_GCC_GPLL8_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_SHFT                                          0x17
#define HWIO_GCC_GPLL8_TEST_CTL_U_FINE_FCW_BMSK                                                      0x7e0000
#define HWIO_GCC_GPLL8_TEST_CTL_U_FINE_FCW_SHFT                                                          0x11
#define HWIO_GCC_GPLL8_TEST_CTL_U_OVERRIDE_FINE_FCW_BMSK                                              0x10000
#define HWIO_GCC_GPLL8_TEST_CTL_U_OVERRIDE_FINE_FCW_SHFT                                                 0x10
#define HWIO_GCC_GPLL8_TEST_CTL_U_REG_COARSE_FCW_BMSK                                                  0xfe00
#define HWIO_GCC_GPLL8_TEST_CTL_U_REG_COARSE_FCW_SHFT                                                     0x9
#define HWIO_GCC_GPLL8_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_BMSK                                          0x100
#define HWIO_GCC_GPLL8_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_SHFT                                            0x8
#define HWIO_GCC_GPLL8_TEST_CTL_U_PROCESS_CALIB_WORD_BMSK                                                0xe0
#define HWIO_GCC_GPLL8_TEST_CTL_U_PROCESS_CALIB_WORD_SHFT                                                 0x5
#define HWIO_GCC_GPLL8_TEST_CTL_U_OVERRIDE_CALIB_WORD_BMSK                                               0x10
#define HWIO_GCC_GPLL8_TEST_CTL_U_OVERRIDE_CALIB_WORD_SHFT                                                0x4
#define HWIO_GCC_GPLL8_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_BMSK                                             0x8
#define HWIO_GCC_GPLL8_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_SHFT                                             0x3
#define HWIO_GCC_GPLL8_TEST_CTL_U_DISABLE_LFSR_BMSK                                                       0x4
#define HWIO_GCC_GPLL8_TEST_CTL_U_DISABLE_LFSR_SHFT                                                       0x2
#define HWIO_GCC_GPLL8_TEST_CTL_U_SKIP_FINE_TUNE_BMSK                                                     0x2
#define HWIO_GCC_GPLL8_TEST_CTL_U_SKIP_FINE_TUNE_SHFT                                                     0x1
#define HWIO_GCC_GPLL8_TEST_CTL_U_SKIP_FAST_LOCK_BMSK                                                     0x1
#define HWIO_GCC_GPLL8_TEST_CTL_U_SKIP_FAST_LOCK_SHFT                                                     0x0

#define HWIO_GCC_GPLL8_TEST_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b02c)
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL8_TEST_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL8_TEST_CTL_U1_ADDR)
#define HWIO_GCC_GPLL8_TEST_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_TEST_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL8_TEST_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_TEST_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL8_TEST_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_TEST_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL8_TEST_CTL_U1_IN)
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL8_TEST_CTL_U1_FLL_COUNT_DISABLE_BMSK                                          0x20000000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_FLL_COUNT_DISABLE_SHFT                                                0x1d
#define HWIO_GCC_GPLL8_TEST_CTL_U1_FLL_COUNT_IN_DIV2_BMSK                                          0x10000000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_FLL_COUNT_IN_DIV2_SHFT                                                0x1c
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL8_TEST_CTL_U1_SILENCE_REF_OUTBUF_BMSK                                           0x400000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_SILENCE_REF_OUTBUF_SHFT                                               0x16
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL8_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_BMSK                                         0x40000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_SHFT                                            0x12
#define HWIO_GCC_GPLL8_TEST_CTL_U1_REF_CLK_SEL_BMSK                                                   0x20000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_REF_CLK_SEL_SHFT                                                      0x11
#define HWIO_GCC_GPLL8_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_BMSK                                     0x10000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_SHFT                                        0x10
#define HWIO_GCC_GPLL8_TEST_CTL_U1_DIS_AMP_STARTUP_BMSK                                                0x8000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_DIS_AMP_STARTUP_SHFT                                                   0xf
#define HWIO_GCC_GPLL8_TEST_CTL_U1_DISABLE_CLAMP_BMSK                                                  0x4000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_DISABLE_CLAMP_SHFT                                                     0xe
#define HWIO_GCC_GPLL8_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_BMSK                                        0x2000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_SHFT                                           0xd
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL8_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_BMSK                                          0x80
#define HWIO_GCC_GPLL8_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_SHFT                                           0x7
#define HWIO_GCC_GPLL8_TEST_CTL_U1_ENABLE_TRAINING_SEQ_BMSK                                              0x40
#define HWIO_GCC_GPLL8_TEST_CTL_U1_ENABLE_TRAINING_SEQ_SHFT                                               0x6
#define HWIO_GCC_GPLL8_TEST_CTL_U1_STATUS_REG_EN_BMSK                                                    0x20
#define HWIO_GCC_GPLL8_TEST_CTL_U1_STATUS_REG_EN_SHFT                                                     0x5
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL8_TEST_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL8_TEST_CTL_U1_CASC_DAC_FCW_MSBS_BMSK                                                 0x3
#define HWIO_GCC_GPLL8_TEST_CTL_U1_CASC_DAC_FCW_MSBS_SHFT                                                 0x0

#define HWIO_GCC_GPLL8_STATUS_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b030)
#define HWIO_GCC_GPLL8_STATUS_RMSK                                                                 0xffffffff
#define HWIO_GCC_GPLL8_STATUS_IN          \
        in_dword(HWIO_GCC_GPLL8_STATUS_ADDR)
#define HWIO_GCC_GPLL8_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_STATUS_ADDR, m)
#define HWIO_GCC_GPLL8_STATUS_STATUS_31_0_BMSK                                                     0xffffffff
#define HWIO_GCC_GPLL8_STATUS_STATUS_31_0_SHFT                                                            0x0

#define HWIO_GCC_GPLL8_FREQ_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b034)
#define HWIO_GCC_GPLL8_FREQ_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL8_FREQ_CTL_IN          \
        in_dword(HWIO_GCC_GPLL8_FREQ_CTL_ADDR)
#define HWIO_GCC_GPLL8_FREQ_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_FREQ_CTL_ADDR, m)
#define HWIO_GCC_GPLL8_FREQ_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_FREQ_CTL_ADDR,v)
#define HWIO_GCC_GPLL8_FREQ_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_FREQ_CTL_ADDR,m,v,HWIO_GCC_GPLL8_FREQ_CTL_IN)
#define HWIO_GCC_GPLL8_FREQ_CTL_FREQUENCY_CTL_WORD_BMSK                                            0xffffffff
#define HWIO_GCC_GPLL8_FREQ_CTL_FREQUENCY_CTL_WORD_SHFT                                                   0x0

#define HWIO_GCC_GPLL8_OPMODE_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b038)
#define HWIO_GCC_GPLL8_OPMODE_RMSK                                                                        0x7
#define HWIO_GCC_GPLL8_OPMODE_IN          \
        in_dword(HWIO_GCC_GPLL8_OPMODE_ADDR)
#define HWIO_GCC_GPLL8_OPMODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_OPMODE_ADDR, m)
#define HWIO_GCC_GPLL8_OPMODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_OPMODE_ADDR,v)
#define HWIO_GCC_GPLL8_OPMODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_OPMODE_ADDR,m,v,HWIO_GCC_GPLL8_OPMODE_IN)
#define HWIO_GCC_GPLL8_OPMODE_PLL_OPMODE_BMSK                                                             0x7
#define HWIO_GCC_GPLL8_OPMODE_PLL_OPMODE_SHFT                                                             0x0

#define HWIO_GCC_GPLL8_STATE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b03c)
#define HWIO_GCC_GPLL8_STATE_RMSK                                                                         0x7
#define HWIO_GCC_GPLL8_STATE_IN          \
        in_dword(HWIO_GCC_GPLL8_STATE_ADDR)
#define HWIO_GCC_GPLL8_STATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_STATE_ADDR, m)
#define HWIO_GCC_GPLL8_STATE_PLL_STATE_BMSK                                                               0x7
#define HWIO_GCC_GPLL8_STATE_PLL_STATE_SHFT                                                               0x0

#define HWIO_GCC_GPLL8_ALPHA_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b040)
#define HWIO_GCC_GPLL8_ALPHA_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL8_ALPHA_VAL_IN          \
        in_dword(HWIO_GCC_GPLL8_ALPHA_VAL_ADDR)
#define HWIO_GCC_GPLL8_ALPHA_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_ALPHA_VAL_ADDR, m)
#define HWIO_GCC_GPLL8_ALPHA_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_ALPHA_VAL_ADDR,v)
#define HWIO_GCC_GPLL8_ALPHA_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_ALPHA_VAL_ADDR,m,v,HWIO_GCC_GPLL8_ALPHA_VAL_IN)
#define HWIO_GCC_GPLL8_ALPHA_VAL_PLL_ALPHA_VAL_BMSK                                                    0xffff
#define HWIO_GCC_GPLL8_ALPHA_VAL_PLL_ALPHA_VAL_SHFT                                                       0x0

#define HWIO_GCC_GPLL8_SPARE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b044)
#define HWIO_GCC_GPLL8_SPARE_RMSK                                                                        0xff
#define HWIO_GCC_GPLL8_SPARE_IN          \
        in_dword(HWIO_GCC_GPLL8_SPARE_ADDR)
#define HWIO_GCC_GPLL8_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_SPARE_ADDR, m)
#define HWIO_GCC_GPLL8_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_SPARE_ADDR,v)
#define HWIO_GCC_GPLL8_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_SPARE_ADDR,m,v,HWIO_GCC_GPLL8_SPARE_IN)
#define HWIO_GCC_GPLL8_SPARE_SPARE_OUTPUTS_BMSK                                                          0xf0
#define HWIO_GCC_GPLL8_SPARE_SPARE_OUTPUTS_SHFT                                                           0x4
#define HWIO_GCC_GPLL8_SPARE_SPARE_INPUTS_BMSK                                                            0xf
#define HWIO_GCC_GPLL8_SPARE_SPARE_INPUTS_SHFT                                                            0x0

#define HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b048)
#define HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_RMSK                                                              0xff
#define HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_IN          \
        in_dword(HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_ADDR)
#define HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_ADDR, m)
#define HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_ADDR,v)
#define HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_ADDR,m,v,HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_IN)
#define HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_BMSK                                              0xff
#define HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_SHFT                                               0x0

#define HWIO_GCC_GPLL8_SSC_NUM_STEPS_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b04c)
#define HWIO_GCC_GPLL8_SSC_NUM_STEPS_RMSK                                                                 0xf
#define HWIO_GCC_GPLL8_SSC_NUM_STEPS_IN          \
        in_dword(HWIO_GCC_GPLL8_SSC_NUM_STEPS_ADDR)
#define HWIO_GCC_GPLL8_SSC_NUM_STEPS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_SSC_NUM_STEPS_ADDR, m)
#define HWIO_GCC_GPLL8_SSC_NUM_STEPS_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_SSC_NUM_STEPS_ADDR,v)
#define HWIO_GCC_GPLL8_SSC_NUM_STEPS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_SSC_NUM_STEPS_ADDR,m,v,HWIO_GCC_GPLL8_SSC_NUM_STEPS_IN)
#define HWIO_GCC_GPLL8_SSC_NUM_STEPS_SSC_NUM_STEPS_BMSK                                                   0xf
#define HWIO_GCC_GPLL8_SSC_NUM_STEPS_SSC_NUM_STEPS_SHFT                                                   0x0

#define HWIO_GCC_GPLL8_SSC_UPDATE_RATE_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0001b050)
#define HWIO_GCC_GPLL8_SSC_UPDATE_RATE_RMSK                                                               0xf
#define HWIO_GCC_GPLL8_SSC_UPDATE_RATE_IN          \
        in_dword(HWIO_GCC_GPLL8_SSC_UPDATE_RATE_ADDR)
#define HWIO_GCC_GPLL8_SSC_UPDATE_RATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL8_SSC_UPDATE_RATE_ADDR, m)
#define HWIO_GCC_GPLL8_SSC_UPDATE_RATE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL8_SSC_UPDATE_RATE_ADDR,v)
#define HWIO_GCC_GPLL8_SSC_UPDATE_RATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL8_SSC_UPDATE_RATE_ADDR,m,v,HWIO_GCC_GPLL8_SSC_UPDATE_RATE_IN)
#define HWIO_GCC_GPLL8_SSC_UPDATE_RATE_SSC_UPDATE_RATE_BMSK                                               0xf
#define HWIO_GCC_GPLL8_SSC_UPDATE_RATE_SSC_UPDATE_RATE_SHFT                                               0x0

#define HWIO_GCC_GPLL9_MODE_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c000)
#define HWIO_GCC_GPLL9_MODE_RMSK                                                                   0xffffffff
#define HWIO_GCC_GPLL9_MODE_IN          \
        in_dword(HWIO_GCC_GPLL9_MODE_ADDR)
#define HWIO_GCC_GPLL9_MODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_MODE_ADDR, m)
#define HWIO_GCC_GPLL9_MODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_MODE_ADDR,v)
#define HWIO_GCC_GPLL9_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_MODE_ADDR,m,v,HWIO_GCC_GPLL9_MODE_IN)
#define HWIO_GCC_GPLL9_MODE_PLL_LOCK_DET_BMSK                                                      0x80000000
#define HWIO_GCC_GPLL9_MODE_PLL_LOCK_DET_SHFT                                                            0x1f
#define HWIO_GCC_GPLL9_MODE_PLL_ACTIVE_FLAG_BMSK                                                   0x40000000
#define HWIO_GCC_GPLL9_MODE_PLL_ACTIVE_FLAG_SHFT                                                         0x1e
#define HWIO_GCC_GPLL9_MODE_PLL_ACK_LATCH_BMSK                                                     0x20000000
#define HWIO_GCC_GPLL9_MODE_PLL_ACK_LATCH_SHFT                                                           0x1d
#define HWIO_GCC_GPLL9_MODE_PLL_LOCK_DET_FINE_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL9_MODE_PLL_LOCK_DET_FINE_SHFT                                                       0x1c
#define HWIO_GCC_GPLL9_MODE_PCAL_DONE_BMSK                                                          0x8000000
#define HWIO_GCC_GPLL9_MODE_PCAL_DONE_SHFT                                                               0x1b
#define HWIO_GCC_GPLL9_MODE_RESERVE_BITS26_25_BMSK                                                  0x6000000
#define HWIO_GCC_GPLL9_MODE_RESERVE_BITS26_25_SHFT                                                       0x19
#define HWIO_GCC_GPLL9_MODE_FSM_LEGACY_MODE_BMSK                                                    0x1000000
#define HWIO_GCC_GPLL9_MODE_FSM_LEGACY_MODE_SHFT                                                         0x18
#define HWIO_GCC_GPLL9_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_BMSK                                          0x800000
#define HWIO_GCC_GPLL9_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_SHFT                                              0x17
#define HWIO_GCC_GPLL9_MODE_PLL_UPDATE_BMSK                                                          0x400000
#define HWIO_GCC_GPLL9_MODE_PLL_UPDATE_SHFT                                                              0x16
#define HWIO_GCC_GPLL9_MODE_PLL_VOTE_FSM_RESET_BMSK                                                  0x200000
#define HWIO_GCC_GPLL9_MODE_PLL_VOTE_FSM_RESET_SHFT                                                      0x15
#define HWIO_GCC_GPLL9_MODE_PLL_VOTE_FSM_ENA_BMSK                                                    0x100000
#define HWIO_GCC_GPLL9_MODE_PLL_VOTE_FSM_ENA_SHFT                                                        0x14
#define HWIO_GCC_GPLL9_MODE_PLL_BIAS_COUNT_BMSK                                                       0xfc000
#define HWIO_GCC_GPLL9_MODE_PLL_BIAS_COUNT_SHFT                                                           0xe
#define HWIO_GCC_GPLL9_MODE_PLL_LOCK_COUNT_BMSK                                                        0x3f00
#define HWIO_GCC_GPLL9_MODE_PLL_LOCK_COUNT_SHFT                                                           0x8
#define HWIO_GCC_GPLL9_MODE_RESERVE_BIT7_BMSK                                                            0x80
#define HWIO_GCC_GPLL9_MODE_RESERVE_BIT7_SHFT                                                             0x7
#define HWIO_GCC_GPLL9_MODE_OUT_TEST_HW_CTL_BMSK                                                         0x40
#define HWIO_GCC_GPLL9_MODE_OUT_TEST_HW_CTL_SHFT                                                          0x6
#define HWIO_GCC_GPLL9_MODE_OUT_ODD_HW_CTL_BMSK                                                          0x20
#define HWIO_GCC_GPLL9_MODE_OUT_ODD_HW_CTL_SHFT                                                           0x5
#define HWIO_GCC_GPLL9_MODE_OUT_EVEN_HW_CTL_BMSK                                                         0x10
#define HWIO_GCC_GPLL9_MODE_OUT_EVEN_HW_CTL_SHFT                                                          0x4
#define HWIO_GCC_GPLL9_MODE_OUT_MAIN_HW_CTL_BMSK                                                          0x8
#define HWIO_GCC_GPLL9_MODE_OUT_MAIN_HW_CTL_SHFT                                                          0x3
#define HWIO_GCC_GPLL9_MODE_PLL_RESET_N_BMSK                                                              0x4
#define HWIO_GCC_GPLL9_MODE_PLL_RESET_N_SHFT                                                              0x2
#define HWIO_GCC_GPLL9_MODE_RESERVE_BIT1_BMSK                                                             0x2
#define HWIO_GCC_GPLL9_MODE_RESERVE_BIT1_SHFT                                                             0x1
#define HWIO_GCC_GPLL9_MODE_PLL_OUTCTRL_BMSK                                                              0x1
#define HWIO_GCC_GPLL9_MODE_PLL_OUTCTRL_SHFT                                                              0x0

#define HWIO_GCC_GPLL9_L_VAL_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c004)
#define HWIO_GCC_GPLL9_L_VAL_RMSK                                                                      0xffff
#define HWIO_GCC_GPLL9_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL9_L_VAL_ADDR)
#define HWIO_GCC_GPLL9_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL9_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL9_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_L_VAL_ADDR,m,v,HWIO_GCC_GPLL9_L_VAL_IN)
#define HWIO_GCC_GPLL9_L_VAL_PLL_L_BMSK                                                                0xffff
#define HWIO_GCC_GPLL9_L_VAL_PLL_L_SHFT                                                                   0x0

#define HWIO_GCC_GPLL9_CAL_L_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c008)
#define HWIO_GCC_GPLL9_CAL_L_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL9_CAL_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL9_CAL_L_VAL_ADDR)
#define HWIO_GCC_GPLL9_CAL_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_CAL_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL9_CAL_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_CAL_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL9_CAL_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_CAL_L_VAL_ADDR,m,v,HWIO_GCC_GPLL9_CAL_L_VAL_IN)
#define HWIO_GCC_GPLL9_CAL_L_VAL_PLL_CAL_L_BMSK                                                        0xffff
#define HWIO_GCC_GPLL9_CAL_L_VAL_PLL_CAL_L_SHFT                                                           0x0

#define HWIO_GCC_GPLL9_USER_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c00c)
#define HWIO_GCC_GPLL9_USER_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL9_USER_CTL_IN          \
        in_dword(HWIO_GCC_GPLL9_USER_CTL_ADDR)
#define HWIO_GCC_GPLL9_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_USER_CTL_ADDR, m)
#define HWIO_GCC_GPLL9_USER_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_USER_CTL_ADDR,v)
#define HWIO_GCC_GPLL9_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_USER_CTL_ADDR,m,v,HWIO_GCC_GPLL9_USER_CTL_IN)
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT31_BMSK                                                 0x80000000
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT31_SHFT                                                       0x1f
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT30_BMSK                                                 0x40000000
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT30_SHFT                                                       0x1e
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT29_BMSK                                                 0x20000000
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT29_SHFT                                                       0x1d
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT28_BMSK                                                 0x10000000
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT28_SHFT                                                       0x1c
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT27_BMSK                                                  0x8000000
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT27_SHFT                                                       0x1b
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT26_BMSK                                                  0x4000000
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT26_SHFT                                                       0x1a
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT25_BMSK                                                  0x2000000
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT25_SHFT                                                       0x19
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT24_BMSK                                                  0x1000000
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT24_SHFT                                                       0x18
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT23_BMSK                                                   0x800000
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT23_SHFT                                                       0x17
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT22_BMSK                                                   0x400000
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT22_SHFT                                                       0x16
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT21_BMSK                                                   0x200000
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT21_SHFT                                                       0x15
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT20_BMSK                                                   0x100000
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT20_SHFT                                                       0x14
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL9_USER_CTL_PRE_DIV_RATIO_BMSK                                                    0x70000
#define HWIO_GCC_GPLL9_USER_CTL_PRE_DIV_RATIO_SHFT                                                       0x10
#define HWIO_GCC_GPLL9_USER_CTL_POST_DIV_RATIO_ODD_BMSK                                                0xf000
#define HWIO_GCC_GPLL9_USER_CTL_POST_DIV_RATIO_ODD_SHFT                                                   0xc
#define HWIO_GCC_GPLL9_USER_CTL_POST_DIV_RATIO_EVEN_BMSK                                                0xf00
#define HWIO_GCC_GPLL9_USER_CTL_POST_DIV_RATIO_EVEN_SHFT                                                  0x8
#define HWIO_GCC_GPLL9_USER_CTL_OUT_CLK_POLARITY_BMSK                                                    0x80
#define HWIO_GCC_GPLL9_USER_CTL_OUT_CLK_POLARITY_SHFT                                                     0x7
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT6_BMSK                                                        0x40
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT6_SHFT                                                         0x6
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT5_BMSK                                                        0x20
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT5_SHFT                                                         0x5
#define HWIO_GCC_GPLL9_USER_CTL_PLLOUT_TEST_BMSK                                                         0x10
#define HWIO_GCC_GPLL9_USER_CTL_PLLOUT_TEST_SHFT                                                          0x4
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT3_BMSK                                                         0x8
#define HWIO_GCC_GPLL9_USER_CTL_RESERVE_BIT3_SHFT                                                         0x3
#define HWIO_GCC_GPLL9_USER_CTL_PLLOUT_ODD_BMSK                                                           0x4
#define HWIO_GCC_GPLL9_USER_CTL_PLLOUT_ODD_SHFT                                                           0x2
#define HWIO_GCC_GPLL9_USER_CTL_PLLOUT_EVEN_BMSK                                                          0x2
#define HWIO_GCC_GPLL9_USER_CTL_PLLOUT_EVEN_SHFT                                                          0x1
#define HWIO_GCC_GPLL9_USER_CTL_PLLOUT_MAIN_BMSK                                                          0x1
#define HWIO_GCC_GPLL9_USER_CTL_PLLOUT_MAIN_SHFT                                                          0x0

#define HWIO_GCC_GPLL9_USER_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c010)
#define HWIO_GCC_GPLL9_USER_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL9_USER_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL9_USER_CTL_U_ADDR)
#define HWIO_GCC_GPLL9_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_USER_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL9_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_USER_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL9_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_USER_CTL_U_ADDR,m,v,HWIO_GCC_GPLL9_USER_CTL_U_IN)
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT63_BMSK                                               0x80000000
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT63_SHFT                                                     0x1f
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT62_BMSK                                               0x40000000
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT62_SHFT                                                     0x1e
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT61_BMSK                                               0x20000000
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT61_SHFT                                                     0x1d
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT60_BMSK                                               0x10000000
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT60_SHFT                                                     0x1c
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT59_BMSK                                                0x8000000
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT59_SHFT                                                     0x1b
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT58_BMSK                                                0x4000000
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT58_SHFT                                                     0x1a
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT57_BMSK                                                0x2000000
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT57_SHFT                                                     0x19
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT56_BMSK                                                0x1000000
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT56_SHFT                                                     0x18
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT55_BMSK                                                 0x800000
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT55_SHFT                                                     0x17
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT54_BMSK                                                 0x400000
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT54_SHFT                                                     0x16
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT53_BMSK                                                 0x200000
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT53_SHFT                                                     0x15
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT52_BMSK                                                 0x100000
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT52_SHFT                                                     0x14
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT51_BMSK                                                  0x80000
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT51_SHFT                                                     0x13
#define HWIO_GCC_GPLL9_USER_CTL_U_LOCK_DETECTOR_SELECTION_BMSK                                        0x40000
#define HWIO_GCC_GPLL9_USER_CTL_U_LOCK_DETECTOR_SELECTION_SHFT                                           0x12
#define HWIO_GCC_GPLL9_USER_CTL_U_TYPE_2_MODE_SELECTION_BMSK                                          0x20000
#define HWIO_GCC_GPLL9_USER_CTL_U_TYPE_2_MODE_SELECTION_SHFT                                             0x11
#define HWIO_GCC_GPLL9_USER_CTL_U_BANG_BANG_MODE_SELECTION_BMSK                                       0x10000
#define HWIO_GCC_GPLL9_USER_CTL_U_BANG_BANG_MODE_SELECTION_SHFT                                          0x10
#define HWIO_GCC_GPLL9_USER_CTL_U_FRAC_FORMAT_SEL_BMSK                                                 0x8000
#define HWIO_GCC_GPLL9_USER_CTL_U_FRAC_FORMAT_SEL_SHFT                                                    0xf
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT46_BMSK                                                   0x4000
#define HWIO_GCC_GPLL9_USER_CTL_U_RESERVE_BIT46_SHFT                                                      0xe
#define HWIO_GCC_GPLL9_USER_CTL_U_REF_CLK_AT_OUT_BMSK                                                  0x2000
#define HWIO_GCC_GPLL9_USER_CTL_U_REF_CLK_AT_OUT_SHFT                                                     0xd
#define HWIO_GCC_GPLL9_USER_CTL_U_SCALE_FREQ_ON_RESTART_BMSK                                           0x1800
#define HWIO_GCC_GPLL9_USER_CTL_U_SCALE_FREQ_ON_RESTART_SHFT                                              0xb
#define HWIO_GCC_GPLL9_USER_CTL_U_LATCH_INTERFACE_BYPASS_BMSK                                           0x400
#define HWIO_GCC_GPLL9_USER_CTL_U_LATCH_INTERFACE_BYPASS_SHFT                                             0xa
#define HWIO_GCC_GPLL9_USER_CTL_U_STATUS_REGISTER_BMSK                                                  0x3e0
#define HWIO_GCC_GPLL9_USER_CTL_U_STATUS_REGISTER_SHFT                                                    0x5
#define HWIO_GCC_GPLL9_USER_CTL_U_WRITE_STATE_EN_BMSK                                                    0x10
#define HWIO_GCC_GPLL9_USER_CTL_U_WRITE_STATE_EN_SHFT                                                     0x4
#define HWIO_GCC_GPLL9_USER_CTL_U_CALIB_CTRL_BMSK                                                         0xe
#define HWIO_GCC_GPLL9_USER_CTL_U_CALIB_CTRL_SHFT                                                         0x1
#define HWIO_GCC_GPLL9_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_BMSK                                             0x1
#define HWIO_GCC_GPLL9_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_SHFT                                             0x0

#define HWIO_GCC_GPLL9_USER_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c014)
#define HWIO_GCC_GPLL9_USER_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL9_USER_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL9_USER_CTL_U1_ADDR)
#define HWIO_GCC_GPLL9_USER_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_USER_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL9_USER_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_USER_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL9_USER_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_USER_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL9_USER_CTL_U1_IN)
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT93_BMSK                                              0x20000000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT93_SHFT                                                    0x1d
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT92_BMSK                                              0x10000000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT92_SHFT                                                    0x1c
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT86_BMSK                                                0x400000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT86_SHFT                                                    0x16
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT82_BMSK                                                 0x40000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT82_SHFT                                                    0x12
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT81_BMSK                                                 0x20000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT81_SHFT                                                    0x11
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT80_BMSK                                                 0x10000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT80_SHFT                                                    0x10
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT79_BMSK                                                  0x8000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT79_SHFT                                                     0xf
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT78_BMSK                                                  0x4000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT78_SHFT                                                     0xe
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT77_BMSK                                                  0x2000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT77_SHFT                                                     0xd
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT71_BMSK                                                    0x80
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT71_SHFT                                                     0x7
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT70_BMSK                                                    0x40
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT70_SHFT                                                     0x6
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT69_BMSK                                                    0x20
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT69_SHFT                                                     0x5
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT65_BMSK                                                     0x2
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT65_SHFT                                                     0x1
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT64_BMSK                                                     0x1
#define HWIO_GCC_GPLL9_USER_CTL_U1_RESERVE_BIT64_SHFT                                                     0x0

#define HWIO_GCC_GPLL9_CONFIG_CTL_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c018)
#define HWIO_GCC_GPLL9_CONFIG_CTL_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL9_CONFIG_CTL_IN          \
        in_dword(HWIO_GCC_GPLL9_CONFIG_CTL_ADDR)
#define HWIO_GCC_GPLL9_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_CONFIG_CTL_ADDR, m)
#define HWIO_GCC_GPLL9_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_CONFIG_CTL_ADDR,v)
#define HWIO_GCC_GPLL9_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_CONFIG_CTL_ADDR,m,v,HWIO_GCC_GPLL9_CONFIG_CTL_IN)
#define HWIO_GCC_GPLL9_CONFIG_CTL_FINE_LDC_THRESHOLD_BMSK                                          0xfc000000
#define HWIO_GCC_GPLL9_CONFIG_CTL_FINE_LDC_THRESHOLD_SHFT                                                0x1a
#define HWIO_GCC_GPLL9_CONFIG_CTL_COARSE_LDC_THRESHOLD_BMSK                                         0x3c00000
#define HWIO_GCC_GPLL9_CONFIG_CTL_COARSE_LDC_THRESHOLD_SHFT                                              0x16
#define HWIO_GCC_GPLL9_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_BMSK                                 0x3c0000
#define HWIO_GCC_GPLL9_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_SHFT                                     0x12
#define HWIO_GCC_GPLL9_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_BMSK                                  0x3c000
#define HWIO_GCC_GPLL9_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_SHFT                                      0xe
#define HWIO_GCC_GPLL9_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_BMSK                                         0x3800
#define HWIO_GCC_GPLL9_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_SHFT                                            0xb
#define HWIO_GCC_GPLL9_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_BMSK                                        0x700
#define HWIO_GCC_GPLL9_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_SHFT                                          0x8
#define HWIO_GCC_GPLL9_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_BMSK                                              0xf0
#define HWIO_GCC_GPLL9_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_SHFT                                               0x4
#define HWIO_GCC_GPLL9_CONFIG_CTL_FWD_GAIN_KFN_BMSK                                                       0xf
#define HWIO_GCC_GPLL9_CONFIG_CTL_FWD_GAIN_KFN_SHFT                                                       0x0

#define HWIO_GCC_GPLL9_CONFIG_CTL_U_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c01c)
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_RMSK                                                           0xffffffff
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL9_CONFIG_CTL_U_ADDR)
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_CONFIG_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_CONFIG_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_CONFIG_CTL_U_ADDR,m,v,HWIO_GCC_GPLL9_CONFIG_CTL_U_IN)
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_BIST_CFG_BMSK                                                  0xffff0000
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_BIST_CFG_SHFT                                                        0x10
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_BMSK                                       0xc000
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_SHFT                                          0xe
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_OSC_SETTLING_TIME_BMSK                                             0x3000
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_OSC_SETTLING_TIME_SHFT                                                0xc
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_BMSK                                            0xc00
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_SHFT                                              0xa
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_CASC_CURRENT_CTL_B_BMSK                                             0x380
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_CASC_CURRENT_CTL_B_SHFT                                               0x7
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_BMSK                                     0x40
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_SHFT                                      0x6
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_BMSK                                            0x30
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_SHFT                                             0x4
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_LDET_THRESH_SCALE_BMSK                                                0x8
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_LDET_THRESH_SCALE_SHFT                                                0x3
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_DCO_STARTUP_CONFIG_BMSK                                               0x6
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_DCO_STARTUP_CONFIG_SHFT                                               0x1
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_BMSK                                          0x1
#define HWIO_GCC_GPLL9_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_SHFT                                          0x0

#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c020)
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_RMSK                                                          0xffffffff
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL9_CONFIG_CTL_U1_ADDR)
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_CONFIG_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_CONFIG_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_CONFIG_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL9_CONFIG_CTL_U1_IN)
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BB_CAL_THRESHOLD_BMSK                                         0xc0000000
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BB_CAL_THRESHOLD_SHFT                                               0x1e
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_PCODE_OFFSET_BMSK                                             0x38000000
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_PCODE_OFFSET_SHFT                                                   0x1b
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_COUNTER_BLANK_BMSK                                             0x4000000
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_COUNTER_BLANK_SHFT                                                  0x1a
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BB_RESYNC_EDGE_BMSK                                            0x2000000
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BB_RESYNC_EDGE_SHFT                                                 0x19
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BB_RESYNC_SEL_BMSK                                             0x1000000
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BB_RESYNC_SEL_SHFT                                                  0x18
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_BMSK                                        0xc00000
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_SHFT                                            0x16
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BB_LOCK_THRESH_BMSK                                             0x380000
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BB_LOCK_THRESH_SHFT                                                 0x13
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_RESERVE_BIT82_BMSK                                               0x40000
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_RESERVE_BIT82_SHFT                                                  0x12
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_BMSK                                          0x30000
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_SHFT                                             0x10
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_BMSK                                            0xc000
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_SHFT                                               0xe
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BB_CAL_EN_BMSK                                                    0x2000
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BB_CAL_EN_SHFT                                                       0xd
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_BMSK                                      0x1800
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_SHFT                                         0xb
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BBMODE_INT_GAIN_BMSK                                               0x780
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BBMODE_INT_GAIN_SHFT                                                 0x7
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BBMODE_PROP_GAIN_BMSK                                               0x78
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_BBMODE_PROP_GAIN_SHFT                                                0x3
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_TDC_SELECTION_BMSK                                                   0x4
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_TDC_SELECTION_SHFT                                                   0x2
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_RESERVE_BIT65_BMSK                                                   0x2
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_RESERVE_BIT65_SHFT                                                   0x1
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_FORCE_DSM_ON_BMSK                                                    0x1
#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_FORCE_DSM_ON_SHFT                                                    0x0

#define HWIO_GCC_GPLL9_TEST_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c024)
#define HWIO_GCC_GPLL9_TEST_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL9_TEST_CTL_IN          \
        in_dword(HWIO_GCC_GPLL9_TEST_CTL_ADDR)
#define HWIO_GCC_GPLL9_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_TEST_CTL_ADDR, m)
#define HWIO_GCC_GPLL9_TEST_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_TEST_CTL_ADDR,v)
#define HWIO_GCC_GPLL9_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_TEST_CTL_ADDR,m,v,HWIO_GCC_GPLL9_TEST_CTL_IN)
#define HWIO_GCC_GPLL9_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_BMSK                                       0xc0000000
#define HWIO_GCC_GPLL9_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_SHFT                                             0x1e
#define HWIO_GCC_GPLL9_TEST_CTL_BYPASS_FIRST_ORDER_DSM_BMSK                                        0x20000000
#define HWIO_GCC_GPLL9_TEST_CTL_BYPASS_FIRST_ORDER_DSM_SHFT                                              0x1d
#define HWIO_GCC_GPLL9_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_BMSK                                   0x18000000
#define HWIO_GCC_GPLL9_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_SHFT                                         0x1b
#define HWIO_GCC_GPLL9_TEST_CTL_GLITCH_PREVENTION_DIS_BMSK                                          0x4000000
#define HWIO_GCC_GPLL9_TEST_CTL_GLITCH_PREVENTION_DIS_SHFT                                               0x1a
#define HWIO_GCC_GPLL9_TEST_CTL_ATEST_ISCALE_BMSK                                                   0x3000000
#define HWIO_GCC_GPLL9_TEST_CTL_ATEST_ISCALE_SHFT                                                        0x18
#define HWIO_GCC_GPLL9_TEST_CTL_PLL_TEST_OUT_SEL_BMSK                                                0xf00000
#define HWIO_GCC_GPLL9_TEST_CTL_PLL_TEST_OUT_SEL_SHFT                                                    0x14
#define HWIO_GCC_GPLL9_TEST_CTL_RESERVE_BIT19_BMSK                                                    0x80000
#define HWIO_GCC_GPLL9_TEST_CTL_RESERVE_BIT19_SHFT                                                       0x13
#define HWIO_GCC_GPLL9_TEST_CTL_DIV2_NMO_EN_BMSK                                                      0x40000
#define HWIO_GCC_GPLL9_TEST_CTL_DIV2_NMO_EN_SHFT                                                         0x12
#define HWIO_GCC_GPLL9_TEST_CTL_NMO_OSC_SEL_BMSK                                                      0x30000
#define HWIO_GCC_GPLL9_TEST_CTL_NMO_OSC_SEL_SHFT                                                         0x10
#define HWIO_GCC_GPLL9_TEST_CTL_NOISE_MAG_BMSK                                                         0xe000
#define HWIO_GCC_GPLL9_TEST_CTL_NOISE_MAG_SHFT                                                            0xd
#define HWIO_GCC_GPLL9_TEST_CTL_NOISE_GEN_EN_BMSK                                                      0x1000
#define HWIO_GCC_GPLL9_TEST_CTL_NOISE_GEN_EN_SHFT                                                         0xc
#define HWIO_GCC_GPLL9_TEST_CTL_DISABLE_DCAPS_BMSK                                                      0x800
#define HWIO_GCC_GPLL9_TEST_CTL_DISABLE_DCAPS_SHFT                                                        0xb
#define HWIO_GCC_GPLL9_TEST_CTL_RESERVE_BIT10_BMSK                                                      0x400
#define HWIO_GCC_GPLL9_TEST_CTL_RESERVE_BIT10_SHFT                                                        0xa
#define HWIO_GCC_GPLL9_TEST_CTL_RESERVE_BIT9_BMSK                                                       0x200
#define HWIO_GCC_GPLL9_TEST_CTL_RESERVE_BIT9_SHFT                                                         0x9
#define HWIO_GCC_GPLL9_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_BMSK                                            0x100
#define HWIO_GCC_GPLL9_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_SHFT                                              0x8
#define HWIO_GCC_GPLL9_TEST_CTL_EN_VDD_TEST_BMSK                                                         0x80
#define HWIO_GCC_GPLL9_TEST_CTL_EN_VDD_TEST_SHFT                                                          0x7
#define HWIO_GCC_GPLL9_TEST_CTL_EN_VREG_TEST_BMSK                                                        0x40
#define HWIO_GCC_GPLL9_TEST_CTL_EN_VREG_TEST_SHFT                                                         0x6
#define HWIO_GCC_GPLL9_TEST_CTL_EN_VREF_TEST_BMSK                                                        0x20
#define HWIO_GCC_GPLL9_TEST_CTL_EN_VREF_TEST_SHFT                                                         0x5
#define HWIO_GCC_GPLL9_TEST_CTL_EN_VDCO_TEST_BMSK                                                        0x10
#define HWIO_GCC_GPLL9_TEST_CTL_EN_VDCO_TEST_SHFT                                                         0x4
#define HWIO_GCC_GPLL9_TEST_CTL_BYPASS_ATEST_BUFFER_BMSK                                                  0x8
#define HWIO_GCC_GPLL9_TEST_CTL_BYPASS_ATEST_BUFFER_SHFT                                                  0x3
#define HWIO_GCC_GPLL9_TEST_CTL_EN_IVCO_TEST_BMSK                                                         0x4
#define HWIO_GCC_GPLL9_TEST_CTL_EN_IVCO_TEST_SHFT                                                         0x2
#define HWIO_GCC_GPLL9_TEST_CTL_ATEST1_EN_BMSK                                                            0x2
#define HWIO_GCC_GPLL9_TEST_CTL_ATEST1_EN_SHFT                                                            0x1
#define HWIO_GCC_GPLL9_TEST_CTL_ATEST0_EN_BMSK                                                            0x1
#define HWIO_GCC_GPLL9_TEST_CTL_ATEST0_EN_SHFT                                                            0x0

#define HWIO_GCC_GPLL9_TEST_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c028)
#define HWIO_GCC_GPLL9_TEST_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_GPLL9_TEST_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL9_TEST_CTL_U_ADDR)
#define HWIO_GCC_GPLL9_TEST_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_TEST_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL9_TEST_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_TEST_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL9_TEST_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_TEST_CTL_U_ADDR,m,v,HWIO_GCC_GPLL9_TEST_CTL_U_IN)
#define HWIO_GCC_GPLL9_TEST_CTL_U_CASC_DAC_FCW_LSBS_BMSK                                           0xe0000000
#define HWIO_GCC_GPLL9_TEST_CTL_U_CASC_DAC_FCW_LSBS_SHFT                                                 0x1d
#define HWIO_GCC_GPLL9_TEST_CTL_U_OVERRIDE_CASC_DAC_BMSK                                           0x10000000
#define HWIO_GCC_GPLL9_TEST_CTL_U_OVERRIDE_CASC_DAC_SHFT                                                 0x1c
#define HWIO_GCC_GPLL9_TEST_CTL_U_COMP_COARSE_FCW_BMSK                                              0xe000000
#define HWIO_GCC_GPLL9_TEST_CTL_U_COMP_COARSE_FCW_SHFT                                                   0x19
#define HWIO_GCC_GPLL9_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_BMSK                                     0x1800000
#define HWIO_GCC_GPLL9_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_SHFT                                          0x17
#define HWIO_GCC_GPLL9_TEST_CTL_U_FINE_FCW_BMSK                                                      0x7e0000
#define HWIO_GCC_GPLL9_TEST_CTL_U_FINE_FCW_SHFT                                                          0x11
#define HWIO_GCC_GPLL9_TEST_CTL_U_OVERRIDE_FINE_FCW_BMSK                                              0x10000
#define HWIO_GCC_GPLL9_TEST_CTL_U_OVERRIDE_FINE_FCW_SHFT                                                 0x10
#define HWIO_GCC_GPLL9_TEST_CTL_U_REG_COARSE_FCW_BMSK                                                  0xfe00
#define HWIO_GCC_GPLL9_TEST_CTL_U_REG_COARSE_FCW_SHFT                                                     0x9
#define HWIO_GCC_GPLL9_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_BMSK                                          0x100
#define HWIO_GCC_GPLL9_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_SHFT                                            0x8
#define HWIO_GCC_GPLL9_TEST_CTL_U_PROCESS_CALIB_WORD_BMSK                                                0xe0
#define HWIO_GCC_GPLL9_TEST_CTL_U_PROCESS_CALIB_WORD_SHFT                                                 0x5
#define HWIO_GCC_GPLL9_TEST_CTL_U_OVERRIDE_CALIB_WORD_BMSK                                               0x10
#define HWIO_GCC_GPLL9_TEST_CTL_U_OVERRIDE_CALIB_WORD_SHFT                                                0x4
#define HWIO_GCC_GPLL9_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_BMSK                                             0x8
#define HWIO_GCC_GPLL9_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_SHFT                                             0x3
#define HWIO_GCC_GPLL9_TEST_CTL_U_DISABLE_LFSR_BMSK                                                       0x4
#define HWIO_GCC_GPLL9_TEST_CTL_U_DISABLE_LFSR_SHFT                                                       0x2
#define HWIO_GCC_GPLL9_TEST_CTL_U_SKIP_FINE_TUNE_BMSK                                                     0x2
#define HWIO_GCC_GPLL9_TEST_CTL_U_SKIP_FINE_TUNE_SHFT                                                     0x1
#define HWIO_GCC_GPLL9_TEST_CTL_U_SKIP_FAST_LOCK_BMSK                                                     0x1
#define HWIO_GCC_GPLL9_TEST_CTL_U_SKIP_FAST_LOCK_SHFT                                                     0x0

#define HWIO_GCC_GPLL9_TEST_CTL_U1_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c02c)
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL9_TEST_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL9_TEST_CTL_U1_ADDR)
#define HWIO_GCC_GPLL9_TEST_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_TEST_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL9_TEST_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_TEST_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL9_TEST_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_TEST_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL9_TEST_CTL_U1_IN)
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT95_BMSK                                              0x80000000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT95_SHFT                                                    0x1f
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT94_BMSK                                              0x40000000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT94_SHFT                                                    0x1e
#define HWIO_GCC_GPLL9_TEST_CTL_U1_FLL_COUNT_DISABLE_BMSK                                          0x20000000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_FLL_COUNT_DISABLE_SHFT                                                0x1d
#define HWIO_GCC_GPLL9_TEST_CTL_U1_FLL_COUNT_IN_DIV2_BMSK                                          0x10000000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_FLL_COUNT_IN_DIV2_SHFT                                                0x1c
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT91_BMSK                                               0x8000000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT91_SHFT                                                    0x1b
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT90_BMSK                                               0x4000000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT90_SHFT                                                    0x1a
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT89_BMSK                                               0x2000000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT89_SHFT                                                    0x19
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT88_BMSK                                               0x1000000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT88_SHFT                                                    0x18
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT87_BMSK                                                0x800000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT87_SHFT                                                    0x17
#define HWIO_GCC_GPLL9_TEST_CTL_U1_SILENCE_REF_OUTBUF_BMSK                                           0x400000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_SILENCE_REF_OUTBUF_SHFT                                               0x16
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT85_BMSK                                                0x200000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT85_SHFT                                                    0x15
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT84_BMSK                                                0x100000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT84_SHFT                                                    0x14
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT83_BMSK                                                 0x80000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT83_SHFT                                                    0x13
#define HWIO_GCC_GPLL9_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_BMSK                                         0x40000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_SHFT                                            0x12
#define HWIO_GCC_GPLL9_TEST_CTL_U1_REF_CLK_SEL_BMSK                                                   0x20000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_REF_CLK_SEL_SHFT                                                      0x11
#define HWIO_GCC_GPLL9_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_BMSK                                     0x10000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_SHFT                                        0x10
#define HWIO_GCC_GPLL9_TEST_CTL_U1_DIS_AMP_STARTUP_BMSK                                                0x8000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_DIS_AMP_STARTUP_SHFT                                                   0xf
#define HWIO_GCC_GPLL9_TEST_CTL_U1_DISABLE_CLAMP_BMSK                                                  0x4000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_DISABLE_CLAMP_SHFT                                                     0xe
#define HWIO_GCC_GPLL9_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_BMSK                                        0x2000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_SHFT                                           0xd
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT76_BMSK                                                  0x1000
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT76_SHFT                                                     0xc
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT75_BMSK                                                   0x800
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT75_SHFT                                                     0xb
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT74_BMSK                                                   0x400
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT74_SHFT                                                     0xa
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT73_BMSK                                                   0x200
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT73_SHFT                                                     0x9
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT72_BMSK                                                   0x100
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT72_SHFT                                                     0x8
#define HWIO_GCC_GPLL9_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_BMSK                                          0x80
#define HWIO_GCC_GPLL9_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_SHFT                                           0x7
#define HWIO_GCC_GPLL9_TEST_CTL_U1_ENABLE_TRAINING_SEQ_BMSK                                              0x40
#define HWIO_GCC_GPLL9_TEST_CTL_U1_ENABLE_TRAINING_SEQ_SHFT                                               0x6
#define HWIO_GCC_GPLL9_TEST_CTL_U1_STATUS_REG_EN_BMSK                                                    0x20
#define HWIO_GCC_GPLL9_TEST_CTL_U1_STATUS_REG_EN_SHFT                                                     0x5
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT68_BMSK                                                    0x10
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT68_SHFT                                                     0x4
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT67_BMSK                                                     0x8
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT67_SHFT                                                     0x3
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT66_BMSK                                                     0x4
#define HWIO_GCC_GPLL9_TEST_CTL_U1_RESERVE_BIT66_SHFT                                                     0x2
#define HWIO_GCC_GPLL9_TEST_CTL_U1_CASC_DAC_FCW_MSBS_BMSK                                                 0x3
#define HWIO_GCC_GPLL9_TEST_CTL_U1_CASC_DAC_FCW_MSBS_SHFT                                                 0x0

#define HWIO_GCC_GPLL9_STATUS_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c030)
#define HWIO_GCC_GPLL9_STATUS_RMSK                                                                 0xffffffff
#define HWIO_GCC_GPLL9_STATUS_IN          \
        in_dword(HWIO_GCC_GPLL9_STATUS_ADDR)
#define HWIO_GCC_GPLL9_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_STATUS_ADDR, m)
#define HWIO_GCC_GPLL9_STATUS_STATUS_31_0_BMSK                                                     0xffffffff
#define HWIO_GCC_GPLL9_STATUS_STATUS_31_0_SHFT                                                            0x0

#define HWIO_GCC_GPLL9_FREQ_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c034)
#define HWIO_GCC_GPLL9_FREQ_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_GPLL9_FREQ_CTL_IN          \
        in_dword(HWIO_GCC_GPLL9_FREQ_CTL_ADDR)
#define HWIO_GCC_GPLL9_FREQ_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_FREQ_CTL_ADDR, m)
#define HWIO_GCC_GPLL9_FREQ_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_FREQ_CTL_ADDR,v)
#define HWIO_GCC_GPLL9_FREQ_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_FREQ_CTL_ADDR,m,v,HWIO_GCC_GPLL9_FREQ_CTL_IN)
#define HWIO_GCC_GPLL9_FREQ_CTL_FREQUENCY_CTL_WORD_BMSK                                            0xffffffff
#define HWIO_GCC_GPLL9_FREQ_CTL_FREQUENCY_CTL_WORD_SHFT                                                   0x0

#define HWIO_GCC_GPLL9_OPMODE_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c038)
#define HWIO_GCC_GPLL9_OPMODE_RMSK                                                                        0x7
#define HWIO_GCC_GPLL9_OPMODE_IN          \
        in_dword(HWIO_GCC_GPLL9_OPMODE_ADDR)
#define HWIO_GCC_GPLL9_OPMODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_OPMODE_ADDR, m)
#define HWIO_GCC_GPLL9_OPMODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_OPMODE_ADDR,v)
#define HWIO_GCC_GPLL9_OPMODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_OPMODE_ADDR,m,v,HWIO_GCC_GPLL9_OPMODE_IN)
#define HWIO_GCC_GPLL9_OPMODE_PLL_OPMODE_BMSK                                                             0x7
#define HWIO_GCC_GPLL9_OPMODE_PLL_OPMODE_SHFT                                                             0x0

#define HWIO_GCC_GPLL9_STATE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c03c)
#define HWIO_GCC_GPLL9_STATE_RMSK                                                                         0x7
#define HWIO_GCC_GPLL9_STATE_IN          \
        in_dword(HWIO_GCC_GPLL9_STATE_ADDR)
#define HWIO_GCC_GPLL9_STATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_STATE_ADDR, m)
#define HWIO_GCC_GPLL9_STATE_PLL_STATE_BMSK                                                               0x7
#define HWIO_GCC_GPLL9_STATE_PLL_STATE_SHFT                                                               0x0

#define HWIO_GCC_GPLL9_ALPHA_VAL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c040)
#define HWIO_GCC_GPLL9_ALPHA_VAL_RMSK                                                                  0xffff
#define HWIO_GCC_GPLL9_ALPHA_VAL_IN          \
        in_dword(HWIO_GCC_GPLL9_ALPHA_VAL_ADDR)
#define HWIO_GCC_GPLL9_ALPHA_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_ALPHA_VAL_ADDR, m)
#define HWIO_GCC_GPLL9_ALPHA_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_ALPHA_VAL_ADDR,v)
#define HWIO_GCC_GPLL9_ALPHA_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_ALPHA_VAL_ADDR,m,v,HWIO_GCC_GPLL9_ALPHA_VAL_IN)
#define HWIO_GCC_GPLL9_ALPHA_VAL_PLL_ALPHA_VAL_BMSK                                                    0xffff
#define HWIO_GCC_GPLL9_ALPHA_VAL_PLL_ALPHA_VAL_SHFT                                                       0x0

#define HWIO_GCC_GPLL9_SPARE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c044)
#define HWIO_GCC_GPLL9_SPARE_RMSK                                                                        0xff
#define HWIO_GCC_GPLL9_SPARE_IN          \
        in_dword(HWIO_GCC_GPLL9_SPARE_ADDR)
#define HWIO_GCC_GPLL9_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_SPARE_ADDR, m)
#define HWIO_GCC_GPLL9_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_SPARE_ADDR,v)
#define HWIO_GCC_GPLL9_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_SPARE_ADDR,m,v,HWIO_GCC_GPLL9_SPARE_IN)
#define HWIO_GCC_GPLL9_SPARE_SPARE_OUTPUTS_BMSK                                                          0xf0
#define HWIO_GCC_GPLL9_SPARE_SPARE_OUTPUTS_SHFT                                                           0x4
#define HWIO_GCC_GPLL9_SPARE_SPARE_INPUTS_BMSK                                                            0xf
#define HWIO_GCC_GPLL9_SPARE_SPARE_INPUTS_SHFT                                                            0x0

#define HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c048)
#define HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_RMSK                                                              0xff
#define HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_IN          \
        in_dword(HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_ADDR)
#define HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_ADDR, m)
#define HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_ADDR,v)
#define HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_ADDR,m,v,HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_IN)
#define HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_BMSK                                              0xff
#define HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_SHFT                                               0x0

#define HWIO_GCC_GPLL9_SSC_NUM_STEPS_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c04c)
#define HWIO_GCC_GPLL9_SSC_NUM_STEPS_RMSK                                                                 0xf
#define HWIO_GCC_GPLL9_SSC_NUM_STEPS_IN          \
        in_dword(HWIO_GCC_GPLL9_SSC_NUM_STEPS_ADDR)
#define HWIO_GCC_GPLL9_SSC_NUM_STEPS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_SSC_NUM_STEPS_ADDR, m)
#define HWIO_GCC_GPLL9_SSC_NUM_STEPS_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_SSC_NUM_STEPS_ADDR,v)
#define HWIO_GCC_GPLL9_SSC_NUM_STEPS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_SSC_NUM_STEPS_ADDR,m,v,HWIO_GCC_GPLL9_SSC_NUM_STEPS_IN)
#define HWIO_GCC_GPLL9_SSC_NUM_STEPS_SSC_NUM_STEPS_BMSK                                                   0xf
#define HWIO_GCC_GPLL9_SSC_NUM_STEPS_SSC_NUM_STEPS_SHFT                                                   0x0

#define HWIO_GCC_GPLL9_SSC_UPDATE_RATE_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0001c050)
#define HWIO_GCC_GPLL9_SSC_UPDATE_RATE_RMSK                                                               0xf
#define HWIO_GCC_GPLL9_SSC_UPDATE_RATE_IN          \
        in_dword(HWIO_GCC_GPLL9_SSC_UPDATE_RATE_ADDR)
#define HWIO_GCC_GPLL9_SSC_UPDATE_RATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL9_SSC_UPDATE_RATE_ADDR, m)
#define HWIO_GCC_GPLL9_SSC_UPDATE_RATE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL9_SSC_UPDATE_RATE_ADDR,v)
#define HWIO_GCC_GPLL9_SSC_UPDATE_RATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL9_SSC_UPDATE_RATE_ADDR,m,v,HWIO_GCC_GPLL9_SSC_UPDATE_RATE_IN)
#define HWIO_GCC_GPLL9_SSC_UPDATE_RATE_SSC_UPDATE_RATE_BMSK                                               0xf
#define HWIO_GCC_GPLL9_SSC_UPDATE_RATE_SSC_UPDATE_RATE_SHFT                                               0x0

#define HWIO_GCC_GPLL10_MODE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d000)
#define HWIO_GCC_GPLL10_MODE_RMSK                                                                  0xffffffff
#define HWIO_GCC_GPLL10_MODE_IN          \
        in_dword(HWIO_GCC_GPLL10_MODE_ADDR)
#define HWIO_GCC_GPLL10_MODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_MODE_ADDR, m)
#define HWIO_GCC_GPLL10_MODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_MODE_ADDR,v)
#define HWIO_GCC_GPLL10_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_MODE_ADDR,m,v,HWIO_GCC_GPLL10_MODE_IN)
#define HWIO_GCC_GPLL10_MODE_PLL_LOCK_DET_BMSK                                                     0x80000000
#define HWIO_GCC_GPLL10_MODE_PLL_LOCK_DET_SHFT                                                           0x1f
#define HWIO_GCC_GPLL10_MODE_PLL_ACTIVE_FLAG_BMSK                                                  0x40000000
#define HWIO_GCC_GPLL10_MODE_PLL_ACTIVE_FLAG_SHFT                                                        0x1e
#define HWIO_GCC_GPLL10_MODE_PLL_ACK_LATCH_BMSK                                                    0x20000000
#define HWIO_GCC_GPLL10_MODE_PLL_ACK_LATCH_SHFT                                                          0x1d
#define HWIO_GCC_GPLL10_MODE_PLL_LOCK_DET_FINE_BMSK                                                0x10000000
#define HWIO_GCC_GPLL10_MODE_PLL_LOCK_DET_FINE_SHFT                                                      0x1c
#define HWIO_GCC_GPLL10_MODE_PCAL_DONE_BMSK                                                         0x8000000
#define HWIO_GCC_GPLL10_MODE_PCAL_DONE_SHFT                                                              0x1b
#define HWIO_GCC_GPLL10_MODE_RESERVE_BITS26_25_BMSK                                                 0x6000000
#define HWIO_GCC_GPLL10_MODE_RESERVE_BITS26_25_SHFT                                                      0x19
#define HWIO_GCC_GPLL10_MODE_FSM_LEGACY_MODE_BMSK                                                   0x1000000
#define HWIO_GCC_GPLL10_MODE_FSM_LEGACY_MODE_SHFT                                                        0x18
#define HWIO_GCC_GPLL10_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_BMSK                                         0x800000
#define HWIO_GCC_GPLL10_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_SHFT                                             0x17
#define HWIO_GCC_GPLL10_MODE_PLL_UPDATE_BMSK                                                         0x400000
#define HWIO_GCC_GPLL10_MODE_PLL_UPDATE_SHFT                                                             0x16
#define HWIO_GCC_GPLL10_MODE_PLL_VOTE_FSM_RESET_BMSK                                                 0x200000
#define HWIO_GCC_GPLL10_MODE_PLL_VOTE_FSM_RESET_SHFT                                                     0x15
#define HWIO_GCC_GPLL10_MODE_PLL_VOTE_FSM_ENA_BMSK                                                   0x100000
#define HWIO_GCC_GPLL10_MODE_PLL_VOTE_FSM_ENA_SHFT                                                       0x14
#define HWIO_GCC_GPLL10_MODE_PLL_BIAS_COUNT_BMSK                                                      0xfc000
#define HWIO_GCC_GPLL10_MODE_PLL_BIAS_COUNT_SHFT                                                          0xe
#define HWIO_GCC_GPLL10_MODE_PLL_LOCK_COUNT_BMSK                                                       0x3f00
#define HWIO_GCC_GPLL10_MODE_PLL_LOCK_COUNT_SHFT                                                          0x8
#define HWIO_GCC_GPLL10_MODE_RESERVE_BIT7_BMSK                                                           0x80
#define HWIO_GCC_GPLL10_MODE_RESERVE_BIT7_SHFT                                                            0x7
#define HWIO_GCC_GPLL10_MODE_OUT_TEST_HW_CTL_BMSK                                                        0x40
#define HWIO_GCC_GPLL10_MODE_OUT_TEST_HW_CTL_SHFT                                                         0x6
#define HWIO_GCC_GPLL10_MODE_OUT_ODD_HW_CTL_BMSK                                                         0x20
#define HWIO_GCC_GPLL10_MODE_OUT_ODD_HW_CTL_SHFT                                                          0x5
#define HWIO_GCC_GPLL10_MODE_OUT_EVEN_HW_CTL_BMSK                                                        0x10
#define HWIO_GCC_GPLL10_MODE_OUT_EVEN_HW_CTL_SHFT                                                         0x4
#define HWIO_GCC_GPLL10_MODE_OUT_MAIN_HW_CTL_BMSK                                                         0x8
#define HWIO_GCC_GPLL10_MODE_OUT_MAIN_HW_CTL_SHFT                                                         0x3
#define HWIO_GCC_GPLL10_MODE_PLL_RESET_N_BMSK                                                             0x4
#define HWIO_GCC_GPLL10_MODE_PLL_RESET_N_SHFT                                                             0x2
#define HWIO_GCC_GPLL10_MODE_RESERVE_BIT1_BMSK                                                            0x2
#define HWIO_GCC_GPLL10_MODE_RESERVE_BIT1_SHFT                                                            0x1
#define HWIO_GCC_GPLL10_MODE_PLL_OUTCTRL_BMSK                                                             0x1
#define HWIO_GCC_GPLL10_MODE_PLL_OUTCTRL_SHFT                                                             0x0

#define HWIO_GCC_GPLL10_L_VAL_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d004)
#define HWIO_GCC_GPLL10_L_VAL_RMSK                                                                     0xffff
#define HWIO_GCC_GPLL10_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL10_L_VAL_ADDR)
#define HWIO_GCC_GPLL10_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL10_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL10_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_L_VAL_ADDR,m,v,HWIO_GCC_GPLL10_L_VAL_IN)
#define HWIO_GCC_GPLL10_L_VAL_PLL_L_BMSK                                                               0xffff
#define HWIO_GCC_GPLL10_L_VAL_PLL_L_SHFT                                                                  0x0

#define HWIO_GCC_GPLL10_CAL_L_VAL_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d008)
#define HWIO_GCC_GPLL10_CAL_L_VAL_RMSK                                                                 0xffff
#define HWIO_GCC_GPLL10_CAL_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL10_CAL_L_VAL_ADDR)
#define HWIO_GCC_GPLL10_CAL_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_CAL_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL10_CAL_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_CAL_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL10_CAL_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_CAL_L_VAL_ADDR,m,v,HWIO_GCC_GPLL10_CAL_L_VAL_IN)
#define HWIO_GCC_GPLL10_CAL_L_VAL_PLL_CAL_L_BMSK                                                       0xffff
#define HWIO_GCC_GPLL10_CAL_L_VAL_PLL_CAL_L_SHFT                                                          0x0

#define HWIO_GCC_GPLL10_USER_CTL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d00c)
#define HWIO_GCC_GPLL10_USER_CTL_RMSK                                                              0xffffffff
#define HWIO_GCC_GPLL10_USER_CTL_IN          \
        in_dword(HWIO_GCC_GPLL10_USER_CTL_ADDR)
#define HWIO_GCC_GPLL10_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_USER_CTL_ADDR, m)
#define HWIO_GCC_GPLL10_USER_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_USER_CTL_ADDR,v)
#define HWIO_GCC_GPLL10_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_USER_CTL_ADDR,m,v,HWIO_GCC_GPLL10_USER_CTL_IN)
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT31_BMSK                                                0x80000000
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT31_SHFT                                                      0x1f
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT30_BMSK                                                0x40000000
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT30_SHFT                                                      0x1e
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT29_BMSK                                                0x20000000
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT29_SHFT                                                      0x1d
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT28_BMSK                                                0x10000000
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT28_SHFT                                                      0x1c
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT27_BMSK                                                 0x8000000
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT27_SHFT                                                      0x1b
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT26_BMSK                                                 0x4000000
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT26_SHFT                                                      0x1a
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT25_BMSK                                                 0x2000000
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT25_SHFT                                                      0x19
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT24_BMSK                                                 0x1000000
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT24_SHFT                                                      0x18
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT23_BMSK                                                  0x800000
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT23_SHFT                                                      0x17
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT22_BMSK                                                  0x400000
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT22_SHFT                                                      0x16
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT21_BMSK                                                  0x200000
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT21_SHFT                                                      0x15
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT20_BMSK                                                  0x100000
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT20_SHFT                                                      0x14
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT19_BMSK                                                   0x80000
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT19_SHFT                                                      0x13
#define HWIO_GCC_GPLL10_USER_CTL_PRE_DIV_RATIO_BMSK                                                   0x70000
#define HWIO_GCC_GPLL10_USER_CTL_PRE_DIV_RATIO_SHFT                                                      0x10
#define HWIO_GCC_GPLL10_USER_CTL_POST_DIV_RATIO_ODD_BMSK                                               0xf000
#define HWIO_GCC_GPLL10_USER_CTL_POST_DIV_RATIO_ODD_SHFT                                                  0xc
#define HWIO_GCC_GPLL10_USER_CTL_POST_DIV_RATIO_EVEN_BMSK                                               0xf00
#define HWIO_GCC_GPLL10_USER_CTL_POST_DIV_RATIO_EVEN_SHFT                                                 0x8
#define HWIO_GCC_GPLL10_USER_CTL_OUT_CLK_POLARITY_BMSK                                                   0x80
#define HWIO_GCC_GPLL10_USER_CTL_OUT_CLK_POLARITY_SHFT                                                    0x7
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT6_BMSK                                                       0x40
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT6_SHFT                                                        0x6
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT5_BMSK                                                       0x20
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT5_SHFT                                                        0x5
#define HWIO_GCC_GPLL10_USER_CTL_PLLOUT_TEST_BMSK                                                        0x10
#define HWIO_GCC_GPLL10_USER_CTL_PLLOUT_TEST_SHFT                                                         0x4
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT3_BMSK                                                        0x8
#define HWIO_GCC_GPLL10_USER_CTL_RESERVE_BIT3_SHFT                                                        0x3
#define HWIO_GCC_GPLL10_USER_CTL_PLLOUT_ODD_BMSK                                                          0x4
#define HWIO_GCC_GPLL10_USER_CTL_PLLOUT_ODD_SHFT                                                          0x2
#define HWIO_GCC_GPLL10_USER_CTL_PLLOUT_EVEN_BMSK                                                         0x2
#define HWIO_GCC_GPLL10_USER_CTL_PLLOUT_EVEN_SHFT                                                         0x1
#define HWIO_GCC_GPLL10_USER_CTL_PLLOUT_MAIN_BMSK                                                         0x1
#define HWIO_GCC_GPLL10_USER_CTL_PLLOUT_MAIN_SHFT                                                         0x0

#define HWIO_GCC_GPLL10_USER_CTL_U_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d010)
#define HWIO_GCC_GPLL10_USER_CTL_U_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL10_USER_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL10_USER_CTL_U_ADDR)
#define HWIO_GCC_GPLL10_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_USER_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL10_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_USER_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL10_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_USER_CTL_U_ADDR,m,v,HWIO_GCC_GPLL10_USER_CTL_U_IN)
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT63_BMSK                                              0x80000000
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT63_SHFT                                                    0x1f
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT62_BMSK                                              0x40000000
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT62_SHFT                                                    0x1e
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT61_BMSK                                              0x20000000
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT61_SHFT                                                    0x1d
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT60_BMSK                                              0x10000000
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT60_SHFT                                                    0x1c
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT59_BMSK                                               0x8000000
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT59_SHFT                                                    0x1b
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT58_BMSK                                               0x4000000
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT58_SHFT                                                    0x1a
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT57_BMSK                                               0x2000000
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT57_SHFT                                                    0x19
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT56_BMSK                                               0x1000000
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT56_SHFT                                                    0x18
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT55_BMSK                                                0x800000
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT55_SHFT                                                    0x17
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT54_BMSK                                                0x400000
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT54_SHFT                                                    0x16
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT53_BMSK                                                0x200000
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT53_SHFT                                                    0x15
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT52_BMSK                                                0x100000
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT52_SHFT                                                    0x14
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT51_BMSK                                                 0x80000
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT51_SHFT                                                    0x13
#define HWIO_GCC_GPLL10_USER_CTL_U_LOCK_DETECTOR_SELECTION_BMSK                                       0x40000
#define HWIO_GCC_GPLL10_USER_CTL_U_LOCK_DETECTOR_SELECTION_SHFT                                          0x12
#define HWIO_GCC_GPLL10_USER_CTL_U_TYPE_2_MODE_SELECTION_BMSK                                         0x20000
#define HWIO_GCC_GPLL10_USER_CTL_U_TYPE_2_MODE_SELECTION_SHFT                                            0x11
#define HWIO_GCC_GPLL10_USER_CTL_U_BANG_BANG_MODE_SELECTION_BMSK                                      0x10000
#define HWIO_GCC_GPLL10_USER_CTL_U_BANG_BANG_MODE_SELECTION_SHFT                                         0x10
#define HWIO_GCC_GPLL10_USER_CTL_U_FRAC_FORMAT_SEL_BMSK                                                0x8000
#define HWIO_GCC_GPLL10_USER_CTL_U_FRAC_FORMAT_SEL_SHFT                                                   0xf
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT46_BMSK                                                  0x4000
#define HWIO_GCC_GPLL10_USER_CTL_U_RESERVE_BIT46_SHFT                                                     0xe
#define HWIO_GCC_GPLL10_USER_CTL_U_REF_CLK_AT_OUT_BMSK                                                 0x2000
#define HWIO_GCC_GPLL10_USER_CTL_U_REF_CLK_AT_OUT_SHFT                                                    0xd
#define HWIO_GCC_GPLL10_USER_CTL_U_SCALE_FREQ_ON_RESTART_BMSK                                          0x1800
#define HWIO_GCC_GPLL10_USER_CTL_U_SCALE_FREQ_ON_RESTART_SHFT                                             0xb
#define HWIO_GCC_GPLL10_USER_CTL_U_LATCH_INTERFACE_BYPASS_BMSK                                          0x400
#define HWIO_GCC_GPLL10_USER_CTL_U_LATCH_INTERFACE_BYPASS_SHFT                                            0xa
#define HWIO_GCC_GPLL10_USER_CTL_U_STATUS_REGISTER_BMSK                                                 0x3e0
#define HWIO_GCC_GPLL10_USER_CTL_U_STATUS_REGISTER_SHFT                                                   0x5
#define HWIO_GCC_GPLL10_USER_CTL_U_WRITE_STATE_EN_BMSK                                                   0x10
#define HWIO_GCC_GPLL10_USER_CTL_U_WRITE_STATE_EN_SHFT                                                    0x4
#define HWIO_GCC_GPLL10_USER_CTL_U_CALIB_CTRL_BMSK                                                        0xe
#define HWIO_GCC_GPLL10_USER_CTL_U_CALIB_CTRL_SHFT                                                        0x1
#define HWIO_GCC_GPLL10_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_BMSK                                            0x1
#define HWIO_GCC_GPLL10_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_SHFT                                            0x0

#define HWIO_GCC_GPLL10_USER_CTL_U1_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d014)
#define HWIO_GCC_GPLL10_USER_CTL_U1_RMSK                                                           0xffffffff
#define HWIO_GCC_GPLL10_USER_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL10_USER_CTL_U1_ADDR)
#define HWIO_GCC_GPLL10_USER_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_USER_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL10_USER_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_USER_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL10_USER_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_USER_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL10_USER_CTL_U1_IN)
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT95_BMSK                                             0x80000000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT95_SHFT                                                   0x1f
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT94_BMSK                                             0x40000000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT94_SHFT                                                   0x1e
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT93_BMSK                                             0x20000000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT93_SHFT                                                   0x1d
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT92_BMSK                                             0x10000000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT92_SHFT                                                   0x1c
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT91_BMSK                                              0x8000000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT91_SHFT                                                   0x1b
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT90_BMSK                                              0x4000000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT90_SHFT                                                   0x1a
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT89_BMSK                                              0x2000000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT89_SHFT                                                   0x19
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT88_BMSK                                              0x1000000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT88_SHFT                                                   0x18
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT87_BMSK                                               0x800000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT87_SHFT                                                   0x17
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT86_BMSK                                               0x400000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT86_SHFT                                                   0x16
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT85_BMSK                                               0x200000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT85_SHFT                                                   0x15
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT84_BMSK                                               0x100000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT84_SHFT                                                   0x14
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT83_BMSK                                                0x80000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT83_SHFT                                                   0x13
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT82_BMSK                                                0x40000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT82_SHFT                                                   0x12
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT81_BMSK                                                0x20000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT81_SHFT                                                   0x11
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT80_BMSK                                                0x10000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT80_SHFT                                                   0x10
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT79_BMSK                                                 0x8000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT79_SHFT                                                    0xf
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT78_BMSK                                                 0x4000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT78_SHFT                                                    0xe
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT77_BMSK                                                 0x2000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT77_SHFT                                                    0xd
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT76_BMSK                                                 0x1000
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT76_SHFT                                                    0xc
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT75_BMSK                                                  0x800
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT75_SHFT                                                    0xb
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT74_BMSK                                                  0x400
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT74_SHFT                                                    0xa
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT73_BMSK                                                  0x200
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT73_SHFT                                                    0x9
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT72_BMSK                                                  0x100
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT72_SHFT                                                    0x8
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT71_BMSK                                                   0x80
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT71_SHFT                                                    0x7
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT70_BMSK                                                   0x40
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT70_SHFT                                                    0x6
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT69_BMSK                                                   0x20
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT69_SHFT                                                    0x5
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT68_BMSK                                                   0x10
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT68_SHFT                                                    0x4
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT67_BMSK                                                    0x8
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT67_SHFT                                                    0x3
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT66_BMSK                                                    0x4
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT66_SHFT                                                    0x2
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT65_BMSK                                                    0x2
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT65_SHFT                                                    0x1
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT64_BMSK                                                    0x1
#define HWIO_GCC_GPLL10_USER_CTL_U1_RESERVE_BIT64_SHFT                                                    0x0

#define HWIO_GCC_GPLL10_CONFIG_CTL_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d018)
#define HWIO_GCC_GPLL10_CONFIG_CTL_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL10_CONFIG_CTL_IN          \
        in_dword(HWIO_GCC_GPLL10_CONFIG_CTL_ADDR)
#define HWIO_GCC_GPLL10_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_CONFIG_CTL_ADDR, m)
#define HWIO_GCC_GPLL10_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_CONFIG_CTL_ADDR,v)
#define HWIO_GCC_GPLL10_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_CONFIG_CTL_ADDR,m,v,HWIO_GCC_GPLL10_CONFIG_CTL_IN)
#define HWIO_GCC_GPLL10_CONFIG_CTL_FINE_LDC_THRESHOLD_BMSK                                         0xfc000000
#define HWIO_GCC_GPLL10_CONFIG_CTL_FINE_LDC_THRESHOLD_SHFT                                               0x1a
#define HWIO_GCC_GPLL10_CONFIG_CTL_COARSE_LDC_THRESHOLD_BMSK                                        0x3c00000
#define HWIO_GCC_GPLL10_CONFIG_CTL_COARSE_LDC_THRESHOLD_SHFT                                             0x16
#define HWIO_GCC_GPLL10_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_BMSK                                0x3c0000
#define HWIO_GCC_GPLL10_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_SHFT                                    0x12
#define HWIO_GCC_GPLL10_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_BMSK                                 0x3c000
#define HWIO_GCC_GPLL10_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_SHFT                                     0xe
#define HWIO_GCC_GPLL10_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_BMSK                                        0x3800
#define HWIO_GCC_GPLL10_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_SHFT                                           0xb
#define HWIO_GCC_GPLL10_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_BMSK                                       0x700
#define HWIO_GCC_GPLL10_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_SHFT                                         0x8
#define HWIO_GCC_GPLL10_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_BMSK                                             0xf0
#define HWIO_GCC_GPLL10_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_SHFT                                              0x4
#define HWIO_GCC_GPLL10_CONFIG_CTL_FWD_GAIN_KFN_BMSK                                                      0xf
#define HWIO_GCC_GPLL10_CONFIG_CTL_FWD_GAIN_KFN_SHFT                                                      0x0

#define HWIO_GCC_GPLL10_CONFIG_CTL_U_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d01c)
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_RMSK                                                          0xffffffff
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL10_CONFIG_CTL_U_ADDR)
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_CONFIG_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_CONFIG_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_CONFIG_CTL_U_ADDR,m,v,HWIO_GCC_GPLL10_CONFIG_CTL_U_IN)
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_BIST_CFG_BMSK                                                 0xffff0000
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_BIST_CFG_SHFT                                                       0x10
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_BMSK                                      0xc000
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_SHFT                                         0xe
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_OSC_SETTLING_TIME_BMSK                                            0x3000
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_OSC_SETTLING_TIME_SHFT                                               0xc
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_BMSK                                           0xc00
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_SHFT                                             0xa
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_CASC_CURRENT_CTL_B_BMSK                                            0x380
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_CASC_CURRENT_CTL_B_SHFT                                              0x7
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_BMSK                                    0x40
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_SHFT                                     0x6
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_BMSK                                           0x30
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_SHFT                                            0x4
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_LDET_THRESH_SCALE_BMSK                                               0x8
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_LDET_THRESH_SCALE_SHFT                                               0x3
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_DCO_STARTUP_CONFIG_BMSK                                              0x6
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_DCO_STARTUP_CONFIG_SHFT                                              0x1
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_BMSK                                         0x1
#define HWIO_GCC_GPLL10_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_SHFT                                         0x0

#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d020)
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_RMSK                                                         0xffffffff
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL10_CONFIG_CTL_U1_ADDR)
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_CONFIG_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_CONFIG_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_CONFIG_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL10_CONFIG_CTL_U1_IN)
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BB_CAL_THRESHOLD_BMSK                                        0xc0000000
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BB_CAL_THRESHOLD_SHFT                                              0x1e
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_PCODE_OFFSET_BMSK                                            0x38000000
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_PCODE_OFFSET_SHFT                                                  0x1b
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_COUNTER_BLANK_BMSK                                            0x4000000
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_COUNTER_BLANK_SHFT                                                 0x1a
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BB_RESYNC_EDGE_BMSK                                           0x2000000
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BB_RESYNC_EDGE_SHFT                                                0x19
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BB_RESYNC_SEL_BMSK                                            0x1000000
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BB_RESYNC_SEL_SHFT                                                 0x18
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_BMSK                                       0xc00000
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_SHFT                                           0x16
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BB_LOCK_THRESH_BMSK                                            0x380000
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BB_LOCK_THRESH_SHFT                                                0x13
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_RESERVE_BIT82_BMSK                                              0x40000
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_RESERVE_BIT82_SHFT                                                 0x12
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_BMSK                                         0x30000
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_SHFT                                            0x10
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_BMSK                                           0xc000
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_SHFT                                              0xe
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BB_CAL_EN_BMSK                                                   0x2000
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BB_CAL_EN_SHFT                                                      0xd
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_BMSK                                     0x1800
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_SHFT                                        0xb
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BBMODE_INT_GAIN_BMSK                                              0x780
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BBMODE_INT_GAIN_SHFT                                                0x7
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BBMODE_PROP_GAIN_BMSK                                              0x78
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_BBMODE_PROP_GAIN_SHFT                                               0x3
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_TDC_SELECTION_BMSK                                                  0x4
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_TDC_SELECTION_SHFT                                                  0x2
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_RESERVE_BIT65_BMSK                                                  0x2
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_RESERVE_BIT65_SHFT                                                  0x1
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_FORCE_DSM_ON_BMSK                                                   0x1
#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_FORCE_DSM_ON_SHFT                                                   0x0

#define HWIO_GCC_GPLL10_TEST_CTL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d024)
#define HWIO_GCC_GPLL10_TEST_CTL_RMSK                                                              0xffffffff
#define HWIO_GCC_GPLL10_TEST_CTL_IN          \
        in_dword(HWIO_GCC_GPLL10_TEST_CTL_ADDR)
#define HWIO_GCC_GPLL10_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_TEST_CTL_ADDR, m)
#define HWIO_GCC_GPLL10_TEST_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_TEST_CTL_ADDR,v)
#define HWIO_GCC_GPLL10_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_TEST_CTL_ADDR,m,v,HWIO_GCC_GPLL10_TEST_CTL_IN)
#define HWIO_GCC_GPLL10_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_BMSK                                      0xc0000000
#define HWIO_GCC_GPLL10_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_SHFT                                            0x1e
#define HWIO_GCC_GPLL10_TEST_CTL_BYPASS_FIRST_ORDER_DSM_BMSK                                       0x20000000
#define HWIO_GCC_GPLL10_TEST_CTL_BYPASS_FIRST_ORDER_DSM_SHFT                                             0x1d
#define HWIO_GCC_GPLL10_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_BMSK                                  0x18000000
#define HWIO_GCC_GPLL10_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_SHFT                                        0x1b
#define HWIO_GCC_GPLL10_TEST_CTL_GLITCH_PREVENTION_DIS_BMSK                                         0x4000000
#define HWIO_GCC_GPLL10_TEST_CTL_GLITCH_PREVENTION_DIS_SHFT                                              0x1a
#define HWIO_GCC_GPLL10_TEST_CTL_ATEST_ISCALE_BMSK                                                  0x3000000
#define HWIO_GCC_GPLL10_TEST_CTL_ATEST_ISCALE_SHFT                                                       0x18
#define HWIO_GCC_GPLL10_TEST_CTL_PLL_TEST_OUT_SEL_BMSK                                               0xf00000
#define HWIO_GCC_GPLL10_TEST_CTL_PLL_TEST_OUT_SEL_SHFT                                                   0x14
#define HWIO_GCC_GPLL10_TEST_CTL_RESERVE_BIT19_BMSK                                                   0x80000
#define HWIO_GCC_GPLL10_TEST_CTL_RESERVE_BIT19_SHFT                                                      0x13
#define HWIO_GCC_GPLL10_TEST_CTL_DIV2_NMO_EN_BMSK                                                     0x40000
#define HWIO_GCC_GPLL10_TEST_CTL_DIV2_NMO_EN_SHFT                                                        0x12
#define HWIO_GCC_GPLL10_TEST_CTL_NMO_OSC_SEL_BMSK                                                     0x30000
#define HWIO_GCC_GPLL10_TEST_CTL_NMO_OSC_SEL_SHFT                                                        0x10
#define HWIO_GCC_GPLL10_TEST_CTL_NOISE_MAG_BMSK                                                        0xe000
#define HWIO_GCC_GPLL10_TEST_CTL_NOISE_MAG_SHFT                                                           0xd
#define HWIO_GCC_GPLL10_TEST_CTL_NOISE_GEN_EN_BMSK                                                     0x1000
#define HWIO_GCC_GPLL10_TEST_CTL_NOISE_GEN_EN_SHFT                                                        0xc
#define HWIO_GCC_GPLL10_TEST_CTL_DISABLE_DCAPS_BMSK                                                     0x800
#define HWIO_GCC_GPLL10_TEST_CTL_DISABLE_DCAPS_SHFT                                                       0xb
#define HWIO_GCC_GPLL10_TEST_CTL_RESERVE_BIT10_BMSK                                                     0x400
#define HWIO_GCC_GPLL10_TEST_CTL_RESERVE_BIT10_SHFT                                                       0xa
#define HWIO_GCC_GPLL10_TEST_CTL_RESERVE_BIT9_BMSK                                                      0x200
#define HWIO_GCC_GPLL10_TEST_CTL_RESERVE_BIT9_SHFT                                                        0x9
#define HWIO_GCC_GPLL10_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_BMSK                                           0x100
#define HWIO_GCC_GPLL10_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_SHFT                                             0x8
#define HWIO_GCC_GPLL10_TEST_CTL_EN_VDD_TEST_BMSK                                                        0x80
#define HWIO_GCC_GPLL10_TEST_CTL_EN_VDD_TEST_SHFT                                                         0x7
#define HWIO_GCC_GPLL10_TEST_CTL_EN_VREG_TEST_BMSK                                                       0x40
#define HWIO_GCC_GPLL10_TEST_CTL_EN_VREG_TEST_SHFT                                                        0x6
#define HWIO_GCC_GPLL10_TEST_CTL_EN_VREF_TEST_BMSK                                                       0x20
#define HWIO_GCC_GPLL10_TEST_CTL_EN_VREF_TEST_SHFT                                                        0x5
#define HWIO_GCC_GPLL10_TEST_CTL_EN_VDCO_TEST_BMSK                                                       0x10
#define HWIO_GCC_GPLL10_TEST_CTL_EN_VDCO_TEST_SHFT                                                        0x4
#define HWIO_GCC_GPLL10_TEST_CTL_BYPASS_ATEST_BUFFER_BMSK                                                 0x8
#define HWIO_GCC_GPLL10_TEST_CTL_BYPASS_ATEST_BUFFER_SHFT                                                 0x3
#define HWIO_GCC_GPLL10_TEST_CTL_EN_IVCO_TEST_BMSK                                                        0x4
#define HWIO_GCC_GPLL10_TEST_CTL_EN_IVCO_TEST_SHFT                                                        0x2
#define HWIO_GCC_GPLL10_TEST_CTL_ATEST1_EN_BMSK                                                           0x2
#define HWIO_GCC_GPLL10_TEST_CTL_ATEST1_EN_SHFT                                                           0x1
#define HWIO_GCC_GPLL10_TEST_CTL_ATEST0_EN_BMSK                                                           0x1
#define HWIO_GCC_GPLL10_TEST_CTL_ATEST0_EN_SHFT                                                           0x0

#define HWIO_GCC_GPLL10_TEST_CTL_U_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d028)
#define HWIO_GCC_GPLL10_TEST_CTL_U_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL10_TEST_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL10_TEST_CTL_U_ADDR)
#define HWIO_GCC_GPLL10_TEST_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_TEST_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL10_TEST_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_TEST_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL10_TEST_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_TEST_CTL_U_ADDR,m,v,HWIO_GCC_GPLL10_TEST_CTL_U_IN)
#define HWIO_GCC_GPLL10_TEST_CTL_U_CASC_DAC_FCW_LSBS_BMSK                                          0xe0000000
#define HWIO_GCC_GPLL10_TEST_CTL_U_CASC_DAC_FCW_LSBS_SHFT                                                0x1d
#define HWIO_GCC_GPLL10_TEST_CTL_U_OVERRIDE_CASC_DAC_BMSK                                          0x10000000
#define HWIO_GCC_GPLL10_TEST_CTL_U_OVERRIDE_CASC_DAC_SHFT                                                0x1c
#define HWIO_GCC_GPLL10_TEST_CTL_U_COMP_COARSE_FCW_BMSK                                             0xe000000
#define HWIO_GCC_GPLL10_TEST_CTL_U_COMP_COARSE_FCW_SHFT                                                  0x19
#define HWIO_GCC_GPLL10_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_BMSK                                    0x1800000
#define HWIO_GCC_GPLL10_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_SHFT                                         0x17
#define HWIO_GCC_GPLL10_TEST_CTL_U_FINE_FCW_BMSK                                                     0x7e0000
#define HWIO_GCC_GPLL10_TEST_CTL_U_FINE_FCW_SHFT                                                         0x11
#define HWIO_GCC_GPLL10_TEST_CTL_U_OVERRIDE_FINE_FCW_BMSK                                             0x10000
#define HWIO_GCC_GPLL10_TEST_CTL_U_OVERRIDE_FINE_FCW_SHFT                                                0x10
#define HWIO_GCC_GPLL10_TEST_CTL_U_REG_COARSE_FCW_BMSK                                                 0xfe00
#define HWIO_GCC_GPLL10_TEST_CTL_U_REG_COARSE_FCW_SHFT                                                    0x9
#define HWIO_GCC_GPLL10_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_BMSK                                         0x100
#define HWIO_GCC_GPLL10_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_SHFT                                           0x8
#define HWIO_GCC_GPLL10_TEST_CTL_U_PROCESS_CALIB_WORD_BMSK                                               0xe0
#define HWIO_GCC_GPLL10_TEST_CTL_U_PROCESS_CALIB_WORD_SHFT                                                0x5
#define HWIO_GCC_GPLL10_TEST_CTL_U_OVERRIDE_CALIB_WORD_BMSK                                              0x10
#define HWIO_GCC_GPLL10_TEST_CTL_U_OVERRIDE_CALIB_WORD_SHFT                                               0x4
#define HWIO_GCC_GPLL10_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_BMSK                                            0x8
#define HWIO_GCC_GPLL10_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_SHFT                                            0x3
#define HWIO_GCC_GPLL10_TEST_CTL_U_DISABLE_LFSR_BMSK                                                      0x4
#define HWIO_GCC_GPLL10_TEST_CTL_U_DISABLE_LFSR_SHFT                                                      0x2
#define HWIO_GCC_GPLL10_TEST_CTL_U_SKIP_FINE_TUNE_BMSK                                                    0x2
#define HWIO_GCC_GPLL10_TEST_CTL_U_SKIP_FINE_TUNE_SHFT                                                    0x1
#define HWIO_GCC_GPLL10_TEST_CTL_U_SKIP_FAST_LOCK_BMSK                                                    0x1
#define HWIO_GCC_GPLL10_TEST_CTL_U_SKIP_FAST_LOCK_SHFT                                                    0x0

#define HWIO_GCC_GPLL10_TEST_CTL_U1_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d02c)
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RMSK                                                           0xffffffff
#define HWIO_GCC_GPLL10_TEST_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL10_TEST_CTL_U1_ADDR)
#define HWIO_GCC_GPLL10_TEST_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_TEST_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL10_TEST_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_TEST_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL10_TEST_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_TEST_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL10_TEST_CTL_U1_IN)
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT95_BMSK                                             0x80000000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT95_SHFT                                                   0x1f
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT94_BMSK                                             0x40000000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT94_SHFT                                                   0x1e
#define HWIO_GCC_GPLL10_TEST_CTL_U1_FLL_COUNT_DISABLE_BMSK                                         0x20000000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_FLL_COUNT_DISABLE_SHFT                                               0x1d
#define HWIO_GCC_GPLL10_TEST_CTL_U1_FLL_COUNT_IN_DIV2_BMSK                                         0x10000000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_FLL_COUNT_IN_DIV2_SHFT                                               0x1c
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT91_BMSK                                              0x8000000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT91_SHFT                                                   0x1b
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT90_BMSK                                              0x4000000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT90_SHFT                                                   0x1a
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT89_BMSK                                              0x2000000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT89_SHFT                                                   0x19
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT88_BMSK                                              0x1000000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT88_SHFT                                                   0x18
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT87_BMSK                                               0x800000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT87_SHFT                                                   0x17
#define HWIO_GCC_GPLL10_TEST_CTL_U1_SILENCE_REF_OUTBUF_BMSK                                          0x400000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_SILENCE_REF_OUTBUF_SHFT                                              0x16
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT85_BMSK                                               0x200000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT85_SHFT                                                   0x15
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT84_BMSK                                               0x100000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT84_SHFT                                                   0x14
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT83_BMSK                                                0x80000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT83_SHFT                                                   0x13
#define HWIO_GCC_GPLL10_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_BMSK                                        0x40000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_SHFT                                           0x12
#define HWIO_GCC_GPLL10_TEST_CTL_U1_REF_CLK_SEL_BMSK                                                  0x20000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_REF_CLK_SEL_SHFT                                                     0x11
#define HWIO_GCC_GPLL10_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_BMSK                                    0x10000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_SHFT                                       0x10
#define HWIO_GCC_GPLL10_TEST_CTL_U1_DIS_AMP_STARTUP_BMSK                                               0x8000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_DIS_AMP_STARTUP_SHFT                                                  0xf
#define HWIO_GCC_GPLL10_TEST_CTL_U1_DISABLE_CLAMP_BMSK                                                 0x4000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_DISABLE_CLAMP_SHFT                                                    0xe
#define HWIO_GCC_GPLL10_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_BMSK                                       0x2000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_SHFT                                          0xd
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT76_BMSK                                                 0x1000
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT76_SHFT                                                    0xc
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT75_BMSK                                                  0x800
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT75_SHFT                                                    0xb
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT74_BMSK                                                  0x400
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT74_SHFT                                                    0xa
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT73_BMSK                                                  0x200
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT73_SHFT                                                    0x9
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT72_BMSK                                                  0x100
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT72_SHFT                                                    0x8
#define HWIO_GCC_GPLL10_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_BMSK                                         0x80
#define HWIO_GCC_GPLL10_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_SHFT                                          0x7
#define HWIO_GCC_GPLL10_TEST_CTL_U1_ENABLE_TRAINING_SEQ_BMSK                                             0x40
#define HWIO_GCC_GPLL10_TEST_CTL_U1_ENABLE_TRAINING_SEQ_SHFT                                              0x6
#define HWIO_GCC_GPLL10_TEST_CTL_U1_STATUS_REG_EN_BMSK                                                   0x20
#define HWIO_GCC_GPLL10_TEST_CTL_U1_STATUS_REG_EN_SHFT                                                    0x5
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT68_BMSK                                                   0x10
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT68_SHFT                                                    0x4
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT67_BMSK                                                    0x8
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT67_SHFT                                                    0x3
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT66_BMSK                                                    0x4
#define HWIO_GCC_GPLL10_TEST_CTL_U1_RESERVE_BIT66_SHFT                                                    0x2
#define HWIO_GCC_GPLL10_TEST_CTL_U1_CASC_DAC_FCW_MSBS_BMSK                                                0x3
#define HWIO_GCC_GPLL10_TEST_CTL_U1_CASC_DAC_FCW_MSBS_SHFT                                                0x0

#define HWIO_GCC_GPLL10_STATUS_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d030)
#define HWIO_GCC_GPLL10_STATUS_RMSK                                                                0xffffffff
#define HWIO_GCC_GPLL10_STATUS_IN          \
        in_dword(HWIO_GCC_GPLL10_STATUS_ADDR)
#define HWIO_GCC_GPLL10_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_STATUS_ADDR, m)
#define HWIO_GCC_GPLL10_STATUS_STATUS_31_0_BMSK                                                    0xffffffff
#define HWIO_GCC_GPLL10_STATUS_STATUS_31_0_SHFT                                                           0x0

#define HWIO_GCC_GPLL10_FREQ_CTL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d034)
#define HWIO_GCC_GPLL10_FREQ_CTL_RMSK                                                              0xffffffff
#define HWIO_GCC_GPLL10_FREQ_CTL_IN          \
        in_dword(HWIO_GCC_GPLL10_FREQ_CTL_ADDR)
#define HWIO_GCC_GPLL10_FREQ_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_FREQ_CTL_ADDR, m)
#define HWIO_GCC_GPLL10_FREQ_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_FREQ_CTL_ADDR,v)
#define HWIO_GCC_GPLL10_FREQ_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_FREQ_CTL_ADDR,m,v,HWIO_GCC_GPLL10_FREQ_CTL_IN)
#define HWIO_GCC_GPLL10_FREQ_CTL_FREQUENCY_CTL_WORD_BMSK                                           0xffffffff
#define HWIO_GCC_GPLL10_FREQ_CTL_FREQUENCY_CTL_WORD_SHFT                                                  0x0

#define HWIO_GCC_GPLL10_OPMODE_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d038)
#define HWIO_GCC_GPLL10_OPMODE_RMSK                                                                       0x7
#define HWIO_GCC_GPLL10_OPMODE_IN          \
        in_dword(HWIO_GCC_GPLL10_OPMODE_ADDR)
#define HWIO_GCC_GPLL10_OPMODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_OPMODE_ADDR, m)
#define HWIO_GCC_GPLL10_OPMODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_OPMODE_ADDR,v)
#define HWIO_GCC_GPLL10_OPMODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_OPMODE_ADDR,m,v,HWIO_GCC_GPLL10_OPMODE_IN)
#define HWIO_GCC_GPLL10_OPMODE_PLL_OPMODE_BMSK                                                            0x7
#define HWIO_GCC_GPLL10_OPMODE_PLL_OPMODE_SHFT                                                            0x0

#define HWIO_GCC_GPLL10_STATE_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d03c)
#define HWIO_GCC_GPLL10_STATE_RMSK                                                                        0x7
#define HWIO_GCC_GPLL10_STATE_IN          \
        in_dword(HWIO_GCC_GPLL10_STATE_ADDR)
#define HWIO_GCC_GPLL10_STATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_STATE_ADDR, m)
#define HWIO_GCC_GPLL10_STATE_PLL_STATE_BMSK                                                              0x7
#define HWIO_GCC_GPLL10_STATE_PLL_STATE_SHFT                                                              0x0

#define HWIO_GCC_GPLL10_ALPHA_VAL_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d040)
#define HWIO_GCC_GPLL10_ALPHA_VAL_RMSK                                                                 0xffff
#define HWIO_GCC_GPLL10_ALPHA_VAL_IN          \
        in_dword(HWIO_GCC_GPLL10_ALPHA_VAL_ADDR)
#define HWIO_GCC_GPLL10_ALPHA_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_ALPHA_VAL_ADDR, m)
#define HWIO_GCC_GPLL10_ALPHA_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_ALPHA_VAL_ADDR,v)
#define HWIO_GCC_GPLL10_ALPHA_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_ALPHA_VAL_ADDR,m,v,HWIO_GCC_GPLL10_ALPHA_VAL_IN)
#define HWIO_GCC_GPLL10_ALPHA_VAL_PLL_ALPHA_VAL_BMSK                                                   0xffff
#define HWIO_GCC_GPLL10_ALPHA_VAL_PLL_ALPHA_VAL_SHFT                                                      0x0

#define HWIO_GCC_GPLL10_SPARE_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d044)
#define HWIO_GCC_GPLL10_SPARE_RMSK                                                                       0xff
#define HWIO_GCC_GPLL10_SPARE_IN          \
        in_dword(HWIO_GCC_GPLL10_SPARE_ADDR)
#define HWIO_GCC_GPLL10_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_SPARE_ADDR, m)
#define HWIO_GCC_GPLL10_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_SPARE_ADDR,v)
#define HWIO_GCC_GPLL10_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_SPARE_ADDR,m,v,HWIO_GCC_GPLL10_SPARE_IN)
#define HWIO_GCC_GPLL10_SPARE_SPARE_OUTPUTS_BMSK                                                         0xf0
#define HWIO_GCC_GPLL10_SPARE_SPARE_OUTPUTS_SHFT                                                          0x4
#define HWIO_GCC_GPLL10_SPARE_SPARE_INPUTS_BMSK                                                           0xf
#define HWIO_GCC_GPLL10_SPARE_SPARE_INPUTS_SHFT                                                           0x0

#define HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d048)
#define HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_RMSK                                                             0xff
#define HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_IN          \
        in_dword(HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_ADDR)
#define HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_ADDR, m)
#define HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_ADDR,v)
#define HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_ADDR,m,v,HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_IN)
#define HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_BMSK                                             0xff
#define HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_SHFT                                              0x0

#define HWIO_GCC_GPLL10_SSC_NUM_STEPS_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d04c)
#define HWIO_GCC_GPLL10_SSC_NUM_STEPS_RMSK                                                                0xf
#define HWIO_GCC_GPLL10_SSC_NUM_STEPS_IN          \
        in_dword(HWIO_GCC_GPLL10_SSC_NUM_STEPS_ADDR)
#define HWIO_GCC_GPLL10_SSC_NUM_STEPS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_SSC_NUM_STEPS_ADDR, m)
#define HWIO_GCC_GPLL10_SSC_NUM_STEPS_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_SSC_NUM_STEPS_ADDR,v)
#define HWIO_GCC_GPLL10_SSC_NUM_STEPS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_SSC_NUM_STEPS_ADDR,m,v,HWIO_GCC_GPLL10_SSC_NUM_STEPS_IN)
#define HWIO_GCC_GPLL10_SSC_NUM_STEPS_SSC_NUM_STEPS_BMSK                                                  0xf
#define HWIO_GCC_GPLL10_SSC_NUM_STEPS_SSC_NUM_STEPS_SHFT                                                  0x0

#define HWIO_GCC_GPLL10_SSC_UPDATE_RATE_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0001d050)
#define HWIO_GCC_GPLL10_SSC_UPDATE_RATE_RMSK                                                              0xf
#define HWIO_GCC_GPLL10_SSC_UPDATE_RATE_IN          \
        in_dword(HWIO_GCC_GPLL10_SSC_UPDATE_RATE_ADDR)
#define HWIO_GCC_GPLL10_SSC_UPDATE_RATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL10_SSC_UPDATE_RATE_ADDR, m)
#define HWIO_GCC_GPLL10_SSC_UPDATE_RATE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL10_SSC_UPDATE_RATE_ADDR,v)
#define HWIO_GCC_GPLL10_SSC_UPDATE_RATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL10_SSC_UPDATE_RATE_ADDR,m,v,HWIO_GCC_GPLL10_SSC_UPDATE_RATE_IN)
#define HWIO_GCC_GPLL10_SSC_UPDATE_RATE_SSC_UPDATE_RATE_BMSK                                              0xf
#define HWIO_GCC_GPLL10_SSC_UPDATE_RATE_SSC_UPDATE_RATE_SHFT                                              0x0

#define HWIO_GCC_GPLL11_MODE_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a000)
#define HWIO_GCC_GPLL11_MODE_RMSK                                                                  0xffffffff
#define HWIO_GCC_GPLL11_MODE_IN          \
        in_dword(HWIO_GCC_GPLL11_MODE_ADDR)
#define HWIO_GCC_GPLL11_MODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_MODE_ADDR, m)
#define HWIO_GCC_GPLL11_MODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_MODE_ADDR,v)
#define HWIO_GCC_GPLL11_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_MODE_ADDR,m,v,HWIO_GCC_GPLL11_MODE_IN)
#define HWIO_GCC_GPLL11_MODE_PLL_LOCK_DET_BMSK                                                     0x80000000
#define HWIO_GCC_GPLL11_MODE_PLL_LOCK_DET_SHFT                                                           0x1f
#define HWIO_GCC_GPLL11_MODE_PLL_ACTIVE_FLAG_BMSK                                                  0x40000000
#define HWIO_GCC_GPLL11_MODE_PLL_ACTIVE_FLAG_SHFT                                                        0x1e
#define HWIO_GCC_GPLL11_MODE_PLL_ACK_LATCH_BMSK                                                    0x20000000
#define HWIO_GCC_GPLL11_MODE_PLL_ACK_LATCH_SHFT                                                          0x1d
#define HWIO_GCC_GPLL11_MODE_PLL_LOCK_DET_FINE_BMSK                                                0x10000000
#define HWIO_GCC_GPLL11_MODE_PLL_LOCK_DET_FINE_SHFT                                                      0x1c
#define HWIO_GCC_GPLL11_MODE_PCAL_DONE_BMSK                                                         0x8000000
#define HWIO_GCC_GPLL11_MODE_PCAL_DONE_SHFT                                                              0x1b
#define HWIO_GCC_GPLL11_MODE_RESERVE_BITS26_25_BMSK                                                 0x6000000
#define HWIO_GCC_GPLL11_MODE_RESERVE_BITS26_25_SHFT                                                      0x19
#define HWIO_GCC_GPLL11_MODE_FSM_LEGACY_MODE_BMSK                                                   0x1000000
#define HWIO_GCC_GPLL11_MODE_FSM_LEGACY_MODE_SHFT                                                        0x18
#define HWIO_GCC_GPLL11_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_BMSK                                         0x800000
#define HWIO_GCC_GPLL11_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_SHFT                                             0x17
#define HWIO_GCC_GPLL11_MODE_PLL_UPDATE_BMSK                                                         0x400000
#define HWIO_GCC_GPLL11_MODE_PLL_UPDATE_SHFT                                                             0x16
#define HWIO_GCC_GPLL11_MODE_PLL_VOTE_FSM_RESET_BMSK                                                 0x200000
#define HWIO_GCC_GPLL11_MODE_PLL_VOTE_FSM_RESET_SHFT                                                     0x15
#define HWIO_GCC_GPLL11_MODE_PLL_VOTE_FSM_ENA_BMSK                                                   0x100000
#define HWIO_GCC_GPLL11_MODE_PLL_VOTE_FSM_ENA_SHFT                                                       0x14
#define HWIO_GCC_GPLL11_MODE_PLL_BIAS_COUNT_BMSK                                                      0xfc000
#define HWIO_GCC_GPLL11_MODE_PLL_BIAS_COUNT_SHFT                                                          0xe
#define HWIO_GCC_GPLL11_MODE_PLL_LOCK_COUNT_BMSK                                                       0x3f00
#define HWIO_GCC_GPLL11_MODE_PLL_LOCK_COUNT_SHFT                                                          0x8
#define HWIO_GCC_GPLL11_MODE_RESERVE_BIT7_BMSK                                                           0x80
#define HWIO_GCC_GPLL11_MODE_RESERVE_BIT7_SHFT                                                            0x7
#define HWIO_GCC_GPLL11_MODE_OUT_TEST_HW_CTL_BMSK                                                        0x40
#define HWIO_GCC_GPLL11_MODE_OUT_TEST_HW_CTL_SHFT                                                         0x6
#define HWIO_GCC_GPLL11_MODE_OUT_ODD_HW_CTL_BMSK                                                         0x20
#define HWIO_GCC_GPLL11_MODE_OUT_ODD_HW_CTL_SHFT                                                          0x5
#define HWIO_GCC_GPLL11_MODE_OUT_EVEN_HW_CTL_BMSK                                                        0x10
#define HWIO_GCC_GPLL11_MODE_OUT_EVEN_HW_CTL_SHFT                                                         0x4
#define HWIO_GCC_GPLL11_MODE_OUT_MAIN_HW_CTL_BMSK                                                         0x8
#define HWIO_GCC_GPLL11_MODE_OUT_MAIN_HW_CTL_SHFT                                                         0x3
#define HWIO_GCC_GPLL11_MODE_PLL_RESET_N_BMSK                                                             0x4
#define HWIO_GCC_GPLL11_MODE_PLL_RESET_N_SHFT                                                             0x2
#define HWIO_GCC_GPLL11_MODE_RESERVE_BIT1_BMSK                                                            0x2
#define HWIO_GCC_GPLL11_MODE_RESERVE_BIT1_SHFT                                                            0x1
#define HWIO_GCC_GPLL11_MODE_PLL_OUTCTRL_BMSK                                                             0x1
#define HWIO_GCC_GPLL11_MODE_PLL_OUTCTRL_SHFT                                                             0x0

#define HWIO_GCC_GPLL11_L_VAL_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a004)
#define HWIO_GCC_GPLL11_L_VAL_RMSK                                                                     0xffff
#define HWIO_GCC_GPLL11_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL11_L_VAL_ADDR)
#define HWIO_GCC_GPLL11_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL11_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL11_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_L_VAL_ADDR,m,v,HWIO_GCC_GPLL11_L_VAL_IN)
#define HWIO_GCC_GPLL11_L_VAL_PLL_L_BMSK                                                               0xffff
#define HWIO_GCC_GPLL11_L_VAL_PLL_L_SHFT                                                                  0x0

#define HWIO_GCC_GPLL11_CAL_L_VAL_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a008)
#define HWIO_GCC_GPLL11_CAL_L_VAL_RMSK                                                                 0xffff
#define HWIO_GCC_GPLL11_CAL_L_VAL_IN          \
        in_dword(HWIO_GCC_GPLL11_CAL_L_VAL_ADDR)
#define HWIO_GCC_GPLL11_CAL_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_CAL_L_VAL_ADDR, m)
#define HWIO_GCC_GPLL11_CAL_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_CAL_L_VAL_ADDR,v)
#define HWIO_GCC_GPLL11_CAL_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_CAL_L_VAL_ADDR,m,v,HWIO_GCC_GPLL11_CAL_L_VAL_IN)
#define HWIO_GCC_GPLL11_CAL_L_VAL_PLL_CAL_L_BMSK                                                       0xffff
#define HWIO_GCC_GPLL11_CAL_L_VAL_PLL_CAL_L_SHFT                                                          0x0

#define HWIO_GCC_GPLL11_USER_CTL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a00c)
#define HWIO_GCC_GPLL11_USER_CTL_RMSK                                                              0xffffffff
#define HWIO_GCC_GPLL11_USER_CTL_IN          \
        in_dword(HWIO_GCC_GPLL11_USER_CTL_ADDR)
#define HWIO_GCC_GPLL11_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_USER_CTL_ADDR, m)
#define HWIO_GCC_GPLL11_USER_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_USER_CTL_ADDR,v)
#define HWIO_GCC_GPLL11_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_USER_CTL_ADDR,m,v,HWIO_GCC_GPLL11_USER_CTL_IN)
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT31_BMSK                                                0x80000000
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT31_SHFT                                                      0x1f
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT30_BMSK                                                0x40000000
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT30_SHFT                                                      0x1e
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT29_BMSK                                                0x20000000
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT29_SHFT                                                      0x1d
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT28_BMSK                                                0x10000000
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT28_SHFT                                                      0x1c
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT27_BMSK                                                 0x8000000
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT27_SHFT                                                      0x1b
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT26_BMSK                                                 0x4000000
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT26_SHFT                                                      0x1a
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT25_BMSK                                                 0x2000000
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT25_SHFT                                                      0x19
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT24_BMSK                                                 0x1000000
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT24_SHFT                                                      0x18
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT23_BMSK                                                  0x800000
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT23_SHFT                                                      0x17
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT22_BMSK                                                  0x400000
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT22_SHFT                                                      0x16
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT21_BMSK                                                  0x200000
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT21_SHFT                                                      0x15
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT20_BMSK                                                  0x100000
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT20_SHFT                                                      0x14
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT19_BMSK                                                   0x80000
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT19_SHFT                                                      0x13
#define HWIO_GCC_GPLL11_USER_CTL_PRE_DIV_RATIO_BMSK                                                   0x70000
#define HWIO_GCC_GPLL11_USER_CTL_PRE_DIV_RATIO_SHFT                                                      0x10
#define HWIO_GCC_GPLL11_USER_CTL_POST_DIV_RATIO_ODD_BMSK                                               0xf000
#define HWIO_GCC_GPLL11_USER_CTL_POST_DIV_RATIO_ODD_SHFT                                                  0xc
#define HWIO_GCC_GPLL11_USER_CTL_POST_DIV_RATIO_EVEN_BMSK                                               0xf00
#define HWIO_GCC_GPLL11_USER_CTL_POST_DIV_RATIO_EVEN_SHFT                                                 0x8
#define HWIO_GCC_GPLL11_USER_CTL_OUT_CLK_POLARITY_BMSK                                                   0x80
#define HWIO_GCC_GPLL11_USER_CTL_OUT_CLK_POLARITY_SHFT                                                    0x7
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT6_BMSK                                                       0x40
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT6_SHFT                                                        0x6
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT5_BMSK                                                       0x20
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT5_SHFT                                                        0x5
#define HWIO_GCC_GPLL11_USER_CTL_PLLOUT_TEST_BMSK                                                        0x10
#define HWIO_GCC_GPLL11_USER_CTL_PLLOUT_TEST_SHFT                                                         0x4
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT3_BMSK                                                        0x8
#define HWIO_GCC_GPLL11_USER_CTL_RESERVE_BIT3_SHFT                                                        0x3
#define HWIO_GCC_GPLL11_USER_CTL_PLLOUT_ODD_BMSK                                                          0x4
#define HWIO_GCC_GPLL11_USER_CTL_PLLOUT_ODD_SHFT                                                          0x2
#define HWIO_GCC_GPLL11_USER_CTL_PLLOUT_EVEN_BMSK                                                         0x2
#define HWIO_GCC_GPLL11_USER_CTL_PLLOUT_EVEN_SHFT                                                         0x1
#define HWIO_GCC_GPLL11_USER_CTL_PLLOUT_MAIN_BMSK                                                         0x1
#define HWIO_GCC_GPLL11_USER_CTL_PLLOUT_MAIN_SHFT                                                         0x0

#define HWIO_GCC_GPLL11_USER_CTL_U_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a010)
#define HWIO_GCC_GPLL11_USER_CTL_U_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL11_USER_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL11_USER_CTL_U_ADDR)
#define HWIO_GCC_GPLL11_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_USER_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL11_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_USER_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL11_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_USER_CTL_U_ADDR,m,v,HWIO_GCC_GPLL11_USER_CTL_U_IN)
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT63_BMSK                                              0x80000000
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT63_SHFT                                                    0x1f
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT62_BMSK                                              0x40000000
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT62_SHFT                                                    0x1e
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT61_BMSK                                              0x20000000
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT61_SHFT                                                    0x1d
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT60_BMSK                                              0x10000000
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT60_SHFT                                                    0x1c
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT59_BMSK                                               0x8000000
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT59_SHFT                                                    0x1b
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT58_BMSK                                               0x4000000
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT58_SHFT                                                    0x1a
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT57_BMSK                                               0x2000000
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT57_SHFT                                                    0x19
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT56_BMSK                                               0x1000000
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT56_SHFT                                                    0x18
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT55_BMSK                                                0x800000
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT55_SHFT                                                    0x17
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT54_BMSK                                                0x400000
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT54_SHFT                                                    0x16
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT53_BMSK                                                0x200000
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT53_SHFT                                                    0x15
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT52_BMSK                                                0x100000
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT52_SHFT                                                    0x14
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT51_BMSK                                                 0x80000
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT51_SHFT                                                    0x13
#define HWIO_GCC_GPLL11_USER_CTL_U_LOCK_DETECTOR_SELECTION_BMSK                                       0x40000
#define HWIO_GCC_GPLL11_USER_CTL_U_LOCK_DETECTOR_SELECTION_SHFT                                          0x12
#define HWIO_GCC_GPLL11_USER_CTL_U_TYPE_2_MODE_SELECTION_BMSK                                         0x20000
#define HWIO_GCC_GPLL11_USER_CTL_U_TYPE_2_MODE_SELECTION_SHFT                                            0x11
#define HWIO_GCC_GPLL11_USER_CTL_U_BANG_BANG_MODE_SELECTION_BMSK                                      0x10000
#define HWIO_GCC_GPLL11_USER_CTL_U_BANG_BANG_MODE_SELECTION_SHFT                                         0x10
#define HWIO_GCC_GPLL11_USER_CTL_U_FRAC_FORMAT_SEL_BMSK                                                0x8000
#define HWIO_GCC_GPLL11_USER_CTL_U_FRAC_FORMAT_SEL_SHFT                                                   0xf
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT46_BMSK                                                  0x4000
#define HWIO_GCC_GPLL11_USER_CTL_U_RESERVE_BIT46_SHFT                                                     0xe
#define HWIO_GCC_GPLL11_USER_CTL_U_REF_CLK_AT_OUT_BMSK                                                 0x2000
#define HWIO_GCC_GPLL11_USER_CTL_U_REF_CLK_AT_OUT_SHFT                                                    0xd
#define HWIO_GCC_GPLL11_USER_CTL_U_SCALE_FREQ_ON_RESTART_BMSK                                          0x1800
#define HWIO_GCC_GPLL11_USER_CTL_U_SCALE_FREQ_ON_RESTART_SHFT                                             0xb
#define HWIO_GCC_GPLL11_USER_CTL_U_LATCH_INTERFACE_BYPASS_BMSK                                          0x400
#define HWIO_GCC_GPLL11_USER_CTL_U_LATCH_INTERFACE_BYPASS_SHFT                                            0xa
#define HWIO_GCC_GPLL11_USER_CTL_U_STATUS_REGISTER_BMSK                                                 0x3e0
#define HWIO_GCC_GPLL11_USER_CTL_U_STATUS_REGISTER_SHFT                                                   0x5
#define HWIO_GCC_GPLL11_USER_CTL_U_WRITE_STATE_EN_BMSK                                                   0x10
#define HWIO_GCC_GPLL11_USER_CTL_U_WRITE_STATE_EN_SHFT                                                    0x4
#define HWIO_GCC_GPLL11_USER_CTL_U_CALIB_CTRL_BMSK                                                        0xe
#define HWIO_GCC_GPLL11_USER_CTL_U_CALIB_CTRL_SHFT                                                        0x1
#define HWIO_GCC_GPLL11_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_BMSK                                            0x1
#define HWIO_GCC_GPLL11_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_SHFT                                            0x0

#define HWIO_GCC_GPLL11_USER_CTL_U1_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a014)
#define HWIO_GCC_GPLL11_USER_CTL_U1_RMSK                                                           0xffffffff
#define HWIO_GCC_GPLL11_USER_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL11_USER_CTL_U1_ADDR)
#define HWIO_GCC_GPLL11_USER_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_USER_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL11_USER_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_USER_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL11_USER_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_USER_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL11_USER_CTL_U1_IN)
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT95_BMSK                                             0x80000000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT95_SHFT                                                   0x1f
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT94_BMSK                                             0x40000000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT94_SHFT                                                   0x1e
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT93_BMSK                                             0x20000000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT93_SHFT                                                   0x1d
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT92_BMSK                                             0x10000000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT92_SHFT                                                   0x1c
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT91_BMSK                                              0x8000000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT91_SHFT                                                   0x1b
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT90_BMSK                                              0x4000000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT90_SHFT                                                   0x1a
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT89_BMSK                                              0x2000000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT89_SHFT                                                   0x19
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT88_BMSK                                              0x1000000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT88_SHFT                                                   0x18
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT87_BMSK                                               0x800000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT87_SHFT                                                   0x17
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT86_BMSK                                               0x400000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT86_SHFT                                                   0x16
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT85_BMSK                                               0x200000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT85_SHFT                                                   0x15
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT84_BMSK                                               0x100000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT84_SHFT                                                   0x14
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT83_BMSK                                                0x80000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT83_SHFT                                                   0x13
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT82_BMSK                                                0x40000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT82_SHFT                                                   0x12
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT81_BMSK                                                0x20000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT81_SHFT                                                   0x11
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT80_BMSK                                                0x10000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT80_SHFT                                                   0x10
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT79_BMSK                                                 0x8000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT79_SHFT                                                    0xf
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT78_BMSK                                                 0x4000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT78_SHFT                                                    0xe
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT77_BMSK                                                 0x2000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT77_SHFT                                                    0xd
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT76_BMSK                                                 0x1000
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT76_SHFT                                                    0xc
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT75_BMSK                                                  0x800
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT75_SHFT                                                    0xb
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT74_BMSK                                                  0x400
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT74_SHFT                                                    0xa
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT73_BMSK                                                  0x200
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT73_SHFT                                                    0x9
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT72_BMSK                                                  0x100
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT72_SHFT                                                    0x8
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT71_BMSK                                                   0x80
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT71_SHFT                                                    0x7
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT70_BMSK                                                   0x40
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT70_SHFT                                                    0x6
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT69_BMSK                                                   0x20
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT69_SHFT                                                    0x5
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT68_BMSK                                                   0x10
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT68_SHFT                                                    0x4
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT67_BMSK                                                    0x8
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT67_SHFT                                                    0x3
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT66_BMSK                                                    0x4
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT66_SHFT                                                    0x2
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT65_BMSK                                                    0x2
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT65_SHFT                                                    0x1
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT64_BMSK                                                    0x1
#define HWIO_GCC_GPLL11_USER_CTL_U1_RESERVE_BIT64_SHFT                                                    0x0

#define HWIO_GCC_GPLL11_CONFIG_CTL_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a018)
#define HWIO_GCC_GPLL11_CONFIG_CTL_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL11_CONFIG_CTL_IN          \
        in_dword(HWIO_GCC_GPLL11_CONFIG_CTL_ADDR)
#define HWIO_GCC_GPLL11_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_CONFIG_CTL_ADDR, m)
#define HWIO_GCC_GPLL11_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_CONFIG_CTL_ADDR,v)
#define HWIO_GCC_GPLL11_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_CONFIG_CTL_ADDR,m,v,HWIO_GCC_GPLL11_CONFIG_CTL_IN)
#define HWIO_GCC_GPLL11_CONFIG_CTL_FINE_LDC_THRESHOLD_BMSK                                         0xfc000000
#define HWIO_GCC_GPLL11_CONFIG_CTL_FINE_LDC_THRESHOLD_SHFT                                               0x1a
#define HWIO_GCC_GPLL11_CONFIG_CTL_COARSE_LDC_THRESHOLD_BMSK                                        0x3c00000
#define HWIO_GCC_GPLL11_CONFIG_CTL_COARSE_LDC_THRESHOLD_SHFT                                             0x16
#define HWIO_GCC_GPLL11_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_BMSK                                0x3c0000
#define HWIO_GCC_GPLL11_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_SHFT                                    0x12
#define HWIO_GCC_GPLL11_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_BMSK                                 0x3c000
#define HWIO_GCC_GPLL11_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_SHFT                                     0xe
#define HWIO_GCC_GPLL11_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_BMSK                                        0x3800
#define HWIO_GCC_GPLL11_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_SHFT                                           0xb
#define HWIO_GCC_GPLL11_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_BMSK                                       0x700
#define HWIO_GCC_GPLL11_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_SHFT                                         0x8
#define HWIO_GCC_GPLL11_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_BMSK                                             0xf0
#define HWIO_GCC_GPLL11_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_SHFT                                              0x4
#define HWIO_GCC_GPLL11_CONFIG_CTL_FWD_GAIN_KFN_BMSK                                                      0xf
#define HWIO_GCC_GPLL11_CONFIG_CTL_FWD_GAIN_KFN_SHFT                                                      0x0

#define HWIO_GCC_GPLL11_CONFIG_CTL_U_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a01c)
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_RMSK                                                          0xffffffff
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL11_CONFIG_CTL_U_ADDR)
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_CONFIG_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_CONFIG_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_CONFIG_CTL_U_ADDR,m,v,HWIO_GCC_GPLL11_CONFIG_CTL_U_IN)
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_BIST_CFG_BMSK                                                 0xffff0000
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_BIST_CFG_SHFT                                                       0x10
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_BMSK                                      0xc000
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_SHFT                                         0xe
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_OSC_SETTLING_TIME_BMSK                                            0x3000
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_OSC_SETTLING_TIME_SHFT                                               0xc
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_BMSK                                           0xc00
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_SHFT                                             0xa
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_CASC_CURRENT_CTL_B_BMSK                                            0x380
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_CASC_CURRENT_CTL_B_SHFT                                              0x7
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_BMSK                                    0x40
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_SHFT                                     0x6
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_BMSK                                           0x30
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_SHFT                                            0x4
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_LDET_THRESH_SCALE_BMSK                                               0x8
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_LDET_THRESH_SCALE_SHFT                                               0x3
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_DCO_STARTUP_CONFIG_BMSK                                              0x6
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_DCO_STARTUP_CONFIG_SHFT                                              0x1
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_BMSK                                         0x1
#define HWIO_GCC_GPLL11_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_SHFT                                         0x0

#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a020)
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_RMSK                                                         0xffffffff
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL11_CONFIG_CTL_U1_ADDR)
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_CONFIG_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_CONFIG_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_CONFIG_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL11_CONFIG_CTL_U1_IN)
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BB_CAL_THRESHOLD_BMSK                                        0xc0000000
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BB_CAL_THRESHOLD_SHFT                                              0x1e
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_PCODE_OFFSET_BMSK                                            0x38000000
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_PCODE_OFFSET_SHFT                                                  0x1b
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_COUNTER_BLANK_BMSK                                            0x4000000
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_COUNTER_BLANK_SHFT                                                 0x1a
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BB_RESYNC_EDGE_BMSK                                           0x2000000
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BB_RESYNC_EDGE_SHFT                                                0x19
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BB_RESYNC_SEL_BMSK                                            0x1000000
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BB_RESYNC_SEL_SHFT                                                 0x18
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_BMSK                                       0xc00000
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_SHFT                                           0x16
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BB_LOCK_THRESH_BMSK                                            0x380000
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BB_LOCK_THRESH_SHFT                                                0x13
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_RESERVE_BIT82_BMSK                                              0x40000
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_RESERVE_BIT82_SHFT                                                 0x12
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_BMSK                                         0x30000
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_SHFT                                            0x10
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_BMSK                                           0xc000
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_SHFT                                              0xe
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BB_CAL_EN_BMSK                                                   0x2000
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BB_CAL_EN_SHFT                                                      0xd
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_BMSK                                     0x1800
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_SHFT                                        0xb
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BBMODE_INT_GAIN_BMSK                                              0x780
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BBMODE_INT_GAIN_SHFT                                                0x7
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BBMODE_PROP_GAIN_BMSK                                              0x78
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_BBMODE_PROP_GAIN_SHFT                                               0x3
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_TDC_SELECTION_BMSK                                                  0x4
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_TDC_SELECTION_SHFT                                                  0x2
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_RESERVE_BIT65_BMSK                                                  0x2
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_RESERVE_BIT65_SHFT                                                  0x1
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_FORCE_DSM_ON_BMSK                                                   0x1
#define HWIO_GCC_GPLL11_CONFIG_CTL_U1_FORCE_DSM_ON_SHFT                                                   0x0

#define HWIO_GCC_GPLL11_TEST_CTL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a024)
#define HWIO_GCC_GPLL11_TEST_CTL_RMSK                                                              0xffffffff
#define HWIO_GCC_GPLL11_TEST_CTL_IN          \
        in_dword(HWIO_GCC_GPLL11_TEST_CTL_ADDR)
#define HWIO_GCC_GPLL11_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_TEST_CTL_ADDR, m)
#define HWIO_GCC_GPLL11_TEST_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_TEST_CTL_ADDR,v)
#define HWIO_GCC_GPLL11_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_TEST_CTL_ADDR,m,v,HWIO_GCC_GPLL11_TEST_CTL_IN)
#define HWIO_GCC_GPLL11_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_BMSK                                      0xc0000000
#define HWIO_GCC_GPLL11_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_SHFT                                            0x1e
#define HWIO_GCC_GPLL11_TEST_CTL_BYPASS_FIRST_ORDER_DSM_BMSK                                       0x20000000
#define HWIO_GCC_GPLL11_TEST_CTL_BYPASS_FIRST_ORDER_DSM_SHFT                                             0x1d
#define HWIO_GCC_GPLL11_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_BMSK                                  0x18000000
#define HWIO_GCC_GPLL11_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_SHFT                                        0x1b
#define HWIO_GCC_GPLL11_TEST_CTL_GLITCH_PREVENTION_DIS_BMSK                                         0x4000000
#define HWIO_GCC_GPLL11_TEST_CTL_GLITCH_PREVENTION_DIS_SHFT                                              0x1a
#define HWIO_GCC_GPLL11_TEST_CTL_ATEST_ISCALE_BMSK                                                  0x3000000
#define HWIO_GCC_GPLL11_TEST_CTL_ATEST_ISCALE_SHFT                                                       0x18
#define HWIO_GCC_GPLL11_TEST_CTL_PLL_TEST_OUT_SEL_BMSK                                               0xf00000
#define HWIO_GCC_GPLL11_TEST_CTL_PLL_TEST_OUT_SEL_SHFT                                                   0x14
#define HWIO_GCC_GPLL11_TEST_CTL_RESERVE_BIT19_BMSK                                                   0x80000
#define HWIO_GCC_GPLL11_TEST_CTL_RESERVE_BIT19_SHFT                                                      0x13
#define HWIO_GCC_GPLL11_TEST_CTL_DIV2_NMO_EN_BMSK                                                     0x40000
#define HWIO_GCC_GPLL11_TEST_CTL_DIV2_NMO_EN_SHFT                                                        0x12
#define HWIO_GCC_GPLL11_TEST_CTL_NMO_OSC_SEL_BMSK                                                     0x30000
#define HWIO_GCC_GPLL11_TEST_CTL_NMO_OSC_SEL_SHFT                                                        0x10
#define HWIO_GCC_GPLL11_TEST_CTL_NOISE_MAG_BMSK                                                        0xe000
#define HWIO_GCC_GPLL11_TEST_CTL_NOISE_MAG_SHFT                                                           0xd
#define HWIO_GCC_GPLL11_TEST_CTL_NOISE_GEN_EN_BMSK                                                     0x1000
#define HWIO_GCC_GPLL11_TEST_CTL_NOISE_GEN_EN_SHFT                                                        0xc
#define HWIO_GCC_GPLL11_TEST_CTL_DISABLE_DCAPS_BMSK                                                     0x800
#define HWIO_GCC_GPLL11_TEST_CTL_DISABLE_DCAPS_SHFT                                                       0xb
#define HWIO_GCC_GPLL11_TEST_CTL_RESERVE_BIT10_BMSK                                                     0x400
#define HWIO_GCC_GPLL11_TEST_CTL_RESERVE_BIT10_SHFT                                                       0xa
#define HWIO_GCC_GPLL11_TEST_CTL_RESERVE_BIT9_BMSK                                                      0x200
#define HWIO_GCC_GPLL11_TEST_CTL_RESERVE_BIT9_SHFT                                                        0x9
#define HWIO_GCC_GPLL11_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_BMSK                                           0x100
#define HWIO_GCC_GPLL11_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_SHFT                                             0x8
#define HWIO_GCC_GPLL11_TEST_CTL_EN_VDD_TEST_BMSK                                                        0x80
#define HWIO_GCC_GPLL11_TEST_CTL_EN_VDD_TEST_SHFT                                                         0x7
#define HWIO_GCC_GPLL11_TEST_CTL_EN_VREG_TEST_BMSK                                                       0x40
#define HWIO_GCC_GPLL11_TEST_CTL_EN_VREG_TEST_SHFT                                                        0x6
#define HWIO_GCC_GPLL11_TEST_CTL_EN_VREF_TEST_BMSK                                                       0x20
#define HWIO_GCC_GPLL11_TEST_CTL_EN_VREF_TEST_SHFT                                                        0x5
#define HWIO_GCC_GPLL11_TEST_CTL_EN_VDCO_TEST_BMSK                                                       0x10
#define HWIO_GCC_GPLL11_TEST_CTL_EN_VDCO_TEST_SHFT                                                        0x4
#define HWIO_GCC_GPLL11_TEST_CTL_BYPASS_ATEST_BUFFER_BMSK                                                 0x8
#define HWIO_GCC_GPLL11_TEST_CTL_BYPASS_ATEST_BUFFER_SHFT                                                 0x3
#define HWIO_GCC_GPLL11_TEST_CTL_EN_IVCO_TEST_BMSK                                                        0x4
#define HWIO_GCC_GPLL11_TEST_CTL_EN_IVCO_TEST_SHFT                                                        0x2
#define HWIO_GCC_GPLL11_TEST_CTL_ATEST1_EN_BMSK                                                           0x2
#define HWIO_GCC_GPLL11_TEST_CTL_ATEST1_EN_SHFT                                                           0x1
#define HWIO_GCC_GPLL11_TEST_CTL_ATEST0_EN_BMSK                                                           0x1
#define HWIO_GCC_GPLL11_TEST_CTL_ATEST0_EN_SHFT                                                           0x0

#define HWIO_GCC_GPLL11_TEST_CTL_U_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a028)
#define HWIO_GCC_GPLL11_TEST_CTL_U_RMSK                                                            0xffffffff
#define HWIO_GCC_GPLL11_TEST_CTL_U_IN          \
        in_dword(HWIO_GCC_GPLL11_TEST_CTL_U_ADDR)
#define HWIO_GCC_GPLL11_TEST_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_TEST_CTL_U_ADDR, m)
#define HWIO_GCC_GPLL11_TEST_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_TEST_CTL_U_ADDR,v)
#define HWIO_GCC_GPLL11_TEST_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_TEST_CTL_U_ADDR,m,v,HWIO_GCC_GPLL11_TEST_CTL_U_IN)
#define HWIO_GCC_GPLL11_TEST_CTL_U_CASC_DAC_FCW_LSBS_BMSK                                          0xe0000000
#define HWIO_GCC_GPLL11_TEST_CTL_U_CASC_DAC_FCW_LSBS_SHFT                                                0x1d
#define HWIO_GCC_GPLL11_TEST_CTL_U_OVERRIDE_CASC_DAC_BMSK                                          0x10000000
#define HWIO_GCC_GPLL11_TEST_CTL_U_OVERRIDE_CASC_DAC_SHFT                                                0x1c
#define HWIO_GCC_GPLL11_TEST_CTL_U_COMP_COARSE_FCW_BMSK                                             0xe000000
#define HWIO_GCC_GPLL11_TEST_CTL_U_COMP_COARSE_FCW_SHFT                                                  0x19
#define HWIO_GCC_GPLL11_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_BMSK                                    0x1800000
#define HWIO_GCC_GPLL11_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_SHFT                                         0x17
#define HWIO_GCC_GPLL11_TEST_CTL_U_FINE_FCW_BMSK                                                     0x7e0000
#define HWIO_GCC_GPLL11_TEST_CTL_U_FINE_FCW_SHFT                                                         0x11
#define HWIO_GCC_GPLL11_TEST_CTL_U_OVERRIDE_FINE_FCW_BMSK                                             0x10000
#define HWIO_GCC_GPLL11_TEST_CTL_U_OVERRIDE_FINE_FCW_SHFT                                                0x10
#define HWIO_GCC_GPLL11_TEST_CTL_U_REG_COARSE_FCW_BMSK                                                 0xfe00
#define HWIO_GCC_GPLL11_TEST_CTL_U_REG_COARSE_FCW_SHFT                                                    0x9
#define HWIO_GCC_GPLL11_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_BMSK                                         0x100
#define HWIO_GCC_GPLL11_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_SHFT                                           0x8
#define HWIO_GCC_GPLL11_TEST_CTL_U_PROCESS_CALIB_WORD_BMSK                                               0xe0
#define HWIO_GCC_GPLL11_TEST_CTL_U_PROCESS_CALIB_WORD_SHFT                                                0x5
#define HWIO_GCC_GPLL11_TEST_CTL_U_OVERRIDE_CALIB_WORD_BMSK                                              0x10
#define HWIO_GCC_GPLL11_TEST_CTL_U_OVERRIDE_CALIB_WORD_SHFT                                               0x4
#define HWIO_GCC_GPLL11_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_BMSK                                            0x8
#define HWIO_GCC_GPLL11_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_SHFT                                            0x3
#define HWIO_GCC_GPLL11_TEST_CTL_U_DISABLE_LFSR_BMSK                                                      0x4
#define HWIO_GCC_GPLL11_TEST_CTL_U_DISABLE_LFSR_SHFT                                                      0x2
#define HWIO_GCC_GPLL11_TEST_CTL_U_SKIP_FINE_TUNE_BMSK                                                    0x2
#define HWIO_GCC_GPLL11_TEST_CTL_U_SKIP_FINE_TUNE_SHFT                                                    0x1
#define HWIO_GCC_GPLL11_TEST_CTL_U_SKIP_FAST_LOCK_BMSK                                                    0x1
#define HWIO_GCC_GPLL11_TEST_CTL_U_SKIP_FAST_LOCK_SHFT                                                    0x0

#define HWIO_GCC_GPLL11_TEST_CTL_U1_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a02c)
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RMSK                                                           0xffffffff
#define HWIO_GCC_GPLL11_TEST_CTL_U1_IN          \
        in_dword(HWIO_GCC_GPLL11_TEST_CTL_U1_ADDR)
#define HWIO_GCC_GPLL11_TEST_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_TEST_CTL_U1_ADDR, m)
#define HWIO_GCC_GPLL11_TEST_CTL_U1_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_TEST_CTL_U1_ADDR,v)
#define HWIO_GCC_GPLL11_TEST_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_TEST_CTL_U1_ADDR,m,v,HWIO_GCC_GPLL11_TEST_CTL_U1_IN)
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT95_BMSK                                             0x80000000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT95_SHFT                                                   0x1f
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT94_BMSK                                             0x40000000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT94_SHFT                                                   0x1e
#define HWIO_GCC_GPLL11_TEST_CTL_U1_FLL_COUNT_DISABLE_BMSK                                         0x20000000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_FLL_COUNT_DISABLE_SHFT                                               0x1d
#define HWIO_GCC_GPLL11_TEST_CTL_U1_FLL_COUNT_IN_DIV2_BMSK                                         0x10000000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_FLL_COUNT_IN_DIV2_SHFT                                               0x1c
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT91_BMSK                                              0x8000000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT91_SHFT                                                   0x1b
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT90_BMSK                                              0x4000000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT90_SHFT                                                   0x1a
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT89_BMSK                                              0x2000000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT89_SHFT                                                   0x19
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT88_BMSK                                              0x1000000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT88_SHFT                                                   0x18
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT87_BMSK                                               0x800000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT87_SHFT                                                   0x17
#define HWIO_GCC_GPLL11_TEST_CTL_U1_SILENCE_REF_OUTBUF_BMSK                                          0x400000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_SILENCE_REF_OUTBUF_SHFT                                              0x16
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT85_BMSK                                               0x200000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT85_SHFT                                                   0x15
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT84_BMSK                                               0x100000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT84_SHFT                                                   0x14
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT83_BMSK                                                0x80000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT83_SHFT                                                   0x13
#define HWIO_GCC_GPLL11_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_BMSK                                        0x40000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_SHFT                                           0x12
#define HWIO_GCC_GPLL11_TEST_CTL_U1_REF_CLK_SEL_BMSK                                                  0x20000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_REF_CLK_SEL_SHFT                                                     0x11
#define HWIO_GCC_GPLL11_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_BMSK                                    0x10000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_SHFT                                       0x10
#define HWIO_GCC_GPLL11_TEST_CTL_U1_DIS_AMP_STARTUP_BMSK                                               0x8000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_DIS_AMP_STARTUP_SHFT                                                  0xf
#define HWIO_GCC_GPLL11_TEST_CTL_U1_DISABLE_CLAMP_BMSK                                                 0x4000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_DISABLE_CLAMP_SHFT                                                    0xe
#define HWIO_GCC_GPLL11_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_BMSK                                       0x2000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_SHFT                                          0xd
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT76_BMSK                                                 0x1000
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT76_SHFT                                                    0xc
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT75_BMSK                                                  0x800
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT75_SHFT                                                    0xb
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT74_BMSK                                                  0x400
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT74_SHFT                                                    0xa
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT73_BMSK                                                  0x200
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT73_SHFT                                                    0x9
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT72_BMSK                                                  0x100
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT72_SHFT                                                    0x8
#define HWIO_GCC_GPLL11_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_BMSK                                         0x80
#define HWIO_GCC_GPLL11_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_SHFT                                          0x7
#define HWIO_GCC_GPLL11_TEST_CTL_U1_ENABLE_TRAINING_SEQ_BMSK                                             0x40
#define HWIO_GCC_GPLL11_TEST_CTL_U1_ENABLE_TRAINING_SEQ_SHFT                                              0x6
#define HWIO_GCC_GPLL11_TEST_CTL_U1_STATUS_REG_EN_BMSK                                                   0x20
#define HWIO_GCC_GPLL11_TEST_CTL_U1_STATUS_REG_EN_SHFT                                                    0x5
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT68_BMSK                                                   0x10
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT68_SHFT                                                    0x4
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT67_BMSK                                                    0x8
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT67_SHFT                                                    0x3
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT66_BMSK                                                    0x4
#define HWIO_GCC_GPLL11_TEST_CTL_U1_RESERVE_BIT66_SHFT                                                    0x2
#define HWIO_GCC_GPLL11_TEST_CTL_U1_CASC_DAC_FCW_MSBS_BMSK                                                0x3
#define HWIO_GCC_GPLL11_TEST_CTL_U1_CASC_DAC_FCW_MSBS_SHFT                                                0x0

#define HWIO_GCC_GPLL11_STATUS_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a030)
#define HWIO_GCC_GPLL11_STATUS_RMSK                                                                0xffffffff
#define HWIO_GCC_GPLL11_STATUS_IN          \
        in_dword(HWIO_GCC_GPLL11_STATUS_ADDR)
#define HWIO_GCC_GPLL11_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_STATUS_ADDR, m)
#define HWIO_GCC_GPLL11_STATUS_STATUS_31_0_BMSK                                                    0xffffffff
#define HWIO_GCC_GPLL11_STATUS_STATUS_31_0_SHFT                                                           0x0

#define HWIO_GCC_GPLL11_FREQ_CTL_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a034)
#define HWIO_GCC_GPLL11_FREQ_CTL_RMSK                                                              0xffffffff
#define HWIO_GCC_GPLL11_FREQ_CTL_IN          \
        in_dword(HWIO_GCC_GPLL11_FREQ_CTL_ADDR)
#define HWIO_GCC_GPLL11_FREQ_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_FREQ_CTL_ADDR, m)
#define HWIO_GCC_GPLL11_FREQ_CTL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_FREQ_CTL_ADDR,v)
#define HWIO_GCC_GPLL11_FREQ_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_FREQ_CTL_ADDR,m,v,HWIO_GCC_GPLL11_FREQ_CTL_IN)
#define HWIO_GCC_GPLL11_FREQ_CTL_FREQUENCY_CTL_WORD_BMSK                                           0xffffffff
#define HWIO_GCC_GPLL11_FREQ_CTL_FREQUENCY_CTL_WORD_SHFT                                                  0x0

#define HWIO_GCC_GPLL11_OPMODE_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a038)
#define HWIO_GCC_GPLL11_OPMODE_RMSK                                                                       0x7
#define HWIO_GCC_GPLL11_OPMODE_IN          \
        in_dword(HWIO_GCC_GPLL11_OPMODE_ADDR)
#define HWIO_GCC_GPLL11_OPMODE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_OPMODE_ADDR, m)
#define HWIO_GCC_GPLL11_OPMODE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_OPMODE_ADDR,v)
#define HWIO_GCC_GPLL11_OPMODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_OPMODE_ADDR,m,v,HWIO_GCC_GPLL11_OPMODE_IN)
#define HWIO_GCC_GPLL11_OPMODE_PLL_OPMODE_BMSK                                                            0x7
#define HWIO_GCC_GPLL11_OPMODE_PLL_OPMODE_SHFT                                                            0x0

#define HWIO_GCC_GPLL11_STATE_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a03c)
#define HWIO_GCC_GPLL11_STATE_RMSK                                                                        0x7
#define HWIO_GCC_GPLL11_STATE_IN          \
        in_dword(HWIO_GCC_GPLL11_STATE_ADDR)
#define HWIO_GCC_GPLL11_STATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_STATE_ADDR, m)
#define HWIO_GCC_GPLL11_STATE_PLL_STATE_BMSK                                                              0x7
#define HWIO_GCC_GPLL11_STATE_PLL_STATE_SHFT                                                              0x0

#define HWIO_GCC_GPLL11_ALPHA_VAL_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a040)
#define HWIO_GCC_GPLL11_ALPHA_VAL_RMSK                                                                 0xffff
#define HWIO_GCC_GPLL11_ALPHA_VAL_IN          \
        in_dword(HWIO_GCC_GPLL11_ALPHA_VAL_ADDR)
#define HWIO_GCC_GPLL11_ALPHA_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_ALPHA_VAL_ADDR, m)
#define HWIO_GCC_GPLL11_ALPHA_VAL_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_ALPHA_VAL_ADDR,v)
#define HWIO_GCC_GPLL11_ALPHA_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_ALPHA_VAL_ADDR,m,v,HWIO_GCC_GPLL11_ALPHA_VAL_IN)
#define HWIO_GCC_GPLL11_ALPHA_VAL_PLL_ALPHA_VAL_BMSK                                                   0xffff
#define HWIO_GCC_GPLL11_ALPHA_VAL_PLL_ALPHA_VAL_SHFT                                                      0x0

#define HWIO_GCC_GPLL11_SPARE_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a044)
#define HWIO_GCC_GPLL11_SPARE_RMSK                                                                       0xff
#define HWIO_GCC_GPLL11_SPARE_IN          \
        in_dword(HWIO_GCC_GPLL11_SPARE_ADDR)
#define HWIO_GCC_GPLL11_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_SPARE_ADDR, m)
#define HWIO_GCC_GPLL11_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_SPARE_ADDR,v)
#define HWIO_GCC_GPLL11_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_SPARE_ADDR,m,v,HWIO_GCC_GPLL11_SPARE_IN)
#define HWIO_GCC_GPLL11_SPARE_SPARE_OUTPUTS_BMSK                                                         0xf0
#define HWIO_GCC_GPLL11_SPARE_SPARE_OUTPUTS_SHFT                                                          0x4
#define HWIO_GCC_GPLL11_SPARE_SPARE_INPUTS_BMSK                                                           0xf
#define HWIO_GCC_GPLL11_SPARE_SPARE_INPUTS_SHFT                                                           0x0

#define HWIO_GCC_GPLL11_SSC_DELTA_ALPHA_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a048)
#define HWIO_GCC_GPLL11_SSC_DELTA_ALPHA_RMSK                                                             0xff
#define HWIO_GCC_GPLL11_SSC_DELTA_ALPHA_IN          \
        in_dword(HWIO_GCC_GPLL11_SSC_DELTA_ALPHA_ADDR)
#define HWIO_GCC_GPLL11_SSC_DELTA_ALPHA_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_SSC_DELTA_ALPHA_ADDR, m)
#define HWIO_GCC_GPLL11_SSC_DELTA_ALPHA_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_SSC_DELTA_ALPHA_ADDR,v)
#define HWIO_GCC_GPLL11_SSC_DELTA_ALPHA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_SSC_DELTA_ALPHA_ADDR,m,v,HWIO_GCC_GPLL11_SSC_DELTA_ALPHA_IN)
#define HWIO_GCC_GPLL11_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_BMSK                                             0xff
#define HWIO_GCC_GPLL11_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_SHFT                                              0x0

#define HWIO_GCC_GPLL11_SSC_NUM_STEPS_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a04c)
#define HWIO_GCC_GPLL11_SSC_NUM_STEPS_RMSK                                                                0xf
#define HWIO_GCC_GPLL11_SSC_NUM_STEPS_IN          \
        in_dword(HWIO_GCC_GPLL11_SSC_NUM_STEPS_ADDR)
#define HWIO_GCC_GPLL11_SSC_NUM_STEPS_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_SSC_NUM_STEPS_ADDR, m)
#define HWIO_GCC_GPLL11_SSC_NUM_STEPS_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_SSC_NUM_STEPS_ADDR,v)
#define HWIO_GCC_GPLL11_SSC_NUM_STEPS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_SSC_NUM_STEPS_ADDR,m,v,HWIO_GCC_GPLL11_SSC_NUM_STEPS_IN)
#define HWIO_GCC_GPLL11_SSC_NUM_STEPS_SSC_NUM_STEPS_BMSK                                                  0xf
#define HWIO_GCC_GPLL11_SSC_NUM_STEPS_SSC_NUM_STEPS_SHFT                                                  0x0

#define HWIO_GCC_GPLL11_SSC_UPDATE_RATE_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0004a050)
#define HWIO_GCC_GPLL11_SSC_UPDATE_RATE_RMSK                                                              0xf
#define HWIO_GCC_GPLL11_SSC_UPDATE_RATE_IN          \
        in_dword(HWIO_GCC_GPLL11_SSC_UPDATE_RATE_ADDR)
#define HWIO_GCC_GPLL11_SSC_UPDATE_RATE_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL11_SSC_UPDATE_RATE_ADDR, m)
#define HWIO_GCC_GPLL11_SSC_UPDATE_RATE_OUT(v)      \
        out_dword(HWIO_GCC_GPLL11_SSC_UPDATE_RATE_ADDR,v)
#define HWIO_GCC_GPLL11_SSC_UPDATE_RATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL11_SSC_UPDATE_RATE_ADDR,m,v,HWIO_GCC_GPLL11_SSC_UPDATE_RATE_IN)
#define HWIO_GCC_GPLL11_SSC_UPDATE_RATE_SSC_UPDATE_RATE_BMSK                                              0xf
#define HWIO_GCC_GPLL11_SSC_UPDATE_RATE_SSC_UPDATE_RATE_SHFT                                              0x0

#define HWIO_GCC_SYSTEM_NOC_BCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00004000)
#define HWIO_GCC_SYSTEM_NOC_BCR_RMSK                                                                      0x1
#define HWIO_GCC_SYSTEM_NOC_BCR_IN          \
        in_dword(HWIO_GCC_SYSTEM_NOC_BCR_ADDR)
#define HWIO_GCC_SYSTEM_NOC_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYSTEM_NOC_BCR_ADDR, m)
#define HWIO_GCC_SYSTEM_NOC_BCR_OUT(v)      \
        out_dword(HWIO_GCC_SYSTEM_NOC_BCR_ADDR,v)
#define HWIO_GCC_SYSTEM_NOC_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYSTEM_NOC_BCR_ADDR,m,v,HWIO_GCC_SYSTEM_NOC_BCR_IN)
#define HWIO_GCC_SYSTEM_NOC_BCR_BLK_ARES_BMSK                                                             0x1
#define HWIO_GCC_SYSTEM_NOC_BCR_BLK_ARES_SHFT                                                             0x0

#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00004004)
#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_RMSK                                                          0x80100005
#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_GC_AXI_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_GC_AXI_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_GC_AXI_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_GC_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_GC_AXI_CBCR_IN)
#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_CLK_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0000401c)
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_RMSK                                                         0x3ffffff
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x3ff8000
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_RCG_SW_CTRL_SHFT                                                   0xf
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_SW_PERF_STATE_BMSK                                              0x7800
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_SW_PERF_STATE_SHFT                                                 0xb
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_SW_OVERRIDE_BMSK                                                 0x400
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_SW_OVERRIDE_SHFT                                                   0xa
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                    0x200
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                      0x9
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_DFS_FSM_STATE_BMSK                                               0x1c0
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_DFS_FSM_STATE_SHFT                                                 0x6
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_HW_CLK_CONTROL_BMSK                                               0x20
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_HW_CLK_CONTROL_SHFT                                                0x5
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_CURR_PERF_STATE_BMSK                                              0x1e
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_CURR_PERF_STATE_SHFT                                               0x1
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_DFS_EN_BMSK                                                        0x1
#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_DFS_EN_SHFT                                                        0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00004024)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00004028)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0000402c)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00004030)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00004034)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00004038)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0000403c)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00004040)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00004044)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00004048)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0000404c)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00004050)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00004054)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00004058)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0000405c)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00004060)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00004008)
#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_RMSK                                                      0x80000013
#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ADDR)
#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ADDR, m)
#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ADDR,v)
#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_IN)
#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0000400c)
#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_RMSK                                                        0x11071f
#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_ADDR)
#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_ADDR, m)
#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_ADDR,v)
#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_IN)
#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_RCGLITE_DISABLE_BMSK                                         0x10000
#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_RCGLITE_DISABLE_SHFT                                            0x10
#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00004134)
#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_RMSK                                                            0x1
#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00004138)
#define HWIO_GCC_SYS_NOC_AXI_CBCR_RMSK                                                             0x80100005
#define HWIO_GCC_SYS_NOC_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_AXI_CBCR_IN)
#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_SYS_NOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_SYS_NOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_SYS_NOC_AXI_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0000413c)
#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_RMSK                                                       0x80100005
#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_IN)
#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                     0x100000
#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                         0x14
#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00004140)
#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_RMSK                                                       0x80100005
#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_IN)
#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                     0x100000
#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                         0x14
#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00004144)
#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_RMSK                                                        0x80100005
#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_IN)
#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                      0x100000
#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                          0x14
#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00004148)
#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_RMSK                                                    0x80100005
#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_IN)
#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                  0x100000
#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                      0x14
#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00048198)
#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_RMSK                                                       0x80000004
#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_IN)
#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_CLK_ARES_SHFT                                                     0x2

#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0000414c)
#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_RMSK                                                         0x80100005
#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IN)
#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                       0x100000
#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                           0x14
#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ARES_SHFT                                                       0x2
#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_CLK_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_SYS_NOC_AT_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00004150)
#define HWIO_GCC_SYS_NOC_AT_CBCR_RMSK                                                              0x80100005
#define HWIO_GCC_SYS_NOC_AT_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_AT_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_AT_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_AT_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_AT_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_AT_CBCR_IN)
#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_SYS_NOC_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                            0x100000
#define HWIO_GCC_SYS_NOC_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                0x14
#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_SYS_NOC_AT_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00004170)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00004174)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00004178)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000417c)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00004180)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00004184)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00004188)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000418c)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00004190)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00004194)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00004198)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000419c)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000041a0)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000041a4)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000041a8)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000041ac)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00004154)
#define HWIO_GCC_SYS_NOC_CMD_RCGR_RMSK                                                             0x80000013
#define HWIO_GCC_SYS_NOC_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR)
#define HWIO_GCC_SYS_NOC_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR, m)
#define HWIO_GCC_SYS_NOC_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR,v)
#define HWIO_GCC_SYS_NOC_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_CMD_RCGR_IN)
#define HWIO_GCC_SYS_NOC_CMD_RCGR_ROOT_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_SYS_NOC_CMD_RCGR_ROOT_OFF_SHFT                                                          0x1f
#define HWIO_GCC_SYS_NOC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                    0x10
#define HWIO_GCC_SYS_NOC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                     0x4
#define HWIO_GCC_SYS_NOC_CMD_RCGR_ROOT_EN_BMSK                                                            0x2
#define HWIO_GCC_SYS_NOC_CMD_RCGR_ROOT_EN_SHFT                                                            0x1
#define HWIO_GCC_SYS_NOC_CMD_RCGR_UPDATE_BMSK                                                             0x1
#define HWIO_GCC_SYS_NOC_CMD_RCGR_UPDATE_SHFT                                                             0x0

#define HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00004158)
#define HWIO_GCC_SYS_NOC_CFG_RCGR_RMSK                                                               0x11071f
#define HWIO_GCC_SYS_NOC_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR)
#define HWIO_GCC_SYS_NOC_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR, m)
#define HWIO_GCC_SYS_NOC_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR,v)
#define HWIO_GCC_SYS_NOC_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_CFG_RCGR_IN)
#define HWIO_GCC_SYS_NOC_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                0x100000
#define HWIO_GCC_SYS_NOC_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                    0x14
#define HWIO_GCC_SYS_NOC_CFG_RCGR_RCGLITE_DISABLE_BMSK                                                0x10000
#define HWIO_GCC_SYS_NOC_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                   0x10
#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_BMSK                                                          0x700
#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_SEL_SHFT                                                            0x8
#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_BMSK                                                           0x1f
#define HWIO_GCC_SYS_NOC_CFG_RCGR_SRC_DIV_SHFT                                                            0x0

#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00004280)
#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_RMSK                                                               0x1
#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00004284)
#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_RMSK                                                           0x80100005
#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_MONAQ_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_MONAQ_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_MONAQ_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_MONAQ_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_MONAQ_CBCR_IN)
#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00004288)
#define HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_RMSK                                                          0x1
#define HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                               0x1
#define HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                               0x0

#define HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0000428c)
#define HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_RMSK                                                         0x1
#define HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                              0x1
#define HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                              0x0

#define HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00004290)
#define HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_RMSK                                                         0x1
#define HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                              0x1
#define HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                              0x0

#define HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00004294)
#define HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_RMSK                                                         0x1
#define HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                              0x1
#define HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                              0x0

#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00004298)
#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_RMSK                                                      0x80000005
#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_IN          \
        in_dword(HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_ADDR)
#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_ADDR, m)
#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_ADDR,v)
#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_ADDR,m,v,HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_IN)
#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_SHFT                                                  0x0

#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000429c)
#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_RMSK                                                          0x80100005
#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_SF_AXI_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_SF_AXI_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_SF_AXI_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_SF_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_SF_AXI_CBCR_IN)
#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_CLK_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000042a0)
#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_RMSK                                                     0x80100005
#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_IN)
#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                   0x100000
#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                       0x14
#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000042a4)
#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_RMSK                                                    0x80100005
#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_IN)
#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                  0x100000
#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                      0x14
#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x000042a8)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_RMSK                                                       0x80100005
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_IN)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                     0x100000
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                         0x14
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000042ac)
#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_RMSK                                                    0x80100005
#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_IN)
#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                  0x100000
#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                      0x14
#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00047018)
#define HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_RMSK                                                    0x80100005
#define HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_IN)
#define HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                  0x100000
#define HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                      0x14
#define HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_SYS_NOC_LPASS_SF_AXI_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x000042cc)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x000042d0)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x000042d4)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x000042d8)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x000042dc)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x000042e0)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x000042e4)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x000042e8)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x000042ec)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x000042f0)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000042f4)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000042f8)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000042fc)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00004300)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00004304)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00004308)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000042b0)
#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_RMSK                                                      0x80000013
#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ADDR)
#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ADDR, m)
#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ADDR,v)
#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_IN)
#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000042b4)
#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_RMSK                                                        0x11071f
#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_ADDR)
#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_ADDR, m)
#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_ADDR,v)
#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_IN)
#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_RCGLITE_DISABLE_BMSK                                         0x10000
#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_RCGLITE_DISABLE_SHFT                                            0x10
#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000043dc)
#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_RMSK                                                            0x1
#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x000043e0)
#define HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_RMSK                                                      0x1
#define HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                           0x1
#define HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                           0x0

#define HWIO_GCC_SYS_NOC_LPASS_SF_DCD_CDIV_DCDR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x000043e4)
#define HWIO_GCC_SYS_NOC_LPASS_SF_DCD_CDIV_DCDR_RMSK                                                      0x1
#define HWIO_GCC_SYS_NOC_LPASS_SF_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_LPASS_SF_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_SYS_NOC_LPASS_SF_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_LPASS_SF_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_SYS_NOC_LPASS_SF_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_LPASS_SF_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_SYS_NOC_LPASS_SF_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_LPASS_SF_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_LPASS_SF_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_SYS_NOC_LPASS_SF_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                           0x1
#define HWIO_GCC_SYS_NOC_LPASS_SF_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00004404)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00004408)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0000440c)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00004410)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00004414)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00004418)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0000441c)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00004420)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00004424)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00004428)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0000442c)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00004430)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00004434)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00004438)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0000443c)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00004440)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000043e8)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_RMSK                                                   0x80000013
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_ADDR)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_ADDR, m)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_ADDR,v)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_IN)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_ROOT_OFF_BMSK                                          0x80000000
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_ROOT_OFF_SHFT                                                0x1f
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                          0x10
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                           0x4
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_ROOT_EN_BMSK                                                  0x2
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_ROOT_EN_SHFT                                                  0x1
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_UPDATE_BMSK                                                   0x1
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_UPDATE_SHFT                                                   0x0

#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000043ec)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_RMSK                                                     0x11071f
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_ADDR)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_ADDR, m)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_ADDR,v)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_ADDR,m,v,HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_IN)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_HW_CLK_CONTROL_BMSK                                      0x100000
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_HW_CLK_CONTROL_SHFT                                          0x14
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_RCGLITE_DISABLE_BMSK                                      0x10000
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_RCGLITE_DISABLE_SHFT                                         0x10
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00004514)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_RMSK                                                     0x1
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                          0x1
#define HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                          0x0

#define HWIO_GCC_CONFIG_NOC_BCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00005000)
#define HWIO_GCC_CONFIG_NOC_BCR_RMSK                                                                      0x1
#define HWIO_GCC_CONFIG_NOC_BCR_IN          \
        in_dword(HWIO_GCC_CONFIG_NOC_BCR_ADDR)
#define HWIO_GCC_CONFIG_NOC_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CONFIG_NOC_BCR_ADDR, m)
#define HWIO_GCC_CONFIG_NOC_BCR_OUT(v)      \
        out_dword(HWIO_GCC_CONFIG_NOC_BCR_ADDR,v)
#define HWIO_GCC_CONFIG_NOC_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_BCR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_BCR_IN)
#define HWIO_GCC_CONFIG_NOC_BCR_BLK_ARES_BMSK                                                             0x1
#define HWIO_GCC_CONFIG_NOC_BCR_BLK_ARES_SHFT                                                             0x0

#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00005004)
#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_RMSK                                                       0x80100005
#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_IN          \
        in_dword(HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_ADDR)
#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_ADDR, m)
#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_ADDR,v)
#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_ADDR,m,v,HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_IN)
#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                     0x100000
#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                         0x14
#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00005008)
#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_RMSK                                                       0x80100005
#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_IN          \
        in_dword(HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_ADDR)
#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_ADDR, m)
#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_ADDR,v)
#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_ADDR,m,v,HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_IN)
#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                     0x100000
#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                         0x14
#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_CFG_NOC_AHB_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000500c)
#define HWIO_GCC_CFG_NOC_AHB_CBCR_RMSK                                                             0x80100005
#define HWIO_GCC_CFG_NOC_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_CFG_NOC_AHB_CBCR_ADDR)
#define HWIO_GCC_CFG_NOC_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CFG_NOC_AHB_CBCR_ADDR, m)
#define HWIO_GCC_CFG_NOC_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CFG_NOC_AHB_CBCR_ADDR,v)
#define HWIO_GCC_CFG_NOC_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CFG_NOC_AHB_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_AHB_CBCR_IN)
#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_CFG_NOC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_CFG_NOC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_CFG_NOC_AHB_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00005010)
#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_RMSK                                                        0x80100005
#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_ADDR)
#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_ADDR, m)
#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_ADDR,v)
#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_IN)
#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                      0x100000
#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                          0x14
#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00005014)
#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_RMSK                                                       0x80100005
#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_ADDR)
#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_ADDR, m)
#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_ADDR,v)
#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_IN)
#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                     0x100000
#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                         0x14
#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00005018)
#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_RMSK                                                       0x80100005
#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_ADDR)
#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_ADDR, m)
#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_ADDR,v)
#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_IN)
#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                     0x100000
#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                         0x14
#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0000501c)
#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_RMSK                                                       0x80100005
#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_ADDR)
#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_ADDR, m)
#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_ADDR,v)
#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_IN)
#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                     0x100000
#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                         0x14
#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00005020)
#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_RMSK                                                       0x80100005
#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_ADDR)
#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_ADDR, m)
#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_ADDR,v)
#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_IN)
#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                     0x100000
#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                         0x14
#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00005024)
#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_RMSK                                                     0x80100005
#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_ADDR)
#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_ADDR, m)
#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_ADDR,v)
#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_IN)
#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                   0x100000
#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                       0x14
#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f07c)
#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_RMSK                                                   0x80000005
#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_ADDR)
#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_ADDR, m)
#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_ADDR,v)
#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_IN)
#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_CLK_ENABLE_SHFT                                               0x0

#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001007c)
#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_RMSK                                                    0x80000005
#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_ADDR)
#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_ADDR, m)
#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_ADDR,v)
#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_IN)
#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00005028)
#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_RMSK                                                         0x80000005
#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_IN          \
        in_dword(HWIO_GCC_NOC_WEST_DCD_XO_CBCR_ADDR)
#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NOC_WEST_DCD_XO_CBCR_ADDR, m)
#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NOC_WEST_DCD_XO_CBCR_ADDR,v)
#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NOC_WEST_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_WEST_DCD_XO_CBCR_IN)
#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_ARES_SHFT                                                       0x2
#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_CLK_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0000502c)
#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_RMSK                                                        0x80000005
#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_IN          \
        in_dword(HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_ADDR)
#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_ADDR, m)
#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_ADDR,v)
#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_IN)
#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00005030)
#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_RMSK                                                        0x80000005
#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_IN          \
        in_dword(HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_ADDR)
#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_ADDR, m)
#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_ADDR,v)
#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_IN)
#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00005034)
#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_RMSK                                                       0x80000005
#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_IN          \
        in_dword(HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_ADDR)
#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_ADDR, m)
#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_ADDR,v)
#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_IN)
#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00005038)
#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_RMSK                                                        0x80000005
#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_IN          \
        in_dword(HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_ADDR)
#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_ADDR, m)
#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_ADDR,v)
#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_IN)
#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0000503c)
#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_RMSK                                                       0x80000005
#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_IN          \
        in_dword(HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_ADDR)
#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_ADDR, m)
#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_ADDR,v)
#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_IN)
#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00005040)
#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_RMSK                                                        0x80000005
#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_IN          \
        in_dword(HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_ADDR)
#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_ADDR, m)
#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_ADDR,v)
#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_IN)
#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00005044)
#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_RMSK                                                      0x80000005
#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_IN          \
        in_dword(HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_ADDR)
#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_ADDR, m)
#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_ADDR,v)
#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_IN)
#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_CLK_ENABLE_SHFT                                                  0x0

#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00005048)
#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_RMSK                                                   0x80000005
#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_IN          \
        in_dword(HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_ADDR)
#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_ADDR, m)
#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_ADDR,v)
#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_IN)
#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_CLK_ENABLE_SHFT                                               0x0

#define HWIO_GCC_CNOC_PERIPH_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000504c)
#define HWIO_GCC_CNOC_PERIPH_CBCR_RMSK                                                             0x80100005
#define HWIO_GCC_CNOC_PERIPH_CBCR_IN          \
        in_dword(HWIO_GCC_CNOC_PERIPH_CBCR_ADDR)
#define HWIO_GCC_CNOC_PERIPH_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CNOC_PERIPH_CBCR_ADDR, m)
#define HWIO_GCC_CNOC_PERIPH_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CNOC_PERIPH_CBCR_ADDR,v)
#define HWIO_GCC_CNOC_PERIPH_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CNOC_PERIPH_CBCR_ADDR,m,v,HWIO_GCC_CNOC_PERIPH_CBCR_IN)
#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_CNOC_PERIPH_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_CNOC_PERIPH_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_CNOC_PERIPH_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_CFG_NOC_LPASS_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0004701c)
#define HWIO_GCC_CFG_NOC_LPASS_CBCR_RMSK                                                           0x80100005
#define HWIO_GCC_CFG_NOC_LPASS_CBCR_IN          \
        in_dword(HWIO_GCC_CFG_NOC_LPASS_CBCR_ADDR)
#define HWIO_GCC_CFG_NOC_LPASS_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CFG_NOC_LPASS_CBCR_ADDR, m)
#define HWIO_GCC_CFG_NOC_LPASS_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CFG_NOC_LPASS_CBCR_ADDR,v)
#define HWIO_GCC_CFG_NOC_LPASS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CFG_NOC_LPASS_CBCR_ADDR,m,v,HWIO_GCC_CFG_NOC_LPASS_CBCR_IN)
#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_CFG_NOC_LPASS_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_CFG_NOC_LPASS_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_CFG_NOC_LPASS_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00005064)
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_RMSK                                                              0x3ffff
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CMD_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_RCG_SW_CTRL_BMSK                                                  0x38000
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_RCG_SW_CTRL_SHFT                                                      0xf
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_SW_PERF_STATE_BMSK                                                 0x7800
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_SW_PERF_STATE_SHFT                                                    0xb
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_SW_OVERRIDE_BMSK                                                    0x400
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_SW_OVERRIDE_SHFT                                                      0xa
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                       0x200
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                         0x9
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_DFS_FSM_STATE_BMSK                                                  0x1c0
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_DFS_FSM_STATE_SHFT                                                    0x6
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_HW_CLK_CONTROL_BMSK                                                  0x20
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_HW_CLK_CONTROL_SHFT                                                   0x5
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_CURR_PERF_STATE_BMSK                                                 0x1e
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_CURR_PERF_STATE_SHFT                                                  0x1
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_DFS_EN_BMSK                                                           0x1
#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_DFS_EN_SHFT                                                           0x0

#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000506c)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00005070)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00005074)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00005078)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000507c)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00005080)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00005084)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00005088)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000508c)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00005090)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00005094)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00005098)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000509c)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000050a0)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000050a4)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000050a8)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00005050)
#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_RMSK                                                          0x80000013
#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_CONFIG_NOC_CMD_RCGR_ADDR)
#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_CONFIG_NOC_CMD_RCGR_ADDR, m)
#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_CONFIG_NOC_CMD_RCGR_ADDR,v)
#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_CMD_RCGR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_CMD_RCGR_IN)
#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_ROOT_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_ROOT_OFF_SHFT                                                       0x1f
#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                 0x10
#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                  0x4
#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_ROOT_EN_BMSK                                                         0x2
#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_ROOT_EN_SHFT                                                         0x1
#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_UPDATE_BMSK                                                          0x1
#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_UPDATE_SHFT                                                          0x0

#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00005054)
#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_RMSK                                                            0x11071f
#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_CONFIG_NOC_CFG_RCGR_ADDR)
#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_CONFIG_NOC_CFG_RCGR_ADDR, m)
#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_CONFIG_NOC_CFG_RCGR_ADDR,v)
#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_CFG_RCGR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_CFG_RCGR_IN)
#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_HW_CLK_CONTROL_BMSK                                             0x100000
#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                 0x14
#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_RCGLITE_DISABLE_BMSK                                             0x10000
#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                0x10
#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_SEL_BMSK                                                       0x700
#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_SEL_SHFT                                                         0x8
#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_BMSK                                                        0x1f
#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_SRC_DIV_SHFT                                                         0x0

#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00005198)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000519c)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000051a0)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000051a4)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000051a8)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000051ac)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000051b0)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000051b4)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000051b8)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000051bc)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000051c0)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000051c4)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000051c8)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000051cc)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000051d0)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000051d4)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0000517c)
#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_RMSK                                                         0x80000013
#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ADDR)
#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ADDR, m)
#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ADDR,v)
#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ADDR,m,v,HWIO_GCC_CNOC_PERIPH_CMD_RCGR_IN)
#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ROOT_OFF_BMSK                                                0x80000000
#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ROOT_OFF_SHFT                                                      0x1f
#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                0x10
#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                 0x4
#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ROOT_EN_BMSK                                                        0x2
#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ROOT_EN_SHFT                                                        0x1
#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_UPDATE_BMSK                                                         0x1
#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_UPDATE_SHFT                                                         0x0

#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00005180)
#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_RMSK                                                           0x11071f
#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_CNOC_PERIPH_CFG_RCGR_ADDR)
#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_CNOC_PERIPH_CFG_RCGR_ADDR, m)
#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_CNOC_PERIPH_CFG_RCGR_ADDR,v)
#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CNOC_PERIPH_CFG_RCGR_ADDR,m,v,HWIO_GCC_CNOC_PERIPH_CFG_RCGR_IN)
#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_HW_CLK_CONTROL_BMSK                                            0x100000
#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                0x14
#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_RCGLITE_DISABLE_BMSK                                            0x10000
#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_RCGLITE_DISABLE_SHFT                                               0x10
#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_SEL_BMSK                                                      0x700
#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_SEL_SHFT                                                        0x8
#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_BMSK                                                       0x1f
#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_SRC_DIV_SHFT                                                        0x0

#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x000052a8)
#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_RMSK                                                     0x1
#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                          0x1
#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                          0x0

#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x000052ac)
#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_RMSK                                                       0x1
#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                            0x1
#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                            0x0

#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x000052b0)
#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_RMSK                                                      0x1
#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                           0x1
#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                           0x0

#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x000052b4)
#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_RMSK                                                      0x1
#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                           0x1
#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                           0x0

#define HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x000052b8)
#define HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_RMSK                                                      0x1
#define HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                           0x1
#define HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                           0x0

#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x000052bc)
#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_RMSK                                                      0x1
#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                           0x1
#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                           0x0

#define HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000052c0)
#define HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_RMSK                                                    0x1
#define HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                         0x1
#define HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                         0x0

#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000052e0)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF0_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000052e4)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF1_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000052e8)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF2_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000052ec)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF3_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000052f0)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF4_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000052f4)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF5_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000052f8)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF6_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000052fc)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF7_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00005300)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF8_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00005304)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF9_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00005308)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF10_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000530c)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF11_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00005310)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF12_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00005314)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF13_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00005318)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF14_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000531c)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_CNOC_CFG_NOC_LPASS_PERF15_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x000052c4)
#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_RMSK                                                       0x80000013
#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ADDR)
#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ADDR, m)
#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ADDR,v)
#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ADDR,m,v,HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_IN)
#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ROOT_OFF_BMSK                                              0x80000000
#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ROOT_OFF_SHFT                                                    0x1f
#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                              0x10
#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                               0x4
#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ROOT_EN_BMSK                                                      0x2
#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_ROOT_EN_SHFT                                                      0x1
#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_UPDATE_BMSK                                                       0x1
#define HWIO_GCC_CFG_NOC_LPASS_CMD_RCGR_UPDATE_SHFT                                                       0x0

#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x000052c8)
#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_RMSK                                                         0x11071f
#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_ADDR)
#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_ADDR, m)
#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_ADDR,v)
#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_ADDR,m,v,HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_IN)
#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_HW_CLK_CONTROL_BMSK                                          0x100000
#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_HW_CLK_CONTROL_SHFT                                              0x14
#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_RCGLITE_DISABLE_BMSK                                          0x10000
#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_RCGLITE_DISABLE_SHFT                                             0x10
#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_SEL_BMSK                                                    0x700
#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_SEL_SHFT                                                      0x8
#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_BMSK                                                     0x1f
#define HWIO_GCC_CFG_NOC_LPASS_CFG_RCGR_SRC_DIV_SHFT                                                      0x0

#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000053f0)
#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_RMSK                                                         0x1
#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                              0x1
#define HWIO_GCC_CFG_NOC_LPASS_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                              0x0

#define HWIO_GCC_TIC_CFG_AHB_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000e000)
#define HWIO_GCC_TIC_CFG_AHB_CBCR_RMSK                                                             0x80107ff5
#define HWIO_GCC_TIC_CFG_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_TIC_CFG_AHB_CBCR_ADDR)
#define HWIO_GCC_TIC_CFG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TIC_CFG_AHB_CBCR_ADDR, m)
#define HWIO_GCC_TIC_CFG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_TIC_CFG_AHB_CBCR_ADDR,v)
#define HWIO_GCC_TIC_CFG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TIC_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_TIC_CFG_AHB_CBCR_IN)
#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_TIC_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_TIC_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_CORE_ON_BMSK                                               0x4000
#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_CORE_ON_SHFT                                                  0xe
#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                             0x2000
#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                0xd
#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                            0x1000
#define HWIO_GCC_TIC_CFG_AHB_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                               0xc
#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_BMSK                                                           0xf00
#define HWIO_GCC_TIC_CFG_AHB_CBCR_WAKEUP_SHFT                                                             0x8
#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_BMSK                                                             0xf0
#define HWIO_GCC_TIC_CFG_AHB_CBCR_SLEEP_SHFT                                                              0x4
#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_TIC_CFG_AHB_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_IMEM_BCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00008000)
#define HWIO_GCC_IMEM_BCR_RMSK                                                                            0x1
#define HWIO_GCC_IMEM_BCR_IN          \
        in_dword(HWIO_GCC_IMEM_BCR_ADDR)
#define HWIO_GCC_IMEM_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_IMEM_BCR_ADDR, m)
#define HWIO_GCC_IMEM_BCR_OUT(v)      \
        out_dword(HWIO_GCC_IMEM_BCR_ADDR,v)
#define HWIO_GCC_IMEM_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IMEM_BCR_ADDR,m,v,HWIO_GCC_IMEM_BCR_IN)
#define HWIO_GCC_IMEM_BCR_BLK_ARES_BMSK                                                                   0x1
#define HWIO_GCC_IMEM_BCR_BLK_ARES_SHFT                                                                   0x0

#define HWIO_GCC_IMEM_AXI_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00008004)
#define HWIO_GCC_IMEM_AXI_CBCR_RMSK                                                                0x80107ff4
#define HWIO_GCC_IMEM_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_IMEM_AXI_CBCR_ADDR)
#define HWIO_GCC_IMEM_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_IMEM_AXI_CBCR_ADDR, m)
#define HWIO_GCC_IMEM_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_IMEM_AXI_CBCR_ADDR,v)
#define HWIO_GCC_IMEM_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IMEM_AXI_CBCR_ADDR,m,v,HWIO_GCC_IMEM_AXI_CBCR_IN)
#define HWIO_GCC_IMEM_AXI_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_IMEM_AXI_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_IMEM_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_IMEM_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK                                                  0x4000
#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT                                                     0xe
#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                                0x2000
#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                   0xd
#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                               0x1000
#define HWIO_GCC_IMEM_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                                  0xc
#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_BMSK                                                              0xf00
#define HWIO_GCC_IMEM_AXI_CBCR_WAKEUP_SHFT                                                                0x8
#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_BMSK                                                                0xf0
#define HWIO_GCC_IMEM_AXI_CBCR_SLEEP_SHFT                                                                 0x4
#define HWIO_GCC_IMEM_AXI_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_IMEM_AXI_CBCR_CLK_ARES_SHFT                                                              0x2

#define HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00008008)
#define HWIO_GCC_IMEM_CFG_AHB_CBCR_RMSK                                                            0x80100005
#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR)
#define HWIO_GCC_IMEM_CFG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR, m)
#define HWIO_GCC_IMEM_CFG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR,v)
#define HWIO_GCC_IMEM_CFG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_IMEM_CFG_AHB_CBCR_IN)
#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                          0x100000
#define HWIO_GCC_IMEM_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                              0x14
#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_IMEM_CFG_AHB_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_MMU_BCR_ADDR                                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00083000)
#define HWIO_GCC_MMU_BCR_RMSK                                                                             0x1
#define HWIO_GCC_MMU_BCR_IN          \
        in_dword(HWIO_GCC_MMU_BCR_ADDR)
#define HWIO_GCC_MMU_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMU_BCR_ADDR, m)
#define HWIO_GCC_MMU_BCR_OUT(v)      \
        out_dword(HWIO_GCC_MMU_BCR_ADDR,v)
#define HWIO_GCC_MMU_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMU_BCR_ADDR,m,v,HWIO_GCC_MMU_BCR_IN)
#define HWIO_GCC_MMU_BCR_BLK_ARES_BMSK                                                                    0x1
#define HWIO_GCC_MMU_BCR_BLK_ARES_SHFT                                                                    0x0

#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00083004)
#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_RMSK                                                          0x80100007
#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_IN          \
        in_dword(HWIO_GCC_SYS_NOC_SF_TCU_CBCR_ADDR)
#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SYS_NOC_SF_TCU_CBCR_ADDR, m)
#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SYS_NOC_SF_TCU_CBCR_ADDR,v)
#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SYS_NOC_SF_TCU_CBCR_ADDR,m,v,HWIO_GCC_SYS_NOC_SF_TCU_CBCR_IN)
#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_HW_CTL_BMSK                                                          0x2
#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_HW_CTL_SHFT                                                          0x1
#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_CLK_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_CLK_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_MMU_TCU_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00083008)
#define HWIO_GCC_MMU_TCU_CBCR_RMSK                                                                 0x80107ff5
#define HWIO_GCC_MMU_TCU_CBCR_IN          \
        in_dword(HWIO_GCC_MMU_TCU_CBCR_ADDR)
#define HWIO_GCC_MMU_TCU_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMU_TCU_CBCR_ADDR, m)
#define HWIO_GCC_MMU_TCU_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MMU_TCU_CBCR_ADDR,v)
#define HWIO_GCC_MMU_TCU_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMU_TCU_CBCR_ADDR,m,v,HWIO_GCC_MMU_TCU_CBCR_IN)
#define HWIO_GCC_MMU_TCU_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_MMU_TCU_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_MMU_TCU_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                               0x100000
#define HWIO_GCC_MMU_TCU_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                   0x14
#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_CORE_ON_BMSK                                                   0x4000
#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_CORE_ON_SHFT                                                      0xe
#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                                 0x2000
#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                    0xd
#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                                0x1000
#define HWIO_GCC_MMU_TCU_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                                   0xc
#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_BMSK                                                               0xf00
#define HWIO_GCC_MMU_TCU_CBCR_WAKEUP_SHFT                                                                 0x8
#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_BMSK                                                                 0xf0
#define HWIO_GCC_MMU_TCU_CBCR_SLEEP_SHFT                                                                  0x4
#define HWIO_GCC_MMU_TCU_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_MMU_TCU_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_MMU_TCU_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_MMU_TCU_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_MMU_TCU_SREGR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0008300c)
#define HWIO_GCC_MMU_TCU_SREGR_RMSK                                                                0xfffff37e
#define HWIO_GCC_MMU_TCU_SREGR_IN          \
        in_dword(HWIO_GCC_MMU_TCU_SREGR_ADDR)
#define HWIO_GCC_MMU_TCU_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMU_TCU_SREGR_ADDR, m)
#define HWIO_GCC_MMU_TCU_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_MMU_TCU_SREGR_ADDR,v)
#define HWIO_GCC_MMU_TCU_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMU_TCU_SREGR_ADDR,m,v,HWIO_GCC_MMU_TCU_SREGR_IN)
#define HWIO_GCC_MMU_TCU_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                                      0xff000000
#define HWIO_GCC_MMU_TCU_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                            0x18
#define HWIO_GCC_MMU_TCU_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                         0xff0000
#define HWIO_GCC_MMU_TCU_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                             0x10
#define HWIO_GCC_MMU_TCU_SREGR_RESERVE_BITS15_13_BMSK                                                  0xe000
#define HWIO_GCC_MMU_TCU_SREGR_RESERVE_BITS15_13_SHFT                                                     0xd
#define HWIO_GCC_MMU_TCU_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                        0x1000
#define HWIO_GCC_MMU_TCU_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                           0xc
#define HWIO_GCC_MMU_TCU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                            0x300
#define HWIO_GCC_MMU_TCU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                              0x8
#define HWIO_GCC_MMU_TCU_SREGR_FORCE_CLK_ON_BMSK                                                         0x40
#define HWIO_GCC_MMU_TCU_SREGR_FORCE_CLK_ON_SHFT                                                          0x6
#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SEL_SLP_STG_BMSK                                                   0x20
#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SEL_SLP_STG_SHFT                                                    0x5
#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SLP_STG_BMSK                                                       0x10
#define HWIO_GCC_MMU_TCU_SREGR_SW_RST_SLP_STG_SHFT                                                        0x4
#define HWIO_GCC_MMU_TCU_SREGR_SW_CTRL_PWR_DOWN_BMSK                                                      0x8
#define HWIO_GCC_MMU_TCU_SREGR_SW_CTRL_PWR_DOWN_SHFT                                                      0x3
#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                                 0x4
#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                                 0x2
#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SLP_STG_BMSK                                                     0x2
#define HWIO_GCC_MMU_TCU_SREGR_SW_CLK_EN_SLP_STG_SHFT                                                     0x1

#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00083024)
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_RMSK                                                             0xffffff
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CMD_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_RCG_SW_CTRL_BMSK                                                 0xff8000
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_RCG_SW_CTRL_SHFT                                                      0xf
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_SW_PERF_STATE_BMSK                                                 0x7800
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_SW_PERF_STATE_SHFT                                                    0xb
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_SW_OVERRIDE_BMSK                                                    0x400
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_SW_OVERRIDE_SHFT                                                      0xa
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                       0x200
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                         0x9
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_DFS_FSM_STATE_BMSK                                                  0x1c0
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_DFS_FSM_STATE_SHFT                                                    0x6
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_HW_CLK_CONTROL_BMSK                                                  0x20
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_HW_CLK_CONTROL_SHFT                                                   0x5
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_CURR_PERF_STATE_BMSK                                                 0x1e
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_CURR_PERF_STATE_SHFT                                                  0x1
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_DFS_EN_BMSK                                                           0x1
#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_DFS_EN_SHFT                                                           0x0

#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0008302c)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_RMSK                                                      0x71f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00083030)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_RMSK                                                      0x71f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00083034)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_RMSK                                                      0x71f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00083038)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_RMSK                                                      0x71f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0008303c)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_RMSK                                                      0x71f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00083040)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_RMSK                                                      0x71f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00083044)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_RMSK                                                      0x71f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00083048)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_RMSK                                                      0x71f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0008304c)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_RMSK                                                      0x71f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00083050)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_RMSK                                                      0x71f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00083054)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_RMSK                                                     0x71f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_BMSK                                             0x700
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_SEL_SHFT                                               0x8
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_BMSK                                              0x1f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_SRC_DIV_SHFT                                               0x0

#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00083058)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_RMSK                                                     0x71f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_BMSK                                             0x700
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_SEL_SHFT                                               0x8
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_BMSK                                              0x1f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_SRC_DIV_SHFT                                               0x0

#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0008305c)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_RMSK                                                     0x71f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_BMSK                                             0x700
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_SEL_SHFT                                               0x8
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_BMSK                                              0x1f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_SRC_DIV_SHFT                                               0x0

#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00083060)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_RMSK                                                     0x71f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_BMSK                                             0x700
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_SEL_SHFT                                               0x8
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_BMSK                                              0x1f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_SRC_DIV_SHFT                                               0x0

#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00083064)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_RMSK                                                     0x71f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_BMSK                                             0x700
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_SEL_SHFT                                               0x8
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_BMSK                                              0x1f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_SRC_DIV_SHFT                                               0x0

#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00083068)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_RMSK                                                     0x71f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_BMSK                                             0x700
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_SEL_SHFT                                               0x8
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_BMSK                                              0x1f
#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_SRC_DIV_SHFT                                               0x0

#define HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00083010)
#define HWIO_GCC_MMU_TCU_CMD_RCGR_RMSK                                                             0x80000013
#define HWIO_GCC_MMU_TCU_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR)
#define HWIO_GCC_MMU_TCU_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR, m)
#define HWIO_GCC_MMU_TCU_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR,v)
#define HWIO_GCC_MMU_TCU_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR,m,v,HWIO_GCC_MMU_TCU_CMD_RCGR_IN)
#define HWIO_GCC_MMU_TCU_CMD_RCGR_ROOT_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_MMU_TCU_CMD_RCGR_ROOT_OFF_SHFT                                                          0x1f
#define HWIO_GCC_MMU_TCU_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                    0x10
#define HWIO_GCC_MMU_TCU_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                     0x4
#define HWIO_GCC_MMU_TCU_CMD_RCGR_ROOT_EN_BMSK                                                            0x2
#define HWIO_GCC_MMU_TCU_CMD_RCGR_ROOT_EN_SHFT                                                            0x1
#define HWIO_GCC_MMU_TCU_CMD_RCGR_UPDATE_BMSK                                                             0x1
#define HWIO_GCC_MMU_TCU_CMD_RCGR_UPDATE_SHFT                                                             0x0

#define HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00083014)
#define HWIO_GCC_MMU_TCU_CFG_RCGR_RMSK                                                               0x11071f
#define HWIO_GCC_MMU_TCU_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR)
#define HWIO_GCC_MMU_TCU_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR, m)
#define HWIO_GCC_MMU_TCU_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR,v)
#define HWIO_GCC_MMU_TCU_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR,m,v,HWIO_GCC_MMU_TCU_CFG_RCGR_IN)
#define HWIO_GCC_MMU_TCU_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                0x100000
#define HWIO_GCC_MMU_TCU_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                    0x14
#define HWIO_GCC_MMU_TCU_CFG_RCGR_RCGLITE_DISABLE_BMSK                                                0x10000
#define HWIO_GCC_MMU_TCU_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                   0x10
#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_BMSK                                                          0x700
#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_SEL_SHFT                                                            0x8
#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_BMSK                                                           0x1f
#define HWIO_GCC_MMU_TCU_CFG_RCGR_SRC_DIV_SHFT                                                            0x0

#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0008313c)
#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_RMSK                                                               0x1
#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_ANOC_TBU_BCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00090000)
#define HWIO_GCC_ANOC_TBU_BCR_RMSK                                                                        0x1
#define HWIO_GCC_ANOC_TBU_BCR_IN          \
        in_dword(HWIO_GCC_ANOC_TBU_BCR_ADDR)
#define HWIO_GCC_ANOC_TBU_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_ANOC_TBU_BCR_ADDR, m)
#define HWIO_GCC_ANOC_TBU_BCR_OUT(v)      \
        out_dword(HWIO_GCC_ANOC_TBU_BCR_ADDR,v)
#define HWIO_GCC_ANOC_TBU_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_ANOC_TBU_BCR_ADDR,m,v,HWIO_GCC_ANOC_TBU_BCR_IN)
#define HWIO_GCC_ANOC_TBU_BCR_BLK_ARES_BMSK                                                               0x1
#define HWIO_GCC_ANOC_TBU_BCR_BLK_ARES_SHFT                                                               0x0

#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00090004)
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_RMSK                                                     0x80107ff5
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                   0x100000
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                       0x14
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_FORCE_MEM_CORE_ON_BMSK                                       0x4000
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_FORCE_MEM_CORE_ON_SHFT                                          0xe
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                     0x2000
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                        0xd
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                    0x1000
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                       0xc
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_WAKEUP_BMSK                                                   0xf00
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_WAKEUP_SHFT                                                     0x8
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_SLEEP_BMSK                                                     0xf0
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_SLEEP_SHFT                                                      0x4
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00090008)
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_RMSK                                                    0xfffff37e
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_ADDR)
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_IN)
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                          0xff000000
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                0x18
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                             0xff0000
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                 0x10
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_RESERVE_BITS15_13_BMSK                                      0xe000
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_RESERVE_BITS15_13_SHFT                                         0xd
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                            0x1000
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                               0xc
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                0x300
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                  0x8
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_FORCE_CLK_ON_BMSK                                             0x40
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_FORCE_CLK_ON_SHFT                                              0x6
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SW_RST_SEL_SLP_STG_BMSK                                       0x20
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SW_RST_SEL_SLP_STG_SHFT                                        0x5
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SW_RST_SLP_STG_BMSK                                           0x10
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SW_RST_SLP_STG_SHFT                                            0x4
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SW_CTRL_PWR_DOWN_BMSK                                          0x8
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SW_CTRL_PWR_DOWN_SHFT                                          0x3
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                     0x4
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                     0x2
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SW_CLK_EN_SLP_STG_BMSK                                         0x2
#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_SW_CLK_EN_SLP_STG_SHFT                                         0x1

#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0009000c)
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_RMSK                                                      0x80107ff5
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                    0x100000
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                        0x14
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_FORCE_MEM_CORE_ON_BMSK                                        0x4000
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_FORCE_MEM_CORE_ON_SHFT                                           0xe
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                      0x2000
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                         0xd
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                     0x1000
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                        0xc
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_WAKEUP_BMSK                                                    0xf00
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_WAKEUP_SHFT                                                      0x8
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_SLEEP_BMSK                                                      0xf0
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_SLEEP_SHFT                                                       0x4
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_CLK_ENABLE_SHFT                                                  0x0

#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00090010)
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_RMSK                                                     0xfffff37e
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_ADDR)
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_IN)
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                           0xff000000
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                 0x18
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                              0xff0000
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                  0x10
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_RESERVE_BITS15_13_BMSK                                       0xe000
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_RESERVE_BITS15_13_SHFT                                          0xd
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                             0x1000
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                0xc
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                 0x300
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                   0x8
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_FORCE_CLK_ON_BMSK                                              0x40
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_FORCE_CLK_ON_SHFT                                               0x6
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SW_RST_SEL_SLP_STG_BMSK                                        0x20
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SW_RST_SEL_SLP_STG_SHFT                                         0x5
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SW_RST_SLP_STG_BMSK                                            0x10
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SW_RST_SLP_STG_SHFT                                             0x4
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SW_CTRL_PWR_DOWN_BMSK                                           0x8
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SW_CTRL_PWR_DOWN_SHFT                                           0x3
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                      0x4
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                      0x2
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SW_CLK_EN_SLP_STG_BMSK                                          0x2
#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_SW_CLK_EN_SLP_STG_SHFT                                          0x1

#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00090014)
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_RMSK                                                          0x80107ff5
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_TBU1_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_TBU1_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_TBU1_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_TBU1_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_TBU1_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_CLK_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00090018)
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_RMSK                                                         0xfffff37e
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_TBU1_SREGR_ADDR)
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_TBU1_SREGR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_TBU1_SREGR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_TBU1_SREGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_TBU1_SREGR_IN)
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                               0xff000000
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                     0x18
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                  0xff0000
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                      0x10
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_RESERVE_BITS15_13_BMSK                                           0xe000
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_RESERVE_BITS15_13_SHFT                                              0xd
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                 0x1000
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                    0xc
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                     0x300
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                       0x8
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_FORCE_CLK_ON_BMSK                                                  0x40
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_FORCE_CLK_ON_SHFT                                                   0x6
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_RST_SEL_SLP_STG_BMSK                                            0x20
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_RST_SEL_SLP_STG_SHFT                                             0x5
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_RST_SLP_STG_BMSK                                                0x10
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_RST_SLP_STG_SHFT                                                 0x4
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CTRL_PWR_DOWN_BMSK                                               0x8
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CTRL_PWR_DOWN_SHFT                                               0x3
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                          0x4
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                          0x2
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CLK_EN_SLP_STG_BMSK                                              0x2
#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_SW_CLK_EN_SLP_STG_SHFT                                              0x1

#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0009001c)
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_RMSK                                                          0x80107ff5
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_TBU2_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_TBU2_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_TBU2_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_TBU2_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_TBU2_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_CLK_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00090020)
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_RMSK                                                         0xfffff37e
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_TBU2_SREGR_ADDR)
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_TBU2_SREGR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_TBU2_SREGR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_TBU2_SREGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_TBU2_SREGR_IN)
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                               0xff000000
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                     0x18
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                  0xff0000
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                      0x10
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_RESERVE_BITS15_13_BMSK                                           0xe000
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_RESERVE_BITS15_13_SHFT                                              0xd
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                 0x1000
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                    0xc
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                     0x300
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                       0x8
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_FORCE_CLK_ON_BMSK                                                  0x40
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_FORCE_CLK_ON_SHFT                                                   0x6
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_RST_SEL_SLP_STG_BMSK                                            0x20
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_RST_SEL_SLP_STG_SHFT                                             0x5
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_RST_SLP_STG_BMSK                                                0x10
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_RST_SLP_STG_SHFT                                                 0x4
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CTRL_PWR_DOWN_BMSK                                               0x8
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CTRL_PWR_DOWN_SHFT                                               0x3
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                          0x4
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                          0x2
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CLK_EN_SLP_STG_BMSK                                              0x2
#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_SW_CLK_EN_SLP_STG_SHFT                                              0x1

#define HWIO_GCC_MMNOC_BCR_ADDR                                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00009000)
#define HWIO_GCC_MMNOC_BCR_RMSK                                                                           0x1
#define HWIO_GCC_MMNOC_BCR_IN          \
        in_dword(HWIO_GCC_MMNOC_BCR_ADDR)
#define HWIO_GCC_MMNOC_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_BCR_ADDR, m)
#define HWIO_GCC_MMNOC_BCR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_BCR_ADDR,v)
#define HWIO_GCC_MMNOC_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_BCR_ADDR,m,v,HWIO_GCC_MMNOC_BCR_IN)
#define HWIO_GCC_MMNOC_BCR_BLK_ARES_BMSK                                                                  0x1
#define HWIO_GCC_MMNOC_BCR_BLK_ARES_SHFT                                                                  0x0

#define HWIO_GCC_MMNOC_GDSCR_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00009004)
#define HWIO_GCC_MMNOC_GDSCR_RMSK                                                                  0xf8ffffff
#define HWIO_GCC_MMNOC_GDSCR_IN          \
        in_dword(HWIO_GCC_MMNOC_GDSCR_ADDR)
#define HWIO_GCC_MMNOC_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_GDSCR_ADDR, m)
#define HWIO_GCC_MMNOC_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_GDSCR_ADDR,v)
#define HWIO_GCC_MMNOC_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_GDSCR_ADDR,m,v,HWIO_GCC_MMNOC_GDSCR_IN)
#define HWIO_GCC_MMNOC_GDSCR_PWR_ON_BMSK                                                           0x80000000
#define HWIO_GCC_MMNOC_GDSCR_PWR_ON_SHFT                                                                 0x1f
#define HWIO_GCC_MMNOC_GDSCR_GDSC_STATE_BMSK                                                       0x78000000
#define HWIO_GCC_MMNOC_GDSCR_GDSC_STATE_SHFT                                                             0x1b
#define HWIO_GCC_MMNOC_GDSCR_EN_REST_WAIT_BMSK                                                       0xf00000
#define HWIO_GCC_MMNOC_GDSCR_EN_REST_WAIT_SHFT                                                           0x14
#define HWIO_GCC_MMNOC_GDSCR_EN_FEW_WAIT_BMSK                                                         0xf0000
#define HWIO_GCC_MMNOC_GDSCR_EN_FEW_WAIT_SHFT                                                            0x10
#define HWIO_GCC_MMNOC_GDSCR_CLK_DIS_WAIT_BMSK                                                         0xf000
#define HWIO_GCC_MMNOC_GDSCR_CLK_DIS_WAIT_SHFT                                                            0xc
#define HWIO_GCC_MMNOC_GDSCR_RETAIN_FF_ENABLE_BMSK                                                      0x800
#define HWIO_GCC_MMNOC_GDSCR_RETAIN_FF_ENABLE_SHFT                                                        0xb
#define HWIO_GCC_MMNOC_GDSCR_RESTORE_BMSK                                                               0x400
#define HWIO_GCC_MMNOC_GDSCR_RESTORE_SHFT                                                                 0xa
#define HWIO_GCC_MMNOC_GDSCR_SAVE_BMSK                                                                  0x200
#define HWIO_GCC_MMNOC_GDSCR_SAVE_SHFT                                                                    0x9
#define HWIO_GCC_MMNOC_GDSCR_RETAIN_BMSK                                                                0x100
#define HWIO_GCC_MMNOC_GDSCR_RETAIN_SHFT                                                                  0x8
#define HWIO_GCC_MMNOC_GDSCR_EN_REST_BMSK                                                                0x80
#define HWIO_GCC_MMNOC_GDSCR_EN_REST_SHFT                                                                 0x7
#define HWIO_GCC_MMNOC_GDSCR_EN_FEW_BMSK                                                                 0x40
#define HWIO_GCC_MMNOC_GDSCR_EN_FEW_SHFT                                                                  0x6
#define HWIO_GCC_MMNOC_GDSCR_CLAMP_IO_BMSK                                                               0x20
#define HWIO_GCC_MMNOC_GDSCR_CLAMP_IO_SHFT                                                                0x5
#define HWIO_GCC_MMNOC_GDSCR_CLK_DISABLE_BMSK                                                            0x10
#define HWIO_GCC_MMNOC_GDSCR_CLK_DISABLE_SHFT                                                             0x4
#define HWIO_GCC_MMNOC_GDSCR_PD_ARES_BMSK                                                                 0x8
#define HWIO_GCC_MMNOC_GDSCR_PD_ARES_SHFT                                                                 0x3
#define HWIO_GCC_MMNOC_GDSCR_SW_OVERRIDE_BMSK                                                             0x4
#define HWIO_GCC_MMNOC_GDSCR_SW_OVERRIDE_SHFT                                                             0x2
#define HWIO_GCC_MMNOC_GDSCR_HW_CONTROL_BMSK                                                              0x2
#define HWIO_GCC_MMNOC_GDSCR_HW_CONTROL_SHFT                                                              0x1
#define HWIO_GCC_MMNOC_GDSCR_SW_COLLAPSE_BMSK                                                             0x1
#define HWIO_GCC_MMNOC_GDSCR_SW_COLLAPSE_SHFT                                                             0x0

#define HWIO_GCC_MMNOC_CFG_GDSCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00009008)
#define HWIO_GCC_MMNOC_CFG_GDSCR_RMSK                                                              0xffffffff
#define HWIO_GCC_MMNOC_CFG_GDSCR_IN          \
        in_dword(HWIO_GCC_MMNOC_CFG_GDSCR_ADDR)
#define HWIO_GCC_MMNOC_CFG_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_CFG_GDSCR_ADDR, m)
#define HWIO_GCC_MMNOC_CFG_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_CFG_GDSCR_ADDR,v)
#define HWIO_GCC_MMNOC_CFG_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_CFG_GDSCR_ADDR,m,v,HWIO_GCC_MMNOC_CFG_GDSCR_IN)
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_SPARE_CTRL_IN_BMSK                                           0xf0000000
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_SPARE_CTRL_IN_SHFT                                                 0x1c
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK                                           0xc000000
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT                                                0x1a
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK                                            0x2000000
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT                                                 0x19
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PWR_UP_START_BMSK                                             0x1000000
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PWR_UP_START_SHFT                                                  0x18
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK                                      0xf00000
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT                                          0x14
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                                         0x80000
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                                            0x13
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK                                             0x40000
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT                                                0x12
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK                                             0x20000
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT                                                0x11
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK                                          0x10000
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT                                             0x10
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                                         0x8000
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                                            0xf
#define HWIO_GCC_MMNOC_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                                        0x7800
#define HWIO_GCC_MMNOC_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                                           0xb
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK                                                0x400
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT                                                  0xa
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                                         0x200
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                                           0x9
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                                         0x100
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                                           0x8
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                                             0x80
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                                              0x7
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                                    0x60
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                                     0x5
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                                              0x10
#define HWIO_GCC_MMNOC_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                                               0x4
#define HWIO_GCC_MMNOC_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                        0x8
#define HWIO_GCC_MMNOC_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                        0x3
#define HWIO_GCC_MMNOC_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                                      0x4
#define HWIO_GCC_MMNOC_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                                      0x2
#define HWIO_GCC_MMNOC_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                          0x2
#define HWIO_GCC_MMNOC_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                          0x1
#define HWIO_GCC_MMNOC_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                                       0x1
#define HWIO_GCC_MMNOC_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                                       0x0

#define HWIO_GCC_MMNOC_CFG2_GDSCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000900c)
#define HWIO_GCC_MMNOC_CFG2_GDSCR_RMSK                                                                0x1ffff
#define HWIO_GCC_MMNOC_CFG2_GDSCR_IN          \
        in_dword(HWIO_GCC_MMNOC_CFG2_GDSCR_ADDR)
#define HWIO_GCC_MMNOC_CFG2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_CFG2_GDSCR_ADDR, m)
#define HWIO_GCC_MMNOC_CFG2_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_CFG2_GDSCR_ADDR,v)
#define HWIO_GCC_MMNOC_CFG2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_MMNOC_CFG2_GDSCR_IN)
#define HWIO_GCC_MMNOC_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK                                              0x10000
#define HWIO_GCC_MMNOC_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT                                                 0x10
#define HWIO_GCC_MMNOC_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK                                                  0xf000
#define HWIO_GCC_MMNOC_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT                                                     0xc
#define HWIO_GCC_MMNOC_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                                           0xf00
#define HWIO_GCC_MMNOC_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                                             0x8
#define HWIO_GCC_MMNOC_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                                              0xf0
#define HWIO_GCC_MMNOC_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                                               0x4
#define HWIO_GCC_MMNOC_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                                                0xf
#define HWIO_GCC_MMNOC_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                                                0x0

#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00009010)
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_RMSK                                                           0x80107ff5
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_IN          \
        in_dword(HWIO_GCC_MMNOC_TBU_SF0_CBCR_ADDR)
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_TBU_SF0_CBCR_ADDR, m)
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_TBU_SF0_CBCR_ADDR,v)
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_TBU_SF0_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_TBU_SF0_CBCR_IN)
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_FORCE_MEM_CORE_ON_BMSK                                             0x4000
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_FORCE_MEM_CORE_ON_SHFT                                                0xe
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                           0x2000
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                              0xd
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                          0x1000
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                             0xc
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_WAKEUP_BMSK                                                         0xf00
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_WAKEUP_SHFT                                                           0x8
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_SLEEP_BMSK                                                           0xf0
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_SLEEP_SHFT                                                            0x4
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_MMNOC_TBU_SF0_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00009014)
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_RMSK                                                          0xfffff37e
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_IN          \
        in_dword(HWIO_GCC_MMNOC_TBU_SF0_SREGR_ADDR)
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_TBU_SF0_SREGR_ADDR, m)
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_TBU_SF0_SREGR_ADDR,v)
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_TBU_SF0_SREGR_ADDR,m,v,HWIO_GCC_MMNOC_TBU_SF0_SREGR_IN)
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                                0xff000000
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                      0x18
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                   0xff0000
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                       0x10
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_RESERVE_BITS15_13_BMSK                                            0xe000
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_RESERVE_BITS15_13_SHFT                                               0xd
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                  0x1000
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                     0xc
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                      0x300
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                        0x8
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_FORCE_CLK_ON_BMSK                                                   0x40
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_FORCE_CLK_ON_SHFT                                                    0x6
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SW_RST_SEL_SLP_STG_BMSK                                             0x20
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SW_RST_SEL_SLP_STG_SHFT                                              0x5
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SW_RST_SLP_STG_BMSK                                                 0x10
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SW_RST_SLP_STG_SHFT                                                  0x4
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SW_CTRL_PWR_DOWN_BMSK                                                0x8
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SW_CTRL_PWR_DOWN_SHFT                                                0x3
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                           0x4
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                           0x2
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SW_CLK_EN_SLP_STG_BMSK                                               0x2
#define HWIO_GCC_MMNOC_TBU_SF0_SREGR_SW_CLK_EN_SLP_STG_SHFT                                               0x1

#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00009018)
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_RMSK                                                           0x80107ff5
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_IN          \
        in_dword(HWIO_GCC_MMNOC_TBU_SF1_CBCR_ADDR)
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_TBU_SF1_CBCR_ADDR, m)
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_TBU_SF1_CBCR_ADDR,v)
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_TBU_SF1_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_TBU_SF1_CBCR_IN)
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_FORCE_MEM_CORE_ON_BMSK                                             0x4000
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_FORCE_MEM_CORE_ON_SHFT                                                0xe
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                           0x2000
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                              0xd
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                          0x1000
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                             0xc
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_WAKEUP_BMSK                                                         0xf00
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_WAKEUP_SHFT                                                           0x8
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_SLEEP_BMSK                                                           0xf0
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_SLEEP_SHFT                                                            0x4
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_MMNOC_TBU_SF1_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000901c)
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_RMSK                                                          0xfffff37e
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_IN          \
        in_dword(HWIO_GCC_MMNOC_TBU_SF1_SREGR_ADDR)
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_TBU_SF1_SREGR_ADDR, m)
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_TBU_SF1_SREGR_ADDR,v)
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_TBU_SF1_SREGR_ADDR,m,v,HWIO_GCC_MMNOC_TBU_SF1_SREGR_IN)
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                                0xff000000
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                      0x18
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                   0xff0000
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                       0x10
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_RESERVE_BITS15_13_BMSK                                            0xe000
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_RESERVE_BITS15_13_SHFT                                               0xd
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                  0x1000
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                     0xc
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                      0x300
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                        0x8
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_FORCE_CLK_ON_BMSK                                                   0x40
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_FORCE_CLK_ON_SHFT                                                    0x6
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SW_RST_SEL_SLP_STG_BMSK                                             0x20
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SW_RST_SEL_SLP_STG_SHFT                                              0x5
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SW_RST_SLP_STG_BMSK                                                 0x10
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SW_RST_SLP_STG_SHFT                                                  0x4
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SW_CTRL_PWR_DOWN_BMSK                                                0x8
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SW_CTRL_PWR_DOWN_SHFT                                                0x3
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                           0x4
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                           0x2
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SW_CLK_EN_SLP_STG_BMSK                                               0x2
#define HWIO_GCC_MMNOC_TBU_SF1_SREGR_SW_CLK_EN_SLP_STG_SHFT                                               0x1

#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00009020)
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_RMSK                                                           0x80107ff5
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_IN          \
        in_dword(HWIO_GCC_MMNOC_TBU_HF0_CBCR_ADDR)
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_TBU_HF0_CBCR_ADDR, m)
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_TBU_HF0_CBCR_ADDR,v)
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_TBU_HF0_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_TBU_HF0_CBCR_IN)
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_FORCE_MEM_CORE_ON_BMSK                                             0x4000
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_FORCE_MEM_CORE_ON_SHFT                                                0xe
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                           0x2000
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                              0xd
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                          0x1000
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                             0xc
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_WAKEUP_BMSK                                                         0xf00
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_WAKEUP_SHFT                                                           0x8
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_SLEEP_BMSK                                                           0xf0
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_SLEEP_SHFT                                                            0x4
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00009024)
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_RMSK                                                          0xfffff37e
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_IN          \
        in_dword(HWIO_GCC_MMNOC_TBU_HF0_SREGR_ADDR)
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_TBU_HF0_SREGR_ADDR, m)
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_TBU_HF0_SREGR_ADDR,v)
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_TBU_HF0_SREGR_ADDR,m,v,HWIO_GCC_MMNOC_TBU_HF0_SREGR_IN)
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                                0xff000000
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                      0x18
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                   0xff0000
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                       0x10
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_RESERVE_BITS15_13_BMSK                                            0xe000
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_RESERVE_BITS15_13_SHFT                                               0xd
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                  0x1000
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                     0xc
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                      0x300
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                        0x8
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_FORCE_CLK_ON_BMSK                                                   0x40
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_FORCE_CLK_ON_SHFT                                                    0x6
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SW_RST_SEL_SLP_STG_BMSK                                             0x20
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SW_RST_SEL_SLP_STG_SHFT                                              0x5
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SW_RST_SLP_STG_BMSK                                                 0x10
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SW_RST_SLP_STG_SHFT                                                  0x4
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SW_CTRL_PWR_DOWN_BMSK                                                0x8
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SW_CTRL_PWR_DOWN_SHFT                                                0x3
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                           0x4
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                           0x2
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SW_CLK_EN_SLP_STG_BMSK                                               0x2
#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_SW_CLK_EN_SLP_STG_SHFT                                               0x1

#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00009028)
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_RMSK                                                           0x80107ff5
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_IN          \
        in_dword(HWIO_GCC_MMNOC_TBU_HF1_CBCR_ADDR)
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_TBU_HF1_CBCR_ADDR, m)
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_TBU_HF1_CBCR_ADDR,v)
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_TBU_HF1_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_TBU_HF1_CBCR_IN)
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_FORCE_MEM_CORE_ON_BMSK                                             0x4000
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_FORCE_MEM_CORE_ON_SHFT                                                0xe
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                           0x2000
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                              0xd
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                          0x1000
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                             0xc
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_WAKEUP_BMSK                                                         0xf00
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_WAKEUP_SHFT                                                           0x8
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_SLEEP_BMSK                                                           0xf0
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_SLEEP_SHFT                                                            0x4
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000902c)
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_RMSK                                                          0xfffff37e
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_IN          \
        in_dword(HWIO_GCC_MMNOC_TBU_HF1_SREGR_ADDR)
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_TBU_HF1_SREGR_ADDR, m)
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_TBU_HF1_SREGR_ADDR,v)
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_TBU_HF1_SREGR_ADDR,m,v,HWIO_GCC_MMNOC_TBU_HF1_SREGR_IN)
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                                0xff000000
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                      0x18
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                   0xff0000
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                       0x10
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_RESERVE_BITS15_13_BMSK                                            0xe000
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_RESERVE_BITS15_13_SHFT                                               0xd
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                  0x1000
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                     0xc
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                      0x300
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                        0x8
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_FORCE_CLK_ON_BMSK                                                   0x40
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_FORCE_CLK_ON_SHFT                                                    0x6
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SW_RST_SEL_SLP_STG_BMSK                                             0x20
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SW_RST_SEL_SLP_STG_SHFT                                              0x5
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SW_RST_SLP_STG_BMSK                                                 0x10
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SW_RST_SLP_STG_SHFT                                                  0x4
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SW_CTRL_PWR_DOWN_BMSK                                                0x8
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SW_CTRL_PWR_DOWN_SHFT                                                0x3
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                           0x4
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                           0x2
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SW_CLK_EN_SLP_STG_BMSK                                               0x2
#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_SW_CLK_EN_SLP_STG_SHFT                                               0x1

#define HWIO_GCC_MMNOC_AT_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00009030)
#define HWIO_GCC_MMNOC_AT_CBCR_RMSK                                                                0x80100005
#define HWIO_GCC_MMNOC_AT_CBCR_IN          \
        in_dword(HWIO_GCC_MMNOC_AT_CBCR_ADDR)
#define HWIO_GCC_MMNOC_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_AT_CBCR_ADDR, m)
#define HWIO_GCC_MMNOC_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_AT_CBCR_ADDR,v)
#define HWIO_GCC_MMNOC_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_AT_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_AT_CBCR_IN)
#define HWIO_GCC_MMNOC_AT_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_MMNOC_AT_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_MMNOC_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_MMNOC_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_MMNOC_AT_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_MMNOC_AT_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_MMNOC_AT_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_MMNOC_AT_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00009034)
#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_RMSK                                                           0x80100005
#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_IN          \
        in_dword(HWIO_GCC_MMNOC_AHB_CFG_CBCR_ADDR)
#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_AHB_CFG_CBCR_ADDR, m)
#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_AHB_CFG_CBCR_ADDR,v)
#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_AHB_CFG_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_AHB_CFG_CBCR_IN)
#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00009038)
#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_RMSK                                                        0x80000005
#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_IN          \
        in_dword(HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_ADDR)
#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_ADDR, m)
#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_ADDR,v)
#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_ADDR,m,v,HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_IN)
#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_MMNOC_HF_QX_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000903c)
#define HWIO_GCC_MMNOC_HF_QX_CBCR_RMSK                                                             0x80100005
#define HWIO_GCC_MMNOC_HF_QX_CBCR_IN          \
        in_dword(HWIO_GCC_MMNOC_HF_QX_CBCR_ADDR)
#define HWIO_GCC_MMNOC_HF_QX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_HF_QX_CBCR_ADDR, m)
#define HWIO_GCC_MMNOC_HF_QX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_HF_QX_CBCR_ADDR,v)
#define HWIO_GCC_MMNOC_HF_QX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_HF_QX_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_HF_QX_CBCR_IN)
#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_MMNOC_HF_QX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_MMNOC_HF_QX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_MMNOC_HF_QX_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00009054)
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_RMSK                                                             0x1ffff
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_CMD_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_CMD_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_CMD_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_CMD_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_RCG_SW_CTRL_BMSK                                                 0x18000
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_RCG_SW_CTRL_SHFT                                                     0xf
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_SW_PERF_STATE_BMSK                                                0x7800
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_SW_PERF_STATE_SHFT                                                   0xb
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_SW_OVERRIDE_BMSK                                                   0x400
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_SW_OVERRIDE_SHFT                                                     0xa
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                      0x200
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                        0x9
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_DFS_FSM_STATE_BMSK                                                 0x1c0
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_DFS_FSM_STATE_SHFT                                                   0x6
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_HW_CLK_CONTROL_BMSK                                                 0x20
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_HW_CLK_CONTROL_SHFT                                                  0x5
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_CURR_PERF_STATE_BMSK                                                0x1e
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_CURR_PERF_STATE_SHFT                                                 0x1
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_DFS_EN_BMSK                                                          0x1
#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_DFS_EN_SHFT                                                          0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000905c)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00009060)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00009064)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00009068)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000906c)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00009070)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00009074)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00009078)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000907c)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00009080)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00009084)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00009088)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000908c)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00009090)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00009094)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00009098)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00009040)
#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_RMSK                                                         0x80000013
#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ADDR)
#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ADDR, m)
#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ADDR,v)
#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ADDR,m,v,HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_IN)
#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ROOT_OFF_BMSK                                                0x80000000
#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ROOT_OFF_SHFT                                                      0x1f
#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                0x10
#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                 0x4
#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ROOT_EN_BMSK                                                        0x2
#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ROOT_EN_SHFT                                                        0x1
#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_UPDATE_BMSK                                                         0x1
#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_UPDATE_SHFT                                                         0x0

#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00009044)
#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_RMSK                                                           0x11071f
#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_ADDR)
#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_ADDR, m)
#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_ADDR,v)
#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_ADDR,m,v,HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_IN)
#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_HW_CLK_CONTROL_BMSK                                            0x100000
#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                0x14
#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_RCGLITE_DISABLE_BMSK                                            0x10000
#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_RCGLITE_DISABLE_SHFT                                               0x10
#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_SEL_BMSK                                                      0x700
#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_SEL_SHFT                                                        0x8
#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_BMSK                                                       0x1f
#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_SRC_DIV_SHFT                                                        0x0

#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0000916c)
#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_RMSK                                                           0x1
#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                                0x1
#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                                0x0

#define HWIO_GCC_MMNOC_SF_QX_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00009170)
#define HWIO_GCC_MMNOC_SF_QX_CBCR_RMSK                                                             0x80100005
#define HWIO_GCC_MMNOC_SF_QX_CBCR_IN          \
        in_dword(HWIO_GCC_MMNOC_SF_QX_CBCR_ADDR)
#define HWIO_GCC_MMNOC_SF_QX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_SF_QX_CBCR_ADDR, m)
#define HWIO_GCC_MMNOC_SF_QX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_SF_QX_CBCR_ADDR,v)
#define HWIO_GCC_MMNOC_SF_QX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_SF_QX_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_SF_QX_CBCR_IN)
#define HWIO_GCC_MMNOC_SF_QX_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_MMNOC_SF_QX_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_MMNOC_SF_QX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_MMNOC_SF_QX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_MMNOC_SF_QX_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_MMNOC_SF_QX_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_MMNOC_SF_QX_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_MMNOC_SF_QX_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00009190)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00009194)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00009198)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000919c)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000091a0)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000091a4)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000091a8)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000091ac)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000091b0)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000091b4)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000091b8)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000091bc)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000091c0)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000091c4)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000091c8)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000091cc)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00009174)
#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_RMSK                                                         0x80000013
#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ADDR)
#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ADDR, m)
#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ADDR,v)
#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ADDR,m,v,HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_IN)
#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ROOT_OFF_BMSK                                                0x80000000
#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ROOT_OFF_SHFT                                                      0x1f
#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                0x10
#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                 0x4
#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ROOT_EN_BMSK                                                        0x2
#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ROOT_EN_SHFT                                                        0x1
#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_UPDATE_BMSK                                                         0x1
#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_UPDATE_SHFT                                                         0x0

#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00009178)
#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_RMSK                                                           0x11071f
#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_ADDR)
#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_ADDR, m)
#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_ADDR,v)
#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_ADDR,m,v,HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_IN)
#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_HW_CLK_CONTROL_BMSK                                            0x100000
#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                0x14
#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_RCGLITE_DISABLE_BMSK                                            0x10000
#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_RCGLITE_DISABLE_SHFT                                               0x10
#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_SEL_BMSK                                                      0x700
#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_SEL_SHFT                                                        0x8
#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_BMSK                                                       0x1f
#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_SRC_DIV_SHFT                                                        0x0

#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000092a0)
#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_RMSK                                                           0x1
#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                                0x1
#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                                0x0

#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000092a4)
#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_RMSK                                                     0x80000005
#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_IN          \
        in_dword(HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_ADDR)
#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_ADDR, m)
#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_ADDR,v)
#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_ADDR,m,v,HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_IN)
#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_MMSS_BCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b000)
#define HWIO_GCC_MMSS_BCR_RMSK                                                                            0x1
#define HWIO_GCC_MMSS_BCR_IN          \
        in_dword(HWIO_GCC_MMSS_BCR_ADDR)
#define HWIO_GCC_MMSS_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMSS_BCR_ADDR, m)
#define HWIO_GCC_MMSS_BCR_OUT(v)      \
        out_dword(HWIO_GCC_MMSS_BCR_ADDR,v)
#define HWIO_GCC_MMSS_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMSS_BCR_ADDR,m,v,HWIO_GCC_MMSS_BCR_IN)
#define HWIO_GCC_MMSS_BCR_BLK_ARES_BMSK                                                                   0x1
#define HWIO_GCC_MMSS_BCR_BLK_ARES_SHFT                                                                   0x0

#define HWIO_GCC_VIDEO_AHB_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b004)
#define HWIO_GCC_VIDEO_AHB_CBCR_RMSK                                                               0x80100007
#define HWIO_GCC_VIDEO_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_VIDEO_AHB_CBCR_ADDR)
#define HWIO_GCC_VIDEO_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_VIDEO_AHB_CBCR_ADDR, m)
#define HWIO_GCC_VIDEO_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_VIDEO_AHB_CBCR_ADDR,v)
#define HWIO_GCC_VIDEO_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VIDEO_AHB_CBCR_ADDR,m,v,HWIO_GCC_VIDEO_AHB_CBCR_IN)
#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_VIDEO_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                             0x100000
#define HWIO_GCC_VIDEO_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                 0x14
#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_ARES_SHFT                                                             0x2
#define HWIO_GCC_VIDEO_AHB_CBCR_HW_CTL_BMSK                                                               0x2
#define HWIO_GCC_VIDEO_AHB_CBCR_HW_CTL_SHFT                                                               0x1
#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_VIDEO_AHB_CBCR_CLK_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_CAMERA_AHB_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b008)
#define HWIO_GCC_CAMERA_AHB_CBCR_RMSK                                                              0x80100007
#define HWIO_GCC_CAMERA_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_CAMERA_AHB_CBCR_ADDR)
#define HWIO_GCC_CAMERA_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CAMERA_AHB_CBCR_ADDR, m)
#define HWIO_GCC_CAMERA_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CAMERA_AHB_CBCR_ADDR,v)
#define HWIO_GCC_CAMERA_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CAMERA_AHB_CBCR_ADDR,m,v,HWIO_GCC_CAMERA_AHB_CBCR_IN)
#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_CAMERA_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                            0x100000
#define HWIO_GCC_CAMERA_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                0x14
#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_CAMERA_AHB_CBCR_HW_CTL_BMSK                                                              0x2
#define HWIO_GCC_CAMERA_AHB_CBCR_HW_CTL_SHFT                                                              0x1
#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_CAMERA_AHB_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_DISP_AHB_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b00c)
#define HWIO_GCC_DISP_AHB_CBCR_RMSK                                                                0x80100007
#define HWIO_GCC_DISP_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_DISP_AHB_CBCR_ADDR)
#define HWIO_GCC_DISP_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DISP_AHB_CBCR_ADDR, m)
#define HWIO_GCC_DISP_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DISP_AHB_CBCR_ADDR,v)
#define HWIO_GCC_DISP_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DISP_AHB_CBCR_ADDR,m,v,HWIO_GCC_DISP_AHB_CBCR_IN)
#define HWIO_GCC_DISP_AHB_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_DISP_AHB_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_DISP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_DISP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_DISP_AHB_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_DISP_AHB_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_DISP_AHB_CBCR_HW_CTL_BMSK                                                                0x2
#define HWIO_GCC_DISP_AHB_CBCR_HW_CTL_SHFT                                                                0x1
#define HWIO_GCC_DISP_AHB_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_DISP_AHB_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b010)
#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_RMSK                                                      0x80100007
#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_ADDR)
#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_ADDR, m)
#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_ADDR,v)
#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_IN)
#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                    0x100000
#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                        0x14
#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_HW_CTL_BMSK                                                      0x2
#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_HW_CTL_SHFT                                                      0x1
#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_CLK_ENABLE_SHFT                                                  0x0

#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b014)
#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_RMSK                                                   0x80100007
#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_ADDR)
#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_ADDR, m)
#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_ADDR,v)
#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_IN)
#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                 0x100000
#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                     0x14
#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_HW_CTL_BMSK                                                   0x2
#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_HW_CTL_SHFT                                                   0x1
#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_CLK_ENABLE_SHFT                                               0x0

#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b018)
#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_RMSK                                                     0x80100007
#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_ADDR)
#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_ADDR, m)
#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_ADDR,v)
#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_IN)
#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                   0x100000
#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                       0x14
#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_HW_CTL_BMSK                                                     0x2
#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_HW_CTL_SHFT                                                     0x1
#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b01c)
#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_RMSK                                                      0x80100007
#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_ADDR)
#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_ADDR, m)
#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_ADDR,v)
#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_IN)
#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                    0x100000
#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                        0x14
#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_HW_CTL_BMSK                                                      0x2
#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_HW_CTL_SHFT                                                      0x1
#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_CLK_ENABLE_SHFT                                                  0x0

#define HWIO_GCC_QMIP_DISP_AHB_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b020)
#define HWIO_GCC_QMIP_DISP_AHB_CBCR_RMSK                                                           0x80100007
#define HWIO_GCC_QMIP_DISP_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_QMIP_DISP_AHB_CBCR_ADDR)
#define HWIO_GCC_QMIP_DISP_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QMIP_DISP_AHB_CBCR_ADDR, m)
#define HWIO_GCC_QMIP_DISP_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QMIP_DISP_AHB_CBCR_ADDR,v)
#define HWIO_GCC_QMIP_DISP_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QMIP_DISP_AHB_CBCR_ADDR,m,v,HWIO_GCC_QMIP_DISP_AHB_CBCR_IN)
#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_QMIP_DISP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_QMIP_DISP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_QMIP_DISP_AHB_CBCR_HW_CTL_BMSK                                                           0x2
#define HWIO_GCC_QMIP_DISP_AHB_CBCR_HW_CTL_SHFT                                                           0x1
#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_QMIP_DISP_AHB_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_VIDEO_AXI0_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b024)
#define HWIO_GCC_VIDEO_AXI0_CBCR_RMSK                                                              0x80107ff5
#define HWIO_GCC_VIDEO_AXI0_CBCR_IN          \
        in_dword(HWIO_GCC_VIDEO_AXI0_CBCR_ADDR)
#define HWIO_GCC_VIDEO_AXI0_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_VIDEO_AXI0_CBCR_ADDR, m)
#define HWIO_GCC_VIDEO_AXI0_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_VIDEO_AXI0_CBCR_ADDR,v)
#define HWIO_GCC_VIDEO_AXI0_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VIDEO_AXI0_CBCR_ADDR,m,v,HWIO_GCC_VIDEO_AXI0_CBCR_IN)
#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_VIDEO_AXI0_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                            0x100000
#define HWIO_GCC_VIDEO_AXI0_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                0x14
#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_CORE_ON_BMSK                                                0x4000
#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_CORE_ON_SHFT                                                   0xe
#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                              0x2000
#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                 0xd
#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                             0x1000
#define HWIO_GCC_VIDEO_AXI0_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                                0xc
#define HWIO_GCC_VIDEO_AXI0_CBCR_WAKEUP_BMSK                                                            0xf00
#define HWIO_GCC_VIDEO_AXI0_CBCR_WAKEUP_SHFT                                                              0x8
#define HWIO_GCC_VIDEO_AXI0_CBCR_SLEEP_BMSK                                                              0xf0
#define HWIO_GCC_VIDEO_AXI0_CBCR_SLEEP_SHFT                                                               0x4
#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_VIDEO_AXI0_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_VIDEO_AXI1_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b028)
#define HWIO_GCC_VIDEO_AXI1_CBCR_RMSK                                                              0x80107ff5
#define HWIO_GCC_VIDEO_AXI1_CBCR_IN          \
        in_dword(HWIO_GCC_VIDEO_AXI1_CBCR_ADDR)
#define HWIO_GCC_VIDEO_AXI1_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_VIDEO_AXI1_CBCR_ADDR, m)
#define HWIO_GCC_VIDEO_AXI1_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_VIDEO_AXI1_CBCR_ADDR,v)
#define HWIO_GCC_VIDEO_AXI1_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VIDEO_AXI1_CBCR_ADDR,m,v,HWIO_GCC_VIDEO_AXI1_CBCR_IN)
#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_VIDEO_AXI1_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                            0x100000
#define HWIO_GCC_VIDEO_AXI1_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                0x14
#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_CORE_ON_BMSK                                                0x4000
#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_CORE_ON_SHFT                                                   0xe
#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                              0x2000
#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                 0xd
#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                             0x1000
#define HWIO_GCC_VIDEO_AXI1_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                                0xc
#define HWIO_GCC_VIDEO_AXI1_CBCR_WAKEUP_BMSK                                                            0xf00
#define HWIO_GCC_VIDEO_AXI1_CBCR_WAKEUP_SHFT                                                              0x8
#define HWIO_GCC_VIDEO_AXI1_CBCR_SLEEP_BMSK                                                              0xf0
#define HWIO_GCC_VIDEO_AXI1_CBCR_SLEEP_SHFT                                                               0x4
#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_VIDEO_AXI1_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_CAMERA_HF_AXI_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b02c)
#define HWIO_GCC_CAMERA_HF_AXI_CBCR_RMSK                                                           0x80100005
#define HWIO_GCC_CAMERA_HF_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_CAMERA_HF_AXI_CBCR_ADDR)
#define HWIO_GCC_CAMERA_HF_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CAMERA_HF_AXI_CBCR_ADDR, m)
#define HWIO_GCC_CAMERA_HF_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CAMERA_HF_AXI_CBCR_ADDR,v)
#define HWIO_GCC_CAMERA_HF_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CAMERA_HF_AXI_CBCR_ADDR,m,v,HWIO_GCC_CAMERA_HF_AXI_CBCR_IN)
#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_CAMERA_HF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_CAMERA_HF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_CAMERA_HF_AXI_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_CAMERA_SF_AXI_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b030)
#define HWIO_GCC_CAMERA_SF_AXI_CBCR_RMSK                                                           0x80100005
#define HWIO_GCC_CAMERA_SF_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_CAMERA_SF_AXI_CBCR_ADDR)
#define HWIO_GCC_CAMERA_SF_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CAMERA_SF_AXI_CBCR_ADDR, m)
#define HWIO_GCC_CAMERA_SF_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CAMERA_SF_AXI_CBCR_ADDR,v)
#define HWIO_GCC_CAMERA_SF_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CAMERA_SF_AXI_CBCR_ADDR,m,v,HWIO_GCC_CAMERA_SF_AXI_CBCR_IN)
#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_CAMERA_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_CAMERA_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_CAMERA_SF_AXI_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_DISP_HF_AXI_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b034)
#define HWIO_GCC_DISP_HF_AXI_CBCR_RMSK                                                             0x80107ff5
#define HWIO_GCC_DISP_HF_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_DISP_HF_AXI_CBCR_ADDR)
#define HWIO_GCC_DISP_HF_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DISP_HF_AXI_CBCR_ADDR, m)
#define HWIO_GCC_DISP_HF_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DISP_HF_AXI_CBCR_ADDR,v)
#define HWIO_GCC_DISP_HF_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DISP_HF_AXI_CBCR_ADDR,m,v,HWIO_GCC_DISP_HF_AXI_CBCR_IN)
#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_DISP_HF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_DISP_HF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK                                               0x4000
#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT                                                  0xe
#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                             0x2000
#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                0xd
#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                            0x1000
#define HWIO_GCC_DISP_HF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                               0xc
#define HWIO_GCC_DISP_HF_AXI_CBCR_WAKEUP_BMSK                                                           0xf00
#define HWIO_GCC_DISP_HF_AXI_CBCR_WAKEUP_SHFT                                                             0x8
#define HWIO_GCC_DISP_HF_AXI_CBCR_SLEEP_BMSK                                                             0xf0
#define HWIO_GCC_DISP_HF_AXI_CBCR_SLEEP_SHFT                                                              0x4
#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_DISP_HF_AXI_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_DISP_SF_AXI_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b038)
#define HWIO_GCC_DISP_SF_AXI_CBCR_RMSK                                                             0x80107ff5
#define HWIO_GCC_DISP_SF_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_DISP_SF_AXI_CBCR_ADDR)
#define HWIO_GCC_DISP_SF_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DISP_SF_AXI_CBCR_ADDR, m)
#define HWIO_GCC_DISP_SF_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DISP_SF_AXI_CBCR_ADDR,v)
#define HWIO_GCC_DISP_SF_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DISP_SF_AXI_CBCR_ADDR,m,v,HWIO_GCC_DISP_SF_AXI_CBCR_IN)
#define HWIO_GCC_DISP_SF_AXI_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_DISP_SF_AXI_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_DISP_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_DISP_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_DISP_SF_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK                                               0x4000
#define HWIO_GCC_DISP_SF_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT                                                  0xe
#define HWIO_GCC_DISP_SF_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                             0x2000
#define HWIO_GCC_DISP_SF_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                0xd
#define HWIO_GCC_DISP_SF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                            0x1000
#define HWIO_GCC_DISP_SF_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                               0xc
#define HWIO_GCC_DISP_SF_AXI_CBCR_WAKEUP_BMSK                                                           0xf00
#define HWIO_GCC_DISP_SF_AXI_CBCR_WAKEUP_SHFT                                                             0x8
#define HWIO_GCC_DISP_SF_AXI_CBCR_SLEEP_BMSK                                                             0xf0
#define HWIO_GCC_DISP_SF_AXI_CBCR_SLEEP_SHFT                                                              0x4
#define HWIO_GCC_DISP_SF_AXI_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_DISP_SF_AXI_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_DISP_SF_AXI_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_DISP_SF_AXI_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_VIDEO_XO_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b03c)
#define HWIO_GCC_VIDEO_XO_CBCR_RMSK                                                                0x80000005
#define HWIO_GCC_VIDEO_XO_CBCR_IN          \
        in_dword(HWIO_GCC_VIDEO_XO_CBCR_ADDR)
#define HWIO_GCC_VIDEO_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_VIDEO_XO_CBCR_ADDR, m)
#define HWIO_GCC_VIDEO_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_VIDEO_XO_CBCR_ADDR,v)
#define HWIO_GCC_VIDEO_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VIDEO_XO_CBCR_ADDR,m,v,HWIO_GCC_VIDEO_XO_CBCR_IN)
#define HWIO_GCC_VIDEO_XO_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_VIDEO_XO_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_VIDEO_XO_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_VIDEO_XO_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_VIDEO_XO_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_VIDEO_XO_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_CAMERA_XO_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b040)
#define HWIO_GCC_CAMERA_XO_CBCR_RMSK                                                               0x80000005
#define HWIO_GCC_CAMERA_XO_CBCR_IN          \
        in_dword(HWIO_GCC_CAMERA_XO_CBCR_ADDR)
#define HWIO_GCC_CAMERA_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CAMERA_XO_CBCR_ADDR, m)
#define HWIO_GCC_CAMERA_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CAMERA_XO_CBCR_ADDR,v)
#define HWIO_GCC_CAMERA_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CAMERA_XO_CBCR_ADDR,m,v,HWIO_GCC_CAMERA_XO_CBCR_IN)
#define HWIO_GCC_CAMERA_XO_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_CAMERA_XO_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_CAMERA_XO_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_CAMERA_XO_CBCR_CLK_ARES_SHFT                                                             0x2
#define HWIO_GCC_CAMERA_XO_CBCR_CLK_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_CAMERA_XO_CBCR_CLK_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_DISP_XO_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b044)
#define HWIO_GCC_DISP_XO_CBCR_RMSK                                                                 0x80000005
#define HWIO_GCC_DISP_XO_CBCR_IN          \
        in_dword(HWIO_GCC_DISP_XO_CBCR_ADDR)
#define HWIO_GCC_DISP_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DISP_XO_CBCR_ADDR, m)
#define HWIO_GCC_DISP_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DISP_XO_CBCR_ADDR,v)
#define HWIO_GCC_DISP_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DISP_XO_CBCR_ADDR,m,v,HWIO_GCC_DISP_XO_CBCR_IN)
#define HWIO_GCC_DISP_XO_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_DISP_XO_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_DISP_XO_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_DISP_XO_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_DISP_XO_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_DISP_XO_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_MMSS_AT_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b048)
#define HWIO_GCC_MMSS_AT_CBCR_RMSK                                                                 0x80100005
#define HWIO_GCC_MMSS_AT_CBCR_IN          \
        in_dword(HWIO_GCC_MMSS_AT_CBCR_ADDR)
#define HWIO_GCC_MMSS_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMSS_AT_CBCR_ADDR, m)
#define HWIO_GCC_MMSS_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MMSS_AT_CBCR_ADDR,v)
#define HWIO_GCC_MMSS_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMSS_AT_CBCR_ADDR,m,v,HWIO_GCC_MMSS_AT_CBCR_IN)
#define HWIO_GCC_MMSS_AT_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_MMSS_AT_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_MMSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                               0x100000
#define HWIO_GCC_MMSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                   0x14
#define HWIO_GCC_MMSS_AT_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_MMSS_AT_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_MMSS_AT_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_MMSS_AT_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_MMSS_QM_CORE_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b04c)
#define HWIO_GCC_MMSS_QM_CORE_CBCR_RMSK                                                            0x80000005
#define HWIO_GCC_MMSS_QM_CORE_CBCR_IN          \
        in_dword(HWIO_GCC_MMSS_QM_CORE_CBCR_ADDR)
#define HWIO_GCC_MMSS_QM_CORE_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMSS_QM_CORE_CBCR_ADDR, m)
#define HWIO_GCC_MMSS_QM_CORE_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MMSS_QM_CORE_CBCR_ADDR,v)
#define HWIO_GCC_MMSS_QM_CORE_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMSS_QM_CORE_CBCR_ADDR,m,v,HWIO_GCC_MMSS_QM_CORE_CBCR_IN)
#define HWIO_GCC_MMSS_QM_CORE_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_MMSS_QM_CORE_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_MMSS_QM_CORE_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_MMSS_QM_CORE_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_MMSS_QM_CORE_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_MMSS_QM_CORE_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_MMSS_TRIG_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b050)
#define HWIO_GCC_MMSS_TRIG_CBCR_RMSK                                                               0x80100005
#define HWIO_GCC_MMSS_TRIG_CBCR_IN          \
        in_dword(HWIO_GCC_MMSS_TRIG_CBCR_ADDR)
#define HWIO_GCC_MMSS_TRIG_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMSS_TRIG_CBCR_ADDR, m)
#define HWIO_GCC_MMSS_TRIG_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MMSS_TRIG_CBCR_ADDR,v)
#define HWIO_GCC_MMSS_TRIG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMSS_TRIG_CBCR_ADDR,m,v,HWIO_GCC_MMSS_TRIG_CBCR_IN)
#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_MMSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                             0x100000
#define HWIO_GCC_MMSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                 0x14
#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_ARES_SHFT                                                             0x2
#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_MMSS_TRIG_CBCR_CLK_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b054)
#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_RMSK                                                        0x80000013
#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_ADDR)
#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_ADDR, m)
#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_ADDR,v)
#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_ADDR,m,v,HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_IN)
#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_ROOT_OFF_BMSK                                               0x80000000
#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_ROOT_OFF_SHFT                                                     0x1f
#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                               0x10
#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                0x4
#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_ROOT_EN_BMSK                                                       0x2
#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_ROOT_EN_SHFT                                                       0x1
#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_UPDATE_BMSK                                                        0x1
#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_UPDATE_SHFT                                                        0x0

#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b058)
#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_RMSK                                                          0x11071f
#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_ADDR)
#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_ADDR, m)
#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_ADDR,v)
#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_ADDR,m,v,HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_IN)
#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_HW_CLK_CONTROL_BMSK                                           0x100000
#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_HW_CLK_CONTROL_SHFT                                               0x14
#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_RCGLITE_DISABLE_BMSK                                           0x10000
#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_RCGLITE_DISABLE_SHFT                                              0x10
#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_SRC_SEL_BMSK                                                     0x700
#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_SRC_SEL_SHFT                                                       0x8
#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_SRC_DIV_BMSK                                                      0x1f
#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_SRC_DIV_SHFT                                                       0x0

#define HWIO_GCC_MMSS_QM_AHB_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000b06c)
#define HWIO_GCC_MMSS_QM_AHB_CBCR_RMSK                                                             0x80100005
#define HWIO_GCC_MMSS_QM_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_MMSS_QM_AHB_CBCR_ADDR)
#define HWIO_GCC_MMSS_QM_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMSS_QM_AHB_CBCR_ADDR, m)
#define HWIO_GCC_MMSS_QM_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MMSS_QM_AHB_CBCR_ADDR,v)
#define HWIO_GCC_MMSS_QM_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMSS_QM_AHB_CBCR_ADDR,m,v,HWIO_GCC_MMSS_QM_AHB_CBCR_IN)
#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_MMSS_QM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_MMSS_QM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_MMSS_QM_AHB_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_PIMEM_BCR_ADDR                                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0000a000)
#define HWIO_GCC_PIMEM_BCR_RMSK                                                                           0x1
#define HWIO_GCC_PIMEM_BCR_IN          \
        in_dword(HWIO_GCC_PIMEM_BCR_ADDR)
#define HWIO_GCC_PIMEM_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PIMEM_BCR_ADDR, m)
#define HWIO_GCC_PIMEM_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PIMEM_BCR_ADDR,v)
#define HWIO_GCC_PIMEM_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PIMEM_BCR_ADDR,m,v,HWIO_GCC_PIMEM_BCR_IN)
#define HWIO_GCC_PIMEM_BCR_BLK_ARES_BMSK                                                                  0x1
#define HWIO_GCC_PIMEM_BCR_BLK_ARES_SHFT                                                                  0x0

#define HWIO_GCC_PIMEM_AXI_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0000a004)
#define HWIO_GCC_PIMEM_AXI_CBCR_RMSK                                                               0x80107ff5
#define HWIO_GCC_PIMEM_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_PIMEM_AXI_CBCR_ADDR)
#define HWIO_GCC_PIMEM_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PIMEM_AXI_CBCR_ADDR, m)
#define HWIO_GCC_PIMEM_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PIMEM_AXI_CBCR_ADDR,v)
#define HWIO_GCC_PIMEM_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PIMEM_AXI_CBCR_ADDR,m,v,HWIO_GCC_PIMEM_AXI_CBCR_IN)
#define HWIO_GCC_PIMEM_AXI_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_PIMEM_AXI_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_PIMEM_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                             0x100000
#define HWIO_GCC_PIMEM_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                 0x14
#define HWIO_GCC_PIMEM_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK                                                 0x4000
#define HWIO_GCC_PIMEM_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT                                                    0xe
#define HWIO_GCC_PIMEM_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                               0x2000
#define HWIO_GCC_PIMEM_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                  0xd
#define HWIO_GCC_PIMEM_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                              0x1000
#define HWIO_GCC_PIMEM_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                                 0xc
#define HWIO_GCC_PIMEM_AXI_CBCR_WAKEUP_BMSK                                                             0xf00
#define HWIO_GCC_PIMEM_AXI_CBCR_WAKEUP_SHFT                                                               0x8
#define HWIO_GCC_PIMEM_AXI_CBCR_SLEEP_BMSK                                                               0xf0
#define HWIO_GCC_PIMEM_AXI_CBCR_SLEEP_SHFT                                                                0x4
#define HWIO_GCC_PIMEM_AXI_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_PIMEM_AXI_CBCR_CLK_ARES_SHFT                                                             0x2
#define HWIO_GCC_PIMEM_AXI_CBCR_CLK_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_PIMEM_AXI_CBCR_CLK_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_PIMEM_AHB_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0000a008)
#define HWIO_GCC_PIMEM_AHB_CBCR_RMSK                                                               0x80100005
#define HWIO_GCC_PIMEM_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_PIMEM_AHB_CBCR_ADDR)
#define HWIO_GCC_PIMEM_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PIMEM_AHB_CBCR_ADDR, m)
#define HWIO_GCC_PIMEM_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PIMEM_AHB_CBCR_ADDR,v)
#define HWIO_GCC_PIMEM_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PIMEM_AHB_CBCR_ADDR,m,v,HWIO_GCC_PIMEM_AHB_CBCR_IN)
#define HWIO_GCC_PIMEM_AHB_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_PIMEM_AHB_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_PIMEM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                             0x100000
#define HWIO_GCC_PIMEM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                 0x14
#define HWIO_GCC_PIMEM_AHB_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_PIMEM_AHB_CBCR_CLK_ARES_SHFT                                                             0x2
#define HWIO_GCC_PIMEM_AHB_CBCR_CLK_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_PIMEM_AHB_CBCR_CLK_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_QDSS_BCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c000)
#define HWIO_GCC_QDSS_BCR_RMSK                                                                            0x1
#define HWIO_GCC_QDSS_BCR_IN          \
        in_dword(HWIO_GCC_QDSS_BCR_ADDR)
#define HWIO_GCC_QDSS_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_BCR_ADDR, m)
#define HWIO_GCC_QDSS_BCR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_BCR_ADDR,v)
#define HWIO_GCC_QDSS_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_BCR_ADDR,m,v,HWIO_GCC_QDSS_BCR_IN)
#define HWIO_GCC_QDSS_BCR_BLK_ARES_BMSK                                                                   0x1
#define HWIO_GCC_QDSS_BCR_BLK_ARES_SHFT                                                                   0x0

#define HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c004)
#define HWIO_GCC_QDSS_DAP_AHB_CBCR_RMSK                                                            0x80100005
#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR)
#define HWIO_GCC_QDSS_DAP_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR, m)
#define HWIO_GCC_QDSS_DAP_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR,v)
#define HWIO_GCC_QDSS_DAP_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR,m,v,HWIO_GCC_QDSS_DAP_AHB_CBCR_IN)
#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                          0x100000
#define HWIO_GCC_QDSS_DAP_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                              0x14
#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_QDSS_DAP_AHB_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c008)
#define HWIO_GCC_QDSS_CFG_AHB_CBCR_RMSK                                                            0x80100006
#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR)
#define HWIO_GCC_QDSS_CFG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR, m)
#define HWIO_GCC_QDSS_CFG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR,v)
#define HWIO_GCC_QDSS_CFG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_QDSS_CFG_AHB_CBCR_IN)
#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                          0x100000
#define HWIO_GCC_QDSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                              0x14
#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_QDSS_CFG_AHB_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_QDSS_CFG_AHB_CBCR_HW_CTL_BMSK                                                            0x2
#define HWIO_GCC_QDSS_CFG_AHB_CBCR_HW_CTL_SHFT                                                            0x1

#define HWIO_GCC_QDSS_CENTER_AT_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c00c)
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_RMSK                                                          0x80107ff5
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_IN          \
        in_dword(HWIO_GCC_QDSS_CENTER_AT_CBCR_ADDR)
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_CENTER_AT_CBCR_ADDR, m)
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_CENTER_AT_CBCR_ADDR,v)
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_CENTER_AT_CBCR_ADDR,m,v,HWIO_GCC_QDSS_CENTER_AT_CBCR_IN)
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_QDSS_CENTER_AT_CBCR_CLK_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_SOUTH_AT_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c010)
#define HWIO_GCC_SOUTH_AT_CBCR_RMSK                                                                0x80100005
#define HWIO_GCC_SOUTH_AT_CBCR_IN          \
        in_dword(HWIO_GCC_SOUTH_AT_CBCR_ADDR)
#define HWIO_GCC_SOUTH_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SOUTH_AT_CBCR_ADDR, m)
#define HWIO_GCC_SOUTH_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SOUTH_AT_CBCR_ADDR,v)
#define HWIO_GCC_SOUTH_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SOUTH_AT_CBCR_ADDR,m,v,HWIO_GCC_SOUTH_AT_CBCR_IN)
#define HWIO_GCC_SOUTH_AT_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_SOUTH_AT_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_SOUTH_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_SOUTH_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_SOUTH_AT_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_SOUTH_AT_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_SOUTH_AT_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_SOUTH_AT_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_COMPUTE_AT_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c014)
#define HWIO_GCC_COMPUTE_AT_CBCR_RMSK                                                              0x80100005
#define HWIO_GCC_COMPUTE_AT_CBCR_IN          \
        in_dword(HWIO_GCC_COMPUTE_AT_CBCR_ADDR)
#define HWIO_GCC_COMPUTE_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_COMPUTE_AT_CBCR_ADDR, m)
#define HWIO_GCC_COMPUTE_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_COMPUTE_AT_CBCR_ADDR,v)
#define HWIO_GCC_COMPUTE_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_COMPUTE_AT_CBCR_ADDR,m,v,HWIO_GCC_COMPUTE_AT_CBCR_IN)
#define HWIO_GCC_COMPUTE_AT_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_COMPUTE_AT_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_COMPUTE_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                            0x100000
#define HWIO_GCC_COMPUTE_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                0x14
#define HWIO_GCC_COMPUTE_AT_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_COMPUTE_AT_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_COMPUTE_AT_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_COMPUTE_AT_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_NORTH_AT_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c018)
#define HWIO_GCC_NORTH_AT_CBCR_RMSK                                                                0x80100005
#define HWIO_GCC_NORTH_AT_CBCR_IN          \
        in_dword(HWIO_GCC_NORTH_AT_CBCR_ADDR)
#define HWIO_GCC_NORTH_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NORTH_AT_CBCR_ADDR, m)
#define HWIO_GCC_NORTH_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NORTH_AT_CBCR_ADDR,v)
#define HWIO_GCC_NORTH_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NORTH_AT_CBCR_ADDR,m,v,HWIO_GCC_NORTH_AT_CBCR_IN)
#define HWIO_GCC_NORTH_AT_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_NORTH_AT_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_NORTH_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_NORTH_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_NORTH_AT_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_NORTH_AT_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_NORTH_AT_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_NORTH_AT_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_PHY_AT_CBCR_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c01c)
#define HWIO_GCC_PHY_AT_CBCR_RMSK                                                                  0x80100005
#define HWIO_GCC_PHY_AT_CBCR_IN          \
        in_dword(HWIO_GCC_PHY_AT_CBCR_ADDR)
#define HWIO_GCC_PHY_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PHY_AT_CBCR_ADDR, m)
#define HWIO_GCC_PHY_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PHY_AT_CBCR_ADDR,v)
#define HWIO_GCC_PHY_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PHY_AT_CBCR_ADDR,m,v,HWIO_GCC_PHY_AT_CBCR_IN)
#define HWIO_GCC_PHY_AT_CBCR_CLK_OFF_BMSK                                                          0x80000000
#define HWIO_GCC_PHY_AT_CBCR_CLK_OFF_SHFT                                                                0x1f
#define HWIO_GCC_PHY_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                                0x100000
#define HWIO_GCC_PHY_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                    0x14
#define HWIO_GCC_PHY_AT_CBCR_CLK_ARES_BMSK                                                                0x4
#define HWIO_GCC_PHY_AT_CBCR_CLK_ARES_SHFT                                                                0x2
#define HWIO_GCC_PHY_AT_CBCR_CLK_ENABLE_BMSK                                                              0x1
#define HWIO_GCC_PHY_AT_CBCR_CLK_ENABLE_SHFT                                                              0x0

#define HWIO_GCC_PIMEM_AT_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c020)
#define HWIO_GCC_PIMEM_AT_CBCR_RMSK                                                                0x80100005
#define HWIO_GCC_PIMEM_AT_CBCR_IN          \
        in_dword(HWIO_GCC_PIMEM_AT_CBCR_ADDR)
#define HWIO_GCC_PIMEM_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PIMEM_AT_CBCR_ADDR, m)
#define HWIO_GCC_PIMEM_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PIMEM_AT_CBCR_ADDR,v)
#define HWIO_GCC_PIMEM_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PIMEM_AT_CBCR_ADDR,m,v,HWIO_GCC_PIMEM_AT_CBCR_IN)
#define HWIO_GCC_PIMEM_AT_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_PIMEM_AT_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_PIMEM_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_PIMEM_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_PIMEM_AT_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_PIMEM_AT_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_PIMEM_AT_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_PIMEM_AT_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c024)
#define HWIO_GCC_QDSS_ETR_USB_CBCR_RMSK                                                            0x80100005
#define HWIO_GCC_QDSS_ETR_USB_CBCR_IN          \
        in_dword(HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR)
#define HWIO_GCC_QDSS_ETR_USB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR, m)
#define HWIO_GCC_QDSS_ETR_USB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR,v)
#define HWIO_GCC_QDSS_ETR_USB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR,m,v,HWIO_GCC_QDSS_ETR_USB_CBCR_IN)
#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_QDSS_ETR_USB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                          0x100000
#define HWIO_GCC_QDSS_ETR_USB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                              0x14
#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_QDSS_ETR_USB_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_QDSS_STM_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c028)
#define HWIO_GCC_QDSS_STM_CBCR_RMSK                                                                0x80100007
#define HWIO_GCC_QDSS_STM_CBCR_IN          \
        in_dword(HWIO_GCC_QDSS_STM_CBCR_ADDR)
#define HWIO_GCC_QDSS_STM_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_STM_CBCR_ADDR, m)
#define HWIO_GCC_QDSS_STM_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_STM_CBCR_ADDR,v)
#define HWIO_GCC_QDSS_STM_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_STM_CBCR_ADDR,m,v,HWIO_GCC_QDSS_STM_CBCR_IN)
#define HWIO_GCC_QDSS_STM_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_QDSS_STM_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_QDSS_STM_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_QDSS_STM_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_QDSS_STM_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_QDSS_STM_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_QDSS_STM_CBCR_HW_CTL_BMSK                                                                0x2
#define HWIO_GCC_QDSS_STM_CBCR_HW_CTL_SHFT                                                                0x1
#define HWIO_GCC_QDSS_STM_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_QDSS_STM_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c02c)
#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_RMSK                                                         0x80100005
#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IN          \
        in_dword(HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR)
#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR, m)
#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR,v)
#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR,m,v,HWIO_GCC_QDSS_TRACECLKIN_CBCR_IN)
#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                       0x100000
#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                           0x14
#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ARES_SHFT                                                       0x2
#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_CLK_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_QDSS_TSCTR_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c030)
#define HWIO_GCC_QDSS_TSCTR_CBCR_RMSK                                                              0x80000005
#define HWIO_GCC_QDSS_TSCTR_CBCR_IN          \
        in_dword(HWIO_GCC_QDSS_TSCTR_CBCR_ADDR)
#define HWIO_GCC_QDSS_TSCTR_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_TSCTR_CBCR_ADDR, m)
#define HWIO_GCC_QDSS_TSCTR_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_TSCTR_CBCR_ADDR,v)
#define HWIO_GCC_QDSS_TSCTR_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_TSCTR_CBCR_ADDR,m,v,HWIO_GCC_QDSS_TSCTR_CBCR_IN)
#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_QDSS_TSCTR_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_QDSS_TRIG_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c034)
#define HWIO_GCC_QDSS_TRIG_CBCR_RMSK                                                               0x80100005
#define HWIO_GCC_QDSS_TRIG_CBCR_IN          \
        in_dword(HWIO_GCC_QDSS_TRIG_CBCR_ADDR)
#define HWIO_GCC_QDSS_TRIG_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_TRIG_CBCR_ADDR, m)
#define HWIO_GCC_QDSS_TRIG_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_TRIG_CBCR_ADDR,v)
#define HWIO_GCC_QDSS_TRIG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_TRIG_CBCR_ADDR,m,v,HWIO_GCC_QDSS_TRIG_CBCR_IN)
#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_QDSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                             0x100000
#define HWIO_GCC_QDSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                 0x14
#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ARES_SHFT                                                             0x2
#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_QDSS_TRIG_CBCR_CLK_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_QDSS_DAP_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c038)
#define HWIO_GCC_QDSS_DAP_CBCR_RMSK                                                                0x80000005
#define HWIO_GCC_QDSS_DAP_CBCR_IN          \
        in_dword(HWIO_GCC_QDSS_DAP_CBCR_ADDR)
#define HWIO_GCC_QDSS_DAP_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_DAP_CBCR_ADDR, m)
#define HWIO_GCC_QDSS_DAP_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_DAP_CBCR_ADDR,v)
#define HWIO_GCC_QDSS_DAP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_DAP_CBCR_ADDR,m,v,HWIO_GCC_QDSS_DAP_CBCR_IN)
#define HWIO_GCC_QDSS_DAP_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_QDSS_DAP_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_QDSS_DAP_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_APB_CBCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c03c)
#define HWIO_GCC_APB_CBCR_RMSK                                                                     0x80000005
#define HWIO_GCC_APB_CBCR_IN          \
        in_dword(HWIO_GCC_APB_CBCR_ADDR)
#define HWIO_GCC_APB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_APB_CBCR_ADDR, m)
#define HWIO_GCC_APB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_APB_CBCR_ADDR,v)
#define HWIO_GCC_APB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APB_CBCR_ADDR,m,v,HWIO_GCC_APB_CBCR_IN)
#define HWIO_GCC_APB_CBCR_CLK_OFF_BMSK                                                             0x80000000
#define HWIO_GCC_APB_CBCR_CLK_OFF_SHFT                                                                   0x1f
#define HWIO_GCC_APB_CBCR_CLK_ARES_BMSK                                                                   0x4
#define HWIO_GCC_APB_CBCR_CLK_ARES_SHFT                                                                   0x2
#define HWIO_GCC_APB_CBCR_CLK_ENABLE_BMSK                                                                 0x1
#define HWIO_GCC_APB_CBCR_CLK_ENABLE_SHFT                                                                 0x0

#define HWIO_GCC_COMPUTE_TRIG_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c040)
#define HWIO_GCC_COMPUTE_TRIG_CBCR_RMSK                                                            0x80100005
#define HWIO_GCC_COMPUTE_TRIG_CBCR_IN          \
        in_dword(HWIO_GCC_COMPUTE_TRIG_CBCR_ADDR)
#define HWIO_GCC_COMPUTE_TRIG_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_COMPUTE_TRIG_CBCR_ADDR, m)
#define HWIO_GCC_COMPUTE_TRIG_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_COMPUTE_TRIG_CBCR_ADDR,v)
#define HWIO_GCC_COMPUTE_TRIG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_COMPUTE_TRIG_CBCR_ADDR,m,v,HWIO_GCC_COMPUTE_TRIG_CBCR_IN)
#define HWIO_GCC_COMPUTE_TRIG_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_COMPUTE_TRIG_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_COMPUTE_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                          0x100000
#define HWIO_GCC_COMPUTE_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                              0x14
#define HWIO_GCC_COMPUTE_TRIG_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_COMPUTE_TRIG_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_COMPUTE_TRIG_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_COMPUTE_TRIG_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_QDSS_XO_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c044)
#define HWIO_GCC_QDSS_XO_CBCR_RMSK                                                                 0x80000005
#define HWIO_GCC_QDSS_XO_CBCR_IN          \
        in_dword(HWIO_GCC_QDSS_XO_CBCR_ADDR)
#define HWIO_GCC_QDSS_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_XO_CBCR_ADDR, m)
#define HWIO_GCC_QDSS_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_XO_CBCR_ADDR,v)
#define HWIO_GCC_QDSS_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_XO_CBCR_ADDR,m,v,HWIO_GCC_QDSS_XO_CBCR_IN)
#define HWIO_GCC_QDSS_XO_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_QDSS_XO_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_QDSS_XO_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_QDSS_XO_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_QDSS_XO_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_QDSS_XO_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c064)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c068)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c06c)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c070)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c074)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c078)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c07c)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c080)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c084)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c088)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c08c)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c090)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c094)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c098)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c09c)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c0a0)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c048)
#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_RMSK                                                          0x80000013
#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ADDR)
#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_ATB_A_CMD_RCGR_IN)
#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ROOT_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ROOT_OFF_SHFT                                                       0x1f
#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                 0x10
#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                  0x4
#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ROOT_EN_BMSK                                                         0x2
#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ROOT_EN_SHFT                                                         0x1
#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_UPDATE_BMSK                                                          0x1
#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_UPDATE_SHFT                                                          0x0

#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c04c)
#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_RMSK                                                            0x11071f
#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QDSS_ATB_A_CFG_RCGR_ADDR)
#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_ATB_A_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_ATB_A_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_ATB_A_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_ATB_A_CFG_RCGR_IN)
#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_HW_CLK_CONTROL_BMSK                                             0x100000
#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                 0x14
#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_RCGLITE_DISABLE_BMSK                                             0x10000
#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                0x10
#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_SEL_BMSK                                                       0x700
#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_SEL_SHFT                                                         0x8
#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_BMSK                                                        0x1f
#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_SRC_DIV_SHFT                                                         0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c190)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c194)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c198)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c19c)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c1a0)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c1a4)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c1a8)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c1ac)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c1b0)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c1b4)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c1b8)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c1bc)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c1c0)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c1c4)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c1c8)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c1cc)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c174)
#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_RMSK                                                          0x80000013
#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ADDR)
#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_ATB_B_CMD_RCGR_IN)
#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ROOT_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ROOT_OFF_SHFT                                                       0x1f
#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                 0x10
#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                  0x4
#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ROOT_EN_BMSK                                                         0x2
#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ROOT_EN_SHFT                                                         0x1
#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_UPDATE_BMSK                                                          0x1
#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_UPDATE_SHFT                                                          0x0

#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c178)
#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_RMSK                                                            0x11071f
#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QDSS_ATB_B_CFG_RCGR_ADDR)
#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_ATB_B_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_ATB_B_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_ATB_B_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_ATB_B_CFG_RCGR_IN)
#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_HW_CLK_CONTROL_BMSK                                             0x100000
#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                 0x14
#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_RCGLITE_DISABLE_BMSK                                             0x10000
#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                0x10
#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_SEL_BMSK                                                       0x700
#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_SEL_SHFT                                                         0x8
#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_BMSK                                                        0x1f
#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_SRC_DIV_SHFT                                                         0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2bc)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2c0)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2c4)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2c8)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2cc)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2d0)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2d4)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2d8)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2dc)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2e0)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2e4)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2e8)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2ec)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2f0)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2f4)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2f8)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2a0)
#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_RMSK                                                          0x80000013
#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ADDR)
#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_ATB_C_CMD_RCGR_IN)
#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ROOT_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ROOT_OFF_SHFT                                                       0x1f
#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                 0x10
#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                  0x4
#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ROOT_EN_BMSK                                                         0x2
#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ROOT_EN_SHFT                                                         0x1
#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_UPDATE_BMSK                                                          0x1
#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_UPDATE_SHFT                                                          0x0

#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c2a4)
#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_RMSK                                                            0x11071f
#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QDSS_ATB_C_CFG_RCGR_ADDR)
#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_ATB_C_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_ATB_C_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_ATB_C_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_ATB_C_CFG_RCGR_IN)
#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_HW_CLK_CONTROL_BMSK                                             0x100000
#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                 0x14
#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_RCGLITE_DISABLE_BMSK                                             0x10000
#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                0x10
#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_SEL_BMSK                                                       0x700
#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_SEL_SHFT                                                         0x8
#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_BMSK                                                        0x1f
#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_SRC_DIV_SHFT                                                         0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c3e8)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c3ec)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c3f0)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c3f4)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c3f8)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c3fc)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c400)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c404)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c408)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c40c)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c410)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c414)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c418)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c41c)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c420)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c424)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c3cc)
#define HWIO_GCC_QDSS_STM_CMD_RCGR_RMSK                                                            0x80000013
#define HWIO_GCC_QDSS_STM_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR)
#define HWIO_GCC_QDSS_STM_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QDSS_STM_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QDSS_STM_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_STM_CMD_RCGR_IN)
#define HWIO_GCC_QDSS_STM_CMD_RCGR_ROOT_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_QDSS_STM_CMD_RCGR_ROOT_OFF_SHFT                                                         0x1f
#define HWIO_GCC_QDSS_STM_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                   0x10
#define HWIO_GCC_QDSS_STM_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                    0x4
#define HWIO_GCC_QDSS_STM_CMD_RCGR_ROOT_EN_BMSK                                                           0x2
#define HWIO_GCC_QDSS_STM_CMD_RCGR_ROOT_EN_SHFT                                                           0x1
#define HWIO_GCC_QDSS_STM_CMD_RCGR_UPDATE_BMSK                                                            0x1
#define HWIO_GCC_QDSS_STM_CMD_RCGR_UPDATE_SHFT                                                            0x0

#define HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c3d0)
#define HWIO_GCC_QDSS_STM_CFG_RCGR_RMSK                                                              0x11071f
#define HWIO_GCC_QDSS_STM_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR)
#define HWIO_GCC_QDSS_STM_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QDSS_STM_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QDSS_STM_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_STM_CFG_RCGR_IN)
#define HWIO_GCC_QDSS_STM_CFG_RCGR_HW_CLK_CONTROL_BMSK                                               0x100000
#define HWIO_GCC_QDSS_STM_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                   0x14
#define HWIO_GCC_QDSS_STM_CFG_RCGR_RCGLITE_DISABLE_BMSK                                               0x10000
#define HWIO_GCC_QDSS_STM_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                  0x10
#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_BMSK                                                         0x700
#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_SEL_SHFT                                                           0x8
#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_BMSK                                                          0x1f
#define HWIO_GCC_QDSS_STM_CFG_RCGR_SRC_DIV_SHFT                                                           0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c514)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c518)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c51c)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c520)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c524)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c528)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c52c)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c530)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c534)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c538)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c53c)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_RMSK                                             0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_BMSK                                     0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_SEL_SHFT                                       0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_BMSK                                      0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_SRC_DIV_SHFT                                       0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c540)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_RMSK                                             0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_BMSK                                     0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_SEL_SHFT                                       0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_BMSK                                      0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_SRC_DIV_SHFT                                       0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c544)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_RMSK                                             0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_BMSK                                     0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_SEL_SHFT                                       0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_BMSK                                      0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_SRC_DIV_SHFT                                       0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c548)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_RMSK                                             0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_BMSK                                     0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_SEL_SHFT                                       0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_BMSK                                      0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_SRC_DIV_SHFT                                       0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c54c)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_RMSK                                             0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_BMSK                                     0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_SEL_SHFT                                       0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_BMSK                                      0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_SRC_DIV_SHFT                                       0x0

#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c550)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_RMSK                                             0x71f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_BMSK                                     0x700
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_SEL_SHFT                                       0x8
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_BMSK                                      0x1f
#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_SRC_DIV_SHFT                                       0x0

#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c4f8)
#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_RMSK                                                     0x80000013
#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR)
#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_IN)
#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ROOT_OFF_BMSK                                            0x80000000
#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ROOT_OFF_SHFT                                                  0x1f
#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                            0x10
#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                             0x4
#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ROOT_EN_BMSK                                                    0x2
#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ROOT_EN_SHFT                                                    0x1
#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_UPDATE_BMSK                                                     0x1
#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_UPDATE_SHFT                                                     0x0

#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c4fc)
#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_RMSK                                                       0x11071f
#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR)
#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_IN)
#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_HW_CLK_CONTROL_BMSK                                        0x100000
#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_HW_CLK_CONTROL_SHFT                                            0x14
#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_RCGLITE_DISABLE_BMSK                                        0x10000
#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_RCGLITE_DISABLE_SHFT                                           0x10
#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_BMSK                                                  0x700
#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_SEL_SHFT                                                    0x8
#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_BMSK                                                   0x1f
#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_SRC_DIV_SHFT                                                    0x0

#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c624)
#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_RMSK                                                      0x80000013
#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR)
#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_IN)
#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c628)
#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_RMSK                                                        0x11071f
#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR)
#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_IN)
#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_RCGLITE_DISABLE_BMSK                                         0x10000
#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_RCGLITE_DISABLE_SHFT                                            0x10
#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c658)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c65c)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c660)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c664)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c668)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c66c)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c670)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c674)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c678)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c67c)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c680)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c684)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c688)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c68c)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c690)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c694)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c63c)
#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_RMSK                                                           0x80000013
#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR)
#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR,m,v,HWIO_GCC_QDSS_TRIG_CMD_RCGR_IN)
#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ROOT_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ROOT_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                  0x10
#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                   0x4
#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ROOT_EN_BMSK                                                          0x2
#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ROOT_EN_SHFT                                                          0x1
#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_UPDATE_BMSK                                                           0x1
#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_UPDATE_SHFT                                                           0x0

#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000c640)
#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_RMSK                                                             0x11071f
#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR)
#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR,m,v,HWIO_GCC_QDSS_TRIG_CFG_RCGR_IN)
#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_HW_CLK_CONTROL_BMSK                                              0x100000
#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                  0x14
#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_RCGLITE_DISABLE_BMSK                                              0x10000
#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                 0x10
#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_BMSK                                                        0x700
#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_SEL_SHFT                                                          0x8
#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_BMSK                                                         0x1f
#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_SRC_DIV_SHFT                                                          0x0

#define HWIO_GCC_USB30_PRIM_BCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f000)
#define HWIO_GCC_USB30_PRIM_BCR_RMSK                                                                      0x1
#define HWIO_GCC_USB30_PRIM_BCR_IN          \
        in_dword(HWIO_GCC_USB30_PRIM_BCR_ADDR)
#define HWIO_GCC_USB30_PRIM_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_PRIM_BCR_ADDR, m)
#define HWIO_GCC_USB30_PRIM_BCR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_PRIM_BCR_ADDR,v)
#define HWIO_GCC_USB30_PRIM_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_PRIM_BCR_ADDR,m,v,HWIO_GCC_USB30_PRIM_BCR_IN)
#define HWIO_GCC_USB30_PRIM_BCR_BLK_ARES_BMSK                                                             0x1
#define HWIO_GCC_USB30_PRIM_BCR_BLK_ARES_SHFT                                                             0x0

#define HWIO_GCC_USB30_PRIM_GDSCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f004)
#define HWIO_GCC_USB30_PRIM_GDSCR_RMSK                                                             0xf8ffffff
#define HWIO_GCC_USB30_PRIM_GDSCR_IN          \
        in_dword(HWIO_GCC_USB30_PRIM_GDSCR_ADDR)
#define HWIO_GCC_USB30_PRIM_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_PRIM_GDSCR_ADDR, m)
#define HWIO_GCC_USB30_PRIM_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_PRIM_GDSCR_ADDR,v)
#define HWIO_GCC_USB30_PRIM_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_PRIM_GDSCR_ADDR,m,v,HWIO_GCC_USB30_PRIM_GDSCR_IN)
#define HWIO_GCC_USB30_PRIM_GDSCR_PWR_ON_BMSK                                                      0x80000000
#define HWIO_GCC_USB30_PRIM_GDSCR_PWR_ON_SHFT                                                            0x1f
#define HWIO_GCC_USB30_PRIM_GDSCR_GDSC_STATE_BMSK                                                  0x78000000
#define HWIO_GCC_USB30_PRIM_GDSCR_GDSC_STATE_SHFT                                                        0x1b
#define HWIO_GCC_USB30_PRIM_GDSCR_EN_REST_WAIT_BMSK                                                  0xf00000
#define HWIO_GCC_USB30_PRIM_GDSCR_EN_REST_WAIT_SHFT                                                      0x14
#define HWIO_GCC_USB30_PRIM_GDSCR_EN_FEW_WAIT_BMSK                                                    0xf0000
#define HWIO_GCC_USB30_PRIM_GDSCR_EN_FEW_WAIT_SHFT                                                       0x10
#define HWIO_GCC_USB30_PRIM_GDSCR_CLK_DIS_WAIT_BMSK                                                    0xf000
#define HWIO_GCC_USB30_PRIM_GDSCR_CLK_DIS_WAIT_SHFT                                                       0xc
#define HWIO_GCC_USB30_PRIM_GDSCR_RETAIN_FF_ENABLE_BMSK                                                 0x800
#define HWIO_GCC_USB30_PRIM_GDSCR_RETAIN_FF_ENABLE_SHFT                                                   0xb
#define HWIO_GCC_USB30_PRIM_GDSCR_RESTORE_BMSK                                                          0x400
#define HWIO_GCC_USB30_PRIM_GDSCR_RESTORE_SHFT                                                            0xa
#define HWIO_GCC_USB30_PRIM_GDSCR_SAVE_BMSK                                                             0x200
#define HWIO_GCC_USB30_PRIM_GDSCR_SAVE_SHFT                                                               0x9
#define HWIO_GCC_USB30_PRIM_GDSCR_RETAIN_BMSK                                                           0x100
#define HWIO_GCC_USB30_PRIM_GDSCR_RETAIN_SHFT                                                             0x8
#define HWIO_GCC_USB30_PRIM_GDSCR_EN_REST_BMSK                                                           0x80
#define HWIO_GCC_USB30_PRIM_GDSCR_EN_REST_SHFT                                                            0x7
#define HWIO_GCC_USB30_PRIM_GDSCR_EN_FEW_BMSK                                                            0x40
#define HWIO_GCC_USB30_PRIM_GDSCR_EN_FEW_SHFT                                                             0x6
#define HWIO_GCC_USB30_PRIM_GDSCR_CLAMP_IO_BMSK                                                          0x20
#define HWIO_GCC_USB30_PRIM_GDSCR_CLAMP_IO_SHFT                                                           0x5
#define HWIO_GCC_USB30_PRIM_GDSCR_CLK_DISABLE_BMSK                                                       0x10
#define HWIO_GCC_USB30_PRIM_GDSCR_CLK_DISABLE_SHFT                                                        0x4
#define HWIO_GCC_USB30_PRIM_GDSCR_PD_ARES_BMSK                                                            0x8
#define HWIO_GCC_USB30_PRIM_GDSCR_PD_ARES_SHFT                                                            0x3
#define HWIO_GCC_USB30_PRIM_GDSCR_SW_OVERRIDE_BMSK                                                        0x4
#define HWIO_GCC_USB30_PRIM_GDSCR_SW_OVERRIDE_SHFT                                                        0x2
#define HWIO_GCC_USB30_PRIM_GDSCR_HW_CONTROL_BMSK                                                         0x2
#define HWIO_GCC_USB30_PRIM_GDSCR_HW_CONTROL_SHFT                                                         0x1
#define HWIO_GCC_USB30_PRIM_GDSCR_SW_COLLAPSE_BMSK                                                        0x1
#define HWIO_GCC_USB30_PRIM_GDSCR_SW_COLLAPSE_SHFT                                                        0x0

#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f008)
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_RMSK                                                         0xffffffff
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_IN          \
        in_dword(HWIO_GCC_USB30_PRIM_CFG_GDSCR_ADDR)
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_PRIM_CFG_GDSCR_ADDR, m)
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_PRIM_CFG_GDSCR_ADDR,v)
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_PRIM_CFG_GDSCR_ADDR,m,v,HWIO_GCC_USB30_PRIM_CFG_GDSCR_IN)
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_SPARE_CTRL_IN_BMSK                                      0xf0000000
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_SPARE_CTRL_IN_SHFT                                            0x1c
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK                                      0xc000000
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT                                           0x1a
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK                                       0x2000000
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT                                            0x19
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PWR_UP_START_BMSK                                        0x1000000
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PWR_UP_START_SHFT                                             0x18
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK                                 0xf00000
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT                                     0x14
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                                    0x80000
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                                       0x13
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK                                        0x40000
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT                                           0x12
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK                                        0x20000
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT                                           0x11
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK                                     0x10000
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT                                        0x10
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                                    0x8000
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                                       0xf
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                                   0x7800
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                                      0xb
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK                                           0x400
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT                                             0xa
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                                    0x200
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                                      0x9
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                                    0x100
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                                      0x8
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                                        0x80
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                                         0x7
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                               0x60
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                                0x5
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                                         0x10
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                                          0x4
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                   0x8
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                   0x3
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                                 0x4
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                                 0x2
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                     0x2
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                     0x1
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                                  0x1
#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                                  0x0

#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f00c)
#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_RMSK                                                           0x1ffff
#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_IN          \
        in_dword(HWIO_GCC_USB30_PRIM_CFG2_GDSCR_ADDR)
#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_PRIM_CFG2_GDSCR_ADDR, m)
#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_PRIM_CFG2_GDSCR_ADDR,v)
#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_PRIM_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_USB30_PRIM_CFG2_GDSCR_IN)
#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK                                         0x10000
#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT                                            0x10
#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK                                             0xf000
#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT                                                0xc
#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                                      0xf00
#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                                        0x8
#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                                         0xf0
#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                                          0x4
#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                                           0xf
#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                                           0x0

#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f010)
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_RMSK                                                       0x80007ff5
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_IN          \
        in_dword(HWIO_GCC_USB30_PRIM_MASTER_CBCR_ADDR)
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_CBCR_ADDR, m)
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_PRIM_MASTER_CBCR_ADDR,v)
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MASTER_CBCR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MASTER_CBCR_IN)
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_CORE_ON_BMSK                                         0x4000
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_CORE_ON_SHFT                                            0xe
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                       0x2000
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                          0xd
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                      0x1000
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                         0xc
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_WAKEUP_BMSK                                                     0xf00
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_WAKEUP_SHFT                                                       0x8
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_SLEEP_BMSK                                                       0xf0
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_SLEEP_SHFT                                                        0x4
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f014)
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_RMSK                                                      0xfffff37e
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_IN          \
        in_dword(HWIO_GCC_USB30_PRIM_MASTER_SREGR_ADDR)
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_SREGR_ADDR, m)
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_PRIM_MASTER_SREGR_ADDR,v)
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MASTER_SREGR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MASTER_SREGR_IN)
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                            0xff000000
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                  0x18
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                               0xff0000
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                   0x10
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_RESERVE_BITS15_13_BMSK                                        0xe000
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_RESERVE_BITS15_13_SHFT                                           0xd
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                              0x1000
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                 0xc
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                  0x300
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                    0x8
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_FORCE_CLK_ON_BMSK                                               0x40
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_FORCE_CLK_ON_SHFT                                                0x6
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_RST_SEL_SLP_STG_BMSK                                         0x20
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_RST_SEL_SLP_STG_SHFT                                          0x5
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_RST_SLP_STG_BMSK                                             0x10
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_RST_SLP_STG_SHFT                                              0x4
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CTRL_PWR_DOWN_BMSK                                            0x8
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CTRL_PWR_DOWN_SHFT                                            0x3
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                       0x4
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                       0x2
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CLK_EN_SLP_STG_BMSK                                           0x2
#define HWIO_GCC_USB30_PRIM_MASTER_SREGR_SW_CLK_EN_SLP_STG_SHFT                                           0x1

#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f018)
#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_RMSK                                                        0x80000005
#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_IN          \
        in_dword(HWIO_GCC_USB30_PRIM_SLEEP_CBCR_ADDR)
#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_PRIM_SLEEP_CBCR_ADDR, m)
#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_PRIM_SLEEP_CBCR_ADDR,v)
#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_PRIM_SLEEP_CBCR_ADDR,m,v,HWIO_GCC_USB30_PRIM_SLEEP_CBCR_IN)
#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f01c)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_RMSK                                                    0x80000005
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_IN          \
        in_dword(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_ADDR)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_ADDR, m)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_ADDR,v)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_IN)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f020)
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_RMSK                                                   0x800000f3
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ADDR)
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ADDR, m)
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ADDR,v)
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_IN)
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ROOT_OFF_BMSK                                          0x80000000
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ROOT_OFF_SHFT                                                0x1f
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_DIRTY_D_BMSK                                                 0x80
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_DIRTY_D_SHFT                                                  0x7
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_DIRTY_N_BMSK                                                 0x40
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_DIRTY_N_SHFT                                                  0x6
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_DIRTY_M_BMSK                                                 0x20
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_DIRTY_M_SHFT                                                  0x5
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                          0x10
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                           0x4
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ROOT_EN_BMSK                                                  0x2
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ROOT_EN_SHFT                                                  0x1
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_UPDATE_BMSK                                                   0x1
#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_UPDATE_SHFT                                                   0x0

#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f024)
#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_RMSK                                                     0x10371f
#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_ADDR)
#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_ADDR, m)
#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_ADDR,v)
#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_IN)
#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_HW_CLK_CONTROL_BMSK                                      0x100000
#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_HW_CLK_CONTROL_SHFT                                          0x14
#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_MODE_BMSK                                                  0x3000
#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_MODE_SHFT                                                     0xc
#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_USB30_PRIM_MASTER_M_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f028)
#define HWIO_GCC_USB30_PRIM_MASTER_M_RMSK                                                                0xff
#define HWIO_GCC_USB30_PRIM_MASTER_M_IN          \
        in_dword(HWIO_GCC_USB30_PRIM_MASTER_M_ADDR)
#define HWIO_GCC_USB30_PRIM_MASTER_M_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_M_ADDR, m)
#define HWIO_GCC_USB30_PRIM_MASTER_M_OUT(v)      \
        out_dword(HWIO_GCC_USB30_PRIM_MASTER_M_ADDR,v)
#define HWIO_GCC_USB30_PRIM_MASTER_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MASTER_M_ADDR,m,v,HWIO_GCC_USB30_PRIM_MASTER_M_IN)
#define HWIO_GCC_USB30_PRIM_MASTER_M_M_BMSK                                                              0xff
#define HWIO_GCC_USB30_PRIM_MASTER_M_M_SHFT                                                               0x0

#define HWIO_GCC_USB30_PRIM_MASTER_N_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f02c)
#define HWIO_GCC_USB30_PRIM_MASTER_N_RMSK                                                                0xff
#define HWIO_GCC_USB30_PRIM_MASTER_N_IN          \
        in_dword(HWIO_GCC_USB30_PRIM_MASTER_N_ADDR)
#define HWIO_GCC_USB30_PRIM_MASTER_N_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_N_ADDR, m)
#define HWIO_GCC_USB30_PRIM_MASTER_N_OUT(v)      \
        out_dword(HWIO_GCC_USB30_PRIM_MASTER_N_ADDR,v)
#define HWIO_GCC_USB30_PRIM_MASTER_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MASTER_N_ADDR,m,v,HWIO_GCC_USB30_PRIM_MASTER_N_IN)
#define HWIO_GCC_USB30_PRIM_MASTER_N_NOT_N_MINUS_M_BMSK                                                  0xff
#define HWIO_GCC_USB30_PRIM_MASTER_N_NOT_N_MINUS_M_SHFT                                                   0x0

#define HWIO_GCC_USB30_PRIM_MASTER_D_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f030)
#define HWIO_GCC_USB30_PRIM_MASTER_D_RMSK                                                                0xff
#define HWIO_GCC_USB30_PRIM_MASTER_D_IN          \
        in_dword(HWIO_GCC_USB30_PRIM_MASTER_D_ADDR)
#define HWIO_GCC_USB30_PRIM_MASTER_D_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_PRIM_MASTER_D_ADDR, m)
#define HWIO_GCC_USB30_PRIM_MASTER_D_OUT(v)      \
        out_dword(HWIO_GCC_USB30_PRIM_MASTER_D_ADDR,v)
#define HWIO_GCC_USB30_PRIM_MASTER_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MASTER_D_ADDR,m,v,HWIO_GCC_USB30_PRIM_MASTER_D_IN)
#define HWIO_GCC_USB30_PRIM_MASTER_D_NOT_2D_BMSK                                                         0xff
#define HWIO_GCC_USB30_PRIM_MASTER_D_NOT_2D_SHFT                                                          0x0

#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f038)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_RMSK                                                0x80000013
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ADDR)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ADDR, m)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ADDR,v)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_IN)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ROOT_OFF_BMSK                                       0x80000000
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ROOT_OFF_SHFT                                             0x1f
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                       0x10
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                        0x4
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ROOT_EN_BMSK                                               0x2
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ROOT_EN_SHFT                                               0x1
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_UPDATE_BMSK                                                0x1
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_UPDATE_SHFT                                                0x0

#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f03c)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_RMSK                                                  0x11071f
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_ADDR)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_ADDR, m)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_ADDR,v)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_IN)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_HW_CLK_CONTROL_BMSK                                   0x100000
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_HW_CLK_CONTROL_SHFT                                       0x14
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_RCGLITE_DISABLE_BMSK                                   0x10000
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_RCGLITE_DISABLE_SHFT                                      0x10
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_SEL_BMSK                                             0x700
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_SEL_SHFT                                               0x8
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_BMSK                                              0x1f
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_SRC_DIV_SHFT                                               0x0

#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f050)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_RMSK                                                  0x3
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_IN          \
        in_dword(HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_ADDR)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_ADDR, m)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_ADDR,v)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_ADDR,m,v,HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_IN)
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_CLK_DIV_BMSK                                          0x3
#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_CLK_DIV_SHFT                                          0x0

#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f054)
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_RMSK                                                       0x80000005
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_IN          \
        in_dword(HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_ADDR)
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_ADDR, m)
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_ADDR,v)
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_ADDR,m,v,HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_IN)
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f058)
#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_RMSK                                                   0x80000005
#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_IN          \
        in_dword(HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_ADDR)
#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_ADDR, m)
#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_ADDR,v)
#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_ADDR,m,v,HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_IN)
#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_CLK_ENABLE_SHFT                                               0x0

#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f05c)
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_RMSK                                                      0x80000005
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_IN          \
        in_dword(HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_ADDR)
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_ADDR, m)
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_ADDR,v)
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_ADDR,m,v,HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_IN)
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_CLK_ENABLE_SHFT                                                  0x0

#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f064)
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_RMSK                                                   0x80000013
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ADDR)
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ADDR, m)
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ADDR,v)
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ADDR,m,v,HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_IN)
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ROOT_OFF_BMSK                                          0x80000000
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ROOT_OFF_SHFT                                                0x1f
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                          0x10
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                           0x4
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ROOT_EN_BMSK                                                  0x2
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ROOT_EN_SHFT                                                  0x1
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_UPDATE_BMSK                                                   0x1
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_UPDATE_SHFT                                                   0x0

#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f068)
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_RMSK                                                     0x11071f
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_ADDR)
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_ADDR, m)
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_ADDR,v)
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_ADDR,m,v,HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_IN)
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_BMSK                                      0x100000
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_SHFT                                          0x14
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_RCGLITE_DISABLE_BMSK                                      0x10000
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_RCGLITE_DISABLE_SHFT                                         0x10
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_USB30_SEC_BCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00010000)
#define HWIO_GCC_USB30_SEC_BCR_RMSK                                                                       0x1
#define HWIO_GCC_USB30_SEC_BCR_IN          \
        in_dword(HWIO_GCC_USB30_SEC_BCR_ADDR)
#define HWIO_GCC_USB30_SEC_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_SEC_BCR_ADDR, m)
#define HWIO_GCC_USB30_SEC_BCR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_SEC_BCR_ADDR,v)
#define HWIO_GCC_USB30_SEC_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_SEC_BCR_ADDR,m,v,HWIO_GCC_USB30_SEC_BCR_IN)
#define HWIO_GCC_USB30_SEC_BCR_BLK_ARES_BMSK                                                              0x1
#define HWIO_GCC_USB30_SEC_BCR_BLK_ARES_SHFT                                                              0x0

#define HWIO_GCC_USB30_SEC_GDSCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00010004)
#define HWIO_GCC_USB30_SEC_GDSCR_RMSK                                                              0xf8ffffff
#define HWIO_GCC_USB30_SEC_GDSCR_IN          \
        in_dword(HWIO_GCC_USB30_SEC_GDSCR_ADDR)
#define HWIO_GCC_USB30_SEC_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_SEC_GDSCR_ADDR, m)
#define HWIO_GCC_USB30_SEC_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_SEC_GDSCR_ADDR,v)
#define HWIO_GCC_USB30_SEC_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_SEC_GDSCR_ADDR,m,v,HWIO_GCC_USB30_SEC_GDSCR_IN)
#define HWIO_GCC_USB30_SEC_GDSCR_PWR_ON_BMSK                                                       0x80000000
#define HWIO_GCC_USB30_SEC_GDSCR_PWR_ON_SHFT                                                             0x1f
#define HWIO_GCC_USB30_SEC_GDSCR_GDSC_STATE_BMSK                                                   0x78000000
#define HWIO_GCC_USB30_SEC_GDSCR_GDSC_STATE_SHFT                                                         0x1b
#define HWIO_GCC_USB30_SEC_GDSCR_EN_REST_WAIT_BMSK                                                   0xf00000
#define HWIO_GCC_USB30_SEC_GDSCR_EN_REST_WAIT_SHFT                                                       0x14
#define HWIO_GCC_USB30_SEC_GDSCR_EN_FEW_WAIT_BMSK                                                     0xf0000
#define HWIO_GCC_USB30_SEC_GDSCR_EN_FEW_WAIT_SHFT                                                        0x10
#define HWIO_GCC_USB30_SEC_GDSCR_CLK_DIS_WAIT_BMSK                                                     0xf000
#define HWIO_GCC_USB30_SEC_GDSCR_CLK_DIS_WAIT_SHFT                                                        0xc
#define HWIO_GCC_USB30_SEC_GDSCR_RETAIN_FF_ENABLE_BMSK                                                  0x800
#define HWIO_GCC_USB30_SEC_GDSCR_RETAIN_FF_ENABLE_SHFT                                                    0xb
#define HWIO_GCC_USB30_SEC_GDSCR_RESTORE_BMSK                                                           0x400
#define HWIO_GCC_USB30_SEC_GDSCR_RESTORE_SHFT                                                             0xa
#define HWIO_GCC_USB30_SEC_GDSCR_SAVE_BMSK                                                              0x200
#define HWIO_GCC_USB30_SEC_GDSCR_SAVE_SHFT                                                                0x9
#define HWIO_GCC_USB30_SEC_GDSCR_RETAIN_BMSK                                                            0x100
#define HWIO_GCC_USB30_SEC_GDSCR_RETAIN_SHFT                                                              0x8
#define HWIO_GCC_USB30_SEC_GDSCR_EN_REST_BMSK                                                            0x80
#define HWIO_GCC_USB30_SEC_GDSCR_EN_REST_SHFT                                                             0x7
#define HWIO_GCC_USB30_SEC_GDSCR_EN_FEW_BMSK                                                             0x40
#define HWIO_GCC_USB30_SEC_GDSCR_EN_FEW_SHFT                                                              0x6
#define HWIO_GCC_USB30_SEC_GDSCR_CLAMP_IO_BMSK                                                           0x20
#define HWIO_GCC_USB30_SEC_GDSCR_CLAMP_IO_SHFT                                                            0x5
#define HWIO_GCC_USB30_SEC_GDSCR_CLK_DISABLE_BMSK                                                        0x10
#define HWIO_GCC_USB30_SEC_GDSCR_CLK_DISABLE_SHFT                                                         0x4
#define HWIO_GCC_USB30_SEC_GDSCR_PD_ARES_BMSK                                                             0x8
#define HWIO_GCC_USB30_SEC_GDSCR_PD_ARES_SHFT                                                             0x3
#define HWIO_GCC_USB30_SEC_GDSCR_SW_OVERRIDE_BMSK                                                         0x4
#define HWIO_GCC_USB30_SEC_GDSCR_SW_OVERRIDE_SHFT                                                         0x2
#define HWIO_GCC_USB30_SEC_GDSCR_HW_CONTROL_BMSK                                                          0x2
#define HWIO_GCC_USB30_SEC_GDSCR_HW_CONTROL_SHFT                                                          0x1
#define HWIO_GCC_USB30_SEC_GDSCR_SW_COLLAPSE_BMSK                                                         0x1
#define HWIO_GCC_USB30_SEC_GDSCR_SW_COLLAPSE_SHFT                                                         0x0

#define HWIO_GCC_USB30_SEC_CFG_GDSCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00010008)
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_RMSK                                                          0xffffffff
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_IN          \
        in_dword(HWIO_GCC_USB30_SEC_CFG_GDSCR_ADDR)
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_SEC_CFG_GDSCR_ADDR, m)
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_SEC_CFG_GDSCR_ADDR,v)
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_SEC_CFG_GDSCR_ADDR,m,v,HWIO_GCC_USB30_SEC_CFG_GDSCR_IN)
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_SPARE_CTRL_IN_BMSK                                       0xf0000000
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_SPARE_CTRL_IN_SHFT                                             0x1c
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK                                       0xc000000
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT                                            0x1a
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK                                        0x2000000
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT                                             0x19
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_PWR_UP_START_BMSK                                         0x1000000
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_PWR_UP_START_SHFT                                              0x18
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK                                  0xf00000
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT                                      0x14
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                                     0x80000
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                                        0x13
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK                                         0x40000
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT                                            0x12
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK                                         0x20000
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT                                            0x11
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK                                      0x10000
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT                                         0x10
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                                     0x8000
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                                        0xf
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                                    0x7800
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                                       0xb
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK                                            0x400
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT                                              0xa
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                                     0x200
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                                       0x9
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                                     0x100
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                                       0x8
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                                         0x80
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                                          0x7
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                                0x60
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                                 0x5
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                                          0x10
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                                           0x4
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                    0x8
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                    0x3
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                                  0x4
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                                  0x2
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                      0x2
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                      0x1
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                                   0x1
#define HWIO_GCC_USB30_SEC_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                                   0x0

#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0001000c)
#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_RMSK                                                            0x1ffff
#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_IN          \
        in_dword(HWIO_GCC_USB30_SEC_CFG2_GDSCR_ADDR)
#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_SEC_CFG2_GDSCR_ADDR, m)
#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_SEC_CFG2_GDSCR_ADDR,v)
#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_SEC_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_USB30_SEC_CFG2_GDSCR_IN)
#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK                                          0x10000
#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT                                             0x10
#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK                                              0xf000
#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT                                                 0xc
#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                                       0xf00
#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                                         0x8
#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                                          0xf0
#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                                           0x4
#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                                            0xf
#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                                            0x0

#define HWIO_GCC_USB30_SEC_MASTER_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00010010)
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_RMSK                                                        0x80007ff5
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_IN          \
        in_dword(HWIO_GCC_USB30_SEC_MASTER_CBCR_ADDR)
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_SEC_MASTER_CBCR_ADDR, m)
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_SEC_MASTER_CBCR_ADDR,v)
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_SEC_MASTER_CBCR_ADDR,m,v,HWIO_GCC_USB30_SEC_MASTER_CBCR_IN)
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_FORCE_MEM_CORE_ON_BMSK                                          0x4000
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_FORCE_MEM_CORE_ON_SHFT                                             0xe
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                        0x2000
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                           0xd
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                       0x1000
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                          0xc
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_WAKEUP_BMSK                                                      0xf00
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_WAKEUP_SHFT                                                        0x8
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_SLEEP_BMSK                                                        0xf0
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_SLEEP_SHFT                                                         0x4
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_USB30_SEC_MASTER_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_USB30_SEC_MASTER_SREGR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00010014)
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_RMSK                                                       0xfffff37e
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_IN          \
        in_dword(HWIO_GCC_USB30_SEC_MASTER_SREGR_ADDR)
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_SEC_MASTER_SREGR_ADDR, m)
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_SEC_MASTER_SREGR_ADDR,v)
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_SEC_MASTER_SREGR_ADDR,m,v,HWIO_GCC_USB30_SEC_MASTER_SREGR_IN)
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                             0xff000000
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                   0x18
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                0xff0000
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                    0x10
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_RESERVE_BITS15_13_BMSK                                         0xe000
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_RESERVE_BITS15_13_SHFT                                            0xd
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                               0x1000
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                  0xc
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                   0x300
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                     0x8
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_FORCE_CLK_ON_BMSK                                                0x40
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_FORCE_CLK_ON_SHFT                                                 0x6
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SW_RST_SEL_SLP_STG_BMSK                                          0x20
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SW_RST_SEL_SLP_STG_SHFT                                           0x5
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SW_RST_SLP_STG_BMSK                                              0x10
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SW_RST_SLP_STG_SHFT                                               0x4
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SW_CTRL_PWR_DOWN_BMSK                                             0x8
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SW_CTRL_PWR_DOWN_SHFT                                             0x3
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                        0x4
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                        0x2
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SW_CLK_EN_SLP_STG_BMSK                                            0x2
#define HWIO_GCC_USB30_SEC_MASTER_SREGR_SW_CLK_EN_SLP_STG_SHFT                                            0x1

#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00010018)
#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_RMSK                                                         0x80000005
#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_IN          \
        in_dword(HWIO_GCC_USB30_SEC_SLEEP_CBCR_ADDR)
#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_SEC_SLEEP_CBCR_ADDR, m)
#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_SEC_SLEEP_CBCR_ADDR,v)
#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_SEC_SLEEP_CBCR_ADDR,m,v,HWIO_GCC_USB30_SEC_SLEEP_CBCR_IN)
#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_CLK_ARES_SHFT                                                       0x2
#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_CLK_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0001001c)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_RMSK                                                     0x80000005
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_IN          \
        in_dword(HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_ADDR)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_ADDR, m)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_ADDR,v)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_ADDR,m,v,HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_IN)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00010020)
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_RMSK                                                    0x800000f3
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_ADDR)
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_ADDR, m)
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_ADDR,v)
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_ADDR,m,v,HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_IN)
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_ROOT_OFF_BMSK                                           0x80000000
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_ROOT_OFF_SHFT                                                 0x1f
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_DIRTY_D_BMSK                                                  0x80
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_DIRTY_D_SHFT                                                   0x7
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_DIRTY_N_BMSK                                                  0x40
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_DIRTY_N_SHFT                                                   0x6
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_DIRTY_M_BMSK                                                  0x20
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_DIRTY_M_SHFT                                                   0x5
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                           0x10
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                            0x4
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_ROOT_EN_BMSK                                                   0x2
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_ROOT_EN_SHFT                                                   0x1
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_UPDATE_BMSK                                                    0x1
#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_UPDATE_SHFT                                                    0x0

#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00010024)
#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_RMSK                                                      0x10371f
#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_ADDR)
#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_ADDR, m)
#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_ADDR,v)
#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_ADDR,m,v,HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_IN)
#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_HW_CLK_CONTROL_BMSK                                       0x100000
#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_HW_CLK_CONTROL_SHFT                                           0x14
#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_MODE_BMSK                                                   0x3000
#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_MODE_SHFT                                                      0xc
#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_SRC_SEL_BMSK                                                 0x700
#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_SRC_SEL_SHFT                                                   0x8
#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_SRC_DIV_SHFT                                                   0x0

#define HWIO_GCC_USB30_SEC_MASTER_M_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00010028)
#define HWIO_GCC_USB30_SEC_MASTER_M_RMSK                                                                 0xff
#define HWIO_GCC_USB30_SEC_MASTER_M_IN          \
        in_dword(HWIO_GCC_USB30_SEC_MASTER_M_ADDR)
#define HWIO_GCC_USB30_SEC_MASTER_M_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_SEC_MASTER_M_ADDR, m)
#define HWIO_GCC_USB30_SEC_MASTER_M_OUT(v)      \
        out_dword(HWIO_GCC_USB30_SEC_MASTER_M_ADDR,v)
#define HWIO_GCC_USB30_SEC_MASTER_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_SEC_MASTER_M_ADDR,m,v,HWIO_GCC_USB30_SEC_MASTER_M_IN)
#define HWIO_GCC_USB30_SEC_MASTER_M_M_BMSK                                                               0xff
#define HWIO_GCC_USB30_SEC_MASTER_M_M_SHFT                                                                0x0

#define HWIO_GCC_USB30_SEC_MASTER_N_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0001002c)
#define HWIO_GCC_USB30_SEC_MASTER_N_RMSK                                                                 0xff
#define HWIO_GCC_USB30_SEC_MASTER_N_IN          \
        in_dword(HWIO_GCC_USB30_SEC_MASTER_N_ADDR)
#define HWIO_GCC_USB30_SEC_MASTER_N_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_SEC_MASTER_N_ADDR, m)
#define HWIO_GCC_USB30_SEC_MASTER_N_OUT(v)      \
        out_dword(HWIO_GCC_USB30_SEC_MASTER_N_ADDR,v)
#define HWIO_GCC_USB30_SEC_MASTER_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_SEC_MASTER_N_ADDR,m,v,HWIO_GCC_USB30_SEC_MASTER_N_IN)
#define HWIO_GCC_USB30_SEC_MASTER_N_NOT_N_MINUS_M_BMSK                                                   0xff
#define HWIO_GCC_USB30_SEC_MASTER_N_NOT_N_MINUS_M_SHFT                                                    0x0

#define HWIO_GCC_USB30_SEC_MASTER_D_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00010030)
#define HWIO_GCC_USB30_SEC_MASTER_D_RMSK                                                                 0xff
#define HWIO_GCC_USB30_SEC_MASTER_D_IN          \
        in_dword(HWIO_GCC_USB30_SEC_MASTER_D_ADDR)
#define HWIO_GCC_USB30_SEC_MASTER_D_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_SEC_MASTER_D_ADDR, m)
#define HWIO_GCC_USB30_SEC_MASTER_D_OUT(v)      \
        out_dword(HWIO_GCC_USB30_SEC_MASTER_D_ADDR,v)
#define HWIO_GCC_USB30_SEC_MASTER_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_SEC_MASTER_D_ADDR,m,v,HWIO_GCC_USB30_SEC_MASTER_D_IN)
#define HWIO_GCC_USB30_SEC_MASTER_D_NOT_2D_BMSK                                                          0xff
#define HWIO_GCC_USB30_SEC_MASTER_D_NOT_2D_SHFT                                                           0x0

#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00010038)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_RMSK                                                 0x80000013
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_ADDR)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_ADDR, m)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_ADDR,v)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_ADDR,m,v,HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_IN)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_ROOT_OFF_BMSK                                        0x80000000
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_ROOT_OFF_SHFT                                              0x1f
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                        0x10
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                         0x4
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_ROOT_EN_BMSK                                                0x2
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_ROOT_EN_SHFT                                                0x1
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_UPDATE_BMSK                                                 0x1
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_UPDATE_SHFT                                                 0x0

#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0001003c)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_RMSK                                                   0x11071f
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_ADDR)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_ADDR, m)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_ADDR,v)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_ADDR,m,v,HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_IN)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_HW_CLK_CONTROL_BMSK                                    0x100000
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_HW_CLK_CONTROL_SHFT                                        0x14
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_RCGLITE_DISABLE_BMSK                                    0x10000
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_RCGLITE_DISABLE_SHFT                                       0x10
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00010050)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_RMSK                                                   0x3
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_IN          \
        in_dword(HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_ADDR)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_ADDR, m)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_ADDR,v)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_ADDR,m,v,HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_IN)
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_CLK_DIV_BMSK                                           0x3
#define HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_CLK_DIV_SHFT                                           0x0

#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00010054)
#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_RMSK                                                        0x80000005
#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_IN          \
        in_dword(HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_ADDR)
#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_ADDR, m)
#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_ADDR,v)
#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_ADDR,m,v,HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_IN)
#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00010058)
#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_RMSK                                                    0x80000005
#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_IN          \
        in_dword(HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_ADDR)
#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_ADDR, m)
#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_ADDR,v)
#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_ADDR,m,v,HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_IN)
#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0001005c)
#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_RMSK                                                       0x80000005
#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_IN          \
        in_dword(HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_ADDR)
#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_ADDR, m)
#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_ADDR,v)
#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_ADDR,m,v,HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_IN)
#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00010064)
#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_RMSK                                                    0x80000013
#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_ADDR)
#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_ADDR, m)
#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_ADDR,v)
#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_ADDR,m,v,HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_IN)
#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_ROOT_OFF_BMSK                                           0x80000000
#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_ROOT_OFF_SHFT                                                 0x1f
#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                           0x10
#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                            0x4
#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_ROOT_EN_BMSK                                                   0x2
#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_ROOT_EN_SHFT                                                   0x1
#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_UPDATE_BMSK                                                    0x1
#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_UPDATE_SHFT                                                    0x0

#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00010068)
#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_RMSK                                                      0x11071f
#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_ADDR)
#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_ADDR, m)
#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_ADDR,v)
#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_ADDR,m,v,HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_IN)
#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_BMSK                                       0x100000
#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_SHFT                                           0x14
#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_RCGLITE_DISABLE_BMSK                                       0x10000
#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_RCGLITE_DISABLE_SHFT                                          0x10
#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_SRC_SEL_BMSK                                                 0x700
#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_SRC_SEL_SHFT                                                   0x8
#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_SRC_DIV_SHFT                                                   0x0

#define HWIO_GCC_USB3_PHY_PRIM_BCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00050000)
#define HWIO_GCC_USB3_PHY_PRIM_BCR_RMSK                                                                   0x1
#define HWIO_GCC_USB3_PHY_PRIM_BCR_IN          \
        in_dword(HWIO_GCC_USB3_PHY_PRIM_BCR_ADDR)
#define HWIO_GCC_USB3_PHY_PRIM_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_PHY_PRIM_BCR_ADDR, m)
#define HWIO_GCC_USB3_PHY_PRIM_BCR_OUT(v)      \
        out_dword(HWIO_GCC_USB3_PHY_PRIM_BCR_ADDR,v)
#define HWIO_GCC_USB3_PHY_PRIM_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_PHY_PRIM_BCR_ADDR,m,v,HWIO_GCC_USB3_PHY_PRIM_BCR_IN)
#define HWIO_GCC_USB3_PHY_PRIM_BCR_BLK_ARES_BMSK                                                          0x1
#define HWIO_GCC_USB3_PHY_PRIM_BCR_BLK_ARES_SHFT                                                          0x0

#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00050004)
#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_RMSK                                                                0x1
#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_IN          \
        in_dword(HWIO_GCC_USB3PHY_PHY_PRIM_BCR_ADDR)
#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3PHY_PHY_PRIM_BCR_ADDR, m)
#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_OUT(v)      \
        out_dword(HWIO_GCC_USB3PHY_PHY_PRIM_BCR_ADDR,v)
#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3PHY_PHY_PRIM_BCR_ADDR,m,v,HWIO_GCC_USB3PHY_PHY_PRIM_BCR_IN)
#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_BLK_ARES_BMSK                                                       0x1
#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_BLK_ARES_SHFT                                                       0x0

#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00050008)
#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_RMSK                                                                0x1
#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_IN          \
        in_dword(HWIO_GCC_USB3_DP_PHY_PRIM_BCR_ADDR)
#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_DP_PHY_PRIM_BCR_ADDR, m)
#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_OUT(v)      \
        out_dword(HWIO_GCC_USB3_DP_PHY_PRIM_BCR_ADDR,v)
#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_DP_PHY_PRIM_BCR_ADDR,m,v,HWIO_GCC_USB3_DP_PHY_PRIM_BCR_IN)
#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_BLK_ARES_BMSK                                                       0x1
#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_BLK_ARES_SHFT                                                       0x0

#define HWIO_GCC_USB3_PHY_SEC_BCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0005000c)
#define HWIO_GCC_USB3_PHY_SEC_BCR_RMSK                                                                    0x1
#define HWIO_GCC_USB3_PHY_SEC_BCR_IN          \
        in_dword(HWIO_GCC_USB3_PHY_SEC_BCR_ADDR)
#define HWIO_GCC_USB3_PHY_SEC_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_PHY_SEC_BCR_ADDR, m)
#define HWIO_GCC_USB3_PHY_SEC_BCR_OUT(v)      \
        out_dword(HWIO_GCC_USB3_PHY_SEC_BCR_ADDR,v)
#define HWIO_GCC_USB3_PHY_SEC_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_PHY_SEC_BCR_ADDR,m,v,HWIO_GCC_USB3_PHY_SEC_BCR_IN)
#define HWIO_GCC_USB3_PHY_SEC_BCR_BLK_ARES_BMSK                                                           0x1
#define HWIO_GCC_USB3_PHY_SEC_BCR_BLK_ARES_SHFT                                                           0x0

#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00050010)
#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_RMSK                                                                 0x1
#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_IN          \
        in_dword(HWIO_GCC_USB3PHY_PHY_SEC_BCR_ADDR)
#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3PHY_PHY_SEC_BCR_ADDR, m)
#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_OUT(v)      \
        out_dword(HWIO_GCC_USB3PHY_PHY_SEC_BCR_ADDR,v)
#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3PHY_PHY_SEC_BCR_ADDR,m,v,HWIO_GCC_USB3PHY_PHY_SEC_BCR_IN)
#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_BLK_ARES_BMSK                                                        0x1
#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_BLK_ARES_SHFT                                                        0x0

#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00050014)
#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_RMSK                                                                 0x1
#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_IN          \
        in_dword(HWIO_GCC_USB3_DP_PHY_SEC_BCR_ADDR)
#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_DP_PHY_SEC_BCR_ADDR, m)
#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_OUT(v)      \
        out_dword(HWIO_GCC_USB3_DP_PHY_SEC_BCR_ADDR,v)
#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_DP_PHY_SEC_BCR_ADDR,m,v,HWIO_GCC_USB3_DP_PHY_SEC_BCR_IN)
#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_BLK_ARES_BMSK                                                        0x1
#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_BLK_ARES_SHFT                                                        0x0

#define HWIO_GCC_QUSB2PHY_PRIM_BCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00012000)
#define HWIO_GCC_QUSB2PHY_PRIM_BCR_RMSK                                                                   0x1
#define HWIO_GCC_QUSB2PHY_PRIM_BCR_IN          \
        in_dword(HWIO_GCC_QUSB2PHY_PRIM_BCR_ADDR)
#define HWIO_GCC_QUSB2PHY_PRIM_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUSB2PHY_PRIM_BCR_ADDR, m)
#define HWIO_GCC_QUSB2PHY_PRIM_BCR_OUT(v)      \
        out_dword(HWIO_GCC_QUSB2PHY_PRIM_BCR_ADDR,v)
#define HWIO_GCC_QUSB2PHY_PRIM_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUSB2PHY_PRIM_BCR_ADDR,m,v,HWIO_GCC_QUSB2PHY_PRIM_BCR_IN)
#define HWIO_GCC_QUSB2PHY_PRIM_BCR_BLK_ARES_BMSK                                                          0x1
#define HWIO_GCC_QUSB2PHY_PRIM_BCR_BLK_ARES_SHFT                                                          0x0

#define HWIO_GCC_QUSB2PHY_SEC_BCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00012004)
#define HWIO_GCC_QUSB2PHY_SEC_BCR_RMSK                                                                    0x1
#define HWIO_GCC_QUSB2PHY_SEC_BCR_IN          \
        in_dword(HWIO_GCC_QUSB2PHY_SEC_BCR_ADDR)
#define HWIO_GCC_QUSB2PHY_SEC_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUSB2PHY_SEC_BCR_ADDR, m)
#define HWIO_GCC_QUSB2PHY_SEC_BCR_OUT(v)      \
        out_dword(HWIO_GCC_QUSB2PHY_SEC_BCR_ADDR,v)
#define HWIO_GCC_QUSB2PHY_SEC_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUSB2PHY_SEC_BCR_ADDR,m,v,HWIO_GCC_QUSB2PHY_SEC_BCR_IN)
#define HWIO_GCC_QUSB2PHY_SEC_BCR_BLK_ARES_BMSK                                                           0x1
#define HWIO_GCC_QUSB2PHY_SEC_BCR_BLK_ARES_SHFT                                                           0x0

#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0006a000)
#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_RMSK                                                             0x1
#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_IN          \
        in_dword(HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR)
#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR, m)
#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_OUT(v)      \
        out_dword(HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR,v)
#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR,m,v,HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_IN)
#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_BLK_ARES_BMSK                                                    0x1
#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_BLK_ARES_SHFT                                                    0x0

#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0006a004)
#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_RMSK                                                           0x80100007
#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_IN          \
        in_dword(HWIO_GCC_AHB2PHY_SOUTH_CBCR_ADDR)
#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AHB2PHY_SOUTH_CBCR_ADDR, m)
#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AHB2PHY_SOUTH_CBCR_ADDR,v)
#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AHB2PHY_SOUTH_CBCR_ADDR,m,v,HWIO_GCC_AHB2PHY_SOUTH_CBCR_IN)
#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_HW_CTL_BMSK                                                           0x2
#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_HW_CTL_SHFT                                                           0x1
#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_SDCC2_BCR_ADDR                                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00014000)
#define HWIO_GCC_SDCC2_BCR_RMSK                                                                           0x1
#define HWIO_GCC_SDCC2_BCR_IN          \
        in_dword(HWIO_GCC_SDCC2_BCR_ADDR)
#define HWIO_GCC_SDCC2_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SDCC2_BCR_ADDR, m)
#define HWIO_GCC_SDCC2_BCR_OUT(v)      \
        out_dword(HWIO_GCC_SDCC2_BCR_ADDR,v)
#define HWIO_GCC_SDCC2_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SDCC2_BCR_ADDR,m,v,HWIO_GCC_SDCC2_BCR_IN)
#define HWIO_GCC_SDCC2_BCR_BLK_ARES_BMSK                                                                  0x1
#define HWIO_GCC_SDCC2_BCR_BLK_ARES_SHFT                                                                  0x0

#define HWIO_GCC_SDCC2_APPS_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00014004)
#define HWIO_GCC_SDCC2_APPS_CBCR_RMSK                                                              0x80007ff5
#define HWIO_GCC_SDCC2_APPS_CBCR_IN          \
        in_dword(HWIO_GCC_SDCC2_APPS_CBCR_ADDR)
#define HWIO_GCC_SDCC2_APPS_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SDCC2_APPS_CBCR_ADDR, m)
#define HWIO_GCC_SDCC2_APPS_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SDCC2_APPS_CBCR_ADDR,v)
#define HWIO_GCC_SDCC2_APPS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SDCC2_APPS_CBCR_ADDR,m,v,HWIO_GCC_SDCC2_APPS_CBCR_IN)
#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_CORE_ON_BMSK                                                0x4000
#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_CORE_ON_SHFT                                                   0xe
#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                              0x2000
#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                 0xd
#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                             0x1000
#define HWIO_GCC_SDCC2_APPS_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                                0xc
#define HWIO_GCC_SDCC2_APPS_CBCR_WAKEUP_BMSK                                                            0xf00
#define HWIO_GCC_SDCC2_APPS_CBCR_WAKEUP_SHFT                                                              0x8
#define HWIO_GCC_SDCC2_APPS_CBCR_SLEEP_BMSK                                                              0xf0
#define HWIO_GCC_SDCC2_APPS_CBCR_SLEEP_SHFT                                                               0x4
#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_SDCC2_APPS_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_SDCC2_AHB_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00014008)
#define HWIO_GCC_SDCC2_AHB_CBCR_RMSK                                                               0x80100005
#define HWIO_GCC_SDCC2_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_SDCC2_AHB_CBCR_ADDR)
#define HWIO_GCC_SDCC2_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SDCC2_AHB_CBCR_ADDR, m)
#define HWIO_GCC_SDCC2_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SDCC2_AHB_CBCR_ADDR,v)
#define HWIO_GCC_SDCC2_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SDCC2_AHB_CBCR_ADDR,m,v,HWIO_GCC_SDCC2_AHB_CBCR_IN)
#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_SDCC2_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                             0x100000
#define HWIO_GCC_SDCC2_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                 0x14
#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_ARES_SHFT                                                             0x2
#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_SDCC2_AHB_CBCR_CLK_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001400c)
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_RMSK                                                          0x800000f3
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_SDCC2_APPS_CMD_RCGR_ADDR)
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SDCC2_APPS_CMD_RCGR_ADDR, m)
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SDCC2_APPS_CMD_RCGR_ADDR,v)
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SDCC2_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_SDCC2_APPS_CMD_RCGR_IN)
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_ROOT_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_ROOT_OFF_SHFT                                                       0x1f
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_DIRTY_D_BMSK                                                        0x80
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_DIRTY_D_SHFT                                                         0x7
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_DIRTY_N_BMSK                                                        0x40
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_DIRTY_N_SHFT                                                         0x6
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_DIRTY_M_BMSK                                                        0x20
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_DIRTY_M_SHFT                                                         0x5
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                 0x10
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                  0x4
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_ROOT_EN_BMSK                                                         0x2
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_ROOT_EN_SHFT                                                         0x1
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_UPDATE_BMSK                                                          0x1
#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_UPDATE_SHFT                                                          0x0

#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00014010)
#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_RMSK                                                            0x10371f
#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_SDCC2_APPS_CFG_RCGR_ADDR)
#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SDCC2_APPS_CFG_RCGR_ADDR, m)
#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SDCC2_APPS_CFG_RCGR_ADDR,v)
#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SDCC2_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_SDCC2_APPS_CFG_RCGR_IN)
#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK                                             0x100000
#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                 0x14
#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_MODE_BMSK                                                         0x3000
#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_MODE_SHFT                                                            0xc
#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_SEL_BMSK                                                       0x700
#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_SEL_SHFT                                                         0x8
#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_BMSK                                                        0x1f
#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_SRC_DIV_SHFT                                                         0x0

#define HWIO_GCC_SDCC2_APPS_M_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00014014)
#define HWIO_GCC_SDCC2_APPS_M_RMSK                                                                       0xff
#define HWIO_GCC_SDCC2_APPS_M_IN          \
        in_dword(HWIO_GCC_SDCC2_APPS_M_ADDR)
#define HWIO_GCC_SDCC2_APPS_M_INM(m)      \
        in_dword_masked(HWIO_GCC_SDCC2_APPS_M_ADDR, m)
#define HWIO_GCC_SDCC2_APPS_M_OUT(v)      \
        out_dword(HWIO_GCC_SDCC2_APPS_M_ADDR,v)
#define HWIO_GCC_SDCC2_APPS_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SDCC2_APPS_M_ADDR,m,v,HWIO_GCC_SDCC2_APPS_M_IN)
#define HWIO_GCC_SDCC2_APPS_M_M_BMSK                                                                     0xff
#define HWIO_GCC_SDCC2_APPS_M_M_SHFT                                                                      0x0

#define HWIO_GCC_SDCC2_APPS_N_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00014018)
#define HWIO_GCC_SDCC2_APPS_N_RMSK                                                                       0xff
#define HWIO_GCC_SDCC2_APPS_N_IN          \
        in_dword(HWIO_GCC_SDCC2_APPS_N_ADDR)
#define HWIO_GCC_SDCC2_APPS_N_INM(m)      \
        in_dword_masked(HWIO_GCC_SDCC2_APPS_N_ADDR, m)
#define HWIO_GCC_SDCC2_APPS_N_OUT(v)      \
        out_dword(HWIO_GCC_SDCC2_APPS_N_ADDR,v)
#define HWIO_GCC_SDCC2_APPS_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SDCC2_APPS_N_ADDR,m,v,HWIO_GCC_SDCC2_APPS_N_IN)
#define HWIO_GCC_SDCC2_APPS_N_NOT_N_MINUS_M_BMSK                                                         0xff
#define HWIO_GCC_SDCC2_APPS_N_NOT_N_MINUS_M_SHFT                                                          0x0

#define HWIO_GCC_SDCC2_APPS_D_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0001401c)
#define HWIO_GCC_SDCC2_APPS_D_RMSK                                                                       0xff
#define HWIO_GCC_SDCC2_APPS_D_IN          \
        in_dword(HWIO_GCC_SDCC2_APPS_D_ADDR)
#define HWIO_GCC_SDCC2_APPS_D_INM(m)      \
        in_dword_masked(HWIO_GCC_SDCC2_APPS_D_ADDR, m)
#define HWIO_GCC_SDCC2_APPS_D_OUT(v)      \
        out_dword(HWIO_GCC_SDCC2_APPS_D_ADDR,v)
#define HWIO_GCC_SDCC2_APPS_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SDCC2_APPS_D_ADDR,m,v,HWIO_GCC_SDCC2_APPS_D_IN)
#define HWIO_GCC_SDCC2_APPS_D_NOT_2D_BMSK                                                                0xff
#define HWIO_GCC_SDCC2_APPS_D_NOT_2D_SHFT                                                                 0x0

#define HWIO_GCC_SDCC4_BCR_ADDR                                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00016000)
#define HWIO_GCC_SDCC4_BCR_RMSK                                                                           0x1
#define HWIO_GCC_SDCC4_BCR_IN          \
        in_dword(HWIO_GCC_SDCC4_BCR_ADDR)
#define HWIO_GCC_SDCC4_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SDCC4_BCR_ADDR, m)
#define HWIO_GCC_SDCC4_BCR_OUT(v)      \
        out_dword(HWIO_GCC_SDCC4_BCR_ADDR,v)
#define HWIO_GCC_SDCC4_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SDCC4_BCR_ADDR,m,v,HWIO_GCC_SDCC4_BCR_IN)
#define HWIO_GCC_SDCC4_BCR_BLK_ARES_BMSK                                                                  0x1
#define HWIO_GCC_SDCC4_BCR_BLK_ARES_SHFT                                                                  0x0

#define HWIO_GCC_SDCC4_APPS_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00016004)
#define HWIO_GCC_SDCC4_APPS_CBCR_RMSK                                                              0x80007ff5
#define HWIO_GCC_SDCC4_APPS_CBCR_IN          \
        in_dword(HWIO_GCC_SDCC4_APPS_CBCR_ADDR)
#define HWIO_GCC_SDCC4_APPS_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SDCC4_APPS_CBCR_ADDR, m)
#define HWIO_GCC_SDCC4_APPS_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SDCC4_APPS_CBCR_ADDR,v)
#define HWIO_GCC_SDCC4_APPS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SDCC4_APPS_CBCR_ADDR,m,v,HWIO_GCC_SDCC4_APPS_CBCR_IN)
#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_CORE_ON_BMSK                                                0x4000
#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_CORE_ON_SHFT                                                   0xe
#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                              0x2000
#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                 0xd
#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                             0x1000
#define HWIO_GCC_SDCC4_APPS_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                                0xc
#define HWIO_GCC_SDCC4_APPS_CBCR_WAKEUP_BMSK                                                            0xf00
#define HWIO_GCC_SDCC4_APPS_CBCR_WAKEUP_SHFT                                                              0x8
#define HWIO_GCC_SDCC4_APPS_CBCR_SLEEP_BMSK                                                              0xf0
#define HWIO_GCC_SDCC4_APPS_CBCR_SLEEP_SHFT                                                               0x4
#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_SDCC4_APPS_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_SDCC4_AHB_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00016008)
#define HWIO_GCC_SDCC4_AHB_CBCR_RMSK                                                               0x80100005
#define HWIO_GCC_SDCC4_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_SDCC4_AHB_CBCR_ADDR)
#define HWIO_GCC_SDCC4_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SDCC4_AHB_CBCR_ADDR, m)
#define HWIO_GCC_SDCC4_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SDCC4_AHB_CBCR_ADDR,v)
#define HWIO_GCC_SDCC4_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SDCC4_AHB_CBCR_ADDR,m,v,HWIO_GCC_SDCC4_AHB_CBCR_IN)
#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_SDCC4_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                             0x100000
#define HWIO_GCC_SDCC4_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                 0x14
#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_ARES_SHFT                                                             0x2
#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_SDCC4_AHB_CBCR_CLK_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001600c)
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_RMSK                                                          0x800000f3
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_SDCC4_APPS_CMD_RCGR_ADDR)
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SDCC4_APPS_CMD_RCGR_ADDR, m)
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SDCC4_APPS_CMD_RCGR_ADDR,v)
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SDCC4_APPS_CMD_RCGR_ADDR,m,v,HWIO_GCC_SDCC4_APPS_CMD_RCGR_IN)
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_ROOT_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_ROOT_OFF_SHFT                                                       0x1f
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_DIRTY_D_BMSK                                                        0x80
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_DIRTY_D_SHFT                                                         0x7
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_DIRTY_N_BMSK                                                        0x40
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_DIRTY_N_SHFT                                                         0x6
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_DIRTY_M_BMSK                                                        0x20
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_DIRTY_M_SHFT                                                         0x5
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                 0x10
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                  0x4
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_ROOT_EN_BMSK                                                         0x2
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_ROOT_EN_SHFT                                                         0x1
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_UPDATE_BMSK                                                          0x1
#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_UPDATE_SHFT                                                          0x0

#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00016010)
#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_RMSK                                                            0x10371f
#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_SDCC4_APPS_CFG_RCGR_ADDR)
#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SDCC4_APPS_CFG_RCGR_ADDR, m)
#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SDCC4_APPS_CFG_RCGR_ADDR,v)
#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SDCC4_APPS_CFG_RCGR_ADDR,m,v,HWIO_GCC_SDCC4_APPS_CFG_RCGR_IN)
#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_HW_CLK_CONTROL_BMSK                                             0x100000
#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                 0x14
#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_MODE_BMSK                                                         0x3000
#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_MODE_SHFT                                                            0xc
#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_SEL_BMSK                                                       0x700
#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_SEL_SHFT                                                         0x8
#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_BMSK                                                        0x1f
#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_SRC_DIV_SHFT                                                         0x0

#define HWIO_GCC_SDCC4_APPS_M_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00016014)
#define HWIO_GCC_SDCC4_APPS_M_RMSK                                                                       0xff
#define HWIO_GCC_SDCC4_APPS_M_IN          \
        in_dword(HWIO_GCC_SDCC4_APPS_M_ADDR)
#define HWIO_GCC_SDCC4_APPS_M_INM(m)      \
        in_dword_masked(HWIO_GCC_SDCC4_APPS_M_ADDR, m)
#define HWIO_GCC_SDCC4_APPS_M_OUT(v)      \
        out_dword(HWIO_GCC_SDCC4_APPS_M_ADDR,v)
#define HWIO_GCC_SDCC4_APPS_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SDCC4_APPS_M_ADDR,m,v,HWIO_GCC_SDCC4_APPS_M_IN)
#define HWIO_GCC_SDCC4_APPS_M_M_BMSK                                                                     0xff
#define HWIO_GCC_SDCC4_APPS_M_M_SHFT                                                                      0x0

#define HWIO_GCC_SDCC4_APPS_N_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00016018)
#define HWIO_GCC_SDCC4_APPS_N_RMSK                                                                       0xff
#define HWIO_GCC_SDCC4_APPS_N_IN          \
        in_dword(HWIO_GCC_SDCC4_APPS_N_ADDR)
#define HWIO_GCC_SDCC4_APPS_N_INM(m)      \
        in_dword_masked(HWIO_GCC_SDCC4_APPS_N_ADDR, m)
#define HWIO_GCC_SDCC4_APPS_N_OUT(v)      \
        out_dword(HWIO_GCC_SDCC4_APPS_N_ADDR,v)
#define HWIO_GCC_SDCC4_APPS_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SDCC4_APPS_N_ADDR,m,v,HWIO_GCC_SDCC4_APPS_N_IN)
#define HWIO_GCC_SDCC4_APPS_N_NOT_N_MINUS_M_BMSK                                                         0xff
#define HWIO_GCC_SDCC4_APPS_N_NOT_N_MINUS_M_SHFT                                                          0x0

#define HWIO_GCC_SDCC4_APPS_D_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0001601c)
#define HWIO_GCC_SDCC4_APPS_D_RMSK                                                                       0xff
#define HWIO_GCC_SDCC4_APPS_D_IN          \
        in_dword(HWIO_GCC_SDCC4_APPS_D_ADDR)
#define HWIO_GCC_SDCC4_APPS_D_INM(m)      \
        in_dword_masked(HWIO_GCC_SDCC4_APPS_D_ADDR, m)
#define HWIO_GCC_SDCC4_APPS_D_OUT(v)      \
        out_dword(HWIO_GCC_SDCC4_APPS_D_ADDR,v)
#define HWIO_GCC_SDCC4_APPS_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SDCC4_APPS_D_ADDR,m,v,HWIO_GCC_SDCC4_APPS_D_IN)
#define HWIO_GCC_SDCC4_APPS_D_NOT_2D_BMSK                                                                0xff
#define HWIO_GCC_SDCC4_APPS_D_NOT_2D_SHFT                                                                 0x0

#define HWIO_GCC_QUPV3_WRAPPER_0_BCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00017000)
#define HWIO_GCC_QUPV3_WRAPPER_0_BCR_RMSK                                                                 0x1
#define HWIO_GCC_QUPV3_WRAPPER_0_BCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAPPER_0_BCR_ADDR)
#define HWIO_GCC_QUPV3_WRAPPER_0_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAPPER_0_BCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAPPER_0_BCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAPPER_0_BCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAPPER_0_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAPPER_0_BCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAPPER_0_BCR_IN)
#define HWIO_GCC_QUPV3_WRAPPER_0_BCR_BLK_ARES_BMSK                                                        0x1
#define HWIO_GCC_QUPV3_WRAPPER_0_BCR_BLK_ARES_SHFT                                                        0x0

#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00017004)
#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_RMSK                                                      0x80100004
#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                    0x100000
#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                        0x14
#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_CLK_ARES_SHFT                                                    0x2

#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00017008)
#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_RMSK                                                      0x80100006
#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                    0x100000
#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                        0x14
#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_HW_CTL_BMSK                                                      0x2
#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_HW_CTL_SHFT                                                      0x1

#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00023000)
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_RMSK                                                        0x80107ff4
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                      0x100000
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                          0x14
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_FORCE_MEM_CORE_ON_BMSK                                          0x4000
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_FORCE_MEM_CORE_ON_SHFT                                             0xe
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                        0x2000
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                           0xd
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                       0x1000
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                          0xc
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_WAKEUP_BMSK                                                      0xf00
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_WAKEUP_SHFT                                                        0x8
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_SLEEP_BMSK                                                        0xf0
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_SLEEP_SHFT                                                         0x4
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_CLK_ARES_SHFT                                                      0x2

#define HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00023004)
#define HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_RMSK                                                              0x3
#define HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_IN)
#define HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_CLK_DIV_BMSK                                                      0x3
#define HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_CLK_DIV_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00023008)
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_RMSK                                                     0x80107ff4
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                   0x100000
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                       0x14
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_FORCE_MEM_CORE_ON_BMSK                                       0x4000
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_FORCE_MEM_CORE_ON_SHFT                                          0xe
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                     0x2000
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                        0xd
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                    0x1000
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                       0xc
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_WAKEUP_BMSK                                                   0xf00
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_WAKEUP_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_SLEEP_BMSK                                                     0xf0
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_SLEEP_SHFT                                                      0x4
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_CLK_ARES_SHFT                                                   0x2

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00023020)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_RMSK                                                     0x3ffff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_RCG_SW_CTRL_BMSK                                         0x38000
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_RCG_SW_CTRL_SHFT                                             0xf
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_SW_PERF_STATE_BMSK                                        0x7800
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_SW_PERF_STATE_SHFT                                           0xb
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_SW_OVERRIDE_BMSK                                           0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_SW_OVERRIDE_SHFT                                             0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                              0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_DFS_FSM_STATE_BMSK                                         0x1c0
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_DFS_FSM_STATE_SHFT                                           0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_HW_CLK_CONTROL_BMSK                                         0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_HW_CLK_CONTROL_SHFT                                          0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_CURR_PERF_STATE_BMSK                                        0x1e
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_CURR_PERF_STATE_SHFT                                         0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_DFS_EN_BMSK                                                  0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_DFS_EN_SHFT                                                  0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00023028)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0002302c)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00023030)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00023034)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00023038)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0002303c)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00023040)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00023044)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00023048)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0002304c)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00023050)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00023054)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00023058)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0002305c)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00023060)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00023064)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0002300c)
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_RMSK                                                 0x80000013
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_ROOT_OFF_BMSK                                        0x80000000
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_ROOT_OFF_SHFT                                              0x1f
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                        0x10
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                         0x4
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_ROOT_EN_BMSK                                                0x2
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_ROOT_EN_SHFT                                                0x1
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_UPDATE_BMSK                                                 0x1
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_UPDATE_SHFT                                                 0x0

#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00023010)
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_RMSK                                                   0x11071f
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_HW_CLK_CONTROL_BMSK                                    0x100000
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_HW_CLK_CONTROL_SHFT                                        0x14
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_RCGLITE_DISABLE_BMSK                                    0x10000
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_RCGLITE_DISABLE_SHFT                                       0x10
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001700c)
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S0_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S0_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S0_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S0_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S0_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00017024)
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001702c)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017030)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017034)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017038)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001703c)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017040)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017044)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017048)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001706c)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017070)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017074)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017078)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001707c)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017080)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017084)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017088)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000170ac)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000170b0)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000170b4)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000170b8)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000170bc)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000170c0)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000170c4)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000170c8)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000170ec)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000170f0)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000170f4)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000170f8)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000170fc)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017100)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017104)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017108)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00017010)
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00017014)
#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP0_S0_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00017018)
#define HWIO_GCC_QUPV3_WRAP0_S0_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S0_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S0_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S0_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S0_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S0_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S0_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S0_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S0_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S0_M_IN)
#define HWIO_GCC_QUPV3_WRAP0_S0_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_S0_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_S0_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001701c)
#define HWIO_GCC_QUPV3_WRAP0_S0_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S0_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S0_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S0_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S0_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S0_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S0_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S0_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S0_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S0_N_IN)
#define HWIO_GCC_QUPV3_WRAP0_S0_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP0_S0_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_S0_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00017020)
#define HWIO_GCC_QUPV3_WRAP0_S0_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S0_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S0_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S0_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S0_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S0_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S0_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S0_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S0_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S0_D_IN)
#define HWIO_GCC_QUPV3_WRAP0_S0_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP0_S0_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001713c)
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S1_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S1_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S1_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S1_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S1_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00017154)
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001715c)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017160)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017164)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017168)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001716c)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017170)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017174)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017178)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001719c)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000171a0)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000171a4)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000171a8)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000171ac)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000171b0)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000171b4)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000171b8)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000171dc)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000171e0)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000171e4)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000171e8)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000171ec)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000171f0)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000171f4)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000171f8)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001721c)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017220)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017224)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017228)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001722c)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017230)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017234)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017238)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00017140)
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00017144)
#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP0_S1_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00017148)
#define HWIO_GCC_QUPV3_WRAP0_S1_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S1_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S1_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S1_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S1_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S1_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S1_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S1_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S1_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S1_M_IN)
#define HWIO_GCC_QUPV3_WRAP0_S1_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_S1_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_S1_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001714c)
#define HWIO_GCC_QUPV3_WRAP0_S1_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S1_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S1_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S1_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S1_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S1_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S1_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S1_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S1_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S1_N_IN)
#define HWIO_GCC_QUPV3_WRAP0_S1_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP0_S1_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_S1_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00017150)
#define HWIO_GCC_QUPV3_WRAP0_S1_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S1_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S1_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S1_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S1_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S1_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S1_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S1_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S1_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S1_D_IN)
#define HWIO_GCC_QUPV3_WRAP0_S1_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP0_S1_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001726c)
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S2_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S2_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S2_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S2_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S2_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00017284)
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001728c)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017290)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017294)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017298)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001729c)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000172a0)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000172a4)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000172a8)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000172cc)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000172d0)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000172d4)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000172d8)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000172dc)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000172e0)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000172e4)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000172e8)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001730c)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017310)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017314)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017318)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001731c)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017320)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017324)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017328)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001734c)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017350)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017354)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017358)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001735c)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017360)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017364)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017368)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00017270)
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00017274)
#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP0_S2_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00017278)
#define HWIO_GCC_QUPV3_WRAP0_S2_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S2_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S2_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S2_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S2_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S2_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S2_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S2_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S2_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S2_M_IN)
#define HWIO_GCC_QUPV3_WRAP0_S2_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_S2_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_S2_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001727c)
#define HWIO_GCC_QUPV3_WRAP0_S2_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S2_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S2_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S2_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S2_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S2_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S2_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S2_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S2_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S2_N_IN)
#define HWIO_GCC_QUPV3_WRAP0_S2_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP0_S2_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_S2_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00017280)
#define HWIO_GCC_QUPV3_WRAP0_S2_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S2_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S2_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S2_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S2_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S2_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S2_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S2_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S2_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S2_D_IN)
#define HWIO_GCC_QUPV3_WRAP0_S2_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP0_S2_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001739c)
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S3_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S3_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S3_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S3_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S3_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000173b4)
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000173bc)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000173c0)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000173c4)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000173c8)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000173cc)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000173d0)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000173d4)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000173d8)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000173fc)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017400)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017404)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017408)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001740c)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017410)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017414)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017418)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001743c)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017440)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017444)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017448)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001744c)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017450)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017454)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017458)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001747c)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017480)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017484)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017488)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001748c)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017490)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017494)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017498)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000173a0)
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000173a4)
#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP0_S3_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000173a8)
#define HWIO_GCC_QUPV3_WRAP0_S3_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S3_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S3_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S3_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S3_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S3_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S3_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S3_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S3_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S3_M_IN)
#define HWIO_GCC_QUPV3_WRAP0_S3_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_S3_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_S3_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000173ac)
#define HWIO_GCC_QUPV3_WRAP0_S3_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S3_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S3_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S3_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S3_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S3_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S3_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S3_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S3_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S3_N_IN)
#define HWIO_GCC_QUPV3_WRAP0_S3_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP0_S3_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_S3_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000173b0)
#define HWIO_GCC_QUPV3_WRAP0_S3_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S3_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S3_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S3_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S3_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S3_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S3_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S3_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S3_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S3_D_IN)
#define HWIO_GCC_QUPV3_WRAP0_S3_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP0_S3_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x000174cc)
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S4_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S4_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S4_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S4_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S4_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000174e4)
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000174ec)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000174f0)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000174f4)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000174f8)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000174fc)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017500)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017504)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017508)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001752c)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017530)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017534)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017538)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001753c)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017540)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017544)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017548)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001756c)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017570)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017574)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017578)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001757c)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017580)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017584)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017588)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000175ac)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000175b0)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000175b4)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000175b8)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000175bc)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000175c0)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000175c4)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000175c8)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000174d0)
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000174d4)
#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP0_S4_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000174d8)
#define HWIO_GCC_QUPV3_WRAP0_S4_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S4_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S4_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S4_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S4_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S4_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S4_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S4_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S4_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S4_M_IN)
#define HWIO_GCC_QUPV3_WRAP0_S4_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_S4_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_S4_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000174dc)
#define HWIO_GCC_QUPV3_WRAP0_S4_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S4_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S4_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S4_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S4_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S4_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S4_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S4_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S4_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S4_N_IN)
#define HWIO_GCC_QUPV3_WRAP0_S4_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP0_S4_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_S4_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000174e0)
#define HWIO_GCC_QUPV3_WRAP0_S4_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S4_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S4_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S4_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S4_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S4_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S4_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S4_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S4_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S4_D_IN)
#define HWIO_GCC_QUPV3_WRAP0_S4_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP0_S4_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x000175fc)
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S5_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S5_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S5_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S5_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S5_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00017614)
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001761c)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017620)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017624)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017628)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001762c)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017630)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017634)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017638)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001765c)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017660)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017664)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017668)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001766c)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017670)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017674)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017678)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001769c)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000176a0)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000176a4)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000176a8)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000176ac)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000176b0)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000176b4)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000176b8)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000176dc)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000176e0)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000176e4)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000176e8)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000176ec)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000176f0)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000176f4)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000176f8)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00017600)
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00017604)
#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP0_S5_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00017608)
#define HWIO_GCC_QUPV3_WRAP0_S5_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S5_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S5_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S5_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S5_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S5_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S5_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S5_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S5_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S5_M_IN)
#define HWIO_GCC_QUPV3_WRAP0_S5_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_S5_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_S5_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001760c)
#define HWIO_GCC_QUPV3_WRAP0_S5_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S5_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S5_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S5_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S5_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S5_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S5_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S5_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S5_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S5_N_IN)
#define HWIO_GCC_QUPV3_WRAP0_S5_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP0_S5_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_S5_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00017610)
#define HWIO_GCC_QUPV3_WRAP0_S5_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S5_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S5_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S5_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S5_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S5_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S5_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S5_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S5_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S5_D_IN)
#define HWIO_GCC_QUPV3_WRAP0_S5_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP0_S5_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001772c)
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S6_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S6_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S6_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S6_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S6_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00017744)
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001774c)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017750)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017754)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017758)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001775c)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017760)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017764)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017768)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001778c)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017790)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017794)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017798)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001779c)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000177a0)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000177a4)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000177a8)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000177cc)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000177d0)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000177d4)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000177d8)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000177dc)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000177e0)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000177e4)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000177e8)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001780c)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017810)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017814)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017818)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001781c)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017820)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017824)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017828)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00017730)
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00017734)
#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP0_S6_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00017738)
#define HWIO_GCC_QUPV3_WRAP0_S6_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S6_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S6_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S6_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S6_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S6_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S6_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S6_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S6_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S6_M_IN)
#define HWIO_GCC_QUPV3_WRAP0_S6_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_S6_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_S6_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001773c)
#define HWIO_GCC_QUPV3_WRAP0_S6_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S6_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S6_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S6_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S6_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S6_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S6_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S6_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S6_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S6_N_IN)
#define HWIO_GCC_QUPV3_WRAP0_S6_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP0_S6_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_S6_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00017740)
#define HWIO_GCC_QUPV3_WRAP0_S6_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S6_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S6_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S6_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S6_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S6_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S6_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S6_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S6_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S6_D_IN)
#define HWIO_GCC_QUPV3_WRAP0_S6_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP0_S6_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001785c)
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S7_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S7_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S7_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S7_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S7_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00017874)
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001787c)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017880)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017884)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017888)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001788c)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017890)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017894)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00017898)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000178bc)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000178c0)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000178c4)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000178c8)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000178cc)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000178d0)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000178d4)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000178d8)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000178fc)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017900)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017904)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017908)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001790c)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017910)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017914)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017918)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001793c)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017940)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017944)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017948)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001794c)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017950)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017954)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00017958)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00017860)
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00017864)
#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP0_S7_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00017868)
#define HWIO_GCC_QUPV3_WRAP0_S7_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S7_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S7_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S7_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S7_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S7_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S7_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S7_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S7_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S7_M_IN)
#define HWIO_GCC_QUPV3_WRAP0_S7_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP0_S7_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP0_S7_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001786c)
#define HWIO_GCC_QUPV3_WRAP0_S7_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S7_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S7_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S7_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S7_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S7_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S7_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S7_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S7_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S7_N_IN)
#define HWIO_GCC_QUPV3_WRAP0_S7_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP0_S7_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP0_S7_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00017870)
#define HWIO_GCC_QUPV3_WRAP0_S7_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP0_S7_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP0_S7_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP0_S7_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP0_S7_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP0_S7_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP0_S7_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP0_S7_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP0_S7_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP0_S7_D_IN)
#define HWIO_GCC_QUPV3_WRAP0_S7_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP0_S7_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00018000)
#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_RMSK                                                                 0x1
#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAPPER_1_BCR_ADDR)
#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAPPER_1_BCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAPPER_1_BCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAPPER_1_BCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAPPER_1_BCR_IN)
#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_BLK_ARES_BMSK                                                        0x1
#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_BLK_ARES_SHFT                                                        0x0

#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00018004)
#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_RMSK                                                      0x80100004
#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                    0x100000
#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                        0x14
#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_CLK_ARES_SHFT                                                    0x2

#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00018008)
#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_RMSK                                                      0x80100006
#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                    0x100000
#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                        0x14
#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_HW_CTL_BMSK                                                      0x2
#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_HW_CTL_SHFT                                                      0x1

#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00023138)
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_RMSK                                                        0x80107ff4
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                      0x100000
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                          0x14
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_CORE_ON_BMSK                                          0x4000
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_CORE_ON_SHFT                                             0xe
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                        0x2000
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                           0xd
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                       0x1000
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                          0xc
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_WAKEUP_BMSK                                                      0xf00
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_WAKEUP_SHFT                                                        0x8
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_SLEEP_BMSK                                                        0xf0
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_SLEEP_SHFT                                                         0x4
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_CLK_ARES_SHFT                                                      0x2

#define HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0002313c)
#define HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_RMSK                                                              0x3
#define HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_IN)
#define HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_CLK_DIV_BMSK                                                      0x3
#define HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_CLK_DIV_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00023140)
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_RMSK                                                     0x80107ff4
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                   0x100000
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                       0x14
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_CORE_ON_BMSK                                       0x4000
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_CORE_ON_SHFT                                          0xe
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                     0x2000
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                        0xd
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                    0x1000
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                       0xc
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_WAKEUP_BMSK                                                   0xf00
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_WAKEUP_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_SLEEP_BMSK                                                     0xf0
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_SLEEP_SHFT                                                      0x4
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_CLK_ARES_SHFT                                                   0x2

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00023160)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00023164)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00023168)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0002316c)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00023170)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00023174)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00023178)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0002317c)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00023180)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00023184)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00023188)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0002318c)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00023190)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00023194)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00023198)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0002319c)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00023144)
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_RMSK                                                 0x80000013
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ROOT_OFF_BMSK                                        0x80000000
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ROOT_OFF_SHFT                                              0x1f
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                        0x10
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                         0x4
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ROOT_EN_BMSK                                                0x2
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ROOT_EN_SHFT                                                0x1
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_UPDATE_BMSK                                                 0x1
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_UPDATE_SHFT                                                 0x0

#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00023148)
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_RMSK                                                   0x11071f
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_HW_CLK_CONTROL_BMSK                                    0x100000
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_HW_CLK_CONTROL_SHFT                                        0x14
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_RCGLITE_DISABLE_BMSK                                    0x10000
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_RCGLITE_DISABLE_SHFT                                       0x10
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001800c)
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S0_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S0_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S0_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S0_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00018024)
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001802c)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018030)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018034)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018038)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001803c)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018040)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018044)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018048)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001806c)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018070)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018074)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018078)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001807c)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018080)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018084)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018088)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000180ac)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000180b0)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000180b4)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000180b8)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000180bc)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000180c0)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000180c4)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000180c8)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000180ec)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000180f0)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000180f4)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000180f8)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000180fc)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018100)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018104)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018108)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00018010)
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00018014)
#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP1_S0_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00018018)
#define HWIO_GCC_QUPV3_WRAP1_S0_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S0_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S0_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S0_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S0_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S0_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S0_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S0_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S0_M_IN)
#define HWIO_GCC_QUPV3_WRAP1_S0_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_S0_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_S0_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001801c)
#define HWIO_GCC_QUPV3_WRAP1_S0_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S0_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S0_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S0_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S0_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S0_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S0_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S0_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S0_N_IN)
#define HWIO_GCC_QUPV3_WRAP1_S0_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP1_S0_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP1_S0_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00018020)
#define HWIO_GCC_QUPV3_WRAP1_S0_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S0_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S0_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S0_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S0_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S0_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S0_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S0_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S0_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S0_D_IN)
#define HWIO_GCC_QUPV3_WRAP1_S0_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP1_S0_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001813c)
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S1_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S1_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S1_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S1_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00018154)
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001815c)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018160)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018164)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018168)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001816c)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018170)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018174)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018178)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001819c)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000181a0)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000181a4)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000181a8)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000181ac)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000181b0)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000181b4)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000181b8)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000181dc)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000181e0)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000181e4)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000181e8)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000181ec)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000181f0)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000181f4)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000181f8)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001821c)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018220)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018224)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018228)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001822c)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018230)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018234)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018238)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00018140)
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00018144)
#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP1_S1_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00018148)
#define HWIO_GCC_QUPV3_WRAP1_S1_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S1_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S1_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S1_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S1_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S1_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S1_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S1_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S1_M_IN)
#define HWIO_GCC_QUPV3_WRAP1_S1_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_S1_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_S1_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001814c)
#define HWIO_GCC_QUPV3_WRAP1_S1_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S1_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S1_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S1_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S1_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S1_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S1_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S1_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S1_N_IN)
#define HWIO_GCC_QUPV3_WRAP1_S1_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP1_S1_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP1_S1_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00018150)
#define HWIO_GCC_QUPV3_WRAP1_S1_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S1_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S1_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S1_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S1_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S1_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S1_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S1_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S1_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S1_D_IN)
#define HWIO_GCC_QUPV3_WRAP1_S1_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP1_S1_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001826c)
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S2_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S2_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S2_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S2_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00018284)
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001828c)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018290)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018294)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018298)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001829c)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000182a0)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000182a4)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000182a8)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000182cc)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000182d0)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000182d4)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000182d8)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000182dc)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000182e0)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000182e4)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000182e8)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001830c)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018310)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018314)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018318)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001831c)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018320)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018324)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018328)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001834c)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018350)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018354)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018358)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001835c)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018360)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018364)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018368)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00018270)
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00018274)
#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP1_S2_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00018278)
#define HWIO_GCC_QUPV3_WRAP1_S2_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S2_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S2_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S2_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S2_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S2_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S2_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S2_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S2_M_IN)
#define HWIO_GCC_QUPV3_WRAP1_S2_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_S2_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_S2_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001827c)
#define HWIO_GCC_QUPV3_WRAP1_S2_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S2_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S2_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S2_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S2_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S2_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S2_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S2_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S2_N_IN)
#define HWIO_GCC_QUPV3_WRAP1_S2_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP1_S2_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP1_S2_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00018280)
#define HWIO_GCC_QUPV3_WRAP1_S2_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S2_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S2_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S2_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S2_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S2_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S2_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S2_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S2_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S2_D_IN)
#define HWIO_GCC_QUPV3_WRAP1_S2_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP1_S2_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001839c)
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S3_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S3_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S3_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S3_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000183b4)
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000183bc)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000183c0)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000183c4)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000183c8)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000183cc)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000183d0)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000183d4)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000183d8)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000183fc)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018400)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018404)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018408)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001840c)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018410)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018414)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018418)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001843c)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018440)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018444)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018448)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001844c)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018450)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018454)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018458)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001847c)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018480)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018484)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018488)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001848c)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018490)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018494)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018498)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000183a0)
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000183a4)
#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP1_S3_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000183a8)
#define HWIO_GCC_QUPV3_WRAP1_S3_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S3_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S3_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S3_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S3_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S3_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S3_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S3_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S3_M_IN)
#define HWIO_GCC_QUPV3_WRAP1_S3_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_S3_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_S3_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000183ac)
#define HWIO_GCC_QUPV3_WRAP1_S3_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S3_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S3_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S3_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S3_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S3_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S3_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S3_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S3_N_IN)
#define HWIO_GCC_QUPV3_WRAP1_S3_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP1_S3_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP1_S3_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000183b0)
#define HWIO_GCC_QUPV3_WRAP1_S3_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S3_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S3_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S3_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S3_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S3_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S3_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S3_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S3_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S3_D_IN)
#define HWIO_GCC_QUPV3_WRAP1_S3_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP1_S3_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x000184cc)
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S4_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S4_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S4_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S4_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000184e4)
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000184ec)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000184f0)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000184f4)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000184f8)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000184fc)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018500)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018504)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018508)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001852c)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018530)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018534)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018538)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001853c)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018540)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018544)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018548)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001856c)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018570)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018574)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018578)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001857c)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018580)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018584)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018588)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000185ac)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000185b0)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000185b4)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000185b8)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000185bc)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000185c0)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000185c4)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000185c8)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000184d0)
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000184d4)
#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP1_S4_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000184d8)
#define HWIO_GCC_QUPV3_WRAP1_S4_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S4_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S4_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S4_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S4_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S4_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S4_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S4_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S4_M_IN)
#define HWIO_GCC_QUPV3_WRAP1_S4_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_S4_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_S4_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000184dc)
#define HWIO_GCC_QUPV3_WRAP1_S4_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S4_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S4_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S4_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S4_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S4_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S4_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S4_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S4_N_IN)
#define HWIO_GCC_QUPV3_WRAP1_S4_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP1_S4_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP1_S4_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000184e0)
#define HWIO_GCC_QUPV3_WRAP1_S4_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S4_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S4_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S4_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S4_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S4_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S4_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S4_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S4_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S4_D_IN)
#define HWIO_GCC_QUPV3_WRAP1_S4_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP1_S4_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x000185fc)
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S5_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S5_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S5_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S5_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00018614)
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001861c)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018620)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018624)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018628)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001862c)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018630)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018634)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00018638)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001865c)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018660)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018664)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018668)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001866c)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018670)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018674)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00018678)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001869c)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000186a0)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000186a4)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000186a8)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000186ac)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000186b0)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000186b4)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000186b8)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000186dc)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000186e0)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000186e4)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000186e8)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000186ec)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000186f0)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000186f4)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000186f8)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00018600)
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00018604)
#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP1_S5_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00018608)
#define HWIO_GCC_QUPV3_WRAP1_S5_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S5_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S5_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S5_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S5_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S5_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S5_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S5_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S5_M_IN)
#define HWIO_GCC_QUPV3_WRAP1_S5_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP1_S5_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP1_S5_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001860c)
#define HWIO_GCC_QUPV3_WRAP1_S5_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S5_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S5_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S5_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S5_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S5_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S5_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S5_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S5_N_IN)
#define HWIO_GCC_QUPV3_WRAP1_S5_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP1_S5_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP1_S5_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00018610)
#define HWIO_GCC_QUPV3_WRAP1_S5_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP1_S5_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP1_S5_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP1_S5_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP1_S5_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP1_S5_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP1_S5_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP1_S5_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP1_S5_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP1_S5_D_IN)
#define HWIO_GCC_QUPV3_WRAP1_S5_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP1_S5_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_PDM_BCR_ADDR                                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00033000)
#define HWIO_GCC_PDM_BCR_RMSK                                                                             0x1
#define HWIO_GCC_PDM_BCR_IN          \
        in_dword(HWIO_GCC_PDM_BCR_ADDR)
#define HWIO_GCC_PDM_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PDM_BCR_ADDR, m)
#define HWIO_GCC_PDM_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PDM_BCR_ADDR,v)
#define HWIO_GCC_PDM_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PDM_BCR_ADDR,m,v,HWIO_GCC_PDM_BCR_IN)
#define HWIO_GCC_PDM_BCR_BLK_ARES_BMSK                                                                    0x1
#define HWIO_GCC_PDM_BCR_BLK_ARES_SHFT                                                                    0x0

#define HWIO_GCC_PDM_AHB_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00033004)
#define HWIO_GCC_PDM_AHB_CBCR_RMSK                                                                 0x80100007
#define HWIO_GCC_PDM_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_PDM_AHB_CBCR_ADDR)
#define HWIO_GCC_PDM_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PDM_AHB_CBCR_ADDR, m)
#define HWIO_GCC_PDM_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PDM_AHB_CBCR_ADDR,v)
#define HWIO_GCC_PDM_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PDM_AHB_CBCR_ADDR,m,v,HWIO_GCC_PDM_AHB_CBCR_IN)
#define HWIO_GCC_PDM_AHB_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_PDM_AHB_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_PDM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                               0x100000
#define HWIO_GCC_PDM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                   0x14
#define HWIO_GCC_PDM_AHB_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_PDM_AHB_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_PDM_AHB_CBCR_HW_CTL_BMSK                                                                 0x2
#define HWIO_GCC_PDM_AHB_CBCR_HW_CTL_SHFT                                                                 0x1
#define HWIO_GCC_PDM_AHB_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_PDM_AHB_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_PDM_XO4_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00033008)
#define HWIO_GCC_PDM_XO4_CBCR_RMSK                                                                 0x80000005
#define HWIO_GCC_PDM_XO4_CBCR_IN          \
        in_dword(HWIO_GCC_PDM_XO4_CBCR_ADDR)
#define HWIO_GCC_PDM_XO4_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PDM_XO4_CBCR_ADDR, m)
#define HWIO_GCC_PDM_XO4_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PDM_XO4_CBCR_ADDR,v)
#define HWIO_GCC_PDM_XO4_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PDM_XO4_CBCR_ADDR,m,v,HWIO_GCC_PDM_XO4_CBCR_IN)
#define HWIO_GCC_PDM_XO4_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_PDM_XO4_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_PDM_XO4_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_PDM_XO4_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_PDM_XO4_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_PDM_XO4_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_PDM2_CBCR_ADDR                                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0003300c)
#define HWIO_GCC_PDM2_CBCR_RMSK                                                                    0x80000005
#define HWIO_GCC_PDM2_CBCR_IN          \
        in_dword(HWIO_GCC_PDM2_CBCR_ADDR)
#define HWIO_GCC_PDM2_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PDM2_CBCR_ADDR, m)
#define HWIO_GCC_PDM2_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PDM2_CBCR_ADDR,v)
#define HWIO_GCC_PDM2_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PDM2_CBCR_ADDR,m,v,HWIO_GCC_PDM2_CBCR_IN)
#define HWIO_GCC_PDM2_CBCR_CLK_OFF_BMSK                                                            0x80000000
#define HWIO_GCC_PDM2_CBCR_CLK_OFF_SHFT                                                                  0x1f
#define HWIO_GCC_PDM2_CBCR_CLK_ARES_BMSK                                                                  0x4
#define HWIO_GCC_PDM2_CBCR_CLK_ARES_SHFT                                                                  0x2
#define HWIO_GCC_PDM2_CBCR_CLK_ENABLE_BMSK                                                                0x1
#define HWIO_GCC_PDM2_CBCR_CLK_ENABLE_SHFT                                                                0x0

#define HWIO_GCC_PDM2_CMD_RCGR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00033010)
#define HWIO_GCC_PDM2_CMD_RCGR_RMSK                                                                0x80000013
#define HWIO_GCC_PDM2_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_PDM2_CMD_RCGR_ADDR)
#define HWIO_GCC_PDM2_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PDM2_CMD_RCGR_ADDR, m)
#define HWIO_GCC_PDM2_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_PDM2_CMD_RCGR_ADDR,v)
#define HWIO_GCC_PDM2_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PDM2_CMD_RCGR_ADDR,m,v,HWIO_GCC_PDM2_CMD_RCGR_IN)
#define HWIO_GCC_PDM2_CMD_RCGR_ROOT_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_PDM2_CMD_RCGR_ROOT_OFF_SHFT                                                             0x1f
#define HWIO_GCC_PDM2_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                       0x10
#define HWIO_GCC_PDM2_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                        0x4
#define HWIO_GCC_PDM2_CMD_RCGR_ROOT_EN_BMSK                                                               0x2
#define HWIO_GCC_PDM2_CMD_RCGR_ROOT_EN_SHFT                                                               0x1
#define HWIO_GCC_PDM2_CMD_RCGR_UPDATE_BMSK                                                                0x1
#define HWIO_GCC_PDM2_CMD_RCGR_UPDATE_SHFT                                                                0x0

#define HWIO_GCC_PDM2_CFG_RCGR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00033014)
#define HWIO_GCC_PDM2_CFG_RCGR_RMSK                                                                  0x11071f
#define HWIO_GCC_PDM2_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_PDM2_CFG_RCGR_ADDR)
#define HWIO_GCC_PDM2_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PDM2_CFG_RCGR_ADDR, m)
#define HWIO_GCC_PDM2_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_PDM2_CFG_RCGR_ADDR,v)
#define HWIO_GCC_PDM2_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PDM2_CFG_RCGR_ADDR,m,v,HWIO_GCC_PDM2_CFG_RCGR_IN)
#define HWIO_GCC_PDM2_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                   0x100000
#define HWIO_GCC_PDM2_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                       0x14
#define HWIO_GCC_PDM2_CFG_RCGR_RCGLITE_DISABLE_BMSK                                                   0x10000
#define HWIO_GCC_PDM2_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                      0x10
#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_BMSK                                                             0x700
#define HWIO_GCC_PDM2_CFG_RCGR_SRC_SEL_SHFT                                                               0x8
#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_BMSK                                                              0x1f
#define HWIO_GCC_PDM2_CFG_RCGR_SRC_DIV_SHFT                                                               0x0

#define HWIO_GCC_PDM_XO4_CDIVR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00033028)
#define HWIO_GCC_PDM_XO4_CDIVR_RMSK                                                                       0x3
#define HWIO_GCC_PDM_XO4_CDIVR_IN          \
        in_dword(HWIO_GCC_PDM_XO4_CDIVR_ADDR)
#define HWIO_GCC_PDM_XO4_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_PDM_XO4_CDIVR_ADDR, m)
#define HWIO_GCC_PDM_XO4_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_PDM_XO4_CDIVR_ADDR,v)
#define HWIO_GCC_PDM_XO4_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PDM_XO4_CDIVR_ADDR,m,v,HWIO_GCC_PDM_XO4_CDIVR_IN)
#define HWIO_GCC_PDM_XO4_CDIVR_CLK_DIV_BMSK                                                               0x3
#define HWIO_GCC_PDM_XO4_CDIVR_CLK_DIV_SHFT                                                               0x0

#define HWIO_GCC_PRNG_BCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00034000)
#define HWIO_GCC_PRNG_BCR_RMSK                                                                            0x1
#define HWIO_GCC_PRNG_BCR_IN          \
        in_dword(HWIO_GCC_PRNG_BCR_ADDR)
#define HWIO_GCC_PRNG_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PRNG_BCR_ADDR, m)
#define HWIO_GCC_PRNG_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PRNG_BCR_ADDR,v)
#define HWIO_GCC_PRNG_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PRNG_BCR_ADDR,m,v,HWIO_GCC_PRNG_BCR_IN)
#define HWIO_GCC_PRNG_BCR_BLK_ARES_BMSK                                                                   0x1
#define HWIO_GCC_PRNG_BCR_BLK_ARES_SHFT                                                                   0x0

#define HWIO_GCC_PRNG_AHB_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00034004)
#define HWIO_GCC_PRNG_AHB_CBCR_RMSK                                                                0x80100004
#define HWIO_GCC_PRNG_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_PRNG_AHB_CBCR_ADDR)
#define HWIO_GCC_PRNG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PRNG_AHB_CBCR_ADDR, m)
#define HWIO_GCC_PRNG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PRNG_AHB_CBCR_ADDR,v)
#define HWIO_GCC_PRNG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PRNG_AHB_CBCR_ADDR,m,v,HWIO_GCC_PRNG_AHB_CBCR_IN)
#define HWIO_GCC_PRNG_AHB_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_PRNG_AHB_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_PRNG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_PRNG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_PRNG_AHB_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_PRNG_AHB_CBCR_CLK_ARES_SHFT                                                              0x2

#define HWIO_GCC_TSIF_BCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00036000)
#define HWIO_GCC_TSIF_BCR_RMSK                                                                            0x1
#define HWIO_GCC_TSIF_BCR_IN          \
        in_dword(HWIO_GCC_TSIF_BCR_ADDR)
#define HWIO_GCC_TSIF_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TSIF_BCR_ADDR, m)
#define HWIO_GCC_TSIF_BCR_OUT(v)      \
        out_dword(HWIO_GCC_TSIF_BCR_ADDR,v)
#define HWIO_GCC_TSIF_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TSIF_BCR_ADDR,m,v,HWIO_GCC_TSIF_BCR_IN)
#define HWIO_GCC_TSIF_BCR_BLK_ARES_BMSK                                                                   0x1
#define HWIO_GCC_TSIF_BCR_BLK_ARES_SHFT                                                                   0x0

#define HWIO_GCC_TSIF_AHB_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00036004)
#define HWIO_GCC_TSIF_AHB_CBCR_RMSK                                                                0x80107ff5
#define HWIO_GCC_TSIF_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_TSIF_AHB_CBCR_ADDR)
#define HWIO_GCC_TSIF_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TSIF_AHB_CBCR_ADDR, m)
#define HWIO_GCC_TSIF_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_TSIF_AHB_CBCR_ADDR,v)
#define HWIO_GCC_TSIF_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TSIF_AHB_CBCR_ADDR,m,v,HWIO_GCC_TSIF_AHB_CBCR_IN)
#define HWIO_GCC_TSIF_AHB_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_TSIF_AHB_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_TSIF_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_TSIF_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_TSIF_AHB_CBCR_FORCE_MEM_CORE_ON_BMSK                                                  0x4000
#define HWIO_GCC_TSIF_AHB_CBCR_FORCE_MEM_CORE_ON_SHFT                                                     0xe
#define HWIO_GCC_TSIF_AHB_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                                0x2000
#define HWIO_GCC_TSIF_AHB_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                   0xd
#define HWIO_GCC_TSIF_AHB_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                               0x1000
#define HWIO_GCC_TSIF_AHB_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                                  0xc
#define HWIO_GCC_TSIF_AHB_CBCR_WAKEUP_BMSK                                                              0xf00
#define HWIO_GCC_TSIF_AHB_CBCR_WAKEUP_SHFT                                                                0x8
#define HWIO_GCC_TSIF_AHB_CBCR_SLEEP_BMSK                                                                0xf0
#define HWIO_GCC_TSIF_AHB_CBCR_SLEEP_SHFT                                                                 0x4
#define HWIO_GCC_TSIF_AHB_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_TSIF_AHB_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_TSIF_AHB_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_TSIF_AHB_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_TSIF_REF_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00036008)
#define HWIO_GCC_TSIF_REF_CBCR_RMSK                                                                0x80000005
#define HWIO_GCC_TSIF_REF_CBCR_IN          \
        in_dword(HWIO_GCC_TSIF_REF_CBCR_ADDR)
#define HWIO_GCC_TSIF_REF_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TSIF_REF_CBCR_ADDR, m)
#define HWIO_GCC_TSIF_REF_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_TSIF_REF_CBCR_ADDR,v)
#define HWIO_GCC_TSIF_REF_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TSIF_REF_CBCR_ADDR,m,v,HWIO_GCC_TSIF_REF_CBCR_IN)
#define HWIO_GCC_TSIF_REF_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_TSIF_REF_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_TSIF_REF_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_TSIF_REF_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_TSIF_REF_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_TSIF_REF_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0003600c)
#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_RMSK                                                  0x80000005
#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_IN          \
        in_dword(HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_ADDR)
#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_ADDR, m)
#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_ADDR,v)
#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_ADDR,m,v,HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_IN)
#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_CLK_ENABLE_SHFT                                              0x0

#define HWIO_GCC_TSIF_REF_CMD_RCGR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00036010)
#define HWIO_GCC_TSIF_REF_CMD_RCGR_RMSK                                                            0x800000f3
#define HWIO_GCC_TSIF_REF_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_TSIF_REF_CMD_RCGR_ADDR)
#define HWIO_GCC_TSIF_REF_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_TSIF_REF_CMD_RCGR_ADDR, m)
#define HWIO_GCC_TSIF_REF_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_TSIF_REF_CMD_RCGR_ADDR,v)
#define HWIO_GCC_TSIF_REF_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TSIF_REF_CMD_RCGR_ADDR,m,v,HWIO_GCC_TSIF_REF_CMD_RCGR_IN)
#define HWIO_GCC_TSIF_REF_CMD_RCGR_ROOT_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_TSIF_REF_CMD_RCGR_ROOT_OFF_SHFT                                                         0x1f
#define HWIO_GCC_TSIF_REF_CMD_RCGR_DIRTY_D_BMSK                                                          0x80
#define HWIO_GCC_TSIF_REF_CMD_RCGR_DIRTY_D_SHFT                                                           0x7
#define HWIO_GCC_TSIF_REF_CMD_RCGR_DIRTY_N_BMSK                                                          0x40
#define HWIO_GCC_TSIF_REF_CMD_RCGR_DIRTY_N_SHFT                                                           0x6
#define HWIO_GCC_TSIF_REF_CMD_RCGR_DIRTY_M_BMSK                                                          0x20
#define HWIO_GCC_TSIF_REF_CMD_RCGR_DIRTY_M_SHFT                                                           0x5
#define HWIO_GCC_TSIF_REF_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                   0x10
#define HWIO_GCC_TSIF_REF_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                    0x4
#define HWIO_GCC_TSIF_REF_CMD_RCGR_ROOT_EN_BMSK                                                           0x2
#define HWIO_GCC_TSIF_REF_CMD_RCGR_ROOT_EN_SHFT                                                           0x1
#define HWIO_GCC_TSIF_REF_CMD_RCGR_UPDATE_BMSK                                                            0x1
#define HWIO_GCC_TSIF_REF_CMD_RCGR_UPDATE_SHFT                                                            0x0

#define HWIO_GCC_TSIF_REF_CFG_RCGR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00036014)
#define HWIO_GCC_TSIF_REF_CFG_RCGR_RMSK                                                              0x10371f
#define HWIO_GCC_TSIF_REF_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_TSIF_REF_CFG_RCGR_ADDR)
#define HWIO_GCC_TSIF_REF_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_TSIF_REF_CFG_RCGR_ADDR, m)
#define HWIO_GCC_TSIF_REF_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_TSIF_REF_CFG_RCGR_ADDR,v)
#define HWIO_GCC_TSIF_REF_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TSIF_REF_CFG_RCGR_ADDR,m,v,HWIO_GCC_TSIF_REF_CFG_RCGR_IN)
#define HWIO_GCC_TSIF_REF_CFG_RCGR_HW_CLK_CONTROL_BMSK                                               0x100000
#define HWIO_GCC_TSIF_REF_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                   0x14
#define HWIO_GCC_TSIF_REF_CFG_RCGR_MODE_BMSK                                                           0x3000
#define HWIO_GCC_TSIF_REF_CFG_RCGR_MODE_SHFT                                                              0xc
#define HWIO_GCC_TSIF_REF_CFG_RCGR_SRC_SEL_BMSK                                                         0x700
#define HWIO_GCC_TSIF_REF_CFG_RCGR_SRC_SEL_SHFT                                                           0x8
#define HWIO_GCC_TSIF_REF_CFG_RCGR_SRC_DIV_BMSK                                                          0x1f
#define HWIO_GCC_TSIF_REF_CFG_RCGR_SRC_DIV_SHFT                                                           0x0

#define HWIO_GCC_TSIF_REF_M_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00036018)
#define HWIO_GCC_TSIF_REF_M_RMSK                                                                         0xff
#define HWIO_GCC_TSIF_REF_M_IN          \
        in_dword(HWIO_GCC_TSIF_REF_M_ADDR)
#define HWIO_GCC_TSIF_REF_M_INM(m)      \
        in_dword_masked(HWIO_GCC_TSIF_REF_M_ADDR, m)
#define HWIO_GCC_TSIF_REF_M_OUT(v)      \
        out_dword(HWIO_GCC_TSIF_REF_M_ADDR,v)
#define HWIO_GCC_TSIF_REF_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TSIF_REF_M_ADDR,m,v,HWIO_GCC_TSIF_REF_M_IN)
#define HWIO_GCC_TSIF_REF_M_M_BMSK                                                                       0xff
#define HWIO_GCC_TSIF_REF_M_M_SHFT                                                                        0x0

#define HWIO_GCC_TSIF_REF_N_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0003601c)
#define HWIO_GCC_TSIF_REF_N_RMSK                                                                         0xff
#define HWIO_GCC_TSIF_REF_N_IN          \
        in_dword(HWIO_GCC_TSIF_REF_N_ADDR)
#define HWIO_GCC_TSIF_REF_N_INM(m)      \
        in_dword_masked(HWIO_GCC_TSIF_REF_N_ADDR, m)
#define HWIO_GCC_TSIF_REF_N_OUT(v)      \
        out_dword(HWIO_GCC_TSIF_REF_N_ADDR,v)
#define HWIO_GCC_TSIF_REF_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TSIF_REF_N_ADDR,m,v,HWIO_GCC_TSIF_REF_N_IN)
#define HWIO_GCC_TSIF_REF_N_NOT_N_MINUS_M_BMSK                                                           0xff
#define HWIO_GCC_TSIF_REF_N_NOT_N_MINUS_M_SHFT                                                            0x0

#define HWIO_GCC_TSIF_REF_D_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00036020)
#define HWIO_GCC_TSIF_REF_D_RMSK                                                                         0xff
#define HWIO_GCC_TSIF_REF_D_IN          \
        in_dword(HWIO_GCC_TSIF_REF_D_ADDR)
#define HWIO_GCC_TSIF_REF_D_INM(m)      \
        in_dword_masked(HWIO_GCC_TSIF_REF_D_ADDR, m)
#define HWIO_GCC_TSIF_REF_D_OUT(v)      \
        out_dword(HWIO_GCC_TSIF_REF_D_ADDR,v)
#define HWIO_GCC_TSIF_REF_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TSIF_REF_D_ADDR,m,v,HWIO_GCC_TSIF_REF_D_IN)
#define HWIO_GCC_TSIF_REF_D_NOT_2D_BMSK                                                                  0xff
#define HWIO_GCC_TSIF_REF_D_NOT_2D_SHFT                                                                   0x0

#define HWIO_GCC_TCSR_BCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00037000)
#define HWIO_GCC_TCSR_BCR_RMSK                                                                            0x1
#define HWIO_GCC_TCSR_BCR_IN          \
        in_dword(HWIO_GCC_TCSR_BCR_ADDR)
#define HWIO_GCC_TCSR_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TCSR_BCR_ADDR, m)
#define HWIO_GCC_TCSR_BCR_OUT(v)      \
        out_dword(HWIO_GCC_TCSR_BCR_ADDR,v)
#define HWIO_GCC_TCSR_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TCSR_BCR_ADDR,m,v,HWIO_GCC_TCSR_BCR_IN)
#define HWIO_GCC_TCSR_BCR_BLK_ARES_BMSK                                                                   0x1
#define HWIO_GCC_TCSR_BCR_BLK_ARES_SHFT                                                                   0x0

#define HWIO_GCC_TCSR_AHB_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00037004)
#define HWIO_GCC_TCSR_AHB_CBCR_RMSK                                                                0x80100004
#define HWIO_GCC_TCSR_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_TCSR_AHB_CBCR_ADDR)
#define HWIO_GCC_TCSR_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TCSR_AHB_CBCR_ADDR, m)
#define HWIO_GCC_TCSR_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_TCSR_AHB_CBCR_ADDR,v)
#define HWIO_GCC_TCSR_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TCSR_AHB_CBCR_ADDR,m,v,HWIO_GCC_TCSR_AHB_CBCR_IN)
#define HWIO_GCC_TCSR_AHB_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_TCSR_AHB_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_TCSR_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_TCSR_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_TCSR_AHB_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_TCSR_AHB_CBCR_CLK_ARES_SHFT                                                              0x2

#define HWIO_GCC_BOOT_ROM_BCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00038000)
#define HWIO_GCC_BOOT_ROM_BCR_RMSK                                                                        0x1
#define HWIO_GCC_BOOT_ROM_BCR_IN          \
        in_dword(HWIO_GCC_BOOT_ROM_BCR_ADDR)
#define HWIO_GCC_BOOT_ROM_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_BOOT_ROM_BCR_ADDR, m)
#define HWIO_GCC_BOOT_ROM_BCR_OUT(v)      \
        out_dword(HWIO_GCC_BOOT_ROM_BCR_ADDR,v)
#define HWIO_GCC_BOOT_ROM_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_BOOT_ROM_BCR_ADDR,m,v,HWIO_GCC_BOOT_ROM_BCR_IN)
#define HWIO_GCC_BOOT_ROM_BCR_BLK_ARES_BMSK                                                               0x1
#define HWIO_GCC_BOOT_ROM_BCR_BLK_ARES_SHFT                                                               0x0

#define HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00038004)
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_RMSK                                                            0x80107ff6
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR)
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR, m)
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR,v)
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR,m,v,HWIO_GCC_BOOT_ROM_AHB_CBCR_IN)
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                          0x100000
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                              0x14
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_CORE_ON_BMSK                                              0x4000
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_CORE_ON_SHFT                                                 0xe
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                            0x2000
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                               0xd
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                           0x1000
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                              0xc
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_BMSK                                                          0xf00
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_WAKEUP_SHFT                                                            0x8
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_BMSK                                                            0xf0
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_SLEEP_SHFT                                                             0x4
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_HW_CTL_BMSK                                                            0x2
#define HWIO_GCC_BOOT_ROM_AHB_CBCR_HW_CTL_SHFT                                                            0x1

#define HWIO_GCC_TLMM_BCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0003a000)
#define HWIO_GCC_TLMM_BCR_RMSK                                                                            0x1
#define HWIO_GCC_TLMM_BCR_IN          \
        in_dword(HWIO_GCC_TLMM_BCR_ADDR)
#define HWIO_GCC_TLMM_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TLMM_BCR_ADDR, m)
#define HWIO_GCC_TLMM_BCR_OUT(v)      \
        out_dword(HWIO_GCC_TLMM_BCR_ADDR,v)
#define HWIO_GCC_TLMM_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TLMM_BCR_ADDR,m,v,HWIO_GCC_TLMM_BCR_IN)
#define HWIO_GCC_TLMM_BCR_BLK_ARES_BMSK                                                                   0x1
#define HWIO_GCC_TLMM_BCR_BLK_ARES_SHFT                                                                   0x0

#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0003a004)
#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_RMSK                                                          0x80100006
#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_TLMM_NORTH_AHB_CBCR_ADDR)
#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TLMM_NORTH_AHB_CBCR_ADDR, m)
#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_TLMM_NORTH_AHB_CBCR_ADDR,v)
#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TLMM_NORTH_AHB_CBCR_ADDR,m,v,HWIO_GCC_TLMM_NORTH_AHB_CBCR_IN)
#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_HW_CTL_BMSK                                                          0x2
#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_HW_CTL_SHFT                                                          0x1

#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0003a008)
#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_RMSK                                                          0x80100006
#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_TLMM_SOUTH_AHB_CBCR_ADDR)
#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TLMM_SOUTH_AHB_CBCR_ADDR, m)
#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_TLMM_SOUTH_AHB_CBCR_ADDR,v)
#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TLMM_SOUTH_AHB_CBCR_ADDR,m,v,HWIO_GCC_TLMM_SOUTH_AHB_CBCR_IN)
#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_HW_CTL_BMSK                                                          0x2
#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_HW_CTL_SHFT                                                          0x1

#define HWIO_GCC_TLMM_WEST_AHB_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0003a00c)
#define HWIO_GCC_TLMM_WEST_AHB_CBCR_RMSK                                                           0x80100006
#define HWIO_GCC_TLMM_WEST_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_TLMM_WEST_AHB_CBCR_ADDR)
#define HWIO_GCC_TLMM_WEST_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TLMM_WEST_AHB_CBCR_ADDR, m)
#define HWIO_GCC_TLMM_WEST_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_TLMM_WEST_AHB_CBCR_ADDR,v)
#define HWIO_GCC_TLMM_WEST_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TLMM_WEST_AHB_CBCR_ADDR,m,v,HWIO_GCC_TLMM_WEST_AHB_CBCR_IN)
#define HWIO_GCC_TLMM_WEST_AHB_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_TLMM_WEST_AHB_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_TLMM_WEST_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_TLMM_WEST_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_TLMM_WEST_AHB_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_TLMM_WEST_AHB_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_TLMM_WEST_AHB_CBCR_HW_CTL_BMSK                                                           0x2
#define HWIO_GCC_TLMM_WEST_AHB_CBCR_HW_CTL_SHFT                                                           0x1

#define HWIO_GCC_TLMM_CBCR_ADDR                                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0003a010)
#define HWIO_GCC_TLMM_CBCR_RMSK                                                                    0x80100004
#define HWIO_GCC_TLMM_CBCR_IN          \
        in_dword(HWIO_GCC_TLMM_CBCR_ADDR)
#define HWIO_GCC_TLMM_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TLMM_CBCR_ADDR, m)
#define HWIO_GCC_TLMM_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_TLMM_CBCR_ADDR,v)
#define HWIO_GCC_TLMM_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TLMM_CBCR_ADDR,m,v,HWIO_GCC_TLMM_CBCR_IN)
#define HWIO_GCC_TLMM_CBCR_CLK_OFF_BMSK                                                            0x80000000
#define HWIO_GCC_TLMM_CBCR_CLK_OFF_SHFT                                                                  0x1f
#define HWIO_GCC_TLMM_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                                  0x100000
#define HWIO_GCC_TLMM_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                      0x14
#define HWIO_GCC_TLMM_CBCR_CLK_ARES_BMSK                                                                  0x4
#define HWIO_GCC_TLMM_CBCR_CLK_ARES_SHFT                                                                  0x2

#define HWIO_GCC_AOSS_BCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0003c000)
#define HWIO_GCC_AOSS_BCR_RMSK                                                                            0x1
#define HWIO_GCC_AOSS_BCR_IN          \
        in_dword(HWIO_GCC_AOSS_BCR_ADDR)
#define HWIO_GCC_AOSS_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AOSS_BCR_ADDR, m)
#define HWIO_GCC_AOSS_BCR_OUT(v)      \
        out_dword(HWIO_GCC_AOSS_BCR_ADDR,v)
#define HWIO_GCC_AOSS_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AOSS_BCR_ADDR,m,v,HWIO_GCC_AOSS_BCR_IN)
#define HWIO_GCC_AOSS_BCR_BLK_ARES_BMSK                                                                   0x1
#define HWIO_GCC_AOSS_BCR_BLK_ARES_SHFT                                                                   0x0

#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0003c004)
#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_RMSK                                                         0x80100005
#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_ADDR)
#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_ADDR, m)
#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_ADDR,v)
#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_ADDR,m,v,HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_IN)
#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                       0x100000
#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                           0x14
#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_ARES_SHFT                                                       0x2
#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_AOSS_CNOC_M_AHB_CBCR_CLK_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0003c008)
#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_RMSK                                                         0x80100007
#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_ADDR)
#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_ADDR, m)
#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_ADDR,v)
#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_ADDR,m,v,HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_IN)
#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                       0x100000
#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                           0x14
#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_ARES_SHFT                                                       0x2
#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_HW_CTL_BMSK                                                         0x2
#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_HW_CTL_SHFT                                                         0x1
#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_AOSS_CNOC_S_AHB_CBCR_CLK_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_AOSS_AT_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0003c00c)
#define HWIO_GCC_AOSS_AT_CBCR_RMSK                                                                 0x80100005
#define HWIO_GCC_AOSS_AT_CBCR_IN          \
        in_dword(HWIO_GCC_AOSS_AT_CBCR_ADDR)
#define HWIO_GCC_AOSS_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AOSS_AT_CBCR_ADDR, m)
#define HWIO_GCC_AOSS_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AOSS_AT_CBCR_ADDR,v)
#define HWIO_GCC_AOSS_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AOSS_AT_CBCR_ADDR,m,v,HWIO_GCC_AOSS_AT_CBCR_IN)
#define HWIO_GCC_AOSS_AT_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_AOSS_AT_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_AOSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                               0x100000
#define HWIO_GCC_AOSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                   0x14
#define HWIO_GCC_AOSS_AT_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_AOSS_AT_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_AOSS_AT_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_AOSS_AT_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_SEC_CTRL_BCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0003d000)
#define HWIO_GCC_SEC_CTRL_BCR_RMSK                                                                        0x1
#define HWIO_GCC_SEC_CTRL_BCR_IN          \
        in_dword(HWIO_GCC_SEC_CTRL_BCR_ADDR)
#define HWIO_GCC_SEC_CTRL_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SEC_CTRL_BCR_ADDR, m)
#define HWIO_GCC_SEC_CTRL_BCR_OUT(v)      \
        out_dword(HWIO_GCC_SEC_CTRL_BCR_ADDR,v)
#define HWIO_GCC_SEC_CTRL_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SEC_CTRL_BCR_ADDR,m,v,HWIO_GCC_SEC_CTRL_BCR_IN)
#define HWIO_GCC_SEC_CTRL_BCR_BLK_ARES_BMSK                                                               0x1
#define HWIO_GCC_SEC_CTRL_BCR_BLK_ARES_SHFT                                                               0x0

#define HWIO_GCC_SEC_CTRL_ACC_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0003d004)
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_RMSK                                                            0x80007ff5
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_IN          \
        in_dword(HWIO_GCC_SEC_CTRL_ACC_CBCR_ADDR)
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SEC_CTRL_ACC_CBCR_ADDR, m)
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SEC_CTRL_ACC_CBCR_ADDR,v)
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SEC_CTRL_ACC_CBCR_ADDR,m,v,HWIO_GCC_SEC_CTRL_ACC_CBCR_IN)
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_FORCE_MEM_CORE_ON_BMSK                                              0x4000
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_FORCE_MEM_CORE_ON_SHFT                                                 0xe
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                            0x2000
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                               0xd
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                           0x1000
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                              0xc
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_WAKEUP_BMSK                                                          0xf00
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_WAKEUP_SHFT                                                            0x8
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_SLEEP_BMSK                                                            0xf0
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_SLEEP_SHFT                                                             0x4
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_SEC_CTRL_ACC_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_SEC_CTRL_AHB_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0003d008)
#define HWIO_GCC_SEC_CTRL_AHB_CBCR_RMSK                                                            0x80100007
#define HWIO_GCC_SEC_CTRL_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_SEC_CTRL_AHB_CBCR_ADDR)
#define HWIO_GCC_SEC_CTRL_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SEC_CTRL_AHB_CBCR_ADDR, m)
#define HWIO_GCC_SEC_CTRL_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SEC_CTRL_AHB_CBCR_ADDR,v)
#define HWIO_GCC_SEC_CTRL_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SEC_CTRL_AHB_CBCR_ADDR,m,v,HWIO_GCC_SEC_CTRL_AHB_CBCR_IN)
#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_SEC_CTRL_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                          0x100000
#define HWIO_GCC_SEC_CTRL_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                              0x14
#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_SEC_CTRL_AHB_CBCR_HW_CTL_BMSK                                                            0x2
#define HWIO_GCC_SEC_CTRL_AHB_CBCR_HW_CTL_SHFT                                                            0x1
#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_SEC_CTRL_AHB_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_SEC_CTRL_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0003d00c)
#define HWIO_GCC_SEC_CTRL_CBCR_RMSK                                                                0x80007ff5
#define HWIO_GCC_SEC_CTRL_CBCR_IN          \
        in_dword(HWIO_GCC_SEC_CTRL_CBCR_ADDR)
#define HWIO_GCC_SEC_CTRL_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SEC_CTRL_CBCR_ADDR, m)
#define HWIO_GCC_SEC_CTRL_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SEC_CTRL_CBCR_ADDR,v)
#define HWIO_GCC_SEC_CTRL_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SEC_CTRL_CBCR_ADDR,m,v,HWIO_GCC_SEC_CTRL_CBCR_IN)
#define HWIO_GCC_SEC_CTRL_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_SEC_CTRL_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_CORE_ON_BMSK                                                  0x4000
#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_CORE_ON_SHFT                                                     0xe
#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                                0x2000
#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                   0xd
#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                               0x1000
#define HWIO_GCC_SEC_CTRL_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                                  0xc
#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_BMSK                                                              0xf00
#define HWIO_GCC_SEC_CTRL_CBCR_WAKEUP_SHFT                                                                0x8
#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_BMSK                                                                0xf0
#define HWIO_GCC_SEC_CTRL_CBCR_SLEEP_SHFT                                                                 0x4
#define HWIO_GCC_SEC_CTRL_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_SEC_CTRL_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_SEC_CTRL_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_SEC_CTRL_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0003d010)
#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_RMSK                                                          0x80000005
#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_IN          \
        in_dword(HWIO_GCC_SEC_CTRL_SENSE_CBCR_ADDR)
#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SEC_CTRL_SENSE_CBCR_ADDR, m)
#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SEC_CTRL_SENSE_CBCR_ADDR,v)
#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SEC_CTRL_SENSE_CBCR_ADDR,m,v,HWIO_GCC_SEC_CTRL_SENSE_CBCR_IN)
#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_CLK_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0003d014)
#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_RMSK                                                 0x80100005
#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_IN          \
        in_dword(HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_ADDR)
#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_ADDR, m)
#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_ADDR,v)
#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_ADDR,m,v,HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_IN)
#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_OFF_BMSK                                         0x80000000
#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_OFF_SHFT                                               0x1f
#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                               0x100000
#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                   0x14
#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_ARES_BMSK                                               0x4
#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_ARES_SHFT                                               0x2
#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_ENABLE_BMSK                                             0x1
#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_CLK_ENABLE_SHFT                                             0x0

#define HWIO_GCC_ACC_CMD_RCGR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0003d018)
#define HWIO_GCC_ACC_CMD_RCGR_RMSK                                                                 0x80000013
#define HWIO_GCC_ACC_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_ACC_CMD_RCGR_ADDR)
#define HWIO_GCC_ACC_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_ACC_CMD_RCGR_ADDR, m)
#define HWIO_GCC_ACC_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_ACC_CMD_RCGR_ADDR,v)
#define HWIO_GCC_ACC_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_ACC_CMD_RCGR_ADDR,m,v,HWIO_GCC_ACC_CMD_RCGR_IN)
#define HWIO_GCC_ACC_CMD_RCGR_ROOT_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_ACC_CMD_RCGR_ROOT_OFF_SHFT                                                              0x1f
#define HWIO_GCC_ACC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                        0x10
#define HWIO_GCC_ACC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                         0x4
#define HWIO_GCC_ACC_CMD_RCGR_ROOT_EN_BMSK                                                                0x2
#define HWIO_GCC_ACC_CMD_RCGR_ROOT_EN_SHFT                                                                0x1
#define HWIO_GCC_ACC_CMD_RCGR_UPDATE_BMSK                                                                 0x1
#define HWIO_GCC_ACC_CMD_RCGR_UPDATE_SHFT                                                                 0x0

#define HWIO_GCC_ACC_CFG_RCGR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0003d01c)
#define HWIO_GCC_ACC_CFG_RCGR_RMSK                                                                   0x11071f
#define HWIO_GCC_ACC_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_ACC_CFG_RCGR_ADDR)
#define HWIO_GCC_ACC_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_ACC_CFG_RCGR_ADDR, m)
#define HWIO_GCC_ACC_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_ACC_CFG_RCGR_ADDR,v)
#define HWIO_GCC_ACC_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_ACC_CFG_RCGR_ADDR,m,v,HWIO_GCC_ACC_CFG_RCGR_IN)
#define HWIO_GCC_ACC_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                    0x100000
#define HWIO_GCC_ACC_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                        0x14
#define HWIO_GCC_ACC_CFG_RCGR_RCGLITE_DISABLE_BMSK                                                    0x10000
#define HWIO_GCC_ACC_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                       0x10
#define HWIO_GCC_ACC_CFG_RCGR_SRC_SEL_BMSK                                                              0x700
#define HWIO_GCC_ACC_CFG_RCGR_SRC_SEL_SHFT                                                                0x8
#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_BMSK                                                               0x1f
#define HWIO_GCC_ACC_CFG_RCGR_SRC_DIV_SHFT                                                                0x0

#define HWIO_GCC_SEC_CTRL_CMD_RCGR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0003d030)
#define HWIO_GCC_SEC_CTRL_CMD_RCGR_RMSK                                                            0x80000013
#define HWIO_GCC_SEC_CTRL_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_SEC_CTRL_CMD_RCGR_ADDR)
#define HWIO_GCC_SEC_CTRL_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SEC_CTRL_CMD_RCGR_ADDR, m)
#define HWIO_GCC_SEC_CTRL_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SEC_CTRL_CMD_RCGR_ADDR,v)
#define HWIO_GCC_SEC_CTRL_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SEC_CTRL_CMD_RCGR_ADDR,m,v,HWIO_GCC_SEC_CTRL_CMD_RCGR_IN)
#define HWIO_GCC_SEC_CTRL_CMD_RCGR_ROOT_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_SEC_CTRL_CMD_RCGR_ROOT_OFF_SHFT                                                         0x1f
#define HWIO_GCC_SEC_CTRL_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                   0x10
#define HWIO_GCC_SEC_CTRL_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                    0x4
#define HWIO_GCC_SEC_CTRL_CMD_RCGR_ROOT_EN_BMSK                                                           0x2
#define HWIO_GCC_SEC_CTRL_CMD_RCGR_ROOT_EN_SHFT                                                           0x1
#define HWIO_GCC_SEC_CTRL_CMD_RCGR_UPDATE_BMSK                                                            0x1
#define HWIO_GCC_SEC_CTRL_CMD_RCGR_UPDATE_SHFT                                                            0x0

#define HWIO_GCC_SEC_CTRL_CFG_RCGR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0003d034)
#define HWIO_GCC_SEC_CTRL_CFG_RCGR_RMSK                                                              0x11071f
#define HWIO_GCC_SEC_CTRL_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_SEC_CTRL_CFG_RCGR_ADDR)
#define HWIO_GCC_SEC_CTRL_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SEC_CTRL_CFG_RCGR_ADDR, m)
#define HWIO_GCC_SEC_CTRL_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SEC_CTRL_CFG_RCGR_ADDR,v)
#define HWIO_GCC_SEC_CTRL_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SEC_CTRL_CFG_RCGR_ADDR,m,v,HWIO_GCC_SEC_CTRL_CFG_RCGR_IN)
#define HWIO_GCC_SEC_CTRL_CFG_RCGR_HW_CLK_CONTROL_BMSK                                               0x100000
#define HWIO_GCC_SEC_CTRL_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                   0x14
#define HWIO_GCC_SEC_CTRL_CFG_RCGR_RCGLITE_DISABLE_BMSK                                               0x10000
#define HWIO_GCC_SEC_CTRL_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                  0x10
#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_SEL_BMSK                                                         0x700
#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_SEL_SHFT                                                           0x8
#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_BMSK                                                          0x1f
#define HWIO_GCC_SEC_CTRL_CFG_RCGR_SRC_DIV_SHFT                                                           0x0

#define HWIO_GCC_SPDM_BCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00040000)
#define HWIO_GCC_SPDM_BCR_RMSK                                                                            0x1
#define HWIO_GCC_SPDM_BCR_IN          \
        in_dword(HWIO_GCC_SPDM_BCR_ADDR)
#define HWIO_GCC_SPDM_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SPDM_BCR_ADDR, m)
#define HWIO_GCC_SPDM_BCR_OUT(v)      \
        out_dword(HWIO_GCC_SPDM_BCR_ADDR,v)
#define HWIO_GCC_SPDM_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPDM_BCR_ADDR,m,v,HWIO_GCC_SPDM_BCR_IN)
#define HWIO_GCC_SPDM_BCR_BLK_ARES_BMSK                                                                   0x1
#define HWIO_GCC_SPDM_BCR_BLK_ARES_SHFT                                                                   0x0

#define HWIO_GCC_SPDM_CFG_AHB_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00040004)
#define HWIO_GCC_SPDM_CFG_AHB_CBCR_RMSK                                                            0x80100007
#define HWIO_GCC_SPDM_CFG_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_SPDM_CFG_AHB_CBCR_ADDR)
#define HWIO_GCC_SPDM_CFG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SPDM_CFG_AHB_CBCR_ADDR, m)
#define HWIO_GCC_SPDM_CFG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SPDM_CFG_AHB_CBCR_ADDR,v)
#define HWIO_GCC_SPDM_CFG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPDM_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_SPDM_CFG_AHB_CBCR_IN)
#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_SPDM_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                          0x100000
#define HWIO_GCC_SPDM_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                              0x14
#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_SPDM_CFG_AHB_CBCR_HW_CTL_BMSK                                                            0x2
#define HWIO_GCC_SPDM_CFG_AHB_CBCR_HW_CTL_SHFT                                                            0x1
#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_SPDM_CFG_AHB_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00040008)
#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_RMSK                                                           0x80100005
#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_SPDM_MSTR_AHB_CBCR_ADDR)
#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SPDM_MSTR_AHB_CBCR_ADDR, m)
#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SPDM_MSTR_AHB_CBCR_ADDR,v)
#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPDM_MSTR_AHB_CBCR_ADDR,m,v,HWIO_GCC_SPDM_MSTR_AHB_CBCR_IN)
#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_SPDM_FF_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0004000c)
#define HWIO_GCC_SPDM_FF_CBCR_RMSK                                                                 0x80000005
#define HWIO_GCC_SPDM_FF_CBCR_IN          \
        in_dword(HWIO_GCC_SPDM_FF_CBCR_ADDR)
#define HWIO_GCC_SPDM_FF_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SPDM_FF_CBCR_ADDR, m)
#define HWIO_GCC_SPDM_FF_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SPDM_FF_CBCR_ADDR,v)
#define HWIO_GCC_SPDM_FF_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPDM_FF_CBCR_ADDR,m,v,HWIO_GCC_SPDM_FF_CBCR_IN)
#define HWIO_GCC_SPDM_FF_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_SPDM_FF_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_SPDM_FF_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_SPDM_FF_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_SPDM_FF_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_SPDM_FF_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00040010)
#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_RMSK                                                          0x80100005
#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IN          \
        in_dword(HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR)
#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR, m)
#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR,v)
#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR,m,v,HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IN)
#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_CLK_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00040014)
#define HWIO_GCC_SPDM_SNOC_CY_CBCR_RMSK                                                            0x80100005
#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IN          \
        in_dword(HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR)
#define HWIO_GCC_SPDM_SNOC_CY_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR, m)
#define HWIO_GCC_SPDM_SNOC_CY_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR,v)
#define HWIO_GCC_SPDM_SNOC_CY_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR,m,v,HWIO_GCC_SPDM_SNOC_CY_CBCR_IN)
#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                          0x100000
#define HWIO_GCC_SPDM_SNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                              0x14
#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_SPDM_SNOC_CY_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00040018)
#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_RMSK                                                           0x80000005
#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_IN          \
        in_dword(HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR)
#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR, m)
#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR,v)
#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR,m,v,HWIO_GCC_SPDM_DEBUG_CY_CBCR_IN)
#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004001c)
#define HWIO_GCC_SPDM_PNOC_CY_CBCR_RMSK                                                            0x80100005
#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IN          \
        in_dword(HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR)
#define HWIO_GCC_SPDM_PNOC_CY_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR, m)
#define HWIO_GCC_SPDM_PNOC_CY_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR,v)
#define HWIO_GCC_SPDM_PNOC_CY_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR,m,v,HWIO_GCC_SPDM_PNOC_CY_CBCR_IN)
#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                          0x100000
#define HWIO_GCC_SPDM_PNOC_CY_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                              0x14
#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_SPDM_PNOC_CY_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00040020)
#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_RMSK                                                                0x3
#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_IN          \
        in_dword(HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_ADDR)
#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_ADDR, m)
#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_ADDR,v)
#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_ADDR,m,v,HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_IN)
#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_CLK_DIV_BMSK                                                        0x3
#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_CLK_DIV_SHFT                                                        0x0

#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00040024)
#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_RMSK                                                                  0x3
#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_IN          \
        in_dword(HWIO_GCC_SPDM_SNOC_CY_CDIVR_ADDR)
#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_SPDM_SNOC_CY_CDIVR_ADDR, m)
#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_SPDM_SNOC_CY_CDIVR_ADDR,v)
#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPDM_SNOC_CY_CDIVR_ADDR,m,v,HWIO_GCC_SPDM_SNOC_CY_CDIVR_IN)
#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_CLK_DIV_BMSK                                                          0x3
#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_CLK_DIV_SHFT                                                          0x0

#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00040028)
#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_RMSK                                                                 0x3
#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_IN          \
        in_dword(HWIO_GCC_SPDM_DEBUG_CY_CDIVR_ADDR)
#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_SPDM_DEBUG_CY_CDIVR_ADDR, m)
#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_SPDM_DEBUG_CY_CDIVR_ADDR,v)
#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPDM_DEBUG_CY_CDIVR_ADDR,m,v,HWIO_GCC_SPDM_DEBUG_CY_CDIVR_IN)
#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_CLK_DIV_BMSK                                                         0x3
#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_CLK_DIV_SHFT                                                         0x0

#define HWIO_GCC_CE1_BCR_ADDR                                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00041000)
#define HWIO_GCC_CE1_BCR_RMSK                                                                             0x1
#define HWIO_GCC_CE1_BCR_IN          \
        in_dword(HWIO_GCC_CE1_BCR_ADDR)
#define HWIO_GCC_CE1_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CE1_BCR_ADDR, m)
#define HWIO_GCC_CE1_BCR_OUT(v)      \
        out_dword(HWIO_GCC_CE1_BCR_ADDR,v)
#define HWIO_GCC_CE1_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CE1_BCR_ADDR,m,v,HWIO_GCC_CE1_BCR_IN)
#define HWIO_GCC_CE1_BCR_BLK_ARES_BMSK                                                                    0x1
#define HWIO_GCC_CE1_BCR_BLK_ARES_SHFT                                                                    0x0

#define HWIO_GCC_CE1_CBCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00041004)
#define HWIO_GCC_CE1_CBCR_RMSK                                                                     0x80107ff4
#define HWIO_GCC_CE1_CBCR_IN          \
        in_dword(HWIO_GCC_CE1_CBCR_ADDR)
#define HWIO_GCC_CE1_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CE1_CBCR_ADDR, m)
#define HWIO_GCC_CE1_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CE1_CBCR_ADDR,v)
#define HWIO_GCC_CE1_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CE1_CBCR_ADDR,m,v,HWIO_GCC_CE1_CBCR_IN)
#define HWIO_GCC_CE1_CBCR_CLK_OFF_BMSK                                                             0x80000000
#define HWIO_GCC_CE1_CBCR_CLK_OFF_SHFT                                                                   0x1f
#define HWIO_GCC_CE1_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                                   0x100000
#define HWIO_GCC_CE1_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                       0x14
#define HWIO_GCC_CE1_CBCR_FORCE_MEM_CORE_ON_BMSK                                                       0x4000
#define HWIO_GCC_CE1_CBCR_FORCE_MEM_CORE_ON_SHFT                                                          0xe
#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                                     0x2000
#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                        0xd
#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                                    0x1000
#define HWIO_GCC_CE1_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                                       0xc
#define HWIO_GCC_CE1_CBCR_WAKEUP_BMSK                                                                   0xf00
#define HWIO_GCC_CE1_CBCR_WAKEUP_SHFT                                                                     0x8
#define HWIO_GCC_CE1_CBCR_SLEEP_BMSK                                                                     0xf0
#define HWIO_GCC_CE1_CBCR_SLEEP_SHFT                                                                      0x4
#define HWIO_GCC_CE1_CBCR_CLK_ARES_BMSK                                                                   0x4
#define HWIO_GCC_CE1_CBCR_CLK_ARES_SHFT                                                                   0x2

#define HWIO_GCC_CE1_AXI_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00041008)
#define HWIO_GCC_CE1_AXI_CBCR_RMSK                                                                 0x80100004
#define HWIO_GCC_CE1_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_CE1_AXI_CBCR_ADDR)
#define HWIO_GCC_CE1_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CE1_AXI_CBCR_ADDR, m)
#define HWIO_GCC_CE1_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CE1_AXI_CBCR_ADDR,v)
#define HWIO_GCC_CE1_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CE1_AXI_CBCR_ADDR,m,v,HWIO_GCC_CE1_AXI_CBCR_IN)
#define HWIO_GCC_CE1_AXI_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_CE1_AXI_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_CE1_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                               0x100000
#define HWIO_GCC_CE1_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                   0x14
#define HWIO_GCC_CE1_AXI_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_CE1_AXI_CBCR_CLK_ARES_SHFT                                                               0x2

#define HWIO_GCC_CE1_AHB_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0004100c)
#define HWIO_GCC_CE1_AHB_CBCR_RMSK                                                                 0x80100006
#define HWIO_GCC_CE1_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_CE1_AHB_CBCR_ADDR)
#define HWIO_GCC_CE1_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CE1_AHB_CBCR_ADDR, m)
#define HWIO_GCC_CE1_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CE1_AHB_CBCR_ADDR,v)
#define HWIO_GCC_CE1_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CE1_AHB_CBCR_ADDR,m,v,HWIO_GCC_CE1_AHB_CBCR_IN)
#define HWIO_GCC_CE1_AHB_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_CE1_AHB_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_CE1_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                               0x100000
#define HWIO_GCC_CE1_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                   0x14
#define HWIO_GCC_CE1_AHB_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_CE1_AHB_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_CE1_AHB_CBCR_HW_CTL_BMSK                                                                 0x2
#define HWIO_GCC_CE1_AHB_CBCR_HW_CTL_SHFT                                                                 0x1

#define HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00041024)
#define HWIO_GCC_RPMH_CE_CMD_DFSR_RMSK                                                                 0xffff
#define HWIO_GCC_RPMH_CE_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CMD_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CMD_DFSR_RCG_SW_CTRL_BMSK                                                     0x8000
#define HWIO_GCC_RPMH_CE_CMD_DFSR_RCG_SW_CTRL_SHFT                                                        0xf
#define HWIO_GCC_RPMH_CE_CMD_DFSR_SW_PERF_STATE_BMSK                                                   0x7800
#define HWIO_GCC_RPMH_CE_CMD_DFSR_SW_PERF_STATE_SHFT                                                      0xb
#define HWIO_GCC_RPMH_CE_CMD_DFSR_SW_OVERRIDE_BMSK                                                      0x400
#define HWIO_GCC_RPMH_CE_CMD_DFSR_SW_OVERRIDE_SHFT                                                        0xa
#define HWIO_GCC_RPMH_CE_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                         0x200
#define HWIO_GCC_RPMH_CE_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                           0x9
#define HWIO_GCC_RPMH_CE_CMD_DFSR_DFS_FSM_STATE_BMSK                                                    0x1c0
#define HWIO_GCC_RPMH_CE_CMD_DFSR_DFS_FSM_STATE_SHFT                                                      0x6
#define HWIO_GCC_RPMH_CE_CMD_DFSR_HW_CLK_CONTROL_BMSK                                                    0x20
#define HWIO_GCC_RPMH_CE_CMD_DFSR_HW_CLK_CONTROL_SHFT                                                     0x5
#define HWIO_GCC_RPMH_CE_CMD_DFSR_CURR_PERF_STATE_BMSK                                                   0x1e
#define HWIO_GCC_RPMH_CE_CMD_DFSR_CURR_PERF_STATE_SHFT                                                    0x1
#define HWIO_GCC_RPMH_CE_CMD_DFSR_DFS_EN_BMSK                                                             0x1
#define HWIO_GCC_RPMH_CE_CMD_DFSR_DFS_EN_SHFT                                                             0x0

#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0004102c)
#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_RMSK                                                            0x71f
#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_BMSK                                                    0x700
#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_SEL_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_BMSK                                                     0x1f
#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_SRC_DIV_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00041030)
#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_RMSK                                                            0x71f
#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_BMSK                                                    0x700
#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_SEL_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_BMSK                                                     0x1f
#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_SRC_DIV_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00041034)
#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_RMSK                                                            0x71f
#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_BMSK                                                    0x700
#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_SEL_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_BMSK                                                     0x1f
#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_SRC_DIV_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00041038)
#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_RMSK                                                            0x71f
#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_BMSK                                                    0x700
#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_SEL_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_BMSK                                                     0x1f
#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_SRC_DIV_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0004103c)
#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_RMSK                                                            0x71f
#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_BMSK                                                    0x700
#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_SEL_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_BMSK                                                     0x1f
#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_SRC_DIV_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00041040)
#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_RMSK                                                            0x71f
#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_BMSK                                                    0x700
#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_SEL_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_BMSK                                                     0x1f
#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_SRC_DIV_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00041044)
#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_RMSK                                                            0x71f
#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_BMSK                                                    0x700
#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_SEL_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_BMSK                                                     0x1f
#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_SRC_DIV_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00041048)
#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_RMSK                                                            0x71f
#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_BMSK                                                    0x700
#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_SEL_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_BMSK                                                     0x1f
#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_SRC_DIV_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0004104c)
#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_RMSK                                                            0x71f
#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_BMSK                                                    0x700
#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_SEL_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_BMSK                                                     0x1f
#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_SRC_DIV_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00041050)
#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_RMSK                                                            0x71f
#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_BMSK                                                    0x700
#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_SEL_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_BMSK                                                     0x1f
#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_SRC_DIV_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00041054)
#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_RMSK                                                           0x71f
#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00041058)
#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_RMSK                                                           0x71f
#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0004105c)
#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_RMSK                                                           0x71f
#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00041060)
#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_RMSK                                                           0x71f
#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00041064)
#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_RMSK                                                           0x71f
#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00041068)
#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_RMSK                                                           0x71f
#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_CE1_CMD_RCGR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00041010)
#define HWIO_GCC_CE1_CMD_RCGR_RMSK                                                                 0x80000013
#define HWIO_GCC_CE1_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_CE1_CMD_RCGR_ADDR)
#define HWIO_GCC_CE1_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_CE1_CMD_RCGR_ADDR, m)
#define HWIO_GCC_CE1_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_CE1_CMD_RCGR_ADDR,v)
#define HWIO_GCC_CE1_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CE1_CMD_RCGR_ADDR,m,v,HWIO_GCC_CE1_CMD_RCGR_IN)
#define HWIO_GCC_CE1_CMD_RCGR_ROOT_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_CE1_CMD_RCGR_ROOT_OFF_SHFT                                                              0x1f
#define HWIO_GCC_CE1_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                        0x10
#define HWIO_GCC_CE1_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                         0x4
#define HWIO_GCC_CE1_CMD_RCGR_ROOT_EN_BMSK                                                                0x2
#define HWIO_GCC_CE1_CMD_RCGR_ROOT_EN_SHFT                                                                0x1
#define HWIO_GCC_CE1_CMD_RCGR_UPDATE_BMSK                                                                 0x1
#define HWIO_GCC_CE1_CMD_RCGR_UPDATE_SHFT                                                                 0x0

#define HWIO_GCC_CE1_CFG_RCGR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00041014)
#define HWIO_GCC_CE1_CFG_RCGR_RMSK                                                                   0x11071f
#define HWIO_GCC_CE1_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_CE1_CFG_RCGR_ADDR)
#define HWIO_GCC_CE1_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_CE1_CFG_RCGR_ADDR, m)
#define HWIO_GCC_CE1_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_CE1_CFG_RCGR_ADDR,v)
#define HWIO_GCC_CE1_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CE1_CFG_RCGR_ADDR,m,v,HWIO_GCC_CE1_CFG_RCGR_IN)
#define HWIO_GCC_CE1_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                    0x100000
#define HWIO_GCC_CE1_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                        0x14
#define HWIO_GCC_CE1_CFG_RCGR_RCGLITE_DISABLE_BMSK                                                    0x10000
#define HWIO_GCC_CE1_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                       0x10
#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_BMSK                                                              0x700
#define HWIO_GCC_CE1_CFG_RCGR_SRC_SEL_SHFT                                                                0x8
#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_BMSK                                                               0x1f
#define HWIO_GCC_CE1_CFG_RCGR_SRC_DIV_SHFT                                                                0x0

#define HWIO_GCC_AHB_CBCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00043000)
#define HWIO_GCC_AHB_CBCR_RMSK                                                                     0x80100004
#define HWIO_GCC_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_AHB_CBCR_ADDR)
#define HWIO_GCC_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AHB_CBCR_ADDR, m)
#define HWIO_GCC_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AHB_CBCR_ADDR,v)
#define HWIO_GCC_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AHB_CBCR_ADDR,m,v,HWIO_GCC_AHB_CBCR_IN)
#define HWIO_GCC_AHB_CBCR_CLK_OFF_BMSK                                                             0x80000000
#define HWIO_GCC_AHB_CBCR_CLK_OFF_SHFT                                                                   0x1f
#define HWIO_GCC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                                   0x100000
#define HWIO_GCC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                       0x14
#define HWIO_GCC_AHB_CBCR_CLK_ARES_BMSK                                                                   0x4
#define HWIO_GCC_AHB_CBCR_CLK_ARES_SHFT                                                                   0x2

#define HWIO_GCC_XO_CBCR_ADDR                                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00043004)
#define HWIO_GCC_XO_CBCR_RMSK                                                                      0x80000005
#define HWIO_GCC_XO_CBCR_IN          \
        in_dword(HWIO_GCC_XO_CBCR_ADDR)
#define HWIO_GCC_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_XO_CBCR_ADDR, m)
#define HWIO_GCC_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_XO_CBCR_ADDR,v)
#define HWIO_GCC_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_XO_CBCR_ADDR,m,v,HWIO_GCC_XO_CBCR_IN)
#define HWIO_GCC_XO_CBCR_CLK_OFF_BMSK                                                              0x80000000
#define HWIO_GCC_XO_CBCR_CLK_OFF_SHFT                                                                    0x1f
#define HWIO_GCC_XO_CBCR_CLK_ARES_BMSK                                                                    0x4
#define HWIO_GCC_XO_CBCR_CLK_ARES_SHFT                                                                    0x2
#define HWIO_GCC_XO_CBCR_CLK_ENABLE_BMSK                                                                  0x1
#define HWIO_GCC_XO_CBCR_CLK_ENABLE_SHFT                                                                  0x0

#define HWIO_GCC_XO_DIV4_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00043008)
#define HWIO_GCC_XO_DIV4_CBCR_RMSK                                                                 0x80000005
#define HWIO_GCC_XO_DIV4_CBCR_IN          \
        in_dword(HWIO_GCC_XO_DIV4_CBCR_ADDR)
#define HWIO_GCC_XO_DIV4_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_XO_DIV4_CBCR_ADDR, m)
#define HWIO_GCC_XO_DIV4_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_XO_DIV4_CBCR_ADDR,v)
#define HWIO_GCC_XO_DIV4_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_XO_DIV4_CBCR_ADDR,m,v,HWIO_GCC_XO_DIV4_CBCR_IN)
#define HWIO_GCC_XO_DIV4_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_XO_DIV4_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_XO_DIV4_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_XO_DIV4_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_XO_DIV4_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_XO_DIV4_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0004300c)
#define HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_RMSK                                                    0x80000005
#define HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_IN          \
        in_dword(HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_ADDR)
#define HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_ADDR, m)
#define HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_ADDR,v)
#define HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_ADDR,m,v,HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_IN)
#define HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_FREQ_MEASUREMENT_REF_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_SLEEP_CBCR_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00043010)
#define HWIO_GCC_SLEEP_CBCR_RMSK                                                                   0x80000005
#define HWIO_GCC_SLEEP_CBCR_IN          \
        in_dword(HWIO_GCC_SLEEP_CBCR_ADDR)
#define HWIO_GCC_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SLEEP_CBCR_ADDR, m)
#define HWIO_GCC_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SLEEP_CBCR_ADDR,v)
#define HWIO_GCC_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SLEEP_CBCR_ADDR,m,v,HWIO_GCC_SLEEP_CBCR_IN)
#define HWIO_GCC_SLEEP_CBCR_CLK_OFF_BMSK                                                           0x80000000
#define HWIO_GCC_SLEEP_CBCR_CLK_OFF_SHFT                                                                 0x1f
#define HWIO_GCC_SLEEP_CBCR_CLK_ARES_BMSK                                                                 0x4
#define HWIO_GCC_SLEEP_CBCR_CLK_ARES_SHFT                                                                 0x2
#define HWIO_GCC_SLEEP_CBCR_CLK_ENABLE_BMSK                                                               0x1
#define HWIO_GCC_SLEEP_CBCR_CLK_ENABLE_SHFT                                                               0x0

#define HWIO_GCC_XO_DIV4_CDIVR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00043014)
#define HWIO_GCC_XO_DIV4_CDIVR_RMSK                                                                       0xf
#define HWIO_GCC_XO_DIV4_CDIVR_IN          \
        in_dword(HWIO_GCC_XO_DIV4_CDIVR_ADDR)
#define HWIO_GCC_XO_DIV4_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_XO_DIV4_CDIVR_ADDR, m)
#define HWIO_GCC_XO_DIV4_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_XO_DIV4_CDIVR_ADDR,v)
#define HWIO_GCC_XO_DIV4_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_XO_DIV4_CDIVR_ADDR,m,v,HWIO_GCC_XO_DIV4_CDIVR_IN)
#define HWIO_GCC_XO_DIV4_CDIVR_CLK_DIV_BMSK                                                               0xf
#define HWIO_GCC_XO_DIV4_CDIVR_CLK_DIV_SHFT                                                               0x0

#define HWIO_GCC_SLEEP_CMD_RCGR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00043018)
#define HWIO_GCC_SLEEP_CMD_RCGR_RMSK                                                               0x80000013
#define HWIO_GCC_SLEEP_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_SLEEP_CMD_RCGR_ADDR)
#define HWIO_GCC_SLEEP_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SLEEP_CMD_RCGR_ADDR, m)
#define HWIO_GCC_SLEEP_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SLEEP_CMD_RCGR_ADDR,v)
#define HWIO_GCC_SLEEP_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SLEEP_CMD_RCGR_ADDR,m,v,HWIO_GCC_SLEEP_CMD_RCGR_IN)
#define HWIO_GCC_SLEEP_CMD_RCGR_ROOT_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_SLEEP_CMD_RCGR_ROOT_OFF_SHFT                                                            0x1f
#define HWIO_GCC_SLEEP_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                      0x10
#define HWIO_GCC_SLEEP_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                       0x4
#define HWIO_GCC_SLEEP_CMD_RCGR_ROOT_EN_BMSK                                                              0x2
#define HWIO_GCC_SLEEP_CMD_RCGR_ROOT_EN_SHFT                                                              0x1
#define HWIO_GCC_SLEEP_CMD_RCGR_UPDATE_BMSK                                                               0x1
#define HWIO_GCC_SLEEP_CMD_RCGR_UPDATE_SHFT                                                               0x0

#define HWIO_GCC_SLEEP_CFG_RCGR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0004301c)
#define HWIO_GCC_SLEEP_CFG_RCGR_RMSK                                                                 0x11071f
#define HWIO_GCC_SLEEP_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_SLEEP_CFG_RCGR_ADDR)
#define HWIO_GCC_SLEEP_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SLEEP_CFG_RCGR_ADDR, m)
#define HWIO_GCC_SLEEP_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SLEEP_CFG_RCGR_ADDR,v)
#define HWIO_GCC_SLEEP_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SLEEP_CFG_RCGR_ADDR,m,v,HWIO_GCC_SLEEP_CFG_RCGR_IN)
#define HWIO_GCC_SLEEP_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                  0x100000
#define HWIO_GCC_SLEEP_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                      0x14
#define HWIO_GCC_SLEEP_CFG_RCGR_RCGLITE_DISABLE_BMSK                                                  0x10000
#define HWIO_GCC_SLEEP_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                     0x10
#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_BMSK                                                            0x700
#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_SEL_SHFT                                                              0x8
#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_BMSK                                                             0x1f
#define HWIO_GCC_SLEEP_CFG_RCGR_SRC_DIV_SHFT                                                              0x0

#define HWIO_GCC_XO_CMD_RCGR_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00043030)
#define HWIO_GCC_XO_CMD_RCGR_RMSK                                                                  0x80000013
#define HWIO_GCC_XO_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_XO_CMD_RCGR_ADDR)
#define HWIO_GCC_XO_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_XO_CMD_RCGR_ADDR, m)
#define HWIO_GCC_XO_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_XO_CMD_RCGR_ADDR,v)
#define HWIO_GCC_XO_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_XO_CMD_RCGR_ADDR,m,v,HWIO_GCC_XO_CMD_RCGR_IN)
#define HWIO_GCC_XO_CMD_RCGR_ROOT_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_XO_CMD_RCGR_ROOT_OFF_SHFT                                                               0x1f
#define HWIO_GCC_XO_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                         0x10
#define HWIO_GCC_XO_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                          0x4
#define HWIO_GCC_XO_CMD_RCGR_ROOT_EN_BMSK                                                                 0x2
#define HWIO_GCC_XO_CMD_RCGR_ROOT_EN_SHFT                                                                 0x1
#define HWIO_GCC_XO_CMD_RCGR_UPDATE_BMSK                                                                  0x1
#define HWIO_GCC_XO_CMD_RCGR_UPDATE_SHFT                                                                  0x0

#define HWIO_GCC_XO_CFG_RCGR_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00043034)
#define HWIO_GCC_XO_CFG_RCGR_RMSK                                                                    0x11071f
#define HWIO_GCC_XO_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_XO_CFG_RCGR_ADDR)
#define HWIO_GCC_XO_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_XO_CFG_RCGR_ADDR, m)
#define HWIO_GCC_XO_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_XO_CFG_RCGR_ADDR,v)
#define HWIO_GCC_XO_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_XO_CFG_RCGR_ADDR,m,v,HWIO_GCC_XO_CFG_RCGR_IN)
#define HWIO_GCC_XO_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                     0x100000
#define HWIO_GCC_XO_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                         0x14
#define HWIO_GCC_XO_CFG_RCGR_RCGLITE_DISABLE_BMSK                                                     0x10000
#define HWIO_GCC_XO_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                        0x10
#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_BMSK                                                               0x700
#define HWIO_GCC_XO_CFG_RCGR_SRC_SEL_SHFT                                                                 0x8
#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_BMSK                                                                0x1f
#define HWIO_GCC_XO_CFG_RCGR_SRC_DIV_SHFT                                                                 0x0

#define HWIO_GCC_DDRSS_BCR_ADDR                                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00044000)
#define HWIO_GCC_DDRSS_BCR_RMSK                                                                           0x1
#define HWIO_GCC_DDRSS_BCR_IN          \
        in_dword(HWIO_GCC_DDRSS_BCR_ADDR)
#define HWIO_GCC_DDRSS_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRSS_BCR_ADDR, m)
#define HWIO_GCC_DDRSS_BCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRSS_BCR_ADDR,v)
#define HWIO_GCC_DDRSS_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRSS_BCR_ADDR,m,v,HWIO_GCC_DDRSS_BCR_IN)
#define HWIO_GCC_DDRSS_BCR_BLK_ARES_BMSK                                                                  0x1
#define HWIO_GCC_DDRSS_BCR_BLK_ARES_SHFT                                                                  0x0

#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x000092a8)
#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_RMSK                                                       0x80100005
#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_IN          \
        in_dword(HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_ADDR)
#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_ADDR, m)
#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_ADDR,v)
#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_IN)
#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                     0x100000
#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                         0x14
#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x000092ac)
#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_RMSK                                                       0x80100005
#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_IN          \
        in_dword(HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_ADDR)
#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_ADDR, m)
#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_ADDR,v)
#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_IN)
#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                     0x100000
#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                         0x14
#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_DDRSS_TCU_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00083140)
#define HWIO_GCC_DDRSS_TCU_CBCR_RMSK                                                               0x80100005
#define HWIO_GCC_DDRSS_TCU_CBCR_IN          \
        in_dword(HWIO_GCC_DDRSS_TCU_CBCR_ADDR)
#define HWIO_GCC_DDRSS_TCU_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRSS_TCU_CBCR_ADDR, m)
#define HWIO_GCC_DDRSS_TCU_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRSS_TCU_CBCR_ADDR,v)
#define HWIO_GCC_DDRSS_TCU_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRSS_TCU_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_TCU_CBCR_IN)
#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_DDRSS_TCU_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                             0x100000
#define HWIO_GCC_DDRSS_TCU_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                 0x14
#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ARES_SHFT                                                             0x2
#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_DDRSS_TCU_CBCR_CLK_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00045284)
#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_RMSK                                                        0x80100005
#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_DDRSS_TURING_AXI_CBCR_ADDR)
#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRSS_TURING_AXI_CBCR_ADDR, m)
#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRSS_TURING_AXI_CBCR_ADDR,v)
#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRSS_TURING_AXI_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_TURING_AXI_CBCR_IN)
#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                      0x100000
#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                          0x14
#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a154)
#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_RMSK                                                        0x80100005
#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_ADDR)
#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_ADDR, m)
#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_ADDR,v)
#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_IN)
#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                      0x100000
#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                          0x14
#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00071154)
#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_RMSK                                                           0x80100005
#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_DDRSS_GPU_AXI_CBCR_ADDR)
#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRSS_GPU_AXI_CBCR_ADDR, m)
#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRSS_GPU_AXI_CBCR_ADDR,v)
#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRSS_GPU_AXI_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_GPU_AXI_CBCR_IN)
#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d058)
#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_RMSK                                                       0x80100005
#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_IN          \
        in_dword(HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_ADDR)
#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_ADDR, m)
#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_ADDR,v)
#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_IN)
#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                     0x100000
#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                         0x14
#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00044004)
#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_RMSK                                                    0x80100005
#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_ADDR)
#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_ADDR, m)
#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_ADDR,v)
#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_IN)
#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                  0x100000
#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                      0x14
#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00044008)
#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_RMSK                                                    0x80100005
#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_ADDR)
#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_ADDR, m)
#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_ADDR,v)
#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_IN)
#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                  0x100000
#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                      0x14
#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0004400c)
#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_RMSK                                                 0x80100005
#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_ADDR)
#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_ADDR, m)
#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_ADDR,v)
#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_IN)
#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_CLK_OFF_BMSK                                         0x80000000
#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_CLK_OFF_SHFT                                               0x1f
#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                               0x100000
#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                   0x14
#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_CLK_ARES_BMSK                                               0x4
#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_CLK_ARES_SHFT                                               0x2
#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_CLK_ENABLE_BMSK                                             0x1
#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_CLK_ENABLE_SHFT                                             0x0

#define HWIO_GCC_DDRSS_XO_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00044010)
#define HWIO_GCC_DDRSS_XO_CBCR_RMSK                                                                0x80000005
#define HWIO_GCC_DDRSS_XO_CBCR_IN          \
        in_dword(HWIO_GCC_DDRSS_XO_CBCR_ADDR)
#define HWIO_GCC_DDRSS_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRSS_XO_CBCR_ADDR, m)
#define HWIO_GCC_DDRSS_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRSS_XO_CBCR_ADDR,v)
#define HWIO_GCC_DDRSS_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRSS_XO_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_XO_CBCR_IN)
#define HWIO_GCC_DDRSS_XO_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_DDRSS_XO_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_DDRSS_XO_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_DDRSS_XO_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_DDRSS_XO_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_DDRSS_XO_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00044014)
#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_RMSK                                                           0x80100005
#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR)
#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR, m)
#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR,v)
#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_CFG_AHB_CBCR_IN)
#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_DDRSS_SLEEP_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00044018)
#define HWIO_GCC_DDRSS_SLEEP_CBCR_RMSK                                                             0x80000005
#define HWIO_GCC_DDRSS_SLEEP_CBCR_IN          \
        in_dword(HWIO_GCC_DDRSS_SLEEP_CBCR_ADDR)
#define HWIO_GCC_DDRSS_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRSS_SLEEP_CBCR_ADDR, m)
#define HWIO_GCC_DDRSS_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRSS_SLEEP_CBCR_ADDR,v)
#define HWIO_GCC_DDRSS_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRSS_SLEEP_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_SLEEP_CBCR_IN)
#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_DDRSS_SLEEP_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_MEMNOC_CBCR_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0004401c)
#define HWIO_GCC_MEMNOC_CBCR_RMSK                                                                  0x80100005
#define HWIO_GCC_MEMNOC_CBCR_IN          \
        in_dword(HWIO_GCC_MEMNOC_CBCR_ADDR)
#define HWIO_GCC_MEMNOC_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MEMNOC_CBCR_ADDR, m)
#define HWIO_GCC_MEMNOC_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MEMNOC_CBCR_ADDR,v)
#define HWIO_GCC_MEMNOC_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MEMNOC_CBCR_ADDR,m,v,HWIO_GCC_MEMNOC_CBCR_IN)
#define HWIO_GCC_MEMNOC_CBCR_CLK_OFF_BMSK                                                          0x80000000
#define HWIO_GCC_MEMNOC_CBCR_CLK_OFF_SHFT                                                                0x1f
#define HWIO_GCC_MEMNOC_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                                0x100000
#define HWIO_GCC_MEMNOC_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                    0x14
#define HWIO_GCC_MEMNOC_CBCR_CLK_ARES_BMSK                                                                0x4
#define HWIO_GCC_MEMNOC_CBCR_CLK_ARES_SHFT                                                                0x2
#define HWIO_GCC_MEMNOC_CBCR_CLK_ENABLE_BMSK                                                              0x1
#define HWIO_GCC_MEMNOC_CBCR_CLK_ENABLE_SHFT                                                              0x0

#define HWIO_GCC_DDRSS_AT_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00044020)
#define HWIO_GCC_DDRSS_AT_CBCR_RMSK                                                                0x80100005
#define HWIO_GCC_DDRSS_AT_CBCR_IN          \
        in_dword(HWIO_GCC_DDRSS_AT_CBCR_ADDR)
#define HWIO_GCC_DDRSS_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRSS_AT_CBCR_ADDR, m)
#define HWIO_GCC_DDRSS_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRSS_AT_CBCR_ADDR,v)
#define HWIO_GCC_DDRSS_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRSS_AT_CBCR_ADDR,m,v,HWIO_GCC_DDRSS_AT_CBCR_IN)
#define HWIO_GCC_DDRSS_AT_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_DDRSS_AT_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_DDRSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_DDRSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_DDRSS_AT_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00044040)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_RMSK                                                       0x71f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00044044)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_RMSK                                                       0x71f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00044048)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_RMSK                                                       0x71f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0004404c)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_RMSK                                                       0x71f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00044050)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_RMSK                                                       0x71f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00044054)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_RMSK                                                       0x71f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00044058)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_RMSK                                                       0x71f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0004405c)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_RMSK                                                       0x71f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00044060)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_RMSK                                                       0x71f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00044064)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_RMSK                                                       0x71f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00044068)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_RMSK                                                      0x71f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0004406c)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_RMSK                                                      0x71f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00044070)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_RMSK                                                      0x71f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00044074)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_RMSK                                                      0x71f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00044078)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_RMSK                                                      0x71f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0004407c)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_RMSK                                                      0x71f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_MEMNOC_CMD_RCGR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00044024)
#define HWIO_GCC_MEMNOC_CMD_RCGR_RMSK                                                              0x80000013
#define HWIO_GCC_MEMNOC_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_MEMNOC_CMD_RCGR_ADDR)
#define HWIO_GCC_MEMNOC_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MEMNOC_CMD_RCGR_ADDR, m)
#define HWIO_GCC_MEMNOC_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_MEMNOC_CMD_RCGR_ADDR,v)
#define HWIO_GCC_MEMNOC_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MEMNOC_CMD_RCGR_ADDR,m,v,HWIO_GCC_MEMNOC_CMD_RCGR_IN)
#define HWIO_GCC_MEMNOC_CMD_RCGR_ROOT_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_MEMNOC_CMD_RCGR_ROOT_OFF_SHFT                                                           0x1f
#define HWIO_GCC_MEMNOC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                     0x10
#define HWIO_GCC_MEMNOC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                      0x4
#define HWIO_GCC_MEMNOC_CMD_RCGR_ROOT_EN_BMSK                                                             0x2
#define HWIO_GCC_MEMNOC_CMD_RCGR_ROOT_EN_SHFT                                                             0x1
#define HWIO_GCC_MEMNOC_CMD_RCGR_UPDATE_BMSK                                                              0x1
#define HWIO_GCC_MEMNOC_CMD_RCGR_UPDATE_SHFT                                                              0x0

#define HWIO_GCC_MEMNOC_CFG_RCGR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00044028)
#define HWIO_GCC_MEMNOC_CFG_RCGR_RMSK                                                                0x11071f
#define HWIO_GCC_MEMNOC_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_MEMNOC_CFG_RCGR_ADDR)
#define HWIO_GCC_MEMNOC_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MEMNOC_CFG_RCGR_ADDR, m)
#define HWIO_GCC_MEMNOC_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_MEMNOC_CFG_RCGR_ADDR,v)
#define HWIO_GCC_MEMNOC_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MEMNOC_CFG_RCGR_ADDR,m,v,HWIO_GCC_MEMNOC_CFG_RCGR_IN)
#define HWIO_GCC_MEMNOC_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                 0x100000
#define HWIO_GCC_MEMNOC_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                     0x14
#define HWIO_GCC_MEMNOC_CFG_RCGR_RCGLITE_DISABLE_BMSK                                                 0x10000
#define HWIO_GCC_MEMNOC_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                    0x10
#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_BMSK                                                           0x700
#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_SEL_SHFT                                                             0x8
#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_BMSK                                                            0x1f
#define HWIO_GCC_MEMNOC_CFG_RCGR_SRC_DIV_SHFT                                                             0x0

#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00044164)
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_RMSK                                                               0xffff
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_CMD_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_RCG_SW_CTRL_BMSK                                                   0x8000
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_RCG_SW_CTRL_SHFT                                                      0xf
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_SW_PERF_STATE_BMSK                                                 0x7800
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_SW_PERF_STATE_SHFT                                                    0xb
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_SW_OVERRIDE_BMSK                                                    0x400
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_SW_OVERRIDE_SHFT                                                      0xa
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                       0x200
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                         0x9
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_DFS_FSM_STATE_BMSK                                                  0x1c0
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_DFS_FSM_STATE_SHFT                                                    0x6
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_HW_CLK_CONTROL_BMSK                                                  0x20
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_HW_CLK_CONTROL_SHFT                                                   0x5
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_CURR_PERF_STATE_BMSK                                                 0x1e
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_CURR_PERF_STATE_SHFT                                                  0x1
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_DFS_EN_BMSK                                                           0x1
#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_DFS_EN_SHFT                                                           0x0

#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0004416c)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_RMSK                                                         0x71f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_BMSK                                                 0x700
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_SEL_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_SRC_DIV_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00044170)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_RMSK                                                         0x71f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_BMSK                                                 0x700
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_SEL_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_SRC_DIV_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00044174)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_RMSK                                                         0x71f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_BMSK                                                 0x700
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_SEL_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_SRC_DIV_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00044178)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_RMSK                                                         0x71f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_BMSK                                                 0x700
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_SEL_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_SRC_DIV_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0004417c)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_RMSK                                                         0x71f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_BMSK                                                 0x700
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_SEL_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_SRC_DIV_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00044180)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_RMSK                                                         0x71f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_BMSK                                                 0x700
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_SEL_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_SRC_DIV_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00044184)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_RMSK                                                         0x71f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_BMSK                                                 0x700
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_SEL_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_SRC_DIV_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00044188)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_RMSK                                                         0x71f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_BMSK                                                 0x700
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_SEL_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_SRC_DIV_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0004418c)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_RMSK                                                         0x71f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_BMSK                                                 0x700
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_SEL_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_SRC_DIV_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00044190)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_RMSK                                                         0x71f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_BMSK                                                 0x700
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_SEL_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_SRC_DIV_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00044194)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_RMSK                                                        0x71f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00044198)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_RMSK                                                        0x71f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0004419c)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_RMSK                                                        0x71f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000441a0)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_RMSK                                                        0x71f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000441a4)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_RMSK                                                        0x71f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000441a8)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_RMSK                                                        0x71f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_SHRM_CMD_RCGR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00044150)
#define HWIO_GCC_SHRM_CMD_RCGR_RMSK                                                                0x80000013
#define HWIO_GCC_SHRM_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_SHRM_CMD_RCGR_ADDR)
#define HWIO_GCC_SHRM_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SHRM_CMD_RCGR_ADDR, m)
#define HWIO_GCC_SHRM_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SHRM_CMD_RCGR_ADDR,v)
#define HWIO_GCC_SHRM_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SHRM_CMD_RCGR_ADDR,m,v,HWIO_GCC_SHRM_CMD_RCGR_IN)
#define HWIO_GCC_SHRM_CMD_RCGR_ROOT_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_SHRM_CMD_RCGR_ROOT_OFF_SHFT                                                             0x1f
#define HWIO_GCC_SHRM_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                       0x10
#define HWIO_GCC_SHRM_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                        0x4
#define HWIO_GCC_SHRM_CMD_RCGR_ROOT_EN_BMSK                                                               0x2
#define HWIO_GCC_SHRM_CMD_RCGR_ROOT_EN_SHFT                                                               0x1
#define HWIO_GCC_SHRM_CMD_RCGR_UPDATE_BMSK                                                                0x1
#define HWIO_GCC_SHRM_CMD_RCGR_UPDATE_SHFT                                                                0x0

#define HWIO_GCC_SHRM_CFG_RCGR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00044154)
#define HWIO_GCC_SHRM_CFG_RCGR_RMSK                                                                  0x11071f
#define HWIO_GCC_SHRM_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_SHRM_CFG_RCGR_ADDR)
#define HWIO_GCC_SHRM_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_SHRM_CFG_RCGR_ADDR, m)
#define HWIO_GCC_SHRM_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_SHRM_CFG_RCGR_ADDR,v)
#define HWIO_GCC_SHRM_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SHRM_CFG_RCGR_ADDR,m,v,HWIO_GCC_SHRM_CFG_RCGR_IN)
#define HWIO_GCC_SHRM_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                   0x100000
#define HWIO_GCC_SHRM_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                       0x14
#define HWIO_GCC_SHRM_CFG_RCGR_RCGLITE_DISABLE_BMSK                                                   0x10000
#define HWIO_GCC_SHRM_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                      0x10
#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_BMSK                                                             0x700
#define HWIO_GCC_SHRM_CFG_RCGR_SRC_SEL_SHFT                                                               0x8
#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_BMSK                                                              0x1f
#define HWIO_GCC_SHRM_CFG_RCGR_SRC_DIV_SHFT                                                               0x0

#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0004427c)
#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_RMSK                                                                  0x1
#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_SHRM_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00044280)
#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_RMSK                                                                0x1
#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_SHRM_CBCR_ADDR                                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00044284)
#define HWIO_GCC_SHRM_CBCR_RMSK                                                                    0x80100005
#define HWIO_GCC_SHRM_CBCR_IN          \
        in_dword(HWIO_GCC_SHRM_CBCR_ADDR)
#define HWIO_GCC_SHRM_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SHRM_CBCR_ADDR, m)
#define HWIO_GCC_SHRM_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SHRM_CBCR_ADDR,v)
#define HWIO_GCC_SHRM_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SHRM_CBCR_ADDR,m,v,HWIO_GCC_SHRM_CBCR_IN)
#define HWIO_GCC_SHRM_CBCR_CLK_OFF_BMSK                                                            0x80000000
#define HWIO_GCC_SHRM_CBCR_CLK_OFF_SHFT                                                                  0x1f
#define HWIO_GCC_SHRM_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                                  0x100000
#define HWIO_GCC_SHRM_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                      0x14
#define HWIO_GCC_SHRM_CBCR_CLK_ARES_BMSK                                                                  0x4
#define HWIO_GCC_SHRM_CBCR_CLK_ARES_SHFT                                                                  0x2
#define HWIO_GCC_SHRM_CBCR_CLK_ENABLE_BMSK                                                                0x1
#define HWIO_GCC_SHRM_CBCR_CLK_ENABLE_SHFT                                                                0x0

#define HWIO_GCC_DDRMC_CH0_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00044288)
#define HWIO_GCC_DDRMC_CH0_CBCR_RMSK                                                               0x80100005
#define HWIO_GCC_DDRMC_CH0_CBCR_IN          \
        in_dword(HWIO_GCC_DDRMC_CH0_CBCR_ADDR)
#define HWIO_GCC_DDRMC_CH0_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRMC_CH0_CBCR_ADDR, m)
#define HWIO_GCC_DDRMC_CH0_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRMC_CH0_CBCR_ADDR,v)
#define HWIO_GCC_DDRMC_CH0_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRMC_CH0_CBCR_ADDR,m,v,HWIO_GCC_DDRMC_CH0_CBCR_IN)
#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_DDRMC_CH0_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                             0x100000
#define HWIO_GCC_DDRMC_CH0_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                 0x14
#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_ARES_SHFT                                                             0x2
#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_DDRMC_CH0_CBCR_CLK_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_DDRMC_CH1_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0004428c)
#define HWIO_GCC_DDRMC_CH1_CBCR_RMSK                                                               0x80100005
#define HWIO_GCC_DDRMC_CH1_CBCR_IN          \
        in_dword(HWIO_GCC_DDRMC_CH1_CBCR_ADDR)
#define HWIO_GCC_DDRMC_CH1_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRMC_CH1_CBCR_ADDR, m)
#define HWIO_GCC_DDRMC_CH1_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DDRMC_CH1_CBCR_ADDR,v)
#define HWIO_GCC_DDRMC_CH1_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRMC_CH1_CBCR_ADDR,m,v,HWIO_GCC_DDRMC_CH1_CBCR_IN)
#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_DDRMC_CH1_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                             0x100000
#define HWIO_GCC_DDRMC_CH1_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                 0x14
#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_ARES_SHFT                                                             0x2
#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_DDRMC_CH1_CBCR_CLK_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000442a4)
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_RMSK                                                          0xffff
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_RCG_SW_CTRL_BMSK                                              0x8000
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_RCG_SW_CTRL_SHFT                                                 0xf
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_SW_PERF_STATE_BMSK                                            0x7800
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_SW_PERF_STATE_SHFT                                               0xb
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_SW_OVERRIDE_BMSK                                               0x400
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_SW_OVERRIDE_SHFT                                                 0xa
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                  0x200
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                    0x9
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_DFS_FSM_STATE_BMSK                                             0x1c0
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_DFS_FSM_STATE_SHFT                                               0x6
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_HW_CLK_CONTROL_BMSK                                             0x20
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_HW_CLK_CONTROL_SHFT                                              0x5
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_CURR_PERF_STATE_BMSK                                            0x1e
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_CURR_PERF_STATE_SHFT                                             0x1
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_DFS_EN_BMSK                                                      0x1
#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_DFS_EN_SHFT                                                      0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000442ac)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000442b0)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000442b4)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000442b8)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000442bc)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000442c0)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000442c4)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000442c8)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000442cc)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000442d0)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000442d4)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000442d8)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000442dc)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000442e0)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000442e4)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000442e8)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00044290)
#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_RMSK                                                      0x80000013
#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ADDR)
#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ADDR, m)
#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ADDR,v)
#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ADDR,m,v,HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_IN)
#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00044294)
#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_RMSK                                                        0x11071f
#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_ADDR)
#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_ADDR, m)
#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_ADDR,v)
#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_ADDR,m,v,HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_IN)
#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_RCGLITE_DISABLE_BMSK                                         0x10000
#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_RCGLITE_DISABLE_SHFT                                            0x10
#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x000443bc)
#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_RMSK                                                        0x1
#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                             0x1
#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                             0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000443d4)
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_RMSK                                                          0xffff
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_RCG_SW_CTRL_BMSK                                              0x8000
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_RCG_SW_CTRL_SHFT                                                 0xf
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_SW_PERF_STATE_BMSK                                            0x7800
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_SW_PERF_STATE_SHFT                                               0xb
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_SW_OVERRIDE_BMSK                                               0x400
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_SW_OVERRIDE_SHFT                                                 0xa
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                  0x200
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                    0x9
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_DFS_FSM_STATE_BMSK                                             0x1c0
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_DFS_FSM_STATE_SHFT                                               0x6
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_HW_CLK_CONTROL_BMSK                                             0x20
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_HW_CLK_CONTROL_SHFT                                              0x5
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_CURR_PERF_STATE_BMSK                                            0x1e
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_CURR_PERF_STATE_SHFT                                             0x1
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_DFS_EN_BMSK                                                      0x1
#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_DFS_EN_SHFT                                                      0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000443dc)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000443e0)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000443e4)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000443e8)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000443ec)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000443f0)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000443f4)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000443f8)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000443fc)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00044400)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_RMSK                                          0x71f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_SEL_BMSK                                  0x700
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_SEL_SHFT                                    0x8
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_BMSK                                   0x1f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_SRC_DIV_SHFT                                    0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00044404)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00044408)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0004440c)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00044410)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00044414)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00044418)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000443c0)
#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_RMSK                                                      0x80000013
#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ADDR)
#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ADDR, m)
#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ADDR,v)
#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ADDR,m,v,HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_IN)
#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000443c4)
#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_RMSK                                                        0x11071f
#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_ADDR)
#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_ADDR, m)
#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_ADDR,v)
#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_ADDR,m,v,HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_IN)
#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_RCGLITE_DISABLE_BMSK                                         0x10000
#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_RCGLITE_DISABLE_SHFT                                            0x10
#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x000444ec)
#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_RMSK                                                        0x1
#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                             0x1
#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                             0x0

#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00047000)
#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_RMSK                                                         0x80100005
#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_IN          \
        in_dword(HWIO_GCC_LPASS_CORE_AXIM_CBCR_ADDR)
#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_LPASS_CORE_AXIM_CBCR_ADDR, m)
#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_LPASS_CORE_AXIM_CBCR_ADDR,v)
#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_LPASS_CORE_AXIM_CBCR_ADDR,m,v,HWIO_GCC_LPASS_CORE_AXIM_CBCR_IN)
#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                       0x100000
#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                           0x14
#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_CLK_ARES_SHFT                                                       0x2
#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_CLK_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00047004)
#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_RMSK                                                      0x80100005
#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_IN          \
        in_dword(HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_ADDR)
#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_ADDR, m)
#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_ADDR,v)
#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_ADDR,m,v,HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_IN)
#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                    0x100000
#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                        0x14
#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_GCC_LPASS_CFG_NOC_SWAY_CBCR_CLK_ENABLE_SHFT                                                  0x0

#define HWIO_GCC_LPASS_AXIS2_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00047008)
#define HWIO_GCC_LPASS_AXIS2_CBCR_RMSK                                                             0x80100007
#define HWIO_GCC_LPASS_AXIS2_CBCR_IN          \
        in_dword(HWIO_GCC_LPASS_AXIS2_CBCR_ADDR)
#define HWIO_GCC_LPASS_AXIS2_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_LPASS_AXIS2_CBCR_ADDR, m)
#define HWIO_GCC_LPASS_AXIS2_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_LPASS_AXIS2_CBCR_ADDR,v)
#define HWIO_GCC_LPASS_AXIS2_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_LPASS_AXIS2_CBCR_ADDR,m,v,HWIO_GCC_LPASS_AXIS2_CBCR_IN)
#define HWIO_GCC_LPASS_AXIS2_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_LPASS_AXIS2_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_LPASS_AXIS2_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_LPASS_AXIS2_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_LPASS_AXIS2_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_LPASS_AXIS2_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_LPASS_AXIS2_CBCR_HW_CTL_BMSK                                                             0x2
#define HWIO_GCC_LPASS_AXIS2_CBCR_HW_CTL_SHFT                                                             0x1
#define HWIO_GCC_LPASS_AXIS2_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_LPASS_AXIS2_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_LPASS_TRIG_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0004700c)
#define HWIO_GCC_LPASS_TRIG_CBCR_RMSK                                                              0x80100005
#define HWIO_GCC_LPASS_TRIG_CBCR_IN          \
        in_dword(HWIO_GCC_LPASS_TRIG_CBCR_ADDR)
#define HWIO_GCC_LPASS_TRIG_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_LPASS_TRIG_CBCR_ADDR, m)
#define HWIO_GCC_LPASS_TRIG_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_LPASS_TRIG_CBCR_ADDR,v)
#define HWIO_GCC_LPASS_TRIG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_LPASS_TRIG_CBCR_ADDR,m,v,HWIO_GCC_LPASS_TRIG_CBCR_IN)
#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_LPASS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                            0x100000
#define HWIO_GCC_LPASS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                0x14
#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_LPASS_TRIG_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_LPASS_AT_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00047010)
#define HWIO_GCC_LPASS_AT_CBCR_RMSK                                                                0x80100005
#define HWIO_GCC_LPASS_AT_CBCR_IN          \
        in_dword(HWIO_GCC_LPASS_AT_CBCR_ADDR)
#define HWIO_GCC_LPASS_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_LPASS_AT_CBCR_ADDR, m)
#define HWIO_GCC_LPASS_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_LPASS_AT_CBCR_ADDR,v)
#define HWIO_GCC_LPASS_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_LPASS_AT_CBCR_ADDR,m,v,HWIO_GCC_LPASS_AT_CBCR_IN)
#define HWIO_GCC_LPASS_AT_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_LPASS_AT_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_LPASS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_LPASS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_LPASS_AT_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_LPASS_AT_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_LPASS_AT_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_LPASS_AT_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_TURING_TBU0_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00045000)
#define HWIO_GCC_TURING_TBU0_CBCR_RMSK                                                             0x80107ff5
#define HWIO_GCC_TURING_TBU0_CBCR_IN          \
        in_dword(HWIO_GCC_TURING_TBU0_CBCR_ADDR)
#define HWIO_GCC_TURING_TBU0_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_TBU0_CBCR_ADDR, m)
#define HWIO_GCC_TURING_TBU0_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_TURING_TBU0_CBCR_ADDR,v)
#define HWIO_GCC_TURING_TBU0_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_TBU0_CBCR_ADDR,m,v,HWIO_GCC_TURING_TBU0_CBCR_IN)
#define HWIO_GCC_TURING_TBU0_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_TURING_TBU0_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_TURING_TBU0_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_TURING_TBU0_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_TURING_TBU0_CBCR_FORCE_MEM_CORE_ON_BMSK                                               0x4000
#define HWIO_GCC_TURING_TBU0_CBCR_FORCE_MEM_CORE_ON_SHFT                                                  0xe
#define HWIO_GCC_TURING_TBU0_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                             0x2000
#define HWIO_GCC_TURING_TBU0_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                0xd
#define HWIO_GCC_TURING_TBU0_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                            0x1000
#define HWIO_GCC_TURING_TBU0_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                               0xc
#define HWIO_GCC_TURING_TBU0_CBCR_WAKEUP_BMSK                                                           0xf00
#define HWIO_GCC_TURING_TBU0_CBCR_WAKEUP_SHFT                                                             0x8
#define HWIO_GCC_TURING_TBU0_CBCR_SLEEP_BMSK                                                             0xf0
#define HWIO_GCC_TURING_TBU0_CBCR_SLEEP_SHFT                                                              0x4
#define HWIO_GCC_TURING_TBU0_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_TURING_TBU0_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_TURING_TBU0_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_TURING_TBU0_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_TURING_TBU0_SREGR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00045004)
#define HWIO_GCC_TURING_TBU0_SREGR_RMSK                                                            0xfffff37e
#define HWIO_GCC_TURING_TBU0_SREGR_IN          \
        in_dword(HWIO_GCC_TURING_TBU0_SREGR_ADDR)
#define HWIO_GCC_TURING_TBU0_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_TBU0_SREGR_ADDR, m)
#define HWIO_GCC_TURING_TBU0_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_TURING_TBU0_SREGR_ADDR,v)
#define HWIO_GCC_TURING_TBU0_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_TBU0_SREGR_ADDR,m,v,HWIO_GCC_TURING_TBU0_SREGR_IN)
#define HWIO_GCC_TURING_TBU0_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                                  0xff000000
#define HWIO_GCC_TURING_TBU0_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                        0x18
#define HWIO_GCC_TURING_TBU0_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                     0xff0000
#define HWIO_GCC_TURING_TBU0_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                         0x10
#define HWIO_GCC_TURING_TBU0_SREGR_RESERVE_BITS15_13_BMSK                                              0xe000
#define HWIO_GCC_TURING_TBU0_SREGR_RESERVE_BITS15_13_SHFT                                                 0xd
#define HWIO_GCC_TURING_TBU0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                    0x1000
#define HWIO_GCC_TURING_TBU0_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                       0xc
#define HWIO_GCC_TURING_TBU0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                        0x300
#define HWIO_GCC_TURING_TBU0_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                          0x8
#define HWIO_GCC_TURING_TBU0_SREGR_FORCE_CLK_ON_BMSK                                                     0x40
#define HWIO_GCC_TURING_TBU0_SREGR_FORCE_CLK_ON_SHFT                                                      0x6
#define HWIO_GCC_TURING_TBU0_SREGR_SW_RST_SEL_SLP_STG_BMSK                                               0x20
#define HWIO_GCC_TURING_TBU0_SREGR_SW_RST_SEL_SLP_STG_SHFT                                                0x5
#define HWIO_GCC_TURING_TBU0_SREGR_SW_RST_SLP_STG_BMSK                                                   0x10
#define HWIO_GCC_TURING_TBU0_SREGR_SW_RST_SLP_STG_SHFT                                                    0x4
#define HWIO_GCC_TURING_TBU0_SREGR_SW_CTRL_PWR_DOWN_BMSK                                                  0x8
#define HWIO_GCC_TURING_TBU0_SREGR_SW_CTRL_PWR_DOWN_SHFT                                                  0x3
#define HWIO_GCC_TURING_TBU0_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                             0x4
#define HWIO_GCC_TURING_TBU0_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                             0x2
#define HWIO_GCC_TURING_TBU0_SREGR_SW_CLK_EN_SLP_STG_BMSK                                                 0x2
#define HWIO_GCC_TURING_TBU0_SREGR_SW_CLK_EN_SLP_STG_SHFT                                                 0x1

#define HWIO_GCC_TURING_TBU1_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00045008)
#define HWIO_GCC_TURING_TBU1_CBCR_RMSK                                                             0x80107ff5
#define HWIO_GCC_TURING_TBU1_CBCR_IN          \
        in_dword(HWIO_GCC_TURING_TBU1_CBCR_ADDR)
#define HWIO_GCC_TURING_TBU1_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_TBU1_CBCR_ADDR, m)
#define HWIO_GCC_TURING_TBU1_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_TURING_TBU1_CBCR_ADDR,v)
#define HWIO_GCC_TURING_TBU1_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_TBU1_CBCR_ADDR,m,v,HWIO_GCC_TURING_TBU1_CBCR_IN)
#define HWIO_GCC_TURING_TBU1_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_TURING_TBU1_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_TURING_TBU1_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_TURING_TBU1_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_TURING_TBU1_CBCR_FORCE_MEM_CORE_ON_BMSK                                               0x4000
#define HWIO_GCC_TURING_TBU1_CBCR_FORCE_MEM_CORE_ON_SHFT                                                  0xe
#define HWIO_GCC_TURING_TBU1_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                             0x2000
#define HWIO_GCC_TURING_TBU1_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                0xd
#define HWIO_GCC_TURING_TBU1_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                            0x1000
#define HWIO_GCC_TURING_TBU1_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                               0xc
#define HWIO_GCC_TURING_TBU1_CBCR_WAKEUP_BMSK                                                           0xf00
#define HWIO_GCC_TURING_TBU1_CBCR_WAKEUP_SHFT                                                             0x8
#define HWIO_GCC_TURING_TBU1_CBCR_SLEEP_BMSK                                                             0xf0
#define HWIO_GCC_TURING_TBU1_CBCR_SLEEP_SHFT                                                              0x4
#define HWIO_GCC_TURING_TBU1_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_TURING_TBU1_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_TURING_TBU1_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_TURING_TBU1_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_TURING_TBU1_SREGR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004500c)
#define HWIO_GCC_TURING_TBU1_SREGR_RMSK                                                            0xfffff37e
#define HWIO_GCC_TURING_TBU1_SREGR_IN          \
        in_dword(HWIO_GCC_TURING_TBU1_SREGR_ADDR)
#define HWIO_GCC_TURING_TBU1_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_TBU1_SREGR_ADDR, m)
#define HWIO_GCC_TURING_TBU1_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_TURING_TBU1_SREGR_ADDR,v)
#define HWIO_GCC_TURING_TBU1_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_TBU1_SREGR_ADDR,m,v,HWIO_GCC_TURING_TBU1_SREGR_IN)
#define HWIO_GCC_TURING_TBU1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                                  0xff000000
#define HWIO_GCC_TURING_TBU1_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                        0x18
#define HWIO_GCC_TURING_TBU1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                     0xff0000
#define HWIO_GCC_TURING_TBU1_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                         0x10
#define HWIO_GCC_TURING_TBU1_SREGR_RESERVE_BITS15_13_BMSK                                              0xe000
#define HWIO_GCC_TURING_TBU1_SREGR_RESERVE_BITS15_13_SHFT                                                 0xd
#define HWIO_GCC_TURING_TBU1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                    0x1000
#define HWIO_GCC_TURING_TBU1_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                       0xc
#define HWIO_GCC_TURING_TBU1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                        0x300
#define HWIO_GCC_TURING_TBU1_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                          0x8
#define HWIO_GCC_TURING_TBU1_SREGR_FORCE_CLK_ON_BMSK                                                     0x40
#define HWIO_GCC_TURING_TBU1_SREGR_FORCE_CLK_ON_SHFT                                                      0x6
#define HWIO_GCC_TURING_TBU1_SREGR_SW_RST_SEL_SLP_STG_BMSK                                               0x20
#define HWIO_GCC_TURING_TBU1_SREGR_SW_RST_SEL_SLP_STG_SHFT                                                0x5
#define HWIO_GCC_TURING_TBU1_SREGR_SW_RST_SLP_STG_BMSK                                                   0x10
#define HWIO_GCC_TURING_TBU1_SREGR_SW_RST_SLP_STG_SHFT                                                    0x4
#define HWIO_GCC_TURING_TBU1_SREGR_SW_CTRL_PWR_DOWN_BMSK                                                  0x8
#define HWIO_GCC_TURING_TBU1_SREGR_SW_CTRL_PWR_DOWN_SHFT                                                  0x3
#define HWIO_GCC_TURING_TBU1_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                             0x4
#define HWIO_GCC_TURING_TBU1_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                             0x2
#define HWIO_GCC_TURING_TBU1_SREGR_SW_CLK_EN_SLP_STG_BMSK                                                 0x2
#define HWIO_GCC_TURING_TBU1_SREGR_SW_CLK_EN_SLP_STG_SHFT                                                 0x1

#define HWIO_GCC_TURING_Q6_AXI_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00045010)
#define HWIO_GCC_TURING_Q6_AXI_CBCR_RMSK                                                           0x80100005
#define HWIO_GCC_TURING_Q6_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_TURING_Q6_AXI_CBCR_ADDR)
#define HWIO_GCC_TURING_Q6_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_Q6_AXI_CBCR_ADDR, m)
#define HWIO_GCC_TURING_Q6_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_TURING_Q6_AXI_CBCR_ADDR,v)
#define HWIO_GCC_TURING_Q6_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_Q6_AXI_CBCR_ADDR,m,v,HWIO_GCC_TURING_Q6_AXI_CBCR_IN)
#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_TURING_Q6_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_TURING_Q6_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_TURING_Q6_AXI_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_TURING_AXI_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00045014)
#define HWIO_GCC_TURING_AXI_CBCR_RMSK                                                              0x80100005
#define HWIO_GCC_TURING_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_TURING_AXI_CBCR_ADDR)
#define HWIO_GCC_TURING_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_AXI_CBCR_ADDR, m)
#define HWIO_GCC_TURING_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_TURING_AXI_CBCR_ADDR,v)
#define HWIO_GCC_TURING_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_AXI_CBCR_ADDR,m,v,HWIO_GCC_TURING_AXI_CBCR_IN)
#define HWIO_GCC_TURING_AXI_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_TURING_AXI_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_TURING_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                            0x100000
#define HWIO_GCC_TURING_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                0x14
#define HWIO_GCC_TURING_AXI_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_TURING_AXI_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_TURING_AXI_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_TURING_AXI_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_TURING_CFG_AHB_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00045018)
#define HWIO_GCC_TURING_CFG_AHB_CBCR_RMSK                                                          0x80100007
#define HWIO_GCC_TURING_CFG_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_TURING_CFG_AHB_CBCR_ADDR)
#define HWIO_GCC_TURING_CFG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_CFG_AHB_CBCR_ADDR, m)
#define HWIO_GCC_TURING_CFG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_TURING_CFG_AHB_CBCR_ADDR,v)
#define HWIO_GCC_TURING_CFG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_TURING_CFG_AHB_CBCR_IN)
#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_TURING_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_TURING_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_TURING_CFG_AHB_CBCR_HW_CTL_BMSK                                                          0x2
#define HWIO_GCC_TURING_CFG_AHB_CBCR_HW_CTL_SHFT                                                          0x1
#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_TURING_CFG_AHB_CBCR_CLK_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_TURING_AT_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0004501c)
#define HWIO_GCC_TURING_AT_CBCR_RMSK                                                               0x80100005
#define HWIO_GCC_TURING_AT_CBCR_IN          \
        in_dword(HWIO_GCC_TURING_AT_CBCR_ADDR)
#define HWIO_GCC_TURING_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_AT_CBCR_ADDR, m)
#define HWIO_GCC_TURING_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_TURING_AT_CBCR_ADDR,v)
#define HWIO_GCC_TURING_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_AT_CBCR_ADDR,m,v,HWIO_GCC_TURING_AT_CBCR_IN)
#define HWIO_GCC_TURING_AT_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_TURING_AT_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_TURING_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                             0x100000
#define HWIO_GCC_TURING_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                 0x14
#define HWIO_GCC_TURING_AT_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_TURING_AT_CBCR_CLK_ARES_SHFT                                                             0x2
#define HWIO_GCC_TURING_AT_CBCR_CLK_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_TURING_AT_CBCR_CLK_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_TURING_TRIG_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00045020)
#define HWIO_GCC_TURING_TRIG_CBCR_RMSK                                                             0x80100005
#define HWIO_GCC_TURING_TRIG_CBCR_IN          \
        in_dword(HWIO_GCC_TURING_TRIG_CBCR_ADDR)
#define HWIO_GCC_TURING_TRIG_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_TRIG_CBCR_ADDR, m)
#define HWIO_GCC_TURING_TRIG_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_TURING_TRIG_CBCR_ADDR,v)
#define HWIO_GCC_TURING_TRIG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_TRIG_CBCR_ADDR,m,v,HWIO_GCC_TURING_TRIG_CBCR_IN)
#define HWIO_GCC_TURING_TRIG_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_TURING_TRIG_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_TURING_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_TURING_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_TURING_TRIG_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_TURING_TRIG_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_TURING_TRIG_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_TURING_TRIG_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00045038)
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_RMSK                                                          0x7ffff
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_RCG_SW_CTRL_BMSK                                              0x78000
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_RCG_SW_CTRL_SHFT                                                  0xf
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_SW_PERF_STATE_BMSK                                             0x7800
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_SW_PERF_STATE_SHFT                                                0xb
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_SW_OVERRIDE_BMSK                                                0x400
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_SW_OVERRIDE_SHFT                                                  0xa
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                   0x200
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                     0x9
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_DFS_FSM_STATE_BMSK                                              0x1c0
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_DFS_FSM_STATE_SHFT                                                0x6
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_HW_CLK_CONTROL_BMSK                                              0x20
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_HW_CLK_CONTROL_SHFT                                               0x5
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_CURR_PERF_STATE_BMSK                                             0x1e
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_CURR_PERF_STATE_SHFT                                              0x1
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_DFS_EN_BMSK                                                       0x1
#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_DFS_EN_SHFT                                                       0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00045040)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF0_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00045044)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF1_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00045048)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF2_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0004504c)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF3_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00045050)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF4_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00045054)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF5_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00045058)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF6_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0004505c)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF7_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00045060)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF8_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00045064)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF9_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00045068)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF10_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0004506c)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF11_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00045070)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF12_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00045074)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF13_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00045078)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF14_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0004507c)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_Q6_AXI_PERF15_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00045024)
#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_RMSK                                                       0x80000013
#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ADDR)
#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ADDR, m)
#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ADDR,v)
#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ADDR,m,v,HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_IN)
#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ROOT_OFF_BMSK                                              0x80000000
#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ROOT_OFF_SHFT                                                    0x1f
#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                              0x10
#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                               0x4
#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ROOT_EN_BMSK                                                      0x2
#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_ROOT_EN_SHFT                                                      0x1
#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_UPDATE_BMSK                                                       0x1
#define HWIO_GCC_TURING_Q6_AXI_CMD_RCGR_UPDATE_SHFT                                                       0x0

#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00045028)
#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_RMSK                                                         0x11071f
#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_ADDR)
#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_ADDR, m)
#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_ADDR,v)
#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_ADDR,m,v,HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_IN)
#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_HW_CLK_CONTROL_BMSK                                          0x100000
#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_HW_CLK_CONTROL_SHFT                                              0x14
#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_RCGLITE_DISABLE_BMSK                                          0x10000
#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_RCGLITE_DISABLE_SHFT                                             0x10
#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_SEL_BMSK                                                    0x700
#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_SEL_SHFT                                                      0x8
#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_BMSK                                                     0x1f
#define HWIO_GCC_TURING_Q6_AXI_CFG_RCGR_SRC_DIV_SHFT                                                      0x0

#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00045150)
#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_RMSK                                                         0x1
#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                              0x1
#define HWIO_GCC_TURING_Q6_AXI_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                              0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00045170)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00045174)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00045178)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0004517c)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00045180)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00045184)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00045188)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0004518c)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00045190)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00045194)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00045198)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0004519c)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x000451a0)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x000451a4)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x000451a8)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x000451ac)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_TURING_AXI_CMD_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00045154)
#define HWIO_GCC_TURING_AXI_CMD_RCGR_RMSK                                                          0x80000013
#define HWIO_GCC_TURING_AXI_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_TURING_AXI_CMD_RCGR_ADDR)
#define HWIO_GCC_TURING_AXI_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_AXI_CMD_RCGR_ADDR, m)
#define HWIO_GCC_TURING_AXI_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_TURING_AXI_CMD_RCGR_ADDR,v)
#define HWIO_GCC_TURING_AXI_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_AXI_CMD_RCGR_ADDR,m,v,HWIO_GCC_TURING_AXI_CMD_RCGR_IN)
#define HWIO_GCC_TURING_AXI_CMD_RCGR_ROOT_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_TURING_AXI_CMD_RCGR_ROOT_OFF_SHFT                                                       0x1f
#define HWIO_GCC_TURING_AXI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                 0x10
#define HWIO_GCC_TURING_AXI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                  0x4
#define HWIO_GCC_TURING_AXI_CMD_RCGR_ROOT_EN_BMSK                                                         0x2
#define HWIO_GCC_TURING_AXI_CMD_RCGR_ROOT_EN_SHFT                                                         0x1
#define HWIO_GCC_TURING_AXI_CMD_RCGR_UPDATE_BMSK                                                          0x1
#define HWIO_GCC_TURING_AXI_CMD_RCGR_UPDATE_SHFT                                                          0x0

#define HWIO_GCC_TURING_AXI_CFG_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00045158)
#define HWIO_GCC_TURING_AXI_CFG_RCGR_RMSK                                                            0x11071f
#define HWIO_GCC_TURING_AXI_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_TURING_AXI_CFG_RCGR_ADDR)
#define HWIO_GCC_TURING_AXI_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_AXI_CFG_RCGR_ADDR, m)
#define HWIO_GCC_TURING_AXI_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_TURING_AXI_CFG_RCGR_ADDR,v)
#define HWIO_GCC_TURING_AXI_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_AXI_CFG_RCGR_ADDR,m,v,HWIO_GCC_TURING_AXI_CFG_RCGR_IN)
#define HWIO_GCC_TURING_AXI_CFG_RCGR_HW_CLK_CONTROL_BMSK                                             0x100000
#define HWIO_GCC_TURING_AXI_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                 0x14
#define HWIO_GCC_TURING_AXI_CFG_RCGR_RCGLITE_DISABLE_BMSK                                             0x10000
#define HWIO_GCC_TURING_AXI_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                0x10
#define HWIO_GCC_TURING_AXI_CFG_RCGR_SRC_SEL_BMSK                                                       0x700
#define HWIO_GCC_TURING_AXI_CFG_RCGR_SRC_SEL_SHFT                                                         0x8
#define HWIO_GCC_TURING_AXI_CFG_RCGR_SRC_DIV_BMSK                                                        0x1f
#define HWIO_GCC_TURING_AXI_CFG_RCGR_SRC_DIV_SHFT                                                         0x0

#define HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00045280)
#define HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_RMSK                                                            0x1
#define HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_CPUSS_AHB_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00048000)
#define HWIO_GCC_CPUSS_AHB_CBCR_RMSK                                                               0x80000004
#define HWIO_GCC_CPUSS_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_CPUSS_AHB_CBCR_ADDR)
#define HWIO_GCC_CPUSS_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CPUSS_AHB_CBCR_ADDR, m)
#define HWIO_GCC_CPUSS_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CPUSS_AHB_CBCR_ADDR,v)
#define HWIO_GCC_CPUSS_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CPUSS_AHB_CBCR_ADDR,m,v,HWIO_GCC_CPUSS_AHB_CBCR_IN)
#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_CPUSS_AHB_CBCR_CLK_ARES_SHFT                                                             0x2

#define HWIO_GCC_CPUSS_RBCPR_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00048004)
#define HWIO_GCC_CPUSS_RBCPR_CBCR_RMSK                                                             0x80000005
#define HWIO_GCC_CPUSS_RBCPR_CBCR_IN          \
        in_dword(HWIO_GCC_CPUSS_RBCPR_CBCR_ADDR)
#define HWIO_GCC_CPUSS_RBCPR_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CPUSS_RBCPR_CBCR_ADDR, m)
#define HWIO_GCC_CPUSS_RBCPR_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CPUSS_RBCPR_CBCR_ADDR,v)
#define HWIO_GCC_CPUSS_RBCPR_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CPUSS_RBCPR_CBCR_ADDR,m,v,HWIO_GCC_CPUSS_RBCPR_CBCR_IN)
#define HWIO_GCC_CPUSS_RBCPR_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_CPUSS_RBCPR_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_CPUSS_RBCPR_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_CPUSS_RBCPR_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_CPUSS_RBCPR_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_CPUSS_RBCPR_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_CPUSS_TRIG_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00048008)
#define HWIO_GCC_CPUSS_TRIG_CBCR_RMSK                                                              0x80100005
#define HWIO_GCC_CPUSS_TRIG_CBCR_IN          \
        in_dword(HWIO_GCC_CPUSS_TRIG_CBCR_ADDR)
#define HWIO_GCC_CPUSS_TRIG_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CPUSS_TRIG_CBCR_ADDR, m)
#define HWIO_GCC_CPUSS_TRIG_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CPUSS_TRIG_CBCR_ADDR,v)
#define HWIO_GCC_CPUSS_TRIG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CPUSS_TRIG_CBCR_ADDR,m,v,HWIO_GCC_CPUSS_TRIG_CBCR_IN)
#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_CPUSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                            0x100000
#define HWIO_GCC_CPUSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                0x14
#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_CPUSS_TRIG_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_CPUSS_AT_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0004800c)
#define HWIO_GCC_CPUSS_AT_CBCR_RMSK                                                                0x80100005
#define HWIO_GCC_CPUSS_AT_CBCR_IN          \
        in_dword(HWIO_GCC_CPUSS_AT_CBCR_ADDR)
#define HWIO_GCC_CPUSS_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CPUSS_AT_CBCR_ADDR, m)
#define HWIO_GCC_CPUSS_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CPUSS_AT_CBCR_ADDR,v)
#define HWIO_GCC_CPUSS_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CPUSS_AT_CBCR_ADDR,m,v,HWIO_GCC_CPUSS_AT_CBCR_IN)
#define HWIO_GCC_CPUSS_AT_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_CPUSS_AT_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_CPUSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_CPUSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_CPUSS_AT_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00048010)
#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_RMSK                                                           0x80000013
#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR)
#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR, m)
#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR,v)
#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_AHB_CMD_RCGR_IN)
#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ROOT_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ROOT_OFF_SHFT                                                        0x1f
#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                  0x10
#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                   0x4
#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ROOT_EN_BMSK                                                          0x2
#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ROOT_EN_SHFT                                                          0x1
#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_UPDATE_BMSK                                                           0x1
#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_UPDATE_SHFT                                                           0x0

#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00048014)
#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_RMSK                                                             0x11071f
#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR)
#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR, m)
#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR,v)
#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_AHB_CFG_RCGR_IN)
#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_HW_CLK_CONTROL_BMSK                                              0x100000
#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                  0x14
#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_RCGLITE_DISABLE_BMSK                                              0x10000
#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                 0x10
#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_BMSK                                                        0x700
#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_SEL_SHFT                                                          0x8
#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_BMSK                                                         0x1f
#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_SRC_DIV_SHFT                                                          0x0

#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00048028)
#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_RMSK                                                             0xf
#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_IN          \
        in_dword(HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR)
#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR, m)
#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR,v)
#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR,m,v,HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_IN)
#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_CLK_DIV_BMSK                                                     0xf
#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_CLK_DIV_SHFT                                                     0x0

#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00048048)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_RMSK                                                    0x71f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_SEL_BMSK                                            0x700
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_SEL_SHFT                                              0x8
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_BMSK                                             0x1f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_SRC_DIV_SHFT                                              0x0

#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0004804c)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_RMSK                                                    0x71f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_SEL_BMSK                                            0x700
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_SEL_SHFT                                              0x8
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_BMSK                                             0x1f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_SRC_DIV_SHFT                                              0x0

#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00048050)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_RMSK                                                    0x71f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_SEL_BMSK                                            0x700
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_SEL_SHFT                                              0x8
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_BMSK                                             0x1f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_SRC_DIV_SHFT                                              0x0

#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00048054)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_RMSK                                                    0x71f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_SEL_BMSK                                            0x700
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_SEL_SHFT                                              0x8
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_BMSK                                             0x1f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_SRC_DIV_SHFT                                              0x0

#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00048058)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_RMSK                                                    0x71f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_SEL_BMSK                                            0x700
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_SEL_SHFT                                              0x8
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_BMSK                                             0x1f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_SRC_DIV_SHFT                                              0x0

#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0004805c)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_RMSK                                                    0x71f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_SEL_BMSK                                            0x700
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_SEL_SHFT                                              0x8
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_BMSK                                             0x1f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_SRC_DIV_SHFT                                              0x0

#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00048060)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_RMSK                                                    0x71f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_SEL_BMSK                                            0x700
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_SEL_SHFT                                              0x8
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_BMSK                                             0x1f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_SRC_DIV_SHFT                                              0x0

#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00048064)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_RMSK                                                    0x71f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_SEL_BMSK                                            0x700
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_SEL_SHFT                                              0x8
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_BMSK                                             0x1f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_SRC_DIV_SHFT                                              0x0

#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00048068)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_RMSK                                                    0x71f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_SEL_BMSK                                            0x700
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_SEL_SHFT                                              0x8
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_BMSK                                             0x1f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_SRC_DIV_SHFT                                              0x0

#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0004806c)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_RMSK                                                    0x71f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_SEL_BMSK                                            0x700
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_SEL_SHFT                                              0x8
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_BMSK                                             0x1f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_SRC_DIV_SHFT                                              0x0

#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00048070)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00048074)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00048078)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0004807c)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00048080)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00048084)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_RMSK                                                   0x71f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_SEL_BMSK                                           0x700
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_SEL_SHFT                                             0x8
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_BMSK                                            0x1f
#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_SRC_DIV_SHFT                                             0x0

#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0004802c)
#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_RMSK                                                           0x80000013
#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_CPUSS_AXI_CMD_RCGR_ADDR)
#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_CPUSS_AXI_CMD_RCGR_ADDR, m)
#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_CPUSS_AXI_CMD_RCGR_ADDR,v)
#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CPUSS_AXI_CMD_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_AXI_CMD_RCGR_IN)
#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_ROOT_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_ROOT_OFF_SHFT                                                        0x1f
#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                  0x10
#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                   0x4
#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_ROOT_EN_BMSK                                                          0x2
#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_ROOT_EN_SHFT                                                          0x1
#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_UPDATE_BMSK                                                           0x1
#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_UPDATE_SHFT                                                           0x0

#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00048030)
#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_RMSK                                                             0x11071f
#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_CPUSS_AXI_CFG_RCGR_ADDR)
#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_CPUSS_AXI_CFG_RCGR_ADDR, m)
#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_CPUSS_AXI_CFG_RCGR_ADDR,v)
#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CPUSS_AXI_CFG_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_AXI_CFG_RCGR_IN)
#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_HW_CLK_CONTROL_BMSK                                              0x100000
#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                  0x14
#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_RCGLITE_DISABLE_BMSK                                              0x10000
#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                 0x10
#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_SEL_BMSK                                                        0x700
#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_SEL_SHFT                                                          0x8
#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_BMSK                                                         0x1f
#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_SRC_DIV_SHFT                                                          0x0

#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00048158)
#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_RMSK                                                         0x80000013
#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_ADDR)
#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_ADDR, m)
#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_ADDR,v)
#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_IN)
#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_ROOT_OFF_BMSK                                                0x80000000
#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_ROOT_OFF_SHFT                                                      0x1f
#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                0x10
#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                 0x4
#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_ROOT_EN_BMSK                                                        0x2
#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_ROOT_EN_SHFT                                                        0x1
#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_UPDATE_BMSK                                                         0x1
#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_UPDATE_SHFT                                                         0x0

#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0004815c)
#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_RMSK                                                           0x11071f
#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_ADDR)
#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_ADDR, m)
#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_ADDR,v)
#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_IN)
#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_HW_CLK_CONTROL_BMSK                                            0x100000
#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                0x14
#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_RCGLITE_DISABLE_BMSK                                            0x10000
#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_RCGLITE_DISABLE_SHFT                                               0x10
#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_SRC_SEL_BMSK                                                      0x700
#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_SRC_SEL_SHFT                                                        0x8
#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_SRC_DIV_BMSK                                                       0x1f
#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_SRC_DIV_SHFT                                                        0x0

#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00048170)
#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_RMSK                                                         0x80000013
#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR)
#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR, m)
#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR,v)
#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_IN)
#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ROOT_OFF_BMSK                                                0x80000000
#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ROOT_OFF_SHFT                                                      0x1f
#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                0x10
#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                 0x4
#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ROOT_EN_BMSK                                                        0x2
#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ROOT_EN_SHFT                                                        0x1
#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_UPDATE_BMSK                                                         0x1
#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_UPDATE_SHFT                                                         0x0

#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00048174)
#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_RMSK                                                           0x11071f
#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR)
#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR, m)
#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR,v)
#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR,m,v,HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_IN)
#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_HW_CLK_CONTROL_BMSK                                            0x100000
#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                0x14
#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_RCGLITE_DISABLE_BMSK                                            0x10000
#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_RCGLITE_DISABLE_SHFT                                               0x10
#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_BMSK                                                      0x700
#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_SEL_SHFT                                                        0x8
#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_BMSK                                                       0x1f
#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_SRC_DIV_SHFT                                                        0x0

#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00048188)
#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_RMSK                                                             0x1
#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                                  0x1
#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                                  0x0

#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0004818c)
#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_RMSK                                                           0x80100005
#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_IN          \
        in_dword(HWIO_GCC_CPUSS_DVM_BUS_CBCR_ADDR)
#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CPUSS_DVM_BUS_CBCR_ADDR, m)
#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CPUSS_DVM_BUS_CBCR_ADDR,v)
#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CPUSS_DVM_BUS_CBCR_ADDR,m,v,HWIO_GCC_CPUSS_DVM_BUS_CBCR_IN)
#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00048190)
#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_RMSK                                                         0x80000005
#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_IN          \
        in_dword(HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR)
#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR, m)
#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR,v)
#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR,m,v,HWIO_GCC_APSS_QDSS_TSCTR_CBCR_IN)
#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ARES_SHFT                                                       0x2
#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_CLK_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00048194)
#define HWIO_GCC_APSS_QDSS_APB_CBCR_RMSK                                                           0x80000005
#define HWIO_GCC_APSS_QDSS_APB_CBCR_IN          \
        in_dword(HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR)
#define HWIO_GCC_APSS_QDSS_APB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR, m)
#define HWIO_GCC_APSS_QDSS_APB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR,v)
#define HWIO_GCC_APSS_QDSS_APB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR,m,v,HWIO_GCC_APSS_QDSS_APB_CBCR_IN)
#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_APSS_QDSS_APB_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00049000)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_RMSK                                                          0x1
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_IN          \
        in_dword(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR, m)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_OUT(v)      \
        out_dword(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR,v)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR,m,v,HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_IN)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_BLK_ARES_BMSK                                                 0x1
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_BLK_ARES_SHFT                                                 0x0

#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00049004)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_RMSK                                                  0x80000005
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_IN          \
        in_dword(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR, m)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR,v)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR,m,v,HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_IN)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_CLK_ENABLE_SHFT                                              0x0

#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00049008)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_RMSK                                                        0xf
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_IN          \
        in_dword(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_ADDR)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_ADDR, m)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_ADDR,v)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_ADDR,m,v,HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_IN)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_CLK_DIV_BMSK                                                0xf
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_CLK_DIV_SHFT                                                0x0

#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0004900c)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_RMSK                                               0x1ff
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_IN          \
        in_dword(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_ADDR)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_ADDR, m)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_ADDR,v)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_ADDR,m,v,HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_IN)
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_CLK_DIV_BMSK                                       0x1ff
#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_CLK_DIV_SHFT                                         0x0

#define HWIO_GCC_APB2JTAG_BCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0004c000)
#define HWIO_GCC_APB2JTAG_BCR_RMSK                                                                        0x1
#define HWIO_GCC_APB2JTAG_BCR_IN          \
        in_dword(HWIO_GCC_APB2JTAG_BCR_ADDR)
#define HWIO_GCC_APB2JTAG_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_APB2JTAG_BCR_ADDR, m)
#define HWIO_GCC_APB2JTAG_BCR_OUT(v)      \
        out_dword(HWIO_GCC_APB2JTAG_BCR_ADDR,v)
#define HWIO_GCC_APB2JTAG_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APB2JTAG_BCR_ADDR,m,v,HWIO_GCC_APB2JTAG_BCR_IN)
#define HWIO_GCC_APB2JTAG_BCR_BLK_ARES_BMSK                                                               0x1
#define HWIO_GCC_APB2JTAG_BCR_BLK_ARES_SHFT                                                               0x0

#define HWIO_GCC_RBCPR_CX_BCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0004e000)
#define HWIO_GCC_RBCPR_CX_BCR_RMSK                                                                        0x1
#define HWIO_GCC_RBCPR_CX_BCR_IN          \
        in_dword(HWIO_GCC_RBCPR_CX_BCR_ADDR)
#define HWIO_GCC_RBCPR_CX_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_RBCPR_CX_BCR_ADDR, m)
#define HWIO_GCC_RBCPR_CX_BCR_OUT(v)      \
        out_dword(HWIO_GCC_RBCPR_CX_BCR_ADDR,v)
#define HWIO_GCC_RBCPR_CX_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RBCPR_CX_BCR_ADDR,m,v,HWIO_GCC_RBCPR_CX_BCR_IN)
#define HWIO_GCC_RBCPR_CX_BCR_BLK_ARES_BMSK                                                               0x1
#define HWIO_GCC_RBCPR_CX_BCR_BLK_ARES_SHFT                                                               0x0

#define HWIO_GCC_RBCPR_CX_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0004e004)
#define HWIO_GCC_RBCPR_CX_CBCR_RMSK                                                                0x80000005
#define HWIO_GCC_RBCPR_CX_CBCR_IN          \
        in_dword(HWIO_GCC_RBCPR_CX_CBCR_ADDR)
#define HWIO_GCC_RBCPR_CX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_RBCPR_CX_CBCR_ADDR, m)
#define HWIO_GCC_RBCPR_CX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_RBCPR_CX_CBCR_ADDR,v)
#define HWIO_GCC_RBCPR_CX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RBCPR_CX_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_CX_CBCR_IN)
#define HWIO_GCC_RBCPR_CX_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_RBCPR_CX_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_RBCPR_CX_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004e008)
#define HWIO_GCC_RBCPR_CX_AHB_CBCR_RMSK                                                            0x80100007
#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR)
#define HWIO_GCC_RBCPR_CX_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR, m)
#define HWIO_GCC_RBCPR_CX_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR,v)
#define HWIO_GCC_RBCPR_CX_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_CX_AHB_CBCR_IN)
#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                          0x100000
#define HWIO_GCC_RBCPR_CX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                              0x14
#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_RBCPR_CX_AHB_CBCR_HW_CTL_BMSK                                                            0x2
#define HWIO_GCC_RBCPR_CX_AHB_CBCR_HW_CTL_SHFT                                                            0x1
#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_RBCPR_CX_AHB_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004e00c)
#define HWIO_GCC_RBCPR_CX_CMD_RCGR_RMSK                                                            0x80000013
#define HWIO_GCC_RBCPR_CX_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR)
#define HWIO_GCC_RBCPR_CX_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR, m)
#define HWIO_GCC_RBCPR_CX_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR,v)
#define HWIO_GCC_RBCPR_CX_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_CX_CMD_RCGR_IN)
#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ROOT_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ROOT_OFF_SHFT                                                         0x1f
#define HWIO_GCC_RBCPR_CX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                   0x10
#define HWIO_GCC_RBCPR_CX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                    0x4
#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ROOT_EN_BMSK                                                           0x2
#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ROOT_EN_SHFT                                                           0x1
#define HWIO_GCC_RBCPR_CX_CMD_RCGR_UPDATE_BMSK                                                            0x1
#define HWIO_GCC_RBCPR_CX_CMD_RCGR_UPDATE_SHFT                                                            0x0

#define HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004e010)
#define HWIO_GCC_RBCPR_CX_CFG_RCGR_RMSK                                                              0x11071f
#define HWIO_GCC_RBCPR_CX_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR)
#define HWIO_GCC_RBCPR_CX_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR, m)
#define HWIO_GCC_RBCPR_CX_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR,v)
#define HWIO_GCC_RBCPR_CX_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_CX_CFG_RCGR_IN)
#define HWIO_GCC_RBCPR_CX_CFG_RCGR_HW_CLK_CONTROL_BMSK                                               0x100000
#define HWIO_GCC_RBCPR_CX_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                   0x14
#define HWIO_GCC_RBCPR_CX_CFG_RCGR_RCGLITE_DISABLE_BMSK                                               0x10000
#define HWIO_GCC_RBCPR_CX_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                  0x10
#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_BMSK                                                         0x700
#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_SEL_SHFT                                                           0x8
#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_BMSK                                                          0x1f
#define HWIO_GCC_RBCPR_CX_CFG_RCGR_SRC_DIV_SHFT                                                           0x0

#define HWIO_GCC_RBCPR_MX_BCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0004f000)
#define HWIO_GCC_RBCPR_MX_BCR_RMSK                                                                        0x1
#define HWIO_GCC_RBCPR_MX_BCR_IN          \
        in_dword(HWIO_GCC_RBCPR_MX_BCR_ADDR)
#define HWIO_GCC_RBCPR_MX_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_RBCPR_MX_BCR_ADDR, m)
#define HWIO_GCC_RBCPR_MX_BCR_OUT(v)      \
        out_dword(HWIO_GCC_RBCPR_MX_BCR_ADDR,v)
#define HWIO_GCC_RBCPR_MX_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RBCPR_MX_BCR_ADDR,m,v,HWIO_GCC_RBCPR_MX_BCR_IN)
#define HWIO_GCC_RBCPR_MX_BCR_BLK_ARES_BMSK                                                               0x1
#define HWIO_GCC_RBCPR_MX_BCR_BLK_ARES_SHFT                                                               0x0

#define HWIO_GCC_RBCPR_MX_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0004f004)
#define HWIO_GCC_RBCPR_MX_CBCR_RMSK                                                                0x80000005
#define HWIO_GCC_RBCPR_MX_CBCR_IN          \
        in_dword(HWIO_GCC_RBCPR_MX_CBCR_ADDR)
#define HWIO_GCC_RBCPR_MX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_RBCPR_MX_CBCR_ADDR, m)
#define HWIO_GCC_RBCPR_MX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_RBCPR_MX_CBCR_ADDR,v)
#define HWIO_GCC_RBCPR_MX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RBCPR_MX_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_MX_CBCR_IN)
#define HWIO_GCC_RBCPR_MX_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_RBCPR_MX_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_RBCPR_MX_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_RBCPR_MX_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_RBCPR_MX_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_RBCPR_MX_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_RBCPR_MX_AHB_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004f008)
#define HWIO_GCC_RBCPR_MX_AHB_CBCR_RMSK                                                            0x80100007
#define HWIO_GCC_RBCPR_MX_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_RBCPR_MX_AHB_CBCR_ADDR)
#define HWIO_GCC_RBCPR_MX_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_RBCPR_MX_AHB_CBCR_ADDR, m)
#define HWIO_GCC_RBCPR_MX_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_RBCPR_MX_AHB_CBCR_ADDR,v)
#define HWIO_GCC_RBCPR_MX_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RBCPR_MX_AHB_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_MX_AHB_CBCR_IN)
#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_RBCPR_MX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                          0x100000
#define HWIO_GCC_RBCPR_MX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                              0x14
#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_RBCPR_MX_AHB_CBCR_HW_CTL_BMSK                                                            0x2
#define HWIO_GCC_RBCPR_MX_AHB_CBCR_HW_CTL_SHFT                                                            0x1
#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_RBCPR_MX_AHB_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_RBCPR_MX_CMD_RCGR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004f00c)
#define HWIO_GCC_RBCPR_MX_CMD_RCGR_RMSK                                                            0x80000013
#define HWIO_GCC_RBCPR_MX_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_RBCPR_MX_CMD_RCGR_ADDR)
#define HWIO_GCC_RBCPR_MX_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_RBCPR_MX_CMD_RCGR_ADDR, m)
#define HWIO_GCC_RBCPR_MX_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_RBCPR_MX_CMD_RCGR_ADDR,v)
#define HWIO_GCC_RBCPR_MX_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RBCPR_MX_CMD_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_MX_CMD_RCGR_IN)
#define HWIO_GCC_RBCPR_MX_CMD_RCGR_ROOT_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_RBCPR_MX_CMD_RCGR_ROOT_OFF_SHFT                                                         0x1f
#define HWIO_GCC_RBCPR_MX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                   0x10
#define HWIO_GCC_RBCPR_MX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                    0x4
#define HWIO_GCC_RBCPR_MX_CMD_RCGR_ROOT_EN_BMSK                                                           0x2
#define HWIO_GCC_RBCPR_MX_CMD_RCGR_ROOT_EN_SHFT                                                           0x1
#define HWIO_GCC_RBCPR_MX_CMD_RCGR_UPDATE_BMSK                                                            0x1
#define HWIO_GCC_RBCPR_MX_CMD_RCGR_UPDATE_SHFT                                                            0x0

#define HWIO_GCC_RBCPR_MX_CFG_RCGR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004f010)
#define HWIO_GCC_RBCPR_MX_CFG_RCGR_RMSK                                                              0x11071f
#define HWIO_GCC_RBCPR_MX_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_RBCPR_MX_CFG_RCGR_ADDR)
#define HWIO_GCC_RBCPR_MX_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_RBCPR_MX_CFG_RCGR_ADDR, m)
#define HWIO_GCC_RBCPR_MX_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_RBCPR_MX_CFG_RCGR_ADDR,v)
#define HWIO_GCC_RBCPR_MX_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RBCPR_MX_CFG_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_MX_CFG_RCGR_IN)
#define HWIO_GCC_RBCPR_MX_CFG_RCGR_HW_CLK_CONTROL_BMSK                                               0x100000
#define HWIO_GCC_RBCPR_MX_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                   0x14
#define HWIO_GCC_RBCPR_MX_CFG_RCGR_RCGLITE_DISABLE_BMSK                                               0x10000
#define HWIO_GCC_RBCPR_MX_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                  0x10
#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_SEL_BMSK                                                         0x700
#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_SEL_SHFT                                                           0x8
#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_BMSK                                                          0x1f
#define HWIO_GCC_RBCPR_MX_CFG_RCGR_SRC_DIV_SHFT                                                           0x0

#define HWIO_GCC_DEBUG_DIV_CDIVR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00062004)
#define HWIO_GCC_DEBUG_DIV_CDIVR_RMSK                                                                     0xf
#define HWIO_GCC_DEBUG_DIV_CDIVR_IN          \
        in_dword(HWIO_GCC_DEBUG_DIV_CDIVR_ADDR)
#define HWIO_GCC_DEBUG_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_DEBUG_DIV_CDIVR_ADDR, m)
#define HWIO_GCC_DEBUG_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_DEBUG_DIV_CDIVR_ADDR,v)
#define HWIO_GCC_DEBUG_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DEBUG_DIV_CDIVR_ADDR,m,v,HWIO_GCC_DEBUG_DIV_CDIVR_IN)
#define HWIO_GCC_DEBUG_DIV_CDIVR_CLK_DIV_BMSK                                                             0xf
#define HWIO_GCC_DEBUG_DIV_CDIVR_CLK_DIV_SHFT                                                             0x0

#define HWIO_GCC_DEBUG_CBCR_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00062008)
#define HWIO_GCC_DEBUG_CBCR_RMSK                                                                   0x80000005
#define HWIO_GCC_DEBUG_CBCR_IN          \
        in_dword(HWIO_GCC_DEBUG_CBCR_ADDR)
#define HWIO_GCC_DEBUG_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DEBUG_CBCR_ADDR, m)
#define HWIO_GCC_DEBUG_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DEBUG_CBCR_ADDR,v)
#define HWIO_GCC_DEBUG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DEBUG_CBCR_ADDR,m,v,HWIO_GCC_DEBUG_CBCR_IN)
#define HWIO_GCC_DEBUG_CBCR_CLK_OFF_BMSK                                                           0x80000000
#define HWIO_GCC_DEBUG_CBCR_CLK_OFF_SHFT                                                                 0x1f
#define HWIO_GCC_DEBUG_CBCR_CLK_ARES_BMSK                                                                 0x4
#define HWIO_GCC_DEBUG_CBCR_CLK_ARES_SHFT                                                                 0x2
#define HWIO_GCC_DEBUG_CBCR_CLK_ENABLE_BMSK                                                               0x1
#define HWIO_GCC_DEBUG_CBCR_CLK_ENABLE_SHFT                                                               0x0

#define HWIO_GCC_GP1_CBCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00064000)
#define HWIO_GCC_GP1_CBCR_RMSK                                                                     0x80000005
#define HWIO_GCC_GP1_CBCR_IN          \
        in_dword(HWIO_GCC_GP1_CBCR_ADDR)
#define HWIO_GCC_GP1_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GP1_CBCR_ADDR, m)
#define HWIO_GCC_GP1_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_GP1_CBCR_ADDR,v)
#define HWIO_GCC_GP1_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP1_CBCR_ADDR,m,v,HWIO_GCC_GP1_CBCR_IN)
#define HWIO_GCC_GP1_CBCR_CLK_OFF_BMSK                                                             0x80000000
#define HWIO_GCC_GP1_CBCR_CLK_OFF_SHFT                                                                   0x1f
#define HWIO_GCC_GP1_CBCR_CLK_ARES_BMSK                                                                   0x4
#define HWIO_GCC_GP1_CBCR_CLK_ARES_SHFT                                                                   0x2
#define HWIO_GCC_GP1_CBCR_CLK_ENABLE_BMSK                                                                 0x1
#define HWIO_GCC_GP1_CBCR_CLK_ENABLE_SHFT                                                                 0x0

#define HWIO_GCC_GP1_CMD_RCGR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00064004)
#define HWIO_GCC_GP1_CMD_RCGR_RMSK                                                                 0x800000f3
#define HWIO_GCC_GP1_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_GP1_CMD_RCGR_ADDR)
#define HWIO_GCC_GP1_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_GP1_CMD_RCGR_ADDR, m)
#define HWIO_GCC_GP1_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_GP1_CMD_RCGR_ADDR,v)
#define HWIO_GCC_GP1_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP1_CMD_RCGR_ADDR,m,v,HWIO_GCC_GP1_CMD_RCGR_IN)
#define HWIO_GCC_GP1_CMD_RCGR_ROOT_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_GP1_CMD_RCGR_ROOT_OFF_SHFT                                                              0x1f
#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_D_BMSK                                                               0x80
#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_D_SHFT                                                                0x7
#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_N_BMSK                                                               0x40
#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_N_SHFT                                                                0x6
#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_M_BMSK                                                               0x20
#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_M_SHFT                                                                0x5
#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                        0x10
#define HWIO_GCC_GP1_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                         0x4
#define HWIO_GCC_GP1_CMD_RCGR_ROOT_EN_BMSK                                                                0x2
#define HWIO_GCC_GP1_CMD_RCGR_ROOT_EN_SHFT                                                                0x1
#define HWIO_GCC_GP1_CMD_RCGR_UPDATE_BMSK                                                                 0x1
#define HWIO_GCC_GP1_CMD_RCGR_UPDATE_SHFT                                                                 0x0

#define HWIO_GCC_GP1_CFG_RCGR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00064008)
#define HWIO_GCC_GP1_CFG_RCGR_RMSK                                                                   0x10371f
#define HWIO_GCC_GP1_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_GP1_CFG_RCGR_ADDR)
#define HWIO_GCC_GP1_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_GP1_CFG_RCGR_ADDR, m)
#define HWIO_GCC_GP1_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_GP1_CFG_RCGR_ADDR,v)
#define HWIO_GCC_GP1_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP1_CFG_RCGR_ADDR,m,v,HWIO_GCC_GP1_CFG_RCGR_IN)
#define HWIO_GCC_GP1_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                    0x100000
#define HWIO_GCC_GP1_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                        0x14
#define HWIO_GCC_GP1_CFG_RCGR_MODE_BMSK                                                                0x3000
#define HWIO_GCC_GP1_CFG_RCGR_MODE_SHFT                                                                   0xc
#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_BMSK                                                              0x700
#define HWIO_GCC_GP1_CFG_RCGR_SRC_SEL_SHFT                                                                0x8
#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_BMSK                                                               0x1f
#define HWIO_GCC_GP1_CFG_RCGR_SRC_DIV_SHFT                                                                0x0

#define HWIO_GCC_GP1_M_ADDR                                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0006400c)
#define HWIO_GCC_GP1_M_RMSK                                                                              0xff
#define HWIO_GCC_GP1_M_IN          \
        in_dword(HWIO_GCC_GP1_M_ADDR)
#define HWIO_GCC_GP1_M_INM(m)      \
        in_dword_masked(HWIO_GCC_GP1_M_ADDR, m)
#define HWIO_GCC_GP1_M_OUT(v)      \
        out_dword(HWIO_GCC_GP1_M_ADDR,v)
#define HWIO_GCC_GP1_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP1_M_ADDR,m,v,HWIO_GCC_GP1_M_IN)
#define HWIO_GCC_GP1_M_M_BMSK                                                                            0xff
#define HWIO_GCC_GP1_M_M_SHFT                                                                             0x0

#define HWIO_GCC_GP1_N_ADDR                                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00064010)
#define HWIO_GCC_GP1_N_RMSK                                                                              0xff
#define HWIO_GCC_GP1_N_IN          \
        in_dword(HWIO_GCC_GP1_N_ADDR)
#define HWIO_GCC_GP1_N_INM(m)      \
        in_dword_masked(HWIO_GCC_GP1_N_ADDR, m)
#define HWIO_GCC_GP1_N_OUT(v)      \
        out_dword(HWIO_GCC_GP1_N_ADDR,v)
#define HWIO_GCC_GP1_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP1_N_ADDR,m,v,HWIO_GCC_GP1_N_IN)
#define HWIO_GCC_GP1_N_NOT_N_MINUS_M_BMSK                                                                0xff
#define HWIO_GCC_GP1_N_NOT_N_MINUS_M_SHFT                                                                 0x0

#define HWIO_GCC_GP1_D_ADDR                                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00064014)
#define HWIO_GCC_GP1_D_RMSK                                                                              0xff
#define HWIO_GCC_GP1_D_IN          \
        in_dword(HWIO_GCC_GP1_D_ADDR)
#define HWIO_GCC_GP1_D_INM(m)      \
        in_dword_masked(HWIO_GCC_GP1_D_ADDR, m)
#define HWIO_GCC_GP1_D_OUT(v)      \
        out_dword(HWIO_GCC_GP1_D_ADDR,v)
#define HWIO_GCC_GP1_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP1_D_ADDR,m,v,HWIO_GCC_GP1_D_IN)
#define HWIO_GCC_GP1_D_NOT_2D_BMSK                                                                       0xff
#define HWIO_GCC_GP1_D_NOT_2D_SHFT                                                                        0x0

#define HWIO_GCC_GP2_CBCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00065000)
#define HWIO_GCC_GP2_CBCR_RMSK                                                                     0x80000005
#define HWIO_GCC_GP2_CBCR_IN          \
        in_dword(HWIO_GCC_GP2_CBCR_ADDR)
#define HWIO_GCC_GP2_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GP2_CBCR_ADDR, m)
#define HWIO_GCC_GP2_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_GP2_CBCR_ADDR,v)
#define HWIO_GCC_GP2_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP2_CBCR_ADDR,m,v,HWIO_GCC_GP2_CBCR_IN)
#define HWIO_GCC_GP2_CBCR_CLK_OFF_BMSK                                                             0x80000000
#define HWIO_GCC_GP2_CBCR_CLK_OFF_SHFT                                                                   0x1f
#define HWIO_GCC_GP2_CBCR_CLK_ARES_BMSK                                                                   0x4
#define HWIO_GCC_GP2_CBCR_CLK_ARES_SHFT                                                                   0x2
#define HWIO_GCC_GP2_CBCR_CLK_ENABLE_BMSK                                                                 0x1
#define HWIO_GCC_GP2_CBCR_CLK_ENABLE_SHFT                                                                 0x0

#define HWIO_GCC_GP2_CMD_RCGR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00065004)
#define HWIO_GCC_GP2_CMD_RCGR_RMSK                                                                 0x800000f3
#define HWIO_GCC_GP2_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_GP2_CMD_RCGR_ADDR)
#define HWIO_GCC_GP2_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_GP2_CMD_RCGR_ADDR, m)
#define HWIO_GCC_GP2_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_GP2_CMD_RCGR_ADDR,v)
#define HWIO_GCC_GP2_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP2_CMD_RCGR_ADDR,m,v,HWIO_GCC_GP2_CMD_RCGR_IN)
#define HWIO_GCC_GP2_CMD_RCGR_ROOT_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_GP2_CMD_RCGR_ROOT_OFF_SHFT                                                              0x1f
#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_D_BMSK                                                               0x80
#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_D_SHFT                                                                0x7
#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_N_BMSK                                                               0x40
#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_N_SHFT                                                                0x6
#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_M_BMSK                                                               0x20
#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_M_SHFT                                                                0x5
#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                        0x10
#define HWIO_GCC_GP2_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                         0x4
#define HWIO_GCC_GP2_CMD_RCGR_ROOT_EN_BMSK                                                                0x2
#define HWIO_GCC_GP2_CMD_RCGR_ROOT_EN_SHFT                                                                0x1
#define HWIO_GCC_GP2_CMD_RCGR_UPDATE_BMSK                                                                 0x1
#define HWIO_GCC_GP2_CMD_RCGR_UPDATE_SHFT                                                                 0x0

#define HWIO_GCC_GP2_CFG_RCGR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00065008)
#define HWIO_GCC_GP2_CFG_RCGR_RMSK                                                                   0x10371f
#define HWIO_GCC_GP2_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_GP2_CFG_RCGR_ADDR)
#define HWIO_GCC_GP2_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_GP2_CFG_RCGR_ADDR, m)
#define HWIO_GCC_GP2_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_GP2_CFG_RCGR_ADDR,v)
#define HWIO_GCC_GP2_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP2_CFG_RCGR_ADDR,m,v,HWIO_GCC_GP2_CFG_RCGR_IN)
#define HWIO_GCC_GP2_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                    0x100000
#define HWIO_GCC_GP2_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                        0x14
#define HWIO_GCC_GP2_CFG_RCGR_MODE_BMSK                                                                0x3000
#define HWIO_GCC_GP2_CFG_RCGR_MODE_SHFT                                                                   0xc
#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_BMSK                                                              0x700
#define HWIO_GCC_GP2_CFG_RCGR_SRC_SEL_SHFT                                                                0x8
#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_BMSK                                                               0x1f
#define HWIO_GCC_GP2_CFG_RCGR_SRC_DIV_SHFT                                                                0x0

#define HWIO_GCC_GP2_M_ADDR                                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0006500c)
#define HWIO_GCC_GP2_M_RMSK                                                                              0xff
#define HWIO_GCC_GP2_M_IN          \
        in_dword(HWIO_GCC_GP2_M_ADDR)
#define HWIO_GCC_GP2_M_INM(m)      \
        in_dword_masked(HWIO_GCC_GP2_M_ADDR, m)
#define HWIO_GCC_GP2_M_OUT(v)      \
        out_dword(HWIO_GCC_GP2_M_ADDR,v)
#define HWIO_GCC_GP2_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP2_M_ADDR,m,v,HWIO_GCC_GP2_M_IN)
#define HWIO_GCC_GP2_M_M_BMSK                                                                            0xff
#define HWIO_GCC_GP2_M_M_SHFT                                                                             0x0

#define HWIO_GCC_GP2_N_ADDR                                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00065010)
#define HWIO_GCC_GP2_N_RMSK                                                                              0xff
#define HWIO_GCC_GP2_N_IN          \
        in_dword(HWIO_GCC_GP2_N_ADDR)
#define HWIO_GCC_GP2_N_INM(m)      \
        in_dword_masked(HWIO_GCC_GP2_N_ADDR, m)
#define HWIO_GCC_GP2_N_OUT(v)      \
        out_dword(HWIO_GCC_GP2_N_ADDR,v)
#define HWIO_GCC_GP2_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP2_N_ADDR,m,v,HWIO_GCC_GP2_N_IN)
#define HWIO_GCC_GP2_N_NOT_N_MINUS_M_BMSK                                                                0xff
#define HWIO_GCC_GP2_N_NOT_N_MINUS_M_SHFT                                                                 0x0

#define HWIO_GCC_GP2_D_ADDR                                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00065014)
#define HWIO_GCC_GP2_D_RMSK                                                                              0xff
#define HWIO_GCC_GP2_D_IN          \
        in_dword(HWIO_GCC_GP2_D_ADDR)
#define HWIO_GCC_GP2_D_INM(m)      \
        in_dword_masked(HWIO_GCC_GP2_D_ADDR, m)
#define HWIO_GCC_GP2_D_OUT(v)      \
        out_dword(HWIO_GCC_GP2_D_ADDR,v)
#define HWIO_GCC_GP2_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP2_D_ADDR,m,v,HWIO_GCC_GP2_D_IN)
#define HWIO_GCC_GP2_D_NOT_2D_BMSK                                                                       0xff
#define HWIO_GCC_GP2_D_NOT_2D_SHFT                                                                        0x0

#define HWIO_GCC_GP3_CBCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00066000)
#define HWIO_GCC_GP3_CBCR_RMSK                                                                     0x80000005
#define HWIO_GCC_GP3_CBCR_IN          \
        in_dword(HWIO_GCC_GP3_CBCR_ADDR)
#define HWIO_GCC_GP3_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GP3_CBCR_ADDR, m)
#define HWIO_GCC_GP3_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_GP3_CBCR_ADDR,v)
#define HWIO_GCC_GP3_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP3_CBCR_ADDR,m,v,HWIO_GCC_GP3_CBCR_IN)
#define HWIO_GCC_GP3_CBCR_CLK_OFF_BMSK                                                             0x80000000
#define HWIO_GCC_GP3_CBCR_CLK_OFF_SHFT                                                                   0x1f
#define HWIO_GCC_GP3_CBCR_CLK_ARES_BMSK                                                                   0x4
#define HWIO_GCC_GP3_CBCR_CLK_ARES_SHFT                                                                   0x2
#define HWIO_GCC_GP3_CBCR_CLK_ENABLE_BMSK                                                                 0x1
#define HWIO_GCC_GP3_CBCR_CLK_ENABLE_SHFT                                                                 0x0

#define HWIO_GCC_GP3_CMD_RCGR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00066004)
#define HWIO_GCC_GP3_CMD_RCGR_RMSK                                                                 0x800000f3
#define HWIO_GCC_GP3_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_GP3_CMD_RCGR_ADDR)
#define HWIO_GCC_GP3_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_GP3_CMD_RCGR_ADDR, m)
#define HWIO_GCC_GP3_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_GP3_CMD_RCGR_ADDR,v)
#define HWIO_GCC_GP3_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP3_CMD_RCGR_ADDR,m,v,HWIO_GCC_GP3_CMD_RCGR_IN)
#define HWIO_GCC_GP3_CMD_RCGR_ROOT_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_GP3_CMD_RCGR_ROOT_OFF_SHFT                                                              0x1f
#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_D_BMSK                                                               0x80
#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_D_SHFT                                                                0x7
#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_N_BMSK                                                               0x40
#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_N_SHFT                                                                0x6
#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_M_BMSK                                                               0x20
#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_M_SHFT                                                                0x5
#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                        0x10
#define HWIO_GCC_GP3_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                         0x4
#define HWIO_GCC_GP3_CMD_RCGR_ROOT_EN_BMSK                                                                0x2
#define HWIO_GCC_GP3_CMD_RCGR_ROOT_EN_SHFT                                                                0x1
#define HWIO_GCC_GP3_CMD_RCGR_UPDATE_BMSK                                                                 0x1
#define HWIO_GCC_GP3_CMD_RCGR_UPDATE_SHFT                                                                 0x0

#define HWIO_GCC_GP3_CFG_RCGR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00066008)
#define HWIO_GCC_GP3_CFG_RCGR_RMSK                                                                   0x10371f
#define HWIO_GCC_GP3_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_GP3_CFG_RCGR_ADDR)
#define HWIO_GCC_GP3_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_GP3_CFG_RCGR_ADDR, m)
#define HWIO_GCC_GP3_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_GP3_CFG_RCGR_ADDR,v)
#define HWIO_GCC_GP3_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP3_CFG_RCGR_ADDR,m,v,HWIO_GCC_GP3_CFG_RCGR_IN)
#define HWIO_GCC_GP3_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                    0x100000
#define HWIO_GCC_GP3_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                        0x14
#define HWIO_GCC_GP3_CFG_RCGR_MODE_BMSK                                                                0x3000
#define HWIO_GCC_GP3_CFG_RCGR_MODE_SHFT                                                                   0xc
#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_BMSK                                                              0x700
#define HWIO_GCC_GP3_CFG_RCGR_SRC_SEL_SHFT                                                                0x8
#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_BMSK                                                               0x1f
#define HWIO_GCC_GP3_CFG_RCGR_SRC_DIV_SHFT                                                                0x0

#define HWIO_GCC_GP3_M_ADDR                                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0006600c)
#define HWIO_GCC_GP3_M_RMSK                                                                              0xff
#define HWIO_GCC_GP3_M_IN          \
        in_dword(HWIO_GCC_GP3_M_ADDR)
#define HWIO_GCC_GP3_M_INM(m)      \
        in_dword_masked(HWIO_GCC_GP3_M_ADDR, m)
#define HWIO_GCC_GP3_M_OUT(v)      \
        out_dword(HWIO_GCC_GP3_M_ADDR,v)
#define HWIO_GCC_GP3_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP3_M_ADDR,m,v,HWIO_GCC_GP3_M_IN)
#define HWIO_GCC_GP3_M_M_BMSK                                                                            0xff
#define HWIO_GCC_GP3_M_M_SHFT                                                                             0x0

#define HWIO_GCC_GP3_N_ADDR                                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00066010)
#define HWIO_GCC_GP3_N_RMSK                                                                              0xff
#define HWIO_GCC_GP3_N_IN          \
        in_dword(HWIO_GCC_GP3_N_ADDR)
#define HWIO_GCC_GP3_N_INM(m)      \
        in_dword_masked(HWIO_GCC_GP3_N_ADDR, m)
#define HWIO_GCC_GP3_N_OUT(v)      \
        out_dword(HWIO_GCC_GP3_N_ADDR,v)
#define HWIO_GCC_GP3_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP3_N_ADDR,m,v,HWIO_GCC_GP3_N_IN)
#define HWIO_GCC_GP3_N_NOT_N_MINUS_M_BMSK                                                                0xff
#define HWIO_GCC_GP3_N_NOT_N_MINUS_M_SHFT                                                                 0x0

#define HWIO_GCC_GP3_D_ADDR                                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00066014)
#define HWIO_GCC_GP3_D_RMSK                                                                              0xff
#define HWIO_GCC_GP3_D_IN          \
        in_dword(HWIO_GCC_GP3_D_ADDR)
#define HWIO_GCC_GP3_D_INM(m)      \
        in_dword_masked(HWIO_GCC_GP3_D_ADDR, m)
#define HWIO_GCC_GP3_D_OUT(v)      \
        out_dword(HWIO_GCC_GP3_D_ADDR,v)
#define HWIO_GCC_GP3_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GP3_D_ADDR,m,v,HWIO_GCC_GP3_D_IN)
#define HWIO_GCC_GP3_D_NOT_2D_BMSK                                                                       0xff
#define HWIO_GCC_GP3_D_NOT_2D_SHFT                                                                        0x0

#define HWIO_GCC_PCIE_0_BCR_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b000)
#define HWIO_GCC_PCIE_0_BCR_RMSK                                                                          0x1
#define HWIO_GCC_PCIE_0_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_0_BCR_ADDR)
#define HWIO_GCC_PCIE_0_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_BCR_ADDR, m)
#define HWIO_GCC_PCIE_0_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_BCR_ADDR,v)
#define HWIO_GCC_PCIE_0_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_BCR_ADDR,m,v,HWIO_GCC_PCIE_0_BCR_IN)
#define HWIO_GCC_PCIE_0_BCR_BLK_ARES_BMSK                                                                 0x1
#define HWIO_GCC_PCIE_0_BCR_BLK_ARES_SHFT                                                                 0x0

#define HWIO_GCC_PCIE_0_GDSCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b004)
#define HWIO_GCC_PCIE_0_GDSCR_RMSK                                                                 0xf8ffffff
#define HWIO_GCC_PCIE_0_GDSCR_IN          \
        in_dword(HWIO_GCC_PCIE_0_GDSCR_ADDR)
#define HWIO_GCC_PCIE_0_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_GDSCR_ADDR, m)
#define HWIO_GCC_PCIE_0_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_GDSCR_ADDR,v)
#define HWIO_GCC_PCIE_0_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_0_GDSCR_IN)
#define HWIO_GCC_PCIE_0_GDSCR_PWR_ON_BMSK                                                          0x80000000
#define HWIO_GCC_PCIE_0_GDSCR_PWR_ON_SHFT                                                                0x1f
#define HWIO_GCC_PCIE_0_GDSCR_GDSC_STATE_BMSK                                                      0x78000000
#define HWIO_GCC_PCIE_0_GDSCR_GDSC_STATE_SHFT                                                            0x1b
#define HWIO_GCC_PCIE_0_GDSCR_EN_REST_WAIT_BMSK                                                      0xf00000
#define HWIO_GCC_PCIE_0_GDSCR_EN_REST_WAIT_SHFT                                                          0x14
#define HWIO_GCC_PCIE_0_GDSCR_EN_FEW_WAIT_BMSK                                                        0xf0000
#define HWIO_GCC_PCIE_0_GDSCR_EN_FEW_WAIT_SHFT                                                           0x10
#define HWIO_GCC_PCIE_0_GDSCR_CLK_DIS_WAIT_BMSK                                                        0xf000
#define HWIO_GCC_PCIE_0_GDSCR_CLK_DIS_WAIT_SHFT                                                           0xc
#define HWIO_GCC_PCIE_0_GDSCR_RETAIN_FF_ENABLE_BMSK                                                     0x800
#define HWIO_GCC_PCIE_0_GDSCR_RETAIN_FF_ENABLE_SHFT                                                       0xb
#define HWIO_GCC_PCIE_0_GDSCR_RESTORE_BMSK                                                              0x400
#define HWIO_GCC_PCIE_0_GDSCR_RESTORE_SHFT                                                                0xa
#define HWIO_GCC_PCIE_0_GDSCR_SAVE_BMSK                                                                 0x200
#define HWIO_GCC_PCIE_0_GDSCR_SAVE_SHFT                                                                   0x9
#define HWIO_GCC_PCIE_0_GDSCR_RETAIN_BMSK                                                               0x100
#define HWIO_GCC_PCIE_0_GDSCR_RETAIN_SHFT                                                                 0x8
#define HWIO_GCC_PCIE_0_GDSCR_EN_REST_BMSK                                                               0x80
#define HWIO_GCC_PCIE_0_GDSCR_EN_REST_SHFT                                                                0x7
#define HWIO_GCC_PCIE_0_GDSCR_EN_FEW_BMSK                                                                0x40
#define HWIO_GCC_PCIE_0_GDSCR_EN_FEW_SHFT                                                                 0x6
#define HWIO_GCC_PCIE_0_GDSCR_CLAMP_IO_BMSK                                                              0x20
#define HWIO_GCC_PCIE_0_GDSCR_CLAMP_IO_SHFT                                                               0x5
#define HWIO_GCC_PCIE_0_GDSCR_CLK_DISABLE_BMSK                                                           0x10
#define HWIO_GCC_PCIE_0_GDSCR_CLK_DISABLE_SHFT                                                            0x4
#define HWIO_GCC_PCIE_0_GDSCR_PD_ARES_BMSK                                                                0x8
#define HWIO_GCC_PCIE_0_GDSCR_PD_ARES_SHFT                                                                0x3
#define HWIO_GCC_PCIE_0_GDSCR_SW_OVERRIDE_BMSK                                                            0x4
#define HWIO_GCC_PCIE_0_GDSCR_SW_OVERRIDE_SHFT                                                            0x2
#define HWIO_GCC_PCIE_0_GDSCR_HW_CONTROL_BMSK                                                             0x2
#define HWIO_GCC_PCIE_0_GDSCR_HW_CONTROL_SHFT                                                             0x1
#define HWIO_GCC_PCIE_0_GDSCR_SW_COLLAPSE_BMSK                                                            0x1
#define HWIO_GCC_PCIE_0_GDSCR_SW_COLLAPSE_SHFT                                                            0x0

#define HWIO_GCC_PCIE_0_CFG_GDSCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b008)
#define HWIO_GCC_PCIE_0_CFG_GDSCR_RMSK                                                             0xffffffff
#define HWIO_GCC_PCIE_0_CFG_GDSCR_IN          \
        in_dword(HWIO_GCC_PCIE_0_CFG_GDSCR_ADDR)
#define HWIO_GCC_PCIE_0_CFG_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_CFG_GDSCR_ADDR, m)
#define HWIO_GCC_PCIE_0_CFG_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_CFG_GDSCR_ADDR,v)
#define HWIO_GCC_PCIE_0_CFG_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_CFG_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_0_CFG_GDSCR_IN)
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_SPARE_CTRL_IN_BMSK                                          0xf0000000
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_SPARE_CTRL_IN_SHFT                                                0x1c
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK                                          0xc000000
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT                                               0x1a
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK                                           0x2000000
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT                                                0x19
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PWR_UP_START_BMSK                                            0x1000000
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PWR_UP_START_SHFT                                                 0x18
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK                                     0xf00000
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT                                         0x14
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                                        0x80000
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                                           0x13
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK                                            0x40000
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT                                               0x12
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK                                            0x20000
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT                                               0x11
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK                                         0x10000
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT                                            0x10
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                                        0x8000
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                                           0xf
#define HWIO_GCC_PCIE_0_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                                       0x7800
#define HWIO_GCC_PCIE_0_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                                          0xb
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK                                               0x400
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT                                                 0xa
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                                        0x200
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                                          0x9
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                                        0x100
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                                          0x8
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                                            0x80
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                                             0x7
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                                   0x60
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                                    0x5
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                                             0x10
#define HWIO_GCC_PCIE_0_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                                              0x4
#define HWIO_GCC_PCIE_0_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                       0x8
#define HWIO_GCC_PCIE_0_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                       0x3
#define HWIO_GCC_PCIE_0_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                                     0x4
#define HWIO_GCC_PCIE_0_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                                     0x2
#define HWIO_GCC_PCIE_0_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                         0x2
#define HWIO_GCC_PCIE_0_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                         0x1
#define HWIO_GCC_PCIE_0_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                                      0x1
#define HWIO_GCC_PCIE_0_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                                      0x0

#define HWIO_GCC_PCIE_0_CFG2_GDSCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b00c)
#define HWIO_GCC_PCIE_0_CFG2_GDSCR_RMSK                                                               0x1ffff
#define HWIO_GCC_PCIE_0_CFG2_GDSCR_IN          \
        in_dword(HWIO_GCC_PCIE_0_CFG2_GDSCR_ADDR)
#define HWIO_GCC_PCIE_0_CFG2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_CFG2_GDSCR_ADDR, m)
#define HWIO_GCC_PCIE_0_CFG2_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_CFG2_GDSCR_ADDR,v)
#define HWIO_GCC_PCIE_0_CFG2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_0_CFG2_GDSCR_IN)
#define HWIO_GCC_PCIE_0_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK                                             0x10000
#define HWIO_GCC_PCIE_0_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT                                                0x10
#define HWIO_GCC_PCIE_0_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK                                                 0xf000
#define HWIO_GCC_PCIE_0_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT                                                    0xc
#define HWIO_GCC_PCIE_0_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                                          0xf00
#define HWIO_GCC_PCIE_0_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                                            0x8
#define HWIO_GCC_PCIE_0_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                                             0xf0
#define HWIO_GCC_PCIE_0_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                                              0x4
#define HWIO_GCC_PCIE_0_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                                               0xf
#define HWIO_GCC_PCIE_0_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                                               0x0

#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b010)
#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_RMSK                                                      0x80100004
#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_ADDR)
#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_IN)
#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                    0x100000
#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                        0x14
#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_CLK_ARES_SHFT                                                    0x2

#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b014)
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_RMSK                                                          0x80107ff6
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_0_SLV_AXI_CBCR_ADDR)
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_SLV_AXI_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_SLV_AXI_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_SLV_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_0_SLV_AXI_CBCR_IN)
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_HW_CTL_BMSK                                                          0x2
#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_HW_CTL_SHFT                                                          0x1

#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b018)
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_RMSK                                                         0xfffff37e
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_IN          \
        in_dword(HWIO_GCC_PCIE_0_SLV_AXI_SREGR_ADDR)
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_SLV_AXI_SREGR_ADDR, m)
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_SLV_AXI_SREGR_ADDR,v)
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_SLV_AXI_SREGR_ADDR,m,v,HWIO_GCC_PCIE_0_SLV_AXI_SREGR_IN)
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                               0xff000000
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                     0x18
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                  0xff0000
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                      0x10
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_RESERVE_BITS15_13_BMSK                                           0xe000
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_RESERVE_BITS15_13_SHFT                                              0xd
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                 0x1000
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                    0xc
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                     0x300
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                       0x8
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_FORCE_CLK_ON_BMSK                                                  0x40
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_FORCE_CLK_ON_SHFT                                                   0x6
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK                                            0x20
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT                                             0x5
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_RST_SLP_STG_BMSK                                                0x10
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_RST_SLP_STG_SHFT                                                 0x4
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK                                               0x8
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT                                               0x3
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                          0x4
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                          0x2
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK                                              0x2
#define HWIO_GCC_PCIE_0_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT                                              0x1

#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b01c)
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_RMSK                                                         0x80107ff4
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_ADDR)
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_IN)
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                       0x100000
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                           0x14
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK                                           0x4000
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT                                              0xe
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                         0x2000
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                            0xd
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                        0x1000
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                           0xc
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_WAKEUP_BMSK                                                       0xf00
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_WAKEUP_SHFT                                                         0x8
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_SLEEP_BMSK                                                         0xf0
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_SLEEP_SHFT                                                          0x4
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_CLK_ARES_SHFT                                                       0x2

#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b020)
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_RMSK                                                        0xfffff37e
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_IN          \
        in_dword(HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_ADDR)
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_ADDR, m)
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_ADDR,v)
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_ADDR,m,v,HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_IN)
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                              0xff000000
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                    0x18
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                 0xff0000
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                     0x10
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_RESERVE_BITS15_13_BMSK                                          0xe000
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_RESERVE_BITS15_13_SHFT                                             0xd
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                0x1000
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                   0xc
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                    0x300
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                      0x8
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_FORCE_CLK_ON_BMSK                                                 0x40
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_FORCE_CLK_ON_SHFT                                                  0x6
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK                                           0x20
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT                                            0x5
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_RST_SLP_STG_BMSK                                               0x10
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_RST_SLP_STG_SHFT                                                0x4
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK                                              0x8
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT                                              0x3
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                         0x4
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                         0x2
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK                                             0x2
#define HWIO_GCC_PCIE_0_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT                                             0x1

#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b024)
#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_RMSK                                                          0x80100006
#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_0_CFG_AHB_CBCR_ADDR)
#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_CFG_AHB_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_CFG_AHB_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_PCIE_0_CFG_AHB_CBCR_IN)
#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_HW_CTL_BMSK                                                          0x2
#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_HW_CTL_SHFT                                                          0x1

#define HWIO_GCC_PCIE_0_AUX_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b028)
#define HWIO_GCC_PCIE_0_AUX_CBCR_RMSK                                                              0x80000004
#define HWIO_GCC_PCIE_0_AUX_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_0_AUX_CBCR_ADDR)
#define HWIO_GCC_PCIE_0_AUX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_AUX_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_0_AUX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_AUX_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_0_AUX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_AUX_CBCR_ADDR,m,v,HWIO_GCC_PCIE_0_AUX_CBCR_IN)
#define HWIO_GCC_PCIE_0_AUX_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_PCIE_0_AUX_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_PCIE_0_AUX_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_PCIE_0_AUX_CBCR_CLK_ARES_SHFT                                                            0x2

#define HWIO_GCC_PCIE_0_PIPE_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b02c)
#define HWIO_GCC_PCIE_0_PIPE_CBCR_RMSK                                                             0x80007ff4
#define HWIO_GCC_PCIE_0_PIPE_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_0_PIPE_CBCR_ADDR)
#define HWIO_GCC_PCIE_0_PIPE_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_PIPE_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_0_PIPE_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_PIPE_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_0_PIPE_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_PIPE_CBCR_ADDR,m,v,HWIO_GCC_PCIE_0_PIPE_CBCR_IN)
#define HWIO_GCC_PCIE_0_PIPE_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_PCIE_0_PIPE_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_CORE_ON_BMSK                                               0x4000
#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_CORE_ON_SHFT                                                  0xe
#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                             0x2000
#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                0xd
#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                            0x1000
#define HWIO_GCC_PCIE_0_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                               0xc
#define HWIO_GCC_PCIE_0_PIPE_CBCR_WAKEUP_BMSK                                                           0xf00
#define HWIO_GCC_PCIE_0_PIPE_CBCR_WAKEUP_SHFT                                                             0x8
#define HWIO_GCC_PCIE_0_PIPE_CBCR_SLEEP_BMSK                                                             0xf0
#define HWIO_GCC_PCIE_0_PIPE_CBCR_SLEEP_SHFT                                                              0x4
#define HWIO_GCC_PCIE_0_PIPE_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_PCIE_0_PIPE_CBCR_CLK_ARES_SHFT                                                           0x2

#define HWIO_GCC_PCIE_0_PIPE_SREGR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b030)
#define HWIO_GCC_PCIE_0_PIPE_SREGR_RMSK                                                            0xfffff37e
#define HWIO_GCC_PCIE_0_PIPE_SREGR_IN          \
        in_dword(HWIO_GCC_PCIE_0_PIPE_SREGR_ADDR)
#define HWIO_GCC_PCIE_0_PIPE_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_PIPE_SREGR_ADDR, m)
#define HWIO_GCC_PCIE_0_PIPE_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_PIPE_SREGR_ADDR,v)
#define HWIO_GCC_PCIE_0_PIPE_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_PIPE_SREGR_ADDR,m,v,HWIO_GCC_PCIE_0_PIPE_SREGR_IN)
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                                  0xff000000
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                        0x18
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                     0xff0000
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                         0x10
#define HWIO_GCC_PCIE_0_PIPE_SREGR_RESERVE_BITS15_13_BMSK                                              0xe000
#define HWIO_GCC_PCIE_0_PIPE_SREGR_RESERVE_BITS15_13_SHFT                                                 0xd
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                    0x1000
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                       0xc
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                        0x300
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                          0x8
#define HWIO_GCC_PCIE_0_PIPE_SREGR_FORCE_CLK_ON_BMSK                                                     0x40
#define HWIO_GCC_PCIE_0_PIPE_SREGR_FORCE_CLK_ON_SHFT                                                      0x6
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_RST_SEL_SLP_STG_BMSK                                               0x20
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_RST_SEL_SLP_STG_SHFT                                                0x5
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_RST_SLP_STG_BMSK                                                   0x10
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_RST_SLP_STG_SHFT                                                    0x4
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CTRL_PWR_DOWN_BMSK                                                  0x8
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CTRL_PWR_DOWN_SHFT                                                  0x3
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                             0x4
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                             0x2
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CLK_EN_SLP_STG_BMSK                                                 0x2
#define HWIO_GCC_PCIE_0_PIPE_SREGR_SW_CLK_EN_SLP_STG_SHFT                                                 0x1

#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b038)
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_RMSK                                                          0x800000f3
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ADDR)
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ADDR, m)
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ADDR,v)
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ADDR,m,v,HWIO_GCC_PCIE_0_AUX_CMD_RCGR_IN)
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ROOT_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ROOT_OFF_SHFT                                                       0x1f
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_DIRTY_D_BMSK                                                        0x80
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_DIRTY_D_SHFT                                                         0x7
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_DIRTY_N_BMSK                                                        0x40
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_DIRTY_N_SHFT                                                         0x6
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_DIRTY_M_BMSK                                                        0x20
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_DIRTY_M_SHFT                                                         0x5
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                 0x10
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                  0x4
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ROOT_EN_BMSK                                                         0x2
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ROOT_EN_SHFT                                                         0x1
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_UPDATE_BMSK                                                          0x1
#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_UPDATE_SHFT                                                          0x0

#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b03c)
#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_RMSK                                                            0x10371f
#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_PCIE_0_AUX_CFG_RCGR_ADDR)
#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_AUX_CFG_RCGR_ADDR, m)
#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_AUX_CFG_RCGR_ADDR,v)
#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_AUX_CFG_RCGR_ADDR,m,v,HWIO_GCC_PCIE_0_AUX_CFG_RCGR_IN)
#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_HW_CLK_CONTROL_BMSK                                             0x100000
#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                 0x14
#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_MODE_BMSK                                                         0x3000
#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_MODE_SHFT                                                            0xc
#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_SEL_BMSK                                                       0x700
#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_SEL_SHFT                                                         0x8
#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_BMSK                                                        0x1f
#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_SRC_DIV_SHFT                                                         0x0

#define HWIO_GCC_PCIE_0_AUX_M_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b040)
#define HWIO_GCC_PCIE_0_AUX_M_RMSK                                                                     0xffff
#define HWIO_GCC_PCIE_0_AUX_M_IN          \
        in_dword(HWIO_GCC_PCIE_0_AUX_M_ADDR)
#define HWIO_GCC_PCIE_0_AUX_M_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_AUX_M_ADDR, m)
#define HWIO_GCC_PCIE_0_AUX_M_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_AUX_M_ADDR,v)
#define HWIO_GCC_PCIE_0_AUX_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_AUX_M_ADDR,m,v,HWIO_GCC_PCIE_0_AUX_M_IN)
#define HWIO_GCC_PCIE_0_AUX_M_M_BMSK                                                                   0xffff
#define HWIO_GCC_PCIE_0_AUX_M_M_SHFT                                                                      0x0

#define HWIO_GCC_PCIE_0_AUX_N_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b044)
#define HWIO_GCC_PCIE_0_AUX_N_RMSK                                                                     0xffff
#define HWIO_GCC_PCIE_0_AUX_N_IN          \
        in_dword(HWIO_GCC_PCIE_0_AUX_N_ADDR)
#define HWIO_GCC_PCIE_0_AUX_N_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_AUX_N_ADDR, m)
#define HWIO_GCC_PCIE_0_AUX_N_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_AUX_N_ADDR,v)
#define HWIO_GCC_PCIE_0_AUX_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_AUX_N_ADDR,m,v,HWIO_GCC_PCIE_0_AUX_N_IN)
#define HWIO_GCC_PCIE_0_AUX_N_NOT_N_MINUS_M_BMSK                                                       0xffff
#define HWIO_GCC_PCIE_0_AUX_N_NOT_N_MINUS_M_SHFT                                                          0x0

#define HWIO_GCC_PCIE_0_AUX_D_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b048)
#define HWIO_GCC_PCIE_0_AUX_D_RMSK                                                                     0xffff
#define HWIO_GCC_PCIE_0_AUX_D_IN          \
        in_dword(HWIO_GCC_PCIE_0_AUX_D_ADDR)
#define HWIO_GCC_PCIE_0_AUX_D_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_AUX_D_ADDR, m)
#define HWIO_GCC_PCIE_0_AUX_D_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_AUX_D_ADDR,v)
#define HWIO_GCC_PCIE_0_AUX_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_AUX_D_ADDR,m,v,HWIO_GCC_PCIE_0_AUX_D_IN)
#define HWIO_GCC_PCIE_0_AUX_D_NOT_2D_BMSK                                                              0xffff
#define HWIO_GCC_PCIE_0_AUX_D_NOT_2D_SHFT                                                                 0x0

#define HWIO_GCC_PCIE_1_BCR_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d000)
#define HWIO_GCC_PCIE_1_BCR_RMSK                                                                          0x1
#define HWIO_GCC_PCIE_1_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_1_BCR_ADDR)
#define HWIO_GCC_PCIE_1_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_BCR_ADDR, m)
#define HWIO_GCC_PCIE_1_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_BCR_ADDR,v)
#define HWIO_GCC_PCIE_1_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_BCR_ADDR,m,v,HWIO_GCC_PCIE_1_BCR_IN)
#define HWIO_GCC_PCIE_1_BCR_BLK_ARES_BMSK                                                                 0x1
#define HWIO_GCC_PCIE_1_BCR_BLK_ARES_SHFT                                                                 0x0

#define HWIO_GCC_PCIE_1_GDSCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d004)
#define HWIO_GCC_PCIE_1_GDSCR_RMSK                                                                 0xf8ffffff
#define HWIO_GCC_PCIE_1_GDSCR_IN          \
        in_dword(HWIO_GCC_PCIE_1_GDSCR_ADDR)
#define HWIO_GCC_PCIE_1_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_GDSCR_ADDR, m)
#define HWIO_GCC_PCIE_1_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_GDSCR_ADDR,v)
#define HWIO_GCC_PCIE_1_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_1_GDSCR_IN)
#define HWIO_GCC_PCIE_1_GDSCR_PWR_ON_BMSK                                                          0x80000000
#define HWIO_GCC_PCIE_1_GDSCR_PWR_ON_SHFT                                                                0x1f
#define HWIO_GCC_PCIE_1_GDSCR_GDSC_STATE_BMSK                                                      0x78000000
#define HWIO_GCC_PCIE_1_GDSCR_GDSC_STATE_SHFT                                                            0x1b
#define HWIO_GCC_PCIE_1_GDSCR_EN_REST_WAIT_BMSK                                                      0xf00000
#define HWIO_GCC_PCIE_1_GDSCR_EN_REST_WAIT_SHFT                                                          0x14
#define HWIO_GCC_PCIE_1_GDSCR_EN_FEW_WAIT_BMSK                                                        0xf0000
#define HWIO_GCC_PCIE_1_GDSCR_EN_FEW_WAIT_SHFT                                                           0x10
#define HWIO_GCC_PCIE_1_GDSCR_CLK_DIS_WAIT_BMSK                                                        0xf000
#define HWIO_GCC_PCIE_1_GDSCR_CLK_DIS_WAIT_SHFT                                                           0xc
#define HWIO_GCC_PCIE_1_GDSCR_RETAIN_FF_ENABLE_BMSK                                                     0x800
#define HWIO_GCC_PCIE_1_GDSCR_RETAIN_FF_ENABLE_SHFT                                                       0xb
#define HWIO_GCC_PCIE_1_GDSCR_RESTORE_BMSK                                                              0x400
#define HWIO_GCC_PCIE_1_GDSCR_RESTORE_SHFT                                                                0xa
#define HWIO_GCC_PCIE_1_GDSCR_SAVE_BMSK                                                                 0x200
#define HWIO_GCC_PCIE_1_GDSCR_SAVE_SHFT                                                                   0x9
#define HWIO_GCC_PCIE_1_GDSCR_RETAIN_BMSK                                                               0x100
#define HWIO_GCC_PCIE_1_GDSCR_RETAIN_SHFT                                                                 0x8
#define HWIO_GCC_PCIE_1_GDSCR_EN_REST_BMSK                                                               0x80
#define HWIO_GCC_PCIE_1_GDSCR_EN_REST_SHFT                                                                0x7
#define HWIO_GCC_PCIE_1_GDSCR_EN_FEW_BMSK                                                                0x40
#define HWIO_GCC_PCIE_1_GDSCR_EN_FEW_SHFT                                                                 0x6
#define HWIO_GCC_PCIE_1_GDSCR_CLAMP_IO_BMSK                                                              0x20
#define HWIO_GCC_PCIE_1_GDSCR_CLAMP_IO_SHFT                                                               0x5
#define HWIO_GCC_PCIE_1_GDSCR_CLK_DISABLE_BMSK                                                           0x10
#define HWIO_GCC_PCIE_1_GDSCR_CLK_DISABLE_SHFT                                                            0x4
#define HWIO_GCC_PCIE_1_GDSCR_PD_ARES_BMSK                                                                0x8
#define HWIO_GCC_PCIE_1_GDSCR_PD_ARES_SHFT                                                                0x3
#define HWIO_GCC_PCIE_1_GDSCR_SW_OVERRIDE_BMSK                                                            0x4
#define HWIO_GCC_PCIE_1_GDSCR_SW_OVERRIDE_SHFT                                                            0x2
#define HWIO_GCC_PCIE_1_GDSCR_HW_CONTROL_BMSK                                                             0x2
#define HWIO_GCC_PCIE_1_GDSCR_HW_CONTROL_SHFT                                                             0x1
#define HWIO_GCC_PCIE_1_GDSCR_SW_COLLAPSE_BMSK                                                            0x1
#define HWIO_GCC_PCIE_1_GDSCR_SW_COLLAPSE_SHFT                                                            0x0

#define HWIO_GCC_PCIE_1_CFG_GDSCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d008)
#define HWIO_GCC_PCIE_1_CFG_GDSCR_RMSK                                                             0xffffffff
#define HWIO_GCC_PCIE_1_CFG_GDSCR_IN          \
        in_dword(HWIO_GCC_PCIE_1_CFG_GDSCR_ADDR)
#define HWIO_GCC_PCIE_1_CFG_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_CFG_GDSCR_ADDR, m)
#define HWIO_GCC_PCIE_1_CFG_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_CFG_GDSCR_ADDR,v)
#define HWIO_GCC_PCIE_1_CFG_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_CFG_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_1_CFG_GDSCR_IN)
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_SPARE_CTRL_IN_BMSK                                          0xf0000000
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_SPARE_CTRL_IN_SHFT                                                0x1c
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK                                          0xc000000
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT                                               0x1a
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK                                           0x2000000
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT                                                0x19
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PWR_UP_START_BMSK                                            0x1000000
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PWR_UP_START_SHFT                                                 0x18
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK                                     0xf00000
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT                                         0x14
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                                        0x80000
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                                           0x13
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK                                            0x40000
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT                                               0x12
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK                                            0x20000
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT                                               0x11
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK                                         0x10000
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT                                            0x10
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                                        0x8000
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                                           0xf
#define HWIO_GCC_PCIE_1_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                                       0x7800
#define HWIO_GCC_PCIE_1_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                                          0xb
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK                                               0x400
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT                                                 0xa
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                                        0x200
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                                          0x9
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                                        0x100
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                                          0x8
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                                            0x80
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                                             0x7
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                                   0x60
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                                    0x5
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                                             0x10
#define HWIO_GCC_PCIE_1_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                                              0x4
#define HWIO_GCC_PCIE_1_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                       0x8
#define HWIO_GCC_PCIE_1_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                       0x3
#define HWIO_GCC_PCIE_1_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                                     0x4
#define HWIO_GCC_PCIE_1_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                                     0x2
#define HWIO_GCC_PCIE_1_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                         0x2
#define HWIO_GCC_PCIE_1_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                         0x1
#define HWIO_GCC_PCIE_1_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                                      0x1
#define HWIO_GCC_PCIE_1_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                                      0x0

#define HWIO_GCC_PCIE_1_CFG2_GDSCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d00c)
#define HWIO_GCC_PCIE_1_CFG2_GDSCR_RMSK                                                               0x1ffff
#define HWIO_GCC_PCIE_1_CFG2_GDSCR_IN          \
        in_dword(HWIO_GCC_PCIE_1_CFG2_GDSCR_ADDR)
#define HWIO_GCC_PCIE_1_CFG2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_CFG2_GDSCR_ADDR, m)
#define HWIO_GCC_PCIE_1_CFG2_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_CFG2_GDSCR_ADDR,v)
#define HWIO_GCC_PCIE_1_CFG2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_1_CFG2_GDSCR_IN)
#define HWIO_GCC_PCIE_1_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK                                             0x10000
#define HWIO_GCC_PCIE_1_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT                                                0x10
#define HWIO_GCC_PCIE_1_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK                                                 0xf000
#define HWIO_GCC_PCIE_1_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT                                                    0xc
#define HWIO_GCC_PCIE_1_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                                          0xf00
#define HWIO_GCC_PCIE_1_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                                            0x8
#define HWIO_GCC_PCIE_1_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                                             0xf0
#define HWIO_GCC_PCIE_1_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                                              0x4
#define HWIO_GCC_PCIE_1_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                                               0xf
#define HWIO_GCC_PCIE_1_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                                               0x0

#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d010)
#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_RMSK                                                      0x80100004
#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_ADDR)
#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_IN)
#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                    0x100000
#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                        0x14
#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_CLK_ARES_SHFT                                                    0x2

#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d014)
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_RMSK                                                          0x80107ff6
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_1_SLV_AXI_CBCR_ADDR)
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_SLV_AXI_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_SLV_AXI_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_SLV_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_1_SLV_AXI_CBCR_IN)
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_HW_CTL_BMSK                                                          0x2
#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_HW_CTL_SHFT                                                          0x1

#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d018)
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_RMSK                                                         0xfffff37e
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_IN          \
        in_dword(HWIO_GCC_PCIE_1_SLV_AXI_SREGR_ADDR)
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_SLV_AXI_SREGR_ADDR, m)
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_SLV_AXI_SREGR_ADDR,v)
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_SLV_AXI_SREGR_ADDR,m,v,HWIO_GCC_PCIE_1_SLV_AXI_SREGR_IN)
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                               0xff000000
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                     0x18
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                  0xff0000
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                      0x10
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_RESERVE_BITS15_13_BMSK                                           0xe000
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_RESERVE_BITS15_13_SHFT                                              0xd
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                 0x1000
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                    0xc
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                     0x300
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                       0x8
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_FORCE_CLK_ON_BMSK                                                  0x40
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_FORCE_CLK_ON_SHFT                                                   0x6
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK                                            0x20
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT                                             0x5
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_RST_SLP_STG_BMSK                                                0x10
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_RST_SLP_STG_SHFT                                                 0x4
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK                                               0x8
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT                                               0x3
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                          0x4
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                          0x2
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK                                              0x2
#define HWIO_GCC_PCIE_1_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT                                              0x1

#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d01c)
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_RMSK                                                         0x80107ff4
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_ADDR)
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_IN)
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                       0x100000
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                           0x14
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK                                           0x4000
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT                                              0xe
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                         0x2000
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                            0xd
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                        0x1000
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                           0xc
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_WAKEUP_BMSK                                                       0xf00
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_WAKEUP_SHFT                                                         0x8
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_SLEEP_BMSK                                                         0xf0
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_SLEEP_SHFT                                                          0x4
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_CLK_ARES_SHFT                                                       0x2

#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d020)
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_RMSK                                                        0xfffff37e
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_IN          \
        in_dword(HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_ADDR)
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_ADDR, m)
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_ADDR,v)
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_ADDR,m,v,HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_IN)
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                              0xff000000
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                    0x18
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                 0xff0000
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                     0x10
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_RESERVE_BITS15_13_BMSK                                          0xe000
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_RESERVE_BITS15_13_SHFT                                             0xd
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                0x1000
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                   0xc
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                    0x300
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                      0x8
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_FORCE_CLK_ON_BMSK                                                 0x40
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_FORCE_CLK_ON_SHFT                                                  0x6
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK                                           0x20
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT                                            0x5
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_RST_SLP_STG_BMSK                                               0x10
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_RST_SLP_STG_SHFT                                                0x4
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK                                              0x8
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT                                              0x3
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                         0x4
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                         0x2
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK                                             0x2
#define HWIO_GCC_PCIE_1_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT                                             0x1

#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d024)
#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_RMSK                                                          0x80100006
#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_1_CFG_AHB_CBCR_ADDR)
#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_CFG_AHB_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_CFG_AHB_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_PCIE_1_CFG_AHB_CBCR_IN)
#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_HW_CTL_BMSK                                                          0x2
#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_HW_CTL_SHFT                                                          0x1

#define HWIO_GCC_PCIE_1_AUX_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d028)
#define HWIO_GCC_PCIE_1_AUX_CBCR_RMSK                                                              0x80000004
#define HWIO_GCC_PCIE_1_AUX_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_1_AUX_CBCR_ADDR)
#define HWIO_GCC_PCIE_1_AUX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_AUX_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_1_AUX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_AUX_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_1_AUX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_AUX_CBCR_ADDR,m,v,HWIO_GCC_PCIE_1_AUX_CBCR_IN)
#define HWIO_GCC_PCIE_1_AUX_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_PCIE_1_AUX_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_PCIE_1_AUX_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_PCIE_1_AUX_CBCR_CLK_ARES_SHFT                                                            0x2

#define HWIO_GCC_PCIE_1_PIPE_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d02c)
#define HWIO_GCC_PCIE_1_PIPE_CBCR_RMSK                                                             0x80007ff4
#define HWIO_GCC_PCIE_1_PIPE_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_1_PIPE_CBCR_ADDR)
#define HWIO_GCC_PCIE_1_PIPE_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_PIPE_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_1_PIPE_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_PIPE_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_1_PIPE_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_PIPE_CBCR_ADDR,m,v,HWIO_GCC_PCIE_1_PIPE_CBCR_IN)
#define HWIO_GCC_PCIE_1_PIPE_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_PCIE_1_PIPE_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_CORE_ON_BMSK                                               0x4000
#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_CORE_ON_SHFT                                                  0xe
#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                             0x2000
#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                0xd
#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                            0x1000
#define HWIO_GCC_PCIE_1_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                               0xc
#define HWIO_GCC_PCIE_1_PIPE_CBCR_WAKEUP_BMSK                                                           0xf00
#define HWIO_GCC_PCIE_1_PIPE_CBCR_WAKEUP_SHFT                                                             0x8
#define HWIO_GCC_PCIE_1_PIPE_CBCR_SLEEP_BMSK                                                             0xf0
#define HWIO_GCC_PCIE_1_PIPE_CBCR_SLEEP_SHFT                                                              0x4
#define HWIO_GCC_PCIE_1_PIPE_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_PCIE_1_PIPE_CBCR_CLK_ARES_SHFT                                                           0x2

#define HWIO_GCC_PCIE_1_PIPE_SREGR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d030)
#define HWIO_GCC_PCIE_1_PIPE_SREGR_RMSK                                                            0xfffff37e
#define HWIO_GCC_PCIE_1_PIPE_SREGR_IN          \
        in_dword(HWIO_GCC_PCIE_1_PIPE_SREGR_ADDR)
#define HWIO_GCC_PCIE_1_PIPE_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_PIPE_SREGR_ADDR, m)
#define HWIO_GCC_PCIE_1_PIPE_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_PIPE_SREGR_ADDR,v)
#define HWIO_GCC_PCIE_1_PIPE_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_PIPE_SREGR_ADDR,m,v,HWIO_GCC_PCIE_1_PIPE_SREGR_IN)
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                                  0xff000000
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                        0x18
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                     0xff0000
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                         0x10
#define HWIO_GCC_PCIE_1_PIPE_SREGR_RESERVE_BITS15_13_BMSK                                              0xe000
#define HWIO_GCC_PCIE_1_PIPE_SREGR_RESERVE_BITS15_13_SHFT                                                 0xd
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                    0x1000
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                       0xc
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                        0x300
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                          0x8
#define HWIO_GCC_PCIE_1_PIPE_SREGR_FORCE_CLK_ON_BMSK                                                     0x40
#define HWIO_GCC_PCIE_1_PIPE_SREGR_FORCE_CLK_ON_SHFT                                                      0x6
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_RST_SEL_SLP_STG_BMSK                                               0x20
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_RST_SEL_SLP_STG_SHFT                                                0x5
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_RST_SLP_STG_BMSK                                                   0x10
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_RST_SLP_STG_SHFT                                                    0x4
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CTRL_PWR_DOWN_BMSK                                                  0x8
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CTRL_PWR_DOWN_SHFT                                                  0x3
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                             0x4
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                             0x2
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CLK_EN_SLP_STG_BMSK                                                 0x2
#define HWIO_GCC_PCIE_1_PIPE_SREGR_SW_CLK_EN_SLP_STG_SHFT                                                 0x1

#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d038)
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_RMSK                                                          0x800000f3
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ADDR)
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ADDR, m)
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ADDR,v)
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ADDR,m,v,HWIO_GCC_PCIE_1_AUX_CMD_RCGR_IN)
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ROOT_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ROOT_OFF_SHFT                                                       0x1f
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_DIRTY_D_BMSK                                                        0x80
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_DIRTY_D_SHFT                                                         0x7
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_DIRTY_N_BMSK                                                        0x40
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_DIRTY_N_SHFT                                                         0x6
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_DIRTY_M_BMSK                                                        0x20
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_DIRTY_M_SHFT                                                         0x5
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                 0x10
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                  0x4
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ROOT_EN_BMSK                                                         0x2
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ROOT_EN_SHFT                                                         0x1
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_UPDATE_BMSK                                                          0x1
#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_UPDATE_SHFT                                                          0x0

#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d03c)
#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_RMSK                                                            0x10371f
#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_PCIE_1_AUX_CFG_RCGR_ADDR)
#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_AUX_CFG_RCGR_ADDR, m)
#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_AUX_CFG_RCGR_ADDR,v)
#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_AUX_CFG_RCGR_ADDR,m,v,HWIO_GCC_PCIE_1_AUX_CFG_RCGR_IN)
#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_HW_CLK_CONTROL_BMSK                                             0x100000
#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                 0x14
#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_MODE_BMSK                                                         0x3000
#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_MODE_SHFT                                                            0xc
#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_SEL_BMSK                                                       0x700
#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_SEL_SHFT                                                         0x8
#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_BMSK                                                        0x1f
#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_SRC_DIV_SHFT                                                         0x0

#define HWIO_GCC_PCIE_1_AUX_M_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d040)
#define HWIO_GCC_PCIE_1_AUX_M_RMSK                                                                     0xffff
#define HWIO_GCC_PCIE_1_AUX_M_IN          \
        in_dword(HWIO_GCC_PCIE_1_AUX_M_ADDR)
#define HWIO_GCC_PCIE_1_AUX_M_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_AUX_M_ADDR, m)
#define HWIO_GCC_PCIE_1_AUX_M_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_AUX_M_ADDR,v)
#define HWIO_GCC_PCIE_1_AUX_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_AUX_M_ADDR,m,v,HWIO_GCC_PCIE_1_AUX_M_IN)
#define HWIO_GCC_PCIE_1_AUX_M_M_BMSK                                                                   0xffff
#define HWIO_GCC_PCIE_1_AUX_M_M_SHFT                                                                      0x0

#define HWIO_GCC_PCIE_1_AUX_N_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d044)
#define HWIO_GCC_PCIE_1_AUX_N_RMSK                                                                     0xffff
#define HWIO_GCC_PCIE_1_AUX_N_IN          \
        in_dword(HWIO_GCC_PCIE_1_AUX_N_ADDR)
#define HWIO_GCC_PCIE_1_AUX_N_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_AUX_N_ADDR, m)
#define HWIO_GCC_PCIE_1_AUX_N_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_AUX_N_ADDR,v)
#define HWIO_GCC_PCIE_1_AUX_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_AUX_N_ADDR,m,v,HWIO_GCC_PCIE_1_AUX_N_IN)
#define HWIO_GCC_PCIE_1_AUX_N_NOT_N_MINUS_M_BMSK                                                       0xffff
#define HWIO_GCC_PCIE_1_AUX_N_NOT_N_MINUS_M_SHFT                                                          0x0

#define HWIO_GCC_PCIE_1_AUX_D_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d048)
#define HWIO_GCC_PCIE_1_AUX_D_RMSK                                                                     0xffff
#define HWIO_GCC_PCIE_1_AUX_D_IN          \
        in_dword(HWIO_GCC_PCIE_1_AUX_D_ADDR)
#define HWIO_GCC_PCIE_1_AUX_D_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_AUX_D_ADDR, m)
#define HWIO_GCC_PCIE_1_AUX_D_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_AUX_D_ADDR,v)
#define HWIO_GCC_PCIE_1_AUX_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_AUX_D_ADDR,m,v,HWIO_GCC_PCIE_1_AUX_D_IN)
#define HWIO_GCC_PCIE_1_AUX_D_NOT_2D_BMSK                                                              0xffff
#define HWIO_GCC_PCIE_1_AUX_D_NOT_2D_SHFT                                                                 0x0

#define HWIO_GCC_PCIE_PHY_BCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0006f000)
#define HWIO_GCC_PCIE_PHY_BCR_RMSK                                                                        0x1
#define HWIO_GCC_PCIE_PHY_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_PHY_BCR_ADDR)
#define HWIO_GCC_PCIE_PHY_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_PHY_BCR_ADDR, m)
#define HWIO_GCC_PCIE_PHY_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_PHY_BCR_ADDR,v)
#define HWIO_GCC_PCIE_PHY_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_PHY_BCR_IN)
#define HWIO_GCC_PCIE_PHY_BCR_BLK_ARES_BMSK                                                               0x1
#define HWIO_GCC_PCIE_PHY_BCR_BLK_ARES_SHFT                                                               0x0

#define HWIO_GCC_PCIE_PHY_AUX_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0006f004)
#define HWIO_GCC_PCIE_PHY_AUX_CBCR_RMSK                                                            0x80000005
#define HWIO_GCC_PCIE_PHY_AUX_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_PHY_AUX_CBCR_ADDR)
#define HWIO_GCC_PCIE_PHY_AUX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_PHY_AUX_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_PHY_AUX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_PHY_AUX_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_PHY_AUX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_PHY_AUX_CBCR_ADDR,m,v,HWIO_GCC_PCIE_PHY_AUX_CBCR_IN)
#define HWIO_GCC_PCIE_PHY_AUX_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_PCIE_PHY_AUX_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_PCIE_PHY_AUX_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_PCIE_PHY_AUX_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_PCIE_PHY_AUX_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_PCIE_PHY_AUX_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0006f014)
#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_RMSK                                                     0x80000013
#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_ADDR)
#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_ADDR, m)
#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_ADDR,v)
#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_ADDR,m,v,HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_IN)
#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_ROOT_OFF_BMSK                                            0x80000000
#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_ROOT_OFF_SHFT                                                  0x1f
#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                            0x10
#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                             0x4
#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_ROOT_EN_BMSK                                                    0x2
#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_ROOT_EN_SHFT                                                    0x1
#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_UPDATE_BMSK                                                     0x1
#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_UPDATE_SHFT                                                     0x0

#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0006f018)
#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_RMSK                                                       0x11071f
#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_ADDR)
#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_ADDR, m)
#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_ADDR,v)
#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_ADDR,m,v,HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_IN)
#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_HW_CLK_CONTROL_BMSK                                        0x100000
#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_HW_CLK_CONTROL_SHFT                                            0x14
#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_RCGLITE_DISABLE_BMSK                                        0x10000
#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_RCGLITE_DISABLE_SHFT                                           0x10
#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_SRC_SEL_BMSK                                                  0x700
#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_SRC_SEL_SHFT                                                    0x8
#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_SRC_DIV_BMSK                                                   0x1f
#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_SRC_DIV_SHFT                                                    0x0

#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0006f02c)
#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_RMSK                                                        0x80000005
#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_ADDR)
#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_ADDR, m)
#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_ADDR,v)
#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_ADDR,m,v,HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_IN)
#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0006f030)
#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_RMSK                                                        0x80000005
#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_ADDR)
#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_ADDR, m)
#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_ADDR,v)
#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_ADDR,m,v,HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_IN)
#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0006f034)
#define HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_RMSK                                                        0x80000005
#define HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_ADDR)
#define HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_ADDR, m)
#define HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_ADDR,v)
#define HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_ADDR,m,v,HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_IN)
#define HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_PCIE2_PHY_REFGEN_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_UFS_CARD_BCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00075000)
#define HWIO_GCC_UFS_CARD_BCR_RMSK                                                                        0x1
#define HWIO_GCC_UFS_CARD_BCR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_BCR_ADDR)
#define HWIO_GCC_UFS_CARD_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_BCR_ADDR, m)
#define HWIO_GCC_UFS_CARD_BCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_BCR_ADDR,v)
#define HWIO_GCC_UFS_CARD_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_BCR_ADDR,m,v,HWIO_GCC_UFS_CARD_BCR_IN)
#define HWIO_GCC_UFS_CARD_BCR_BLK_ARES_BMSK                                                               0x1
#define HWIO_GCC_UFS_CARD_BCR_BLK_ARES_SHFT                                                               0x0

#define HWIO_GCC_UFS_CARD_GDSCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00075004)
#define HWIO_GCC_UFS_CARD_GDSCR_RMSK                                                               0xf8ffffff
#define HWIO_GCC_UFS_CARD_GDSCR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_GDSCR_ADDR)
#define HWIO_GCC_UFS_CARD_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_GDSCR_ADDR, m)
#define HWIO_GCC_UFS_CARD_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_GDSCR_ADDR,v)
#define HWIO_GCC_UFS_CARD_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_GDSCR_ADDR,m,v,HWIO_GCC_UFS_CARD_GDSCR_IN)
#define HWIO_GCC_UFS_CARD_GDSCR_PWR_ON_BMSK                                                        0x80000000
#define HWIO_GCC_UFS_CARD_GDSCR_PWR_ON_SHFT                                                              0x1f
#define HWIO_GCC_UFS_CARD_GDSCR_GDSC_STATE_BMSK                                                    0x78000000
#define HWIO_GCC_UFS_CARD_GDSCR_GDSC_STATE_SHFT                                                          0x1b
#define HWIO_GCC_UFS_CARD_GDSCR_EN_REST_WAIT_BMSK                                                    0xf00000
#define HWIO_GCC_UFS_CARD_GDSCR_EN_REST_WAIT_SHFT                                                        0x14
#define HWIO_GCC_UFS_CARD_GDSCR_EN_FEW_WAIT_BMSK                                                      0xf0000
#define HWIO_GCC_UFS_CARD_GDSCR_EN_FEW_WAIT_SHFT                                                         0x10
#define HWIO_GCC_UFS_CARD_GDSCR_CLK_DIS_WAIT_BMSK                                                      0xf000
#define HWIO_GCC_UFS_CARD_GDSCR_CLK_DIS_WAIT_SHFT                                                         0xc
#define HWIO_GCC_UFS_CARD_GDSCR_RETAIN_FF_ENABLE_BMSK                                                   0x800
#define HWIO_GCC_UFS_CARD_GDSCR_RETAIN_FF_ENABLE_SHFT                                                     0xb
#define HWIO_GCC_UFS_CARD_GDSCR_RESTORE_BMSK                                                            0x400
#define HWIO_GCC_UFS_CARD_GDSCR_RESTORE_SHFT                                                              0xa
#define HWIO_GCC_UFS_CARD_GDSCR_SAVE_BMSK                                                               0x200
#define HWIO_GCC_UFS_CARD_GDSCR_SAVE_SHFT                                                                 0x9
#define HWIO_GCC_UFS_CARD_GDSCR_RETAIN_BMSK                                                             0x100
#define HWIO_GCC_UFS_CARD_GDSCR_RETAIN_SHFT                                                               0x8
#define HWIO_GCC_UFS_CARD_GDSCR_EN_REST_BMSK                                                             0x80
#define HWIO_GCC_UFS_CARD_GDSCR_EN_REST_SHFT                                                              0x7
#define HWIO_GCC_UFS_CARD_GDSCR_EN_FEW_BMSK                                                              0x40
#define HWIO_GCC_UFS_CARD_GDSCR_EN_FEW_SHFT                                                               0x6
#define HWIO_GCC_UFS_CARD_GDSCR_CLAMP_IO_BMSK                                                            0x20
#define HWIO_GCC_UFS_CARD_GDSCR_CLAMP_IO_SHFT                                                             0x5
#define HWIO_GCC_UFS_CARD_GDSCR_CLK_DISABLE_BMSK                                                         0x10
#define HWIO_GCC_UFS_CARD_GDSCR_CLK_DISABLE_SHFT                                                          0x4
#define HWIO_GCC_UFS_CARD_GDSCR_PD_ARES_BMSK                                                              0x8
#define HWIO_GCC_UFS_CARD_GDSCR_PD_ARES_SHFT                                                              0x3
#define HWIO_GCC_UFS_CARD_GDSCR_SW_OVERRIDE_BMSK                                                          0x4
#define HWIO_GCC_UFS_CARD_GDSCR_SW_OVERRIDE_SHFT                                                          0x2
#define HWIO_GCC_UFS_CARD_GDSCR_HW_CONTROL_BMSK                                                           0x2
#define HWIO_GCC_UFS_CARD_GDSCR_HW_CONTROL_SHFT                                                           0x1
#define HWIO_GCC_UFS_CARD_GDSCR_SW_COLLAPSE_BMSK                                                          0x1
#define HWIO_GCC_UFS_CARD_GDSCR_SW_COLLAPSE_SHFT                                                          0x0

#define HWIO_GCC_UFS_CARD_CFG_GDSCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00075008)
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_RMSK                                                           0xffffffff
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_CFG_GDSCR_ADDR)
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_CFG_GDSCR_ADDR, m)
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_CFG_GDSCR_ADDR,v)
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_CFG_GDSCR_ADDR,m,v,HWIO_GCC_UFS_CARD_CFG_GDSCR_IN)
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_SPARE_CTRL_IN_BMSK                                        0xf0000000
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_SPARE_CTRL_IN_SHFT                                              0x1c
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK                                        0xc000000
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT                                             0x1a
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK                                         0x2000000
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT                                              0x19
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_PWR_UP_START_BMSK                                          0x1000000
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_PWR_UP_START_SHFT                                               0x18
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK                                   0xf00000
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT                                       0x14
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                                      0x80000
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                                         0x13
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK                                          0x40000
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT                                             0x12
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK                                          0x20000
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT                                             0x11
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK                                       0x10000
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT                                          0x10
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                                      0x8000
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                                         0xf
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                                     0x7800
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                                        0xb
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK                                             0x400
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT                                               0xa
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                                      0x200
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                                        0x9
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                                      0x100
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                                        0x8
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                                          0x80
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                                           0x7
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                                 0x60
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                                  0x5
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                                           0x10
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                                            0x4
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                     0x8
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                     0x3
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                                   0x4
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                                   0x2
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                       0x2
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                       0x1
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                                    0x1
#define HWIO_GCC_UFS_CARD_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                                    0x0

#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0007500c)
#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_RMSK                                                             0x1ffff
#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_CFG2_GDSCR_ADDR)
#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_CFG2_GDSCR_ADDR, m)
#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_CFG2_GDSCR_ADDR,v)
#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_UFS_CARD_CFG2_GDSCR_IN)
#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK                                           0x10000
#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT                                              0x10
#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK                                               0xf000
#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT                                                  0xc
#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                                        0xf00
#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                                          0x8
#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                                           0xf0
#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                                            0x4
#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                                             0xf
#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                                             0x0

#define HWIO_GCC_UFS_CARD_AXI_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00075010)
#define HWIO_GCC_UFS_CARD_AXI_CBCR_RMSK                                                            0x80007ff7
#define HWIO_GCC_UFS_CARD_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_AXI_CBCR_ADDR)
#define HWIO_GCC_UFS_CARD_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_AXI_CBCR_ADDR, m)
#define HWIO_GCC_UFS_CARD_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_AXI_CBCR_ADDR,v)
#define HWIO_GCC_UFS_CARD_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_AXI_CBCR_ADDR,m,v,HWIO_GCC_UFS_CARD_AXI_CBCR_IN)
#define HWIO_GCC_UFS_CARD_AXI_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_UFS_CARD_AXI_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_UFS_CARD_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK                                              0x4000
#define HWIO_GCC_UFS_CARD_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT                                                 0xe
#define HWIO_GCC_UFS_CARD_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                            0x2000
#define HWIO_GCC_UFS_CARD_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                               0xd
#define HWIO_GCC_UFS_CARD_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                           0x1000
#define HWIO_GCC_UFS_CARD_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                              0xc
#define HWIO_GCC_UFS_CARD_AXI_CBCR_WAKEUP_BMSK                                                          0xf00
#define HWIO_GCC_UFS_CARD_AXI_CBCR_WAKEUP_SHFT                                                            0x8
#define HWIO_GCC_UFS_CARD_AXI_CBCR_SLEEP_BMSK                                                            0xf0
#define HWIO_GCC_UFS_CARD_AXI_CBCR_SLEEP_SHFT                                                             0x4
#define HWIO_GCC_UFS_CARD_AXI_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_UFS_CARD_AXI_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_UFS_CARD_AXI_CBCR_HW_CTL_BMSK                                                            0x2
#define HWIO_GCC_UFS_CARD_AXI_CBCR_HW_CTL_SHFT                                                            0x1
#define HWIO_GCC_UFS_CARD_AXI_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_UFS_CARD_AXI_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_UFS_CARD_AXI_SREGR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00075014)
#define HWIO_GCC_UFS_CARD_AXI_SREGR_RMSK                                                           0xfffff37e
#define HWIO_GCC_UFS_CARD_AXI_SREGR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_AXI_SREGR_ADDR)
#define HWIO_GCC_UFS_CARD_AXI_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_AXI_SREGR_ADDR, m)
#define HWIO_GCC_UFS_CARD_AXI_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_AXI_SREGR_ADDR,v)
#define HWIO_GCC_UFS_CARD_AXI_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_AXI_SREGR_ADDR,m,v,HWIO_GCC_UFS_CARD_AXI_SREGR_IN)
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                                 0xff000000
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                       0x18
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                    0xff0000
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                        0x10
#define HWIO_GCC_UFS_CARD_AXI_SREGR_RESERVE_BITS15_13_BMSK                                             0xe000
#define HWIO_GCC_UFS_CARD_AXI_SREGR_RESERVE_BITS15_13_SHFT                                                0xd
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                   0x1000
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                      0xc
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                       0x300
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                         0x8
#define HWIO_GCC_UFS_CARD_AXI_SREGR_FORCE_CLK_ON_BMSK                                                    0x40
#define HWIO_GCC_UFS_CARD_AXI_SREGR_FORCE_CLK_ON_SHFT                                                     0x6
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK                                              0x20
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT                                               0x5
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SW_RST_SLP_STG_BMSK                                                  0x10
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SW_RST_SLP_STG_SHFT                                                   0x4
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK                                                 0x8
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT                                                 0x3
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                            0x4
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                            0x2
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK                                                0x2
#define HWIO_GCC_UFS_CARD_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT                                                0x1

#define HWIO_GCC_UFS_CARD_AHB_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00075018)
#define HWIO_GCC_UFS_CARD_AHB_CBCR_RMSK                                                            0x80100007
#define HWIO_GCC_UFS_CARD_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_AHB_CBCR_ADDR)
#define HWIO_GCC_UFS_CARD_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_AHB_CBCR_ADDR, m)
#define HWIO_GCC_UFS_CARD_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_AHB_CBCR_ADDR,v)
#define HWIO_GCC_UFS_CARD_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_AHB_CBCR_ADDR,m,v,HWIO_GCC_UFS_CARD_AHB_CBCR_IN)
#define HWIO_GCC_UFS_CARD_AHB_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_UFS_CARD_AHB_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_UFS_CARD_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                          0x100000
#define HWIO_GCC_UFS_CARD_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                              0x14
#define HWIO_GCC_UFS_CARD_AHB_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_UFS_CARD_AHB_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_UFS_CARD_AHB_CBCR_HW_CTL_BMSK                                                            0x2
#define HWIO_GCC_UFS_CARD_AHB_CBCR_HW_CTL_SHFT                                                            0x1
#define HWIO_GCC_UFS_CARD_AHB_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_UFS_CARD_AHB_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0007501c)
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_RMSK                                                    0x80000005
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_ADDR)
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_ADDR, m)
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_ADDR,v)
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_ADDR,m,v,HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_IN)
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00075020)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_RMSK                                                    0x80000005
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_ADDR)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_ADDR, m)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_ADDR,v)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_ADDR,m,v,HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_IN)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00075024)
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_RMSK                                                        0x800000f3
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_ADDR)
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_ADDR, m)
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_ADDR,v)
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_ADDR,m,v,HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_IN)
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_ROOT_OFF_BMSK                                               0x80000000
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_ROOT_OFF_SHFT                                                     0x1f
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_DIRTY_D_BMSK                                                      0x80
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_DIRTY_D_SHFT                                                       0x7
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_DIRTY_N_BMSK                                                      0x40
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_DIRTY_N_SHFT                                                       0x6
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_DIRTY_M_BMSK                                                      0x20
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_DIRTY_M_SHFT                                                       0x5
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                               0x10
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                0x4
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_ROOT_EN_BMSK                                                       0x2
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_ROOT_EN_SHFT                                                       0x1
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_UPDATE_BMSK                                                        0x1
#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_UPDATE_SHFT                                                        0x0

#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00075028)
#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_RMSK                                                          0x10371f
#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_ADDR)
#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_ADDR, m)
#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_ADDR,v)
#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_ADDR,m,v,HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_IN)
#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_HW_CLK_CONTROL_BMSK                                           0x100000
#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_HW_CLK_CONTROL_SHFT                                               0x14
#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_MODE_BMSK                                                       0x3000
#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_MODE_SHFT                                                          0xc
#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_SRC_SEL_BMSK                                                     0x700
#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_SRC_SEL_SHFT                                                       0x8
#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_SRC_DIV_BMSK                                                      0x1f
#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_SRC_DIV_SHFT                                                       0x0

#define HWIO_GCC_UFS_CARD_AXI_M_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007502c)
#define HWIO_GCC_UFS_CARD_AXI_M_RMSK                                                                     0xff
#define HWIO_GCC_UFS_CARD_AXI_M_IN          \
        in_dword(HWIO_GCC_UFS_CARD_AXI_M_ADDR)
#define HWIO_GCC_UFS_CARD_AXI_M_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_AXI_M_ADDR, m)
#define HWIO_GCC_UFS_CARD_AXI_M_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_AXI_M_ADDR,v)
#define HWIO_GCC_UFS_CARD_AXI_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_AXI_M_ADDR,m,v,HWIO_GCC_UFS_CARD_AXI_M_IN)
#define HWIO_GCC_UFS_CARD_AXI_M_M_BMSK                                                                   0xff
#define HWIO_GCC_UFS_CARD_AXI_M_M_SHFT                                                                    0x0

#define HWIO_GCC_UFS_CARD_AXI_N_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00075030)
#define HWIO_GCC_UFS_CARD_AXI_N_RMSK                                                                     0xff
#define HWIO_GCC_UFS_CARD_AXI_N_IN          \
        in_dword(HWIO_GCC_UFS_CARD_AXI_N_ADDR)
#define HWIO_GCC_UFS_CARD_AXI_N_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_AXI_N_ADDR, m)
#define HWIO_GCC_UFS_CARD_AXI_N_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_AXI_N_ADDR,v)
#define HWIO_GCC_UFS_CARD_AXI_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_AXI_N_ADDR,m,v,HWIO_GCC_UFS_CARD_AXI_N_IN)
#define HWIO_GCC_UFS_CARD_AXI_N_NOT_N_MINUS_M_BMSK                                                       0xff
#define HWIO_GCC_UFS_CARD_AXI_N_NOT_N_MINUS_M_SHFT                                                        0x0

#define HWIO_GCC_UFS_CARD_AXI_D_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00075034)
#define HWIO_GCC_UFS_CARD_AXI_D_RMSK                                                                     0xff
#define HWIO_GCC_UFS_CARD_AXI_D_IN          \
        in_dword(HWIO_GCC_UFS_CARD_AXI_D_ADDR)
#define HWIO_GCC_UFS_CARD_AXI_D_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_AXI_D_ADDR, m)
#define HWIO_GCC_UFS_CARD_AXI_D_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_AXI_D_ADDR,v)
#define HWIO_GCC_UFS_CARD_AXI_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_AXI_D_ADDR,m,v,HWIO_GCC_UFS_CARD_AXI_D_IN)
#define HWIO_GCC_UFS_CARD_AXI_D_NOT_2D_BMSK                                                              0xff
#define HWIO_GCC_UFS_CARD_AXI_D_NOT_2D_SHFT                                                               0x0

#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00075040)
#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_RMSK                                                0xf
#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_IN          \
        in_dword(HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_ADDR)
#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_ADDR, m)
#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_ADDR,v)
#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_IN)
#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_CLK_DIV_BMSK                                        0xf
#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_CLK_DIV_SHFT                                        0x0

#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00075050)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_RMSK                                                0xf
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_IN          \
        in_dword(HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_ADDR)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_ADDR, m)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_ADDR,v)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_IN)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_CLK_DIV_BMSK                                        0xf
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_CLK_DIV_SHFT                                        0x0

#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0007505c)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_RMSK                                                    0x80007ff7
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_ADDR)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_ADDR, m)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_ADDR,v)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_ADDR,m,v,HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_IN)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_FORCE_MEM_CORE_ON_BMSK                                      0x4000
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_FORCE_MEM_CORE_ON_SHFT                                         0xe
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                    0x2000
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                       0xd
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                   0x1000
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                      0xc
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_WAKEUP_BMSK                                                  0xf00
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_WAKEUP_SHFT                                                    0x8
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_SLEEP_BMSK                                                    0xf0
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_SLEEP_SHFT                                                     0x4
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_HW_CTL_BMSK                                                    0x2
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_HW_CTL_SHFT                                                    0x1
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00075060)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_RMSK                                                   0xfffff37e
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_ADDR)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_ADDR, m)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_ADDR,v)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_ADDR,m,v,HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_IN)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                         0xff000000
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                               0x18
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                            0xff0000
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                0x10
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_RESERVE_BITS15_13_BMSK                                     0xe000
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_RESERVE_BITS15_13_SHFT                                        0xd
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                           0x1000
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                              0xc
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                               0x300
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                 0x8
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_FORCE_CLK_ON_BMSK                                            0x40
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_FORCE_CLK_ON_SHFT                                             0x6
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SW_RST_SEL_SLP_STG_BMSK                                      0x20
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SW_RST_SEL_SLP_STG_SHFT                                       0x5
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SW_RST_SLP_STG_BMSK                                          0x10
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SW_RST_SLP_STG_SHFT                                           0x4
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SW_CTRL_PWR_DOWN_BMSK                                         0x8
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SW_CTRL_PWR_DOWN_SHFT                                         0x3
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                    0x4
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                    0x2
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SW_CLK_EN_SLP_STG_BMSK                                        0x2
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_SREGR_SW_CLK_EN_SLP_STG_SHFT                                        0x1

#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00075064)
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_RMSK                                                       0x80007ff7
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_ADDR)
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_ADDR, m)
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_ADDR,v)
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_ADDR,m,v,HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_IN)
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_FORCE_MEM_CORE_ON_BMSK                                         0x4000
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_FORCE_MEM_CORE_ON_SHFT                                            0xe
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                       0x2000
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                          0xd
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                      0x1000
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                         0xc
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_WAKEUP_BMSK                                                     0xf00
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_WAKEUP_SHFT                                                       0x8
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_SLEEP_BMSK                                                       0xf0
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_SLEEP_SHFT                                                        0x4
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_HW_CTL_BMSK                                                       0x2
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_HW_CTL_SHFT                                                       0x1
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00075068)
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_RMSK                                                      0xfffff37e
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_ADDR)
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_ADDR, m)
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_ADDR,v)
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_ADDR,m,v,HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_IN)
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                            0xff000000
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                  0x18
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                               0xff0000
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                   0x10
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_RESERVE_BITS15_13_BMSK                                        0xe000
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_RESERVE_BITS15_13_SHFT                                           0xd
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                              0x1000
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                 0xc
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                  0x300
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                    0x8
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_FORCE_CLK_ON_BMSK                                               0x40
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_FORCE_CLK_ON_SHFT                                                0x6
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SW_RST_SEL_SLP_STG_BMSK                                         0x20
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SW_RST_SEL_SLP_STG_SHFT                                          0x5
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SW_RST_SLP_STG_BMSK                                             0x10
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SW_RST_SLP_STG_SHFT                                              0x4
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SW_CTRL_PWR_DOWN_BMSK                                            0x8
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SW_CTRL_PWR_DOWN_SHFT                                            0x3
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                       0x4
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                       0x2
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SW_CLK_EN_SLP_STG_BMSK                                           0x2
#define HWIO_GCC_UFS_CARD_ICE_CORE_SREGR_SW_CLK_EN_SLP_STG_SHFT                                           0x1

#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0007506c)
#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_RMSK                                                   0x80000013
#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_ADDR)
#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_ADDR, m)
#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_ADDR,v)
#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_ADDR,m,v,HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_IN)
#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_ROOT_OFF_BMSK                                          0x80000000
#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_ROOT_OFF_SHFT                                                0x1f
#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                          0x10
#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                           0x4
#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_ROOT_EN_BMSK                                                  0x2
#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_ROOT_EN_SHFT                                                  0x1
#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_UPDATE_BMSK                                                   0x1
#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_UPDATE_SHFT                                                   0x0

#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00075070)
#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_RMSK                                                     0x11071f
#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_ADDR)
#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_ADDR, m)
#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_ADDR,v)
#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_ADDR,m,v,HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_IN)
#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_HW_CLK_CONTROL_BMSK                                      0x100000
#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_HW_CLK_CONTROL_SHFT                                          0x14
#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_RCGLITE_DISABLE_BMSK                                      0x10000
#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_RCGLITE_DISABLE_SHFT                                         0x10
#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00075084)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_RMSK                                                0x80000013
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_ADDR)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_ADDR, m)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_ADDR,v)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_ADDR,m,v,HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_IN)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_ROOT_OFF_BMSK                                       0x80000000
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_ROOT_OFF_SHFT                                             0x1f
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                       0x10
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                        0x4
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_ROOT_EN_BMSK                                               0x2
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_ROOT_EN_SHFT                                               0x1
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_UPDATE_BMSK                                                0x1
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_UPDATE_SHFT                                                0x0

#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00075088)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_RMSK                                                  0x11071f
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_ADDR)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_ADDR, m)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_ADDR,v)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_ADDR,m,v,HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_IN)
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_HW_CLK_CONTROL_BMSK                                   0x100000
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_HW_CLK_CONTROL_SHFT                                       0x14
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_RCGLITE_DISABLE_BMSK                                   0x10000
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_RCGLITE_DISABLE_SHFT                                      0x10
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_SRC_SEL_BMSK                                             0x700
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_SRC_SEL_SHFT                                               0x8
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_SRC_DIV_BMSK                                              0x1f
#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_SRC_DIV_SHFT                                               0x0

#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0007509c)
#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_RMSK                                                        0x80000007
#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_ADDR)
#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_ADDR, m)
#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_ADDR,v)
#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_ADDR,m,v,HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_IN)
#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_HW_CTL_BMSK                                                        0x2
#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_HW_CTL_SHFT                                                        0x1
#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000750a0)
#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_RMSK                                                    0x80000013
#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_ADDR)
#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_ADDR, m)
#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_ADDR,v)
#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_ADDR,m,v,HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_IN)
#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_ROOT_OFF_BMSK                                           0x80000000
#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_ROOT_OFF_SHFT                                                 0x1f
#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                           0x10
#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                            0x4
#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_ROOT_EN_BMSK                                                   0x2
#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_ROOT_EN_SHFT                                                   0x1
#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_UPDATE_BMSK                                                    0x1
#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_UPDATE_SHFT                                                    0x0

#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000750a4)
#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_RMSK                                                      0x11071f
#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_ADDR)
#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_ADDR, m)
#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_ADDR,v)
#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_ADDR,m,v,HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_IN)
#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_BMSK                                       0x100000
#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_SHFT                                           0x14
#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_RCGLITE_DISABLE_BMSK                                       0x10000
#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_RCGLITE_DISABLE_SHFT                                          0x10
#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_SRC_SEL_BMSK                                                 0x700
#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_SRC_SEL_SHFT                                                   0x8
#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_SRC_DIV_SHFT                                                   0x0

#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000750b8)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_RMSK                                                    0x80000005
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_ADDR)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_ADDR, m)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_ADDR,v)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_ADDR,m,v,HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_IN)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x000750c0)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_RMSK                                                0xf
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_IN          \
        in_dword(HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_ADDR)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_ADDR, m)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_ADDR,v)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_IN)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_CLK_DIV_BMSK                                        0xf
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_CLK_DIV_SHFT                                        0x0

#define HWIO_GCC_UFS_PHY_BCR_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00077000)
#define HWIO_GCC_UFS_PHY_BCR_RMSK                                                                         0x1
#define HWIO_GCC_UFS_PHY_BCR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_BCR_ADDR)
#define HWIO_GCC_UFS_PHY_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_BCR_ADDR, m)
#define HWIO_GCC_UFS_PHY_BCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_BCR_ADDR,v)
#define HWIO_GCC_UFS_PHY_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_BCR_ADDR,m,v,HWIO_GCC_UFS_PHY_BCR_IN)
#define HWIO_GCC_UFS_PHY_BCR_BLK_ARES_BMSK                                                                0x1
#define HWIO_GCC_UFS_PHY_BCR_BLK_ARES_SHFT                                                                0x0

#define HWIO_GCC_UFS_PHY_GDSCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00077004)
#define HWIO_GCC_UFS_PHY_GDSCR_RMSK                                                                0xf8ffffff
#define HWIO_GCC_UFS_PHY_GDSCR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_GDSCR_ADDR)
#define HWIO_GCC_UFS_PHY_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_GDSCR_ADDR, m)
#define HWIO_GCC_UFS_PHY_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_GDSCR_ADDR,v)
#define HWIO_GCC_UFS_PHY_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_GDSCR_ADDR,m,v,HWIO_GCC_UFS_PHY_GDSCR_IN)
#define HWIO_GCC_UFS_PHY_GDSCR_PWR_ON_BMSK                                                         0x80000000
#define HWIO_GCC_UFS_PHY_GDSCR_PWR_ON_SHFT                                                               0x1f
#define HWIO_GCC_UFS_PHY_GDSCR_GDSC_STATE_BMSK                                                     0x78000000
#define HWIO_GCC_UFS_PHY_GDSCR_GDSC_STATE_SHFT                                                           0x1b
#define HWIO_GCC_UFS_PHY_GDSCR_EN_REST_WAIT_BMSK                                                     0xf00000
#define HWIO_GCC_UFS_PHY_GDSCR_EN_REST_WAIT_SHFT                                                         0x14
#define HWIO_GCC_UFS_PHY_GDSCR_EN_FEW_WAIT_BMSK                                                       0xf0000
#define HWIO_GCC_UFS_PHY_GDSCR_EN_FEW_WAIT_SHFT                                                          0x10
#define HWIO_GCC_UFS_PHY_GDSCR_CLK_DIS_WAIT_BMSK                                                       0xf000
#define HWIO_GCC_UFS_PHY_GDSCR_CLK_DIS_WAIT_SHFT                                                          0xc
#define HWIO_GCC_UFS_PHY_GDSCR_RETAIN_FF_ENABLE_BMSK                                                    0x800
#define HWIO_GCC_UFS_PHY_GDSCR_RETAIN_FF_ENABLE_SHFT                                                      0xb
#define HWIO_GCC_UFS_PHY_GDSCR_RESTORE_BMSK                                                             0x400
#define HWIO_GCC_UFS_PHY_GDSCR_RESTORE_SHFT                                                               0xa
#define HWIO_GCC_UFS_PHY_GDSCR_SAVE_BMSK                                                                0x200
#define HWIO_GCC_UFS_PHY_GDSCR_SAVE_SHFT                                                                  0x9
#define HWIO_GCC_UFS_PHY_GDSCR_RETAIN_BMSK                                                              0x100
#define HWIO_GCC_UFS_PHY_GDSCR_RETAIN_SHFT                                                                0x8
#define HWIO_GCC_UFS_PHY_GDSCR_EN_REST_BMSK                                                              0x80
#define HWIO_GCC_UFS_PHY_GDSCR_EN_REST_SHFT                                                               0x7
#define HWIO_GCC_UFS_PHY_GDSCR_EN_FEW_BMSK                                                               0x40
#define HWIO_GCC_UFS_PHY_GDSCR_EN_FEW_SHFT                                                                0x6
#define HWIO_GCC_UFS_PHY_GDSCR_CLAMP_IO_BMSK                                                             0x20
#define HWIO_GCC_UFS_PHY_GDSCR_CLAMP_IO_SHFT                                                              0x5
#define HWIO_GCC_UFS_PHY_GDSCR_CLK_DISABLE_BMSK                                                          0x10
#define HWIO_GCC_UFS_PHY_GDSCR_CLK_DISABLE_SHFT                                                           0x4
#define HWIO_GCC_UFS_PHY_GDSCR_PD_ARES_BMSK                                                               0x8
#define HWIO_GCC_UFS_PHY_GDSCR_PD_ARES_SHFT                                                               0x3
#define HWIO_GCC_UFS_PHY_GDSCR_SW_OVERRIDE_BMSK                                                           0x4
#define HWIO_GCC_UFS_PHY_GDSCR_SW_OVERRIDE_SHFT                                                           0x2
#define HWIO_GCC_UFS_PHY_GDSCR_HW_CONTROL_BMSK                                                            0x2
#define HWIO_GCC_UFS_PHY_GDSCR_HW_CONTROL_SHFT                                                            0x1
#define HWIO_GCC_UFS_PHY_GDSCR_SW_COLLAPSE_BMSK                                                           0x1
#define HWIO_GCC_UFS_PHY_GDSCR_SW_COLLAPSE_SHFT                                                           0x0

#define HWIO_GCC_UFS_PHY_CFG_GDSCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00077008)
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_RMSK                                                            0xffffffff
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_CFG_GDSCR_ADDR)
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_CFG_GDSCR_ADDR, m)
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_CFG_GDSCR_ADDR,v)
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_CFG_GDSCR_ADDR,m,v,HWIO_GCC_UFS_PHY_CFG_GDSCR_IN)
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_SPARE_CTRL_IN_BMSK                                         0xf0000000
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_SPARE_CTRL_IN_SHFT                                               0x1c
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK                                         0xc000000
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT                                              0x1a
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK                                          0x2000000
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT                                               0x19
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PWR_UP_START_BMSK                                           0x1000000
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PWR_UP_START_SHFT                                                0x18
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK                                    0xf00000
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT                                        0x14
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                                       0x80000
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                                          0x13
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK                                           0x40000
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT                                              0x12
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK                                           0x20000
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT                                              0x11
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK                                        0x10000
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT                                           0x10
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                                       0x8000
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                                          0xf
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                                      0x7800
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                                         0xb
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK                                              0x400
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT                                                0xa
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                                       0x200
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                                         0x9
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                                       0x100
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                                         0x8
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                                           0x80
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                                            0x7
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                                  0x60
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                                   0x5
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                                            0x10
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                                             0x4
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                      0x8
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                      0x3
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                                    0x4
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                                    0x2
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                        0x2
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                        0x1
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                                     0x1
#define HWIO_GCC_UFS_PHY_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                                     0x0

#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0007700c)
#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_RMSK                                                              0x1ffff
#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_CFG2_GDSCR_ADDR)
#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_CFG2_GDSCR_ADDR, m)
#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_CFG2_GDSCR_ADDR,v)
#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_UFS_PHY_CFG2_GDSCR_IN)
#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK                                            0x10000
#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT                                               0x10
#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK                                                0xf000
#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT                                                   0xc
#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                                         0xf00
#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                                           0x8
#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                                            0xf0
#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                                             0x4
#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                                              0xf
#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                                              0x0

#define HWIO_GCC_UFS_PHY_AXI_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00077010)
#define HWIO_GCC_UFS_PHY_AXI_CBCR_RMSK                                                             0x80007ff7
#define HWIO_GCC_UFS_PHY_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_AXI_CBCR_ADDR)
#define HWIO_GCC_UFS_PHY_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_AXI_CBCR_ADDR, m)
#define HWIO_GCC_UFS_PHY_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_AXI_CBCR_ADDR,v)
#define HWIO_GCC_UFS_PHY_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_AXI_CBCR_ADDR,m,v,HWIO_GCC_UFS_PHY_AXI_CBCR_IN)
#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK                                               0x4000
#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT                                                  0xe
#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                             0x2000
#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                0xd
#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                            0x1000
#define HWIO_GCC_UFS_PHY_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                               0xc
#define HWIO_GCC_UFS_PHY_AXI_CBCR_WAKEUP_BMSK                                                           0xf00
#define HWIO_GCC_UFS_PHY_AXI_CBCR_WAKEUP_SHFT                                                             0x8
#define HWIO_GCC_UFS_PHY_AXI_CBCR_SLEEP_BMSK                                                             0xf0
#define HWIO_GCC_UFS_PHY_AXI_CBCR_SLEEP_SHFT                                                              0x4
#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_UFS_PHY_AXI_CBCR_HW_CTL_BMSK                                                             0x2
#define HWIO_GCC_UFS_PHY_AXI_CBCR_HW_CTL_SHFT                                                             0x1
#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_UFS_PHY_AXI_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_UFS_PHY_AXI_SREGR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00077014)
#define HWIO_GCC_UFS_PHY_AXI_SREGR_RMSK                                                            0xfffff37e
#define HWIO_GCC_UFS_PHY_AXI_SREGR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_AXI_SREGR_ADDR)
#define HWIO_GCC_UFS_PHY_AXI_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_AXI_SREGR_ADDR, m)
#define HWIO_GCC_UFS_PHY_AXI_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_AXI_SREGR_ADDR,v)
#define HWIO_GCC_UFS_PHY_AXI_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_AXI_SREGR_ADDR,m,v,HWIO_GCC_UFS_PHY_AXI_SREGR_IN)
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                                  0xff000000
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                        0x18
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                     0xff0000
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                         0x10
#define HWIO_GCC_UFS_PHY_AXI_SREGR_RESERVE_BITS15_13_BMSK                                              0xe000
#define HWIO_GCC_UFS_PHY_AXI_SREGR_RESERVE_BITS15_13_SHFT                                                 0xd
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                    0x1000
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                       0xc
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                        0x300
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                          0x8
#define HWIO_GCC_UFS_PHY_AXI_SREGR_FORCE_CLK_ON_BMSK                                                     0x40
#define HWIO_GCC_UFS_PHY_AXI_SREGR_FORCE_CLK_ON_SHFT                                                      0x6
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK                                               0x20
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT                                                0x5
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_RST_SLP_STG_BMSK                                                   0x10
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_RST_SLP_STG_SHFT                                                    0x4
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK                                                  0x8
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT                                                  0x3
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                             0x4
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                             0x2
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK                                                 0x2
#define HWIO_GCC_UFS_PHY_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT                                                 0x1

#define HWIO_GCC_UFS_PHY_AHB_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00077018)
#define HWIO_GCC_UFS_PHY_AHB_CBCR_RMSK                                                             0x80100007
#define HWIO_GCC_UFS_PHY_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_AHB_CBCR_ADDR)
#define HWIO_GCC_UFS_PHY_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_AHB_CBCR_ADDR, m)
#define HWIO_GCC_UFS_PHY_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_AHB_CBCR_ADDR,v)
#define HWIO_GCC_UFS_PHY_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_AHB_CBCR_ADDR,m,v,HWIO_GCC_UFS_PHY_AHB_CBCR_IN)
#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_UFS_PHY_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_UFS_PHY_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_UFS_PHY_AHB_CBCR_HW_CTL_BMSK                                                             0x2
#define HWIO_GCC_UFS_PHY_AHB_CBCR_HW_CTL_SHFT                                                             0x1
#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_UFS_PHY_AHB_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0007701c)
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_RMSK                                                     0x80000005
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_ADDR)
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_ADDR, m)
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_ADDR,v)
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_ADDR,m,v,HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_IN)
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00077020)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_RMSK                                                     0x80000005
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_ADDR)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_ADDR, m)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_ADDR,v)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_ADDR,m,v,HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_IN)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00077024)
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_RMSK                                                         0x800000f3
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ADDR)
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ADDR, m)
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ADDR,v)
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ADDR,m,v,HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_IN)
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ROOT_OFF_BMSK                                                0x80000000
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ROOT_OFF_SHFT                                                      0x1f
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_DIRTY_D_BMSK                                                       0x80
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_DIRTY_D_SHFT                                                        0x7
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_DIRTY_N_BMSK                                                       0x40
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_DIRTY_N_SHFT                                                        0x6
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_DIRTY_M_BMSK                                                       0x20
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_DIRTY_M_SHFT                                                        0x5
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                0x10
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                 0x4
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ROOT_EN_BMSK                                                        0x2
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ROOT_EN_SHFT                                                        0x1
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_UPDATE_BMSK                                                         0x1
#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_UPDATE_SHFT                                                         0x0

#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00077028)
#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_RMSK                                                           0x10371f
#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_ADDR)
#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_ADDR, m)
#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_ADDR,v)
#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_ADDR,m,v,HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_IN)
#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_HW_CLK_CONTROL_BMSK                                            0x100000
#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                0x14
#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_MODE_BMSK                                                        0x3000
#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_MODE_SHFT                                                           0xc
#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_SEL_BMSK                                                      0x700
#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_SEL_SHFT                                                        0x8
#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_BMSK                                                       0x1f
#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_SRC_DIV_SHFT                                                        0x0

#define HWIO_GCC_UFS_PHY_AXI_M_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0007702c)
#define HWIO_GCC_UFS_PHY_AXI_M_RMSK                                                                      0xff
#define HWIO_GCC_UFS_PHY_AXI_M_IN          \
        in_dword(HWIO_GCC_UFS_PHY_AXI_M_ADDR)
#define HWIO_GCC_UFS_PHY_AXI_M_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_AXI_M_ADDR, m)
#define HWIO_GCC_UFS_PHY_AXI_M_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_AXI_M_ADDR,v)
#define HWIO_GCC_UFS_PHY_AXI_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_AXI_M_ADDR,m,v,HWIO_GCC_UFS_PHY_AXI_M_IN)
#define HWIO_GCC_UFS_PHY_AXI_M_M_BMSK                                                                    0xff
#define HWIO_GCC_UFS_PHY_AXI_M_M_SHFT                                                                     0x0

#define HWIO_GCC_UFS_PHY_AXI_N_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00077030)
#define HWIO_GCC_UFS_PHY_AXI_N_RMSK                                                                      0xff
#define HWIO_GCC_UFS_PHY_AXI_N_IN          \
        in_dword(HWIO_GCC_UFS_PHY_AXI_N_ADDR)
#define HWIO_GCC_UFS_PHY_AXI_N_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_AXI_N_ADDR, m)
#define HWIO_GCC_UFS_PHY_AXI_N_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_AXI_N_ADDR,v)
#define HWIO_GCC_UFS_PHY_AXI_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_AXI_N_ADDR,m,v,HWIO_GCC_UFS_PHY_AXI_N_IN)
#define HWIO_GCC_UFS_PHY_AXI_N_NOT_N_MINUS_M_BMSK                                                        0xff
#define HWIO_GCC_UFS_PHY_AXI_N_NOT_N_MINUS_M_SHFT                                                         0x0

#define HWIO_GCC_UFS_PHY_AXI_D_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00077034)
#define HWIO_GCC_UFS_PHY_AXI_D_RMSK                                                                      0xff
#define HWIO_GCC_UFS_PHY_AXI_D_IN          \
        in_dword(HWIO_GCC_UFS_PHY_AXI_D_ADDR)
#define HWIO_GCC_UFS_PHY_AXI_D_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_AXI_D_ADDR, m)
#define HWIO_GCC_UFS_PHY_AXI_D_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_AXI_D_ADDR,v)
#define HWIO_GCC_UFS_PHY_AXI_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_AXI_D_ADDR,m,v,HWIO_GCC_UFS_PHY_AXI_D_IN)
#define HWIO_GCC_UFS_PHY_AXI_D_NOT_2D_BMSK                                                               0xff
#define HWIO_GCC_UFS_PHY_AXI_D_NOT_2D_SHFT                                                                0x0

#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00077040)
#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_RMSK                                                 0xf
#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_IN          \
        in_dword(HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_ADDR)
#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_ADDR, m)
#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_ADDR,v)
#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_IN)
#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_CLK_DIV_BMSK                                         0xf
#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_CLK_DIV_SHFT                                         0x0

#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00077050)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_RMSK                                                 0xf
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_IN          \
        in_dword(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_ADDR)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_ADDR, m)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_ADDR,v)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_IN)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_CLK_DIV_BMSK                                         0xf
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_CLK_DIV_SHFT                                         0x0

#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0007705c)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_RMSK                                                     0x80007ff7
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_ADDR)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_ADDR, m)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_ADDR,v)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_ADDR,m,v,HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_IN)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_CORE_ON_BMSK                                       0x4000
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_CORE_ON_SHFT                                          0xe
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                     0x2000
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                        0xd
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                    0x1000
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                       0xc
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_WAKEUP_BMSK                                                   0xf00
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_WAKEUP_SHFT                                                     0x8
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_SLEEP_BMSK                                                     0xf0
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_SLEEP_SHFT                                                      0x4
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_HW_CTL_BMSK                                                     0x2
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_HW_CTL_SHFT                                                     0x1
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00077060)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_RMSK                                                    0xfffff37e
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_ADDR)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_ADDR, m)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_ADDR,v)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_ADDR,m,v,HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_IN)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                          0xff000000
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                0x18
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                             0xff0000
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                 0x10
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_RESERVE_BITS15_13_BMSK                                      0xe000
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_RESERVE_BITS15_13_SHFT                                         0xd
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                            0x1000
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                               0xc
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                0x300
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                  0x8
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_FORCE_CLK_ON_BMSK                                             0x40
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_FORCE_CLK_ON_SHFT                                              0x6
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_RST_SEL_SLP_STG_BMSK                                       0x20
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_RST_SEL_SLP_STG_SHFT                                        0x5
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_RST_SLP_STG_BMSK                                           0x10
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_RST_SLP_STG_SHFT                                            0x4
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CTRL_PWR_DOWN_BMSK                                          0x8
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CTRL_PWR_DOWN_SHFT                                          0x3
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                     0x4
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                     0x2
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CLK_EN_SLP_STG_BMSK                                         0x2
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_SREGR_SW_CLK_EN_SLP_STG_SHFT                                         0x1

#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00077064)
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_RMSK                                                        0x80007ff7
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_ADDR)
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_ADDR, m)
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_ADDR,v)
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_ADDR,m,v,HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_IN)
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_CORE_ON_BMSK                                          0x4000
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_CORE_ON_SHFT                                             0xe
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                        0x2000
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                           0xd
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                       0x1000
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                          0xc
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_WAKEUP_BMSK                                                      0xf00
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_WAKEUP_SHFT                                                        0x8
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_SLEEP_BMSK                                                        0xf0
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_SLEEP_SHFT                                                         0x4
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_HW_CTL_BMSK                                                        0x2
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_HW_CTL_SHFT                                                        0x1
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00077068)
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_RMSK                                                       0xfffff37e
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_ADDR)
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_ADDR, m)
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_ADDR,v)
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_ADDR,m,v,HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_IN)
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                             0xff000000
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                   0x18
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                0xff0000
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                    0x10
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_RESERVE_BITS15_13_BMSK                                         0xe000
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_RESERVE_BITS15_13_SHFT                                            0xd
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                               0x1000
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                  0xc
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                   0x300
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                     0x8
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_FORCE_CLK_ON_BMSK                                                0x40
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_FORCE_CLK_ON_SHFT                                                 0x6
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_RST_SEL_SLP_STG_BMSK                                          0x20
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_RST_SEL_SLP_STG_SHFT                                           0x5
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_RST_SLP_STG_BMSK                                              0x10
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_RST_SLP_STG_SHFT                                               0x4
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CTRL_PWR_DOWN_BMSK                                             0x8
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CTRL_PWR_DOWN_SHFT                                             0x3
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                        0x4
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                        0x2
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CLK_EN_SLP_STG_BMSK                                            0x2
#define HWIO_GCC_UFS_PHY_ICE_CORE_SREGR_SW_CLK_EN_SLP_STG_SHFT                                            0x1

#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0007706c)
#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_RMSK                                                    0x80000013
#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ADDR)
#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ADDR, m)
#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ADDR,v)
#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ADDR,m,v,HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_IN)
#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ROOT_OFF_BMSK                                           0x80000000
#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ROOT_OFF_SHFT                                                 0x1f
#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                           0x10
#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                            0x4
#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ROOT_EN_BMSK                                                   0x2
#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ROOT_EN_SHFT                                                   0x1
#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_UPDATE_BMSK                                                    0x1
#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_UPDATE_SHFT                                                    0x0

#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00077070)
#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_RMSK                                                      0x11071f
#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_ADDR)
#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_ADDR, m)
#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_ADDR,v)
#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_ADDR,m,v,HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_IN)
#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_HW_CLK_CONTROL_BMSK                                       0x100000
#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_HW_CLK_CONTROL_SHFT                                           0x14
#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_RCGLITE_DISABLE_BMSK                                       0x10000
#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_RCGLITE_DISABLE_SHFT                                          0x10
#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_SEL_BMSK                                                 0x700
#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_SEL_SHFT                                                   0x8
#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_SRC_DIV_SHFT                                                   0x0

#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00077084)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_RMSK                                                 0x80000013
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ADDR)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ADDR, m)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ADDR,v)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ADDR,m,v,HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_IN)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ROOT_OFF_BMSK                                        0x80000000
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ROOT_OFF_SHFT                                              0x1f
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                        0x10
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                         0x4
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ROOT_EN_BMSK                                                0x2
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ROOT_EN_SHFT                                                0x1
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_UPDATE_BMSK                                                 0x1
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_UPDATE_SHFT                                                 0x0

#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00077088)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_RMSK                                                   0x11071f
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_ADDR)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_ADDR, m)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_ADDR,v)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_ADDR,m,v,HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_IN)
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_HW_CLK_CONTROL_BMSK                                    0x100000
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_HW_CLK_CONTROL_SHFT                                        0x14
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_RCGLITE_DISABLE_BMSK                                    0x10000
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_RCGLITE_DISABLE_SHFT                                       0x10
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0007709c)
#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_RMSK                                                         0x80000007
#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_ADDR)
#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_ADDR, m)
#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_ADDR,v)
#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_ADDR,m,v,HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_IN)
#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_ARES_SHFT                                                       0x2
#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_HW_CTL_BMSK                                                         0x2
#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_HW_CTL_SHFT                                                         0x1
#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_CLK_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000770a0)
#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_RMSK                                                     0x80000013
#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ADDR)
#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ADDR, m)
#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ADDR,v)
#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ADDR,m,v,HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_IN)
#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ROOT_OFF_BMSK                                            0x80000000
#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ROOT_OFF_SHFT                                                  0x1f
#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                            0x10
#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                             0x4
#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ROOT_EN_BMSK                                                    0x2
#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ROOT_EN_SHFT                                                    0x1
#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_UPDATE_BMSK                                                     0x1
#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_UPDATE_SHFT                                                     0x0

#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000770a4)
#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_RMSK                                                       0x11071f
#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_ADDR)
#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_ADDR, m)
#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_ADDR,v)
#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_ADDR,m,v,HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_IN)
#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_BMSK                                        0x100000
#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_HW_CLK_CONTROL_SHFT                                            0x14
#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_RCGLITE_DISABLE_BMSK                                        0x10000
#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_RCGLITE_DISABLE_SHFT                                           0x10
#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_SEL_BMSK                                                  0x700
#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_SEL_SHFT                                                    0x8
#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_BMSK                                                   0x1f
#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_SRC_DIV_SHFT                                                    0x0

#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000770b8)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_RMSK                                                     0x80000005
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_ADDR)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_ADDR, m)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_ADDR,v)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_ADDR,m,v,HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_IN)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x000770c0)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_RMSK                                                 0xf
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_IN          \
        in_dword(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_ADDR)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_ADDR, m)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_ADDR,v)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_IN)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_CLK_DIV_BMSK                                         0xf
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_CLK_DIV_SHFT                                         0x0

#define HWIO_GCC_SSC_BCR_ADDR                                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00063000)
#define HWIO_GCC_SSC_BCR_RMSK                                                                             0x1
#define HWIO_GCC_SSC_BCR_IN          \
        in_dword(HWIO_GCC_SSC_BCR_ADDR)
#define HWIO_GCC_SSC_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SSC_BCR_ADDR, m)
#define HWIO_GCC_SSC_BCR_OUT(v)      \
        out_dword(HWIO_GCC_SSC_BCR_ADDR,v)
#define HWIO_GCC_SSC_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SSC_BCR_ADDR,m,v,HWIO_GCC_SSC_BCR_IN)
#define HWIO_GCC_SSC_BCR_BLK_ARES_BMSK                                                                    0x1
#define HWIO_GCC_SSC_BCR_BLK_ARES_SHFT                                                                    0x0

#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00063004)
#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_RMSK                                                      0x80100005
#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_IN          \
        in_dword(HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_ADDR)
#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_ADDR, m)
#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_ADDR,v)
#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_ADDR,m,v,HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_IN)
#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                    0x100000
#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                        0x14
#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_CLK_ENABLE_SHFT                                                  0x0

#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00063008)
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_RMSK                                                    0x80107ff7
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_ADDR)
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_ADDR, m)
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_ADDR,v)
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_ADDR,m,v,HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_IN)
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                  0x100000
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                      0x14
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK                                      0x4000
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT                                         0xe
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                    0x2000
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                       0xd
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                   0x1000
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                      0xc
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_WAKEUP_BMSK                                                  0xf00
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_WAKEUP_SHFT                                                    0x8
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_SLEEP_BMSK                                                    0xf0
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_SLEEP_SHFT                                                     0x4
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_HW_CTL_BMSK                                                    0x2
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_HW_CTL_SHFT                                                    0x1
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_SSC_Q6_AGGRE_NOC_AXI_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0006300c)
#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_RMSK                                                           0x80100005
#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_IN          \
        in_dword(HWIO_GCC_SSC_CNOC_AHBS_CBCR_ADDR)
#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SSC_CNOC_AHBS_CBCR_ADDR, m)
#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SSC_CNOC_AHBS_CBCR_ADDR,v)
#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SSC_CNOC_AHBS_CBCR_ADDR,m,v,HWIO_GCC_SSC_CNOC_AHBS_CBCR_IN)
#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_SSC_CNOC_MPU_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00063010)
#define HWIO_GCC_SSC_CNOC_MPU_CBCR_RMSK                                                            0x80100005
#define HWIO_GCC_SSC_CNOC_MPU_CBCR_IN          \
        in_dword(HWIO_GCC_SSC_CNOC_MPU_CBCR_ADDR)
#define HWIO_GCC_SSC_CNOC_MPU_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SSC_CNOC_MPU_CBCR_ADDR, m)
#define HWIO_GCC_SSC_CNOC_MPU_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SSC_CNOC_MPU_CBCR_ADDR,v)
#define HWIO_GCC_SSC_CNOC_MPU_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SSC_CNOC_MPU_CBCR_ADDR,m,v,HWIO_GCC_SSC_CNOC_MPU_CBCR_IN)
#define HWIO_GCC_SSC_CNOC_MPU_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_SSC_CNOC_MPU_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_SSC_CNOC_MPU_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                          0x100000
#define HWIO_GCC_SSC_CNOC_MPU_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                              0x14
#define HWIO_GCC_SSC_CNOC_MPU_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_SSC_CNOC_MPU_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_SSC_CNOC_MPU_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_SSC_CNOC_MPU_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_VS_BCR_ADDR                                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0007a000)
#define HWIO_GCC_VS_BCR_RMSK                                                                              0x1
#define HWIO_GCC_VS_BCR_IN          \
        in_dword(HWIO_GCC_VS_BCR_ADDR)
#define HWIO_GCC_VS_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_VS_BCR_ADDR, m)
#define HWIO_GCC_VS_BCR_OUT(v)      \
        out_dword(HWIO_GCC_VS_BCR_ADDR,v)
#define HWIO_GCC_VS_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VS_BCR_ADDR,m,v,HWIO_GCC_VS_BCR_IN)
#define HWIO_GCC_VS_BCR_BLK_ARES_BMSK                                                                     0x1
#define HWIO_GCC_VS_BCR_BLK_ARES_SHFT                                                                     0x0

#define HWIO_GCC_VDDCX_VS_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0007a004)
#define HWIO_GCC_VDDCX_VS_CBCR_RMSK                                                                0x80000005
#define HWIO_GCC_VDDCX_VS_CBCR_IN          \
        in_dword(HWIO_GCC_VDDCX_VS_CBCR_ADDR)
#define HWIO_GCC_VDDCX_VS_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_VDDCX_VS_CBCR_ADDR, m)
#define HWIO_GCC_VDDCX_VS_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_VDDCX_VS_CBCR_ADDR,v)
#define HWIO_GCC_VDDCX_VS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VDDCX_VS_CBCR_ADDR,m,v,HWIO_GCC_VDDCX_VS_CBCR_IN)
#define HWIO_GCC_VDDCX_VS_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_VDDCX_VS_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_VDDCX_VS_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_VDDMX_VS_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0007a008)
#define HWIO_GCC_VDDMX_VS_CBCR_RMSK                                                                0x80000005
#define HWIO_GCC_VDDMX_VS_CBCR_IN          \
        in_dword(HWIO_GCC_VDDMX_VS_CBCR_ADDR)
#define HWIO_GCC_VDDMX_VS_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_VDDMX_VS_CBCR_ADDR, m)
#define HWIO_GCC_VDDMX_VS_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_VDDMX_VS_CBCR_ADDR,v)
#define HWIO_GCC_VDDMX_VS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VDDMX_VS_CBCR_ADDR,m,v,HWIO_GCC_VDDMX_VS_CBCR_IN)
#define HWIO_GCC_VDDMX_VS_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_VDDMX_VS_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_VDDMX_VS_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_VDDA_VS_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0007a00c)
#define HWIO_GCC_VDDA_VS_CBCR_RMSK                                                                 0x80000005
#define HWIO_GCC_VDDA_VS_CBCR_IN          \
        in_dword(HWIO_GCC_VDDA_VS_CBCR_ADDR)
#define HWIO_GCC_VDDA_VS_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_VDDA_VS_CBCR_ADDR, m)
#define HWIO_GCC_VDDA_VS_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_VDDA_VS_CBCR_ADDR,v)
#define HWIO_GCC_VDDA_VS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VDDA_VS_CBCR_ADDR,m,v,HWIO_GCC_VDDA_VS_CBCR_IN)
#define HWIO_GCC_VDDA_VS_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_VDDA_VS_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_VDDA_VS_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_VDDA_VS_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_VDDA_VS_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_VDDA_VS_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_VS_CTRL_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0007a010)
#define HWIO_GCC_VS_CTRL_CBCR_RMSK                                                                 0x80000005
#define HWIO_GCC_VS_CTRL_CBCR_IN          \
        in_dword(HWIO_GCC_VS_CTRL_CBCR_ADDR)
#define HWIO_GCC_VS_CTRL_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_VS_CTRL_CBCR_ADDR, m)
#define HWIO_GCC_VS_CTRL_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_VS_CTRL_CBCR_ADDR,v)
#define HWIO_GCC_VS_CTRL_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VS_CTRL_CBCR_ADDR,m,v,HWIO_GCC_VS_CTRL_CBCR_IN)
#define HWIO_GCC_VS_CTRL_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_VS_CTRL_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_VS_CTRL_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_VS_CTRL_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_VS_CTRL_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_VS_CTRL_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007a014)
#define HWIO_GCC_VS_CTRL_AHB_CBCR_RMSK                                                             0x80100007
#define HWIO_GCC_VS_CTRL_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR)
#define HWIO_GCC_VS_CTRL_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR, m)
#define HWIO_GCC_VS_CTRL_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR,v)
#define HWIO_GCC_VS_CTRL_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR,m,v,HWIO_GCC_VS_CTRL_AHB_CBCR_IN)
#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_VS_CTRL_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_VS_CTRL_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_VS_CTRL_AHB_CBCR_HW_CTL_BMSK                                                             0x2
#define HWIO_GCC_VS_CTRL_AHB_CBCR_HW_CTL_SHFT                                                             0x1
#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_VS_CTRL_AHB_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_VSENSOR_CMD_RCGR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007a018)
#define HWIO_GCC_VSENSOR_CMD_RCGR_RMSK                                                             0x80000013
#define HWIO_GCC_VSENSOR_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_VSENSOR_CMD_RCGR_ADDR)
#define HWIO_GCC_VSENSOR_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_VSENSOR_CMD_RCGR_ADDR, m)
#define HWIO_GCC_VSENSOR_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_VSENSOR_CMD_RCGR_ADDR,v)
#define HWIO_GCC_VSENSOR_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VSENSOR_CMD_RCGR_ADDR,m,v,HWIO_GCC_VSENSOR_CMD_RCGR_IN)
#define HWIO_GCC_VSENSOR_CMD_RCGR_ROOT_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_VSENSOR_CMD_RCGR_ROOT_OFF_SHFT                                                          0x1f
#define HWIO_GCC_VSENSOR_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                    0x10
#define HWIO_GCC_VSENSOR_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                     0x4
#define HWIO_GCC_VSENSOR_CMD_RCGR_ROOT_EN_BMSK                                                            0x2
#define HWIO_GCC_VSENSOR_CMD_RCGR_ROOT_EN_SHFT                                                            0x1
#define HWIO_GCC_VSENSOR_CMD_RCGR_UPDATE_BMSK                                                             0x1
#define HWIO_GCC_VSENSOR_CMD_RCGR_UPDATE_SHFT                                                             0x0

#define HWIO_GCC_VSENSOR_CFG_RCGR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007a01c)
#define HWIO_GCC_VSENSOR_CFG_RCGR_RMSK                                                               0x11071f
#define HWIO_GCC_VSENSOR_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_VSENSOR_CFG_RCGR_ADDR)
#define HWIO_GCC_VSENSOR_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_VSENSOR_CFG_RCGR_ADDR, m)
#define HWIO_GCC_VSENSOR_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_VSENSOR_CFG_RCGR_ADDR,v)
#define HWIO_GCC_VSENSOR_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VSENSOR_CFG_RCGR_ADDR,m,v,HWIO_GCC_VSENSOR_CFG_RCGR_IN)
#define HWIO_GCC_VSENSOR_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                0x100000
#define HWIO_GCC_VSENSOR_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                    0x14
#define HWIO_GCC_VSENSOR_CFG_RCGR_RCGLITE_DISABLE_BMSK                                                0x10000
#define HWIO_GCC_VSENSOR_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                   0x10
#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_BMSK                                                          0x700
#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_SEL_SHFT                                                            0x8
#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_BMSK                                                           0x1f
#define HWIO_GCC_VSENSOR_CFG_RCGR_SRC_DIV_SHFT                                                            0x0

#define HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007a030)
#define HWIO_GCC_VS_CTRL_CMD_RCGR_RMSK                                                             0x80000013
#define HWIO_GCC_VS_CTRL_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR)
#define HWIO_GCC_VS_CTRL_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR, m)
#define HWIO_GCC_VS_CTRL_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR,v)
#define HWIO_GCC_VS_CTRL_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR,m,v,HWIO_GCC_VS_CTRL_CMD_RCGR_IN)
#define HWIO_GCC_VS_CTRL_CMD_RCGR_ROOT_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_VS_CTRL_CMD_RCGR_ROOT_OFF_SHFT                                                          0x1f
#define HWIO_GCC_VS_CTRL_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                    0x10
#define HWIO_GCC_VS_CTRL_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                     0x4
#define HWIO_GCC_VS_CTRL_CMD_RCGR_ROOT_EN_BMSK                                                            0x2
#define HWIO_GCC_VS_CTRL_CMD_RCGR_ROOT_EN_SHFT                                                            0x1
#define HWIO_GCC_VS_CTRL_CMD_RCGR_UPDATE_BMSK                                                             0x1
#define HWIO_GCC_VS_CTRL_CMD_RCGR_UPDATE_SHFT                                                             0x0

#define HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007a034)
#define HWIO_GCC_VS_CTRL_CFG_RCGR_RMSK                                                               0x11071f
#define HWIO_GCC_VS_CTRL_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR)
#define HWIO_GCC_VS_CTRL_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR, m)
#define HWIO_GCC_VS_CTRL_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR,v)
#define HWIO_GCC_VS_CTRL_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR,m,v,HWIO_GCC_VS_CTRL_CFG_RCGR_IN)
#define HWIO_GCC_VS_CTRL_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                0x100000
#define HWIO_GCC_VS_CTRL_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                    0x14
#define HWIO_GCC_VS_CTRL_CFG_RCGR_RCGLITE_DISABLE_BMSK                                                0x10000
#define HWIO_GCC_VS_CTRL_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                   0x10
#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_BMSK                                                          0x700
#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_SEL_SHFT                                                            0x8
#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_BMSK                                                           0x1f
#define HWIO_GCC_VS_CTRL_CFG_RCGR_SRC_DIV_SHFT                                                            0x0

#define HWIO_GCC_MSS_VS_CBCR_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0007a048)
#define HWIO_GCC_MSS_VS_CBCR_RMSK                                                                  0x80000005
#define HWIO_GCC_MSS_VS_CBCR_IN          \
        in_dword(HWIO_GCC_MSS_VS_CBCR_ADDR)
#define HWIO_GCC_MSS_VS_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VS_CBCR_ADDR, m)
#define HWIO_GCC_MSS_VS_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VS_CBCR_ADDR,v)
#define HWIO_GCC_MSS_VS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VS_CBCR_ADDR,m,v,HWIO_GCC_MSS_VS_CBCR_IN)
#define HWIO_GCC_MSS_VS_CBCR_CLK_OFF_BMSK                                                          0x80000000
#define HWIO_GCC_MSS_VS_CBCR_CLK_OFF_SHFT                                                                0x1f
#define HWIO_GCC_MSS_VS_CBCR_CLK_ARES_BMSK                                                                0x4
#define HWIO_GCC_MSS_VS_CBCR_CLK_ARES_SHFT                                                                0x2
#define HWIO_GCC_MSS_VS_CBCR_CLK_ENABLE_BMSK                                                              0x1
#define HWIO_GCC_MSS_VS_CBCR_CLK_ENABLE_SHFT                                                              0x0

#define HWIO_GCC_GPU_VS_CBCR_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0007a04c)
#define HWIO_GCC_GPU_VS_CBCR_RMSK                                                                  0x80000005
#define HWIO_GCC_GPU_VS_CBCR_IN          \
        in_dword(HWIO_GCC_GPU_VS_CBCR_ADDR)
#define HWIO_GCC_GPU_VS_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPU_VS_CBCR_ADDR, m)
#define HWIO_GCC_GPU_VS_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_GPU_VS_CBCR_ADDR,v)
#define HWIO_GCC_GPU_VS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPU_VS_CBCR_ADDR,m,v,HWIO_GCC_GPU_VS_CBCR_IN)
#define HWIO_GCC_GPU_VS_CBCR_CLK_OFF_BMSK                                                          0x80000000
#define HWIO_GCC_GPU_VS_CBCR_CLK_OFF_SHFT                                                                0x1f
#define HWIO_GCC_GPU_VS_CBCR_CLK_ARES_BMSK                                                                0x4
#define HWIO_GCC_GPU_VS_CBCR_CLK_ARES_SHFT                                                                0x2
#define HWIO_GCC_GPU_VS_CBCR_CLK_ENABLE_BMSK                                                              0x1
#define HWIO_GCC_GPU_VS_CBCR_CLK_ENABLE_SHFT                                                              0x0

#define HWIO_GCC_APC_VS_CBCR_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0007a050)
#define HWIO_GCC_APC_VS_CBCR_RMSK                                                                  0x80000005
#define HWIO_GCC_APC_VS_CBCR_IN          \
        in_dword(HWIO_GCC_APC_VS_CBCR_ADDR)
#define HWIO_GCC_APC_VS_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_APC_VS_CBCR_ADDR, m)
#define HWIO_GCC_APC_VS_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_APC_VS_CBCR_ADDR,v)
#define HWIO_GCC_APC_VS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APC_VS_CBCR_ADDR,m,v,HWIO_GCC_APC_VS_CBCR_IN)
#define HWIO_GCC_APC_VS_CBCR_CLK_OFF_BMSK                                                          0x80000000
#define HWIO_GCC_APC_VS_CBCR_CLK_OFF_SHFT                                                                0x1f
#define HWIO_GCC_APC_VS_CBCR_CLK_ARES_BMSK                                                                0x4
#define HWIO_GCC_APC_VS_CBCR_CLK_ARES_SHFT                                                                0x2
#define HWIO_GCC_APC_VS_CBCR_CLK_ENABLE_BMSK                                                              0x1
#define HWIO_GCC_APC_VS_CBCR_CLK_ENABLE_SHFT                                                              0x0

#define HWIO_GCC_VDDMMCX_VS_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0007a054)
#define HWIO_GCC_VDDMMCX_VS_CBCR_RMSK                                                              0x80000005
#define HWIO_GCC_VDDMMCX_VS_CBCR_IN          \
        in_dword(HWIO_GCC_VDDMMCX_VS_CBCR_ADDR)
#define HWIO_GCC_VDDMMCX_VS_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_VDDMMCX_VS_CBCR_ADDR, m)
#define HWIO_GCC_VDDMMCX_VS_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_VDDMMCX_VS_CBCR_ADDR,v)
#define HWIO_GCC_VDDMMCX_VS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VDDMMCX_VS_CBCR_ADDR,m,v,HWIO_GCC_VDDMMCX_VS_CBCR_IN)
#define HWIO_GCC_VDDMMCX_VS_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_VDDMMCX_VS_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_VDDMMCX_VS_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_VDDMMCX_VS_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_VDDMMCX_VS_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_VDDMMCX_VS_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_WCSS_VS_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0007a058)
#define HWIO_GCC_WCSS_VS_CBCR_RMSK                                                                 0x80000005
#define HWIO_GCC_WCSS_VS_CBCR_IN          \
        in_dword(HWIO_GCC_WCSS_VS_CBCR_ADDR)
#define HWIO_GCC_WCSS_VS_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_WCSS_VS_CBCR_ADDR, m)
#define HWIO_GCC_WCSS_VS_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_WCSS_VS_CBCR_ADDR,v)
#define HWIO_GCC_WCSS_VS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_WCSS_VS_CBCR_ADDR,m,v,HWIO_GCC_WCSS_VS_CBCR_IN)
#define HWIO_GCC_WCSS_VS_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_WCSS_VS_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_WCSS_VS_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_WCSS_VS_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_WCSS_VS_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_WCSS_VS_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_VDDMMMX_VS_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0007a05c)
#define HWIO_GCC_VDDMMMX_VS_CBCR_RMSK                                                              0x80000005
#define HWIO_GCC_VDDMMMX_VS_CBCR_IN          \
        in_dword(HWIO_GCC_VDDMMMX_VS_CBCR_ADDR)
#define HWIO_GCC_VDDMMMX_VS_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_VDDMMMX_VS_CBCR_ADDR, m)
#define HWIO_GCC_VDDMMMX_VS_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_VDDMMMX_VS_CBCR_ADDR,v)
#define HWIO_GCC_VDDMMMX_VS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VDDMMMX_VS_CBCR_ADDR,m,v,HWIO_GCC_VDDMMMX_VS_CBCR_IN)
#define HWIO_GCC_VDDMMMX_VS_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_VDDMMMX_VS_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_VDDMMMX_VS_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_VDDMMMX_VS_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_VDDMMMX_VS_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_VDDMMMX_VS_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_AGGRE_NOC_BCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00082000)
#define HWIO_GCC_AGGRE_NOC_BCR_RMSK                                                                       0x1
#define HWIO_GCC_AGGRE_NOC_BCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_BCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_BCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_BCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_BCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_BCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_BCR_IN)
#define HWIO_GCC_AGGRE_NOC_BCR_BLK_ARES_BMSK                                                              0x1
#define HWIO_GCC_AGGRE_NOC_BCR_BLK_ARES_SHFT                                                              0x0

#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00082004)
#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_RMSK                                                 0x80100005
#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_OFF_BMSK                                         0x80000000
#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_OFF_SHFT                                               0x1f
#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                               0x100000
#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                   0x14
#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_ARES_BMSK                                               0x4
#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_ARES_SHFT                                               0x2
#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_ENABLE_BMSK                                             0x1
#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_CLK_ENABLE_SHFT                                             0x0

#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00082008)
#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_RMSK                                                           0x80100005
#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_AHB_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_AHB_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_AHB_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_AHB_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_AHB_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0008200c)
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_RMSK                                                   0x80100005
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                 0x100000
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                     0x14
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_CLK_ENABLE_SHFT                                               0x0

#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00082010)
#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_RMSK                                             0x80100005
#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_ADDR)
#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_IN)
#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_OFF_BMSK                                     0x80000000
#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_OFF_SHFT                                           0x1f
#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                           0x100000
#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                               0x14
#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_ARES_BMSK                                           0x4
#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_ARES_SHFT                                           0x2
#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_ENABLE_BMSK                                         0x1
#define HWIO_GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR_CLK_ENABLE_SHFT                                         0x0

#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00082014)
#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_RMSK                                             0x80100005
#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_ADDR)
#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_IN)
#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_OFF_BMSK                                     0x80000000
#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_OFF_SHFT                                           0x1f
#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                           0x100000
#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                               0x14
#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_ARES_BMSK                                           0x4
#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_ARES_SHFT                                           0x2
#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_ENABLE_BMSK                                         0x1
#define HWIO_GCC_AGGRE_CNOC_PERIPH_SOUTH_AHB_CBCR_CLK_ENABLE_SHFT                                         0x0

#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00082018)
#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_RMSK                                                   0x80100005
#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                 0x100000
#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                     0x14
#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_CLK_ENABLE_SHFT                                               0x0

#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0008201c)
#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_RMSK                                                  0x80100005
#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                0x100000
#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                    0x14
#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_CLK_ENABLE_SHFT                                              0x0

#define HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00082020)
#define HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_RMSK                                                  0x80100005
#define HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                0x100000
#define HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                    0x14
#define HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_GCC_AGGRE_NOC_SF_SOUTH_AXI_CBCR_CLK_ENABLE_SHFT                                              0x0

#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00082024)
#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_RMSK                                                 0x80100005
#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_CLK_OFF_BMSK                                         0x80000000
#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_CLK_OFF_SHFT                                               0x1f
#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                               0x100000
#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                   0x14
#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_CLK_ARES_BMSK                                               0x4
#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_CLK_ARES_SHFT                                               0x2
#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_CLK_ENABLE_BMSK                                             0x1
#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_CLK_ENABLE_SHFT                                             0x0

#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00082028)
#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_RMSK                                                 0x80000005
#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_OFF_BMSK                                         0x80000000
#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_OFF_SHFT                                               0x1f
#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_ARES_BMSK                                               0x4
#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_ARES_SHFT                                               0x2
#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_BMSK                                             0x1
#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_CLK_ENABLE_SHFT                                             0x0

#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0008202c)
#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_RMSK                                                    0x80100005
#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                  0x100000
#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                      0x14
#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00082030)
#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_RMSK                                                      0x80100005
#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                    0x100000
#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                        0x14
#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_CLK_ENABLE_SHFT                                                  0x0

#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00082034)
#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_RMSK                                                     0x80100005
#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                   0x100000
#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                       0x14
#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00082038)
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_RMSK                                                   0x80100005
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                 0x100000
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                     0x14
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_GCC_AGGRE_NOC_COMPUTE_AXI_CBCR_CLK_ENABLE_SHFT                                               0x0

#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0008203c)
#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_RMSK                                                     0x80100005
#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                   0x100000
#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                       0x14
#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00082040)
#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_RMSK                                                     0x80100005
#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                   0x100000
#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                       0x14
#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f080)
#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_RMSK                                                     0x80000005
#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_ADDR)
#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_IN)
#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00010080)
#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_RMSK                                                      0x80000005
#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_ADDR)
#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_IN)
#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_CLK_ENABLE_SHFT                                                  0x0

#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x000770cc)
#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_RMSK                                                       0x80000007
#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_ADDR)
#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_IN)
#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_HW_CTL_BMSK                                                       0x2
#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_HW_CTL_SHFT                                                       0x1
#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000750cc)
#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_RMSK                                                      0x80000007
#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_ADDR)
#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_IN)
#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_HW_CTL_BMSK                                                      0x2
#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_HW_CTL_SHFT                                                      0x1
#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_CLK_ENABLE_SHFT                                                  0x0

#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00089164)
#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_RMSK                                                           0x80100005
#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_IPA_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_IPA_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_IPA_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_IPA_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_IPA_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00045288)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_RMSK                                               0x80100005
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                             0x100000
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                 0x14
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_CLK_ARES_BMSK                                             0x4
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_CLK_ARES_SHFT                                             0x2
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0004528c)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_RMSK                                                  0x80100005
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_ADDR)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_IN)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                0x100000
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                    0x14
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_CLK_ENABLE_SHFT                                              0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00082060)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00082064)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00082068)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0008206c)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00082070)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00082074)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00082078)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0008207c)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00082080)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00082084)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00082088)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0008208c)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00082090)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00082094)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00082098)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0008209c)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_RMSK                                                0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_SEL_BMSK                                        0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_SEL_SHFT                                          0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_BMSK                                         0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_SRC_DIV_SHFT                                          0x0

#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00082044)
#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_RMSK                                                           0x80000013
#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_CMD_RCGR_ADDR)
#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_CMD_RCGR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_CMD_RCGR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CMD_RCGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CMD_RCGR_IN)
#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_ROOT_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_ROOT_OFF_SHFT                                                        0x1f
#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                  0x10
#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                   0x4
#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_ROOT_EN_BMSK                                                          0x2
#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_ROOT_EN_SHFT                                                          0x1
#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_UPDATE_BMSK                                                           0x1
#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_UPDATE_SHFT                                                           0x0

#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00082048)
#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_RMSK                                                             0x11071f
#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_CFG_RCGR_ADDR)
#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_CFG_RCGR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_CFG_RCGR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CFG_RCGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CFG_RCGR_IN)
#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_HW_CLK_CONTROL_BMSK                                              0x100000
#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                  0x14
#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_RCGLITE_DISABLE_BMSK                                              0x10000
#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                 0x10
#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_SEL_BMSK                                                        0x700
#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_SEL_SHFT                                                          0x8
#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_BMSK                                                         0x1f
#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_SRC_DIV_SHFT                                                          0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0008218c)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00082190)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00082194)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00082198)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0008219c)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000821a0)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000821a4)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000821a8)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000821ac)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000821b0)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_RMSK                                         0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000821b4)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000821b8)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000821bc)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000821c0)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000821c4)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000821c8)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00082170)
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_RMSK                                                   0x80000013
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_ADDR)
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_IN)
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_ROOT_OFF_BMSK                                          0x80000000
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_ROOT_OFF_SHFT                                                0x1f
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                          0x10
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                           0x4
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_ROOT_EN_BMSK                                                  0x2
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_ROOT_EN_SHFT                                                  0x1
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_UPDATE_BMSK                                                   0x1
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_UPDATE_SHFT                                                   0x0

#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00082174)
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_RMSK                                                     0x11071f
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_ADDR)
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_IN)
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_HW_CLK_CONTROL_BMSK                                      0x100000
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_HW_CLK_CONTROL_SHFT                                          0x14
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_RCGLITE_DISABLE_BMSK                                      0x10000
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_RCGLITE_DISABLE_SHFT                                         0x10
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000822b8)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000822bc)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000822c0)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000822c4)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000822c8)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000822cc)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000822d0)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000822d4)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000822d8)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000822dc)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000822e0)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000822e4)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000822e8)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000822ec)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000822f0)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000822f4)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0008229c)
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_RMSK                                                  0x80000013
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ADDR)
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_IN)
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ROOT_OFF_BMSK                                         0x80000000
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ROOT_OFF_SHFT                                               0x1f
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                         0x10
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                          0x4
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ROOT_EN_BMSK                                                 0x2
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ROOT_EN_SHFT                                                 0x1
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_UPDATE_BMSK                                                  0x1
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_UPDATE_SHFT                                                  0x0

#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000822a0)
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_RMSK                                                    0x11071f
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_ADDR)
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_IN)
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_HW_CLK_CONTROL_BMSK                                     0x100000
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_HW_CLK_CONTROL_SHFT                                         0x14
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_RCGLITE_DISABLE_BMSK                                     0x10000
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_RCGLITE_DISABLE_SHFT                                        0x10
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF0_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000823e4)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF0_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF0_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF0_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF0_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF0_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF1_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000823e8)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF1_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF1_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF1_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF1_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF1_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF2_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000823ec)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF2_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF2_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF2_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF2_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF2_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF3_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000823f0)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF3_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF3_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF3_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF3_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF3_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF4_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000823f4)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF4_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF4_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF4_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF4_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF4_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF5_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000823f8)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF5_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF5_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF5_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF5_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF5_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF6_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x000823fc)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF6_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF6_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF6_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF6_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF6_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF7_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00082400)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF7_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF7_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF7_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF7_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF7_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF8_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00082404)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF8_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF8_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF8_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF8_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF8_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF9_DFSR_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00082408)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF9_DFSR_RMSK                                        0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF9_DFSR_SRC_SEL_BMSK                                0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF9_DFSR_SRC_SEL_SHFT                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF9_DFSR_SRC_DIV_BMSK                                 0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF9_DFSR_SRC_DIV_SHFT                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF10_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0008240c)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF10_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF10_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF10_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF10_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF10_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF11_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00082410)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF11_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF11_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF11_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF11_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF11_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF12_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00082414)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF12_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF12_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF12_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF12_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF12_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF13_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00082418)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF13_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF13_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF13_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF13_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF13_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF14_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0008241c)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF14_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF14_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF14_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF14_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF14_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF15_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00082420)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF15_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF15_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF15_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF15_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SOUTH_SF_PERF15_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000823c8)
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_RMSK                                                  0x80000013
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_ADDR)
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_IN)
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_ROOT_OFF_BMSK                                         0x80000000
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_ROOT_OFF_SHFT                                               0x1f
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                         0x10
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                          0x4
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_ROOT_EN_BMSK                                                 0x2
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_ROOT_EN_SHFT                                                 0x1
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_UPDATE_BMSK                                                  0x1
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CMD_RCGR_UPDATE_SHFT                                                  0x0

#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x000823cc)
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_RMSK                                                    0x11071f
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_ADDR)
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_IN)
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_HW_CLK_CONTROL_BMSK                                     0x100000
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_HW_CLK_CONTROL_SHFT                                         0x14
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_RCGLITE_DISABLE_BMSK                                     0x10000
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_RCGLITE_DISABLE_SHFT                                        0x10
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_CFG_RCGR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x000824f4)
#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_RMSK                                                             0x1
#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                                  0x1
#define HWIO_GCC_AGGRE_NOC_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                                  0x0

#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x000824f8)
#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_RMSK                                                        0x1
#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                             0x1
#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                             0x0

#define HWIO_GCC_AGGRE_NOC_COMPUTE_DCD_CDIV_DCDR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x000824fc)
#define HWIO_GCC_AGGRE_NOC_COMPUTE_DCD_CDIV_DCDR_RMSK                                                     0x1
#define HWIO_GCC_AGGRE_NOC_COMPUTE_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_COMPUTE_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_AGGRE_NOC_COMPUTE_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_COMPUTE_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_COMPUTE_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_COMPUTE_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_COMPUTE_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_COMPUTE_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_COMPUTE_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_AGGRE_NOC_COMPUTE_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                          0x1
#define HWIO_GCC_AGGRE_NOC_COMPUTE_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                          0x0

#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00082500)
#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_RMSK                                                       0x1
#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                            0x1
#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                            0x0

#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00082504)
#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_RMSK                                                       0x1
#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                            0x1
#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                            0x0

#define HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00082508)
#define HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_RMSK                                                       0x1
#define HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                            0x1
#define HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                            0x0

#define HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0008250c)
#define HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_RMSK                                                          0x1
#define HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_ADDR)
#define HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_IN)
#define HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_DCD_ENABLE_BMSK                                               0x1
#define HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_DCD_ENABLE_SHFT                                               0x0

#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00082510)
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_RMSK                                                         0x1
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_ADDR)
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_IN)
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_DCD_ENABLE_BMSK                                              0x1
#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_DCD_ENABLE_SHFT                                              0x0

#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_DCD_DCDR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00082514)
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_DCD_DCDR_RMSK                                                         0x1
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_DCD_DCDR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_SOUTH_SF_DCD_DCDR_ADDR)
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_DCD_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_SOUTH_SF_DCD_DCDR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_DCD_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_SOUTH_SF_DCD_DCDR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_DCD_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SOUTH_SF_DCD_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SOUTH_SF_DCD_DCDR_IN)
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_DCD_DCDR_DCD_ENABLE_BMSK                                              0x1
#define HWIO_GCC_AGGRE_NOC_SOUTH_SF_DCD_DCDR_DCD_ENABLE_SHFT                                              0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF0_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00082534)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF0_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF0_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF0_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF0_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF0_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF1_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00082538)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF1_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF1_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF1_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF1_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF1_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF2_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0008253c)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF2_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF2_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF2_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF2_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF2_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF3_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00082540)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF3_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF3_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF3_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF3_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF3_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF4_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00082544)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF4_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF4_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF4_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF4_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF4_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF5_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00082548)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF5_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF5_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF5_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF5_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF5_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF6_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0008254c)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF6_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF6_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF6_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF6_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF6_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF7_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00082550)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF7_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF7_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF7_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF7_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF7_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF8_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00082554)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF8_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF8_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF8_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF8_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF8_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF9_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00082558)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF9_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF9_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF9_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF9_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF9_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF10_DFSR_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0008255c)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF10_DFSR_RMSK                                             0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF10_DFSR_SRC_SEL_BMSK                                     0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF10_DFSR_SRC_SEL_SHFT                                       0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF10_DFSR_SRC_DIV_BMSK                                      0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF10_DFSR_SRC_DIV_SHFT                                       0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF11_DFSR_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00082560)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF11_DFSR_RMSK                                             0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF11_DFSR_SRC_SEL_BMSK                                     0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF11_DFSR_SRC_SEL_SHFT                                       0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF11_DFSR_SRC_DIV_BMSK                                      0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF11_DFSR_SRC_DIV_SHFT                                       0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF12_DFSR_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00082564)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF12_DFSR_RMSK                                             0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF12_DFSR_SRC_SEL_BMSK                                     0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF12_DFSR_SRC_SEL_SHFT                                       0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF12_DFSR_SRC_DIV_BMSK                                      0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF12_DFSR_SRC_DIV_SHFT                                       0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF13_DFSR_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00082568)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF13_DFSR_RMSK                                             0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF13_DFSR_SRC_SEL_BMSK                                     0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF13_DFSR_SRC_SEL_SHFT                                       0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF13_DFSR_SRC_DIV_BMSK                                      0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF13_DFSR_SRC_DIV_SHFT                                       0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF14_DFSR_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0008256c)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF14_DFSR_RMSK                                             0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF14_DFSR_SRC_SEL_BMSK                                     0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF14_DFSR_SRC_SEL_SHFT                                       0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF14_DFSR_SRC_DIV_BMSK                                      0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF14_DFSR_SRC_DIV_SHFT                                       0x0

#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF15_DFSR_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00082570)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF15_DFSR_RMSK                                             0x71f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF15_DFSR_SRC_SEL_BMSK                                     0x700
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF15_DFSR_SRC_SEL_SHFT                                       0x8
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF15_DFSR_SRC_DIV_BMSK                                      0x1f
#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_SF_PERF15_DFSR_SRC_DIV_SHFT                                       0x0

#define HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00082518)
#define HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_RMSK                                                        0x80000013
#define HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_ADDR)
#define HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_IN)
#define HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_ROOT_OFF_BMSK                                               0x80000000
#define HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_ROOT_OFF_SHFT                                                     0x1f
#define HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                               0x10
#define HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                0x4
#define HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_ROOT_EN_BMSK                                                       0x2
#define HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_ROOT_EN_SHFT                                                       0x1
#define HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_UPDATE_BMSK                                                        0x1
#define HWIO_GCC_AGGRE_NOC_SF_CMD_RCGR_UPDATE_SHFT                                                        0x0

#define HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0008251c)
#define HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_RMSK                                                          0x11071f
#define HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_ADDR)
#define HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_IN)
#define HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_HW_CLK_CONTROL_BMSK                                           0x100000
#define HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_HW_CLK_CONTROL_SHFT                                               0x14
#define HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_RCGLITE_DISABLE_BMSK                                           0x10000
#define HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_RCGLITE_DISABLE_SHFT                                              0x10
#define HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_SRC_SEL_BMSK                                                     0x700
#define HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_SRC_SEL_SHFT                                                       0x8
#define HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_SRC_DIV_BMSK                                                      0x1f
#define HWIO_GCC_AGGRE_NOC_SF_CFG_RCGR_SRC_DIV_SHFT                                                       0x0

#define HWIO_GCC_AGGRE_NOC_SF_DCD_CDIV_DCDR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00082644)
#define HWIO_GCC_AGGRE_NOC_SF_DCD_CDIV_DCDR_RMSK                                                          0x1
#define HWIO_GCC_AGGRE_NOC_SF_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_SF_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_AGGRE_NOC_SF_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_SF_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_SF_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_SF_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_SF_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_SF_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_SF_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_AGGRE_NOC_SF_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                               0x1
#define HWIO_GCC_AGGRE_NOC_SF_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                               0x0

#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00082664)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00082668)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0008266c)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00082670)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00082674)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00082678)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0008267c)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00082680)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00082684)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00082688)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_RMSK                                       0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_SRC_SEL_BMSK                               0x700
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_SRC_SEL_SHFT                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_SRC_DIV_BMSK                                0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_SRC_DIV_SHFT                                 0x0

#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_ADDR                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0008268c)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_RMSK                                      0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_SRC_SEL_BMSK                              0x700
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_SRC_SEL_SHFT                                0x8
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_SRC_DIV_BMSK                               0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_SRC_DIV_SHFT                                0x0

#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_ADDR                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00082690)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_RMSK                                      0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_SRC_SEL_BMSK                              0x700
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_SRC_SEL_SHFT                                0x8
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_SRC_DIV_BMSK                               0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_SRC_DIV_SHFT                                0x0

#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_ADDR                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00082694)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_RMSK                                      0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_SRC_SEL_BMSK                              0x700
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_SRC_SEL_SHFT                                0x8
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_SRC_DIV_BMSK                               0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_SRC_DIV_SHFT                                0x0

#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_ADDR                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00082698)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_RMSK                                      0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_SRC_SEL_BMSK                              0x700
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_SRC_SEL_SHFT                                0x8
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_SRC_DIV_BMSK                               0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_SRC_DIV_SHFT                                0x0

#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_ADDR                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0008269c)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_RMSK                                      0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_SRC_SEL_BMSK                              0x700
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_SRC_SEL_SHFT                                0x8
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_SRC_DIV_BMSK                               0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_SRC_DIV_SHFT                                0x0

#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_ADDR                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x000826a0)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_RMSK                                      0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_SRC_SEL_BMSK                              0x700
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_SRC_SEL_SHFT                                0x8
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_SRC_DIV_BMSK                               0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_SRC_DIV_SHFT                                0x0

#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00082648)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_RMSK                                                  0x80000013
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_ADDR)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_IN)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_ROOT_OFF_BMSK                                         0x80000000
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_ROOT_OFF_SHFT                                               0x1f
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                         0x10
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                          0x4
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_ROOT_EN_BMSK                                                 0x2
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_ROOT_EN_SHFT                                                 0x1
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_UPDATE_BMSK                                                  0x1
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_UPDATE_SHFT                                                  0x0

#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0008264c)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_RMSK                                                    0x11071f
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_ADDR)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_IN)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_HW_CLK_CONTROL_BMSK                                     0x100000
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_HW_CLK_CONTROL_SHFT                                         0x14
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_RCGLITE_DISABLE_BMSK                                     0x10000
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_RCGLITE_DISABLE_SHFT                                        0x10
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00082774)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_RMSK                                                    0x1
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                         0x1
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                         0x0

#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00082778)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_RMSK                                                       0x3
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_IN          \
        in_dword(HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_ADDR)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_ADDR, m)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_ADDR,v)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_ADDR,m,v,HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_IN)
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_CLK_DIV_BMSK                                               0x3
#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_CLK_DIV_SHFT                                               0x0

#define HWIO_GCC_DCC_BCR_ADDR                                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00084000)
#define HWIO_GCC_DCC_BCR_RMSK                                                                             0x1
#define HWIO_GCC_DCC_BCR_IN          \
        in_dword(HWIO_GCC_DCC_BCR_ADDR)
#define HWIO_GCC_DCC_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DCC_BCR_ADDR, m)
#define HWIO_GCC_DCC_BCR_OUT(v)      \
        out_dword(HWIO_GCC_DCC_BCR_ADDR,v)
#define HWIO_GCC_DCC_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DCC_BCR_ADDR,m,v,HWIO_GCC_DCC_BCR_IN)
#define HWIO_GCC_DCC_BCR_BLK_ARES_BMSK                                                                    0x1
#define HWIO_GCC_DCC_BCR_BLK_ARES_SHFT                                                                    0x0

#define HWIO_GCC_DCC_AHB_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00084004)
#define HWIO_GCC_DCC_AHB_CBCR_RMSK                                                                 0x80107ff5
#define HWIO_GCC_DCC_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_DCC_AHB_CBCR_ADDR)
#define HWIO_GCC_DCC_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DCC_AHB_CBCR_ADDR, m)
#define HWIO_GCC_DCC_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DCC_AHB_CBCR_ADDR,v)
#define HWIO_GCC_DCC_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DCC_AHB_CBCR_ADDR,m,v,HWIO_GCC_DCC_AHB_CBCR_IN)
#define HWIO_GCC_DCC_AHB_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_DCC_AHB_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_DCC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                               0x100000
#define HWIO_GCC_DCC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                   0x14
#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_CORE_ON_BMSK                                                   0x4000
#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_CORE_ON_SHFT                                                      0xe
#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                                 0x2000
#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                    0xd
#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                                0x1000
#define HWIO_GCC_DCC_AHB_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                                   0xc
#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_BMSK                                                               0xf00
#define HWIO_GCC_DCC_AHB_CBCR_WAKEUP_SHFT                                                                 0x8
#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_BMSK                                                                 0xf0
#define HWIO_GCC_DCC_AHB_CBCR_SLEEP_SHFT                                                                  0x4
#define HWIO_GCC_DCC_AHB_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_DCC_AHB_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_DCC_AHB_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_DCC_AHB_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_IPA_BCR_ADDR                                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00089000)
#define HWIO_GCC_IPA_BCR_RMSK                                                                             0x1
#define HWIO_GCC_IPA_BCR_IN          \
        in_dword(HWIO_GCC_IPA_BCR_ADDR)
#define HWIO_GCC_IPA_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPA_BCR_ADDR, m)
#define HWIO_GCC_IPA_BCR_OUT(v)      \
        out_dword(HWIO_GCC_IPA_BCR_ADDR,v)
#define HWIO_GCC_IPA_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPA_BCR_ADDR,m,v,HWIO_GCC_IPA_BCR_IN)
#define HWIO_GCC_IPA_BCR_BLK_ARES_BMSK                                                                    0x1
#define HWIO_GCC_IPA_BCR_BLK_ARES_SHFT                                                                    0x0

#define HWIO_GCC_IPA_GDSCR_ADDR                                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00089004)
#define HWIO_GCC_IPA_GDSCR_RMSK                                                                    0xf8ffffff
#define HWIO_GCC_IPA_GDSCR_IN          \
        in_dword(HWIO_GCC_IPA_GDSCR_ADDR)
#define HWIO_GCC_IPA_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPA_GDSCR_ADDR, m)
#define HWIO_GCC_IPA_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_IPA_GDSCR_ADDR,v)
#define HWIO_GCC_IPA_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPA_GDSCR_ADDR,m,v,HWIO_GCC_IPA_GDSCR_IN)
#define HWIO_GCC_IPA_GDSCR_PWR_ON_BMSK                                                             0x80000000
#define HWIO_GCC_IPA_GDSCR_PWR_ON_SHFT                                                                   0x1f
#define HWIO_GCC_IPA_GDSCR_GDSC_STATE_BMSK                                                         0x78000000
#define HWIO_GCC_IPA_GDSCR_GDSC_STATE_SHFT                                                               0x1b
#define HWIO_GCC_IPA_GDSCR_EN_REST_WAIT_BMSK                                                         0xf00000
#define HWIO_GCC_IPA_GDSCR_EN_REST_WAIT_SHFT                                                             0x14
#define HWIO_GCC_IPA_GDSCR_EN_FEW_WAIT_BMSK                                                           0xf0000
#define HWIO_GCC_IPA_GDSCR_EN_FEW_WAIT_SHFT                                                              0x10
#define HWIO_GCC_IPA_GDSCR_CLK_DIS_WAIT_BMSK                                                           0xf000
#define HWIO_GCC_IPA_GDSCR_CLK_DIS_WAIT_SHFT                                                              0xc
#define HWIO_GCC_IPA_GDSCR_RETAIN_FF_ENABLE_BMSK                                                        0x800
#define HWIO_GCC_IPA_GDSCR_RETAIN_FF_ENABLE_SHFT                                                          0xb
#define HWIO_GCC_IPA_GDSCR_RESTORE_BMSK                                                                 0x400
#define HWIO_GCC_IPA_GDSCR_RESTORE_SHFT                                                                   0xa
#define HWIO_GCC_IPA_GDSCR_SAVE_BMSK                                                                    0x200
#define HWIO_GCC_IPA_GDSCR_SAVE_SHFT                                                                      0x9
#define HWIO_GCC_IPA_GDSCR_RETAIN_BMSK                                                                  0x100
#define HWIO_GCC_IPA_GDSCR_RETAIN_SHFT                                                                    0x8
#define HWIO_GCC_IPA_GDSCR_EN_REST_BMSK                                                                  0x80
#define HWIO_GCC_IPA_GDSCR_EN_REST_SHFT                                                                   0x7
#define HWIO_GCC_IPA_GDSCR_EN_FEW_BMSK                                                                   0x40
#define HWIO_GCC_IPA_GDSCR_EN_FEW_SHFT                                                                    0x6
#define HWIO_GCC_IPA_GDSCR_CLAMP_IO_BMSK                                                                 0x20
#define HWIO_GCC_IPA_GDSCR_CLAMP_IO_SHFT                                                                  0x5
#define HWIO_GCC_IPA_GDSCR_CLK_DISABLE_BMSK                                                              0x10
#define HWIO_GCC_IPA_GDSCR_CLK_DISABLE_SHFT                                                               0x4
#define HWIO_GCC_IPA_GDSCR_PD_ARES_BMSK                                                                   0x8
#define HWIO_GCC_IPA_GDSCR_PD_ARES_SHFT                                                                   0x3
#define HWIO_GCC_IPA_GDSCR_SW_OVERRIDE_BMSK                                                               0x4
#define HWIO_GCC_IPA_GDSCR_SW_OVERRIDE_SHFT                                                               0x2
#define HWIO_GCC_IPA_GDSCR_HW_CONTROL_BMSK                                                                0x2
#define HWIO_GCC_IPA_GDSCR_HW_CONTROL_SHFT                                                                0x1
#define HWIO_GCC_IPA_GDSCR_SW_COLLAPSE_BMSK                                                               0x1
#define HWIO_GCC_IPA_GDSCR_SW_COLLAPSE_SHFT                                                               0x0

#define HWIO_GCC_IPA_CFG_GDSCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00089008)
#define HWIO_GCC_IPA_CFG_GDSCR_RMSK                                                                0xffffffff
#define HWIO_GCC_IPA_CFG_GDSCR_IN          \
        in_dword(HWIO_GCC_IPA_CFG_GDSCR_ADDR)
#define HWIO_GCC_IPA_CFG_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPA_CFG_GDSCR_ADDR, m)
#define HWIO_GCC_IPA_CFG_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_IPA_CFG_GDSCR_ADDR,v)
#define HWIO_GCC_IPA_CFG_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPA_CFG_GDSCR_ADDR,m,v,HWIO_GCC_IPA_CFG_GDSCR_IN)
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_SPARE_CTRL_IN_BMSK                                             0xf0000000
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_SPARE_CTRL_IN_SHFT                                                   0x1c
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK                                             0xc000000
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT                                                  0x1a
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK                                              0x2000000
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT                                                   0x19
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PWR_UP_START_BMSK                                               0x1000000
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PWR_UP_START_SHFT                                                    0x18
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK                                        0xf00000
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT                                            0x14
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                                           0x80000
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                                              0x13
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK                                               0x40000
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT                                                  0x12
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK                                               0x20000
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT                                                  0x11
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK                                            0x10000
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT                                               0x10
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                                           0x8000
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                                              0xf
#define HWIO_GCC_IPA_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                                          0x7800
#define HWIO_GCC_IPA_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                                             0xb
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK                                                  0x400
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT                                                    0xa
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                                           0x200
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                                             0x9
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                                           0x100
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                                             0x8
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                                               0x80
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                                                0x7
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                                      0x60
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                                       0x5
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                                                0x10
#define HWIO_GCC_IPA_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                                                 0x4
#define HWIO_GCC_IPA_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                          0x8
#define HWIO_GCC_IPA_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                          0x3
#define HWIO_GCC_IPA_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                                        0x4
#define HWIO_GCC_IPA_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                                        0x2
#define HWIO_GCC_IPA_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                            0x2
#define HWIO_GCC_IPA_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                            0x1
#define HWIO_GCC_IPA_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                                         0x1
#define HWIO_GCC_IPA_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                                         0x0

#define HWIO_GCC_IPA_CFG2_GDSCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0008900c)
#define HWIO_GCC_IPA_CFG2_GDSCR_RMSK                                                                  0x1ffff
#define HWIO_GCC_IPA_CFG2_GDSCR_IN          \
        in_dword(HWIO_GCC_IPA_CFG2_GDSCR_ADDR)
#define HWIO_GCC_IPA_CFG2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPA_CFG2_GDSCR_ADDR, m)
#define HWIO_GCC_IPA_CFG2_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_IPA_CFG2_GDSCR_ADDR,v)
#define HWIO_GCC_IPA_CFG2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPA_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_IPA_CFG2_GDSCR_IN)
#define HWIO_GCC_IPA_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK                                                0x10000
#define HWIO_GCC_IPA_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT                                                   0x10
#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK                                                    0xf000
#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT                                                       0xc
#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                                             0xf00
#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                                               0x8
#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                                                0xf0
#define HWIO_GCC_IPA_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                                                 0x4
#define HWIO_GCC_IPA_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                                                  0xf
#define HWIO_GCC_IPA_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                                                  0x0

#define HWIO_GCC_IPA_2X_CBCR_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00089010)
#define HWIO_GCC_IPA_2X_CBCR_RMSK                                                                  0x80107ff5
#define HWIO_GCC_IPA_2X_CBCR_IN          \
        in_dword(HWIO_GCC_IPA_2X_CBCR_ADDR)
#define HWIO_GCC_IPA_2X_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPA_2X_CBCR_ADDR, m)
#define HWIO_GCC_IPA_2X_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_IPA_2X_CBCR_ADDR,v)
#define HWIO_GCC_IPA_2X_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPA_2X_CBCR_ADDR,m,v,HWIO_GCC_IPA_2X_CBCR_IN)
#define HWIO_GCC_IPA_2X_CBCR_CLK_OFF_BMSK                                                          0x80000000
#define HWIO_GCC_IPA_2X_CBCR_CLK_OFF_SHFT                                                                0x1f
#define HWIO_GCC_IPA_2X_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                                0x100000
#define HWIO_GCC_IPA_2X_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                    0x14
#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_CORE_ON_BMSK                                                    0x4000
#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_CORE_ON_SHFT                                                       0xe
#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                                  0x2000
#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                     0xd
#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                                 0x1000
#define HWIO_GCC_IPA_2X_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                                    0xc
#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_BMSK                                                                0xf00
#define HWIO_GCC_IPA_2X_CBCR_WAKEUP_SHFT                                                                  0x8
#define HWIO_GCC_IPA_2X_CBCR_SLEEP_BMSK                                                                  0xf0
#define HWIO_GCC_IPA_2X_CBCR_SLEEP_SHFT                                                                   0x4
#define HWIO_GCC_IPA_2X_CBCR_CLK_ARES_BMSK                                                                0x4
#define HWIO_GCC_IPA_2X_CBCR_CLK_ARES_SHFT                                                                0x2
#define HWIO_GCC_IPA_2X_CBCR_CLK_ENABLE_BMSK                                                              0x1
#define HWIO_GCC_IPA_2X_CBCR_CLK_ENABLE_SHFT                                                              0x0

#define HWIO_GCC_IPA_2X_SREGR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00089014)
#define HWIO_GCC_IPA_2X_SREGR_RMSK                                                                 0xfffff37e
#define HWIO_GCC_IPA_2X_SREGR_IN          \
        in_dword(HWIO_GCC_IPA_2X_SREGR_ADDR)
#define HWIO_GCC_IPA_2X_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPA_2X_SREGR_ADDR, m)
#define HWIO_GCC_IPA_2X_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_IPA_2X_SREGR_ADDR,v)
#define HWIO_GCC_IPA_2X_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPA_2X_SREGR_ADDR,m,v,HWIO_GCC_IPA_2X_SREGR_IN)
#define HWIO_GCC_IPA_2X_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                                       0xff000000
#define HWIO_GCC_IPA_2X_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                             0x18
#define HWIO_GCC_IPA_2X_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                          0xff0000
#define HWIO_GCC_IPA_2X_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                              0x10
#define HWIO_GCC_IPA_2X_SREGR_RESERVE_BITS15_13_BMSK                                                   0xe000
#define HWIO_GCC_IPA_2X_SREGR_RESERVE_BITS15_13_SHFT                                                      0xd
#define HWIO_GCC_IPA_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                         0x1000
#define HWIO_GCC_IPA_2X_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                            0xc
#define HWIO_GCC_IPA_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                             0x300
#define HWIO_GCC_IPA_2X_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                               0x8
#define HWIO_GCC_IPA_2X_SREGR_FORCE_CLK_ON_BMSK                                                          0x40
#define HWIO_GCC_IPA_2X_SREGR_FORCE_CLK_ON_SHFT                                                           0x6
#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SEL_SLP_STG_BMSK                                                    0x20
#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SEL_SLP_STG_SHFT                                                     0x5
#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SLP_STG_BMSK                                                        0x10
#define HWIO_GCC_IPA_2X_SREGR_SW_RST_SLP_STG_SHFT                                                         0x4
#define HWIO_GCC_IPA_2X_SREGR_SW_CTRL_PWR_DOWN_BMSK                                                       0x8
#define HWIO_GCC_IPA_2X_SREGR_SW_CTRL_PWR_DOWN_SHFT                                                       0x3
#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                                  0x4
#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                                  0x2
#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SLP_STG_BMSK                                                      0x2
#define HWIO_GCC_IPA_2X_SREGR_SW_CLK_EN_SLP_STG_SHFT                                                      0x1

#define HWIO_GCC_IPA_CBCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00089018)
#define HWIO_GCC_IPA_CBCR_RMSK                                                                     0x80107ff5
#define HWIO_GCC_IPA_CBCR_IN          \
        in_dword(HWIO_GCC_IPA_CBCR_ADDR)
#define HWIO_GCC_IPA_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPA_CBCR_ADDR, m)
#define HWIO_GCC_IPA_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_IPA_CBCR_ADDR,v)
#define HWIO_GCC_IPA_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPA_CBCR_ADDR,m,v,HWIO_GCC_IPA_CBCR_IN)
#define HWIO_GCC_IPA_CBCR_CLK_OFF_BMSK                                                             0x80000000
#define HWIO_GCC_IPA_CBCR_CLK_OFF_SHFT                                                                   0x1f
#define HWIO_GCC_IPA_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                                   0x100000
#define HWIO_GCC_IPA_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                       0x14
#define HWIO_GCC_IPA_CBCR_FORCE_MEM_CORE_ON_BMSK                                                       0x4000
#define HWIO_GCC_IPA_CBCR_FORCE_MEM_CORE_ON_SHFT                                                          0xe
#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                                     0x2000
#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                        0xd
#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                                    0x1000
#define HWIO_GCC_IPA_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                                       0xc
#define HWIO_GCC_IPA_CBCR_WAKEUP_BMSK                                                                   0xf00
#define HWIO_GCC_IPA_CBCR_WAKEUP_SHFT                                                                     0x8
#define HWIO_GCC_IPA_CBCR_SLEEP_BMSK                                                                     0xf0
#define HWIO_GCC_IPA_CBCR_SLEEP_SHFT                                                                      0x4
#define HWIO_GCC_IPA_CBCR_CLK_ARES_BMSK                                                                   0x4
#define HWIO_GCC_IPA_CBCR_CLK_ARES_SHFT                                                                   0x2
#define HWIO_GCC_IPA_CBCR_CLK_ENABLE_BMSK                                                                 0x1
#define HWIO_GCC_IPA_CBCR_CLK_ENABLE_SHFT                                                                 0x0

#define HWIO_GCC_IPA_SREGR_ADDR                                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0008901c)
#define HWIO_GCC_IPA_SREGR_RMSK                                                                    0xfffff37e
#define HWIO_GCC_IPA_SREGR_IN          \
        in_dword(HWIO_GCC_IPA_SREGR_ADDR)
#define HWIO_GCC_IPA_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPA_SREGR_ADDR, m)
#define HWIO_GCC_IPA_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_IPA_SREGR_ADDR,v)
#define HWIO_GCC_IPA_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPA_SREGR_ADDR,m,v,HWIO_GCC_IPA_SREGR_IN)
#define HWIO_GCC_IPA_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                                          0xff000000
#define HWIO_GCC_IPA_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                                0x18
#define HWIO_GCC_IPA_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                             0xff0000
#define HWIO_GCC_IPA_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                                 0x10
#define HWIO_GCC_IPA_SREGR_RESERVE_BITS15_13_BMSK                                                      0xe000
#define HWIO_GCC_IPA_SREGR_RESERVE_BITS15_13_SHFT                                                         0xd
#define HWIO_GCC_IPA_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                            0x1000
#define HWIO_GCC_IPA_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                               0xc
#define HWIO_GCC_IPA_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                                0x300
#define HWIO_GCC_IPA_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                                  0x8
#define HWIO_GCC_IPA_SREGR_FORCE_CLK_ON_BMSK                                                             0x40
#define HWIO_GCC_IPA_SREGR_FORCE_CLK_ON_SHFT                                                              0x6
#define HWIO_GCC_IPA_SREGR_SW_RST_SEL_SLP_STG_BMSK                                                       0x20
#define HWIO_GCC_IPA_SREGR_SW_RST_SEL_SLP_STG_SHFT                                                        0x5
#define HWIO_GCC_IPA_SREGR_SW_RST_SLP_STG_BMSK                                                           0x10
#define HWIO_GCC_IPA_SREGR_SW_RST_SLP_STG_SHFT                                                            0x4
#define HWIO_GCC_IPA_SREGR_SW_CTRL_PWR_DOWN_BMSK                                                          0x8
#define HWIO_GCC_IPA_SREGR_SW_CTRL_PWR_DOWN_SHFT                                                          0x3
#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                                     0x4
#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                                     0x2
#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SLP_STG_BMSK                                                         0x2
#define HWIO_GCC_IPA_SREGR_SW_CLK_EN_SLP_STG_SHFT                                                         0x1

#define HWIO_GCC_IPA_AHB_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00089020)
#define HWIO_GCC_IPA_AHB_CBCR_RMSK                                                                 0x80100007
#define HWIO_GCC_IPA_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_IPA_AHB_CBCR_ADDR)
#define HWIO_GCC_IPA_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPA_AHB_CBCR_ADDR, m)
#define HWIO_GCC_IPA_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_IPA_AHB_CBCR_ADDR,v)
#define HWIO_GCC_IPA_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPA_AHB_CBCR_ADDR,m,v,HWIO_GCC_IPA_AHB_CBCR_IN)
#define HWIO_GCC_IPA_AHB_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_IPA_AHB_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_IPA_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                               0x100000
#define HWIO_GCC_IPA_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                   0x14
#define HWIO_GCC_IPA_AHB_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_IPA_AHB_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_IPA_AHB_CBCR_HW_CTL_BMSK                                                                 0x2
#define HWIO_GCC_IPA_AHB_CBCR_HW_CTL_SHFT                                                                 0x1
#define HWIO_GCC_IPA_AHB_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_IPA_AHB_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_IPA_SLEEP_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00089024)
#define HWIO_GCC_IPA_SLEEP_CBCR_RMSK                                                               0x80000005
#define HWIO_GCC_IPA_SLEEP_CBCR_IN          \
        in_dword(HWIO_GCC_IPA_SLEEP_CBCR_ADDR)
#define HWIO_GCC_IPA_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPA_SLEEP_CBCR_ADDR, m)
#define HWIO_GCC_IPA_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_IPA_SLEEP_CBCR_ADDR,v)
#define HWIO_GCC_IPA_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPA_SLEEP_CBCR_ADDR,m,v,HWIO_GCC_IPA_SLEEP_CBCR_IN)
#define HWIO_GCC_IPA_SLEEP_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_IPA_SLEEP_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_IPA_SLEEP_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_IPA_SLEEP_CBCR_CLK_ARES_SHFT                                                             0x2
#define HWIO_GCC_IPA_SLEEP_CBCR_CLK_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_IPA_SLEEP_CBCR_CLK_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_IPA_APB_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00089028)
#define HWIO_GCC_IPA_APB_CBCR_RMSK                                                                 0x80000005
#define HWIO_GCC_IPA_APB_CBCR_IN          \
        in_dword(HWIO_GCC_IPA_APB_CBCR_ADDR)
#define HWIO_GCC_IPA_APB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPA_APB_CBCR_ADDR, m)
#define HWIO_GCC_IPA_APB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_IPA_APB_CBCR_ADDR,v)
#define HWIO_GCC_IPA_APB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPA_APB_CBCR_ADDR,m,v,HWIO_GCC_IPA_APB_CBCR_IN)
#define HWIO_GCC_IPA_APB_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_IPA_APB_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_IPA_APB_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_IPA_APB_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_IPA_APB_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_IPA_APB_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_IPA_XO_CBCR_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0008902c)
#define HWIO_GCC_IPA_XO_CBCR_RMSK                                                                  0x80000005
#define HWIO_GCC_IPA_XO_CBCR_IN          \
        in_dword(HWIO_GCC_IPA_XO_CBCR_ADDR)
#define HWIO_GCC_IPA_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPA_XO_CBCR_ADDR, m)
#define HWIO_GCC_IPA_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_IPA_XO_CBCR_ADDR,v)
#define HWIO_GCC_IPA_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPA_XO_CBCR_ADDR,m,v,HWIO_GCC_IPA_XO_CBCR_IN)
#define HWIO_GCC_IPA_XO_CBCR_CLK_OFF_BMSK                                                          0x80000000
#define HWIO_GCC_IPA_XO_CBCR_CLK_OFF_SHFT                                                                0x1f
#define HWIO_GCC_IPA_XO_CBCR_CLK_ARES_BMSK                                                                0x4
#define HWIO_GCC_IPA_XO_CBCR_CLK_ARES_SHFT                                                                0x2
#define HWIO_GCC_IPA_XO_CBCR_CLK_ENABLE_BMSK                                                              0x1
#define HWIO_GCC_IPA_XO_CBCR_CLK_ENABLE_SHFT                                                              0x0

#define HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00089044)
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_RMSK                                                                0xffff
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_CMD_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_RCG_SW_CTRL_BMSK                                                    0x8000
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_RCG_SW_CTRL_SHFT                                                       0xf
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_SW_PERF_STATE_BMSK                                                  0x7800
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_SW_PERF_STATE_SHFT                                                     0xb
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_SW_OVERRIDE_BMSK                                                     0x400
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_SW_OVERRIDE_SHFT                                                       0xa
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                        0x200
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                          0x9
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_DFS_FSM_STATE_BMSK                                                   0x1c0
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_DFS_FSM_STATE_SHFT                                                     0x6
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_HW_CLK_CONTROL_BMSK                                                   0x20
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_HW_CLK_CONTROL_SHFT                                                    0x5
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_CURR_PERF_STATE_BMSK                                                  0x1e
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_CURR_PERF_STATE_SHFT                                                   0x1
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_DFS_EN_BMSK                                                            0x1
#define HWIO_GCC_RPMH_IPA_CMD_DFSR_DFS_EN_SHFT                                                            0x0

#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0008904c)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_RMSK                                                        0x71f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00089050)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_RMSK                                                        0x71f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00089054)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_RMSK                                                        0x71f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00089058)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_RMSK                                                        0x71f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0008905c)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_RMSK                                                        0x71f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00089060)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_RMSK                                                        0x71f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00089064)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_RMSK                                                        0x71f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00089068)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_RMSK                                                        0x71f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0008906c)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_RMSK                                                        0x71f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00089070)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_RMSK                                                        0x71f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00089074)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_RMSK                                                       0x71f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00089078)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_RMSK                                                       0x71f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0008907c)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_RMSK                                                       0x71f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00089080)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_RMSK                                                       0x71f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00089084)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_RMSK                                                       0x71f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00089088)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_RMSK                                                       0x71f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_BMSK                                               0x700
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_SEL_SHFT                                                 0x8
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_BMSK                                                0x1f
#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_SRC_DIV_SHFT                                                 0x0

#define HWIO_GCC_IPA_2X_CMD_RCGR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00089030)
#define HWIO_GCC_IPA_2X_CMD_RCGR_RMSK                                                              0x80000013
#define HWIO_GCC_IPA_2X_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_IPA_2X_CMD_RCGR_ADDR)
#define HWIO_GCC_IPA_2X_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPA_2X_CMD_RCGR_ADDR, m)
#define HWIO_GCC_IPA_2X_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_IPA_2X_CMD_RCGR_ADDR,v)
#define HWIO_GCC_IPA_2X_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPA_2X_CMD_RCGR_ADDR,m,v,HWIO_GCC_IPA_2X_CMD_RCGR_IN)
#define HWIO_GCC_IPA_2X_CMD_RCGR_ROOT_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_IPA_2X_CMD_RCGR_ROOT_OFF_SHFT                                                           0x1f
#define HWIO_GCC_IPA_2X_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                     0x10
#define HWIO_GCC_IPA_2X_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                      0x4
#define HWIO_GCC_IPA_2X_CMD_RCGR_ROOT_EN_BMSK                                                             0x2
#define HWIO_GCC_IPA_2X_CMD_RCGR_ROOT_EN_SHFT                                                             0x1
#define HWIO_GCC_IPA_2X_CMD_RCGR_UPDATE_BMSK                                                              0x1
#define HWIO_GCC_IPA_2X_CMD_RCGR_UPDATE_SHFT                                                              0x0

#define HWIO_GCC_IPA_2X_CFG_RCGR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00089034)
#define HWIO_GCC_IPA_2X_CFG_RCGR_RMSK                                                                0x11071f
#define HWIO_GCC_IPA_2X_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_IPA_2X_CFG_RCGR_ADDR)
#define HWIO_GCC_IPA_2X_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPA_2X_CFG_RCGR_ADDR, m)
#define HWIO_GCC_IPA_2X_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_IPA_2X_CFG_RCGR_ADDR,v)
#define HWIO_GCC_IPA_2X_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPA_2X_CFG_RCGR_ADDR,m,v,HWIO_GCC_IPA_2X_CFG_RCGR_IN)
#define HWIO_GCC_IPA_2X_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                 0x100000
#define HWIO_GCC_IPA_2X_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                     0x14
#define HWIO_GCC_IPA_2X_CFG_RCGR_RCGLITE_DISABLE_BMSK                                                 0x10000
#define HWIO_GCC_IPA_2X_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                    0x10
#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_BMSK                                                           0x700
#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_SEL_SHFT                                                             0x8
#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_BMSK                                                            0x1f
#define HWIO_GCC_IPA_2X_CFG_RCGR_SRC_DIV_SHFT                                                             0x0

#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0008915c)
#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_RMSK                                                                0x1
#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_IPA_CDIVR_ADDR                                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00089160)
#define HWIO_GCC_IPA_CDIVR_RMSK                                                                           0x3
#define HWIO_GCC_IPA_CDIVR_IN          \
        in_dword(HWIO_GCC_IPA_CDIVR_ADDR)
#define HWIO_GCC_IPA_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPA_CDIVR_ADDR, m)
#define HWIO_GCC_IPA_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_IPA_CDIVR_ADDR,v)
#define HWIO_GCC_IPA_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPA_CDIVR_ADDR,m,v,HWIO_GCC_IPA_CDIVR_IN)
#define HWIO_GCC_IPA_CDIVR_CLK_DIV_BMSK                                                                   0x3
#define HWIO_GCC_IPA_CDIVR_CLK_DIV_SHFT                                                                   0x0

#define HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a000)
#define HWIO_GCC_MSS_CFG_AHB_CBCR_RMSK                                                             0x80100007
#define HWIO_GCC_MSS_CFG_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR)
#define HWIO_GCC_MSS_CFG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR, m)
#define HWIO_GCC_MSS_CFG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR,v)
#define HWIO_GCC_MSS_CFG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_MSS_CFG_AHB_CBCR_IN)
#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_MSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_MSS_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_MSS_CFG_AHB_CBCR_HW_CTL_BMSK                                                             0x2
#define HWIO_GCC_MSS_CFG_AHB_CBCR_HW_CTL_SHFT                                                             0x1
#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_MSS_CFG_AHB_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a004)
#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_RMSK                                                           0x80100007
#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_IN          \
        in_dword(HWIO_GCC_MSS_MFAB_AXIS_CBCR_ADDR)
#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_MFAB_AXIS_CBCR_ADDR, m)
#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_MFAB_AXIS_CBCR_ADDR,v)
#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_MFAB_AXIS_CBCR_ADDR,m,v,HWIO_GCC_MSS_MFAB_AXIS_CBCR_IN)
#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_HW_CTL_BMSK                                                           0x2
#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_HW_CTL_SHFT                                                           0x1
#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_MSS_AXIS2_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a008)
#define HWIO_GCC_MSS_AXIS2_CBCR_RMSK                                                               0x80100005
#define HWIO_GCC_MSS_AXIS2_CBCR_IN          \
        in_dword(HWIO_GCC_MSS_AXIS2_CBCR_ADDR)
#define HWIO_GCC_MSS_AXIS2_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_AXIS2_CBCR_ADDR, m)
#define HWIO_GCC_MSS_AXIS2_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_AXIS2_CBCR_ADDR,v)
#define HWIO_GCC_MSS_AXIS2_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_AXIS2_CBCR_ADDR,m,v,HWIO_GCC_MSS_AXIS2_CBCR_IN)
#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_MSS_AXIS2_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                             0x100000
#define HWIO_GCC_MSS_AXIS2_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                 0x14
#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_ARES_SHFT                                                             0x2
#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_MSS_AXIS2_CBCR_CLK_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_MSS_TRIG_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a00c)
#define HWIO_GCC_MSS_TRIG_CBCR_RMSK                                                                0x80100005
#define HWIO_GCC_MSS_TRIG_CBCR_IN          \
        in_dword(HWIO_GCC_MSS_TRIG_CBCR_ADDR)
#define HWIO_GCC_MSS_TRIG_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_TRIG_CBCR_ADDR, m)
#define HWIO_GCC_MSS_TRIG_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_TRIG_CBCR_ADDR,v)
#define HWIO_GCC_MSS_TRIG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_TRIG_CBCR_ADDR,m,v,HWIO_GCC_MSS_TRIG_CBCR_IN)
#define HWIO_GCC_MSS_TRIG_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_MSS_TRIG_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_MSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_MSS_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_MSS_TRIG_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_MSS_AT_CBCR_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a010)
#define HWIO_GCC_MSS_AT_CBCR_RMSK                                                                  0x80100005
#define HWIO_GCC_MSS_AT_CBCR_IN          \
        in_dword(HWIO_GCC_MSS_AT_CBCR_ADDR)
#define HWIO_GCC_MSS_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_AT_CBCR_ADDR, m)
#define HWIO_GCC_MSS_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_AT_CBCR_ADDR,v)
#define HWIO_GCC_MSS_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_AT_CBCR_ADDR,m,v,HWIO_GCC_MSS_AT_CBCR_IN)
#define HWIO_GCC_MSS_AT_CBCR_CLK_OFF_BMSK                                                          0x80000000
#define HWIO_GCC_MSS_AT_CBCR_CLK_OFF_SHFT                                                                0x1f
#define HWIO_GCC_MSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                                0x100000
#define HWIO_GCC_MSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                    0x14
#define HWIO_GCC_MSS_AT_CBCR_CLK_ARES_BMSK                                                                0x4
#define HWIO_GCC_MSS_AT_CBCR_CLK_ARES_SHFT                                                                0x2
#define HWIO_GCC_MSS_AT_CBCR_CLK_ENABLE_BMSK                                                              0x1
#define HWIO_GCC_MSS_AT_CBCR_CLK_ENABLE_SHFT                                                              0x0

#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a014)
#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_RMSK                                                             0x3
#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_IN          \
        in_dword(HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR)
#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR, m)
#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR,v)
#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR,m,v,HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_IN)
#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_CLK_DIV_BMSK                                                     0x3
#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_CLK_DIV_SHFT                                                     0x0

#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a034)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a038)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a03c)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a040)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a044)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a048)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a04c)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a050)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a054)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a058)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_RMSK                                            0x71f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_SEL_BMSK                                    0x700
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_SEL_SHFT                                      0x8
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_BMSK                                     0x1f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_SRC_DIV_SHFT                                      0x0

#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a05c)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a060)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a064)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a068)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a06c)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_ADDR                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a070)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_RMSK                                           0x71f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_SEL_BMSK                                   0x700
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_SEL_SHFT                                     0x8
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_BMSK                                    0x1f
#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_SRC_DIV_SHFT                                     0x0

#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a018)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_RMSK                                                   0x80000013
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ADDR)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ADDR, m)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ADDR,v)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ADDR,m,v,HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_IN)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ROOT_OFF_BMSK                                          0x80000000
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ROOT_OFF_SHFT                                                0x1f
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                          0x10
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                           0x4
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ROOT_EN_BMSK                                                  0x2
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ROOT_EN_SHFT                                                  0x1
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_UPDATE_BMSK                                                   0x1
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_UPDATE_SHFT                                                   0x0

#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a01c)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_RMSK                                                     0x11071f
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_ADDR)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_ADDR, m)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_ADDR,v)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_ADDR,m,v,HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_IN)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_HW_CLK_CONTROL_BMSK                                      0x100000
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_HW_CLK_CONTROL_SHFT                                          0x14
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_RCGLITE_DISABLE_BMSK                                      0x10000
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_RCGLITE_DISABLE_SHFT                                         0x10
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_SEL_BMSK                                                0x700
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_SEL_SHFT                                                  0x8
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_SRC_DIV_SHFT                                                  0x0

#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a144)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_RMSK                                                     0x1
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                          0x1
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                          0x0

#define HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a14c)
#define HWIO_GCC_MSS_SNOC_AXI_CBCR_RMSK                                                            0x80100005
#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR)
#define HWIO_GCC_MSS_SNOC_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR, m)
#define HWIO_GCC_MSS_SNOC_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR,v)
#define HWIO_GCC_MSS_SNOC_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR,m,v,HWIO_GCC_MSS_SNOC_AXI_CBCR_IN)
#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_OFF_SHFT                                                          0x1f
#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                          0x100000
#define HWIO_GCC_MSS_SNOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                              0x14
#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ARES_BMSK                                                          0x4
#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ARES_SHFT                                                          0x2
#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ENABLE_BMSK                                                        0x1
#define HWIO_GCC_MSS_SNOC_AXI_CBCR_CLK_ENABLE_SHFT                                                        0x0

#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a150)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_RMSK                                                       0x80100005
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_ADDR)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_ADDR, m)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_ADDR,v)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_ADDR,m,v,HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_IN)
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                     0x100000
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                         0x14
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_GLM_BCR_ADDR                                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0008b000)
#define HWIO_GCC_GLM_BCR_RMSK                                                                             0x1
#define HWIO_GCC_GLM_BCR_IN          \
        in_dword(HWIO_GCC_GLM_BCR_ADDR)
#define HWIO_GCC_GLM_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GLM_BCR_ADDR, m)
#define HWIO_GCC_GLM_BCR_OUT(v)      \
        out_dword(HWIO_GCC_GLM_BCR_ADDR,v)
#define HWIO_GCC_GLM_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GLM_BCR_ADDR,m,v,HWIO_GCC_GLM_BCR_IN)
#define HWIO_GCC_GLM_BCR_BLK_ARES_BMSK                                                                    0x1
#define HWIO_GCC_GLM_BCR_BLK_ARES_SHFT                                                                    0x0

#define HWIO_GCC_GLM_AHB_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0008b004)
#define HWIO_GCC_GLM_AHB_CBCR_RMSK                                                                 0x80100005
#define HWIO_GCC_GLM_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_GLM_AHB_CBCR_ADDR)
#define HWIO_GCC_GLM_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GLM_AHB_CBCR_ADDR, m)
#define HWIO_GCC_GLM_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_GLM_AHB_CBCR_ADDR,v)
#define HWIO_GCC_GLM_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GLM_AHB_CBCR_ADDR,m,v,HWIO_GCC_GLM_AHB_CBCR_IN)
#define HWIO_GCC_GLM_AHB_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_GLM_AHB_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_GLM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                               0x100000
#define HWIO_GCC_GLM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                   0x14
#define HWIO_GCC_GLM_AHB_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_GLM_AHB_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_GLM_AHB_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_GLM_AHB_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_GLM_CBCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0008b008)
#define HWIO_GCC_GLM_CBCR_RMSK                                                                     0x80000005
#define HWIO_GCC_GLM_CBCR_IN          \
        in_dword(HWIO_GCC_GLM_CBCR_ADDR)
#define HWIO_GCC_GLM_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GLM_CBCR_ADDR, m)
#define HWIO_GCC_GLM_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_GLM_CBCR_ADDR,v)
#define HWIO_GCC_GLM_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GLM_CBCR_ADDR,m,v,HWIO_GCC_GLM_CBCR_IN)
#define HWIO_GCC_GLM_CBCR_CLK_OFF_BMSK                                                             0x80000000
#define HWIO_GCC_GLM_CBCR_CLK_OFF_SHFT                                                                   0x1f
#define HWIO_GCC_GLM_CBCR_CLK_ARES_BMSK                                                                   0x4
#define HWIO_GCC_GLM_CBCR_CLK_ARES_SHFT                                                                   0x2
#define HWIO_GCC_GLM_CBCR_CLK_ENABLE_BMSK                                                                 0x1
#define HWIO_GCC_GLM_CBCR_CLK_ENABLE_SHFT                                                                 0x0

#define HWIO_GCC_GLM_XO_CBCR_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0008b00c)
#define HWIO_GCC_GLM_XO_CBCR_RMSK                                                                  0x80000005
#define HWIO_GCC_GLM_XO_CBCR_IN          \
        in_dword(HWIO_GCC_GLM_XO_CBCR_ADDR)
#define HWIO_GCC_GLM_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GLM_XO_CBCR_ADDR, m)
#define HWIO_GCC_GLM_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_GLM_XO_CBCR_ADDR,v)
#define HWIO_GCC_GLM_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GLM_XO_CBCR_ADDR,m,v,HWIO_GCC_GLM_XO_CBCR_IN)
#define HWIO_GCC_GLM_XO_CBCR_CLK_OFF_BMSK                                                          0x80000000
#define HWIO_GCC_GLM_XO_CBCR_CLK_OFF_SHFT                                                                0x1f
#define HWIO_GCC_GLM_XO_CBCR_CLK_ARES_BMSK                                                                0x4
#define HWIO_GCC_GLM_XO_CBCR_CLK_ARES_SHFT                                                                0x2
#define HWIO_GCC_GLM_XO_CBCR_CLK_ENABLE_BMSK                                                              0x1
#define HWIO_GCC_GLM_XO_CBCR_CLK_ENABLE_SHFT                                                              0x0

#define HWIO_GCC_GLM_CMD_RCGR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0008b010)
#define HWIO_GCC_GLM_CMD_RCGR_RMSK                                                                 0x80000013
#define HWIO_GCC_GLM_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_GLM_CMD_RCGR_ADDR)
#define HWIO_GCC_GLM_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_GLM_CMD_RCGR_ADDR, m)
#define HWIO_GCC_GLM_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_GLM_CMD_RCGR_ADDR,v)
#define HWIO_GCC_GLM_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GLM_CMD_RCGR_ADDR,m,v,HWIO_GCC_GLM_CMD_RCGR_IN)
#define HWIO_GCC_GLM_CMD_RCGR_ROOT_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_GLM_CMD_RCGR_ROOT_OFF_SHFT                                                              0x1f
#define HWIO_GCC_GLM_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                        0x10
#define HWIO_GCC_GLM_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                         0x4
#define HWIO_GCC_GLM_CMD_RCGR_ROOT_EN_BMSK                                                                0x2
#define HWIO_GCC_GLM_CMD_RCGR_ROOT_EN_SHFT                                                                0x1
#define HWIO_GCC_GLM_CMD_RCGR_UPDATE_BMSK                                                                 0x1
#define HWIO_GCC_GLM_CMD_RCGR_UPDATE_SHFT                                                                 0x0

#define HWIO_GCC_GLM_CFG_RCGR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0008b014)
#define HWIO_GCC_GLM_CFG_RCGR_RMSK                                                                   0x11071f
#define HWIO_GCC_GLM_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_GLM_CFG_RCGR_ADDR)
#define HWIO_GCC_GLM_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_GLM_CFG_RCGR_ADDR, m)
#define HWIO_GCC_GLM_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_GLM_CFG_RCGR_ADDR,v)
#define HWIO_GCC_GLM_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GLM_CFG_RCGR_ADDR,m,v,HWIO_GCC_GLM_CFG_RCGR_IN)
#define HWIO_GCC_GLM_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                    0x100000
#define HWIO_GCC_GLM_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                        0x14
#define HWIO_GCC_GLM_CFG_RCGR_RCGLITE_DISABLE_BMSK                                                    0x10000
#define HWIO_GCC_GLM_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                       0x10
#define HWIO_GCC_GLM_CFG_RCGR_SRC_SEL_BMSK                                                              0x700
#define HWIO_GCC_GLM_CFG_RCGR_SRC_SEL_SHFT                                                                0x8
#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_BMSK                                                               0x1f
#define HWIO_GCC_GLM_CFG_RCGR_SRC_DIV_SHFT                                                                0x0

#define HWIO_GCC_QREFS_VBG_CAL_BCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00088000)
#define HWIO_GCC_QREFS_VBG_CAL_BCR_RMSK                                                                   0x1
#define HWIO_GCC_QREFS_VBG_CAL_BCR_IN          \
        in_dword(HWIO_GCC_QREFS_VBG_CAL_BCR_ADDR)
#define HWIO_GCC_QREFS_VBG_CAL_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QREFS_VBG_CAL_BCR_ADDR, m)
#define HWIO_GCC_QREFS_VBG_CAL_BCR_OUT(v)      \
        out_dword(HWIO_GCC_QREFS_VBG_CAL_BCR_ADDR,v)
#define HWIO_GCC_QREFS_VBG_CAL_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QREFS_VBG_CAL_BCR_ADDR,m,v,HWIO_GCC_QREFS_VBG_CAL_BCR_IN)
#define HWIO_GCC_QREFS_VBG_CAL_BCR_BLK_ARES_BMSK                                                          0x1
#define HWIO_GCC_QREFS_VBG_CAL_BCR_BLK_ARES_SHFT                                                          0x0

#define HWIO_GCC_QREFS_VBG_CAL_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00088004)
#define HWIO_GCC_QREFS_VBG_CAL_CBCR_RMSK                                                           0x80000005
#define HWIO_GCC_QREFS_VBG_CAL_CBCR_IN          \
        in_dword(HWIO_GCC_QREFS_VBG_CAL_CBCR_ADDR)
#define HWIO_GCC_QREFS_VBG_CAL_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QREFS_VBG_CAL_CBCR_ADDR, m)
#define HWIO_GCC_QREFS_VBG_CAL_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QREFS_VBG_CAL_CBCR_ADDR,v)
#define HWIO_GCC_QREFS_VBG_CAL_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QREFS_VBG_CAL_CBCR_ADDR,m,v,HWIO_GCC_QREFS_VBG_CAL_CBCR_IN)
#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_QREFS_VBG_CAL_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_WCSS_AHB_S0_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00011000)
#define HWIO_GCC_WCSS_AHB_S0_CBCR_RMSK                                                             0x80100005
#define HWIO_GCC_WCSS_AHB_S0_CBCR_IN          \
        in_dword(HWIO_GCC_WCSS_AHB_S0_CBCR_ADDR)
#define HWIO_GCC_WCSS_AHB_S0_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_WCSS_AHB_S0_CBCR_ADDR, m)
#define HWIO_GCC_WCSS_AHB_S0_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_WCSS_AHB_S0_CBCR_ADDR,v)
#define HWIO_GCC_WCSS_AHB_S0_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_WCSS_AHB_S0_CBCR_ADDR,m,v,HWIO_GCC_WCSS_AHB_S0_CBCR_IN)
#define HWIO_GCC_WCSS_AHB_S0_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_WCSS_AHB_S0_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_WCSS_AHB_S0_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_WCSS_AHB_S0_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_WCSS_AHB_S0_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_WCSS_AHB_S0_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_WCSS_AHB_S0_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_WCSS_AHB_S0_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_WCSS_AXI_M_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00011004)
#define HWIO_GCC_WCSS_AXI_M_CBCR_RMSK                                                              0x80100005
#define HWIO_GCC_WCSS_AXI_M_CBCR_IN          \
        in_dword(HWIO_GCC_WCSS_AXI_M_CBCR_ADDR)
#define HWIO_GCC_WCSS_AXI_M_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_WCSS_AXI_M_CBCR_ADDR, m)
#define HWIO_GCC_WCSS_AXI_M_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_WCSS_AXI_M_CBCR_ADDR,v)
#define HWIO_GCC_WCSS_AXI_M_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_WCSS_AXI_M_CBCR_ADDR,m,v,HWIO_GCC_WCSS_AXI_M_CBCR_IN)
#define HWIO_GCC_WCSS_AXI_M_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_WCSS_AXI_M_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_WCSS_AXI_M_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                            0x100000
#define HWIO_GCC_WCSS_AXI_M_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                0x14
#define HWIO_GCC_WCSS_AXI_M_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_WCSS_AXI_M_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_WCSS_AXI_M_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_WCSS_AXI_M_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_WCSS_ECAHB_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00011008)
#define HWIO_GCC_WCSS_ECAHB_CBCR_RMSK                                                              0x80100005
#define HWIO_GCC_WCSS_ECAHB_CBCR_IN          \
        in_dword(HWIO_GCC_WCSS_ECAHB_CBCR_ADDR)
#define HWIO_GCC_WCSS_ECAHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_WCSS_ECAHB_CBCR_ADDR, m)
#define HWIO_GCC_WCSS_ECAHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_WCSS_ECAHB_CBCR_ADDR,v)
#define HWIO_GCC_WCSS_ECAHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_WCSS_ECAHB_CBCR_ADDR,m,v,HWIO_GCC_WCSS_ECAHB_CBCR_IN)
#define HWIO_GCC_WCSS_ECAHB_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_WCSS_ECAHB_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_WCSS_ECAHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                            0x100000
#define HWIO_GCC_WCSS_ECAHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                0x14
#define HWIO_GCC_WCSS_ECAHB_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_WCSS_ECAHB_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_WCSS_ECAHB_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_WCSS_ECAHB_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0001100c)
#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_RMSK                                                         0x80100005
#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_WCSS_SHDREG_AHB_CBCR_ADDR)
#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_WCSS_SHDREG_AHB_CBCR_ADDR, m)
#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_WCSS_SHDREG_AHB_CBCR_ADDR,v)
#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_WCSS_SHDREG_AHB_CBCR_ADDR,m,v,HWIO_GCC_WCSS_SHDREG_AHB_CBCR_IN)
#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                       0x100000
#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                           0x14
#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_CLK_ARES_SHFT                                                       0x2
#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_CLK_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_WCSS_AT_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00011010)
#define HWIO_GCC_WCSS_AT_CBCR_RMSK                                                                 0x80100005
#define HWIO_GCC_WCSS_AT_CBCR_IN          \
        in_dword(HWIO_GCC_WCSS_AT_CBCR_ADDR)
#define HWIO_GCC_WCSS_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_WCSS_AT_CBCR_ADDR, m)
#define HWIO_GCC_WCSS_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_WCSS_AT_CBCR_ADDR,v)
#define HWIO_GCC_WCSS_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_WCSS_AT_CBCR_ADDR,m,v,HWIO_GCC_WCSS_AT_CBCR_IN)
#define HWIO_GCC_WCSS_AT_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_WCSS_AT_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_WCSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                               0x100000
#define HWIO_GCC_WCSS_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                   0x14
#define HWIO_GCC_WCSS_AT_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_WCSS_AT_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_WCSS_AT_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_WCSS_AT_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_WCSS_APB_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00011014)
#define HWIO_GCC_WCSS_APB_CBCR_RMSK                                                                0x80000005
#define HWIO_GCC_WCSS_APB_CBCR_IN          \
        in_dword(HWIO_GCC_WCSS_APB_CBCR_ADDR)
#define HWIO_GCC_WCSS_APB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_WCSS_APB_CBCR_ADDR, m)
#define HWIO_GCC_WCSS_APB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_WCSS_APB_CBCR_ADDR,v)
#define HWIO_GCC_WCSS_APB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_WCSS_APB_CBCR_ADDR,m,v,HWIO_GCC_WCSS_APB_CBCR_IN)
#define HWIO_GCC_WCSS_APB_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_WCSS_APB_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_WCSS_APB_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_WCSS_APB_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_WCSS_APB_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_WCSS_APB_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_GPU_BCR_ADDR                                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00071000)
#define HWIO_GCC_GPU_BCR_RMSK                                                                             0x1
#define HWIO_GCC_GPU_BCR_IN          \
        in_dword(HWIO_GCC_GPU_BCR_ADDR)
#define HWIO_GCC_GPU_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPU_BCR_ADDR, m)
#define HWIO_GCC_GPU_BCR_OUT(v)      \
        out_dword(HWIO_GCC_GPU_BCR_ADDR,v)
#define HWIO_GCC_GPU_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPU_BCR_ADDR,m,v,HWIO_GCC_GPU_BCR_IN)
#define HWIO_GCC_GPU_BCR_BLK_ARES_BMSK                                                                    0x1
#define HWIO_GCC_GPU_BCR_BLK_ARES_SHFT                                                                    0x0

#define HWIO_GCC_GPU_CFG_AHB_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00071004)
#define HWIO_GCC_GPU_CFG_AHB_CBCR_RMSK                                                             0x80100007
#define HWIO_GCC_GPU_CFG_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_GPU_CFG_AHB_CBCR_ADDR)
#define HWIO_GCC_GPU_CFG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPU_CFG_AHB_CBCR_ADDR, m)
#define HWIO_GCC_GPU_CFG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_GPU_CFG_AHB_CBCR_ADDR,v)
#define HWIO_GCC_GPU_CFG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPU_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_GPU_CFG_AHB_CBCR_IN)
#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_GPU_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_GPU_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_GPU_CFG_AHB_CBCR_HW_CTL_BMSK                                                             0x2
#define HWIO_GCC_GPU_CFG_AHB_CBCR_HW_CTL_SHFT                                                             0x1
#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_GPU_CFG_AHB_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_GPU_AT_CBCR_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00071008)
#define HWIO_GCC_GPU_AT_CBCR_RMSK                                                                  0x80100005
#define HWIO_GCC_GPU_AT_CBCR_IN          \
        in_dword(HWIO_GCC_GPU_AT_CBCR_ADDR)
#define HWIO_GCC_GPU_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPU_AT_CBCR_ADDR, m)
#define HWIO_GCC_GPU_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_GPU_AT_CBCR_ADDR,v)
#define HWIO_GCC_GPU_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPU_AT_CBCR_ADDR,m,v,HWIO_GCC_GPU_AT_CBCR_IN)
#define HWIO_GCC_GPU_AT_CBCR_CLK_OFF_BMSK                                                          0x80000000
#define HWIO_GCC_GPU_AT_CBCR_CLK_OFF_SHFT                                                                0x1f
#define HWIO_GCC_GPU_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                                0x100000
#define HWIO_GCC_GPU_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                    0x14
#define HWIO_GCC_GPU_AT_CBCR_CLK_ARES_BMSK                                                                0x4
#define HWIO_GCC_GPU_AT_CBCR_CLK_ARES_SHFT                                                                0x2
#define HWIO_GCC_GPU_AT_CBCR_CLK_ENABLE_BMSK                                                              0x1
#define HWIO_GCC_GPU_AT_CBCR_CLK_ENABLE_SHFT                                                              0x0

#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0007100c)
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_RMSK                                                          0x80107ff5
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_IN          \
        in_dword(HWIO_GCC_GPU_MEMNOC_GFX_CBCR_ADDR)
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPU_MEMNOC_GFX_CBCR_ADDR, m)
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_GPU_MEMNOC_GFX_CBCR_ADDR,v)
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPU_MEMNOC_GFX_CBCR_ADDR,m,v,HWIO_GCC_GPU_MEMNOC_GFX_CBCR_IN)
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_CLK_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00071010)
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_RMSK                                                         0xfffff37e
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_IN          \
        in_dword(HWIO_GCC_GPU_MEMNOC_GFX_SREGR_ADDR)
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPU_MEMNOC_GFX_SREGR_ADDR, m)
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_GPU_MEMNOC_GFX_SREGR_ADDR,v)
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPU_MEMNOC_GFX_SREGR_ADDR,m,v,HWIO_GCC_GPU_MEMNOC_GFX_SREGR_IN)
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                               0xff000000
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                     0x18
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                  0xff0000
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                      0x10
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_RESERVE_BITS15_13_BMSK                                           0xe000
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_RESERVE_BITS15_13_SHFT                                              0xd
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                 0x1000
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                    0xc
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                     0x300
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                       0x8
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_FORCE_CLK_ON_BMSK                                                  0x40
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_FORCE_CLK_ON_SHFT                                                   0x6
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SW_RST_SEL_SLP_STG_BMSK                                            0x20
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SW_RST_SEL_SLP_STG_SHFT                                             0x5
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SW_RST_SLP_STG_BMSK                                                0x10
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SW_RST_SLP_STG_SHFT                                                 0x4
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SW_CTRL_PWR_DOWN_BMSK                                               0x8
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SW_CTRL_PWR_DOWN_SHFT                                               0x3
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                          0x4
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                          0x2
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SW_CLK_EN_SLP_STG_BMSK                                              0x2
#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_SW_CLK_EN_SLP_STG_SHFT                                              0x1

#define HWIO_GCC_GPU_TRIG_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00071014)
#define HWIO_GCC_GPU_TRIG_CBCR_RMSK                                                                0x80100005
#define HWIO_GCC_GPU_TRIG_CBCR_IN          \
        in_dword(HWIO_GCC_GPU_TRIG_CBCR_ADDR)
#define HWIO_GCC_GPU_TRIG_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPU_TRIG_CBCR_ADDR, m)
#define HWIO_GCC_GPU_TRIG_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_GPU_TRIG_CBCR_ADDR,v)
#define HWIO_GCC_GPU_TRIG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPU_TRIG_CBCR_ADDR,m,v,HWIO_GCC_GPU_TRIG_CBCR_IN)
#define HWIO_GCC_GPU_TRIG_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_GPU_TRIG_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_GPU_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_GPU_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_GPU_TRIG_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_GPU_TRIG_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_GPU_TRIG_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_GPU_TRIG_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00071018)
#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_RMSK                                                        0x80100005
#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_IN          \
        in_dword(HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_ADDR)
#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_ADDR, m)
#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_ADDR,v)
#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_ADDR,m,v,HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_IN)
#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                      0x100000
#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                          0x14
#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00071038)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0007103c)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00071040)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00071044)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00071048)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0007104c)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00071050)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00071054)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00071058)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0007105c)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_RMSK                                               0x71f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_SEL_BMSK                                       0x700
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_SEL_SHFT                                         0x8
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_BMSK                                        0x1f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_SRC_DIV_SHFT                                         0x0

#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00071060)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00071064)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00071068)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0007106c)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00071070)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00071074)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_RMSK                                              0x71f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_SEL_BMSK                                      0x700
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_SEL_SHFT                                        0x8
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_BMSK                                       0x1f
#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_SRC_DIV_SHFT                                        0x0

#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0007101c)
#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_RMSK                                                      0x80000013
#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ADDR)
#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ADDR, m)
#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ADDR,v)
#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ADDR,m,v,HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_IN)
#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00071020)
#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_RMSK                                                        0x11071f
#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_ADDR)
#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_ADDR, m)
#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_ADDR,v)
#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_ADDR,m,v,HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_IN)
#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_RCGLITE_DISABLE_BMSK                                         0x10000
#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_RCGLITE_DISABLE_SHFT                                            0x10
#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00071148)
#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_RMSK                                                        0x1
#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                             0x1
#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                             0x0

#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0007114c)
#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_RMSK                                                             0x3
#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_IN          \
        in_dword(HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_ADDR)
#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_ADDR, m)
#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_ADDR,v)
#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_ADDR,m,v,HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_IN)
#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_CLK_DIV_BMSK                                                     0x3
#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_CLK_DIV_SHFT                                                     0x0

#define HWIO_GCC_GPU_TRIG_CDIVR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00071150)
#define HWIO_GCC_GPU_TRIG_CDIVR_RMSK                                                                      0x3
#define HWIO_GCC_GPU_TRIG_CDIVR_IN          \
        in_dword(HWIO_GCC_GPU_TRIG_CDIVR_ADDR)
#define HWIO_GCC_GPU_TRIG_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPU_TRIG_CDIVR_ADDR, m)
#define HWIO_GCC_GPU_TRIG_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_GPU_TRIG_CDIVR_ADDR,v)
#define HWIO_GCC_GPU_TRIG_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPU_TRIG_CDIVR_ADDR,m,v,HWIO_GCC_GPU_TRIG_CDIVR_IN)
#define HWIO_GCC_GPU_TRIG_CDIVR_CLK_DIV_BMSK                                                              0x3
#define HWIO_GCC_GPU_TRIG_CDIVR_CLK_DIV_SHFT                                                              0x0

#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00072000)
#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_RMSK                                                        0x80100005
#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_ADDR)
#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_ADDR, m)
#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_ADDR,v)
#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_ADDR,m,v,HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_IN)
#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                      0x100000
#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                          0x14
#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_SP_SCR_NIU_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00072004)
#define HWIO_GCC_SP_SCR_NIU_CBCR_RMSK                                                              0x80100005
#define HWIO_GCC_SP_SCR_NIU_CBCR_IN          \
        in_dword(HWIO_GCC_SP_SCR_NIU_CBCR_ADDR)
#define HWIO_GCC_SP_SCR_NIU_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_SCR_NIU_CBCR_ADDR, m)
#define HWIO_GCC_SP_SCR_NIU_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_SCR_NIU_CBCR_ADDR,v)
#define HWIO_GCC_SP_SCR_NIU_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_SCR_NIU_CBCR_ADDR,m,v,HWIO_GCC_SP_SCR_NIU_CBCR_IN)
#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_SP_SCR_NIU_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                            0x100000
#define HWIO_GCC_SP_SCR_NIU_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                0x14
#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_SP_SCR_NIU_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_SP_CFG_AHB_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00072008)
#define HWIO_GCC_SP_CFG_AHB_CBCR_RMSK                                                              0x80100007
#define HWIO_GCC_SP_CFG_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_SP_CFG_AHB_CBCR_ADDR)
#define HWIO_GCC_SP_CFG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_CFG_AHB_CBCR_ADDR, m)
#define HWIO_GCC_SP_CFG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_CFG_AHB_CBCR_ADDR,v)
#define HWIO_GCC_SP_CFG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_SP_CFG_AHB_CBCR_IN)
#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_SP_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                            0x100000
#define HWIO_GCC_SP_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                0x14
#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_SP_CFG_AHB_CBCR_HW_CTL_BMSK                                                              0x2
#define HWIO_GCC_SP_CFG_AHB_CBCR_HW_CTL_SHFT                                                              0x1
#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_SP_CFG_AHB_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_SP_SCSR_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0007200c)
#define HWIO_GCC_SP_SCSR_CBCR_RMSK                                                                 0x80100005
#define HWIO_GCC_SP_SCSR_CBCR_IN          \
        in_dword(HWIO_GCC_SP_SCSR_CBCR_ADDR)
#define HWIO_GCC_SP_SCSR_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_SCSR_CBCR_ADDR, m)
#define HWIO_GCC_SP_SCSR_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_SCSR_CBCR_ADDR,v)
#define HWIO_GCC_SP_SCSR_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_SCSR_CBCR_ADDR,m,v,HWIO_GCC_SP_SCSR_CBCR_IN)
#define HWIO_GCC_SP_SCSR_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_SP_SCSR_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_SP_SCSR_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                               0x100000
#define HWIO_GCC_SP_SCSR_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                   0x14
#define HWIO_GCC_SP_SCSR_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_SP_SCSR_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_SP_SCSR_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_SP_SCSR_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_SP_SEC_CTRL_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00072010)
#define HWIO_GCC_SP_SEC_CTRL_CBCR_RMSK                                                             0x80000005
#define HWIO_GCC_SP_SEC_CTRL_CBCR_IN          \
        in_dword(HWIO_GCC_SP_SEC_CTRL_CBCR_ADDR)
#define HWIO_GCC_SP_SEC_CTRL_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_SEC_CTRL_CBCR_ADDR, m)
#define HWIO_GCC_SP_SEC_CTRL_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_SEC_CTRL_CBCR_ADDR,v)
#define HWIO_GCC_SP_SEC_CTRL_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_SEC_CTRL_CBCR_ADDR,m,v,HWIO_GCC_SP_SEC_CTRL_CBCR_IN)
#define HWIO_GCC_SP_SEC_CTRL_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_SP_SEC_CTRL_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_SP_SEC_CTRL_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_SP_SEC_CTRL_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_SP_SEC_CTRL_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_SP_SEC_CTRL_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_SP_GPKT_XO_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00072014)
#define HWIO_GCC_SP_GPKT_XO_CBCR_RMSK                                                              0x80000005
#define HWIO_GCC_SP_GPKT_XO_CBCR_IN          \
        in_dword(HWIO_GCC_SP_GPKT_XO_CBCR_ADDR)
#define HWIO_GCC_SP_GPKT_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_GPKT_XO_CBCR_ADDR, m)
#define HWIO_GCC_SP_GPKT_XO_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_GPKT_XO_CBCR_ADDR,v)
#define HWIO_GCC_SP_GPKT_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_GPKT_XO_CBCR_ADDR,m,v,HWIO_GCC_SP_GPKT_XO_CBCR_IN)
#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_SP_GPKT_XO_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_SP_TRIG_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00072018)
#define HWIO_GCC_SP_TRIG_CBCR_RMSK                                                                 0x80100005
#define HWIO_GCC_SP_TRIG_CBCR_IN          \
        in_dword(HWIO_GCC_SP_TRIG_CBCR_ADDR)
#define HWIO_GCC_SP_TRIG_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_TRIG_CBCR_ADDR, m)
#define HWIO_GCC_SP_TRIG_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_TRIG_CBCR_ADDR,v)
#define HWIO_GCC_SP_TRIG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_TRIG_CBCR_ADDR,m,v,HWIO_GCC_SP_TRIG_CBCR_IN)
#define HWIO_GCC_SP_TRIG_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_SP_TRIG_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_SP_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                               0x100000
#define HWIO_GCC_SP_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                   0x14
#define HWIO_GCC_SP_TRIG_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_SP_TRIG_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_SP_TRIG_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_SP_TRIG_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_SP_AT_CBCR_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0007201c)
#define HWIO_GCC_SP_AT_CBCR_RMSK                                                                   0x80100005
#define HWIO_GCC_SP_AT_CBCR_IN          \
        in_dword(HWIO_GCC_SP_AT_CBCR_ADDR)
#define HWIO_GCC_SP_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_AT_CBCR_ADDR, m)
#define HWIO_GCC_SP_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_AT_CBCR_ADDR,v)
#define HWIO_GCC_SP_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_AT_CBCR_ADDR,m,v,HWIO_GCC_SP_AT_CBCR_IN)
#define HWIO_GCC_SP_AT_CBCR_CLK_OFF_BMSK                                                           0x80000000
#define HWIO_GCC_SP_AT_CBCR_CLK_OFF_SHFT                                                                 0x1f
#define HWIO_GCC_SP_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                                 0x100000
#define HWIO_GCC_SP_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                     0x14
#define HWIO_GCC_SP_AT_CBCR_CLK_ARES_BMSK                                                                 0x4
#define HWIO_GCC_SP_AT_CBCR_CLK_ARES_SHFT                                                                 0x2
#define HWIO_GCC_SP_AT_CBCR_CLK_ENABLE_BMSK                                                               0x1
#define HWIO_GCC_SP_AT_CBCR_CLK_ENABLE_SHFT                                                               0x0

#define HWIO_GCC_NAV_BCR_ADDR                                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00015000)
#define HWIO_GCC_NAV_BCR_RMSK                                                                             0x1
#define HWIO_GCC_NAV_BCR_IN          \
        in_dword(HWIO_GCC_NAV_BCR_ADDR)
#define HWIO_GCC_NAV_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NAV_BCR_ADDR, m)
#define HWIO_GCC_NAV_BCR_OUT(v)      \
        out_dword(HWIO_GCC_NAV_BCR_ADDR,v)
#define HWIO_GCC_NAV_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NAV_BCR_ADDR,m,v,HWIO_GCC_NAV_BCR_IN)
#define HWIO_GCC_NAV_BCR_BLK_ARES_BMSK                                                                    0x1
#define HWIO_GCC_NAV_BCR_BLK_ARES_SHFT                                                                    0x0

#define HWIO_GCC_NAV_AXI_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00015004)
#define HWIO_GCC_NAV_AXI_CBCR_RMSK                                                                 0x80100005
#define HWIO_GCC_NAV_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_NAV_AXI_CBCR_ADDR)
#define HWIO_GCC_NAV_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NAV_AXI_CBCR_ADDR, m)
#define HWIO_GCC_NAV_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NAV_AXI_CBCR_ADDR,v)
#define HWIO_GCC_NAV_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NAV_AXI_CBCR_ADDR,m,v,HWIO_GCC_NAV_AXI_CBCR_IN)
#define HWIO_GCC_NAV_AXI_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_NAV_AXI_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_NAV_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                               0x100000
#define HWIO_GCC_NAV_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                   0x14
#define HWIO_GCC_NAV_AXI_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_NAV_AXI_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_NAV_AXI_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_NAV_AXI_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_AHB2PHY_SOUTH_BCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00007000)
#define HWIO_GCC_AHB2PHY_SOUTH_BCR_RMSK                                                                   0x1
#define HWIO_GCC_AHB2PHY_SOUTH_BCR_IN          \
        in_dword(HWIO_GCC_AHB2PHY_SOUTH_BCR_ADDR)
#define HWIO_GCC_AHB2PHY_SOUTH_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AHB2PHY_SOUTH_BCR_ADDR, m)
#define HWIO_GCC_AHB2PHY_SOUTH_BCR_OUT(v)      \
        out_dword(HWIO_GCC_AHB2PHY_SOUTH_BCR_ADDR,v)
#define HWIO_GCC_AHB2PHY_SOUTH_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AHB2PHY_SOUTH_BCR_ADDR,m,v,HWIO_GCC_AHB2PHY_SOUTH_BCR_IN)
#define HWIO_GCC_AHB2PHY_SOUTH_BCR_BLK_ARES_BMSK                                                          0x1
#define HWIO_GCC_AHB2PHY_SOUTH_BCR_BLK_ARES_SHFT                                                          0x0

#define HWIO_GCC_AHB2PHY_NORTH_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00007004)
#define HWIO_GCC_AHB2PHY_NORTH_CBCR_RMSK                                                           0x80000007
#define HWIO_GCC_AHB2PHY_NORTH_CBCR_IN          \
        in_dword(HWIO_GCC_AHB2PHY_NORTH_CBCR_ADDR)
#define HWIO_GCC_AHB2PHY_NORTH_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_AHB2PHY_NORTH_CBCR_ADDR, m)
#define HWIO_GCC_AHB2PHY_NORTH_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_AHB2PHY_NORTH_CBCR_ADDR,v)
#define HWIO_GCC_AHB2PHY_NORTH_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_AHB2PHY_NORTH_CBCR_ADDR,m,v,HWIO_GCC_AHB2PHY_NORTH_CBCR_IN)
#define HWIO_GCC_AHB2PHY_NORTH_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_AHB2PHY_NORTH_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_AHB2PHY_NORTH_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_AHB2PHY_NORTH_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_AHB2PHY_NORTH_CBCR_HW_CTL_BMSK                                                           0x2
#define HWIO_GCC_AHB2PHY_NORTH_CBCR_HW_CTL_SHFT                                                           0x1
#define HWIO_GCC_AHB2PHY_NORTH_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_AHB2PHY_NORTH_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00022000)
#define HWIO_GCC_CM_PHY_REFGEN1_BCR_RMSK                                                                  0x1
#define HWIO_GCC_CM_PHY_REFGEN1_BCR_IN          \
        in_dword(HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR)
#define HWIO_GCC_CM_PHY_REFGEN1_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR, m)
#define HWIO_GCC_CM_PHY_REFGEN1_BCR_OUT(v)      \
        out_dword(HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR,v)
#define HWIO_GCC_CM_PHY_REFGEN1_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR,m,v,HWIO_GCC_CM_PHY_REFGEN1_BCR_IN)
#define HWIO_GCC_CM_PHY_REFGEN1_BCR_BLK_ARES_BMSK                                                         0x1
#define HWIO_GCC_CM_PHY_REFGEN1_BCR_BLK_ARES_SHFT                                                         0x0

#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00022004)
#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_RMSK                                                          0x80000005
#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_IN          \
        in_dword(HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR)
#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR, m)
#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR,v)
#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR,m,v,HWIO_GCC_CM_PHY_REFGEN1_CBCR_IN)
#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_CLK_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_CM_PHY_REFGEN2_BCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00024000)
#define HWIO_GCC_CM_PHY_REFGEN2_BCR_RMSK                                                                  0x1
#define HWIO_GCC_CM_PHY_REFGEN2_BCR_IN          \
        in_dword(HWIO_GCC_CM_PHY_REFGEN2_BCR_ADDR)
#define HWIO_GCC_CM_PHY_REFGEN2_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CM_PHY_REFGEN2_BCR_ADDR, m)
#define HWIO_GCC_CM_PHY_REFGEN2_BCR_OUT(v)      \
        out_dword(HWIO_GCC_CM_PHY_REFGEN2_BCR_ADDR,v)
#define HWIO_GCC_CM_PHY_REFGEN2_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CM_PHY_REFGEN2_BCR_ADDR,m,v,HWIO_GCC_CM_PHY_REFGEN2_BCR_IN)
#define HWIO_GCC_CM_PHY_REFGEN2_BCR_BLK_ARES_BMSK                                                         0x1
#define HWIO_GCC_CM_PHY_REFGEN2_BCR_BLK_ARES_SHFT                                                         0x0

#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00024004)
#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_RMSK                                                          0x80000005
#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_IN          \
        in_dword(HWIO_GCC_CM_PHY_REFGEN2_CBCR_ADDR)
#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CM_PHY_REFGEN2_CBCR_ADDR, m)
#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_CM_PHY_REFGEN2_CBCR_ADDR,v)
#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CM_PHY_REFGEN2_CBCR_ADDR,m,v,HWIO_GCC_CM_PHY_REFGEN2_CBCR_IN)
#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_CLK_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_QSPI_BCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00024008)
#define HWIO_GCC_QSPI_BCR_RMSK                                                                            0x1
#define HWIO_GCC_QSPI_BCR_IN          \
        in_dword(HWIO_GCC_QSPI_BCR_ADDR)
#define HWIO_GCC_QSPI_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QSPI_BCR_ADDR, m)
#define HWIO_GCC_QSPI_BCR_OUT(v)      \
        out_dword(HWIO_GCC_QSPI_BCR_ADDR,v)
#define HWIO_GCC_QSPI_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QSPI_BCR_ADDR,m,v,HWIO_GCC_QSPI_BCR_IN)
#define HWIO_GCC_QSPI_BCR_BLK_ARES_BMSK                                                                   0x1
#define HWIO_GCC_QSPI_BCR_BLK_ARES_SHFT                                                                   0x0

#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0004b000)
#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_RMSK                                                    0x80100005
#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_ADDR)
#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_ADDR, m)
#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_ADDR,v)
#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_ADDR,m,v,HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_IN)
#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                  0x100000
#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                      0x14
#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_QSPI_CORE_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0004b004)
#define HWIO_GCC_QSPI_CORE_CBCR_RMSK                                                               0x80000005
#define HWIO_GCC_QSPI_CORE_CBCR_IN          \
        in_dword(HWIO_GCC_QSPI_CORE_CBCR_ADDR)
#define HWIO_GCC_QSPI_CORE_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QSPI_CORE_CBCR_ADDR, m)
#define HWIO_GCC_QSPI_CORE_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QSPI_CORE_CBCR_ADDR,v)
#define HWIO_GCC_QSPI_CORE_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QSPI_CORE_CBCR_ADDR,m,v,HWIO_GCC_QSPI_CORE_CBCR_IN)
#define HWIO_GCC_QSPI_CORE_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_QSPI_CORE_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_QSPI_CORE_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_QSPI_CORE_CBCR_CLK_ARES_SHFT                                                             0x2
#define HWIO_GCC_QSPI_CORE_CBCR_CLK_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_QSPI_CORE_CBCR_CLK_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_QSPI_CORE_CMD_RCGR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0004b008)
#define HWIO_GCC_QSPI_CORE_CMD_RCGR_RMSK                                                           0x80000013
#define HWIO_GCC_QSPI_CORE_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QSPI_CORE_CMD_RCGR_ADDR)
#define HWIO_GCC_QSPI_CORE_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QSPI_CORE_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QSPI_CORE_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QSPI_CORE_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QSPI_CORE_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QSPI_CORE_CMD_RCGR_ADDR,m,v,HWIO_GCC_QSPI_CORE_CMD_RCGR_IN)
#define HWIO_GCC_QSPI_CORE_CMD_RCGR_ROOT_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QSPI_CORE_CMD_RCGR_ROOT_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QSPI_CORE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                  0x10
#define HWIO_GCC_QSPI_CORE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                   0x4
#define HWIO_GCC_QSPI_CORE_CMD_RCGR_ROOT_EN_BMSK                                                          0x2
#define HWIO_GCC_QSPI_CORE_CMD_RCGR_ROOT_EN_SHFT                                                          0x1
#define HWIO_GCC_QSPI_CORE_CMD_RCGR_UPDATE_BMSK                                                           0x1
#define HWIO_GCC_QSPI_CORE_CMD_RCGR_UPDATE_SHFT                                                           0x0

#define HWIO_GCC_QSPI_CORE_CFG_RCGR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0004b00c)
#define HWIO_GCC_QSPI_CORE_CFG_RCGR_RMSK                                                             0x11071f
#define HWIO_GCC_QSPI_CORE_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QSPI_CORE_CFG_RCGR_ADDR)
#define HWIO_GCC_QSPI_CORE_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QSPI_CORE_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QSPI_CORE_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QSPI_CORE_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QSPI_CORE_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QSPI_CORE_CFG_RCGR_ADDR,m,v,HWIO_GCC_QSPI_CORE_CFG_RCGR_IN)
#define HWIO_GCC_QSPI_CORE_CFG_RCGR_HW_CLK_CONTROL_BMSK                                              0x100000
#define HWIO_GCC_QSPI_CORE_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                  0x14
#define HWIO_GCC_QSPI_CORE_CFG_RCGR_RCGLITE_DISABLE_BMSK                                              0x10000
#define HWIO_GCC_QSPI_CORE_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                 0x10
#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_SEL_BMSK                                                        0x700
#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_SEL_SHFT                                                          0x8
#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_BMSK                                                         0x1f
#define HWIO_GCC_QSPI_CORE_CFG_RCGR_SRC_DIV_SHFT                                                          0x0

#define HWIO_GCC_NPU_BCR_ADDR                                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d000)
#define HWIO_GCC_NPU_BCR_RMSK                                                                             0x1
#define HWIO_GCC_NPU_BCR_IN          \
        in_dword(HWIO_GCC_NPU_BCR_ADDR)
#define HWIO_GCC_NPU_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_BCR_ADDR, m)
#define HWIO_GCC_NPU_BCR_OUT(v)      \
        out_dword(HWIO_GCC_NPU_BCR_ADDR,v)
#define HWIO_GCC_NPU_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_BCR_ADDR,m,v,HWIO_GCC_NPU_BCR_IN)
#define HWIO_GCC_NPU_BCR_BLK_ARES_BMSK                                                                    0x1
#define HWIO_GCC_NPU_BCR_BLK_ARES_SHFT                                                                    0x0

#define HWIO_GCC_NPU_CFG_AHB_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d004)
#define HWIO_GCC_NPU_CFG_AHB_CBCR_RMSK                                                             0x80100007
#define HWIO_GCC_NPU_CFG_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_NPU_CFG_AHB_CBCR_ADDR)
#define HWIO_GCC_NPU_CFG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_CFG_AHB_CBCR_ADDR, m)
#define HWIO_GCC_NPU_CFG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NPU_CFG_AHB_CBCR_ADDR,v)
#define HWIO_GCC_NPU_CFG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_NPU_CFG_AHB_CBCR_IN)
#define HWIO_GCC_NPU_CFG_AHB_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_NPU_CFG_AHB_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_NPU_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                           0x100000
#define HWIO_GCC_NPU_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                               0x14
#define HWIO_GCC_NPU_CFG_AHB_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_NPU_CFG_AHB_CBCR_CLK_ARES_SHFT                                                           0x2
#define HWIO_GCC_NPU_CFG_AHB_CBCR_HW_CTL_BMSK                                                             0x2
#define HWIO_GCC_NPU_CFG_AHB_CBCR_HW_CTL_SHFT                                                             0x1
#define HWIO_GCC_NPU_CFG_AHB_CBCR_CLK_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_NPU_CFG_AHB_CBCR_CLK_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_NPU_AXI_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d008)
#define HWIO_GCC_NPU_AXI_CBCR_RMSK                                                                 0x80100005
#define HWIO_GCC_NPU_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_NPU_AXI_CBCR_ADDR)
#define HWIO_GCC_NPU_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_AXI_CBCR_ADDR, m)
#define HWIO_GCC_NPU_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NPU_AXI_CBCR_ADDR,v)
#define HWIO_GCC_NPU_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_AXI_CBCR_ADDR,m,v,HWIO_GCC_NPU_AXI_CBCR_IN)
#define HWIO_GCC_NPU_AXI_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_NPU_AXI_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_NPU_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                               0x100000
#define HWIO_GCC_NPU_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                   0x14
#define HWIO_GCC_NPU_AXI_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_NPU_AXI_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_NPU_AXI_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_NPU_AXI_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_NPU_DMA_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d00c)
#define HWIO_GCC_NPU_DMA_CBCR_RMSK                                                                 0x80100005
#define HWIO_GCC_NPU_DMA_CBCR_IN          \
        in_dword(HWIO_GCC_NPU_DMA_CBCR_ADDR)
#define HWIO_GCC_NPU_DMA_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_DMA_CBCR_ADDR, m)
#define HWIO_GCC_NPU_DMA_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NPU_DMA_CBCR_ADDR,v)
#define HWIO_GCC_NPU_DMA_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_DMA_CBCR_ADDR,m,v,HWIO_GCC_NPU_DMA_CBCR_IN)
#define HWIO_GCC_NPU_DMA_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_NPU_DMA_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_NPU_DMA_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                               0x100000
#define HWIO_GCC_NPU_DMA_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                   0x14
#define HWIO_GCC_NPU_DMA_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_NPU_DMA_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_NPU_DMA_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_NPU_DMA_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_NPU_TRIG_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d010)
#define HWIO_GCC_NPU_TRIG_CBCR_RMSK                                                                0x80100005
#define HWIO_GCC_NPU_TRIG_CBCR_IN          \
        in_dword(HWIO_GCC_NPU_TRIG_CBCR_ADDR)
#define HWIO_GCC_NPU_TRIG_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_TRIG_CBCR_ADDR, m)
#define HWIO_GCC_NPU_TRIG_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NPU_TRIG_CBCR_ADDR,v)
#define HWIO_GCC_NPU_TRIG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_TRIG_CBCR_ADDR,m,v,HWIO_GCC_NPU_TRIG_CBCR_IN)
#define HWIO_GCC_NPU_TRIG_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_NPU_TRIG_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_NPU_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_NPU_TRIG_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_NPU_TRIG_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_NPU_TRIG_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_NPU_TRIG_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_NPU_TRIG_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_NPU_AT_CBCR_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d014)
#define HWIO_GCC_NPU_AT_CBCR_RMSK                                                                  0x80100005
#define HWIO_GCC_NPU_AT_CBCR_IN          \
        in_dword(HWIO_GCC_NPU_AT_CBCR_ADDR)
#define HWIO_GCC_NPU_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_AT_CBCR_ADDR, m)
#define HWIO_GCC_NPU_AT_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NPU_AT_CBCR_ADDR,v)
#define HWIO_GCC_NPU_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_AT_CBCR_ADDR,m,v,HWIO_GCC_NPU_AT_CBCR_IN)
#define HWIO_GCC_NPU_AT_CBCR_CLK_OFF_BMSK                                                          0x80000000
#define HWIO_GCC_NPU_AT_CBCR_CLK_OFF_SHFT                                                                0x1f
#define HWIO_GCC_NPU_AT_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                                0x100000
#define HWIO_GCC_NPU_AT_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                    0x14
#define HWIO_GCC_NPU_AT_CBCR_CLK_ARES_BMSK                                                                0x4
#define HWIO_GCC_NPU_AT_CBCR_CLK_ARES_SHFT                                                                0x2
#define HWIO_GCC_NPU_AT_CBCR_CLK_ENABLE_BMSK                                                              0x1
#define HWIO_GCC_NPU_AT_CBCR_CLK_ENABLE_SHFT                                                              0x0

#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF0_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d034)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF0_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF0_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF0_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF0_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF0_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF1_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d038)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF1_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF1_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF1_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF1_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF1_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF2_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d03c)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF2_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF2_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF2_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF2_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF2_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF3_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d040)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF3_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF3_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF3_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF3_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF3_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF4_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d044)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF4_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF4_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF4_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF4_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF4_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF5_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d048)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF5_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF5_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF5_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF5_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF5_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF6_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d04c)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF6_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF6_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF6_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF6_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF6_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF7_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d050)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF7_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF7_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF7_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF7_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF7_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF8_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d054)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF8_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF8_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF8_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF8_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF8_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF9_DFSR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d058)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF9_DFSR_RMSK                                                  0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF9_DFSR_SRC_SEL_BMSK                                          0x700
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF9_DFSR_SRC_SEL_SHFT                                            0x8
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF9_DFSR_SRC_DIV_BMSK                                           0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF9_DFSR_SRC_DIV_SHFT                                            0x0

#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF10_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d05c)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF10_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF10_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF10_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF10_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF10_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF11_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d060)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF11_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF11_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF11_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF11_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF11_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF12_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d064)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF12_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF12_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF12_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF12_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF12_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF13_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d068)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF13_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF13_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF13_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF13_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF13_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF14_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d06c)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF14_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF14_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF14_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF14_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF14_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF15_DFSR_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d070)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF15_DFSR_RMSK                                                 0x71f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF15_DFSR_SRC_SEL_BMSK                                         0x700
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF15_DFSR_SRC_SEL_SHFT                                           0x8
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF15_DFSR_SRC_DIV_BMSK                                          0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_NPU_DMA_PERF15_DFSR_SRC_DIV_SHFT                                           0x0

#define HWIO_GCC_NPU_DMA_CMD_RCGR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d018)
#define HWIO_GCC_NPU_DMA_CMD_RCGR_RMSK                                                             0x80000013
#define HWIO_GCC_NPU_DMA_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_NPU_DMA_CMD_RCGR_ADDR)
#define HWIO_GCC_NPU_DMA_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_DMA_CMD_RCGR_ADDR, m)
#define HWIO_GCC_NPU_DMA_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_NPU_DMA_CMD_RCGR_ADDR,v)
#define HWIO_GCC_NPU_DMA_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_DMA_CMD_RCGR_ADDR,m,v,HWIO_GCC_NPU_DMA_CMD_RCGR_IN)
#define HWIO_GCC_NPU_DMA_CMD_RCGR_ROOT_OFF_BMSK                                                    0x80000000
#define HWIO_GCC_NPU_DMA_CMD_RCGR_ROOT_OFF_SHFT                                                          0x1f
#define HWIO_GCC_NPU_DMA_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                    0x10
#define HWIO_GCC_NPU_DMA_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                     0x4
#define HWIO_GCC_NPU_DMA_CMD_RCGR_ROOT_EN_BMSK                                                            0x2
#define HWIO_GCC_NPU_DMA_CMD_RCGR_ROOT_EN_SHFT                                                            0x1
#define HWIO_GCC_NPU_DMA_CMD_RCGR_UPDATE_BMSK                                                             0x1
#define HWIO_GCC_NPU_DMA_CMD_RCGR_UPDATE_SHFT                                                             0x0

#define HWIO_GCC_NPU_DMA_CFG_RCGR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d01c)
#define HWIO_GCC_NPU_DMA_CFG_RCGR_RMSK                                                               0x11071f
#define HWIO_GCC_NPU_DMA_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_NPU_DMA_CFG_RCGR_ADDR)
#define HWIO_GCC_NPU_DMA_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_DMA_CFG_RCGR_ADDR, m)
#define HWIO_GCC_NPU_DMA_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_NPU_DMA_CFG_RCGR_ADDR,v)
#define HWIO_GCC_NPU_DMA_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_DMA_CFG_RCGR_ADDR,m,v,HWIO_GCC_NPU_DMA_CFG_RCGR_IN)
#define HWIO_GCC_NPU_DMA_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                0x100000
#define HWIO_GCC_NPU_DMA_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                    0x14
#define HWIO_GCC_NPU_DMA_CFG_RCGR_RCGLITE_DISABLE_BMSK                                                0x10000
#define HWIO_GCC_NPU_DMA_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                   0x10
#define HWIO_GCC_NPU_DMA_CFG_RCGR_SRC_SEL_BMSK                                                          0x700
#define HWIO_GCC_NPU_DMA_CFG_RCGR_SRC_SEL_SHFT                                                            0x8
#define HWIO_GCC_NPU_DMA_CFG_RCGR_SRC_DIV_BMSK                                                           0x1f
#define HWIO_GCC_NPU_DMA_CFG_RCGR_SRC_DIV_SHFT                                                            0x0

#define HWIO_GCC_NPU_DMA_DCD_CDIV_DCDR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d144)
#define HWIO_GCC_NPU_DMA_DCD_CDIV_DCDR_RMSK                                                               0x1
#define HWIO_GCC_NPU_DMA_DCD_CDIV_DCDR_IN          \
        in_dword(HWIO_GCC_NPU_DMA_DCD_CDIV_DCDR_ADDR)
#define HWIO_GCC_NPU_DMA_DCD_CDIV_DCDR_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_DMA_DCD_CDIV_DCDR_ADDR, m)
#define HWIO_GCC_NPU_DMA_DCD_CDIV_DCDR_OUT(v)      \
        out_dword(HWIO_GCC_NPU_DMA_DCD_CDIV_DCDR_ADDR,v)
#define HWIO_GCC_NPU_DMA_DCD_CDIV_DCDR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_DMA_DCD_CDIV_DCDR_ADDR,m,v,HWIO_GCC_NPU_DMA_DCD_CDIV_DCDR_IN)
#define HWIO_GCC_NPU_DMA_DCD_CDIV_DCDR_DCD_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_NPU_DMA_DCD_CDIV_DCDR_DCD_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_PLL0_MAIN_DIV_CDIVR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d148)
#define HWIO_GCC_PLL0_MAIN_DIV_CDIVR_RMSK                                                                 0x3
#define HWIO_GCC_PLL0_MAIN_DIV_CDIVR_IN          \
        in_dword(HWIO_GCC_PLL0_MAIN_DIV_CDIVR_ADDR)
#define HWIO_GCC_PLL0_MAIN_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_PLL0_MAIN_DIV_CDIVR_ADDR, m)
#define HWIO_GCC_PLL0_MAIN_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_PLL0_MAIN_DIV_CDIVR_ADDR,v)
#define HWIO_GCC_PLL0_MAIN_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PLL0_MAIN_DIV_CDIVR_ADDR,m,v,HWIO_GCC_PLL0_MAIN_DIV_CDIVR_IN)
#define HWIO_GCC_PLL0_MAIN_DIV_CDIVR_CLK_DIV_BMSK                                                         0x3
#define HWIO_GCC_PLL0_MAIN_DIV_CDIVR_CLK_DIV_SHFT                                                         0x0

#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e000)
#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_RMSK                                                                 0x1
#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAPPER_2_BCR_ADDR)
#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAPPER_2_BCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAPPER_2_BCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAPPER_2_BCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAPPER_2_BCR_IN)
#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_BLK_ARES_BMSK                                                        0x1
#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_BLK_ARES_SHFT                                                        0x0

#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e004)
#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_RMSK                                                      0x80100004
#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                    0x100000
#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                        0x14
#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_CLK_ARES_SHFT                                                    0x2

#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e008)
#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_RMSK                                                      0x80100006
#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                    0x100000
#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                        0x14
#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_HW_CTL_BMSK                                                      0x2
#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_HW_CTL_SHFT                                                      0x1

#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00023270)
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_RMSK                                                        0x80107ff4
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                      0x100000
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                          0x14
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_CORE_ON_BMSK                                          0x4000
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_CORE_ON_SHFT                                             0xe
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                        0x2000
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                           0xd
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                       0x1000
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                          0xc
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_WAKEUP_BMSK                                                      0xf00
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_WAKEUP_SHFT                                                        0x8
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_SLEEP_BMSK                                                        0xf0
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_SLEEP_SHFT                                                         0x4
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_CLK_ARES_SHFT                                                      0x2

#define HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00023274)
#define HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_RMSK                                                              0x3
#define HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_IN)
#define HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_CLK_DIV_BMSK                                                      0x3
#define HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_CLK_DIV_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00023278)
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_RMSK                                                     0x80107ff4
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                   0x100000
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                       0x14
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_CORE_ON_BMSK                                       0x4000
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_CORE_ON_SHFT                                          0xe
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                     0x2000
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                        0xd
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                    0x1000
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                       0xc
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_WAKEUP_BMSK                                                   0xf00
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_WAKEUP_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_SLEEP_BMSK                                                     0xf0
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_SLEEP_SHFT                                                      0x4
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_CLK_ARES_SHFT                                                   0x2

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00023298)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0002329c)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000232a0)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000232a4)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000232a8)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000232ac)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000232b0)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000232b4)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000232b8)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_ADDR                            (GCC_CLK_CTL_REG_REG_BASE      + 0x000232bc)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_RMSK                                 0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_SEL_BMSK                         0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_SEL_SHFT                           0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_BMSK                          0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_SRC_DIV_SHFT                           0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000232c0)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000232c4)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000232c8)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000232cc)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000232d0)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000232d4)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_RMSK                                0x71f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_SEL_BMSK                        0x700
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_SEL_SHFT                          0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_BMSK                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_SRC_DIV_SHFT                          0x0

#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0002327c)
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_RMSK                                                 0x80000013
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ROOT_OFF_BMSK                                        0x80000000
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ROOT_OFF_SHFT                                              0x1f
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                        0x10
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                         0x4
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ROOT_EN_BMSK                                                0x2
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ROOT_EN_SHFT                                                0x1
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_UPDATE_BMSK                                                 0x1
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_UPDATE_SHFT                                                 0x0

#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00023280)
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_RMSK                                                   0x11071f
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_HW_CLK_CONTROL_BMSK                                    0x100000
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_HW_CLK_CONTROL_SHFT                                        0x14
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_RCGLITE_DISABLE_BMSK                                    0x10000
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_RCGLITE_DISABLE_SHFT                                       0x10
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_SEL_BMSK                                              0x700
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_SEL_SHFT                                                0x8
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_BMSK                                               0x1f
#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_SRC_DIV_SHFT                                                0x0

#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e00c)
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S0_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S0_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S0_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S0_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e024)
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e02c)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e030)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e034)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e038)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e03c)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e040)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e044)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e048)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e06c)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e070)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e074)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e078)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e07c)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e080)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e084)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e088)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e0ac)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e0b0)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e0b4)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e0b8)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e0bc)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e0c0)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e0c4)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e0c8)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e0ec)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e0f0)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e0f4)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e0f8)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e0fc)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e100)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e104)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e108)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e010)
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e014)
#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP2_S0_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e018)
#define HWIO_GCC_QUPV3_WRAP2_S0_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S0_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S0_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S0_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S0_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S0_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S0_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S0_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S0_M_IN)
#define HWIO_GCC_QUPV3_WRAP2_S0_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_S0_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_S0_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e01c)
#define HWIO_GCC_QUPV3_WRAP2_S0_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S0_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S0_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S0_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S0_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S0_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S0_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S0_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S0_N_IN)
#define HWIO_GCC_QUPV3_WRAP2_S0_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP2_S0_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP2_S0_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e020)
#define HWIO_GCC_QUPV3_WRAP2_S0_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S0_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S0_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S0_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S0_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S0_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S0_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S0_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S0_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S0_D_IN)
#define HWIO_GCC_QUPV3_WRAP2_S0_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP2_S0_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e13c)
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S1_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S1_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S1_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S1_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e154)
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e15c)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e160)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e164)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e168)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e16c)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e170)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e174)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e178)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e19c)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e1a0)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e1a4)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e1a8)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e1ac)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e1b0)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e1b4)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e1b8)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e1dc)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e1e0)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e1e4)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e1e8)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e1ec)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e1f0)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e1f4)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e1f8)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e21c)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e220)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e224)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e228)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e22c)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e230)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e234)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e238)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e140)
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e144)
#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP2_S1_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e148)
#define HWIO_GCC_QUPV3_WRAP2_S1_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S1_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S1_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S1_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S1_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S1_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S1_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S1_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S1_M_IN)
#define HWIO_GCC_QUPV3_WRAP2_S1_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_S1_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_S1_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e14c)
#define HWIO_GCC_QUPV3_WRAP2_S1_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S1_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S1_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S1_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S1_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S1_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S1_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S1_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S1_N_IN)
#define HWIO_GCC_QUPV3_WRAP2_S1_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP2_S1_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP2_S1_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e150)
#define HWIO_GCC_QUPV3_WRAP2_S1_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S1_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S1_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S1_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S1_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S1_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S1_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S1_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S1_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S1_D_IN)
#define HWIO_GCC_QUPV3_WRAP2_S1_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP2_S1_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e26c)
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S2_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S2_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S2_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S2_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e284)
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e28c)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e290)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e294)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e298)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e29c)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e2a0)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e2a4)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e2a8)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e2cc)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e2d0)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e2d4)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e2d8)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e2dc)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e2e0)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e2e4)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e2e8)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e30c)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e310)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e314)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e318)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e31c)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e320)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e324)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e328)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e34c)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e350)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e354)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e358)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e35c)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e360)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e364)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e368)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e270)
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e274)
#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP2_S2_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e278)
#define HWIO_GCC_QUPV3_WRAP2_S2_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S2_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S2_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S2_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S2_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S2_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S2_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S2_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S2_M_IN)
#define HWIO_GCC_QUPV3_WRAP2_S2_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_S2_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_S2_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e27c)
#define HWIO_GCC_QUPV3_WRAP2_S2_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S2_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S2_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S2_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S2_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S2_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S2_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S2_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S2_N_IN)
#define HWIO_GCC_QUPV3_WRAP2_S2_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP2_S2_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP2_S2_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e280)
#define HWIO_GCC_QUPV3_WRAP2_S2_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S2_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S2_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S2_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S2_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S2_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S2_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S2_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S2_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S2_D_IN)
#define HWIO_GCC_QUPV3_WRAP2_S2_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP2_S2_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e39c)
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S3_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S3_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S3_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S3_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e3b4)
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e3bc)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e3c0)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e3c4)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e3c8)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e3cc)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e3d0)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e3d4)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e3d8)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e3fc)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e400)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e404)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e408)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e40c)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e410)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e414)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e418)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e43c)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e440)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e444)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e448)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e44c)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e450)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e454)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e458)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e47c)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e480)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e484)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e488)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e48c)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e490)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e494)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e498)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e3a0)
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e3a4)
#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP2_S3_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e3a8)
#define HWIO_GCC_QUPV3_WRAP2_S3_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S3_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S3_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S3_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S3_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S3_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S3_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S3_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S3_M_IN)
#define HWIO_GCC_QUPV3_WRAP2_S3_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_S3_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_S3_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e3ac)
#define HWIO_GCC_QUPV3_WRAP2_S3_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S3_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S3_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S3_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S3_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S3_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S3_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S3_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S3_N_IN)
#define HWIO_GCC_QUPV3_WRAP2_S3_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP2_S3_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP2_S3_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e3b0)
#define HWIO_GCC_QUPV3_WRAP2_S3_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S3_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S3_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S3_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S3_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S3_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S3_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S3_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S3_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S3_D_IN)
#define HWIO_GCC_QUPV3_WRAP2_S3_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP2_S3_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e4cc)
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S4_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S4_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S4_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S4_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e4e4)
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e4ec)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e4f0)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e4f4)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e4f8)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e4fc)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e500)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e504)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e508)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e52c)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e530)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e534)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e538)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e53c)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e540)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e544)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e548)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e56c)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e570)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e574)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e578)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e57c)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e580)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e584)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e588)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e5ac)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e5b0)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e5b4)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e5b8)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e5bc)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e5c0)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e5c4)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e5c8)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e4d0)
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e4d4)
#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP2_S4_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e4d8)
#define HWIO_GCC_QUPV3_WRAP2_S4_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S4_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S4_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S4_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S4_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S4_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S4_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S4_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S4_M_IN)
#define HWIO_GCC_QUPV3_WRAP2_S4_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_S4_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_S4_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e4dc)
#define HWIO_GCC_QUPV3_WRAP2_S4_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S4_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S4_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S4_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S4_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S4_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S4_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S4_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S4_N_IN)
#define HWIO_GCC_QUPV3_WRAP2_S4_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP2_S4_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP2_S4_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e4e0)
#define HWIO_GCC_QUPV3_WRAP2_S4_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S4_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S4_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S4_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S4_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S4_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S4_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S4_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S4_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S4_D_IN)
#define HWIO_GCC_QUPV3_WRAP2_S4_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP2_S4_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e5fc)
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_RMSK                                                          0x80007ff4
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S5_CBCR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_CBCR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S5_CBCR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S5_CBCR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S5_CBCR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_CLK_ARES_SHFT                                                        0x2

#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e614)
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_RMSK                                                         0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_RCG_SW_CTRL_BMSK                                             0x8000
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_RCG_SW_CTRL_SHFT                                                0xf
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_SW_PERF_STATE_BMSK                                           0x7800
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_SW_PERF_STATE_SHFT                                              0xb
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_SW_OVERRIDE_BMSK                                              0x400
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_SW_OVERRIDE_SHFT                                                0xa
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_PERF_STATE_UPDATE_STATUS_BMSK                                 0x200
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_PERF_STATE_UPDATE_STATUS_SHFT                                   0x9
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_DFS_FSM_STATE_BMSK                                            0x1c0
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_DFS_FSM_STATE_SHFT                                              0x6
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_HW_CLK_CONTROL_BMSK                                            0x20
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_HW_CLK_CONTROL_SHFT                                             0x5
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_CURR_PERF_STATE_BMSK                                           0x1e
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_CURR_PERF_STATE_SHFT                                            0x1
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_DFS_EN_BMSK                                                     0x1
#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_DFS_EN_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e61c)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e620)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e624)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e628)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e62c)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e630)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e634)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e638)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_RMSK                                        0x371f
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_MODE_BMSK                                   0x3000
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_MODE_SHFT                                      0xc
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_SEL_BMSK                                 0x700
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_SEL_SHFT                                   0x8
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_BMSK                                  0x1f
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_SRC_DIV_SHFT                                   0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e65c)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e660)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e664)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e668)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e66c)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e670)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e674)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e678)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_M_BMSK                                    0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_M_SHFT                                       0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e69c)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e6a0)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e6a4)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e6a8)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e6ac)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e6b0)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e6b4)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e6b8)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_NOT_N_MINUS_M_BMSK                        0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_NOT_N_MINUS_M_SHFT                           0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e6dc)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e6e0)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e6e4)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e6e8)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e6ec)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e6f0)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e6f4)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e6f8)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_RMSK                                      0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_IN)
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_NOT_2D_BMSK                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_NOT_2D_SHFT                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e600)
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_RMSK                                                      0x800000f3
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ROOT_OFF_BMSK                                             0x80000000
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ROOT_OFF_SHFT                                                   0x1f
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_DIRTY_D_BMSK                                                    0x80
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_DIRTY_D_SHFT                                                     0x7
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_DIRTY_N_BMSK                                                    0x40
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_DIRTY_N_SHFT                                                     0x6
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_DIRTY_M_BMSK                                                    0x20
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_DIRTY_M_SHFT                                                     0x5
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                             0x10
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                              0x4
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ROOT_EN_BMSK                                                     0x2
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ROOT_EN_SHFT                                                     0x1
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_UPDATE_BMSK                                                      0x1
#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_UPDATE_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e604)
#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_RMSK                                                        0x10371f
#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_IN)
#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_HW_CLK_CONTROL_BMSK                                         0x100000
#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_HW_CLK_CONTROL_SHFT                                             0x14
#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_MODE_BMSK                                                     0x3000
#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_MODE_SHFT                                                        0xc
#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_SEL_BMSK                                                   0x700
#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_SEL_SHFT                                                     0x8
#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_BMSK                                                    0x1f
#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_SRC_DIV_SHFT                                                     0x0

#define HWIO_GCC_QUPV3_WRAP2_S5_M_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e608)
#define HWIO_GCC_QUPV3_WRAP2_S5_M_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S5_M_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S5_M_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S5_M_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_M_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S5_M_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S5_M_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S5_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S5_M_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S5_M_IN)
#define HWIO_GCC_QUPV3_WRAP2_S5_M_M_BMSK                                                               0xffff
#define HWIO_GCC_QUPV3_WRAP2_S5_M_M_SHFT                                                                  0x0

#define HWIO_GCC_QUPV3_WRAP2_S5_N_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e60c)
#define HWIO_GCC_QUPV3_WRAP2_S5_N_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S5_N_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S5_N_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S5_N_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_N_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S5_N_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S5_N_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S5_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S5_N_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S5_N_IN)
#define HWIO_GCC_QUPV3_WRAP2_S5_N_NOT_N_MINUS_M_BMSK                                                   0xffff
#define HWIO_GCC_QUPV3_WRAP2_S5_N_NOT_N_MINUS_M_SHFT                                                      0x0

#define HWIO_GCC_QUPV3_WRAP2_S5_D_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0001e610)
#define HWIO_GCC_QUPV3_WRAP2_S5_D_RMSK                                                                 0xffff
#define HWIO_GCC_QUPV3_WRAP2_S5_D_IN          \
        in_dword(HWIO_GCC_QUPV3_WRAP2_S5_D_ADDR)
#define HWIO_GCC_QUPV3_WRAP2_S5_D_INM(m)      \
        in_dword_masked(HWIO_GCC_QUPV3_WRAP2_S5_D_ADDR, m)
#define HWIO_GCC_QUPV3_WRAP2_S5_D_OUT(v)      \
        out_dword(HWIO_GCC_QUPV3_WRAP2_S5_D_ADDR,v)
#define HWIO_GCC_QUPV3_WRAP2_S5_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_QUPV3_WRAP2_S5_D_ADDR,m,v,HWIO_GCC_QUPV3_WRAP2_S5_D_IN)
#define HWIO_GCC_QUPV3_WRAP2_S5_D_NOT_2D_BMSK                                                          0xffff
#define HWIO_GCC_QUPV3_WRAP2_S5_D_NOT_2D_SHFT                                                             0x0

#define HWIO_GCC_RBCPR_MMCX_BCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0000d000)
#define HWIO_GCC_RBCPR_MMCX_BCR_RMSK                                                                      0x1
#define HWIO_GCC_RBCPR_MMCX_BCR_IN          \
        in_dword(HWIO_GCC_RBCPR_MMCX_BCR_ADDR)
#define HWIO_GCC_RBCPR_MMCX_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_RBCPR_MMCX_BCR_ADDR, m)
#define HWIO_GCC_RBCPR_MMCX_BCR_OUT(v)      \
        out_dword(HWIO_GCC_RBCPR_MMCX_BCR_ADDR,v)
#define HWIO_GCC_RBCPR_MMCX_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RBCPR_MMCX_BCR_ADDR,m,v,HWIO_GCC_RBCPR_MMCX_BCR_IN)
#define HWIO_GCC_RBCPR_MMCX_BCR_BLK_ARES_BMSK                                                             0x1
#define HWIO_GCC_RBCPR_MMCX_BCR_BLK_ARES_SHFT                                                             0x0

#define HWIO_GCC_RBCPR_MMCX_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0000d004)
#define HWIO_GCC_RBCPR_MMCX_CBCR_RMSK                                                              0x80000005
#define HWIO_GCC_RBCPR_MMCX_CBCR_IN          \
        in_dword(HWIO_GCC_RBCPR_MMCX_CBCR_ADDR)
#define HWIO_GCC_RBCPR_MMCX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_RBCPR_MMCX_CBCR_ADDR, m)
#define HWIO_GCC_RBCPR_MMCX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_RBCPR_MMCX_CBCR_ADDR,v)
#define HWIO_GCC_RBCPR_MMCX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RBCPR_MMCX_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_MMCX_CBCR_IN)
#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_ARES_SHFT                                                            0x2
#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_ENABLE_BMSK                                                          0x1
#define HWIO_GCC_RBCPR_MMCX_CBCR_CLK_ENABLE_SHFT                                                          0x0

#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000d008)
#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_RMSK                                                          0x80100007
#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_RBCPR_MMCX_AHB_CBCR_ADDR)
#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_RBCPR_MMCX_AHB_CBCR_ADDR, m)
#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_RBCPR_MMCX_AHB_CBCR_ADDR,v)
#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RBCPR_MMCX_AHB_CBCR_ADDR,m,v,HWIO_GCC_RBCPR_MMCX_AHB_CBCR_IN)
#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_HW_CTL_BMSK                                                          0x2
#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_HW_CTL_SHFT                                                          0x1
#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_CLK_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000d00c)
#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_RMSK                                                          0x80000013
#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ADDR)
#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ADDR, m)
#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ADDR,v)
#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_MMCX_CMD_RCGR_IN)
#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ROOT_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ROOT_OFF_SHFT                                                       0x1f
#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                 0x10
#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                  0x4
#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ROOT_EN_BMSK                                                         0x2
#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ROOT_EN_SHFT                                                         0x1
#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_UPDATE_BMSK                                                          0x1
#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_UPDATE_SHFT                                                          0x0

#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000d010)
#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_RMSK                                                            0x11071f
#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_RBCPR_MMCX_CFG_RCGR_ADDR)
#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_RBCPR_MMCX_CFG_RCGR_ADDR, m)
#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_RBCPR_MMCX_CFG_RCGR_ADDR,v)
#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RBCPR_MMCX_CFG_RCGR_ADDR,m,v,HWIO_GCC_RBCPR_MMCX_CFG_RCGR_IN)
#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_HW_CLK_CONTROL_BMSK                                             0x100000
#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                 0x14
#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_RCGLITE_DISABLE_BMSK                                             0x10000
#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                0x10
#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_SEL_BMSK                                                       0x700
#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_SEL_SHFT                                                         0x8
#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_BMSK                                                        0x1f
#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_SRC_DIV_SHFT                                                         0x0

#define HWIO_GCC_PCIE_2_BCR_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00006000)
#define HWIO_GCC_PCIE_2_BCR_RMSK                                                                          0x1
#define HWIO_GCC_PCIE_2_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_2_BCR_ADDR)
#define HWIO_GCC_PCIE_2_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_BCR_ADDR, m)
#define HWIO_GCC_PCIE_2_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_BCR_ADDR,v)
#define HWIO_GCC_PCIE_2_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_BCR_ADDR,m,v,HWIO_GCC_PCIE_2_BCR_IN)
#define HWIO_GCC_PCIE_2_BCR_BLK_ARES_BMSK                                                                 0x1
#define HWIO_GCC_PCIE_2_BCR_BLK_ARES_SHFT                                                                 0x0

#define HWIO_GCC_PCIE_2_GDSCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00006004)
#define HWIO_GCC_PCIE_2_GDSCR_RMSK                                                                 0xf8ffffff
#define HWIO_GCC_PCIE_2_GDSCR_IN          \
        in_dword(HWIO_GCC_PCIE_2_GDSCR_ADDR)
#define HWIO_GCC_PCIE_2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_GDSCR_ADDR, m)
#define HWIO_GCC_PCIE_2_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_GDSCR_ADDR,v)
#define HWIO_GCC_PCIE_2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_2_GDSCR_IN)
#define HWIO_GCC_PCIE_2_GDSCR_PWR_ON_BMSK                                                          0x80000000
#define HWIO_GCC_PCIE_2_GDSCR_PWR_ON_SHFT                                                                0x1f
#define HWIO_GCC_PCIE_2_GDSCR_GDSC_STATE_BMSK                                                      0x78000000
#define HWIO_GCC_PCIE_2_GDSCR_GDSC_STATE_SHFT                                                            0x1b
#define HWIO_GCC_PCIE_2_GDSCR_EN_REST_WAIT_BMSK                                                      0xf00000
#define HWIO_GCC_PCIE_2_GDSCR_EN_REST_WAIT_SHFT                                                          0x14
#define HWIO_GCC_PCIE_2_GDSCR_EN_FEW_WAIT_BMSK                                                        0xf0000
#define HWIO_GCC_PCIE_2_GDSCR_EN_FEW_WAIT_SHFT                                                           0x10
#define HWIO_GCC_PCIE_2_GDSCR_CLK_DIS_WAIT_BMSK                                                        0xf000
#define HWIO_GCC_PCIE_2_GDSCR_CLK_DIS_WAIT_SHFT                                                           0xc
#define HWIO_GCC_PCIE_2_GDSCR_RETAIN_FF_ENABLE_BMSK                                                     0x800
#define HWIO_GCC_PCIE_2_GDSCR_RETAIN_FF_ENABLE_SHFT                                                       0xb
#define HWIO_GCC_PCIE_2_GDSCR_RESTORE_BMSK                                                              0x400
#define HWIO_GCC_PCIE_2_GDSCR_RESTORE_SHFT                                                                0xa
#define HWIO_GCC_PCIE_2_GDSCR_SAVE_BMSK                                                                 0x200
#define HWIO_GCC_PCIE_2_GDSCR_SAVE_SHFT                                                                   0x9
#define HWIO_GCC_PCIE_2_GDSCR_RETAIN_BMSK                                                               0x100
#define HWIO_GCC_PCIE_2_GDSCR_RETAIN_SHFT                                                                 0x8
#define HWIO_GCC_PCIE_2_GDSCR_EN_REST_BMSK                                                               0x80
#define HWIO_GCC_PCIE_2_GDSCR_EN_REST_SHFT                                                                0x7
#define HWIO_GCC_PCIE_2_GDSCR_EN_FEW_BMSK                                                                0x40
#define HWIO_GCC_PCIE_2_GDSCR_EN_FEW_SHFT                                                                 0x6
#define HWIO_GCC_PCIE_2_GDSCR_CLAMP_IO_BMSK                                                              0x20
#define HWIO_GCC_PCIE_2_GDSCR_CLAMP_IO_SHFT                                                               0x5
#define HWIO_GCC_PCIE_2_GDSCR_CLK_DISABLE_BMSK                                                           0x10
#define HWIO_GCC_PCIE_2_GDSCR_CLK_DISABLE_SHFT                                                            0x4
#define HWIO_GCC_PCIE_2_GDSCR_PD_ARES_BMSK                                                                0x8
#define HWIO_GCC_PCIE_2_GDSCR_PD_ARES_SHFT                                                                0x3
#define HWIO_GCC_PCIE_2_GDSCR_SW_OVERRIDE_BMSK                                                            0x4
#define HWIO_GCC_PCIE_2_GDSCR_SW_OVERRIDE_SHFT                                                            0x2
#define HWIO_GCC_PCIE_2_GDSCR_HW_CONTROL_BMSK                                                             0x2
#define HWIO_GCC_PCIE_2_GDSCR_HW_CONTROL_SHFT                                                             0x1
#define HWIO_GCC_PCIE_2_GDSCR_SW_COLLAPSE_BMSK                                                            0x1
#define HWIO_GCC_PCIE_2_GDSCR_SW_COLLAPSE_SHFT                                                            0x0

#define HWIO_GCC_PCIE_2_CFG_GDSCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00006008)
#define HWIO_GCC_PCIE_2_CFG_GDSCR_RMSK                                                             0xffffffff
#define HWIO_GCC_PCIE_2_CFG_GDSCR_IN          \
        in_dword(HWIO_GCC_PCIE_2_CFG_GDSCR_ADDR)
#define HWIO_GCC_PCIE_2_CFG_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_CFG_GDSCR_ADDR, m)
#define HWIO_GCC_PCIE_2_CFG_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_CFG_GDSCR_ADDR,v)
#define HWIO_GCC_PCIE_2_CFG_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_CFG_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_2_CFG_GDSCR_IN)
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_SPARE_CTRL_IN_BMSK                                          0xf0000000
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_SPARE_CTRL_IN_SHFT                                                0x1c
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK                                          0xc000000
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT                                               0x1a
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK                                           0x2000000
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT                                                0x19
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_PWR_UP_START_BMSK                                            0x1000000
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_PWR_UP_START_SHFT                                                 0x18
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK                                     0xf00000
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT                                         0x14
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                                        0x80000
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                                           0x13
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK                                            0x40000
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT                                               0x12
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK                                            0x20000
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT                                               0x11
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK                                         0x10000
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT                                            0x10
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                                        0x8000
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                                           0xf
#define HWIO_GCC_PCIE_2_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                                       0x7800
#define HWIO_GCC_PCIE_2_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                                          0xb
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK                                               0x400
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT                                                 0xa
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                                        0x200
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                                          0x9
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                                        0x100
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                                          0x8
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                                            0x80
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                                             0x7
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                                   0x60
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                                    0x5
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                                             0x10
#define HWIO_GCC_PCIE_2_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                                              0x4
#define HWIO_GCC_PCIE_2_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                       0x8
#define HWIO_GCC_PCIE_2_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                       0x3
#define HWIO_GCC_PCIE_2_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                                     0x4
#define HWIO_GCC_PCIE_2_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                                     0x2
#define HWIO_GCC_PCIE_2_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                                         0x2
#define HWIO_GCC_PCIE_2_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                                         0x1
#define HWIO_GCC_PCIE_2_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                                      0x1
#define HWIO_GCC_PCIE_2_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                                      0x0

#define HWIO_GCC_PCIE_2_CFG2_GDSCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000600c)
#define HWIO_GCC_PCIE_2_CFG2_GDSCR_RMSK                                                               0x1ffff
#define HWIO_GCC_PCIE_2_CFG2_GDSCR_IN          \
        in_dword(HWIO_GCC_PCIE_2_CFG2_GDSCR_ADDR)
#define HWIO_GCC_PCIE_2_CFG2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_CFG2_GDSCR_ADDR, m)
#define HWIO_GCC_PCIE_2_CFG2_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_CFG2_GDSCR_ADDR,v)
#define HWIO_GCC_PCIE_2_CFG2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_CFG2_GDSCR_ADDR,m,v,HWIO_GCC_PCIE_2_CFG2_GDSCR_IN)
#define HWIO_GCC_PCIE_2_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK                                             0x10000
#define HWIO_GCC_PCIE_2_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT                                                0x10
#define HWIO_GCC_PCIE_2_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK                                                 0xf000
#define HWIO_GCC_PCIE_2_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT                                                    0xc
#define HWIO_GCC_PCIE_2_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                                          0xf00
#define HWIO_GCC_PCIE_2_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                                            0x8
#define HWIO_GCC_PCIE_2_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                                             0xf0
#define HWIO_GCC_PCIE_2_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                                              0x4
#define HWIO_GCC_PCIE_2_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                                               0xf
#define HWIO_GCC_PCIE_2_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                                               0x0

#define HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00006010)
#define HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_RMSK                                                      0x80100004
#define HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_ADDR)
#define HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_IN)
#define HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                    0x100000
#define HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                        0x14
#define HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_GCC_PCIE_2_SLV_Q2A_AXI_CBCR_CLK_ARES_SHFT                                                    0x2

#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00006014)
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_RMSK                                                          0x80107ff6
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_2_SLV_AXI_CBCR_ADDR)
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_SLV_AXI_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_SLV_AXI_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_SLV_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_2_SLV_AXI_CBCR_IN)
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK                                            0x4000
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT                                               0xe
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                          0x2000
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                             0xd
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                         0x1000
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                            0xc
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_WAKEUP_BMSK                                                        0xf00
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_WAKEUP_SHFT                                                          0x8
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_SLEEP_BMSK                                                          0xf0
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_SLEEP_SHFT                                                           0x4
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_HW_CTL_BMSK                                                          0x2
#define HWIO_GCC_PCIE_2_SLV_AXI_CBCR_HW_CTL_SHFT                                                          0x1

#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00006018)
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_RMSK                                                         0xfffff37e
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_IN          \
        in_dword(HWIO_GCC_PCIE_2_SLV_AXI_SREGR_ADDR)
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_SLV_AXI_SREGR_ADDR, m)
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_SLV_AXI_SREGR_ADDR,v)
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_SLV_AXI_SREGR_ADDR,m,v,HWIO_GCC_PCIE_2_SLV_AXI_SREGR_IN)
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                               0xff000000
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                     0x18
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                  0xff0000
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                      0x10
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_RESERVE_BITS15_13_BMSK                                           0xe000
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_RESERVE_BITS15_13_SHFT                                              0xd
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                 0x1000
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                    0xc
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                     0x300
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                       0x8
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_FORCE_CLK_ON_BMSK                                                  0x40
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_FORCE_CLK_ON_SHFT                                                   0x6
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK                                            0x20
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT                                             0x5
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SW_RST_SLP_STG_BMSK                                                0x10
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SW_RST_SLP_STG_SHFT                                                 0x4
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK                                               0x8
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT                                               0x3
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                          0x4
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                          0x2
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK                                              0x2
#define HWIO_GCC_PCIE_2_SLV_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT                                              0x1

#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0000601c)
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_RMSK                                                         0x80107ff4
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_ADDR)
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_ADDR,m,v,HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_IN)
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                       0x100000
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                           0x14
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_BMSK                                           0x4000
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_FORCE_MEM_CORE_ON_SHFT                                              0xe
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                         0x2000
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                            0xd
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                        0x1000
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                           0xc
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_WAKEUP_BMSK                                                       0xf00
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_WAKEUP_SHFT                                                         0x8
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_SLEEP_BMSK                                                         0xf0
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_SLEEP_SHFT                                                          0x4
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_GCC_PCIE_2_MSTR_AXI_CBCR_CLK_ARES_SHFT                                                       0x2

#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00006020)
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_RMSK                                                        0xfffff37e
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_IN          \
        in_dword(HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_ADDR)
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_ADDR, m)
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_ADDR,v)
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_ADDR,m,v,HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_IN)
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                              0xff000000
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                    0x18
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                 0xff0000
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                     0x10
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_RESERVE_BITS15_13_BMSK                                          0xe000
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_RESERVE_BITS15_13_SHFT                                             0xd
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                0x1000
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                   0xc
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                    0x300
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                      0x8
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_FORCE_CLK_ON_BMSK                                                 0x40
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_FORCE_CLK_ON_SHFT                                                  0x6
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_BMSK                                           0x20
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SW_RST_SEL_SLP_STG_SHFT                                            0x5
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SW_RST_SLP_STG_BMSK                                               0x10
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SW_RST_SLP_STG_SHFT                                                0x4
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_BMSK                                              0x8
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SW_CTRL_PWR_DOWN_SHFT                                              0x3
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                         0x4
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                         0x2
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_BMSK                                             0x2
#define HWIO_GCC_PCIE_2_MSTR_AXI_SREGR_SW_CLK_EN_SLP_STG_SHFT                                             0x1

#define HWIO_GCC_PCIE_2_CFG_AHB_CBCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00006024)
#define HWIO_GCC_PCIE_2_CFG_AHB_CBCR_RMSK                                                          0x80100006
#define HWIO_GCC_PCIE_2_CFG_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_2_CFG_AHB_CBCR_ADDR)
#define HWIO_GCC_PCIE_2_CFG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_CFG_AHB_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_2_CFG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_CFG_AHB_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_2_CFG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_PCIE_2_CFG_AHB_CBCR_IN)
#define HWIO_GCC_PCIE_2_CFG_AHB_CBCR_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_PCIE_2_CFG_AHB_CBCR_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_PCIE_2_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                        0x100000
#define HWIO_GCC_PCIE_2_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                            0x14
#define HWIO_GCC_PCIE_2_CFG_AHB_CBCR_CLK_ARES_BMSK                                                        0x4
#define HWIO_GCC_PCIE_2_CFG_AHB_CBCR_CLK_ARES_SHFT                                                        0x2
#define HWIO_GCC_PCIE_2_CFG_AHB_CBCR_HW_CTL_BMSK                                                          0x2
#define HWIO_GCC_PCIE_2_CFG_AHB_CBCR_HW_CTL_SHFT                                                          0x1

#define HWIO_GCC_PCIE_2_AUX_CBCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00006028)
#define HWIO_GCC_PCIE_2_AUX_CBCR_RMSK                                                              0x80000004
#define HWIO_GCC_PCIE_2_AUX_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_2_AUX_CBCR_ADDR)
#define HWIO_GCC_PCIE_2_AUX_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_AUX_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_2_AUX_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_AUX_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_2_AUX_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_AUX_CBCR_ADDR,m,v,HWIO_GCC_PCIE_2_AUX_CBCR_IN)
#define HWIO_GCC_PCIE_2_AUX_CBCR_CLK_OFF_BMSK                                                      0x80000000
#define HWIO_GCC_PCIE_2_AUX_CBCR_CLK_OFF_SHFT                                                            0x1f
#define HWIO_GCC_PCIE_2_AUX_CBCR_CLK_ARES_BMSK                                                            0x4
#define HWIO_GCC_PCIE_2_AUX_CBCR_CLK_ARES_SHFT                                                            0x2

#define HWIO_GCC_PCIE_2_PIPE_CBCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0000602c)
#define HWIO_GCC_PCIE_2_PIPE_CBCR_RMSK                                                             0x80007ff4
#define HWIO_GCC_PCIE_2_PIPE_CBCR_IN          \
        in_dword(HWIO_GCC_PCIE_2_PIPE_CBCR_ADDR)
#define HWIO_GCC_PCIE_2_PIPE_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_PIPE_CBCR_ADDR, m)
#define HWIO_GCC_PCIE_2_PIPE_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_PIPE_CBCR_ADDR,v)
#define HWIO_GCC_PCIE_2_PIPE_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_PIPE_CBCR_ADDR,m,v,HWIO_GCC_PCIE_2_PIPE_CBCR_IN)
#define HWIO_GCC_PCIE_2_PIPE_CBCR_CLK_OFF_BMSK                                                     0x80000000
#define HWIO_GCC_PCIE_2_PIPE_CBCR_CLK_OFF_SHFT                                                           0x1f
#define HWIO_GCC_PCIE_2_PIPE_CBCR_FORCE_MEM_CORE_ON_BMSK                                               0x4000
#define HWIO_GCC_PCIE_2_PIPE_CBCR_FORCE_MEM_CORE_ON_SHFT                                                  0xe
#define HWIO_GCC_PCIE_2_PIPE_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                             0x2000
#define HWIO_GCC_PCIE_2_PIPE_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                                0xd
#define HWIO_GCC_PCIE_2_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                            0x1000
#define HWIO_GCC_PCIE_2_PIPE_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                               0xc
#define HWIO_GCC_PCIE_2_PIPE_CBCR_WAKEUP_BMSK                                                           0xf00
#define HWIO_GCC_PCIE_2_PIPE_CBCR_WAKEUP_SHFT                                                             0x8
#define HWIO_GCC_PCIE_2_PIPE_CBCR_SLEEP_BMSK                                                             0xf0
#define HWIO_GCC_PCIE_2_PIPE_CBCR_SLEEP_SHFT                                                              0x4
#define HWIO_GCC_PCIE_2_PIPE_CBCR_CLK_ARES_BMSK                                                           0x4
#define HWIO_GCC_PCIE_2_PIPE_CBCR_CLK_ARES_SHFT                                                           0x2

#define HWIO_GCC_PCIE_2_PIPE_SREGR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00006030)
#define HWIO_GCC_PCIE_2_PIPE_SREGR_RMSK                                                            0xfffff37e
#define HWIO_GCC_PCIE_2_PIPE_SREGR_IN          \
        in_dword(HWIO_GCC_PCIE_2_PIPE_SREGR_ADDR)
#define HWIO_GCC_PCIE_2_PIPE_SREGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_PIPE_SREGR_ADDR, m)
#define HWIO_GCC_PCIE_2_PIPE_SREGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_PIPE_SREGR_ADDR,v)
#define HWIO_GCC_PCIE_2_PIPE_SREGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_PIPE_SREGR_ADDR,m,v,HWIO_GCC_PCIE_2_PIPE_SREGR_IN)
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_BMSK                                  0xff000000
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_OUT_SHFT                                        0x18
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_BMSK                                     0xff0000
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SREG_PSCBC_SPARE_CTRL_IN_SHFT                                         0x10
#define HWIO_GCC_PCIE_2_PIPE_SREGR_RESERVE_BITS15_13_BMSK                                              0xe000
#define HWIO_GCC_PCIE_2_PIPE_SREGR_RESERVE_BITS15_13_SHFT                                                 0xd
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_BMSK                                    0x1000
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SW_SM_PSCBC_SEQ_IN_OVERRIDE_SHFT                                       0xc
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_BMSK                                        0x300
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SW_DIV_RATIO_SLP_STG_CLK_SHFT                                          0x8
#define HWIO_GCC_PCIE_2_PIPE_SREGR_FORCE_CLK_ON_BMSK                                                     0x40
#define HWIO_GCC_PCIE_2_PIPE_SREGR_FORCE_CLK_ON_SHFT                                                      0x6
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SW_RST_SEL_SLP_STG_BMSK                                               0x20
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SW_RST_SEL_SLP_STG_SHFT                                                0x5
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SW_RST_SLP_STG_BMSK                                                   0x10
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SW_RST_SLP_STG_SHFT                                                    0x4
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SW_CTRL_PWR_DOWN_BMSK                                                  0x8
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SW_CTRL_PWR_DOWN_SHFT                                                  0x3
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_BMSK                                             0x4
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SW_CLK_EN_SEL_SLP_STG_SHFT                                             0x2
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SW_CLK_EN_SLP_STG_BMSK                                                 0x2
#define HWIO_GCC_PCIE_2_PIPE_SREGR_SW_CLK_EN_SLP_STG_SHFT                                                 0x1

#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00006038)
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_RMSK                                                          0x800000f3
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_PCIE_2_AUX_CMD_RCGR_ADDR)
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_AUX_CMD_RCGR_ADDR, m)
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_AUX_CMD_RCGR_ADDR,v)
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_AUX_CMD_RCGR_ADDR,m,v,HWIO_GCC_PCIE_2_AUX_CMD_RCGR_IN)
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_ROOT_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_ROOT_OFF_SHFT                                                       0x1f
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_DIRTY_D_BMSK                                                        0x80
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_DIRTY_D_SHFT                                                         0x7
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_DIRTY_N_BMSK                                                        0x40
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_DIRTY_N_SHFT                                                         0x6
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_DIRTY_M_BMSK                                                        0x20
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_DIRTY_M_SHFT                                                         0x5
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                 0x10
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                  0x4
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_ROOT_EN_BMSK                                                         0x2
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_ROOT_EN_SHFT                                                         0x1
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_UPDATE_BMSK                                                          0x1
#define HWIO_GCC_PCIE_2_AUX_CMD_RCGR_UPDATE_SHFT                                                          0x0

#define HWIO_GCC_PCIE_2_AUX_CFG_RCGR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0000603c)
#define HWIO_GCC_PCIE_2_AUX_CFG_RCGR_RMSK                                                            0x10371f
#define HWIO_GCC_PCIE_2_AUX_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_PCIE_2_AUX_CFG_RCGR_ADDR)
#define HWIO_GCC_PCIE_2_AUX_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_AUX_CFG_RCGR_ADDR, m)
#define HWIO_GCC_PCIE_2_AUX_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_AUX_CFG_RCGR_ADDR,v)
#define HWIO_GCC_PCIE_2_AUX_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_AUX_CFG_RCGR_ADDR,m,v,HWIO_GCC_PCIE_2_AUX_CFG_RCGR_IN)
#define HWIO_GCC_PCIE_2_AUX_CFG_RCGR_HW_CLK_CONTROL_BMSK                                             0x100000
#define HWIO_GCC_PCIE_2_AUX_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                 0x14
#define HWIO_GCC_PCIE_2_AUX_CFG_RCGR_MODE_BMSK                                                         0x3000
#define HWIO_GCC_PCIE_2_AUX_CFG_RCGR_MODE_SHFT                                                            0xc
#define HWIO_GCC_PCIE_2_AUX_CFG_RCGR_SRC_SEL_BMSK                                                       0x700
#define HWIO_GCC_PCIE_2_AUX_CFG_RCGR_SRC_SEL_SHFT                                                         0x8
#define HWIO_GCC_PCIE_2_AUX_CFG_RCGR_SRC_DIV_BMSK                                                        0x1f
#define HWIO_GCC_PCIE_2_AUX_CFG_RCGR_SRC_DIV_SHFT                                                         0x0

#define HWIO_GCC_PCIE_2_AUX_M_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00006040)
#define HWIO_GCC_PCIE_2_AUX_M_RMSK                                                                     0xffff
#define HWIO_GCC_PCIE_2_AUX_M_IN          \
        in_dword(HWIO_GCC_PCIE_2_AUX_M_ADDR)
#define HWIO_GCC_PCIE_2_AUX_M_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_AUX_M_ADDR, m)
#define HWIO_GCC_PCIE_2_AUX_M_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_AUX_M_ADDR,v)
#define HWIO_GCC_PCIE_2_AUX_M_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_AUX_M_ADDR,m,v,HWIO_GCC_PCIE_2_AUX_M_IN)
#define HWIO_GCC_PCIE_2_AUX_M_M_BMSK                                                                   0xffff
#define HWIO_GCC_PCIE_2_AUX_M_M_SHFT                                                                      0x0

#define HWIO_GCC_PCIE_2_AUX_N_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00006044)
#define HWIO_GCC_PCIE_2_AUX_N_RMSK                                                                     0xffff
#define HWIO_GCC_PCIE_2_AUX_N_IN          \
        in_dword(HWIO_GCC_PCIE_2_AUX_N_ADDR)
#define HWIO_GCC_PCIE_2_AUX_N_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_AUX_N_ADDR, m)
#define HWIO_GCC_PCIE_2_AUX_N_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_AUX_N_ADDR,v)
#define HWIO_GCC_PCIE_2_AUX_N_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_AUX_N_ADDR,m,v,HWIO_GCC_PCIE_2_AUX_N_IN)
#define HWIO_GCC_PCIE_2_AUX_N_NOT_N_MINUS_M_BMSK                                                       0xffff
#define HWIO_GCC_PCIE_2_AUX_N_NOT_N_MINUS_M_SHFT                                                          0x0

#define HWIO_GCC_PCIE_2_AUX_D_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00006048)
#define HWIO_GCC_PCIE_2_AUX_D_RMSK                                                                     0xffff
#define HWIO_GCC_PCIE_2_AUX_D_IN          \
        in_dword(HWIO_GCC_PCIE_2_AUX_D_ADDR)
#define HWIO_GCC_PCIE_2_AUX_D_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_AUX_D_ADDR, m)
#define HWIO_GCC_PCIE_2_AUX_D_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_AUX_D_ADDR,v)
#define HWIO_GCC_PCIE_2_AUX_D_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_AUX_D_ADDR,m,v,HWIO_GCC_PCIE_2_AUX_D_IN)
#define HWIO_GCC_PCIE_2_AUX_D_NOT_2D_BMSK                                                              0xffff
#define HWIO_GCC_PCIE_2_AUX_D_NOT_2D_SHFT                                                                 0x0

#define HWIO_GCC_IPCC_BCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00025000)
#define HWIO_GCC_IPCC_BCR_RMSK                                                                            0x1
#define HWIO_GCC_IPCC_BCR_IN          \
        in_dword(HWIO_GCC_IPCC_BCR_ADDR)
#define HWIO_GCC_IPCC_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPCC_BCR_ADDR, m)
#define HWIO_GCC_IPCC_BCR_OUT(v)      \
        out_dword(HWIO_GCC_IPCC_BCR_ADDR,v)
#define HWIO_GCC_IPCC_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPCC_BCR_ADDR,m,v,HWIO_GCC_IPCC_BCR_IN)
#define HWIO_GCC_IPCC_BCR_BLK_ARES_BMSK                                                                   0x1
#define HWIO_GCC_IPCC_BCR_BLK_ARES_SHFT                                                                   0x0

#define HWIO_GCC_IPCC_CORE_CBCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00025004)
#define HWIO_GCC_IPCC_CORE_CBCR_RMSK                                                               0x80000005
#define HWIO_GCC_IPCC_CORE_CBCR_IN          \
        in_dword(HWIO_GCC_IPCC_CORE_CBCR_ADDR)
#define HWIO_GCC_IPCC_CORE_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPCC_CORE_CBCR_ADDR, m)
#define HWIO_GCC_IPCC_CORE_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_IPCC_CORE_CBCR_ADDR,v)
#define HWIO_GCC_IPCC_CORE_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPCC_CORE_CBCR_ADDR,m,v,HWIO_GCC_IPCC_CORE_CBCR_IN)
#define HWIO_GCC_IPCC_CORE_CBCR_CLK_OFF_BMSK                                                       0x80000000
#define HWIO_GCC_IPCC_CORE_CBCR_CLK_OFF_SHFT                                                             0x1f
#define HWIO_GCC_IPCC_CORE_CBCR_CLK_ARES_BMSK                                                             0x4
#define HWIO_GCC_IPCC_CORE_CBCR_CLK_ARES_SHFT                                                             0x2
#define HWIO_GCC_IPCC_CORE_CBCR_CLK_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_IPCC_CORE_CBCR_CLK_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_IPCC_AHB_CBCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00025008)
#define HWIO_GCC_IPCC_AHB_CBCR_RMSK                                                                0x80100007
#define HWIO_GCC_IPCC_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_IPCC_AHB_CBCR_ADDR)
#define HWIO_GCC_IPCC_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPCC_AHB_CBCR_ADDR, m)
#define HWIO_GCC_IPCC_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_IPCC_AHB_CBCR_ADDR,v)
#define HWIO_GCC_IPCC_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPCC_AHB_CBCR_ADDR,m,v,HWIO_GCC_IPCC_AHB_CBCR_IN)
#define HWIO_GCC_IPCC_AHB_CBCR_CLK_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_IPCC_AHB_CBCR_CLK_OFF_SHFT                                                              0x1f
#define HWIO_GCC_IPCC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                              0x100000
#define HWIO_GCC_IPCC_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                  0x14
#define HWIO_GCC_IPCC_AHB_CBCR_CLK_ARES_BMSK                                                              0x4
#define HWIO_GCC_IPCC_AHB_CBCR_CLK_ARES_SHFT                                                              0x2
#define HWIO_GCC_IPCC_AHB_CBCR_HW_CTL_BMSK                                                                0x2
#define HWIO_GCC_IPCC_AHB_CBCR_HW_CTL_SHFT                                                                0x1
#define HWIO_GCC_IPCC_AHB_CBCR_CLK_ENABLE_BMSK                                                            0x1
#define HWIO_GCC_IPCC_AHB_CBCR_CLK_ENABLE_SHFT                                                            0x0

#define HWIO_GCC_IPCC_CORE_CMD_RCGR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0002500c)
#define HWIO_GCC_IPCC_CORE_CMD_RCGR_RMSK                                                           0x80000013
#define HWIO_GCC_IPCC_CORE_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_IPCC_CORE_CMD_RCGR_ADDR)
#define HWIO_GCC_IPCC_CORE_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPCC_CORE_CMD_RCGR_ADDR, m)
#define HWIO_GCC_IPCC_CORE_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_IPCC_CORE_CMD_RCGR_ADDR,v)
#define HWIO_GCC_IPCC_CORE_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPCC_CORE_CMD_RCGR_ADDR,m,v,HWIO_GCC_IPCC_CORE_CMD_RCGR_IN)
#define HWIO_GCC_IPCC_CORE_CMD_RCGR_ROOT_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_IPCC_CORE_CMD_RCGR_ROOT_OFF_SHFT                                                        0x1f
#define HWIO_GCC_IPCC_CORE_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                  0x10
#define HWIO_GCC_IPCC_CORE_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                   0x4
#define HWIO_GCC_IPCC_CORE_CMD_RCGR_ROOT_EN_BMSK                                                          0x2
#define HWIO_GCC_IPCC_CORE_CMD_RCGR_ROOT_EN_SHFT                                                          0x1
#define HWIO_GCC_IPCC_CORE_CMD_RCGR_UPDATE_BMSK                                                           0x1
#define HWIO_GCC_IPCC_CORE_CMD_RCGR_UPDATE_SHFT                                                           0x0

#define HWIO_GCC_IPCC_CORE_CFG_RCGR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00025010)
#define HWIO_GCC_IPCC_CORE_CFG_RCGR_RMSK                                                             0x11071f
#define HWIO_GCC_IPCC_CORE_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_IPCC_CORE_CFG_RCGR_ADDR)
#define HWIO_GCC_IPCC_CORE_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_IPCC_CORE_CFG_RCGR_ADDR, m)
#define HWIO_GCC_IPCC_CORE_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_IPCC_CORE_CFG_RCGR_ADDR,v)
#define HWIO_GCC_IPCC_CORE_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_IPCC_CORE_CFG_RCGR_ADDR,m,v,HWIO_GCC_IPCC_CORE_CFG_RCGR_IN)
#define HWIO_GCC_IPCC_CORE_CFG_RCGR_HW_CLK_CONTROL_BMSK                                              0x100000
#define HWIO_GCC_IPCC_CORE_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                  0x14
#define HWIO_GCC_IPCC_CORE_CFG_RCGR_RCGLITE_DISABLE_BMSK                                              0x10000
#define HWIO_GCC_IPCC_CORE_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                 0x10
#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_SEL_BMSK                                                        0x700
#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_SEL_SHFT                                                          0x8
#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_BMSK                                                         0x1f
#define HWIO_GCC_IPCC_CORE_CFG_RCGR_SRC_DIV_SHFT                                                          0x0

#define HWIO_GCC_DPM_BCR_ADDR                                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00046000)
#define HWIO_GCC_DPM_BCR_RMSK                                                                             0x1
#define HWIO_GCC_DPM_BCR_IN          \
        in_dword(HWIO_GCC_DPM_BCR_ADDR)
#define HWIO_GCC_DPM_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DPM_BCR_ADDR, m)
#define HWIO_GCC_DPM_BCR_OUT(v)      \
        out_dword(HWIO_GCC_DPM_BCR_ADDR,v)
#define HWIO_GCC_DPM_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DPM_BCR_ADDR,m,v,HWIO_GCC_DPM_BCR_IN)
#define HWIO_GCC_DPM_BCR_BLK_ARES_BMSK                                                                    0x1
#define HWIO_GCC_DPM_BCR_BLK_ARES_SHFT                                                                    0x0

#define HWIO_GCC_DPM_CBCR_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00046004)
#define HWIO_GCC_DPM_CBCR_RMSK                                                                     0x80000005
#define HWIO_GCC_DPM_CBCR_IN          \
        in_dword(HWIO_GCC_DPM_CBCR_ADDR)
#define HWIO_GCC_DPM_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DPM_CBCR_ADDR, m)
#define HWIO_GCC_DPM_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DPM_CBCR_ADDR,v)
#define HWIO_GCC_DPM_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DPM_CBCR_ADDR,m,v,HWIO_GCC_DPM_CBCR_IN)
#define HWIO_GCC_DPM_CBCR_CLK_OFF_BMSK                                                             0x80000000
#define HWIO_GCC_DPM_CBCR_CLK_OFF_SHFT                                                                   0x1f
#define HWIO_GCC_DPM_CBCR_CLK_ARES_BMSK                                                                   0x4
#define HWIO_GCC_DPM_CBCR_CLK_ARES_SHFT                                                                   0x2
#define HWIO_GCC_DPM_CBCR_CLK_ENABLE_BMSK                                                                 0x1
#define HWIO_GCC_DPM_CBCR_CLK_ENABLE_SHFT                                                                 0x0

#define HWIO_GCC_DPM_AHB_CBCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00046008)
#define HWIO_GCC_DPM_AHB_CBCR_RMSK                                                                 0x80100007
#define HWIO_GCC_DPM_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_DPM_AHB_CBCR_ADDR)
#define HWIO_GCC_DPM_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_DPM_AHB_CBCR_ADDR, m)
#define HWIO_GCC_DPM_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_DPM_AHB_CBCR_ADDR,v)
#define HWIO_GCC_DPM_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DPM_AHB_CBCR_ADDR,m,v,HWIO_GCC_DPM_AHB_CBCR_IN)
#define HWIO_GCC_DPM_AHB_CBCR_CLK_OFF_BMSK                                                         0x80000000
#define HWIO_GCC_DPM_AHB_CBCR_CLK_OFF_SHFT                                                               0x1f
#define HWIO_GCC_DPM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                               0x100000
#define HWIO_GCC_DPM_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                                   0x14
#define HWIO_GCC_DPM_AHB_CBCR_CLK_ARES_BMSK                                                               0x4
#define HWIO_GCC_DPM_AHB_CBCR_CLK_ARES_SHFT                                                               0x2
#define HWIO_GCC_DPM_AHB_CBCR_HW_CTL_BMSK                                                                 0x2
#define HWIO_GCC_DPM_AHB_CBCR_HW_CTL_SHFT                                                                 0x1
#define HWIO_GCC_DPM_AHB_CBCR_CLK_ENABLE_BMSK                                                             0x1
#define HWIO_GCC_DPM_AHB_CBCR_CLK_ENABLE_SHFT                                                             0x0

#define HWIO_GCC_DPM_CMD_RCGR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0004600c)
#define HWIO_GCC_DPM_CMD_RCGR_RMSK                                                                 0x80000013
#define HWIO_GCC_DPM_CMD_RCGR_IN          \
        in_dword(HWIO_GCC_DPM_CMD_RCGR_ADDR)
#define HWIO_GCC_DPM_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_DPM_CMD_RCGR_ADDR, m)
#define HWIO_GCC_DPM_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_DPM_CMD_RCGR_ADDR,v)
#define HWIO_GCC_DPM_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DPM_CMD_RCGR_ADDR,m,v,HWIO_GCC_DPM_CMD_RCGR_IN)
#define HWIO_GCC_DPM_CMD_RCGR_ROOT_OFF_BMSK                                                        0x80000000
#define HWIO_GCC_DPM_CMD_RCGR_ROOT_OFF_SHFT                                                              0x1f
#define HWIO_GCC_DPM_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                                        0x10
#define HWIO_GCC_DPM_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                                         0x4
#define HWIO_GCC_DPM_CMD_RCGR_ROOT_EN_BMSK                                                                0x2
#define HWIO_GCC_DPM_CMD_RCGR_ROOT_EN_SHFT                                                                0x1
#define HWIO_GCC_DPM_CMD_RCGR_UPDATE_BMSK                                                                 0x1
#define HWIO_GCC_DPM_CMD_RCGR_UPDATE_SHFT                                                                 0x0

#define HWIO_GCC_DPM_CFG_RCGR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00046010)
#define HWIO_GCC_DPM_CFG_RCGR_RMSK                                                                   0x11071f
#define HWIO_GCC_DPM_CFG_RCGR_IN          \
        in_dword(HWIO_GCC_DPM_CFG_RCGR_ADDR)
#define HWIO_GCC_DPM_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_GCC_DPM_CFG_RCGR_ADDR, m)
#define HWIO_GCC_DPM_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_GCC_DPM_CFG_RCGR_ADDR,v)
#define HWIO_GCC_DPM_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DPM_CFG_RCGR_ADDR,m,v,HWIO_GCC_DPM_CFG_RCGR_IN)
#define HWIO_GCC_DPM_CFG_RCGR_HW_CLK_CONTROL_BMSK                                                    0x100000
#define HWIO_GCC_DPM_CFG_RCGR_HW_CLK_CONTROL_SHFT                                                        0x14
#define HWIO_GCC_DPM_CFG_RCGR_RCGLITE_DISABLE_BMSK                                                    0x10000
#define HWIO_GCC_DPM_CFG_RCGR_RCGLITE_DISABLE_SHFT                                                       0x10
#define HWIO_GCC_DPM_CFG_RCGR_SRC_SEL_BMSK                                                              0x700
#define HWIO_GCC_DPM_CFG_RCGR_SRC_SEL_SHFT                                                                0x8
#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_BMSK                                                               0x1f
#define HWIO_GCC_DPM_CFG_RCGR_SRC_DIV_SHFT                                                                0x0

#define HWIO_GCC_NPU_BWMON_BCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00073000)
#define HWIO_GCC_NPU_BWMON_BCR_RMSK                                                                       0x1
#define HWIO_GCC_NPU_BWMON_BCR_IN          \
        in_dword(HWIO_GCC_NPU_BWMON_BCR_ADDR)
#define HWIO_GCC_NPU_BWMON_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_BWMON_BCR_ADDR, m)
#define HWIO_GCC_NPU_BWMON_BCR_OUT(v)      \
        out_dword(HWIO_GCC_NPU_BWMON_BCR_ADDR,v)
#define HWIO_GCC_NPU_BWMON_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_BWMON_BCR_ADDR,m,v,HWIO_GCC_NPU_BWMON_BCR_IN)
#define HWIO_GCC_NPU_BWMON_BCR_BLK_ARES_BMSK                                                              0x1
#define HWIO_GCC_NPU_BWMON_BCR_BLK_ARES_SHFT                                                              0x0

#define HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00073004)
#define HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_RMSK                                                       0x80100005
#define HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_IN          \
        in_dword(HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_ADDR)
#define HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_ADDR, m)
#define HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_ADDR,v)
#define HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_ADDR,m,v,HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_IN)
#define HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                     0x100000
#define HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                         0x14
#define HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_NPU_BWMON_CFG_AHB_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_NPU_BWMON_AXI_CBCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00073008)
#define HWIO_GCC_NPU_BWMON_AXI_CBCR_RMSK                                                           0x80100005
#define HWIO_GCC_NPU_BWMON_AXI_CBCR_IN          \
        in_dword(HWIO_GCC_NPU_BWMON_AXI_CBCR_ADDR)
#define HWIO_GCC_NPU_BWMON_AXI_CBCR_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_BWMON_AXI_CBCR_ADDR, m)
#define HWIO_GCC_NPU_BWMON_AXI_CBCR_OUT(v)      \
        out_dword(HWIO_GCC_NPU_BWMON_AXI_CBCR_ADDR,v)
#define HWIO_GCC_NPU_BWMON_AXI_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_BWMON_AXI_CBCR_ADDR,m,v,HWIO_GCC_NPU_BWMON_AXI_CBCR_IN)
#define HWIO_GCC_NPU_BWMON_AXI_CBCR_CLK_OFF_BMSK                                                   0x80000000
#define HWIO_GCC_NPU_BWMON_AXI_CBCR_CLK_OFF_SHFT                                                         0x1f
#define HWIO_GCC_NPU_BWMON_AXI_CBCR_IGNORE_RPMH_CLK_DIS_BMSK                                         0x100000
#define HWIO_GCC_NPU_BWMON_AXI_CBCR_IGNORE_RPMH_CLK_DIS_SHFT                                             0x14
#define HWIO_GCC_NPU_BWMON_AXI_CBCR_CLK_ARES_BMSK                                                         0x4
#define HWIO_GCC_NPU_BWMON_AXI_CBCR_CLK_ARES_SHFT                                                         0x2
#define HWIO_GCC_NPU_BWMON_AXI_CBCR_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_NPU_BWMON_AXI_CBCR_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00000ff8)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_RMSK                                     0x80000001
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                              0x80000000
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                    0x1f
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                 0x1
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                 0x0

#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00000ff4)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_RMSK                                     0x80000001
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                              0x80000000
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                    0x1f
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                 0x1
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                 0x0

#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00000ff0)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_RMSK                                     0x80000001
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                              0x80000000
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                    0x1f
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                 0x1
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                 0x0

#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fec)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_RMSK                                     0x80000001
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                              0x80000000
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                    0x1f
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                 0x1
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                 0x0

#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fe8)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_RMSK                                     0x80000001
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                              0x80000000
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                    0x1f
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                 0x1
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                 0x0

#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fe4)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_RMSK                                     0x80000001
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                              0x80000000
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                    0x1f
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                 0x1
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                 0x0

#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fe0)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_RMSK                                     0x80000001
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                              0x80000000
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                    0x1f
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                 0x1
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                 0x0

#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fdc)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_RMSK                                     0x80000001
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                              0x80000000
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                    0x1f
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                 0x1
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                 0x0

#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fd8)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_RMSK                                     0x80000001
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                              0x80000000
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                    0x1f
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                 0x1
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                 0x0

#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fd4)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fd0)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fcc)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fc8)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP13_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fc4)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fc0)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fbc)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fb8)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fb4)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fb0)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fac)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fa8)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fa4)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000fa0)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000f9c)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000f98)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP25_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_ADDR                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000f94)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_RMSK                                    0x80000001
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_IN)
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_CLK_ON_BMSK                             0x80000000
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_CLK_ON_SHFT                                   0x1f
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_CLK_ENABLE_BMSK                                0x1
#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP26_CLKGEN_ACGC_ACGCR_CLK_ENABLE_SHFT                                0x0

#define HWIO_GCC_SP_IPA_SGDSCR_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0003f000)
#define HWIO_GCC_SP_IPA_SGDSCR_RMSK                                                                       0x3
#define HWIO_GCC_SP_IPA_SGDSCR_IN          \
        in_dword(HWIO_GCC_SP_IPA_SGDSCR_ADDR)
#define HWIO_GCC_SP_IPA_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_IPA_SGDSCR_ADDR, m)
#define HWIO_GCC_SP_IPA_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_IPA_SGDSCR_ADDR,v)
#define HWIO_GCC_SP_IPA_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_IPA_SGDSCR_ADDR,m,v,HWIO_GCC_SP_IPA_SGDSCR_IN)
#define HWIO_GCC_SP_IPA_SGDSCR_RETAIN_FF_ENABLE_BMSK                                                      0x2
#define HWIO_GCC_SP_IPA_SGDSCR_RETAIN_FF_ENABLE_SHFT                                                      0x1
#define HWIO_GCC_SP_IPA_SGDSCR_SW_OVERRIDE_BMSK                                                           0x1
#define HWIO_GCC_SP_IPA_SGDSCR_SW_OVERRIDE_SHFT                                                           0x0

#define HWIO_GCC_SP_UFS_CARD_SGDSCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0003f004)
#define HWIO_GCC_SP_UFS_CARD_SGDSCR_RMSK                                                                  0x3
#define HWIO_GCC_SP_UFS_CARD_SGDSCR_IN          \
        in_dword(HWIO_GCC_SP_UFS_CARD_SGDSCR_ADDR)
#define HWIO_GCC_SP_UFS_CARD_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_UFS_CARD_SGDSCR_ADDR, m)
#define HWIO_GCC_SP_UFS_CARD_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_UFS_CARD_SGDSCR_ADDR,v)
#define HWIO_GCC_SP_UFS_CARD_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_UFS_CARD_SGDSCR_ADDR,m,v,HWIO_GCC_SP_UFS_CARD_SGDSCR_IN)
#define HWIO_GCC_SP_UFS_CARD_SGDSCR_RETAIN_FF_ENABLE_BMSK                                                 0x2
#define HWIO_GCC_SP_UFS_CARD_SGDSCR_RETAIN_FF_ENABLE_SHFT                                                 0x1
#define HWIO_GCC_SP_UFS_CARD_SGDSCR_SW_OVERRIDE_BMSK                                                      0x1
#define HWIO_GCC_SP_UFS_CARD_SGDSCR_SW_OVERRIDE_SHFT                                                      0x0

#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0003f008)
#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_RMSK                                                                0x3
#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_IN          \
        in_dword(HWIO_GCC_SP_USB30_PRIM_SGDSCR_ADDR)
#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_USB30_PRIM_SGDSCR_ADDR, m)
#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_USB30_PRIM_SGDSCR_ADDR,v)
#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_USB30_PRIM_SGDSCR_ADDR,m,v,HWIO_GCC_SP_USB30_PRIM_SGDSCR_IN)
#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_BMSK                                               0x2
#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_SHFT                                               0x1
#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_SW_OVERRIDE_BMSK                                                    0x1
#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_SW_OVERRIDE_SHFT                                                    0x0

#define HWIO_GCC_SP_UFS_PHY_SGDSCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0003f00c)
#define HWIO_GCC_SP_UFS_PHY_SGDSCR_RMSK                                                                   0x3
#define HWIO_GCC_SP_UFS_PHY_SGDSCR_IN          \
        in_dword(HWIO_GCC_SP_UFS_PHY_SGDSCR_ADDR)
#define HWIO_GCC_SP_UFS_PHY_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_UFS_PHY_SGDSCR_ADDR, m)
#define HWIO_GCC_SP_UFS_PHY_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_UFS_PHY_SGDSCR_ADDR,v)
#define HWIO_GCC_SP_UFS_PHY_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_UFS_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_SP_UFS_PHY_SGDSCR_IN)
#define HWIO_GCC_SP_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK                                                  0x2
#define HWIO_GCC_SP_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT                                                  0x1
#define HWIO_GCC_SP_UFS_PHY_SGDSCR_SW_OVERRIDE_BMSK                                                       0x1
#define HWIO_GCC_SP_UFS_PHY_SGDSCR_SW_OVERRIDE_SHFT                                                       0x0

#define HWIO_GCC_SP_PCIE_2_SGDSCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0003f010)
#define HWIO_GCC_SP_PCIE_2_SGDSCR_RMSK                                                                    0x3
#define HWIO_GCC_SP_PCIE_2_SGDSCR_IN          \
        in_dword(HWIO_GCC_SP_PCIE_2_SGDSCR_ADDR)
#define HWIO_GCC_SP_PCIE_2_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_PCIE_2_SGDSCR_ADDR, m)
#define HWIO_GCC_SP_PCIE_2_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_PCIE_2_SGDSCR_ADDR,v)
#define HWIO_GCC_SP_PCIE_2_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_PCIE_2_SGDSCR_ADDR,m,v,HWIO_GCC_SP_PCIE_2_SGDSCR_IN)
#define HWIO_GCC_SP_PCIE_2_SGDSCR_RETAIN_FF_ENABLE_BMSK                                                   0x2
#define HWIO_GCC_SP_PCIE_2_SGDSCR_RETAIN_FF_ENABLE_SHFT                                                   0x1
#define HWIO_GCC_SP_PCIE_2_SGDSCR_SW_OVERRIDE_BMSK                                                        0x1
#define HWIO_GCC_SP_PCIE_2_SGDSCR_SW_OVERRIDE_SHFT                                                        0x0

#define HWIO_GCC_SP_PCIE_0_SGDSCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0003f014)
#define HWIO_GCC_SP_PCIE_0_SGDSCR_RMSK                                                                    0x3
#define HWIO_GCC_SP_PCIE_0_SGDSCR_IN          \
        in_dword(HWIO_GCC_SP_PCIE_0_SGDSCR_ADDR)
#define HWIO_GCC_SP_PCIE_0_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_PCIE_0_SGDSCR_ADDR, m)
#define HWIO_GCC_SP_PCIE_0_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_PCIE_0_SGDSCR_ADDR,v)
#define HWIO_GCC_SP_PCIE_0_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_PCIE_0_SGDSCR_ADDR,m,v,HWIO_GCC_SP_PCIE_0_SGDSCR_IN)
#define HWIO_GCC_SP_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_BMSK                                                   0x2
#define HWIO_GCC_SP_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_SHFT                                                   0x1
#define HWIO_GCC_SP_PCIE_0_SGDSCR_SW_OVERRIDE_BMSK                                                        0x1
#define HWIO_GCC_SP_PCIE_0_SGDSCR_SW_OVERRIDE_SHFT                                                        0x0

#define HWIO_GCC_SP_PCIE_1_SGDSCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0003f018)
#define HWIO_GCC_SP_PCIE_1_SGDSCR_RMSK                                                                    0x3
#define HWIO_GCC_SP_PCIE_1_SGDSCR_IN          \
        in_dword(HWIO_GCC_SP_PCIE_1_SGDSCR_ADDR)
#define HWIO_GCC_SP_PCIE_1_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_PCIE_1_SGDSCR_ADDR, m)
#define HWIO_GCC_SP_PCIE_1_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_PCIE_1_SGDSCR_ADDR,v)
#define HWIO_GCC_SP_PCIE_1_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_PCIE_1_SGDSCR_ADDR,m,v,HWIO_GCC_SP_PCIE_1_SGDSCR_IN)
#define HWIO_GCC_SP_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_BMSK                                                   0x2
#define HWIO_GCC_SP_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_SHFT                                                   0x1
#define HWIO_GCC_SP_PCIE_1_SGDSCR_SW_OVERRIDE_BMSK                                                        0x1
#define HWIO_GCC_SP_PCIE_1_SGDSCR_SW_OVERRIDE_SHFT                                                        0x0

#define HWIO_GCC_SP_USB30_SEC_SGDSCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0003f01c)
#define HWIO_GCC_SP_USB30_SEC_SGDSCR_RMSK                                                                 0x3
#define HWIO_GCC_SP_USB30_SEC_SGDSCR_IN          \
        in_dword(HWIO_GCC_SP_USB30_SEC_SGDSCR_ADDR)
#define HWIO_GCC_SP_USB30_SEC_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_USB30_SEC_SGDSCR_ADDR, m)
#define HWIO_GCC_SP_USB30_SEC_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_USB30_SEC_SGDSCR_ADDR,v)
#define HWIO_GCC_SP_USB30_SEC_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_USB30_SEC_SGDSCR_ADDR,m,v,HWIO_GCC_SP_USB30_SEC_SGDSCR_IN)
#define HWIO_GCC_SP_USB30_SEC_SGDSCR_RETAIN_FF_ENABLE_BMSK                                                0x2
#define HWIO_GCC_SP_USB30_SEC_SGDSCR_RETAIN_FF_ENABLE_SHFT                                                0x1
#define HWIO_GCC_SP_USB30_SEC_SGDSCR_SW_OVERRIDE_BMSK                                                     0x1
#define HWIO_GCC_SP_USB30_SEC_SGDSCR_SW_OVERRIDE_SHFT                                                     0x0

#define HWIO_GCC_SP_MMNOC_SGDSCR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0003f020)
#define HWIO_GCC_SP_MMNOC_SGDSCR_RMSK                                                                     0x3
#define HWIO_GCC_SP_MMNOC_SGDSCR_IN          \
        in_dword(HWIO_GCC_SP_MMNOC_SGDSCR_ADDR)
#define HWIO_GCC_SP_MMNOC_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_MMNOC_SGDSCR_ADDR, m)
#define HWIO_GCC_SP_MMNOC_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_SP_MMNOC_SGDSCR_ADDR,v)
#define HWIO_GCC_SP_MMNOC_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_MMNOC_SGDSCR_ADDR,m,v,HWIO_GCC_SP_MMNOC_SGDSCR_IN)
#define HWIO_GCC_SP_MMNOC_SGDSCR_RETAIN_FF_ENABLE_BMSK                                                    0x2
#define HWIO_GCC_SP_MMNOC_SGDSCR_RETAIN_FF_ENABLE_SHFT                                                    0x1
#define HWIO_GCC_SP_MMNOC_SGDSCR_SW_OVERRIDE_BMSK                                                         0x1
#define HWIO_GCC_SP_MMNOC_SGDSCR_SW_OVERRIDE_SHFT                                                         0x0

#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00053000)
#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_RMSK                                                                  0x3
#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_IN          \
        in_dword(HWIO_GCC_APCS_TZ_IPA_SGDSCR_ADDR)
#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_IPA_SGDSCR_ADDR, m)
#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_IPA_SGDSCR_ADDR,v)
#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_IPA_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_IPA_SGDSCR_IN)
#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_RETAIN_FF_ENABLE_BMSK                                                 0x2
#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_RETAIN_FF_ENABLE_SHFT                                                 0x1
#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_SW_OVERRIDE_BMSK                                                      0x1
#define HWIO_GCC_APCS_TZ_IPA_SGDSCR_SW_OVERRIDE_SHFT                                                      0x0

#define HWIO_GCC_APCS_TZ_UFS_CARD_SGDSCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00053004)
#define HWIO_GCC_APCS_TZ_UFS_CARD_SGDSCR_RMSK                                                             0x3
#define HWIO_GCC_APCS_TZ_UFS_CARD_SGDSCR_IN          \
        in_dword(HWIO_GCC_APCS_TZ_UFS_CARD_SGDSCR_ADDR)
#define HWIO_GCC_APCS_TZ_UFS_CARD_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_UFS_CARD_SGDSCR_ADDR, m)
#define HWIO_GCC_APCS_TZ_UFS_CARD_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_UFS_CARD_SGDSCR_ADDR,v)
#define HWIO_GCC_APCS_TZ_UFS_CARD_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_UFS_CARD_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_UFS_CARD_SGDSCR_IN)
#define HWIO_GCC_APCS_TZ_UFS_CARD_SGDSCR_RETAIN_FF_ENABLE_BMSK                                            0x2
#define HWIO_GCC_APCS_TZ_UFS_CARD_SGDSCR_RETAIN_FF_ENABLE_SHFT                                            0x1
#define HWIO_GCC_APCS_TZ_UFS_CARD_SGDSCR_SW_OVERRIDE_BMSK                                                 0x1
#define HWIO_GCC_APCS_TZ_UFS_CARD_SGDSCR_SW_OVERRIDE_SHFT                                                 0x0

#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00053008)
#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_RMSK                                                           0x3
#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_IN          \
        in_dword(HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_ADDR)
#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_ADDR, m)
#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_ADDR,v)
#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_IN)
#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_BMSK                                          0x2
#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_SHFT                                          0x1
#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_SW_OVERRIDE_BMSK                                               0x1
#define HWIO_GCC_APCS_TZ_USB30_PRIM_SGDSCR_SW_OVERRIDE_SHFT                                               0x0

#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0005300c)
#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_RMSK                                                              0x3
#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_IN          \
        in_dword(HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_ADDR)
#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_ADDR, m)
#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_ADDR,v)
#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_IN)
#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK                                             0x2
#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT                                             0x1
#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_SW_OVERRIDE_BMSK                                                  0x1
#define HWIO_GCC_APCS_TZ_UFS_PHY_SGDSCR_SW_OVERRIDE_SHFT                                                  0x0

#define HWIO_GCC_APCS_TZ_PCIE_2_SGDSCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00053010)
#define HWIO_GCC_APCS_TZ_PCIE_2_SGDSCR_RMSK                                                               0x3
#define HWIO_GCC_APCS_TZ_PCIE_2_SGDSCR_IN          \
        in_dword(HWIO_GCC_APCS_TZ_PCIE_2_SGDSCR_ADDR)
#define HWIO_GCC_APCS_TZ_PCIE_2_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_PCIE_2_SGDSCR_ADDR, m)
#define HWIO_GCC_APCS_TZ_PCIE_2_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_PCIE_2_SGDSCR_ADDR,v)
#define HWIO_GCC_APCS_TZ_PCIE_2_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_PCIE_2_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_PCIE_2_SGDSCR_IN)
#define HWIO_GCC_APCS_TZ_PCIE_2_SGDSCR_RETAIN_FF_ENABLE_BMSK                                              0x2
#define HWIO_GCC_APCS_TZ_PCIE_2_SGDSCR_RETAIN_FF_ENABLE_SHFT                                              0x1
#define HWIO_GCC_APCS_TZ_PCIE_2_SGDSCR_SW_OVERRIDE_BMSK                                                   0x1
#define HWIO_GCC_APCS_TZ_PCIE_2_SGDSCR_SW_OVERRIDE_SHFT                                                   0x0

#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00053014)
#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_RMSK                                                               0x3
#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_IN          \
        in_dword(HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_ADDR)
#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_ADDR, m)
#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_ADDR,v)
#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_IN)
#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_BMSK                                              0x2
#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_SHFT                                              0x1
#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_SW_OVERRIDE_BMSK                                                   0x1
#define HWIO_GCC_APCS_TZ_PCIE_0_SGDSCR_SW_OVERRIDE_SHFT                                                   0x0

#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00053018)
#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_RMSK                                                               0x3
#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_IN          \
        in_dword(HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_ADDR)
#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_ADDR, m)
#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_ADDR,v)
#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_IN)
#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_BMSK                                              0x2
#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_SHFT                                              0x1
#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_SW_OVERRIDE_BMSK                                                   0x1
#define HWIO_GCC_APCS_TZ_PCIE_1_SGDSCR_SW_OVERRIDE_SHFT                                                   0x0

#define HWIO_GCC_APCS_TZ_USB30_SEC_SGDSCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0005301c)
#define HWIO_GCC_APCS_TZ_USB30_SEC_SGDSCR_RMSK                                                            0x3
#define HWIO_GCC_APCS_TZ_USB30_SEC_SGDSCR_IN          \
        in_dword(HWIO_GCC_APCS_TZ_USB30_SEC_SGDSCR_ADDR)
#define HWIO_GCC_APCS_TZ_USB30_SEC_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_USB30_SEC_SGDSCR_ADDR, m)
#define HWIO_GCC_APCS_TZ_USB30_SEC_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_USB30_SEC_SGDSCR_ADDR,v)
#define HWIO_GCC_APCS_TZ_USB30_SEC_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_USB30_SEC_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_USB30_SEC_SGDSCR_IN)
#define HWIO_GCC_APCS_TZ_USB30_SEC_SGDSCR_RETAIN_FF_ENABLE_BMSK                                           0x2
#define HWIO_GCC_APCS_TZ_USB30_SEC_SGDSCR_RETAIN_FF_ENABLE_SHFT                                           0x1
#define HWIO_GCC_APCS_TZ_USB30_SEC_SGDSCR_SW_OVERRIDE_BMSK                                                0x1
#define HWIO_GCC_APCS_TZ_USB30_SEC_SGDSCR_SW_OVERRIDE_SHFT                                                0x0

#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00053020)
#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_RMSK                                                                0x3
#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_IN          \
        in_dword(HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_ADDR)
#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_ADDR, m)
#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_ADDR,v)
#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_ADDR,m,v,HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_IN)
#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_RETAIN_FF_ENABLE_BMSK                                               0x2
#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_RETAIN_FF_ENABLE_SHFT                                               0x1
#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_SW_OVERRIDE_BMSK                                                    0x1
#define HWIO_GCC_APCS_TZ_MMNOC_SGDSCR_SW_OVERRIDE_SHFT                                                    0x0

#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00035000)
#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_RMSK                                                                   0x3
#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_IN          \
        in_dword(HWIO_GCC_MSS_Q6_IPA_SGDSCR_ADDR)
#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_IPA_SGDSCR_ADDR, m)
#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_IPA_SGDSCR_ADDR,v)
#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_IPA_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_IPA_SGDSCR_IN)
#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_RETAIN_FF_ENABLE_BMSK                                                  0x2
#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_RETAIN_FF_ENABLE_SHFT                                                  0x1
#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_SW_OVERRIDE_BMSK                                                       0x1
#define HWIO_GCC_MSS_Q6_IPA_SGDSCR_SW_OVERRIDE_SHFT                                                       0x0

#define HWIO_GCC_MSS_Q6_UFS_CARD_SGDSCR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00035004)
#define HWIO_GCC_MSS_Q6_UFS_CARD_SGDSCR_RMSK                                                              0x3
#define HWIO_GCC_MSS_Q6_UFS_CARD_SGDSCR_IN          \
        in_dword(HWIO_GCC_MSS_Q6_UFS_CARD_SGDSCR_ADDR)
#define HWIO_GCC_MSS_Q6_UFS_CARD_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_UFS_CARD_SGDSCR_ADDR, m)
#define HWIO_GCC_MSS_Q6_UFS_CARD_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_UFS_CARD_SGDSCR_ADDR,v)
#define HWIO_GCC_MSS_Q6_UFS_CARD_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_UFS_CARD_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_UFS_CARD_SGDSCR_IN)
#define HWIO_GCC_MSS_Q6_UFS_CARD_SGDSCR_RETAIN_FF_ENABLE_BMSK                                             0x2
#define HWIO_GCC_MSS_Q6_UFS_CARD_SGDSCR_RETAIN_FF_ENABLE_SHFT                                             0x1
#define HWIO_GCC_MSS_Q6_UFS_CARD_SGDSCR_SW_OVERRIDE_BMSK                                                  0x1
#define HWIO_GCC_MSS_Q6_UFS_CARD_SGDSCR_SW_OVERRIDE_SHFT                                                  0x0

#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00035008)
#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_RMSK                                                            0x3
#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_IN          \
        in_dword(HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_ADDR)
#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_ADDR, m)
#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_ADDR,v)
#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_IN)
#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_BMSK                                           0x2
#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_RETAIN_FF_ENABLE_SHFT                                           0x1
#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_SW_OVERRIDE_BMSK                                                0x1
#define HWIO_GCC_MSS_Q6_USB30_PRIM_SGDSCR_SW_OVERRIDE_SHFT                                                0x0

#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0003500c)
#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_RMSK                                                               0x3
#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_IN          \
        in_dword(HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_ADDR)
#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_ADDR, m)
#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_ADDR,v)
#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_IN)
#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_BMSK                                              0x2
#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_RETAIN_FF_ENABLE_SHFT                                              0x1
#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_SW_OVERRIDE_BMSK                                                   0x1
#define HWIO_GCC_MSS_Q6_UFS_PHY_SGDSCR_SW_OVERRIDE_SHFT                                                   0x0

#define HWIO_GCC_MSS_Q6_PCIE_2_SGDSCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00035010)
#define HWIO_GCC_MSS_Q6_PCIE_2_SGDSCR_RMSK                                                                0x3
#define HWIO_GCC_MSS_Q6_PCIE_2_SGDSCR_IN          \
        in_dword(HWIO_GCC_MSS_Q6_PCIE_2_SGDSCR_ADDR)
#define HWIO_GCC_MSS_Q6_PCIE_2_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_PCIE_2_SGDSCR_ADDR, m)
#define HWIO_GCC_MSS_Q6_PCIE_2_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_PCIE_2_SGDSCR_ADDR,v)
#define HWIO_GCC_MSS_Q6_PCIE_2_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_PCIE_2_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_PCIE_2_SGDSCR_IN)
#define HWIO_GCC_MSS_Q6_PCIE_2_SGDSCR_RETAIN_FF_ENABLE_BMSK                                               0x2
#define HWIO_GCC_MSS_Q6_PCIE_2_SGDSCR_RETAIN_FF_ENABLE_SHFT                                               0x1
#define HWIO_GCC_MSS_Q6_PCIE_2_SGDSCR_SW_OVERRIDE_BMSK                                                    0x1
#define HWIO_GCC_MSS_Q6_PCIE_2_SGDSCR_SW_OVERRIDE_SHFT                                                    0x0

#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00035014)
#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_RMSK                                                                0x3
#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_IN          \
        in_dword(HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_ADDR)
#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_ADDR, m)
#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_ADDR,v)
#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_IN)
#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_BMSK                                               0x2
#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_RETAIN_FF_ENABLE_SHFT                                               0x1
#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_SW_OVERRIDE_BMSK                                                    0x1
#define HWIO_GCC_MSS_Q6_PCIE_0_SGDSCR_SW_OVERRIDE_SHFT                                                    0x0

#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00035018)
#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_RMSK                                                                0x3
#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_IN          \
        in_dword(HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_ADDR)
#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_ADDR, m)
#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_ADDR,v)
#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_IN)
#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_BMSK                                               0x2
#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_RETAIN_FF_ENABLE_SHFT                                               0x1
#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_SW_OVERRIDE_BMSK                                                    0x1
#define HWIO_GCC_MSS_Q6_PCIE_1_SGDSCR_SW_OVERRIDE_SHFT                                                    0x0

#define HWIO_GCC_MSS_Q6_USB30_SEC_SGDSCR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0003501c)
#define HWIO_GCC_MSS_Q6_USB30_SEC_SGDSCR_RMSK                                                             0x3
#define HWIO_GCC_MSS_Q6_USB30_SEC_SGDSCR_IN          \
        in_dword(HWIO_GCC_MSS_Q6_USB30_SEC_SGDSCR_ADDR)
#define HWIO_GCC_MSS_Q6_USB30_SEC_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_USB30_SEC_SGDSCR_ADDR, m)
#define HWIO_GCC_MSS_Q6_USB30_SEC_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_USB30_SEC_SGDSCR_ADDR,v)
#define HWIO_GCC_MSS_Q6_USB30_SEC_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_USB30_SEC_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_USB30_SEC_SGDSCR_IN)
#define HWIO_GCC_MSS_Q6_USB30_SEC_SGDSCR_RETAIN_FF_ENABLE_BMSK                                            0x2
#define HWIO_GCC_MSS_Q6_USB30_SEC_SGDSCR_RETAIN_FF_ENABLE_SHFT                                            0x1
#define HWIO_GCC_MSS_Q6_USB30_SEC_SGDSCR_SW_OVERRIDE_BMSK                                                 0x1
#define HWIO_GCC_MSS_Q6_USB30_SEC_SGDSCR_SW_OVERRIDE_SHFT                                                 0x0

#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00035020)
#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_RMSK                                                                 0x3
#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_IN          \
        in_dword(HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_ADDR)
#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_ADDR, m)
#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_ADDR,v)
#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_ADDR,m,v,HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_IN)
#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_RETAIN_FF_ENABLE_BMSK                                                0x2
#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_RETAIN_FF_ENABLE_SHFT                                                0x1
#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_SW_OVERRIDE_BMSK                                                     0x1
#define HWIO_GCC_MSS_Q6_MMNOC_SGDSCR_SW_OVERRIDE_SHFT                                                     0x0

#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007503c)
#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_RMSK                                                    0x1
#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_IN)
#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_CLK_ENABLE_BMSK                                         0x1
#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_CLK_ENABLE_SHFT                                         0x0

#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007504c)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_RMSK                                                    0x1
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_IN)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_CLK_ENABLE_BMSK                                         0x1
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_CLK_ENABLE_SHFT                                         0x0

#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x000750bc)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_RMSK                                                    0x1
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_IN)
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_CLK_ENABLE_BMSK                                         0x1
#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_CLK_ENABLE_SHFT                                         0x0

#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0007703c)
#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_RMSK                                                     0x1
#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_IN)
#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_CLK_ENABLE_BMSK                                          0x1
#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_CLK_ENABLE_SHFT                                          0x0

#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0007704c)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_RMSK                                                     0x1
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_IN)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_CLK_ENABLE_BMSK                                          0x1
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_CLK_ENABLE_SHFT                                          0x0

#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x000770bc)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_RMSK                                                     0x1
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_IN          \
        in_dword(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_ADDR)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_ADDR, m)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_ADDR,v)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_ADDR,m,v,HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_IN)
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_CLK_ENABLE_BMSK                                          0x1
#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_CLK_ENABLE_SHFT                                          0x0

#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0000f060)
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_RMSK                                                             0x3
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_IN          \
        in_dword(HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_ADDR)
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_ADDR, m)
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_ADDR,v)
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_ADDR,m,v,HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_IN)
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_MUX_SEL_BMSK                                                     0x3
#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_MUX_SEL_SHFT                                                     0x0

#define HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00010060)
#define HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_RMSK                                                              0x3
#define HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_IN          \
        in_dword(HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_ADDR)
#define HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_ADDR, m)
#define HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_ADDR,v)
#define HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_ADDR,m,v,HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_IN)
#define HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_MUX_SEL_BMSK                                                      0x3
#define HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_MUX_SEL_SHFT                                                      0x0

#define HWIO_GCC_PCIE_0_PIPE_MUXR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0006b034)
#define HWIO_GCC_PCIE_0_PIPE_MUXR_RMSK                                                                    0x3
#define HWIO_GCC_PCIE_0_PIPE_MUXR_IN          \
        in_dword(HWIO_GCC_PCIE_0_PIPE_MUXR_ADDR)
#define HWIO_GCC_PCIE_0_PIPE_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_PIPE_MUXR_ADDR, m)
#define HWIO_GCC_PCIE_0_PIPE_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_PIPE_MUXR_ADDR,v)
#define HWIO_GCC_PCIE_0_PIPE_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_PIPE_MUXR_ADDR,m,v,HWIO_GCC_PCIE_0_PIPE_MUXR_IN)
#define HWIO_GCC_PCIE_0_PIPE_MUXR_MUX_SEL_BMSK                                                            0x3
#define HWIO_GCC_PCIE_0_PIPE_MUXR_MUX_SEL_SHFT                                                            0x0

#define HWIO_GCC_PCIE_1_PIPE_MUXR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0008d034)
#define HWIO_GCC_PCIE_1_PIPE_MUXR_RMSK                                                                    0x3
#define HWIO_GCC_PCIE_1_PIPE_MUXR_IN          \
        in_dword(HWIO_GCC_PCIE_1_PIPE_MUXR_ADDR)
#define HWIO_GCC_PCIE_1_PIPE_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_PIPE_MUXR_ADDR, m)
#define HWIO_GCC_PCIE_1_PIPE_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_PIPE_MUXR_ADDR,v)
#define HWIO_GCC_PCIE_1_PIPE_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_PIPE_MUXR_ADDR,m,v,HWIO_GCC_PCIE_1_PIPE_MUXR_IN)
#define HWIO_GCC_PCIE_1_PIPE_MUXR_MUX_SEL_BMSK                                                            0x3
#define HWIO_GCC_PCIE_1_PIPE_MUXR_MUX_SEL_SHFT                                                            0x0

#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_ADDR                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00075044)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_RMSK                                 0x1
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_IN          \
        in_dword(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_ADDR)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_ADDR, m)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_ADDR,v)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_ADDR,m,v,HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_IN)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_MUX_SEL_BMSK                         0x1
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_MUX_SEL_SHFT                         0x0

#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00075048)
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_RMSK                                                           0x3
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_ADDR)
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_ADDR, m)
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_ADDR,v)
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_ADDR,m,v,HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_IN)
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_MUX_SEL_BMSK                                                   0x3
#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_MUX_SEL_SHFT                                                   0x0

#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_ADDR                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00075054)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_RMSK                                 0x1
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_IN          \
        in_dword(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_ADDR)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_ADDR, m)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_ADDR,v)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_ADDR,m,v,HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_IN)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_MUX_SEL_BMSK                         0x1
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_MUX_SEL_SHFT                         0x0

#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00075058)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_RMSK                                                           0x3
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_ADDR)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_ADDR, m)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_ADDR,v)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_ADDR,m,v,HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_IN)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_MUX_SEL_BMSK                                                   0x3
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_MUX_SEL_SHFT                                                   0x0

#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_ADDR                          (GCC_CLK_CTL_REG_REG_BASE      + 0x000750c4)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_RMSK                                 0x1
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_IN          \
        in_dword(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_ADDR)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_ADDR, m)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_ADDR,v)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_ADDR,m,v,HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_IN)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_MUX_SEL_BMSK                         0x1
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_MUX_SEL_SHFT                         0x0

#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x000750c8)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_RMSK                                                           0x3
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_IN          \
        in_dword(HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_ADDR)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_ADDR, m)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_ADDR,v)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_ADDR,m,v,HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_IN)
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_MUX_SEL_BMSK                                                   0x3
#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_MUX_SEL_SHFT                                                   0x0

#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00077044)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_RMSK                                  0x1
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_IN          \
        in_dword(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_ADDR)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_ADDR, m)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_ADDR,v)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_ADDR,m,v,HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_IN)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_MUX_SEL_BMSK                          0x1
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_MUX_SEL_SHFT                          0x0

#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00077048)
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_RMSK                                                            0x3
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_ADDR)
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_ADDR, m)
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_ADDR,v)
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_ADDR,m,v,HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_IN)
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_MUX_SEL_BMSK                                                    0x3
#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_MUX_SEL_SHFT                                                    0x0

#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00077054)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_RMSK                                  0x1
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_IN          \
        in_dword(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_ADDR)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_ADDR, m)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_ADDR,v)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_ADDR,m,v,HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_IN)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_MUX_SEL_BMSK                          0x1
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_MUX_SEL_SHFT                          0x0

#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00077058)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_RMSK                                                            0x3
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_ADDR)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_ADDR, m)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_ADDR,v)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_ADDR,m,v,HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_IN)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_MUX_SEL_BMSK                                                    0x3
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_MUX_SEL_SHFT                                                    0x0

#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_ADDR                           (GCC_CLK_CTL_REG_REG_BASE      + 0x000770c4)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_RMSK                                  0x1
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_IN          \
        in_dword(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_ADDR)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_ADDR, m)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_ADDR,v)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_ADDR,m,v,HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_IN)
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_MUX_SEL_BMSK                          0x1
#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_MUX_SEL_SHFT                          0x0

#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x000770c8)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_RMSK                                                            0x3
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_IN          \
        in_dword(HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_ADDR)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_ADDR, m)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_ADDR,v)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_ADDR,m,v,HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_IN)
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_MUX_SEL_BMSK                                                    0x3
#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_MUX_SEL_SHFT                                                    0x0

#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0008a148)
#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_RMSK                                                            0x1
#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_IN          \
        in_dword(HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR)
#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR, m)
#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR,v)
#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR,m,v,HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_IN)
#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_MUX_SEL_BMSK                                                    0x1
#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_MUX_SEL_SHFT                                                    0x0

#define HWIO_GCC_PCIE_2_PIPE_MUXR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00006034)
#define HWIO_GCC_PCIE_2_PIPE_MUXR_RMSK                                                                    0x3
#define HWIO_GCC_PCIE_2_PIPE_MUXR_IN          \
        in_dword(HWIO_GCC_PCIE_2_PIPE_MUXR_ADDR)
#define HWIO_GCC_PCIE_2_PIPE_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_PIPE_MUXR_ADDR, m)
#define HWIO_GCC_PCIE_2_PIPE_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_PIPE_MUXR_ADDR,v)
#define HWIO_GCC_PCIE_2_PIPE_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_PIPE_MUXR_ADDR,m,v,HWIO_GCC_PCIE_2_PIPE_MUXR_IN)
#define HWIO_GCC_PCIE_2_PIPE_MUXR_MUX_SEL_BMSK                                                            0x3
#define HWIO_GCC_PCIE_2_PIPE_MUXR_MUX_SEL_SHFT                                                            0x0

#define HWIO_GCC_ACC_MISC_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0003e030)
#define HWIO_GCC_ACC_MISC_RMSK                                                                            0x1
#define HWIO_GCC_ACC_MISC_IN          \
        in_dword(HWIO_GCC_ACC_MISC_ADDR)
#define HWIO_GCC_ACC_MISC_INM(m)      \
        in_dword_masked(HWIO_GCC_ACC_MISC_ADDR, m)
#define HWIO_GCC_ACC_MISC_OUT(v)      \
        out_dword(HWIO_GCC_ACC_MISC_ADDR,v)
#define HWIO_GCC_ACC_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_ACC_MISC_ADDR,m,v,HWIO_GCC_ACC_MISC_IN)
#define HWIO_GCC_ACC_MISC_JTAG_ACC_SRC_SEL_EN_BMSK                                                        0x1
#define HWIO_GCC_ACC_MISC_JTAG_ACC_SRC_SEL_EN_SHFT                                                        0x0

#define HWIO_GCC_CPUSS_AHB_MISC_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00048024)
#define HWIO_GCC_CPUSS_AHB_MISC_RMSK                                                                     0xf1
#define HWIO_GCC_CPUSS_AHB_MISC_IN          \
        in_dword(HWIO_GCC_CPUSS_AHB_MISC_ADDR)
#define HWIO_GCC_CPUSS_AHB_MISC_INM(m)      \
        in_dword_masked(HWIO_GCC_CPUSS_AHB_MISC_ADDR, m)
#define HWIO_GCC_CPUSS_AHB_MISC_OUT(v)      \
        out_dword(HWIO_GCC_CPUSS_AHB_MISC_ADDR,v)
#define HWIO_GCC_CPUSS_AHB_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CPUSS_AHB_MISC_ADDR,m,v,HWIO_GCC_CPUSS_AHB_MISC_IN)
#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_BMSK                                        0xf0
#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIV_SHFT                                         0x4
#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIS_BMSK                                         0x1
#define HWIO_GCC_CPUSS_AHB_MISC_CPUSS_AHB_CLK_AUTO_SCALE_DIS_SHFT                                         0x0

#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00051000)
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_RMSK                                                    0x7f2fed7f
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK                                0x40000000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT                                      0x1e
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK                                 0x20000000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT                                       0x1d
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK                             0x10000000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT                                   0x1c
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK                             0x8000000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT                                  0x1b
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK                              0x4000000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT                                   0x1a
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK                          0x2000000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT                               0x19
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK                                    0x1000000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT                                         0x18
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK                                    0x200000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT                                        0x15
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                             0x80000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                                0x13
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_BMSK                                 0x40000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_SHFT                                    0x12
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK                             0x20000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT                                0x11
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                             0x10000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                                0x10
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK                                  0x8000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT                                     0xf
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_BMSK                                  0x4000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_SHFT                                     0xe
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK                                       0x2000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT                                          0xd
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_BMSK                                  0x800
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_SHFT                                    0xb
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK                                    0x400
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT                                      0xa
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_BMSK                                  0x100
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_SHFT                                    0x8
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK                                             0x40
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT                                              0x6
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK                                              0x20
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT                                               0x5
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK                                          0x10
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT                                           0x4
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK                                           0x8
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT                                           0x3
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK                                      0x4
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT                                      0x2
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK                                          0x2
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT                                          0x1
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK                                 0x1
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT                                 0x0

#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00051004)
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_RMSK                                                     0x7f2fed7f
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK                           0x40000000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT                                 0x1e
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK                            0x20000000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT                                  0x1d
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK                        0x10000000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT                              0x1c
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK                        0x8000000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT                             0x1b
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK                         0x4000000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT                              0x1a
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                     0x2000000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                          0x19
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK                               0x1000000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT                                    0x18
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                               0x200000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                                   0x15
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                        0x80000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                           0x13
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                            0x40000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                               0x12
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                        0x20000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                           0x11
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                        0x10000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                           0x10
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                             0x8000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                                0xf
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_BMSK                             0x4000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_SHFT                                0xe
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK                                  0x2000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT                                     0xd
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_BMSK                             0x800
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_SHFT                               0xb
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK                               0x400
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT                                 0xa
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_BMSK                             0x100
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_SHFT                               0x8
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK                                        0x40
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT                                         0x6
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK                                         0x20
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT                                          0x5
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK                                     0x10
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT                                      0x4
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK                                      0x8
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT                                      0x3
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK                                 0x4
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT                                 0x2
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK                                     0x2
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT                                     0x1
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                            0x1
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                            0x0

#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00051008)
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_RMSK                                                   0xfffffff
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR)
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_IN)
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK                            0x8000000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT                                 0x1b
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK                            0x4000000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT                                 0x1a
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK                            0x2000000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT                                 0x19
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK                            0x1000000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT                                 0x18
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK                             0x800000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT                                 0x17
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK                             0x400000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT                                 0x16
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK                         0x200000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT                             0x15
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK                         0x100000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT                             0x14
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK                            0x80000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT                               0x13
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK                         0x40000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT                            0x12
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_BMSK                              0x20000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_SHFT                                 0x11
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_BMSK                              0x10000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_SHFT                                 0x10
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_BMSK                               0x8000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_SHFT                                  0xf
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_BMSK                               0x4000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_SHFT                                  0xe
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_BMSK                               0x2000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_SHFT                                  0xd
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_BMSK                               0x1000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_SHFT                                  0xc
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_BMSK                                0x800
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_SHFT                                  0xb
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_BMSK                                0x400
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_SHFT                                  0xa
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_BMSK                           0x200
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_SHFT                             0x9
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_BMSK                              0x100
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_SHFT                                0x8
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_BMSK                             0x80
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_SHFT                              0x7
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_BMSK                             0x40
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_SHFT                              0x6
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK                             0x20
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT                              0x5
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK                                    0x10
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT                                     0x4
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK                                      0x8
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT                                      0x3
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK                                  0x4
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT                                  0x2
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK                                 0x2
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT                                 0x1
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK                                  0x1
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT                                  0x0

#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0005100c)
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_RMSK                                                    0xfffffff
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR)
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_IN)
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK                       0x8000000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT                            0x1b
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK                       0x4000000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT                            0x1a
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK                       0x2000000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT                            0x19
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK                       0x1000000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT                            0x18
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK                        0x800000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT                            0x17
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK                        0x400000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT                            0x16
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK                    0x200000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT                        0x15
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK                    0x100000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT                        0x14
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK                       0x80000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT                          0x13
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK                    0x40000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT                       0x12
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_BMSK                         0x20000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_SHFT                            0x11
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_BMSK                         0x10000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_SHFT                            0x10
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_BMSK                          0x8000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_SHFT                             0xf
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_BMSK                          0x4000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_SHFT                             0xe
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_BMSK                          0x2000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_SHFT                             0xd
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_BMSK                          0x1000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_SHFT                             0xc
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_BMSK                           0x800
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_SHFT                             0xb
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_BMSK                           0x400
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_SHFT                             0xa
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_BMSK                      0x200
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_SHFT                        0x9
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_BMSK                         0x100
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_SHFT                           0x8
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_BMSK                        0x80
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_SHFT                         0x7
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_BMSK                        0x40
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_SHFT                         0x6
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                        0x20
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                         0x5
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK                               0x10
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT                                0x4
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK                                 0x8
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT                                 0x3
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK                             0x4
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT                             0x2
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK                            0x2
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT                            0x1
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK                             0x1
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT                             0x0

#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00051010)
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_RMSK                                                      0xffff
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ADDR)
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_IN)
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_BMSK                                  0x8000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_SHFT                                     0xf
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_BMSK                                   0x4000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_SHFT                                      0xe
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_BMSK                               0x2000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_SHFT                                  0xd
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_BMSK                              0x1000
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_SHFT                                 0xc
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_BMSK                                0x800
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_SHFT                                  0xb
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_BMSK                            0x400
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_SHFT                              0xa
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK                                0x200
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT                                  0x9
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK                                0x100
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT                                  0x8
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK                                 0x80
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT                                  0x7
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK                                 0x40
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT                                  0x6
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK                                 0x20
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT                                  0x5
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK                                 0x10
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT                                  0x4
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK                             0x8
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT                             0x3
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK                              0x4
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT                              0x2
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK                              0x2
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT                              0x1
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK                                0x1
#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT                                0x0

#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00051014)
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_RMSK                                                       0xffff
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ADDR)
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_IN)
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_BMSK                             0x8000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_SHFT                                0xf
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_BMSK                              0x4000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_SHFT                                 0xe
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_BMSK                          0x2000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_SHFT                             0xd
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_BMSK                         0x1000
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_SHFT                            0xc
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_BMSK                           0x800
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_SHFT                             0xb
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                       0x400
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                         0xa
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK                           0x200
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT                             0x9
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK                           0x100
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT                             0x8
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK                            0x80
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT                             0x7
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK                            0x40
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT                             0x6
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK                            0x20
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT                             0x5
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK                            0x10
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT                             0x4
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK                        0x8
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT                        0x3
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK                         0x4
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT                         0x2
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK                         0x2
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT                         0x1
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK                           0x1
#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT                           0x0

#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00051018)
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_RMSK                                                           0xfff
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL11_BMSK                                                    0x800
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL11_SHFT                                                      0xb
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL10_BMSK                                                    0x400
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL10_SHFT                                                      0xa
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL9_BMSK                                                     0x200
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL9_SHFT                                                       0x9
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL8_BMSK                                                     0x100
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL8_SHFT                                                       0x8
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL7_BMSK                                                      0x80
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL7_SHFT                                                       0x7
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL6_BMSK                                                      0x40
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL6_SHFT                                                       0x6
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL5_BMSK                                                      0x20
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL5_SHFT                                                       0x5
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL4_BMSK                                                      0x10
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL4_SHFT                                                       0x4
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL3_BMSK                                                       0x8
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL3_SHFT                                                       0x3
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL2_BMSK                                                       0x4
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL2_SHFT                                                       0x2
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPM_PLL_BRANCH_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0005101c)
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_RMSK                                                            0xfff
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL11_BMSK                                                     0x800
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL11_SHFT                                                       0xb
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL10_BMSK                                                     0x400
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL10_SHFT                                                       0xa
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL9_BMSK                                                      0x200
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL9_SHFT                                                        0x9
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL8_BMSK                                                      0x100
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL8_SHFT                                                        0x8
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL7_BMSK                                                       0x80
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL7_SHFT                                                        0x7
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL6_BMSK                                                       0x40
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL6_SHFT                                                        0x6
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL5_BMSK                                                       0x20
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL5_SHFT                                                        0x5
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL4_BMSK                                                       0x10
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL4_SHFT                                                        0x4
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL3_BMSK                                                        0x8
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL3_SHFT                                                        0x3
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL2_BMSK                                                        0x4
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL2_SHFT                                                        0x2
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL1_BMSK                                                        0x2
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL1_SHFT                                                        0x1
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL0_BMSK                                                        0x1
#define HWIO_GCC_RPM_PLL_SLEEP_ENA_VOTE_GPLL0_SHFT                                                        0x0

#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00052000)
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_RMSK                                                   0x7f2fed7f
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK                               0x40000000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT                                     0x1e
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK                                0x20000000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT                                      0x1d
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK                            0x10000000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT                                  0x1c
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK                            0x8000000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT                                 0x1b
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK                             0x4000000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT                                  0x1a
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK                         0x2000000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT                              0x19
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK                                   0x1000000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT                                        0x18
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK                                   0x200000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT                                       0x15
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                            0x80000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                               0x13
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_BMSK                                0x40000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_SHFT                                   0x12
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK                            0x20000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT                               0x11
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                            0x10000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                               0x10
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK                                 0x8000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT                                    0xf
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_BMSK                                 0x4000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_SHFT                                    0xe
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK                                      0x2000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT                                         0xd
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_BMSK                                 0x800
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_SHFT                                   0xb
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK                                   0x400
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT                                     0xa
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_BMSK                                 0x100
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_SHFT                                   0x8
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK                                            0x40
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT                                             0x6
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK                                             0x20
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT                                              0x5
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK                                         0x10
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT                                          0x4
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK                                          0x8
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT                                          0x3
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK                                     0x4
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT                                     0x2
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK                                         0x2
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT                                         0x1
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK                                0x1
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT                                0x0

#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00052004)
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_RMSK                                                    0x7f2fed7f
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK                          0x40000000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT                                0x1e
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK                           0x20000000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT                                 0x1d
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK                       0x10000000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT                             0x1c
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK                       0x8000000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT                            0x1b
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK                        0x4000000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT                             0x1a
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                    0x2000000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                         0x19
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK                              0x1000000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT                                   0x18
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                              0x200000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                                  0x15
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                       0x80000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                          0x13
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                           0x40000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                              0x12
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                       0x20000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                          0x11
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                       0x10000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                          0x10
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                            0x8000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                               0xf
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_BMSK                            0x4000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_SHFT                               0xe
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK                                 0x2000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT                                    0xd
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_BMSK                            0x800
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_SHFT                              0xb
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK                              0x400
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT                                0xa
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_BMSK                            0x100
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_SHFT                              0x8
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK                                       0x40
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT                                        0x6
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK                                        0x20
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT                                         0x5
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK                                    0x10
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT                                     0x4
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK                                     0x8
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT                                     0x3
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK                                0x4
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT                                0x2
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK                                    0x2
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT                                    0x1
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                           0x1
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                           0x0

#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00052008)
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_RMSK                                                  0xfffffff
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR)
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_IN)
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK                           0x8000000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT                                0x1b
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK                           0x4000000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT                                0x1a
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK                           0x2000000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT                                0x19
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK                           0x1000000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT                                0x18
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK                            0x800000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT                                0x17
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK                            0x400000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT                                0x16
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK                        0x200000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT                            0x15
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK                        0x100000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT                            0x14
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK                           0x80000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT                              0x13
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK                        0x40000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT                           0x12
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_BMSK                             0x20000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_SHFT                                0x11
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_BMSK                             0x10000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_SHFT                                0x10
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_BMSK                              0x8000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_SHFT                                 0xf
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_BMSK                              0x4000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_SHFT                                 0xe
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_BMSK                              0x2000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_SHFT                                 0xd
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_BMSK                              0x1000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_SHFT                                 0xc
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_BMSK                               0x800
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_SHFT                                 0xb
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_BMSK                               0x400
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_SHFT                                 0xa
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_BMSK                          0x200
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_SHFT                            0x9
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_BMSK                             0x100
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_SHFT                               0x8
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_BMSK                            0x80
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_SHFT                             0x7
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_BMSK                            0x40
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_SHFT                             0x6
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK                            0x20
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT                             0x5
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK                                   0x10
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT                                    0x4
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK                                     0x8
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT                                     0x3
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK                                 0x4
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT                                 0x2
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK                                0x2
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT                                0x1
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK                                 0x1
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT                                 0x0

#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0005200c)
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_RMSK                                                   0xfffffff
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR)
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_IN)
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK                      0x8000000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT                           0x1b
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK                      0x4000000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT                           0x1a
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK                      0x2000000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT                           0x19
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK                      0x1000000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT                           0x18
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK                       0x800000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT                           0x17
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK                       0x400000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT                           0x16
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK                   0x200000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT                       0x15
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK                   0x100000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT                       0x14
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK                      0x80000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT                         0x13
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK                   0x40000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT                      0x12
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_BMSK                        0x20000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_SHFT                           0x11
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_BMSK                        0x10000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_SHFT                           0x10
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_BMSK                         0x8000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_SHFT                            0xf
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_BMSK                         0x4000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_SHFT                            0xe
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_BMSK                         0x2000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_SHFT                            0xd
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_BMSK                         0x1000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_SHFT                            0xc
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_BMSK                          0x800
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_SHFT                            0xb
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_BMSK                          0x400
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_SHFT                            0xa
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_BMSK                     0x200
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_SHFT                       0x9
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_BMSK                        0x100
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_SHFT                          0x8
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_BMSK                       0x80
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_SHFT                        0x7
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_BMSK                       0x40
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_SHFT                        0x6
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                       0x20
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                        0x5
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK                              0x10
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT                               0x4
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK                                0x8
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT                                0x3
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK                            0x4
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT                            0x2
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK                           0x2
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT                           0x1
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK                            0x1
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT                            0x0

#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00052010)
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_RMSK                                                     0xffff
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ADDR)
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_IN)
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_BMSK                                 0x8000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_SHFT                                    0xf
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_BMSK                                  0x4000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_SHFT                                     0xe
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_BMSK                              0x2000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_SHFT                                 0xd
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_BMSK                             0x1000
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_SHFT                                0xc
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_BMSK                               0x800
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_SHFT                                 0xb
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_BMSK                           0x400
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_SHFT                             0xa
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK                               0x200
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT                                 0x9
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK                               0x100
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT                                 0x8
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK                                0x80
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT                                 0x7
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK                                0x40
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT                                 0x6
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK                                0x20
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT                                 0x5
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK                                0x10
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT                                 0x4
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK                            0x8
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT                            0x3
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK                             0x4
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT                             0x2
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK                             0x2
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT                             0x1
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK                               0x1
#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT                               0x0

#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00052014)
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_RMSK                                                      0xffff
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ADDR)
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_IN)
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_BMSK                            0x8000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_SHFT                               0xf
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_BMSK                             0x4000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_SHFT                                0xe
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_BMSK                         0x2000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_SHFT                            0xd
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_BMSK                        0x1000
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_SHFT                           0xc
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_BMSK                          0x800
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_SHFT                            0xb
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                      0x400
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                        0xa
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK                          0x200
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT                            0x9
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK                          0x100
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT                            0x8
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK                           0x80
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT                            0x7
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK                           0x40
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT                            0x6
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK                           0x20
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT                            0x5
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK                           0x10
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT                            0x4
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK                       0x8
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT                       0x3
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK                        0x4
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT                        0x2
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK                        0x2
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT                        0x1
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK                          0x1
#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT                          0x0

#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00052018)
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_RMSK                                                          0xfff
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL11_BMSK                                                   0x800
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL11_SHFT                                                     0xb
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL10_BMSK                                                   0x400
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL10_SHFT                                                     0xa
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL9_BMSK                                                    0x200
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL9_SHFT                                                      0x9
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL8_BMSK                                                    0x100
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL8_SHFT                                                      0x8
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL7_BMSK                                                     0x80
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL7_SHFT                                                      0x7
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL6_BMSK                                                     0x40
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL6_SHFT                                                      0x6
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL5_BMSK                                                     0x20
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL5_SHFT                                                      0x5
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL4_BMSK                                                     0x10
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL4_SHFT                                                      0x4
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL3_BMSK                                                      0x8
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL3_SHFT                                                      0x3
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL2_BMSK                                                      0x4
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL2_SHFT                                                      0x2
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_APCS_PLL_BRANCH_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0005201c)
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_RMSK                                                           0xfff
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL11_BMSK                                                    0x800
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL11_SHFT                                                      0xb
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL10_BMSK                                                    0x400
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL10_SHFT                                                      0xa
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL9_BMSK                                                     0x200
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL9_SHFT                                                       0x9
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL8_BMSK                                                     0x100
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL8_SHFT                                                       0x8
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL7_BMSK                                                      0x80
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL7_SHFT                                                       0x7
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL6_BMSK                                                      0x40
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL6_SHFT                                                       0x6
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL5_BMSK                                                      0x20
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL5_SHFT                                                       0x5
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL4_BMSK                                                      0x10
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL4_SHFT                                                       0x4
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL3_BMSK                                                       0x8
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL3_SHFT                                                       0x3
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL2_BMSK                                                       0x4
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL2_SHFT                                                       0x2
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_APCS_PLL_SLEEP_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00053024)
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_RMSK                                                0x7f2fed7f
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK                            0x40000000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT                                  0x1e
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK                             0x20000000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT                                   0x1d
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK                         0x10000000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT                               0x1c
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK                         0x8000000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT                              0x1b
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK                          0x4000000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT                               0x1a
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK                      0x2000000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT                           0x19
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK                                0x1000000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT                                     0x18
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK                                0x200000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT                                    0x15
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                         0x80000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                            0x13
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_BMSK                             0x40000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_SHFT                                0x12
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK                         0x20000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT                            0x11
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                         0x10000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                            0x10
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK                              0x8000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT                                 0xf
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_BMSK                              0x4000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_SHFT                                 0xe
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK                                   0x2000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT                                      0xd
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_BMSK                              0x800
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_SHFT                                0xb
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK                                0x400
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT                                  0xa
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_BMSK                              0x100
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_SHFT                                0x8
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK                                         0x40
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT                                          0x6
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK                                          0x20
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT                                           0x5
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK                                      0x10
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT                                       0x4
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK                                       0x8
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT                                       0x3
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK                                  0x4
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT                                  0x2
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK                                      0x2
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT                                      0x1
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK                             0x1
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT                             0x0

#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00053028)
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_RMSK                                                 0x7f2fed7f
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK                       0x40000000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT                             0x1e
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK                        0x20000000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT                              0x1d
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK                    0x10000000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT                          0x1c
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK                    0x8000000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT                         0x1b
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK                     0x4000000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT                          0x1a
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                 0x2000000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                      0x19
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK                           0x1000000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT                                0x18
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                           0x200000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                               0x15
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                    0x80000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                       0x13
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                        0x40000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                           0x12
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                    0x20000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                       0x11
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                    0x10000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                       0x10
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                         0x8000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                            0xf
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_BMSK                         0x4000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_SHFT                            0xe
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK                              0x2000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT                                 0xd
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_BMSK                         0x800
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_SHFT                           0xb
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK                           0x400
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT                             0xa
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_BMSK                         0x100
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_SHFT                           0x8
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK                                    0x40
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT                                     0x6
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK                                     0x20
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT                                      0x5
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK                                 0x10
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT                                  0x4
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK                                  0x8
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT                                  0x3
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK                             0x4
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT                             0x2
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK                                 0x2
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT                                 0x1
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                        0x1
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                        0x0

#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0005302c)
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_RMSK                                               0xfffffff
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR)
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_IN)
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK                        0x8000000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT                             0x1b
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK                        0x4000000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT                             0x1a
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK                        0x2000000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT                             0x19
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK                        0x1000000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT                             0x18
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK                         0x800000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT                             0x17
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK                         0x400000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT                             0x16
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK                     0x200000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT                         0x15
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK                     0x100000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT                         0x14
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK                        0x80000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT                           0x13
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK                     0x40000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT                        0x12
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_BMSK                          0x20000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_SHFT                             0x11
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_BMSK                          0x10000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_SHFT                             0x10
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_BMSK                           0x8000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_SHFT                              0xf
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_BMSK                           0x4000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_SHFT                              0xe
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_BMSK                           0x2000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_SHFT                              0xd
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_BMSK                           0x1000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_SHFT                              0xc
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_BMSK                            0x800
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_SHFT                              0xb
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_BMSK                            0x400
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_SHFT                              0xa
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_BMSK                       0x200
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_SHFT                         0x9
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_BMSK                          0x100
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_SHFT                            0x8
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_BMSK                         0x80
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_SHFT                          0x7
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_BMSK                         0x40
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_SHFT                          0x6
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK                         0x20
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT                          0x5
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK                                0x10
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT                                 0x4
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK                                  0x8
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT                                  0x3
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK                              0x4
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT                              0x2
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK                             0x2
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT                             0x1
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK                              0x1
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT                              0x0

#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00053030)
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_RMSK                                                0xfffffff
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR)
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_IN)
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK                   0x8000000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT                        0x1b
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK                   0x4000000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT                        0x1a
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK                   0x2000000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT                        0x19
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK                   0x1000000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT                        0x18
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK                    0x800000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT                        0x17
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK                    0x400000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT                        0x16
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK                0x200000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT                    0x15
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK                0x100000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT                    0x14
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK                   0x80000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT                      0x13
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK                0x40000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT                   0x12
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_BMSK                     0x20000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_SHFT                        0x11
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_BMSK                     0x10000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_SHFT                        0x10
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_BMSK                      0x8000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_SHFT                         0xf
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_BMSK                      0x4000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_SHFT                         0xe
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_BMSK                      0x2000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_SHFT                         0xd
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_BMSK                      0x1000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_SHFT                         0xc
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_BMSK                       0x800
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_SHFT                         0xb
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_BMSK                       0x400
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_SHFT                         0xa
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_BMSK                  0x200
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_SHFT                    0x9
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_BMSK                     0x100
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_SHFT                       0x8
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_BMSK                    0x80
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_SHFT                     0x7
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_BMSK                    0x40
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_SHFT                     0x6
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                    0x20
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                     0x5
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK                           0x10
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT                            0x4
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK                             0x8
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT                             0x3
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK                         0x4
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT                         0x2
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK                        0x2
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT                        0x1
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK                         0x1
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT                         0x0

#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00053034)
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_RMSK                                                  0xffff
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ADDR)
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_IN)
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_BMSK                              0x8000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_SHFT                                 0xf
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_BMSK                               0x4000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_SHFT                                  0xe
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_BMSK                           0x2000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_SHFT                              0xd
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_BMSK                          0x1000
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_SHFT                             0xc
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_BMSK                            0x800
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_SHFT                              0xb
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_BMSK                        0x400
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_SHFT                          0xa
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK                            0x200
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT                              0x9
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK                            0x100
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT                              0x8
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK                             0x80
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT                              0x7
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK                             0x40
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT                              0x6
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK                             0x20
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT                              0x5
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK                             0x10
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT                              0x4
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK                         0x8
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT                         0x3
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK                          0x4
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT                          0x2
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK                          0x2
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT                          0x1
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK                            0x1
#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT                            0x0

#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00053038)
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_RMSK                                                   0xffff
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ADDR)
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_IN)
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_BMSK                         0x8000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_SHFT                            0xf
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_BMSK                          0x4000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_SHFT                             0xe
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_BMSK                      0x2000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_SHFT                         0xd
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_BMSK                     0x1000
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_SHFT                        0xc
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_BMSK                       0x800
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_SHFT                         0xb
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                   0x400
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                     0xa
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK                       0x200
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT                         0x9
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK                       0x100
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT                         0x8
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK                        0x80
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT                         0x7
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK                        0x40
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT                         0x6
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK                        0x20
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT                         0x5
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK                        0x10
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT                         0x4
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK                    0x8
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT                    0x3
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK                     0x4
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT                     0x2
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK                     0x2
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT                     0x1
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK                       0x1
#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT                       0x0

#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0005303c)
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_RMSK                                                       0xfff
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL11_BMSK                                                0x800
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL11_SHFT                                                  0xb
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL10_BMSK                                                0x400
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL10_SHFT                                                  0xa
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL9_BMSK                                                 0x200
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL9_SHFT                                                   0x9
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL8_BMSK                                                 0x100
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL8_SHFT                                                   0x8
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL7_BMSK                                                  0x80
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL7_SHFT                                                   0x7
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL6_BMSK                                                  0x40
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL6_SHFT                                                   0x6
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL5_BMSK                                                  0x20
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL5_SHFT                                                   0x5
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL4_BMSK                                                  0x10
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL4_SHFT                                                   0x4
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL3_BMSK                                                   0x8
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL3_SHFT                                                   0x3
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL2_BMSK                                                   0x4
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL2_SHFT                                                   0x2
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL1_BMSK                                                   0x2
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL1_SHFT                                                   0x1
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL0_BMSK                                                   0x1
#define HWIO_GCC_APCS_TZ_PLL_BRANCH_ENA_VOTE_GPLL0_SHFT                                                   0x0

#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00053040)
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_RMSK                                                        0xfff
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL11_BMSK                                                 0x800
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL11_SHFT                                                   0xb
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL10_BMSK                                                 0x400
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL10_SHFT                                                   0xa
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL9_BMSK                                                  0x200
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL9_SHFT                                                    0x9
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL8_BMSK                                                  0x100
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL8_SHFT                                                    0x8
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL7_BMSK                                                   0x80
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL7_SHFT                                                    0x7
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL6_BMSK                                                   0x40
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL6_SHFT                                                    0x6
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL5_BMSK                                                   0x20
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL5_SHFT                                                    0x5
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL4_BMSK                                                   0x10
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL4_SHFT                                                    0x4
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL3_BMSK                                                    0x8
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL3_SHFT                                                    0x3
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL2_BMSK                                                    0x4
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL2_SHFT                                                    0x2
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL1_BMSK                                                    0x2
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL1_SHFT                                                    0x1
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL0_BMSK                                                    0x1
#define HWIO_GCC_APCS_TZ_PLL_SLEEP_ENA_VOTE_GPLL0_SHFT                                                    0x0

#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00054000)
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_RMSK                                                    0x7f2fed7f
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK                                0x40000000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT                                      0x1e
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK                                 0x20000000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT                                       0x1d
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK                             0x10000000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT                                   0x1c
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK                             0x8000000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT                                  0x1b
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK                              0x4000000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT                                   0x1a
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK                          0x2000000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT                               0x19
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK                                    0x1000000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT                                         0x18
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK                                    0x200000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT                                        0x15
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                             0x80000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                                0x13
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_BMSK                                 0x40000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_SHFT                                    0x12
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK                             0x20000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT                                0x11
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                             0x10000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                                0x10
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK                                  0x8000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT                                     0xf
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_BMSK                                  0x4000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_SHFT                                     0xe
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK                                       0x2000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT                                          0xd
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_BMSK                                  0x800
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_SHFT                                    0xb
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK                                    0x400
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT                                      0xa
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_BMSK                                  0x100
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_SHFT                                    0x8
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK                                             0x40
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT                                              0x6
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK                                              0x20
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT                                               0x5
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK                                          0x10
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT                                           0x4
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK                                           0x8
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT                                           0x3
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK                                      0x4
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT                                      0x2
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK                                          0x2
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT                                          0x1
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK                                 0x1
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT                                 0x0

#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00054004)
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_RMSK                                                     0x7f2fed7f
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK                           0x40000000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT                                 0x1e
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK                            0x20000000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT                                  0x1d
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK                        0x10000000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT                              0x1c
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK                        0x8000000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT                             0x1b
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK                         0x4000000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT                              0x1a
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                     0x2000000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                          0x19
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK                               0x1000000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT                                    0x18
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                               0x200000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                                   0x15
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                        0x80000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                           0x13
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                            0x40000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                               0x12
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                        0x20000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                           0x11
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                        0x10000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                           0x10
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                             0x8000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                                0xf
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_BMSK                             0x4000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_SHFT                                0xe
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK                                  0x2000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT                                     0xd
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_BMSK                             0x800
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_SHFT                               0xb
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK                               0x400
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT                                 0xa
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_BMSK                             0x100
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_SHFT                               0x8
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK                                        0x40
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT                                         0x6
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK                                         0x20
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT                                          0x5
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK                                     0x10
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT                                      0x4
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK                                      0x8
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT                                      0x3
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK                                 0x4
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT                                 0x2
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK                                     0x2
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT                                     0x1
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                            0x1
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                            0x0

#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00054008)
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_RMSK                                                   0xfffffff
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_ADDR)
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_IN)
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK                            0x8000000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT                                 0x1b
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK                            0x4000000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT                                 0x1a
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK                            0x2000000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT                                 0x19
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK                            0x1000000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT                                 0x18
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK                             0x800000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT                                 0x17
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK                             0x400000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT                                 0x16
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK                         0x200000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT                             0x15
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK                         0x100000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT                             0x14
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK                            0x80000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT                               0x13
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK                         0x40000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT                            0x12
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_BMSK                              0x20000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_SHFT                                 0x11
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_BMSK                              0x10000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_SHFT                                 0x10
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_BMSK                               0x8000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_SHFT                                  0xf
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_BMSK                               0x4000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_SHFT                                  0xe
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_BMSK                               0x2000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_SHFT                                  0xd
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_BMSK                               0x1000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_SHFT                                  0xc
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_BMSK                                0x800
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_SHFT                                  0xb
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_BMSK                                0x400
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_SHFT                                  0xa
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_BMSK                           0x200
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_SHFT                             0x9
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_BMSK                              0x100
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_SHFT                                0x8
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_BMSK                             0x80
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_SHFT                              0x7
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_BMSK                             0x40
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_SHFT                              0x6
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK                             0x20
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT                              0x5
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK                                    0x10
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT                                     0x4
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK                                      0x8
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT                                      0x3
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK                                  0x4
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT                                  0x2
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK                                 0x2
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT                                 0x1
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK                                  0x1
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT                                  0x0

#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0005400c)
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_RMSK                                                    0xfffffff
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_ADDR)
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_IN)
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK                       0x8000000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT                            0x1b
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK                       0x4000000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT                            0x1a
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK                       0x2000000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT                            0x19
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK                       0x1000000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT                            0x18
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK                        0x800000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT                            0x17
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK                        0x400000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT                            0x16
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK                    0x200000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT                        0x15
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK                    0x100000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT                        0x14
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK                       0x80000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT                          0x13
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK                    0x40000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT                       0x12
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_BMSK                         0x20000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_SHFT                            0x11
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_BMSK                         0x10000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_SHFT                            0x10
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_BMSK                          0x8000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_SHFT                             0xf
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_BMSK                          0x4000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_SHFT                             0xe
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_BMSK                          0x2000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_SHFT                             0xd
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_BMSK                          0x1000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_SHFT                             0xc
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_BMSK                           0x800
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_SHFT                             0xb
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_BMSK                           0x400
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_SHFT                             0xa
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_BMSK                      0x200
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_SHFT                        0x9
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_BMSK                         0x100
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_SHFT                           0x8
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_BMSK                        0x80
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_SHFT                         0x7
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_BMSK                        0x40
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_SHFT                         0x6
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                        0x20
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                         0x5
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK                               0x10
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT                                0x4
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK                                 0x8
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT                                 0x3
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK                             0x4
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT                             0x2
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK                            0x2
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT                            0x1
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK                             0x1
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT                             0x0

#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00054010)
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_RMSK                                                      0xffff
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_ADDR)
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_IN)
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_BMSK                                  0x8000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_SHFT                                     0xf
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_BMSK                                   0x4000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_SHFT                                      0xe
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_BMSK                               0x2000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_SHFT                                  0xd
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_BMSK                              0x1000
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_SHFT                                 0xc
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_BMSK                                0x800
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_SHFT                                  0xb
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_BMSK                            0x400
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_SHFT                              0xa
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK                                0x200
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT                                  0x9
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK                                0x100
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT                                  0x8
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK                                 0x80
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT                                  0x7
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK                                 0x40
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT                                  0x6
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK                                 0x20
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT                                  0x5
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK                                 0x10
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT                                  0x4
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK                             0x8
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT                             0x3
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK                              0x4
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT                              0x2
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK                              0x2
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT                              0x1
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK                                0x1
#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT                                0x0

#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00054014)
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_RMSK                                                       0xffff
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_ADDR)
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_IN)
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_BMSK                             0x8000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_SHFT                                0xf
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_BMSK                              0x4000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_SHFT                                 0xe
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_BMSK                          0x2000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_SHFT                             0xd
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_BMSK                         0x1000
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_SHFT                            0xc
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_BMSK                           0x800
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_SHFT                             0xb
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                       0x400
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                         0xa
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK                           0x200
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT                             0x9
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK                           0x100
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT                             0x8
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK                            0x80
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT                             0x7
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK                            0x40
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT                             0x6
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK                            0x20
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT                             0x5
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK                            0x10
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT                             0x4
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK                        0x8
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT                        0x3
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK                         0x4
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT                         0x2
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK                         0x2
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT                         0x1
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK                           0x1
#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT                           0x0

#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00054018)
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_RMSK                                                           0xfff
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL11_BMSK                                                    0x800
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL11_SHFT                                                      0xb
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL10_BMSK                                                    0x400
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL10_SHFT                                                      0xa
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL9_BMSK                                                     0x200
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL9_SHFT                                                       0x9
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL8_BMSK                                                     0x100
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL8_SHFT                                                       0x8
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL7_BMSK                                                      0x80
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL7_SHFT                                                       0x7
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL6_BMSK                                                      0x40
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL6_SHFT                                                       0x6
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL5_BMSK                                                      0x20
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL5_SHFT                                                       0x5
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL4_BMSK                                                      0x10
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL4_SHFT                                                       0x4
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL3_BMSK                                                       0x8
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL3_SHFT                                                       0x3
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL2_BMSK                                                       0x4
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL2_SHFT                                                       0x2
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_SSC_PLL_BRANCH_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0005401c)
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_RMSK                                                            0xfff
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL11_BMSK                                                     0x800
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL11_SHFT                                                       0xb
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL10_BMSK                                                     0x400
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL10_SHFT                                                       0xa
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL9_BMSK                                                      0x200
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL9_SHFT                                                        0x9
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL8_BMSK                                                      0x100
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL8_SHFT                                                        0x8
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL7_BMSK                                                       0x80
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL7_SHFT                                                        0x7
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL6_BMSK                                                       0x40
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL6_SHFT                                                        0x6
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL5_BMSK                                                       0x20
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL5_SHFT                                                        0x5
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL4_BMSK                                                       0x10
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL4_SHFT                                                        0x4
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL3_BMSK                                                        0x8
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL3_SHFT                                                        0x3
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL2_BMSK                                                        0x4
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL2_SHFT                                                        0x2
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL1_BMSK                                                        0x2
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL1_SHFT                                                        0x1
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL0_BMSK                                                        0x1
#define HWIO_GCC_SSC_PLL_SLEEP_ENA_VOTE_GPLL0_SHFT                                                        0x0

#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00055000)
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_RMSK                                              0x7f2fed7f
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK                          0x40000000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT                                0x1e
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK                           0x20000000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT                                 0x1d
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK                       0x10000000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT                             0x1c
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK                       0x8000000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT                            0x1b
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK                        0x4000000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT                             0x1a
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK                    0x2000000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT                         0x19
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK                              0x1000000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT                                   0x18
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK                              0x200000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT                                  0x15
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                       0x80000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                          0x13
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_BMSK                           0x40000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_SHFT                              0x12
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK                       0x20000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT                          0x11
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                       0x10000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                          0x10
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK                            0x8000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT                               0xf
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_BMSK                            0x4000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_SHFT                               0xe
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK                                 0x2000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT                                    0xd
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_BMSK                            0x800
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_SHFT                              0xb
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK                              0x400
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT                                0xa
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_BMSK                            0x100
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_SHFT                              0x8
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK                                       0x40
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT                                        0x6
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK                                        0x20
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT                                         0x5
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK                                    0x10
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT                                     0x4
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK                                     0x8
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT                                     0x3
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK                                0x4
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT                                0x2
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK                                    0x2
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT                                    0x1
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK                           0x1
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT                           0x0

#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00055004)
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_RMSK                                               0x7f2fed7f
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK                     0x40000000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT                           0x1e
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK                      0x20000000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT                            0x1d
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK                  0x10000000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT                        0x1c
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK                  0x8000000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT                       0x1b
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK                   0x4000000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT                        0x1a
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK               0x2000000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                    0x19
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK                         0x1000000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT                              0x18
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                         0x200000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                             0x15
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                  0x80000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                     0x13
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                      0x40000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                         0x12
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                  0x20000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                     0x11
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                  0x10000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                     0x10
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                       0x8000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                          0xf
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_BMSK                       0x4000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_SHFT                          0xe
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK                            0x2000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT                               0xd
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_BMSK                       0x800
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_SHFT                         0xb
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK                         0x400
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT                           0xa
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_BMSK                       0x100
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_SHFT                         0x8
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK                                  0x40
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT                                   0x6
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK                                   0x20
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT                                    0x5
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK                               0x10
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT                                0x4
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK                                0x8
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT                                0x3
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK                           0x4
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT                           0x2
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK                               0x2
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT                               0x1
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                      0x1
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                      0x0

#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00055008)
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_RMSK                                             0xfffffff
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR)
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_IN)
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK                      0x8000000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT                           0x1b
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK                      0x4000000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT                           0x1a
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK                      0x2000000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT                           0x19
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK                      0x1000000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT                           0x18
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK                       0x800000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT                           0x17
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK                       0x400000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT                           0x16
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK                   0x200000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT                       0x15
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK                   0x100000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT                       0x14
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK                      0x80000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT                         0x13
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK                   0x40000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT                      0x12
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_BMSK                        0x20000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_SHFT                           0x11
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_BMSK                        0x10000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_SHFT                           0x10
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_BMSK                         0x8000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_SHFT                            0xf
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_BMSK                         0x4000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_SHFT                            0xe
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_BMSK                         0x2000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_SHFT                            0xd
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_BMSK                         0x1000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_SHFT                            0xc
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_BMSK                          0x800
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_SHFT                            0xb
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_BMSK                          0x400
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_SHFT                            0xa
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_BMSK                     0x200
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_SHFT                       0x9
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_BMSK                        0x100
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_SHFT                          0x8
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_BMSK                       0x80
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_SHFT                        0x7
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_BMSK                       0x40
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_SHFT                        0x6
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK                       0x20
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT                        0x5
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK                              0x10
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT                               0x4
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK                                0x8
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT                                0x3
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK                            0x4
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT                            0x2
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK                           0x2
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT                           0x1
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK                            0x1
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT                            0x0

#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0005500c)
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_RMSK                                              0xfffffff
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR)
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_IN)
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK                 0x8000000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT                      0x1b
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK                 0x4000000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT                      0x1a
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK                 0x2000000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT                      0x19
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK                 0x1000000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT                      0x18
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK                  0x800000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT                      0x17
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK                  0x400000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT                      0x16
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK              0x200000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT                  0x15
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK              0x100000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT                  0x14
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK                 0x80000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT                    0x13
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK              0x40000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT                 0x12
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_BMSK                   0x20000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_SHFT                      0x11
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_BMSK                   0x10000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_SHFT                      0x10
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_BMSK                    0x8000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_SHFT                       0xf
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_BMSK                    0x4000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_SHFT                       0xe
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_BMSK                    0x2000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_SHFT                       0xd
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_BMSK                    0x1000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_SHFT                       0xc
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_BMSK                     0x800
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_SHFT                       0xb
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_BMSK                     0x400
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_SHFT                       0xa
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_BMSK                0x200
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_SHFT                  0x9
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_BMSK                   0x100
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_SHFT                     0x8
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_BMSK                  0x80
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_SHFT                   0x7
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_BMSK                  0x40
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_SHFT                   0x6
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                  0x20
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                   0x5
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK                         0x10
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT                          0x4
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK                           0x8
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT                           0x3
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK                       0x4
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT                       0x2
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK                      0x2
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT                      0x1
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK                       0x1
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT                       0x0

#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00055010)
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_RMSK                                                0xffff
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR)
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_IN)
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_BMSK                            0x8000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_SHFT                               0xf
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_BMSK                             0x4000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_SHFT                                0xe
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_BMSK                         0x2000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_SHFT                            0xd
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_BMSK                        0x1000
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_SHFT                           0xc
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_BMSK                          0x800
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_SHFT                            0xb
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_BMSK                      0x400
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_SHFT                        0xa
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK                          0x200
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT                            0x9
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK                          0x100
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT                            0x8
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK                           0x80
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT                            0x7
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK                           0x40
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT                            0x6
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK                           0x20
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT                            0x5
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK                           0x10
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT                            0x4
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK                       0x8
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT                       0x3
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK                        0x4
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT                        0x2
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK                        0x2
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT                        0x1
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK                          0x1
#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT                          0x0

#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00055014)
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_RMSK                                                 0xffff
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR)
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_IN)
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_BMSK                       0x8000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_SHFT                          0xf
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_BMSK                        0x4000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_SHFT                           0xe
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_BMSK                    0x2000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_SHFT                       0xd
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_BMSK                   0x1000
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_SHFT                      0xc
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_BMSK                     0x800
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_SHFT                       0xb
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                 0x400
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                   0xa
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK                     0x200
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT                       0x9
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK                     0x100
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT                       0x8
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK                      0x80
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT                       0x7
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK                      0x40
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT                       0x6
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK                      0x20
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT                       0x5
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK                      0x10
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT                       0x4
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK                  0x8
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT                  0x3
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK                   0x4
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT                   0x2
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK                   0x2
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT                   0x1
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK                     0x1
#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT                     0x0

#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00055018)
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_RMSK                                                     0xfff
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL11_BMSK                                              0x800
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL11_SHFT                                                0xb
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL10_BMSK                                              0x400
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL10_SHFT                                                0xa
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL9_BMSK                                               0x200
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL9_SHFT                                                 0x9
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL8_BMSK                                               0x100
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL8_SHFT                                                 0x8
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL7_BMSK                                                0x80
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL7_SHFT                                                 0x7
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL6_BMSK                                                0x40
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL6_SHFT                                                 0x6
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL5_BMSK                                                0x20
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL5_SHFT                                                 0x5
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL4_BMSK                                                0x10
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL4_SHFT                                                 0x4
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL3_BMSK                                                 0x8
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL3_SHFT                                                 0x3
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL2_BMSK                                                 0x4
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL2_SHFT                                                 0x2
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL1_BMSK                                                 0x2
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL1_SHFT                                                 0x1
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL0_BMSK                                                 0x1
#define HWIO_GCC_LPASS_DSP_PLL_BRANCH_ENA_VOTE_GPLL0_SHFT                                                 0x0

#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0005501c)
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_RMSK                                                      0xfff
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL11_BMSK                                               0x800
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL11_SHFT                                                 0xb
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL10_BMSK                                               0x400
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL10_SHFT                                                 0xa
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL9_BMSK                                                0x200
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL9_SHFT                                                  0x9
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL8_BMSK                                                0x100
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL8_SHFT                                                  0x8
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL7_BMSK                                                 0x80
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL7_SHFT                                                  0x7
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL6_BMSK                                                 0x40
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL6_SHFT                                                  0x6
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL5_BMSK                                                 0x20
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL5_SHFT                                                  0x5
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL4_BMSK                                                 0x10
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL4_SHFT                                                  0x4
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL3_BMSK                                                  0x8
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL3_SHFT                                                  0x3
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL2_BMSK                                                  0x4
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL2_SHFT                                                  0x2
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_LPASS_DSP_PLL_SLEEP_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0005b000)
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_RMSK                                             0x7f2fed7f
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK                         0x40000000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT                               0x1e
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK                          0x20000000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT                                0x1d
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK                      0x10000000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT                            0x1c
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK                      0x8000000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT                           0x1b
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK                       0x4000000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT                            0x1a
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK                   0x2000000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT                        0x19
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK                             0x1000000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT                                  0x18
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK                             0x200000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT                                 0x15
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                      0x80000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                         0x13
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_BMSK                          0x40000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_SHFT                             0x12
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK                      0x20000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT                         0x11
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                      0x10000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                         0x10
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK                           0x8000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT                              0xf
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_BMSK                           0x4000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_SHFT                              0xe
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK                                0x2000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT                                   0xd
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_BMSK                           0x800
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_SHFT                             0xb
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK                             0x400
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT                               0xa
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_BMSK                           0x100
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_SHFT                             0x8
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK                                      0x40
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT                                       0x6
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK                                       0x20
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT                                        0x5
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK                                   0x10
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT                                    0x4
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK                                    0x8
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT                                    0x3
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK                               0x4
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT                               0x2
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK                                   0x2
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT                                   0x1
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK                          0x1
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT                          0x0

#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0005b004)
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_RMSK                                              0x7f2fed7f
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK                    0x40000000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT                          0x1e
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK                     0x20000000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT                           0x1d
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK                 0x10000000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT                       0x1c
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK                 0x8000000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT                      0x1b
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK                  0x4000000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT                       0x1a
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK              0x2000000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                   0x19
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK                        0x1000000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT                             0x18
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                        0x200000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                            0x15
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                 0x80000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                    0x13
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                     0x40000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                        0x12
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                 0x20000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                    0x11
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                 0x10000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                    0x10
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                      0x8000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                         0xf
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_BMSK                      0x4000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_SHFT                         0xe
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK                           0x2000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT                              0xd
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_BMSK                      0x800
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_SHFT                        0xb
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK                        0x400
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT                          0xa
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_BMSK                      0x100
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_SHFT                        0x8
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK                                 0x40
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT                                  0x6
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK                                  0x20
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT                                   0x5
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK                              0x10
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT                               0x4
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK                               0x8
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT                               0x3
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK                          0x4
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT                          0x2
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK                              0x2
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT                              0x1
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                     0x1
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                     0x0

#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0005b008)
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_RMSK                                            0xfffffff
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR)
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_IN)
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK                     0x8000000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT                          0x1b
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK                     0x4000000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT                          0x1a
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK                     0x2000000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT                          0x19
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK                     0x1000000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT                          0x18
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK                      0x800000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT                          0x17
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK                      0x400000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT                          0x16
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK                  0x200000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT                      0x15
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK                  0x100000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT                      0x14
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK                     0x80000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT                        0x13
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK                  0x40000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT                     0x12
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_BMSK                       0x20000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_SHFT                          0x11
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_BMSK                       0x10000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_SHFT                          0x10
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_BMSK                        0x8000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_SHFT                           0xf
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_BMSK                        0x4000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_SHFT                           0xe
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_BMSK                        0x2000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_SHFT                           0xd
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_BMSK                        0x1000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_SHFT                           0xc
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_BMSK                         0x800
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_SHFT                           0xb
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_BMSK                         0x400
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_SHFT                           0xa
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_BMSK                    0x200
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_SHFT                      0x9
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_BMSK                       0x100
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_SHFT                         0x8
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_BMSK                      0x80
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_SHFT                       0x7
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_BMSK                      0x40
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_SHFT                       0x6
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK                      0x20
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT                       0x5
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK                             0x10
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT                              0x4
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK                               0x8
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT                               0x3
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK                           0x4
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT                           0x2
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK                          0x2
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT                          0x1
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK                           0x1
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT                           0x0

#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0005b00c)
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_RMSK                                             0xfffffff
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR)
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_IN)
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK                0x8000000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT                     0x1b
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK                0x4000000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT                     0x1a
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK                0x2000000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT                     0x19
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK                0x1000000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT                     0x18
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK                 0x800000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT                     0x17
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK                 0x400000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT                     0x16
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK             0x200000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT                 0x15
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK             0x100000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT                 0x14
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK                0x80000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT                   0x13
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK             0x40000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT                0x12
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_BMSK                  0x20000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_SHFT                     0x11
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_BMSK                  0x10000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_SHFT                     0x10
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_BMSK                   0x8000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_SHFT                      0xf
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_BMSK                   0x4000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_SHFT                      0xe
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_BMSK                   0x2000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_SHFT                      0xd
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_BMSK                   0x1000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_SHFT                      0xc
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_BMSK                    0x800
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_SHFT                      0xb
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_BMSK                    0x400
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_SHFT                      0xa
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_BMSK               0x200
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_SHFT                 0x9
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_BMSK                  0x100
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_SHFT                    0x8
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_BMSK                 0x80
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_SHFT                  0x7
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_BMSK                 0x40
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_SHFT                  0x6
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                 0x20
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                  0x5
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK                        0x10
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT                         0x4
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK                          0x8
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT                          0x3
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK                      0x4
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT                      0x2
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK                     0x2
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT                     0x1
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK                      0x1
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT                      0x0

#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0005b010)
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_RMSK                                               0xffff
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR)
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_IN)
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_BMSK                           0x8000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_SHFT                              0xf
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_BMSK                            0x4000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_SHFT                               0xe
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_BMSK                        0x2000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_SHFT                           0xd
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_BMSK                       0x1000
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_SHFT                          0xc
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_BMSK                         0x800
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_SHFT                           0xb
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_BMSK                     0x400
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_SHFT                       0xa
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK                         0x200
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT                           0x9
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK                         0x100
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT                           0x8
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK                          0x80
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT                           0x7
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK                          0x40
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT                           0x6
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK                          0x20
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT                           0x5
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK                          0x10
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT                           0x4
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK                      0x8
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT                      0x3
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK                       0x4
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT                       0x2
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK                       0x2
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT                       0x1
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK                         0x1
#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT                         0x0

#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0005b014)
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_RMSK                                                0xffff
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR)
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_IN)
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_BMSK                      0x8000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_SHFT                         0xf
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_BMSK                       0x4000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_SHFT                          0xe
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_BMSK                   0x2000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_SHFT                      0xd
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_BMSK                  0x1000
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_SHFT                     0xc
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_BMSK                    0x800
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_SHFT                      0xb
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                0x400
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                  0xa
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK                    0x200
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT                      0x9
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK                    0x100
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT                      0x8
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK                     0x80
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT                      0x7
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK                     0x40
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT                      0x6
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK                     0x20
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT                      0x5
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK                     0x10
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT                      0x4
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK                 0x8
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT                 0x3
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK                  0x4
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT                  0x2
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK                  0x2
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT                  0x1
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK                    0x1
#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT                    0x0

#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0005b018)
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_RMSK                                                    0xfff
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL11_BMSK                                             0x800
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL11_SHFT                                               0xb
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL10_BMSK                                             0x400
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL10_SHFT                                               0xa
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL9_BMSK                                              0x200
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL9_SHFT                                                0x9
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL8_BMSK                                              0x100
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL8_SHFT                                                0x8
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL7_BMSK                                               0x80
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL7_SHFT                                                0x7
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL6_BMSK                                               0x40
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL6_SHFT                                                0x6
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL5_BMSK                                               0x20
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL5_SHFT                                                0x5
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL4_BMSK                                               0x10
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL4_SHFT                                                0x4
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL3_BMSK                                                0x8
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL3_SHFT                                                0x3
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL2_BMSK                                                0x4
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL2_SHFT                                                0x2
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL1_BMSK                                                0x2
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL1_SHFT                                                0x1
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL0_BMSK                                                0x1
#define HWIO_GCC_TURING_DSP_PLL_BRANCH_ENA_VOTE_GPLL0_SHFT                                                0x0

#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0005b01c)
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_RMSK                                                     0xfff
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL11_BMSK                                              0x800
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL11_SHFT                                                0xb
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL10_BMSK                                              0x400
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL10_SHFT                                                0xa
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL9_BMSK                                               0x200
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL9_SHFT                                                 0x9
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL8_BMSK                                               0x100
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL8_SHFT                                                 0x8
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL7_BMSK                                                0x80
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL7_SHFT                                                 0x7
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL6_BMSK                                                0x40
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL6_SHFT                                                 0x6
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL5_BMSK                                                0x20
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL5_SHFT                                                 0x5
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL4_BMSK                                                0x10
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL4_SHFT                                                 0x4
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL3_BMSK                                                 0x8
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL3_SHFT                                                 0x3
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL2_BMSK                                                 0x4
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL2_SHFT                                                 0x2
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL1_BMSK                                                 0x2
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL1_SHFT                                                 0x1
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL0_BMSK                                                 0x1
#define HWIO_GCC_TURING_DSP_PLL_SLEEP_ENA_VOTE_GPLL0_SHFT                                                 0x0

#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00057000)
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_RMSK                                                  0x7f2fed7f
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK                              0x40000000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT                                    0x1e
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK                               0x20000000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT                                     0x1d
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK                           0x10000000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT                                 0x1c
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK                           0x8000000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT                                0x1b
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK                            0x4000000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT                                 0x1a
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK                        0x2000000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT                             0x19
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK                                  0x1000000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT                                       0x18
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK                                  0x200000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT                                      0x15
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                           0x80000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                              0x13
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_BMSK                               0x40000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_SHFT                                  0x12
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK                           0x20000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT                              0x11
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                           0x10000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                              0x10
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK                                0x8000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT                                   0xf
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_BMSK                                0x4000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_SHFT                                   0xe
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK                                     0x2000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT                                        0xd
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_BMSK                                0x800
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_SHFT                                  0xb
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK                                  0x400
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT                                    0xa
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_BMSK                                0x100
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_SHFT                                  0x8
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK                                           0x40
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT                                            0x6
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK                                            0x20
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT                                             0x5
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK                                        0x10
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT                                         0x4
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK                                         0x8
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT                                         0x3
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK                                    0x4
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT                                    0x2
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK                                        0x2
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT                                        0x1
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK                               0x1
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT                               0x0

#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00057004)
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_RMSK                                                   0x7f2fed7f
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK                         0x40000000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT                               0x1e
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK                          0x20000000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT                                0x1d
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK                      0x10000000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT                            0x1c
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK                      0x8000000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT                           0x1b
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK                       0x4000000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT                            0x1a
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                   0x2000000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                        0x19
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK                             0x1000000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT                                  0x18
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                             0x200000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                                 0x15
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                      0x80000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                         0x13
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                          0x40000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                             0x12
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                      0x20000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                         0x11
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                      0x10000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                         0x10
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                           0x8000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                              0xf
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_BMSK                           0x4000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_SHFT                              0xe
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK                                0x2000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT                                   0xd
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_BMSK                           0x800
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_SHFT                             0xb
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK                             0x400
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT                               0xa
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_BMSK                           0x100
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_SHFT                             0x8
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK                                      0x40
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT                                       0x6
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK                                       0x20
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT                                        0x5
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK                                   0x10
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT                                    0x4
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK                                    0x8
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT                                    0x3
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK                               0x4
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT                               0x2
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK                                   0x2
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT                                   0x1
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                          0x1
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                          0x0

#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00057008)
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_RMSK                                                 0xfffffff
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR)
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_IN)
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK                          0x8000000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT                               0x1b
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK                          0x4000000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT                               0x1a
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK                          0x2000000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT                               0x19
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK                          0x1000000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT                               0x18
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK                           0x800000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT                               0x17
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK                           0x400000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT                               0x16
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK                       0x200000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT                           0x15
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK                       0x100000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT                           0x14
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK                          0x80000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT                             0x13
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK                       0x40000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT                          0x12
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_BMSK                            0x20000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_SHFT                               0x11
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_BMSK                            0x10000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_SHFT                               0x10
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_BMSK                             0x8000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_SHFT                                0xf
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_BMSK                             0x4000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_SHFT                                0xe
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_BMSK                             0x2000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_SHFT                                0xd
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_BMSK                             0x1000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_SHFT                                0xc
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_BMSK                              0x800
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_SHFT                                0xb
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_BMSK                              0x400
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_SHFT                                0xa
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_BMSK                         0x200
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_SHFT                           0x9
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_BMSK                            0x100
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_SHFT                              0x8
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_BMSK                           0x80
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_SHFT                            0x7
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_BMSK                           0x40
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_SHFT                            0x6
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK                           0x20
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT                            0x5
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK                                  0x10
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT                                   0x4
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK                                    0x8
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT                                    0x3
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK                                0x4
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT                                0x2
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK                               0x2
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT                               0x1
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK                                0x1
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT                                0x0

#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0005700c)
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_RMSK                                                  0xfffffff
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR)
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_IN)
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK                     0x8000000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT                          0x1b
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK                     0x4000000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT                          0x1a
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK                     0x2000000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT                          0x19
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK                     0x1000000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT                          0x18
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK                      0x800000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT                          0x17
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK                      0x400000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT                          0x16
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK                  0x200000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT                      0x15
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK                  0x100000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT                      0x14
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK                     0x80000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT                        0x13
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK                  0x40000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT                     0x12
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_BMSK                       0x20000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_SHFT                          0x11
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_BMSK                       0x10000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_SHFT                          0x10
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_BMSK                        0x8000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_SHFT                           0xf
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_BMSK                        0x4000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_SHFT                           0xe
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_BMSK                        0x2000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_SHFT                           0xd
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_BMSK                        0x1000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_SHFT                           0xc
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_BMSK                         0x800
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_SHFT                           0xb
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_BMSK                         0x400
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_SHFT                           0xa
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_BMSK                    0x200
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_SHFT                      0x9
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_BMSK                       0x100
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_SHFT                         0x8
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_BMSK                      0x80
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_SHFT                       0x7
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_BMSK                      0x40
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_SHFT                       0x6
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                      0x20
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                       0x5
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK                             0x10
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT                              0x4
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK                               0x8
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT                               0x3
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK                           0x4
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT                           0x2
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK                          0x2
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT                          0x1
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK                           0x1
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT                           0x0

#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00057010)
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_RMSK                                                    0xffff
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ADDR)
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_IN)
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_BMSK                                0x8000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_SHFT                                   0xf
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_BMSK                                 0x4000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_SHFT                                    0xe
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_BMSK                             0x2000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_SHFT                                0xd
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_BMSK                            0x1000
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_SHFT                               0xc
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_BMSK                              0x800
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_SHFT                                0xb
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_BMSK                          0x400
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_SHFT                            0xa
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK                              0x200
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT                                0x9
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK                              0x100
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT                                0x8
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK                               0x80
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT                                0x7
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK                               0x40
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT                                0x6
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK                               0x20
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT                                0x5
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK                               0x10
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT                                0x4
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK                           0x8
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT                           0x3
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK                            0x4
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT                            0x2
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK                            0x2
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT                            0x1
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK                              0x1
#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT                              0x0

#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00057014)
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_RMSK                                                     0xffff
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ADDR)
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_IN)
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_BMSK                           0x8000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_SHFT                              0xf
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_BMSK                            0x4000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_SHFT                               0xe
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_BMSK                        0x2000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_SHFT                           0xd
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_BMSK                       0x1000
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_SHFT                          0xc
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_BMSK                         0x800
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_SHFT                           0xb
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                     0x400
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                       0xa
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK                         0x200
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT                           0x9
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK                         0x100
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT                           0x8
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK                          0x80
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT                           0x7
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK                          0x40
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT                           0x6
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK                          0x20
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT                           0x5
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK                          0x10
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT                           0x4
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK                      0x8
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT                      0x3
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK                       0x4
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT                       0x2
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK                       0x2
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT                       0x1
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK                         0x1
#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT                         0x0

#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00057018)
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_RMSK                                                         0xfff
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL11_BMSK                                                  0x800
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL11_SHFT                                                    0xb
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL10_BMSK                                                  0x400
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL10_SHFT                                                    0xa
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL9_BMSK                                                   0x200
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL9_SHFT                                                     0x9
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL8_BMSK                                                   0x100
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL8_SHFT                                                     0x8
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL7_BMSK                                                    0x80
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL7_SHFT                                                     0x7
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL6_BMSK                                                    0x40
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL6_SHFT                                                     0x6
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL5_BMSK                                                    0x20
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL5_SHFT                                                     0x5
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL4_BMSK                                                    0x10
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL4_SHFT                                                     0x4
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL3_BMSK                                                     0x8
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL3_SHFT                                                     0x3
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL2_BMSK                                                     0x4
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL2_SHFT                                                     0x2
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_SPARE_PLL_BRANCH_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0005701c)
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_RMSK                                                          0xfff
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL11_BMSK                                                   0x800
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL11_SHFT                                                     0xb
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL10_BMSK                                                   0x400
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL10_SHFT                                                     0xa
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL9_BMSK                                                    0x200
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL9_SHFT                                                      0x9
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL8_BMSK                                                    0x100
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL8_SHFT                                                      0x8
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL7_BMSK                                                     0x80
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL7_SHFT                                                      0x7
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL6_BMSK                                                     0x40
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL6_SHFT                                                      0x6
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL5_BMSK                                                     0x20
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL5_SHFT                                                      0x5
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL4_BMSK                                                     0x10
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL4_SHFT                                                      0x4
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL3_BMSK                                                      0x8
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL3_SHFT                                                      0x3
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL2_BMSK                                                      0x4
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL2_SHFT                                                      0x2
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_SPARE_PLL_SLEEP_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00035024)
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_RMSK                                                 0x7f2fed7f
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK                             0x40000000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT                                   0x1e
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK                              0x20000000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT                                    0x1d
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK                          0x10000000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT                                0x1c
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK                          0x8000000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT                               0x1b
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK                           0x4000000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT                                0x1a
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK                       0x2000000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT                            0x19
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK                                 0x1000000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT                                      0x18
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK                                 0x200000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT                                     0x15
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                          0x80000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                             0x13
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_BMSK                              0x40000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_SHFT                                 0x12
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK                          0x20000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT                             0x11
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                          0x10000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                             0x10
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK                               0x8000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT                                  0xf
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_BMSK                               0x4000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_SHFT                                  0xe
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK                                    0x2000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT                                       0xd
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_BMSK                               0x800
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_SHFT                                 0xb
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK                                 0x400
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT                                   0xa
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_BMSK                               0x100
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_SHFT                                 0x8
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK                                          0x40
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT                                           0x6
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK                                           0x20
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT                                            0x5
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK                                       0x10
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT                                        0x4
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK                                        0x8
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT                                        0x3
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK                                   0x4
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT                                   0x2
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK                                       0x2
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT                                       0x1
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK                              0x1
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT                              0x0

#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00035028)
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_RMSK                                                  0x7f2fed7f
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK                        0x40000000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT                              0x1e
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK                         0x20000000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT                               0x1d
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK                     0x10000000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT                           0x1c
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK                     0x8000000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT                          0x1b
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK                      0x4000000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT                           0x1a
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                  0x2000000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                       0x19
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK                            0x1000000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT                                 0x18
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                            0x200000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                                0x15
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                     0x80000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                        0x13
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                         0x40000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                            0x12
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                     0x20000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                        0x11
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                     0x10000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                        0x10
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                          0x8000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                             0xf
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_BMSK                          0x4000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_SHFT                             0xe
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK                               0x2000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT                                  0xd
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_BMSK                          0x800
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_SHFT                            0xb
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK                            0x400
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT                              0xa
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_BMSK                          0x100
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_SHFT                            0x8
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK                                     0x40
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT                                      0x6
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK                                      0x20
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT                                       0x5
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK                                  0x10
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT                                   0x4
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK                                   0x8
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT                                   0x3
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK                              0x4
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT                              0x2
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK                                  0x2
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT                                  0x1
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                         0x1
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                         0x0

#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0003502c)
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_RMSK                                                0xfffffff
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR)
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_IN)
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK                         0x8000000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT                              0x1b
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK                         0x4000000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT                              0x1a
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK                         0x2000000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT                              0x19
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK                         0x1000000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT                              0x18
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK                          0x800000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT                              0x17
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK                          0x400000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT                              0x16
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK                      0x200000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT                          0x15
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK                      0x100000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT                          0x14
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK                         0x80000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT                            0x13
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK                      0x40000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT                         0x12
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_BMSK                           0x20000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_SHFT                              0x11
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_BMSK                           0x10000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_SHFT                              0x10
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_BMSK                            0x8000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_SHFT                               0xf
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_BMSK                            0x4000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_SHFT                               0xe
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_BMSK                            0x2000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_SHFT                               0xd
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_BMSK                            0x1000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_SHFT                               0xc
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_BMSK                             0x800
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_SHFT                               0xb
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_BMSK                             0x400
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_SHFT                               0xa
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_BMSK                        0x200
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_SHFT                          0x9
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_BMSK                           0x100
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_SHFT                             0x8
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_BMSK                          0x80
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_SHFT                           0x7
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_BMSK                          0x40
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_SHFT                           0x6
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK                          0x20
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT                           0x5
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK                                 0x10
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT                                  0x4
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK                                   0x8
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT                                   0x3
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK                               0x4
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT                               0x2
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK                              0x2
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT                              0x1
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK                               0x1
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT                               0x0

#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00035030)
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_RMSK                                                 0xfffffff
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR)
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_IN)
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK                    0x8000000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT                         0x1b
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK                    0x4000000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT                         0x1a
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK                    0x2000000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT                         0x19
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK                    0x1000000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT                         0x18
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK                     0x800000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT                         0x17
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK                     0x400000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT                         0x16
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK                 0x200000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT                     0x15
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK                 0x100000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT                     0x14
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK                    0x80000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT                       0x13
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK                 0x40000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT                    0x12
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_BMSK                      0x20000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_SHFT                         0x11
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_BMSK                      0x10000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_SHFT                         0x10
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_BMSK                       0x8000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_SHFT                          0xf
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_BMSK                       0x4000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_SHFT                          0xe
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_BMSK                       0x2000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_SHFT                          0xd
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_BMSK                       0x1000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_SHFT                          0xc
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_BMSK                        0x800
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_SHFT                          0xb
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_BMSK                        0x400
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_SHFT                          0xa
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_BMSK                   0x200
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_SHFT                     0x9
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_BMSK                      0x100
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_SHFT                        0x8
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_BMSK                     0x80
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_SHFT                      0x7
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_BMSK                     0x40
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_SHFT                      0x6
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                     0x20
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                      0x5
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK                            0x10
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT                             0x4
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK                              0x8
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT                              0x3
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK                          0x4
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT                          0x2
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK                         0x2
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT                         0x1
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK                          0x1
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT                          0x0

#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00035034)
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_RMSK                                                   0xffff
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR)
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_IN)
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_BMSK                               0x8000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_SHFT                                  0xf
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_BMSK                                0x4000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_SHFT                                   0xe
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_BMSK                            0x2000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_SHFT                               0xd
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_BMSK                           0x1000
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_SHFT                              0xc
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_BMSK                             0x800
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_SHFT                               0xb
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_BMSK                         0x400
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_SHFT                           0xa
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK                             0x200
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT                               0x9
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK                             0x100
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT                               0x8
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK                              0x80
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT                               0x7
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK                              0x40
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT                               0x6
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK                              0x20
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT                               0x5
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK                              0x10
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT                               0x4
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK                          0x8
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT                          0x3
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK                           0x4
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT                           0x2
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK                           0x2
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT                           0x1
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK                             0x1
#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT                             0x0

#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00035038)
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_RMSK                                                    0xffff
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR)
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_IN)
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_BMSK                          0x8000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_SHFT                             0xf
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_BMSK                           0x4000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_SHFT                              0xe
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_BMSK                       0x2000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_SHFT                          0xd
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_BMSK                      0x1000
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_SHFT                         0xc
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_BMSK                        0x800
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_SHFT                          0xb
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                    0x400
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                      0xa
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK                        0x200
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT                          0x9
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK                        0x100
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT                          0x8
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK                         0x80
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT                          0x7
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK                         0x40
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT                          0x6
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK                         0x20
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT                          0x5
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK                         0x10
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT                          0x4
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK                     0x8
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT                     0x3
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK                      0x4
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT                      0x2
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK                      0x2
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT                      0x1
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK                        0x1
#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT                        0x0

#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0003503c)
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_RMSK                                                        0xfff
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL11_BMSK                                                 0x800
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL11_SHFT                                                   0xb
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL10_BMSK                                                 0x400
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL10_SHFT                                                   0xa
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL9_BMSK                                                  0x200
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL9_SHFT                                                    0x9
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL8_BMSK                                                  0x100
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL8_SHFT                                                    0x8
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL7_BMSK                                                   0x80
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL7_SHFT                                                    0x7
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL6_BMSK                                                   0x40
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL6_SHFT                                                    0x6
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL5_BMSK                                                   0x20
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL5_SHFT                                                    0x5
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL4_BMSK                                                   0x10
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL4_SHFT                                                    0x4
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL3_BMSK                                                    0x8
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL3_SHFT                                                    0x3
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL2_BMSK                                                    0x4
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL2_SHFT                                                    0x2
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL1_BMSK                                                    0x2
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL1_SHFT                                                    0x1
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL0_BMSK                                                    0x1
#define HWIO_GCC_MSS_Q6_PLL_BRANCH_ENA_VOTE_GPLL0_SHFT                                                    0x0

#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00035040)
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_RMSK                                                         0xfff
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL11_BMSK                                                  0x800
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL11_SHFT                                                    0xb
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL10_BMSK                                                  0x400
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL10_SHFT                                                    0xa
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL9_BMSK                                                   0x200
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL9_SHFT                                                     0x9
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL8_BMSK                                                   0x100
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL8_SHFT                                                     0x8
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL7_BMSK                                                    0x80
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL7_SHFT                                                     0x7
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL6_BMSK                                                    0x40
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL6_SHFT                                                     0x6
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL5_BMSK                                                    0x20
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL5_SHFT                                                     0x5
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL4_BMSK                                                    0x10
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL4_SHFT                                                     0x4
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL3_BMSK                                                     0x8
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL3_SHFT                                                     0x3
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL2_BMSK                                                     0x4
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL2_SHFT                                                     0x2
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_MSS_Q6_PLL_SLEEP_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00056000)
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_RMSK                                                    0x7f2fed7f
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK                                0x40000000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT                                      0x1e
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK                                 0x20000000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT                                       0x1d
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK                             0x10000000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT                                   0x1c
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK                             0x8000000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT                                  0x1b
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK                              0x4000000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT                                   0x1a
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK                          0x2000000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT                               0x19
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK                                    0x1000000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT                                         0x18
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK                                    0x200000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT                                        0x15
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                             0x80000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                                0x13
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_BMSK                                 0x40000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_SHFT                                    0x12
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK                             0x20000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT                                0x11
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                             0x10000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                                0x10
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK                                  0x8000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT                                     0xf
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_BMSK                                  0x4000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_SHFT                                     0xe
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK                                       0x2000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT                                          0xd
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_BMSK                                  0x800
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_SHFT                                    0xb
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK                                    0x400
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT                                      0xa
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_BMSK                                  0x100
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_SHFT                                    0x8
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK                                             0x40
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT                                              0x6
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK                                              0x20
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT                                               0x5
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK                                          0x10
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT                                           0x4
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK                                           0x8
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT                                           0x3
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK                                      0x4
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT                                      0x2
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK                                          0x2
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT                                          0x1
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK                                 0x1
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT                                 0x0

#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00056004)
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_RMSK                                                     0x7f2fed7f
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK                           0x40000000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT                                 0x1e
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK                            0x20000000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT                                  0x1d
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK                        0x10000000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT                              0x1c
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK                        0x8000000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT                             0x1b
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK                         0x4000000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT                              0x1a
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                     0x2000000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                          0x19
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK                               0x1000000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT                                    0x18
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                               0x200000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                                   0x15
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                        0x80000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                           0x13
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                            0x40000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                               0x12
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                        0x20000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                           0x11
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                        0x10000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                           0x10
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                             0x8000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                                0xf
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_BMSK                             0x4000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_SHFT                                0xe
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK                                  0x2000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT                                     0xd
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_BMSK                             0x800
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_SHFT                               0xb
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK                               0x400
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT                                 0xa
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_BMSK                             0x100
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_SHFT                               0x8
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK                                        0x40
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT                                         0x6
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK                                         0x20
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT                                          0x5
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK                                     0x10
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT                                      0x4
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK                                      0x8
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT                                      0x3
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK                                 0x4
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT                                 0x2
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK                                     0x2
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT                                     0x1
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                            0x1
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                            0x0

#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00056008)
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_RMSK                                                   0xfffffff
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR)
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_IN)
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK                            0x8000000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT                                 0x1b
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK                            0x4000000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT                                 0x1a
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK                            0x2000000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT                                 0x19
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK                            0x1000000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT                                 0x18
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK                             0x800000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT                                 0x17
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK                             0x400000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT                                 0x16
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK                         0x200000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT                             0x15
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK                         0x100000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT                             0x14
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK                            0x80000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT                               0x13
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK                         0x40000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT                            0x12
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_BMSK                              0x20000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_SHFT                                 0x11
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_BMSK                              0x10000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_SHFT                                 0x10
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_BMSK                               0x8000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_SHFT                                  0xf
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_BMSK                               0x4000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_SHFT                                  0xe
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_BMSK                               0x2000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_SHFT                                  0xd
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_BMSK                               0x1000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_SHFT                                  0xc
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_BMSK                                0x800
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_SHFT                                  0xb
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_BMSK                                0x400
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_SHFT                                  0xa
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_BMSK                           0x200
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_SHFT                             0x9
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_BMSK                              0x100
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_SHFT                                0x8
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_BMSK                             0x80
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_SHFT                              0x7
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_BMSK                             0x40
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_SHFT                              0x6
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK                             0x20
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT                              0x5
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK                                    0x10
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT                                     0x4
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK                                      0x8
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT                                      0x3
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK                                  0x4
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT                                  0x2
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK                                 0x2
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT                                 0x1
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK                                  0x1
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT                                  0x0

#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0005600c)
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_RMSK                                                    0xfffffff
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR)
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_IN)
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK                       0x8000000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT                            0x1b
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK                       0x4000000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT                            0x1a
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK                       0x2000000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT                            0x19
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK                       0x1000000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT                            0x18
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK                        0x800000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT                            0x17
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK                        0x400000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT                            0x16
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK                    0x200000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT                        0x15
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK                    0x100000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT                        0x14
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK                       0x80000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT                          0x13
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK                    0x40000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT                       0x12
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_BMSK                         0x20000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_SHFT                            0x11
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_BMSK                         0x10000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_SHFT                            0x10
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_BMSK                          0x8000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_SHFT                             0xf
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_BMSK                          0x4000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_SHFT                             0xe
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_BMSK                          0x2000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_SHFT                             0xd
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_BMSK                          0x1000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_SHFT                             0xc
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_BMSK                           0x800
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_SHFT                             0xb
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_BMSK                           0x400
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_SHFT                             0xa
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_BMSK                      0x200
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_SHFT                        0x9
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_BMSK                         0x100
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_SHFT                           0x8
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_BMSK                        0x80
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_SHFT                         0x7
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_BMSK                        0x40
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_SHFT                         0x6
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                        0x20
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                         0x5
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK                               0x10
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT                                0x4
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK                                 0x8
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT                                 0x3
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK                             0x4
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT                             0x2
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK                            0x2
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT                            0x1
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK                             0x1
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT                             0x0

#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00056010)
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_RMSK                                                      0xffff
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ADDR)
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_IN)
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_BMSK                                  0x8000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_SHFT                                     0xf
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_BMSK                                   0x4000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_SHFT                                      0xe
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_BMSK                               0x2000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_SHFT                                  0xd
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_BMSK                              0x1000
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_SHFT                                 0xc
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_BMSK                                0x800
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_SHFT                                  0xb
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_BMSK                            0x400
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_SHFT                              0xa
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK                                0x200
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT                                  0x9
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK                                0x100
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT                                  0x8
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK                                 0x80
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT                                  0x7
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK                                 0x40
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT                                  0x6
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK                                 0x20
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT                                  0x5
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK                                 0x10
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT                                  0x4
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK                             0x8
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT                             0x3
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK                              0x4
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT                              0x2
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK                              0x2
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT                              0x1
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK                                0x1
#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT                                0x0

#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00056014)
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_RMSK                                                       0xffff
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ADDR)
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_IN)
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_BMSK                             0x8000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_SHFT                                0xf
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_BMSK                              0x4000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_SHFT                                 0xe
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_BMSK                          0x2000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_SHFT                             0xd
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_BMSK                         0x1000
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_SHFT                            0xc
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_BMSK                           0x800
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_SHFT                             0xb
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                       0x400
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                         0xa
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK                           0x200
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT                             0x9
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK                           0x100
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT                             0x8
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK                            0x80
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT                             0x7
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK                            0x40
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT                             0x6
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK                            0x20
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT                             0x5
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK                            0x10
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT                             0x4
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK                        0x8
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT                        0x3
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK                         0x4
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT                         0x2
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK                         0x2
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT                         0x1
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK                           0x1
#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT                           0x0

#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00056018)
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_RMSK                                                           0xfff
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL11_BMSK                                                    0x800
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL11_SHFT                                                      0xb
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL10_BMSK                                                    0x400
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL10_SHFT                                                      0xa
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL9_BMSK                                                     0x200
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL9_SHFT                                                       0x9
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL8_BMSK                                                     0x100
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL8_SHFT                                                       0x8
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL7_BMSK                                                      0x80
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL7_SHFT                                                       0x7
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL6_BMSK                                                      0x40
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL6_SHFT                                                       0x6
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL5_BMSK                                                      0x20
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL5_SHFT                                                       0x5
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL4_BMSK                                                      0x10
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL4_SHFT                                                       0x4
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL3_BMSK                                                       0x8
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL3_SHFT                                                       0x3
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL2_BMSK                                                       0x4
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL2_SHFT                                                       0x2
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_HYP_PLL_BRANCH_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0005601c)
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_RMSK                                                            0xfff
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL11_BMSK                                                     0x800
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL11_SHFT                                                       0xb
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL10_BMSK                                                     0x400
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL10_SHFT                                                       0xa
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL9_BMSK                                                      0x200
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL9_SHFT                                                        0x9
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL8_BMSK                                                      0x100
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL8_SHFT                                                        0x8
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL7_BMSK                                                       0x80
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL7_SHFT                                                        0x7
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL6_BMSK                                                       0x40
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL6_SHFT                                                        0x6
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL5_BMSK                                                       0x20
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL5_SHFT                                                        0x5
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL4_BMSK                                                       0x10
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL4_SHFT                                                        0x4
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL3_BMSK                                                        0x8
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL3_SHFT                                                        0x3
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL2_BMSK                                                        0x4
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL2_SHFT                                                        0x2
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL1_BMSK                                                        0x2
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL1_SHFT                                                        0x1
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL0_BMSK                                                        0x1
#define HWIO_GCC_HYP_PLL_SLEEP_ENA_VOTE_GPLL0_SHFT                                                        0x0

#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0005a000)
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_RMSK                                                 0x7f2fed7f
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK                             0x40000000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT                                   0x1e
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK                              0x20000000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT                                    0x1d
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK                          0x10000000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT                                0x1c
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK                          0x8000000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT                               0x1b
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK                           0x4000000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT                                0x1a
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK                       0x2000000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT                            0x19
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK                                 0x1000000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT                                      0x18
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK                                 0x200000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT                                     0x15
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                          0x80000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                             0x13
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_BMSK                              0x40000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_SHFT                                 0x12
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK                          0x20000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT                             0x11
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                          0x10000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                             0x10
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK                               0x8000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT                                  0xf
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_BMSK                               0x4000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_SHFT                                  0xe
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK                                    0x2000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT                                       0xd
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_BMSK                               0x800
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_SHFT                                 0xb
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK                                 0x400
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT                                   0xa
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_BMSK                               0x100
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_SHFT                                 0x8
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK                                          0x40
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT                                           0x6
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK                                           0x20
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT                                            0x5
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK                                       0x10
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT                                        0x4
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK                                        0x8
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT                                        0x3
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK                                   0x4
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT                                   0x2
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK                                       0x2
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT                                       0x1
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK                              0x1
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT                              0x0

#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0005a004)
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_RMSK                                                  0x7f2fed7f
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK                        0x40000000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT                              0x1e
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK                         0x20000000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT                               0x1d
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK                     0x10000000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT                           0x1c
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK                     0x8000000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT                          0x1b
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK                      0x4000000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT                           0x1a
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                  0x2000000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                       0x19
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK                            0x1000000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT                                 0x18
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                            0x200000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                                0x15
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                     0x80000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                        0x13
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                         0x40000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                            0x12
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                     0x20000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                        0x11
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                     0x10000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                        0x10
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                          0x8000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                             0xf
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_BMSK                          0x4000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_SHFT                             0xe
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK                               0x2000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT                                  0xd
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_BMSK                          0x800
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_SHFT                            0xb
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK                            0x400
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT                              0xa
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_BMSK                          0x100
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_SHFT                            0x8
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK                                     0x40
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT                                      0x6
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK                                      0x20
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT                                       0x5
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK                                  0x10
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT                                   0x4
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK                                   0x8
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT                                   0x3
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK                              0x4
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT                              0x2
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK                                  0x2
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT                                  0x1
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                         0x1
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                         0x0

#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0005a008)
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_RMSK                                                0xfffffff
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR)
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_IN)
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK                         0x8000000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT                              0x1b
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK                         0x4000000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT                              0x1a
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK                         0x2000000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT                              0x19
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK                         0x1000000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT                              0x18
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK                          0x800000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT                              0x17
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK                          0x400000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT                              0x16
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK                      0x200000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT                          0x15
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK                      0x100000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT                          0x14
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK                         0x80000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT                            0x13
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK                      0x40000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT                         0x12
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_BMSK                           0x20000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_SHFT                              0x11
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_BMSK                           0x10000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_SHFT                              0x10
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_BMSK                            0x8000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_SHFT                               0xf
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_BMSK                            0x4000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_SHFT                               0xe
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_BMSK                            0x2000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_SHFT                               0xd
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_BMSK                            0x1000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_SHFT                               0xc
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_BMSK                             0x800
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_SHFT                               0xb
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_BMSK                             0x400
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_SHFT                               0xa
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_BMSK                        0x200
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_SHFT                          0x9
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_BMSK                           0x100
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_SHFT                             0x8
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_BMSK                          0x80
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_SHFT                           0x7
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_BMSK                          0x40
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_SHFT                           0x6
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK                          0x20
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT                           0x5
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK                                 0x10
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT                                  0x4
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK                                   0x8
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT                                   0x3
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK                               0x4
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT                               0x2
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK                              0x2
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT                              0x1
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK                               0x1
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT                               0x0

#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0005a00c)
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_RMSK                                                 0xfffffff
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR)
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_IN)
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK                    0x8000000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT                         0x1b
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK                    0x4000000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT                         0x1a
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK                    0x2000000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT                         0x19
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK                    0x1000000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT                         0x18
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK                     0x800000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT                         0x17
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK                     0x400000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT                         0x16
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK                 0x200000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT                     0x15
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK                 0x100000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT                     0x14
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK                    0x80000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT                       0x13
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK                 0x40000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT                    0x12
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_BMSK                      0x20000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_SHFT                         0x11
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_BMSK                      0x10000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_SHFT                         0x10
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_BMSK                       0x8000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_SHFT                          0xf
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_BMSK                       0x4000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_SHFT                          0xe
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_BMSK                       0x2000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_SHFT                          0xd
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_BMSK                       0x1000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_SHFT                          0xc
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_BMSK                        0x800
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_SHFT                          0xb
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_BMSK                        0x400
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_SHFT                          0xa
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_BMSK                   0x200
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_SHFT                     0x9
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_BMSK                      0x100
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_SHFT                        0x8
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_BMSK                     0x80
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_SHFT                      0x7
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_BMSK                     0x40
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_SHFT                      0x6
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                     0x20
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                      0x5
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK                            0x10
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT                             0x4
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK                              0x8
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT                              0x3
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK                          0x4
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT                          0x2
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK                         0x2
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT                         0x1
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK                          0x1
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT                          0x0

#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0005a010)
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_RMSK                                                   0xffff
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ADDR)
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_IN)
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_BMSK                               0x8000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_SHFT                                  0xf
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_BMSK                                0x4000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_SHFT                                   0xe
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_BMSK                            0x2000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_SHFT                               0xd
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_BMSK                           0x1000
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_SHFT                              0xc
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_BMSK                             0x800
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_SHFT                               0xb
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_BMSK                         0x400
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_SHFT                           0xa
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK                             0x200
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT                               0x9
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK                             0x100
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT                               0x8
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK                              0x80
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT                               0x7
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK                              0x40
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT                               0x6
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK                              0x20
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT                               0x5
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK                              0x10
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT                               0x4
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK                          0x8
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT                          0x3
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK                           0x4
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT                           0x2
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK                           0x2
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT                           0x1
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK                             0x1
#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT                             0x0

#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0005a014)
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_RMSK                                                    0xffff
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ADDR)
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_IN)
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_BMSK                          0x8000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_SHFT                             0xf
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_BMSK                           0x4000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_SHFT                              0xe
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_BMSK                       0x2000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_SHFT                          0xd
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_BMSK                      0x1000
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_SHFT                         0xc
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_BMSK                        0x800
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_SHFT                          0xb
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                    0x400
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                      0xa
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK                        0x200
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT                          0x9
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK                        0x100
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT                          0x8
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK                         0x80
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT                          0x7
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK                         0x40
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT                          0x6
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK                         0x20
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT                          0x5
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK                         0x10
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT                          0x4
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK                     0x8
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT                     0x3
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK                      0x4
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT                      0x2
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK                      0x2
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT                      0x1
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK                        0x1
#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT                        0x0

#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0005a018)
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_RMSK                                                        0xfff
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL11_BMSK                                                 0x800
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL11_SHFT                                                   0xb
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL10_BMSK                                                 0x400
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL10_SHFT                                                   0xa
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL9_BMSK                                                  0x200
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL9_SHFT                                                    0x9
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL8_BMSK                                                  0x100
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL8_SHFT                                                    0x8
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL7_BMSK                                                   0x80
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL7_SHFT                                                    0x7
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL6_BMSK                                                   0x40
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL6_SHFT                                                    0x6
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL5_BMSK                                                   0x20
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL5_SHFT                                                    0x5
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL4_BMSK                                                   0x10
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL4_SHFT                                                    0x4
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL3_BMSK                                                    0x8
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL3_SHFT                                                    0x3
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL2_BMSK                                                    0x4
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL2_SHFT                                                    0x2
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL1_BMSK                                                    0x2
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL1_SHFT                                                    0x1
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL0_BMSK                                                    0x1
#define HWIO_GCC_SPARE1_PLL_BRANCH_ENA_VOTE_GPLL0_SHFT                                                    0x0

#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0005a01c)
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_RMSK                                                         0xfff
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL11_BMSK                                                  0x800
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL11_SHFT                                                    0xb
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL10_BMSK                                                  0x400
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL10_SHFT                                                    0xa
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL9_BMSK                                                   0x200
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL9_SHFT                                                     0x9
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL8_BMSK                                                   0x100
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL8_SHFT                                                     0x8
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL7_BMSK                                                    0x80
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL7_SHFT                                                     0x7
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL6_BMSK                                                    0x40
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL6_SHFT                                                     0x6
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL5_BMSK                                                    0x20
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL5_SHFT                                                     0x5
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL4_BMSK                                                    0x10
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL4_SHFT                                                     0x4
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL3_BMSK                                                     0x8
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL3_SHFT                                                     0x3
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL2_BMSK                                                     0x4
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL2_SHFT                                                     0x2
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_SPARE1_PLL_SLEEP_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00069000)
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_RMSK                                                 0x7f2fed7f
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_BMSK                             0x40000000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_PIPE_CLK_ENA_SHFT                                   0x1e
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_BMSK                              0x20000000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_AUX_CLK_ENA_SHFT                                    0x1d
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_BMSK                          0x10000000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_CFG_AHB_CLK_ENA_SHFT                                0x1c
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_BMSK                          0x8000000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_ENA_SHFT                               0x1b
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_BMSK                           0x4000000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_AXI_CLK_ENA_SHFT                                0x1a
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_BMSK                       0x2000000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_ENA_SHFT                            0x19
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_BMSK                                 0x1000000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_IMEM_AXI_CLK_ENA_SHFT                                      0x18
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_BMSK                                 0x200000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_CPUSS_AHB_CLK_ENA_SHFT                                     0x15
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                          0x80000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                             0x13
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_BMSK                              0x40000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_NPU_GPLL0_CLK_SRC_ENA_SHFT                                 0x12
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_BMSK                          0x20000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_ENA_SHFT                             0x11
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_BMSK                          0x10000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_ENA_SHFT                             0x10
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_BMSK                               0x8000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_GPU_GPLL0_CLK_SRC_ENA_SHFT                                  0xf
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_BMSK                               0x4000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_WEST_AHB_CLK_ENA_SHFT                                  0xe
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_BMSK                                    0x2000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_PRNG_AHB_CLK_ENA_SHFT                                       0xd
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_BMSK                               0x800
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_SOUTH_AHB_CLK_ENA_SHFT                                 0xb
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_BMSK                                 0x400
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_BOOT_ROM_AHB_CLK_ENA_SHFT                                   0xa
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_BMSK                               0x100
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_NORTH_AHB_CLK_ENA_SHFT                                 0x8
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_BMSK                                          0x40
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_TLMM_CLK_ENA_SHFT                                           0x6
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_BMSK                                           0x20
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_CLK_ENA_SHFT                                            0x5
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_BMSK                                       0x10
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AXI_CLK_ENA_SHFT                                        0x4
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_BMSK                                        0x8
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_CE1_AHB_CLK_ENA_SHFT                                        0x3
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_BMSK                                   0x4
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_QDSS_CFG_AHB_CLK_ENA_SHFT                                   0x2
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_BMSK                                       0x2
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_TCSR_AHB_CLK_ENA_SHFT                                       0x1
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_BMSK                              0x1
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_ENA_SHFT                              0x0

#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00069004)
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_RMSK                                                  0x7f2fed7f
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_BMSK                        0x40000000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_PIPE_CLK_SLEEP_ENA_SHFT                              0x1e
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_BMSK                         0x20000000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_AUX_CLK_SLEEP_ENA_SHFT                               0x1d
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_BMSK                     0x10000000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_CFG_AHB_CLK_SLEEP_ENA_SHFT                           0x1c
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_BMSK                     0x8000000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_MSTR_AXI_CLK_SLEEP_ENA_SHFT                          0x1b
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_BMSK                      0x4000000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_AXI_CLK_SLEEP_ENA_SHFT                           0x1a
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                  0x2000000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_PCIE_1_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                       0x19
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_BMSK                            0x1000000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_IMEM_AXI_CLK_SLEEP_ENA_SHFT                                 0x18
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                            0x200000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                                0x15
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                     0x80000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                        0x13
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                         0x40000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_NPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                            0x12
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                     0x20000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_MSS_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                        0x11
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_BMSK                     0x10000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_DIV_CLK_SRC_SLEEP_ENA_SHFT                        0x10
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_BMSK                          0x8000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_GPU_GPLL0_CLK_SRC_SLEEP_ENA_SHFT                             0xf
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_BMSK                          0x4000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_WEST_AHB_CLK_SLEEP_ENA_SHFT                             0xe
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_BMSK                               0x2000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_PRNG_AHB_CLK_SLEEP_ENA_SHFT                                  0xd
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_BMSK                          0x800
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_SOUTH_AHB_CLK_SLEEP_ENA_SHFT                            0xb
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_BMSK                            0x400
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_BOOT_ROM_AHB_CLK_SLEEP_ENA_SHFT                              0xa
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_BMSK                          0x100
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_NORTH_AHB_CLK_SLEEP_ENA_SHFT                            0x8
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_BMSK                                     0x40
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_TLMM_CLK_SLEEP_ENA_SHFT                                      0x6
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_BMSK                                      0x20
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_CLK_SLEEP_ENA_SHFT                                       0x5
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_BMSK                                  0x10
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AXI_CLK_SLEEP_ENA_SHFT                                   0x4
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_BMSK                                   0x8
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_CE1_AHB_CLK_SLEEP_ENA_SHFT                                   0x3
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_BMSK                              0x4
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_QDSS_CFG_AHB_CLK_SLEEP_ENA_SHFT                              0x2
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_BMSK                                  0x2
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_TCSR_AHB_CLK_SLEEP_ENA_SHFT                                  0x1
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_BMSK                         0x1
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA_SHFT                         0x0

#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00069008)
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_RMSK                                                0xfffffff
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR)
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_IN)
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_BMSK                         0x8000000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_ENA_SHFT                              0x1b
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_BMSK                         0x4000000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_ENA_SHFT                              0x1a
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_BMSK                         0x2000000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_ENA_SHFT                              0x19
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_BMSK                         0x1000000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_ENA_SHFT                              0x18
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_BMSK                          0x800000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_ENA_SHFT                              0x17
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_BMSK                          0x400000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_ENA_SHFT                              0x16
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_BMSK                      0x200000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_ENA_SHFT                          0x15
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_BMSK                      0x100000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_ENA_SHFT                          0x14
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_BMSK                         0x80000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_ENA_SHFT                            0x13
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_BMSK                      0x40000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_ENA_SHFT                         0x12
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_BMSK                           0x20000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_ENA_SHFT                              0x11
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_BMSK                           0x10000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_ENA_SHFT                              0x10
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_BMSK                            0x8000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_ENA_SHFT                               0xf
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_BMSK                            0x4000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_ENA_SHFT                               0xe
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_BMSK                            0x2000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_ENA_SHFT                               0xd
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_BMSK                            0x1000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_ENA_SHFT                               0xc
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_BMSK                             0x800
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_ENA_SHFT                               0xb
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_BMSK                             0x400
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_ENA_SHFT                               0xa
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_BMSK                        0x200
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_ENA_SHFT                          0x9
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_BMSK                           0x100
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_ENA_SHFT                             0x8
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_BMSK                          0x80
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_ENA_SHFT                           0x7
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_BMSK                          0x40
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_ENA_SHFT                           0x6
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_BMSK                          0x20
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_ENA_SHFT                           0x5
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_BMSK                                 0x10
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_PIPE_CLK_ENA_SHFT                                  0x4
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_BMSK                                   0x8
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_AUX_CLK_ENA_SHFT                                   0x3
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_BMSK                               0x4
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_ENA_SHFT                               0x2
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_BMSK                              0x2
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_ENA_SHFT                              0x1
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_BMSK                               0x1
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_ENA_SHFT                               0x0

#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0006900c)
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_RMSK                                                 0xfffffff
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_IN          \
        in_dword(HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR)
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR, m)
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_OUT(v)      \
        out_dword(HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR,v)
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR,m,v,HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_IN)
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_BMSK                    0x8000000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S5_CLK_SLEEP_ENA_SHFT                         0x1b
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_BMSK                    0x4000000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S4_CLK_SLEEP_ENA_SHFT                         0x1a
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_BMSK                    0x2000000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S3_CLK_SLEEP_ENA_SHFT                         0x19
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_BMSK                    0x1000000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S2_CLK_SLEEP_ENA_SHFT                         0x18
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_BMSK                     0x800000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S1_CLK_SLEEP_ENA_SHFT                         0x17
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_BMSK                     0x400000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_S0_CLK_SLEEP_ENA_SHFT                         0x16
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_BMSK                 0x200000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_S_AHB_CLK_SLEEP_ENA_SHFT                     0x15
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_BMSK                 0x100000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_1_M_AHB_CLK_SLEEP_ENA_SHFT                     0x14
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_BMSK                    0x80000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_CLK_SLEEP_ENA_SHFT                       0x13
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_BMSK                 0x40000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP1_CORE_2X_CLK_SLEEP_ENA_SHFT                    0x12
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_BMSK                      0x20000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S7_CLK_SLEEP_ENA_SHFT                         0x11
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_BMSK                      0x10000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S6_CLK_SLEEP_ENA_SHFT                         0x10
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_BMSK                       0x8000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S5_CLK_SLEEP_ENA_SHFT                          0xf
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_BMSK                       0x4000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S4_CLK_SLEEP_ENA_SHFT                          0xe
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_BMSK                       0x2000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S3_CLK_SLEEP_ENA_SHFT                          0xd
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_BMSK                       0x1000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S2_CLK_SLEEP_ENA_SHFT                          0xc
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_BMSK                        0x800
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S1_CLK_SLEEP_ENA_SHFT                          0xb
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_BMSK                        0x400
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_S0_CLK_SLEEP_ENA_SHFT                          0xa
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_BMSK                   0x200
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_2X_CLK_SLEEP_ENA_SHFT                     0x9
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_BMSK                      0x100
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP0_CORE_CLK_SLEEP_ENA_SHFT                        0x8
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_BMSK                     0x80
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_S_AHB_CLK_SLEEP_ENA_SHFT                      0x7
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_BMSK                     0x40
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_QUPV3_WRAP_0_M_AHB_CLK_SLEEP_ENA_SHFT                      0x6
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                     0x20
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                      0x5
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_BMSK                            0x10
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_PIPE_CLK_SLEEP_ENA_SHFT                             0x4
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_BMSK                              0x8
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_AUX_CLK_SLEEP_ENA_SHFT                              0x3
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_BMSK                          0x4
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_CFG_AHB_CLK_SLEEP_ENA_SHFT                          0x2
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_BMSK                         0x2
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_MSTR_AXI_CLK_SLEEP_ENA_SHFT                         0x1
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_BMSK                          0x1
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_1_PCIE_0_SLV_AXI_CLK_SLEEP_ENA_SHFT                          0x0

#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00069010)
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_RMSK                                                   0xffff
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR)
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_IN)
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_BMSK                               0x8000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_PIPE_CLK_ENA_SHFT                                  0xf
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_BMSK                                0x4000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_AUX_CLK_ENA_SHFT                                   0xe
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_BMSK                            0x2000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_ENA_SHFT                               0xd
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_BMSK                           0x1000
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_ENA_SHFT                              0xc
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_BMSK                             0x800
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_ENA_SHFT                               0xb
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_BMSK                         0x400
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_ENA_SHFT                           0xa
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_BMSK                             0x200
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_ENA_SHFT                               0x9
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_BMSK                             0x100
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_ENA_SHFT                               0x8
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_BMSK                              0x80
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_ENA_SHFT                               0x7
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_BMSK                              0x40
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_ENA_SHFT                               0x6
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_BMSK                              0x20
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_ENA_SHFT                               0x5
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_BMSK                              0x10
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_ENA_SHFT                               0x4
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_BMSK                          0x8
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_ENA_SHFT                          0x3
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_BMSK                           0x4
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_ENA_SHFT                           0x2
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_BMSK                           0x2
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_ENA_SHFT                           0x1
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_BMSK                             0x1
#define HWIO_GCC_NPU_Q6_CLOCK_BRANCH_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_ENA_SHFT                             0x0

#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00069014)
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_RMSK                                                    0xffff
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_IN          \
        in_dword(HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR)
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR, m)
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_OUT(v)      \
        out_dword(HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR,v)
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR,m,v,HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_IN)
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_BMSK                          0x8000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_PIPE_CLK_SLEEP_ENA_SHFT                             0xf
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_BMSK                           0x4000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_AUX_CLK_SLEEP_ENA_SHFT                              0xe
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_BMSK                       0x2000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_CFG_AHB_CLK_SLEEP_ENA_SHFT                          0xd
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_BMSK                      0x1000
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_MSTR_AXI_CLK_SLEEP_ENA_SHFT                         0xc
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_BMSK                        0x800
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_AXI_CLK_SLEEP_ENA_SHFT                          0xb
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_BMSK                    0x400
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_PCIE_2_SLV_Q2A_AXI_CLK_SLEEP_ENA_SHFT                      0xa
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_BMSK                        0x200
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S5_CLK_SLEEP_ENA_SHFT                          0x9
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_BMSK                        0x100
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S4_CLK_SLEEP_ENA_SHFT                          0x8
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_BMSK                         0x80
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S3_CLK_SLEEP_ENA_SHFT                          0x7
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_BMSK                         0x40
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S2_CLK_SLEEP_ENA_SHFT                          0x6
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_BMSK                         0x20
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S1_CLK_SLEEP_ENA_SHFT                          0x5
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_BMSK                         0x10
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_S0_CLK_SLEEP_ENA_SHFT                          0x4
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_BMSK                     0x8
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_2X_CLK_SLEEP_ENA_SHFT                     0x3
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_BMSK                      0x4
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_M_AHB_CLK_SLEEP_ENA_SHFT                      0x2
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_BMSK                      0x2
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP_2_S_AHB_CLK_SLEEP_ENA_SHFT                      0x1
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_BMSK                        0x1
#define HWIO_GCC_NPU_Q6_CLOCK_SLEEP_ENA_VOTE_2_QUPV3_WRAP2_CORE_CLK_SLEEP_ENA_SHFT                        0x0

#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00069018)
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_RMSK                                                        0xfff
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_ADDR)
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_ADDR, m)
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_ADDR,v)
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_ADDR,m,v,HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_IN)
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL11_BMSK                                                 0x800
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL11_SHFT                                                   0xb
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL10_BMSK                                                 0x400
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL10_SHFT                                                   0xa
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL9_BMSK                                                  0x200
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL9_SHFT                                                    0x9
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL8_BMSK                                                  0x100
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL8_SHFT                                                    0x8
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL7_BMSK                                                   0x80
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL7_SHFT                                                    0x7
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL6_BMSK                                                   0x40
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL6_SHFT                                                    0x6
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL5_BMSK                                                   0x20
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL5_SHFT                                                    0x5
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL4_BMSK                                                   0x10
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL4_SHFT                                                    0x4
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL3_BMSK                                                    0x8
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL3_SHFT                                                    0x3
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL2_BMSK                                                    0x4
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL2_SHFT                                                    0x2
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL1_BMSK                                                    0x2
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL1_SHFT                                                    0x1
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL0_BMSK                                                    0x1
#define HWIO_GCC_NPU_Q6_PLL_BRANCH_ENA_VOTE_GPLL0_SHFT                                                    0x0

#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0006901c)
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_RMSK                                                         0xfff
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_ADDR)
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_ADDR, m)
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_ADDR,v)
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_ADDR,m,v,HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_IN)
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL11_BMSK                                                  0x800
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL11_SHFT                                                    0xb
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL10_BMSK                                                  0x400
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL10_SHFT                                                    0xa
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL9_BMSK                                                   0x200
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL9_SHFT                                                     0x9
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL8_BMSK                                                   0x100
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL8_SHFT                                                     0x8
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL7_BMSK                                                    0x80
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL7_SHFT                                                     0x7
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL6_BMSK                                                    0x40
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL6_SHFT                                                     0x6
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL5_BMSK                                                    0x20
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL5_SHFT                                                     0x5
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL4_BMSK                                                    0x10
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL4_SHFT                                                     0x4
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL3_BMSK                                                     0x8
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL3_SHFT                                                     0x3
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL2_BMSK                                                     0x4
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL2_SHFT                                                     0x2
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_NPU_Q6_PLL_SLEEP_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0006c014)
#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_RMSK                                                                0x1
#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_0_LINK_DOWN_BCR_ADDR)
#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_LINK_DOWN_BCR_ADDR, m)
#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_LINK_DOWN_BCR_ADDR,v)
#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_LINK_DOWN_BCR_ADDR,m,v,HWIO_GCC_PCIE_0_LINK_DOWN_BCR_IN)
#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_BLK_ARES_BMSK                                                       0x1
#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_BLK_ARES_SHFT                                                       0x0

#define HWIO_GCC_PCIE_0_MISC_RESET_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0006c018)
#define HWIO_GCC_PCIE_0_MISC_RESET_RMSK                                                                  0xff
#define HWIO_GCC_PCIE_0_MISC_RESET_IN          \
        in_dword(HWIO_GCC_PCIE_0_MISC_RESET_ADDR)
#define HWIO_GCC_PCIE_0_MISC_RESET_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_MISC_RESET_ADDR, m)
#define HWIO_GCC_PCIE_0_MISC_RESET_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_MISC_RESET_ADDR,v)
#define HWIO_GCC_PCIE_0_MISC_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_MISC_RESET_ADDR,m,v,HWIO_GCC_PCIE_0_MISC_RESET_IN)
#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_SLV_AXI_STICKY_BCR_BLK_ARES_BMSK                               0x80
#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_SLV_AXI_STICKY_BCR_BLK_ARES_SHFT                                0x7
#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_CORE_STICKY_BCR_BLK_ARES_BMSK                                  0x40
#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_CORE_STICKY_BCR_BLK_ARES_SHFT                                   0x6
#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_MSTR_AXI_STICKY_BCR_BLK_ARES_BMSK                              0x20
#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_MSTR_AXI_STICKY_BCR_BLK_ARES_SHFT                               0x5
#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_PIPE_BCR_BLK_ARES_BMSK                                         0x10
#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_PIPE_BCR_BLK_ARES_SHFT                                          0x4
#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_AUX_BCR_BLK_ARES_BMSK                                           0x8
#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_AUX_BCR_BLK_ARES_SHFT                                           0x3
#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_CFG_AHB_BCR_BLK_ARES_BMSK                                       0x4
#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_CFG_AHB_BCR_BLK_ARES_SHFT                                       0x2
#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_MSTR_AXI_BCR_BLK_ARES_BMSK                                      0x2
#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_MSTR_AXI_BCR_BLK_ARES_SHFT                                      0x1
#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_SLV_AXI_BCR_BLK_ARES_BMSK                                       0x1
#define HWIO_GCC_PCIE_0_MISC_RESET_PCIE_0_SLV_AXI_BCR_BLK_ARES_SHFT                                       0x0

#define HWIO_GCC_PCIE_0_PHY_BCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0006c01c)
#define HWIO_GCC_PCIE_0_PHY_BCR_RMSK                                                                      0x1
#define HWIO_GCC_PCIE_0_PHY_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_0_PHY_BCR_ADDR)
#define HWIO_GCC_PCIE_0_PHY_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_PHY_BCR_ADDR, m)
#define HWIO_GCC_PCIE_0_PHY_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_PHY_BCR_ADDR,v)
#define HWIO_GCC_PCIE_0_PHY_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_0_PHY_BCR_IN)
#define HWIO_GCC_PCIE_0_PHY_BCR_BLK_ARES_BMSK                                                             0x1
#define HWIO_GCC_PCIE_0_PHY_BCR_BLK_ARES_SHFT                                                             0x0

#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0006c020)
#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_RMSK                                                            0x1
#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_ADDR)
#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_ADDR, m)
#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_ADDR,v)
#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_IN)
#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_BLK_ARES_BMSK                                                   0x1
#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_BLK_ARES_SHFT                                                   0x0

#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0006c028)
#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_RMSK                                                        0x1
#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_ADDR)
#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_ADDR, m)
#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_ADDR,v)
#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_IN)
#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_BMSK                                               0x1
#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_SHFT                                               0x0

#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0006f00c)
#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_RMSK                                                                0x1
#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR)
#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR, m)
#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR,v)
#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR,m,v,HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_IN)
#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_BLK_ARES_BMSK                                                       0x1
#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_BLK_ARES_SHFT                                                       0x0

#define HWIO_GCC_PCIE_PHY_COM_BCR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0006f010)
#define HWIO_GCC_PCIE_PHY_COM_BCR_RMSK                                                                    0x1
#define HWIO_GCC_PCIE_PHY_COM_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_PHY_COM_BCR_ADDR)
#define HWIO_GCC_PCIE_PHY_COM_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_PHY_COM_BCR_ADDR, m)
#define HWIO_GCC_PCIE_PHY_COM_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_PHY_COM_BCR_ADDR,v)
#define HWIO_GCC_PCIE_PHY_COM_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_PHY_COM_BCR_ADDR,m,v,HWIO_GCC_PCIE_PHY_COM_BCR_IN)
#define HWIO_GCC_PCIE_PHY_COM_BCR_BLK_ARES_BMSK                                                           0x1
#define HWIO_GCC_PCIE_PHY_COM_BCR_BLK_ARES_SHFT                                                           0x0

#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0008e014)
#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_RMSK                                                                0x1
#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_1_LINK_DOWN_BCR_ADDR)
#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_LINK_DOWN_BCR_ADDR, m)
#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_LINK_DOWN_BCR_ADDR,v)
#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_LINK_DOWN_BCR_ADDR,m,v,HWIO_GCC_PCIE_1_LINK_DOWN_BCR_IN)
#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_BLK_ARES_BMSK                                                       0x1
#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_BLK_ARES_SHFT                                                       0x0

#define HWIO_GCC_PCIE_1_MISC_RESET_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0008e018)
#define HWIO_GCC_PCIE_1_MISC_RESET_RMSK                                                                  0xff
#define HWIO_GCC_PCIE_1_MISC_RESET_IN          \
        in_dword(HWIO_GCC_PCIE_1_MISC_RESET_ADDR)
#define HWIO_GCC_PCIE_1_MISC_RESET_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_MISC_RESET_ADDR, m)
#define HWIO_GCC_PCIE_1_MISC_RESET_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_MISC_RESET_ADDR,v)
#define HWIO_GCC_PCIE_1_MISC_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_MISC_RESET_ADDR,m,v,HWIO_GCC_PCIE_1_MISC_RESET_IN)
#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_SLV_AXI_STICKY_BCR_BLK_ARES_BMSK                               0x80
#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_SLV_AXI_STICKY_BCR_BLK_ARES_SHFT                                0x7
#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_CORE_STICKY_BCR_BLK_ARES_BMSK                                  0x40
#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_CORE_STICKY_BCR_BLK_ARES_SHFT                                   0x6
#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_MSTR_AXI_STICKY_BCR_BLK_ARES_BMSK                              0x20
#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_MSTR_AXI_STICKY_BCR_BLK_ARES_SHFT                               0x5
#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_PIPE_BCR_BLK_ARES_BMSK                                         0x10
#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_PIPE_BCR_BLK_ARES_SHFT                                          0x4
#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_AUX_BCR_BLK_ARES_BMSK                                           0x8
#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_AUX_BCR_BLK_ARES_SHFT                                           0x3
#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_CFG_AHB_BCR_BLK_ARES_BMSK                                       0x4
#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_CFG_AHB_BCR_BLK_ARES_SHFT                                       0x2
#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_MSTR_AXI_BCR_BLK_ARES_BMSK                                      0x2
#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_MSTR_AXI_BCR_BLK_ARES_SHFT                                      0x1
#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_SLV_AXI_BCR_BLK_ARES_BMSK                                       0x1
#define HWIO_GCC_PCIE_1_MISC_RESET_PCIE_1_SLV_AXI_BCR_BLK_ARES_SHFT                                       0x0

#define HWIO_GCC_PCIE_1_PHY_BCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0008e01c)
#define HWIO_GCC_PCIE_1_PHY_BCR_RMSK                                                                      0x1
#define HWIO_GCC_PCIE_1_PHY_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_1_PHY_BCR_ADDR)
#define HWIO_GCC_PCIE_1_PHY_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_PHY_BCR_ADDR, m)
#define HWIO_GCC_PCIE_1_PHY_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_PHY_BCR_ADDR,v)
#define HWIO_GCC_PCIE_1_PHY_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_1_PHY_BCR_IN)
#define HWIO_GCC_PCIE_1_PHY_BCR_BLK_ARES_BMSK                                                             0x1
#define HWIO_GCC_PCIE_1_PHY_BCR_BLK_ARES_SHFT                                                             0x0

#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0008e020)
#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_RMSK                                                            0x1
#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_ADDR)
#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_ADDR, m)
#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_ADDR,v)
#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_IN)
#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_BLK_ARES_BMSK                                                   0x1
#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_BLK_ARES_SHFT                                                   0x0

#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0008e000)
#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_RMSK                                                        0x1
#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_ADDR)
#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_ADDR, m)
#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_ADDR,v)
#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_IN)
#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_BMSK                                               0x1
#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_SHFT                                               0x0

#define HWIO_GCC_PCIE_2_LINK_DOWN_BCR_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0001f014)
#define HWIO_GCC_PCIE_2_LINK_DOWN_BCR_RMSK                                                                0x1
#define HWIO_GCC_PCIE_2_LINK_DOWN_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_2_LINK_DOWN_BCR_ADDR)
#define HWIO_GCC_PCIE_2_LINK_DOWN_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_LINK_DOWN_BCR_ADDR, m)
#define HWIO_GCC_PCIE_2_LINK_DOWN_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_LINK_DOWN_BCR_ADDR,v)
#define HWIO_GCC_PCIE_2_LINK_DOWN_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_LINK_DOWN_BCR_ADDR,m,v,HWIO_GCC_PCIE_2_LINK_DOWN_BCR_IN)
#define HWIO_GCC_PCIE_2_LINK_DOWN_BCR_BLK_ARES_BMSK                                                       0x1
#define HWIO_GCC_PCIE_2_LINK_DOWN_BCR_BLK_ARES_SHFT                                                       0x0

#define HWIO_GCC_PCIE_2_MISC_RESET_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0001f018)
#define HWIO_GCC_PCIE_2_MISC_RESET_RMSK                                                                  0xff
#define HWIO_GCC_PCIE_2_MISC_RESET_IN          \
        in_dword(HWIO_GCC_PCIE_2_MISC_RESET_ADDR)
#define HWIO_GCC_PCIE_2_MISC_RESET_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_MISC_RESET_ADDR, m)
#define HWIO_GCC_PCIE_2_MISC_RESET_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_MISC_RESET_ADDR,v)
#define HWIO_GCC_PCIE_2_MISC_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_MISC_RESET_ADDR,m,v,HWIO_GCC_PCIE_2_MISC_RESET_IN)
#define HWIO_GCC_PCIE_2_MISC_RESET_PCIE_2_SLV_AXI_STICKY_BCR_BLK_ARES_BMSK                               0x80
#define HWIO_GCC_PCIE_2_MISC_RESET_PCIE_2_SLV_AXI_STICKY_BCR_BLK_ARES_SHFT                                0x7
#define HWIO_GCC_PCIE_2_MISC_RESET_PCIE_2_CORE_STICKY_BCR_BLK_ARES_BMSK                                  0x40
#define HWIO_GCC_PCIE_2_MISC_RESET_PCIE_2_CORE_STICKY_BCR_BLK_ARES_SHFT                                   0x6
#define HWIO_GCC_PCIE_2_MISC_RESET_PCIE_2_MSTR_AXI_STICKY_BCR_BLK_ARES_BMSK                              0x20
#define HWIO_GCC_PCIE_2_MISC_RESET_PCIE_2_MSTR_AXI_STICKY_BCR_BLK_ARES_SHFT                               0x5
#define HWIO_GCC_PCIE_2_MISC_RESET_PCIE_2_PIPE_BCR_BLK_ARES_BMSK                                         0x10
#define HWIO_GCC_PCIE_2_MISC_RESET_PCIE_2_PIPE_BCR_BLK_ARES_SHFT                                          0x4
#define HWIO_GCC_PCIE_2_MISC_RESET_PCIE_2_AUX_BCR_BLK_ARES_BMSK                                           0x8
#define HWIO_GCC_PCIE_2_MISC_RESET_PCIE_2_AUX_BCR_BLK_ARES_SHFT                                           0x3
#define HWIO_GCC_PCIE_2_MISC_RESET_PCIE_2_CFG_AHB_BCR_BLK_ARES_BMSK                                       0x4
#define HWIO_GCC_PCIE_2_MISC_RESET_PCIE_2_CFG_AHB_BCR_BLK_ARES_SHFT                                       0x2
#define HWIO_GCC_PCIE_2_MISC_RESET_PCIE_2_MSTR_AXI_BCR_BLK_ARES_BMSK                                      0x2
#define HWIO_GCC_PCIE_2_MISC_RESET_PCIE_2_MSTR_AXI_BCR_BLK_ARES_SHFT                                      0x1
#define HWIO_GCC_PCIE_2_MISC_RESET_PCIE_2_SLV_AXI_BCR_BLK_ARES_BMSK                                       0x1
#define HWIO_GCC_PCIE_2_MISC_RESET_PCIE_2_SLV_AXI_BCR_BLK_ARES_SHFT                                       0x0

#define HWIO_GCC_PCIE_2_PHY_BCR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0001f01c)
#define HWIO_GCC_PCIE_2_PHY_BCR_RMSK                                                                      0x1
#define HWIO_GCC_PCIE_2_PHY_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_2_PHY_BCR_ADDR)
#define HWIO_GCC_PCIE_2_PHY_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_PHY_BCR_ADDR, m)
#define HWIO_GCC_PCIE_2_PHY_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_PHY_BCR_ADDR,v)
#define HWIO_GCC_PCIE_2_PHY_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_2_PHY_BCR_IN)
#define HWIO_GCC_PCIE_2_PHY_BCR_BLK_ARES_BMSK                                                             0x1
#define HWIO_GCC_PCIE_2_PHY_BCR_BLK_ARES_SHFT                                                             0x0

#define HWIO_GCC_PCIE_2_NOCSR_COM_PHY_BCR_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0001f020)
#define HWIO_GCC_PCIE_2_NOCSR_COM_PHY_BCR_RMSK                                                            0x1
#define HWIO_GCC_PCIE_2_NOCSR_COM_PHY_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_2_NOCSR_COM_PHY_BCR_ADDR)
#define HWIO_GCC_PCIE_2_NOCSR_COM_PHY_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_NOCSR_COM_PHY_BCR_ADDR, m)
#define HWIO_GCC_PCIE_2_NOCSR_COM_PHY_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_NOCSR_COM_PHY_BCR_ADDR,v)
#define HWIO_GCC_PCIE_2_NOCSR_COM_PHY_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_NOCSR_COM_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_2_NOCSR_COM_PHY_BCR_IN)
#define HWIO_GCC_PCIE_2_NOCSR_COM_PHY_BCR_BLK_ARES_BMSK                                                   0x1
#define HWIO_GCC_PCIE_2_NOCSR_COM_PHY_BCR_BLK_ARES_SHFT                                                   0x0

#define HWIO_GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0001f028)
#define HWIO_GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR_RMSK                                                        0x1
#define HWIO_GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR_IN          \
        in_dword(HWIO_GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR_ADDR)
#define HWIO_GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR_ADDR, m)
#define HWIO_GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR_ADDR,v)
#define HWIO_GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR_ADDR,m,v,HWIO_GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR_IN)
#define HWIO_GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_BMSK                                               0x1
#define HWIO_GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR_BLK_ARES_SHFT                                               0x0

#define HWIO_GCC_SSC_RESET_ADDR                                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00063020)
#define HWIO_GCC_SSC_RESET_RMSK                                                                           0x1
#define HWIO_GCC_SSC_RESET_IN          \
        in_dword(HWIO_GCC_SSC_RESET_ADDR)
#define HWIO_GCC_SSC_RESET_INM(m)      \
        in_dword_masked(HWIO_GCC_SSC_RESET_ADDR, m)
#define HWIO_GCC_SSC_RESET_OUT(v)      \
        out_dword(HWIO_GCC_SSC_RESET_ADDR,v)
#define HWIO_GCC_SSC_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SSC_RESET_ADDR,m,v,HWIO_GCC_SSC_RESET_IN)
#define HWIO_GCC_SSC_RESET_SSC_ARES_BMSK                                                                  0x1
#define HWIO_GCC_SSC_RESET_SSC_ARES_SHFT                                                                  0x0

#define HWIO_GCC_LPASS_RESET_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00047030)
#define HWIO_GCC_LPASS_RESET_RMSK                                                                         0x1
#define HWIO_GCC_LPASS_RESET_IN          \
        in_dword(HWIO_GCC_LPASS_RESET_ADDR)
#define HWIO_GCC_LPASS_RESET_INM(m)      \
        in_dword_masked(HWIO_GCC_LPASS_RESET_ADDR, m)
#define HWIO_GCC_LPASS_RESET_OUT(v)      \
        out_dword(HWIO_GCC_LPASS_RESET_ADDR,v)
#define HWIO_GCC_LPASS_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_LPASS_RESET_ADDR,m,v,HWIO_GCC_LPASS_RESET_IN)
#define HWIO_GCC_LPASS_RESET_LPASS_ARES_BMSK                                                              0x1
#define HWIO_GCC_LPASS_RESET_LPASS_ARES_SHFT                                                              0x0

#define HWIO_GCC_DEBUG_MUX_MUXR_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00062000)
#define HWIO_GCC_DEBUG_MUX_MUXR_RMSK                                                                    0x3ff
#define HWIO_GCC_DEBUG_MUX_MUXR_IN          \
        in_dword(HWIO_GCC_DEBUG_MUX_MUXR_ADDR)
#define HWIO_GCC_DEBUG_MUX_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_DEBUG_MUX_MUXR_ADDR, m)
#define HWIO_GCC_DEBUG_MUX_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_DEBUG_MUX_MUXR_ADDR,v)
#define HWIO_GCC_DEBUG_MUX_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DEBUG_MUX_MUXR_ADDR,m,v,HWIO_GCC_DEBUG_MUX_MUXR_IN)
#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_BMSK                                                            0x3ff
#define HWIO_GCC_DEBUG_MUX_MUXR_MUX_SEL_SHFT                                                              0x0

#define HWIO_GCC_PLL_TEST_MUX_MUXR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0006200c)
#define HWIO_GCC_PLL_TEST_MUX_MUXR_RMSK                                                                  0x3f
#define HWIO_GCC_PLL_TEST_MUX_MUXR_IN          \
        in_dword(HWIO_GCC_PLL_TEST_MUX_MUXR_ADDR)
#define HWIO_GCC_PLL_TEST_MUX_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_PLL_TEST_MUX_MUXR_ADDR, m)
#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_PLL_TEST_MUX_MUXR_ADDR,v)
#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PLL_TEST_MUX_MUXR_ADDR,m,v,HWIO_GCC_PLL_TEST_MUX_MUXR_IN)
#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_BMSK                                                          0x3f
#define HWIO_GCC_PLL_TEST_MUX_MUXR_OUT_SEL_SHFT                                                           0x0

#define HWIO_GCC_PLL_RESET_N_MUXR_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00062018)
#define HWIO_GCC_PLL_RESET_N_MUXR_RMSK                                                                   0x1f
#define HWIO_GCC_PLL_RESET_N_MUXR_IN          \
        in_dword(HWIO_GCC_PLL_RESET_N_MUXR_ADDR)
#define HWIO_GCC_PLL_RESET_N_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_PLL_RESET_N_MUXR_ADDR, m)
#define HWIO_GCC_PLL_RESET_N_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_PLL_RESET_N_MUXR_ADDR,v)
#define HWIO_GCC_PLL_RESET_N_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PLL_RESET_N_MUXR_ADDR,m,v,HWIO_GCC_PLL_RESET_N_MUXR_IN)
#define HWIO_GCC_PLL_RESET_N_MUXR_PLL_RESETN_MUX_SEL_BMSK                                                0x1f
#define HWIO_GCC_PLL_RESET_N_MUXR_PLL_RESETN_MUX_SEL_SHFT                                                 0x0

#define HWIO_GCC_PLL_STATUS_MUXR_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0006201c)
#define HWIO_GCC_PLL_STATUS_MUXR_RMSK                                                                    0x1f
#define HWIO_GCC_PLL_STATUS_MUXR_IN          \
        in_dword(HWIO_GCC_PLL_STATUS_MUXR_ADDR)
#define HWIO_GCC_PLL_STATUS_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_PLL_STATUS_MUXR_ADDR, m)
#define HWIO_GCC_PLL_STATUS_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_PLL_STATUS_MUXR_ADDR,v)
#define HWIO_GCC_PLL_STATUS_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PLL_STATUS_MUXR_ADDR,m,v,HWIO_GCC_PLL_STATUS_MUXR_IN)
#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_BMSK                                                      0x1f
#define HWIO_GCC_PLL_STATUS_MUXR_DEBUG_BUS_SEL_SHFT                                                       0x0

#define HWIO_GCC_PLL_BYPASSNL_MUXR_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00062020)
#define HWIO_GCC_PLL_BYPASSNL_MUXR_RMSK                                                                   0xf
#define HWIO_GCC_PLL_BYPASSNL_MUXR_IN          \
        in_dword(HWIO_GCC_PLL_BYPASSNL_MUXR_ADDR)
#define HWIO_GCC_PLL_BYPASSNL_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_PLL_BYPASSNL_MUXR_ADDR, m)
#define HWIO_GCC_PLL_BYPASSNL_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_PLL_BYPASSNL_MUXR_ADDR,v)
#define HWIO_GCC_PLL_BYPASSNL_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PLL_BYPASSNL_MUXR_ADDR,m,v,HWIO_GCC_PLL_BYPASSNL_MUXR_IN)
#define HWIO_GCC_PLL_BYPASSNL_MUXR_PLL_BYPASSNL_MUX_SEL_BMSK                                              0xf
#define HWIO_GCC_PLL_BYPASSNL_MUXR_PLL_BYPASSNL_MUX_SEL_SHFT                                              0x0

#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00062030)
#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_RMSK                                                          0x1
#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_IN          \
        in_dword(HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_ADDR)
#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_ADDR, m)
#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_ADDR,v)
#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_ADDR,m,v,HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_IN)
#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_PLLTEST_DE_SEL_BMSK                                           0x1
#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_PLLTEST_DE_SEL_SHFT                                           0x0

#define HWIO_GCC_PLLTEST_PAD_CFG_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00062034)
#define HWIO_GCC_PLLTEST_PAD_CFG_RMSK                                                               0x3ffffff
#define HWIO_GCC_PLLTEST_PAD_CFG_IN          \
        in_dword(HWIO_GCC_PLLTEST_PAD_CFG_ADDR)
#define HWIO_GCC_PLLTEST_PAD_CFG_INM(m)      \
        in_dword_masked(HWIO_GCC_PLLTEST_PAD_CFG_ADDR, m)
#define HWIO_GCC_PLLTEST_PAD_CFG_OUT(v)      \
        out_dword(HWIO_GCC_PLLTEST_PAD_CFG_ADDR,v)
#define HWIO_GCC_PLLTEST_PAD_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PLLTEST_PAD_CFG_ADDR,m,v,HWIO_GCC_PLLTEST_PAD_CFG_IN)
#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_B_BMSK                                                    0x3000000
#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_B_SHFT                                                         0x18
#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BITS23_20_BMSK                                              0xf00000
#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BITS23_20_SHFT                                                  0x14
#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_EN_BMSK                                                     0x80000
#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_PLL_EN_SHFT                                                        0x13
#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BIT18_BMSK                                                   0x40000
#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BIT18_SHFT                                                      0x12
#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_OE_BMSK                                                         0x20000
#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_OE_SHFT                                                            0x11
#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BIT16_BMSK                                                   0x10000
#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BIT16_SHFT                                                      0x10
#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_IE_BMSK                                                          0x8000
#define HWIO_GCC_PLLTEST_PAD_CFG_CORE_IE_SHFT                                                             0xf
#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BIT14_BMSK                                                    0x4000
#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BIT14_SHFT                                                       0xe
#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_BMSK                                                           0x3800
#define HWIO_GCC_PLLTEST_PAD_CFG_HDRIVE_SHFT                                                              0xb
#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BITS10_6_BMSK                                                  0x7c0
#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BITS10_6_SHFT                                                    0x6
#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BITS5_0_BMSK                                                    0x3f
#define HWIO_GCC_PLLTEST_PAD_CFG_RESERVE_BITS5_0_SHFT                                                     0x0

#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00062038)
#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_RMSK                                                          0x3fffff
#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_IN          \
        in_dword(HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR)
#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR, m)
#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_OUT(v)      \
        out_dword(HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR,v)
#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR,m,v,HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_IN)
#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CLR_CNT_BMSK                                                  0x200000
#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CLR_CNT_SHFT                                                      0x15
#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CNT_EN_BMSK                                                   0x100000
#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_CNT_EN_SHFT                                                       0x14
#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_XO_DIV4_TERM_CNT_BMSK                                          0xfffff
#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_XO_DIV4_TERM_CNT_SHFT                                              0x0

#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0006203c)
#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_RMSK                                                      0x3ffffff
#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_IN          \
        in_dword(HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_ADDR)
#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_ADDR, m)
#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_XO_DIV4_CNT_DONE_BMSK                                     0x2000000
#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_XO_DIV4_CNT_DONE_SHFT                                          0x19
#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_MEASURE_CNT_BMSK                                          0x1ffffff
#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_MEASURE_CNT_SHFT                                                0x0

#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00078040)
#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_RMSK                                                                 0x1
#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_IN          \
        in_dword(HWIO_GCC_GDS_HW_CTRL_SW_OVRD_ADDR)
#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_INM(m)      \
        in_dword_masked(HWIO_GCC_GDS_HW_CTRL_SW_OVRD_ADDR, m)
#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_OUT(v)      \
        out_dword(HWIO_GCC_GDS_HW_CTRL_SW_OVRD_ADDR,v)
#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GDS_HW_CTRL_SW_OVRD_ADDR,m,v,HWIO_GCC_GDS_HW_CTRL_SW_OVRD_IN)
#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_SW_OVERRIDE_BMSK                                                     0x1
#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_SW_OVERRIDE_SHFT                                                     0x0

#define HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00067000)
#define HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_RMSK                                                             0x1
#define HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_IN          \
        in_dword(HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_ADDR)
#define HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_ADDR, m)
#define HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_OUT(v)      \
        out_dword(HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_ADDR,v)
#define HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_ADDR,m,v,HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_IN)
#define HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_CLK_ENABLE_SHFT                                                  0x0

#define HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00067020)
#define HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_RMSK                                                              0x1
#define HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_IN          \
        in_dword(HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_ADDR)
#define HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_ADDR, m)
#define HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_OUT(v)      \
        out_dword(HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_ADDR,v)
#define HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_ADDR,m,v,HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_IN)
#define HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_USB_BOOT_CLOCK_CTL_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00068000)
#define HWIO_GCC_USB_BOOT_CLOCK_CTL_RMSK                                                                  0x1
#define HWIO_GCC_USB_BOOT_CLOCK_CTL_IN          \
        in_dword(HWIO_GCC_USB_BOOT_CLOCK_CTL_ADDR)
#define HWIO_GCC_USB_BOOT_CLOCK_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_USB_BOOT_CLOCK_CTL_ADDR, m)
#define HWIO_GCC_USB_BOOT_CLOCK_CTL_OUT(v)      \
        out_dword(HWIO_GCC_USB_BOOT_CLOCK_CTL_ADDR,v)
#define HWIO_GCC_USB_BOOT_CLOCK_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB_BOOT_CLOCK_CTL_ADDR,m,v,HWIO_GCC_USB_BOOT_CLOCK_CTL_IN)
#define HWIO_GCC_USB_BOOT_CLOCK_CTL_CLK_ENABLE_BMSK                                                       0x1
#define HWIO_GCC_USB_BOOT_CLOCK_CTL_CLK_ENABLE_SHFT                                                       0x0

#define HWIO_GCC_VTT_EN_TIMER_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0007300c)
#define HWIO_GCC_VTT_EN_TIMER_RMSK                                                                    0xfffff
#define HWIO_GCC_VTT_EN_TIMER_IN          \
        in_dword(HWIO_GCC_VTT_EN_TIMER_ADDR)
#define HWIO_GCC_VTT_EN_TIMER_INM(m)      \
        in_dword_masked(HWIO_GCC_VTT_EN_TIMER_ADDR, m)
#define HWIO_GCC_VTT_EN_TIMER_OUT(v)      \
        out_dword(HWIO_GCC_VTT_EN_TIMER_ADDR,v)
#define HWIO_GCC_VTT_EN_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VTT_EN_TIMER_ADDR,m,v,HWIO_GCC_VTT_EN_TIMER_IN)
#define HWIO_GCC_VTT_EN_TIMER_PVC_LOAD_VALUE_BMSK                                                     0xfffff
#define HWIO_GCC_VTT_EN_TIMER_PVC_LOAD_VALUE_SHFT                                                         0x0

#define HWIO_GCC_VREF_EN_TIMER_ADDR                                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00073010)
#define HWIO_GCC_VREF_EN_TIMER_RMSK                                                                  0x3fffff
#define HWIO_GCC_VREF_EN_TIMER_IN          \
        in_dword(HWIO_GCC_VREF_EN_TIMER_ADDR)
#define HWIO_GCC_VREF_EN_TIMER_INM(m)      \
        in_dword_masked(HWIO_GCC_VREF_EN_TIMER_ADDR, m)
#define HWIO_GCC_VREF_EN_TIMER_OUT(v)      \
        out_dword(HWIO_GCC_VREF_EN_TIMER_ADDR,v)
#define HWIO_GCC_VREF_EN_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_VREF_EN_TIMER_ADDR,m,v,HWIO_GCC_VREF_EN_TIMER_IN)
#define HWIO_GCC_VREF_EN_TIMER_MAX_INDEX_BMSK                                                        0x300000
#define HWIO_GCC_VREF_EN_TIMER_MAX_INDEX_SHFT                                                            0x14
#define HWIO_GCC_VREF_EN_TIMER_PVC_LOAD_VALUE_BMSK                                                    0xfffff
#define HWIO_GCC_VREF_EN_TIMER_PVC_LOAD_VALUE_SHFT                                                        0x0

#define HWIO_GCC_PVC_DATA_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00073014)
#define HWIO_GCC_PVC_DATA_RMSK                                                                     0xffffffff
#define HWIO_GCC_PVC_DATA_IN          \
        in_dword(HWIO_GCC_PVC_DATA_ADDR)
#define HWIO_GCC_PVC_DATA_INM(m)      \
        in_dword_masked(HWIO_GCC_PVC_DATA_ADDR, m)
#define HWIO_GCC_PVC_DATA_OUT(v)      \
        out_dword(HWIO_GCC_PVC_DATA_ADDR,v)
#define HWIO_GCC_PVC_DATA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PVC_DATA_ADDR,m,v,HWIO_GCC_PVC_DATA_IN)
#define HWIO_GCC_PVC_DATA_DATA3_BMSK                                                               0xff000000
#define HWIO_GCC_PVC_DATA_DATA3_SHFT                                                                     0x18
#define HWIO_GCC_PVC_DATA_DATA2_BMSK                                                                 0xff0000
#define HWIO_GCC_PVC_DATA_DATA2_SHFT                                                                     0x10
#define HWIO_GCC_PVC_DATA_DATA1_BMSK                                                                   0xff00
#define HWIO_GCC_PVC_DATA_DATA1_SHFT                                                                      0x8
#define HWIO_GCC_PVC_DATA_DATA0_BMSK                                                                     0xff
#define HWIO_GCC_PVC_DATA_DATA0_SHFT                                                                      0x0

#define HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00078030)
#define HWIO_GCC_GDS_HW_CTRL_SPARE_RMSK                                                                  0xff
#define HWIO_GCC_GDS_HW_CTRL_SPARE_IN          \
        in_dword(HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR)
#define HWIO_GCC_GDS_HW_CTRL_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR, m)
#define HWIO_GCC_GDS_HW_CTRL_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR,v)
#define HWIO_GCC_GDS_HW_CTRL_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR,m,v,HWIO_GCC_GDS_HW_CTRL_SPARE_IN)
#define HWIO_GCC_GDS_HW_CTRL_SPARE_SPARE_BMSK                                                            0xff
#define HWIO_GCC_GDS_HW_CTRL_SPARE_SPARE_SHFT                                                             0x0

#define HWIO_GCC_WCSS_PD_CLK_DIS_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00011104)
#define HWIO_GCC_WCSS_PD_CLK_DIS_RMSK                                                                     0x1
#define HWIO_GCC_WCSS_PD_CLK_DIS_IN          \
        in_dword(HWIO_GCC_WCSS_PD_CLK_DIS_ADDR)
#define HWIO_GCC_WCSS_PD_CLK_DIS_INM(m)      \
        in_dword_masked(HWIO_GCC_WCSS_PD_CLK_DIS_ADDR, m)
#define HWIO_GCC_WCSS_PD_CLK_DIS_OUT(v)      \
        out_dword(HWIO_GCC_WCSS_PD_CLK_DIS_ADDR,v)
#define HWIO_GCC_WCSS_PD_CLK_DIS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_WCSS_PD_CLK_DIS_ADDR,m,v,HWIO_GCC_WCSS_PD_CLK_DIS_IN)
#define HWIO_GCC_WCSS_PD_CLK_DIS_SW_OVERRIDE_BMSK                                                         0x1
#define HWIO_GCC_WCSS_PD_CLK_DIS_SW_OVERRIDE_SHFT                                                         0x0

#define HWIO_GCC_SPARE0_REG_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0006d000)
#define HWIO_GCC_SPARE0_REG_RMSK                                                                   0xffffffff
#define HWIO_GCC_SPARE0_REG_IN          \
        in_dword(HWIO_GCC_SPARE0_REG_ADDR)
#define HWIO_GCC_SPARE0_REG_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE0_REG_ADDR, m)
#define HWIO_GCC_SPARE0_REG_OUT(v)      \
        out_dword(HWIO_GCC_SPARE0_REG_ADDR,v)
#define HWIO_GCC_SPARE0_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE0_REG_ADDR,m,v,HWIO_GCC_SPARE0_REG_IN)
#define HWIO_GCC_SPARE0_REG_SPARE_BITS_BMSK                                                        0xffffffff
#define HWIO_GCC_SPARE0_REG_SPARE_BITS_SHFT                                                               0x0

#define HWIO_GCC_SPARE1_REG_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0006e000)
#define HWIO_GCC_SPARE1_REG_RMSK                                                                   0xffffffff
#define HWIO_GCC_SPARE1_REG_IN          \
        in_dword(HWIO_GCC_SPARE1_REG_ADDR)
#define HWIO_GCC_SPARE1_REG_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE1_REG_ADDR, m)
#define HWIO_GCC_SPARE1_REG_OUT(v)      \
        out_dword(HWIO_GCC_SPARE1_REG_ADDR,v)
#define HWIO_GCC_SPARE1_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE1_REG_ADDR,m,v,HWIO_GCC_SPARE1_REG_IN)
#define HWIO_GCC_SPARE1_REG_SPARE_BITS_BMSK                                                        0xffffffff
#define HWIO_GCC_SPARE1_REG_SPARE_BITS_SHFT                                                               0x0

#define HWIO_GCC_SPARE2_REG_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00081000)
#define HWIO_GCC_SPARE2_REG_RMSK                                                                   0xffffffff
#define HWIO_GCC_SPARE2_REG_IN          \
        in_dword(HWIO_GCC_SPARE2_REG_ADDR)
#define HWIO_GCC_SPARE2_REG_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE2_REG_ADDR, m)
#define HWIO_GCC_SPARE2_REG_OUT(v)      \
        out_dword(HWIO_GCC_SPARE2_REG_ADDR,v)
#define HWIO_GCC_SPARE2_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE2_REG_ADDR,m,v,HWIO_GCC_SPARE2_REG_IN)
#define HWIO_GCC_SPARE2_REG_SPARE_BITS_BMSK                                                        0xffffffff
#define HWIO_GCC_SPARE2_REG_SPARE_BITS_SHFT                                                               0x0

#define HWIO_GCC_SPARE3_REG_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00042000)
#define HWIO_GCC_SPARE3_REG_RMSK                                                                   0xffffffff
#define HWIO_GCC_SPARE3_REG_IN          \
        in_dword(HWIO_GCC_SPARE3_REG_ADDR)
#define HWIO_GCC_SPARE3_REG_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE3_REG_ADDR, m)
#define HWIO_GCC_SPARE3_REG_OUT(v)      \
        out_dword(HWIO_GCC_SPARE3_REG_ADDR,v)
#define HWIO_GCC_SPARE3_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE3_REG_ADDR,m,v,HWIO_GCC_SPARE3_REG_IN)
#define HWIO_GCC_SPARE3_REG_SPARE_BITS_BMSK                                                        0xffffffff
#define HWIO_GCC_SPARE3_REG_SPARE_BITS_SHFT                                                               0x0

#define HWIO_GCC_SPARE4_REG_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00039000)
#define HWIO_GCC_SPARE4_REG_RMSK                                                                   0xffffffff
#define HWIO_GCC_SPARE4_REG_IN          \
        in_dword(HWIO_GCC_SPARE4_REG_ADDR)
#define HWIO_GCC_SPARE4_REG_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE4_REG_ADDR, m)
#define HWIO_GCC_SPARE4_REG_OUT(v)      \
        out_dword(HWIO_GCC_SPARE4_REG_ADDR,v)
#define HWIO_GCC_SPARE4_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE4_REG_ADDR,m,v,HWIO_GCC_SPARE4_REG_IN)
#define HWIO_GCC_SPARE4_REG_SPARE_BITS_BMSK                                                        0xffffffff
#define HWIO_GCC_SPARE4_REG_SPARE_BITS_SHFT                                                               0x0

#define HWIO_GCC_SPARE5_REG_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00032000)
#define HWIO_GCC_SPARE5_REG_RMSK                                                                   0xffffffff
#define HWIO_GCC_SPARE5_REG_IN          \
        in_dword(HWIO_GCC_SPARE5_REG_ADDR)
#define HWIO_GCC_SPARE5_REG_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE5_REG_ADDR, m)
#define HWIO_GCC_SPARE5_REG_OUT(v)      \
        out_dword(HWIO_GCC_SPARE5_REG_ADDR,v)
#define HWIO_GCC_SPARE5_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE5_REG_ADDR,m,v,HWIO_GCC_SPARE5_REG_IN)
#define HWIO_GCC_SPARE5_REG_SPARE_BITS_BMSK                                                        0xffffffff
#define HWIO_GCC_SPARE5_REG_SPARE_BITS_SHFT                                                               0x0

#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0007f000)
#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_RMSK                                                                  0x1
#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_IN          \
        in_dword(HWIO_GCC_RAW_SLEEP_CLK_CTRL_ADDR)
#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_INM(m)      \
        in_dword_masked(HWIO_GCC_RAW_SLEEP_CLK_CTRL_ADDR, m)
#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_OUT(v)      \
        out_dword(HWIO_GCC_RAW_SLEEP_CLK_CTRL_ADDR,v)
#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RAW_SLEEP_CLK_CTRL_ADDR,m,v,HWIO_GCC_RAW_SLEEP_CLK_CTRL_IN)
#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_GATING_DISABLE_BMSK                                                   0x1
#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_GATING_DISABLE_SHFT                                                   0x0

#define HWIO_GCC_TSIF_0_RESET_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00036024)
#define HWIO_GCC_TSIF_0_RESET_RMSK                                                                        0x1
#define HWIO_GCC_TSIF_0_RESET_IN          \
        in_dword(HWIO_GCC_TSIF_0_RESET_ADDR)
#define HWIO_GCC_TSIF_0_RESET_INM(m)      \
        in_dword_masked(HWIO_GCC_TSIF_0_RESET_ADDR, m)
#define HWIO_GCC_TSIF_0_RESET_OUT(v)      \
        out_dword(HWIO_GCC_TSIF_0_RESET_ADDR,v)
#define HWIO_GCC_TSIF_0_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TSIF_0_RESET_ADDR,m,v,HWIO_GCC_TSIF_0_RESET_IN)
#define HWIO_GCC_TSIF_0_RESET_RESET_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_TSIF_0_RESET_RESET_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_TSIF_1_RESET_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00036028)
#define HWIO_GCC_TSIF_1_RESET_RMSK                                                                        0x1
#define HWIO_GCC_TSIF_1_RESET_IN          \
        in_dword(HWIO_GCC_TSIF_1_RESET_ADDR)
#define HWIO_GCC_TSIF_1_RESET_INM(m)      \
        in_dword_masked(HWIO_GCC_TSIF_1_RESET_ADDR, m)
#define HWIO_GCC_TSIF_1_RESET_OUT(v)      \
        out_dword(HWIO_GCC_TSIF_1_RESET_ADDR,v)
#define HWIO_GCC_TSIF_1_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TSIF_1_RESET_ADDR,m,v,HWIO_GCC_TSIF_1_RESET_IN)
#define HWIO_GCC_TSIF_1_RESET_RESET_ENABLE_BMSK                                                           0x1
#define HWIO_GCC_TSIF_1_RESET_RESET_ENABLE_SHFT                                                           0x0

#define HWIO_GCC_NPU_MISC_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0004d110)
#define HWIO_GCC_NPU_MISC_RMSK                                                                            0x3
#define HWIO_GCC_NPU_MISC_IN          \
        in_dword(HWIO_GCC_NPU_MISC_ADDR)
#define HWIO_GCC_NPU_MISC_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_MISC_ADDR, m)
#define HWIO_GCC_NPU_MISC_OUT(v)      \
        out_dword(HWIO_GCC_NPU_MISC_ADDR,v)
#define HWIO_GCC_NPU_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_MISC_ADDR,m,v,HWIO_GCC_NPU_MISC_IN)
#define HWIO_GCC_NPU_MISC_GPLL0_SRC_DISABLE_BMSK                                                          0x2
#define HWIO_GCC_NPU_MISC_GPLL0_SRC_DISABLE_SHFT                                                          0x1
#define HWIO_GCC_NPU_MISC_GPLL0_DIV_SRC_DISABLE_BMSK                                                      0x1
#define HWIO_GCC_NPU_MISC_GPLL0_DIV_SRC_DISABLE_SHFT                                                      0x0

#define HWIO_GCC_GPU_MISC_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00071028)
#define HWIO_GCC_GPU_MISC_RMSK                                                                            0x3
#define HWIO_GCC_GPU_MISC_IN          \
        in_dword(HWIO_GCC_GPU_MISC_ADDR)
#define HWIO_GCC_GPU_MISC_INM(m)      \
        in_dword_masked(HWIO_GCC_GPU_MISC_ADDR, m)
#define HWIO_GCC_GPU_MISC_OUT(v)      \
        out_dword(HWIO_GCC_GPU_MISC_ADDR,v)
#define HWIO_GCC_GPU_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPU_MISC_ADDR,m,v,HWIO_GCC_GPU_MISC_IN)
#define HWIO_GCC_GPU_MISC_GPLL0_SRC_DISABLE_BMSK                                                          0x2
#define HWIO_GCC_GPU_MISC_GPLL0_SRC_DISABLE_SHFT                                                          0x1
#define HWIO_GCC_GPU_MISC_GPLL0_DIV_SRC_DISABLE_BMSK                                                      0x1
#define HWIO_GCC_GPU_MISC_GPLL0_DIV_SRC_DISABLE_SHFT                                                      0x0

#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b000)
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_RMSK                                                         0x80000001
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_ADDR)
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_ADDR, m)
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_ADDR,v)
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_IN)
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_CLK_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b004)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_RMSK                                          0x80000001
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR, m)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR,v)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_IN)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_OFF_BMSK                                  0x80000000
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_OFF_SHFT                                        0x1f
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_ENABLE_BMSK                                      0x1
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_ENABLE_SHFT                                      0x0

#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b008)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK                                               0x80000001
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, m)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,v)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b00c)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK                                               0x80000001
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, m)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,v)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b010)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_RMSK                                           0x80000001
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR, m)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR,v)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_IN)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_OFF_BMSK                                   0x80000000
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_OFF_SHFT                                         0x1f
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_ENABLE_BMSK                                       0x1
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_ENABLE_SHFT                                       0x0

#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b014)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_CLK_RMSK                                                0x80000001
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_CLK_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR, m)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR,v)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_CLK_IN)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_OFF_BMSK                                        0x80000000
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_OFF_SHFT                                              0x1f
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_ENABLE_BMSK                                            0x1
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_ENABLE_SHFT                                            0x0

#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b018)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_RMSK                                                0x80000001
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR, m)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR,v)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_IN)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_OFF_BMSK                                        0x80000000
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_OFF_SHFT                                              0x1f
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_ENABLE_BMSK                                            0x1
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_ENABLE_SHFT                                            0x0

#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b01c)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_RMSK                                                0x80000001
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR, m)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR,v)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_IN)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_OFF_BMSK                                        0x80000000
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_OFF_SHFT                                              0x1f
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_ENABLE_BMSK                                            0x1
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_ENABLE_SHFT                                            0x0

#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b020)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_RMSK                                                  0x80000001
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_ADDR)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_ADDR, m)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_ADDR,v)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_IN)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_CLK_OFF_BMSK                                          0x80000000
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_CLK_OFF_SHFT                                                0x1f
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_CLK_ENABLE_BMSK                                              0x1
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_CLK_ENABLE_SHFT                                              0x0

#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b024)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_RMSK                                                  0x80000001
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_ADDR)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_ADDR, m)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_ADDR,v)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_IN)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_CLK_OFF_BMSK                                          0x80000000
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_CLK_OFF_SHFT                                                0x1f
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_CLK_ENABLE_BMSK                                              0x1
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_CLK_ENABLE_SHFT                                              0x0

#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b028)
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_RMSK                                                     0x80000001
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR)
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR, m)
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR,v)
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_IN)
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b02c)
#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_RMSK                                                          0x80000001
#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR)
#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR, m)
#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR,v)
#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_IN)
#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b030)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_CLK_RMSK                                                0x80000001
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_CLK_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR, m)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR,v)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_CLK_IN)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_OFF_BMSK                                        0x80000000
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_OFF_SHFT                                              0x1f
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_ENABLE_BMSK                                            0x1
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_ENABLE_SHFT                                            0x0

#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b03c)
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_RMSK                                                         0x80000001
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_ADDR)
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_ADDR, m)
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_ADDR,v)
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_IN)
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_PWR_ON_BMSK                                                  0x80000000
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_PWR_ON_SHFT                                                        0x1f
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_BMSK                                                    0x1
#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_SHFT                                                    0x0

#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b040)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_RMSK                                          0x80000001
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR, m)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR,v)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_IN)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PWR_ON_BMSK                                   0x80000000
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PWR_ON_SHFT                                         0x1f
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_SW_COLLAPSE_BMSK                                     0x1
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_SW_COLLAPSE_SHFT                                     0x0

#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b044)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_RMSK                                               0x80000001
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR, m)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR,v)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_IN)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PWR_ON_BMSK                                        0x80000000
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PWR_ON_SHFT                                              0x1f
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_SW_COLLAPSE_BMSK                                          0x1
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_SW_COLLAPSE_SHFT                                          0x0

#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b048)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_RMSK                                               0x80000001
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR, m)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR,v)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_IN)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PWR_ON_BMSK                                        0x80000000
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PWR_ON_SHFT                                              0x1f
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_SW_COLLAPSE_BMSK                                          0x1
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_SW_COLLAPSE_SHFT                                          0x0

#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b04c)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_RMSK                                           0x80000001
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR, m)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR,v)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_IN)
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PWR_ON_BMSK                                    0x80000000
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PWR_ON_SHFT                                          0x1f
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_SW_COLLAPSE_BMSK                                      0x1
#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_SW_COLLAPSE_SHFT                                      0x0

#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b050)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_RMSK                                                0x80000001
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR, m)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR,v)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_IN)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_PWR_ON_BMSK                                         0x80000000
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_PWR_ON_SHFT                                               0x1f
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_SW_COLLAPSE_BMSK                                           0x1
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_SW_COLLAPSE_SHFT                                           0x0

#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b054)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_GDS_RMSK                                                0x80000001
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_GDS_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR, m)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR,v)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_GDS_IN)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_GDS_PWR_ON_BMSK                                         0x80000000
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_GDS_PWR_ON_SHFT                                               0x1f
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_GDS_SW_COLLAPSE_BMSK                                           0x1
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF0_GDS_SW_COLLAPSE_SHFT                                           0x0

#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b058)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_RMSK                                                0x80000001
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR, m)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR,v)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_IN)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_PWR_ON_BMSK                                         0x80000000
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_PWR_ON_SHFT                                               0x1f
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_SW_COLLAPSE_BMSK                                           0x1
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_SW_COLLAPSE_SHFT                                           0x0

#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b05c)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_RMSK                                                  0x80000001
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_ADDR)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_ADDR, m)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_ADDR,v)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_IN)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_PWR_ON_BMSK                                           0x80000000
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_PWR_ON_SHFT                                                 0x1f
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_SW_COLLAPSE_BMSK                                             0x1
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_SW_COLLAPSE_SHFT                                             0x0

#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b060)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_RMSK                                                  0x80000001
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_ADDR)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_ADDR, m)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_ADDR,v)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_IN)
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_PWR_ON_BMSK                                           0x80000000
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_PWR_ON_SHFT                                                 0x1f
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_SW_COLLAPSE_BMSK                                             0x1
#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_SW_COLLAPSE_SHFT                                             0x0

#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b064)
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_RMSK                                                     0x80000001
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_ADDR)
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_ADDR, m)
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_ADDR,v)
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_IN)
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_BMSK                                              0x80000000
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_SHFT                                                    0x1f
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_BMSK                                                0x1
#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_SHFT                                                0x0

#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b068)
#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_RMSK                                                          0x80000001
#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_ADDR)
#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_ADDR, m)
#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_ADDR,v)
#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_IN)
#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_PWR_ON_BMSK                                                   0x80000000
#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_PWR_ON_SHFT                                                         0x1f
#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_SW_COLLAPSE_BMSK                                                     0x1
#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_SW_COLLAPSE_SHFT                                                     0x0

#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0007b06c)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_GDS_RMSK                                                0x80000001
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_GDS_IN          \
        in_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR, m)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR,v)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR,m,v,HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_GDS_IN)
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_GDS_PWR_ON_BMSK                                         0x80000000
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_GDS_PWR_ON_SHFT                                               0x1f
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_GDS_SW_COLLAPSE_BMSK                                           0x1
#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF1_GDS_SW_COLLAPSE_SHFT                                           0x0

#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c000)
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_RMSK                                                        0x80000001
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_ADDR)
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_ADDR, m)
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_ADDR,v)
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_IN)
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c004)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_RMSK                                         0x80000001
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR, m)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR,v)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_IN)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_OFF_BMSK                                 0x80000000
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_OFF_SHFT                                       0x1f
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_ENABLE_BMSK                                     0x1
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_ENABLE_SHFT                                     0x0

#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c008)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK                                              0x80000001
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, m)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,v)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_BMSK                                      0x80000000
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_SHFT                                            0x1f
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_BMSK                                          0x1
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_SHFT                                          0x0

#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c00c)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK                                              0x80000001
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, m)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,v)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_BMSK                                      0x80000000
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_SHFT                                            0x1f
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_BMSK                                          0x1
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_SHFT                                          0x0

#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c010)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_RMSK                                          0x80000001
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR, m)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR,v)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_IN)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_OFF_BMSK                                  0x80000000
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_OFF_SHFT                                        0x1f
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_ENABLE_BMSK                                      0x1
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_ENABLE_SHFT                                      0x0

#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c014)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_CLK_RMSK                                               0x80000001
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_CLK_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR, m)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR,v)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_CLK_IN)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c018)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_RMSK                                               0x80000001
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR, m)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR,v)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_IN)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c01c)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_RMSK                                               0x80000001
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR, m)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR,v)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_IN)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c020)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_RMSK                                                 0x80000001
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_ADDR)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_ADDR, m)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_ADDR,v)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_IN)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_CLK_OFF_BMSK                                         0x80000000
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_CLK_OFF_SHFT                                               0x1f
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_CLK_ENABLE_BMSK                                             0x1
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_CLK_ENABLE_SHFT                                             0x0

#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c024)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_RMSK                                                 0x80000001
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_ADDR)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_ADDR, m)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_ADDR,v)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_IN)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_CLK_OFF_BMSK                                         0x80000000
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_CLK_OFF_SHFT                                               0x1f
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_CLK_ENABLE_BMSK                                             0x1
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_CLK_ENABLE_SHFT                                             0x0

#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c028)
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_RMSK                                                    0x80000001
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR)
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR, m)
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR,v)
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_IN)
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c02c)
#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_RMSK                                                         0x80000001
#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR)
#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR, m)
#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR,v)
#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_IN)
#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c030)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_CLK_RMSK                                               0x80000001
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_CLK_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR, m)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR,v)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_CLK_IN)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c03c)
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_RMSK                                                        0x80000001
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_ADDR)
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_ADDR, m)
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_ADDR,v)
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_IN)
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_PWR_ON_BMSK                                                 0x80000000
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_PWR_ON_SHFT                                                       0x1f
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_BMSK                                                   0x1
#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_SHFT                                                   0x0

#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c040)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_RMSK                                         0x80000001
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR, m)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR,v)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_IN)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PWR_ON_BMSK                                  0x80000000
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PWR_ON_SHFT                                        0x1f
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_SW_COLLAPSE_BMSK                                    0x1
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_SW_COLLAPSE_SHFT                                    0x0

#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c044)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_RMSK                                              0x80000001
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR, m)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR,v)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_IN)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PWR_ON_BMSK                                       0x80000000
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PWR_ON_SHFT                                             0x1f
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_SW_COLLAPSE_BMSK                                         0x1
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_SW_COLLAPSE_SHFT                                         0x0

#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c048)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_RMSK                                              0x80000001
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR, m)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR,v)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_IN)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PWR_ON_BMSK                                       0x80000000
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PWR_ON_SHFT                                             0x1f
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_SW_COLLAPSE_BMSK                                         0x1
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_SW_COLLAPSE_SHFT                                         0x0

#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c04c)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_RMSK                                          0x80000001
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR, m)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR,v)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_IN)
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PWR_ON_BMSK                                   0x80000000
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PWR_ON_SHFT                                         0x1f
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_SW_COLLAPSE_BMSK                                     0x1
#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_SW_COLLAPSE_SHFT                                     0x0

#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c050)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_RMSK                                               0x80000001
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR, m)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR,v)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_IN)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_PWR_ON_BMSK                                        0x80000000
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_PWR_ON_SHFT                                              0x1f
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_SW_COLLAPSE_BMSK                                          0x1
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_SW_COLLAPSE_SHFT                                          0x0

#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c054)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_GDS_RMSK                                               0x80000001
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_GDS_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR, m)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR,v)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_GDS_IN)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_GDS_PWR_ON_BMSK                                        0x80000000
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_GDS_PWR_ON_SHFT                                              0x1f
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_GDS_SW_COLLAPSE_BMSK                                          0x1
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF0_GDS_SW_COLLAPSE_SHFT                                          0x0

#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c058)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_RMSK                                               0x80000001
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR, m)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR,v)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_IN)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_PWR_ON_BMSK                                        0x80000000
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_PWR_ON_SHFT                                              0x1f
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_SW_COLLAPSE_BMSK                                          0x1
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_SW_COLLAPSE_SHFT                                          0x0

#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c05c)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_RMSK                                                 0x80000001
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_ADDR)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_ADDR, m)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_ADDR,v)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_IN)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_PWR_ON_BMSK                                          0x80000000
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_PWR_ON_SHFT                                                0x1f
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_SW_COLLAPSE_BMSK                                            0x1
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_SW_COLLAPSE_SHFT                                            0x0

#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c060)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_RMSK                                                 0x80000001
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_ADDR)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_ADDR, m)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_ADDR,v)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_IN)
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_PWR_ON_BMSK                                          0x80000000
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_PWR_ON_SHFT                                                0x1f
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_SW_COLLAPSE_BMSK                                            0x1
#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_SW_COLLAPSE_SHFT                                            0x0

#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c064)
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_RMSK                                                    0x80000001
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_ADDR)
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_ADDR, m)
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_ADDR,v)
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_IN)
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_BMSK                                             0x80000000
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_SHFT                                                   0x1f
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_BMSK                                               0x1
#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_SHFT                                               0x0

#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c068)
#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_RMSK                                                         0x80000001
#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_ADDR)
#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_ADDR, m)
#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_ADDR,v)
#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_IN)
#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_PWR_ON_BMSK                                                  0x80000000
#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_PWR_ON_SHFT                                                        0x1f
#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_BMSK                                                    0x1
#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_SHFT                                                    0x0

#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007c06c)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_GDS_RMSK                                               0x80000001
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_GDS_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR, m)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR,v)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR,m,v,HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_GDS_IN)
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_GDS_PWR_ON_BMSK                                        0x80000000
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_GDS_PWR_ON_SHFT                                              0x1f
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_GDS_SW_COLLAPSE_BMSK                                          0x1
#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF1_GDS_SW_COLLAPSE_SHFT                                          0x0

#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d000)
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_RMSK                                                      0x80000001
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_ADDR)
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_IN)
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_CLK_ENABLE_SHFT                                                  0x0

#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d004)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_RMSK                                       0x80000001
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_IN)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_OFF_BMSK                               0x80000000
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_OFF_SHFT                                     0x1f
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_ENABLE_BMSK                                   0x1
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_ENABLE_SHFT                                   0x0

#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d008)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK                                            0x80000001
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_BMSK                                    0x80000000
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_SHFT                                          0x1f
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_BMSK                                        0x1
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_SHFT                                        0x0

#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d00c)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK                                            0x80000001
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_BMSK                                    0x80000000
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_SHFT                                          0x1f
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_BMSK                                        0x1
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_SHFT                                        0x0

#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d010)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_RMSK                                        0x80000001
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_IN)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_OFF_BMSK                                0x80000000
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_OFF_SHFT                                      0x1f
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_ENABLE_BMSK                                    0x1
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_ENABLE_SHFT                                    0x0

#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d014)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK_RMSK                                             0x80000001
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK_IN)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_OFF_BMSK                                     0x80000000
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_OFF_SHFT                                           0x1f
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_ENABLE_BMSK                                         0x1
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_ENABLE_SHFT                                         0x0

#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d018)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_RMSK                                             0x80000001
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_IN)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_OFF_BMSK                                     0x80000000
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_OFF_SHFT                                           0x1f
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_ENABLE_BMSK                                         0x1
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_ENABLE_SHFT                                         0x0

#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d01c)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_RMSK                                             0x80000001
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_IN)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_OFF_BMSK                                     0x80000000
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_OFF_SHFT                                           0x1f
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_ENABLE_BMSK                                         0x1
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_ENABLE_SHFT                                         0x0

#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d020)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_RMSK                                               0x80000001
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_ADDR)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_IN)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d024)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_RMSK                                               0x80000001
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_ADDR)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_IN)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d028)
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_RMSK                                                  0x80000001
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR)
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_IN)
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK                                          0x80000000
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT                                                0x1f
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK                                              0x1
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT                                              0x0

#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d02c)
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_RMSK                                                       0x80000001
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR)
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_IN)
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d030)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_CLK_RMSK                                             0x80000001
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_CLK_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_CLK_IN)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_OFF_BMSK                                     0x80000000
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_OFF_SHFT                                           0x1f
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_ENABLE_BMSK                                         0x1
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_ENABLE_SHFT                                         0x0

#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d03c)
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_RMSK                                                      0x80000001
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_ADDR)
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_IN)
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_PWR_ON_BMSK                                               0x80000000
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_PWR_ON_SHFT                                                     0x1f
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_BMSK                                                 0x1
#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_SHFT                                                 0x0

#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d040)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_RMSK                                       0x80000001
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_IN)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PWR_ON_BMSK                                0x80000000
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PWR_ON_SHFT                                      0x1f
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_SW_COLLAPSE_BMSK                                  0x1
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_SW_COLLAPSE_SHFT                                  0x0

#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d044)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_RMSK                                            0x80000001
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_IN)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PWR_ON_BMSK                                     0x80000000
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PWR_ON_SHFT                                           0x1f
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_SW_COLLAPSE_BMSK                                       0x1
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_SW_COLLAPSE_SHFT                                       0x0

#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d048)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_RMSK                                            0x80000001
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_IN)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PWR_ON_BMSK                                     0x80000000
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PWR_ON_SHFT                                           0x1f
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_SW_COLLAPSE_BMSK                                       0x1
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_SW_COLLAPSE_SHFT                                       0x0

#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d04c)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_RMSK                                        0x80000001
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_IN)
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PWR_ON_BMSK                                 0x80000000
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PWR_ON_SHFT                                       0x1f
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_SW_COLLAPSE_BMSK                                   0x1
#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_SW_COLLAPSE_SHFT                                   0x0

#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d050)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_RMSK                                             0x80000001
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_IN)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_PWR_ON_BMSK                                      0x80000000
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_PWR_ON_SHFT                                            0x1f
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_SW_COLLAPSE_BMSK                                        0x1
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_SW_COLLAPSE_SHFT                                        0x0

#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d054)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDS_RMSK                                             0x80000001
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDS_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDS_IN)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDS_PWR_ON_BMSK                                      0x80000000
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDS_PWR_ON_SHFT                                            0x1f
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDS_SW_COLLAPSE_BMSK                                        0x1
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDS_SW_COLLAPSE_SHFT                                        0x0

#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d058)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_RMSK                                             0x80000001
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_IN)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_PWR_ON_BMSK                                      0x80000000
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_PWR_ON_SHFT                                            0x1f
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_SW_COLLAPSE_BMSK                                        0x1
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_SW_COLLAPSE_SHFT                                        0x0

#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d05c)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_RMSK                                               0x80000001
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_ADDR)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_IN)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_PWR_ON_BMSK                                        0x80000000
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_PWR_ON_SHFT                                              0x1f
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_SW_COLLAPSE_BMSK                                          0x1
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_SW_COLLAPSE_SHFT                                          0x0

#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d060)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_RMSK                                               0x80000001
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_ADDR)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_IN)
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_PWR_ON_BMSK                                        0x80000000
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_PWR_ON_SHFT                                              0x1f
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_SW_COLLAPSE_BMSK                                          0x1
#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_SW_COLLAPSE_SHFT                                          0x0

#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d064)
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_RMSK                                                  0x80000001
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_ADDR)
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_IN)
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_BMSK                                           0x80000000
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_SHFT                                                 0x1f
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_BMSK                                             0x1
#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_SHFT                                             0x0

#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d068)
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_RMSK                                                       0x80000001
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_ADDR)
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_IN)
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_PWR_ON_BMSK                                                0x80000000
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_PWR_ON_SHFT                                                      0x1f
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_SW_COLLAPSE_BMSK                                                  0x1
#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_SW_COLLAPSE_SHFT                                                  0x0

#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007d06c)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDS_RMSK                                             0x80000001
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDS_IN          \
        in_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR, m)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR,v)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR,m,v,HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDS_IN)
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDS_PWR_ON_BMSK                                      0x80000000
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDS_PWR_ON_SHFT                                            0x1f
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDS_SW_COLLAPSE_BMSK                                        0x1
#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDS_SW_COLLAPSE_SHFT                                        0x0

#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e000)
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_RMSK                                                      0x80000001
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_ADDR)
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_IN)
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_CLK_OFF_BMSK                                              0x80000000
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_CLK_OFF_SHFT                                                    0x1f
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_CLK_ENABLE_SHFT                                                  0x0

#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e004)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_RMSK                                       0x80000001
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_IN)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_OFF_BMSK                               0x80000000
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_OFF_SHFT                                     0x1f
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_ENABLE_BMSK                                   0x1
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_ENABLE_SHFT                                   0x0

#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e008)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK                                            0x80000001
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_BMSK                                    0x80000000
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_SHFT                                          0x1f
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_BMSK                                        0x1
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_SHFT                                        0x0

#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e00c)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK                                            0x80000001
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_BMSK                                    0x80000000
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_SHFT                                          0x1f
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_BMSK                                        0x1
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_SHFT                                        0x0

#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e010)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_RMSK                                        0x80000001
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_IN)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_OFF_BMSK                                0x80000000
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_OFF_SHFT                                      0x1f
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_ENABLE_BMSK                                    0x1
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_ENABLE_SHFT                                    0x0

#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e014)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_CLK_RMSK                                             0x80000001
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_CLK_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_CLK_IN)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_OFF_BMSK                                     0x80000000
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_OFF_SHFT                                           0x1f
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_ENABLE_BMSK                                         0x1
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_ENABLE_SHFT                                         0x0

#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e018)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_RMSK                                             0x80000001
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_IN)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_OFF_BMSK                                     0x80000000
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_OFF_SHFT                                           0x1f
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_ENABLE_BMSK                                         0x1
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_ENABLE_SHFT                                         0x0

#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e01c)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_RMSK                                             0x80000001
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_IN)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_OFF_BMSK                                     0x80000000
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_OFF_SHFT                                           0x1f
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_ENABLE_BMSK                                         0x1
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_ENABLE_SHFT                                         0x0

#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e020)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_RMSK                                               0x80000001
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_ADDR)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_IN)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e024)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_RMSK                                               0x80000001
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_ADDR)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_IN)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e028)
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_RMSK                                                  0x80000001
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR)
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_IN)
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK                                          0x80000000
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT                                                0x1f
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK                                              0x1
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT                                              0x0

#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e02c)
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_RMSK                                                       0x80000001
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR)
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_IN)
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e030)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_CLK_RMSK                                             0x80000001
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_CLK_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_CLK_IN)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_OFF_BMSK                                     0x80000000
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_OFF_SHFT                                           0x1f
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_ENABLE_BMSK                                         0x1
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_ENABLE_SHFT                                         0x0

#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e03c)
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_RMSK                                                      0x80000001
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_ADDR)
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_IN)
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_PWR_ON_BMSK                                               0x80000000
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_PWR_ON_SHFT                                                     0x1f
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_BMSK                                                 0x1
#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_SHFT                                                 0x0

#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e040)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_RMSK                                       0x80000001
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_IN)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PWR_ON_BMSK                                0x80000000
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PWR_ON_SHFT                                      0x1f
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_SW_COLLAPSE_BMSK                                  0x1
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_SW_COLLAPSE_SHFT                                  0x0

#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e044)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_RMSK                                            0x80000001
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_IN)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PWR_ON_BMSK                                     0x80000000
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PWR_ON_SHFT                                           0x1f
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_SW_COLLAPSE_BMSK                                       0x1
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_SW_COLLAPSE_SHFT                                       0x0

#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e048)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_RMSK                                            0x80000001
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_IN)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PWR_ON_BMSK                                     0x80000000
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PWR_ON_SHFT                                           0x1f
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_SW_COLLAPSE_BMSK                                       0x1
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_SW_COLLAPSE_SHFT                                       0x0

#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e04c)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_RMSK                                        0x80000001
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_IN)
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PWR_ON_BMSK                                 0x80000000
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PWR_ON_SHFT                                       0x1f
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_SW_COLLAPSE_BMSK                                   0x1
#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_SW_COLLAPSE_SHFT                                   0x0

#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e050)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_RMSK                                             0x80000001
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_IN)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_PWR_ON_BMSK                                      0x80000000
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_PWR_ON_SHFT                                            0x1f
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_SW_COLLAPSE_BMSK                                        0x1
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_SW_COLLAPSE_SHFT                                        0x0

#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e054)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_GDS_RMSK                                             0x80000001
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_GDS_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_GDS_IN)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_GDS_PWR_ON_BMSK                                      0x80000000
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_GDS_PWR_ON_SHFT                                            0x1f
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_GDS_SW_COLLAPSE_BMSK                                        0x1
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF0_GDS_SW_COLLAPSE_SHFT                                        0x0

#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e058)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_RMSK                                             0x80000001
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_IN)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_PWR_ON_BMSK                                      0x80000000
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_PWR_ON_SHFT                                            0x1f
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_SW_COLLAPSE_BMSK                                        0x1
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_SW_COLLAPSE_SHFT                                        0x0

#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e05c)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_RMSK                                               0x80000001
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_ADDR)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_IN)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_PWR_ON_BMSK                                        0x80000000
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_PWR_ON_SHFT                                              0x1f
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_SW_COLLAPSE_BMSK                                          0x1
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_SW_COLLAPSE_SHFT                                          0x0

#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e060)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_RMSK                                               0x80000001
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_ADDR)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_IN)
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_PWR_ON_BMSK                                        0x80000000
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_PWR_ON_SHFT                                              0x1f
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_SW_COLLAPSE_BMSK                                          0x1
#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_SW_COLLAPSE_SHFT                                          0x0

#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e064)
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_RMSK                                                  0x80000001
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_ADDR)
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_IN)
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_BMSK                                           0x80000000
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_SHFT                                                 0x1f
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_BMSK                                             0x1
#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_SHFT                                             0x0

#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e068)
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_RMSK                                                       0x80000001
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_ADDR)
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_IN)
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_PWR_ON_BMSK                                                0x80000000
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_PWR_ON_SHFT                                                      0x1f
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_SW_COLLAPSE_BMSK                                                  0x1
#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_SW_COLLAPSE_SHFT                                                  0x0

#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0007e06c)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_GDS_RMSK                                             0x80000001
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_GDS_IN          \
        in_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR, m)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR,v)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR,m,v,HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_GDS_IN)
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_GDS_PWR_ON_BMSK                                      0x80000000
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_GDS_PWR_ON_SHFT                                            0x1f
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_GDS_SW_COLLAPSE_BMSK                                        0x1
#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF1_GDS_SW_COLLAPSE_SHFT                                        0x0

#define HWIO_GCC_UFS_1X_CLKREF_EN_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0008c000)
#define HWIO_GCC_UFS_1X_CLKREF_EN_RMSK                                                             0x80000001
#define HWIO_GCC_UFS_1X_CLKREF_EN_IN          \
        in_dword(HWIO_GCC_UFS_1X_CLKREF_EN_ADDR)
#define HWIO_GCC_UFS_1X_CLKREF_EN_INM(m)      \
        in_dword_masked(HWIO_GCC_UFS_1X_CLKREF_EN_ADDR, m)
#define HWIO_GCC_UFS_1X_CLKREF_EN_OUT(v)      \
        out_dword(HWIO_GCC_UFS_1X_CLKREF_EN_ADDR,v)
#define HWIO_GCC_UFS_1X_CLKREF_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_UFS_1X_CLKREF_EN_ADDR,m,v,HWIO_GCC_UFS_1X_CLKREF_EN_IN)
#define HWIO_GCC_UFS_1X_CLKREF_EN_UFS_STATUS_BMSK                                                  0x80000000
#define HWIO_GCC_UFS_1X_CLKREF_EN_UFS_STATUS_SHFT                                                        0x1f
#define HWIO_GCC_UFS_1X_CLKREF_EN_UFS_ENABLE_BMSK                                                         0x1
#define HWIO_GCC_UFS_1X_CLKREF_EN_UFS_ENABLE_SHFT                                                         0x0

#define HWIO_GCC_PCIE_WIFI_CLKREF_EN_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0008c004)
#define HWIO_GCC_PCIE_WIFI_CLKREF_EN_RMSK                                                          0x80000001
#define HWIO_GCC_PCIE_WIFI_CLKREF_EN_IN          \
        in_dword(HWIO_GCC_PCIE_WIFI_CLKREF_EN_ADDR)
#define HWIO_GCC_PCIE_WIFI_CLKREF_EN_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_WIFI_CLKREF_EN_ADDR, m)
#define HWIO_GCC_PCIE_WIFI_CLKREF_EN_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_WIFI_CLKREF_EN_ADDR,v)
#define HWIO_GCC_PCIE_WIFI_CLKREF_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_WIFI_CLKREF_EN_ADDR,m,v,HWIO_GCC_PCIE_WIFI_CLKREF_EN_IN)
#define HWIO_GCC_PCIE_WIFI_CLKREF_EN_PCIE_STATUS_BMSK                                              0x80000000
#define HWIO_GCC_PCIE_WIFI_CLKREF_EN_PCIE_STATUS_SHFT                                                    0x1f
#define HWIO_GCC_PCIE_WIFI_CLKREF_EN_PCIE_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_PCIE_WIFI_CLKREF_EN_PCIE_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_PCIE_WIGIG_CLKREF_EN_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0008c008)
#define HWIO_GCC_PCIE_WIGIG_CLKREF_EN_RMSK                                                         0x80000001
#define HWIO_GCC_PCIE_WIGIG_CLKREF_EN_IN          \
        in_dword(HWIO_GCC_PCIE_WIGIG_CLKREF_EN_ADDR)
#define HWIO_GCC_PCIE_WIGIG_CLKREF_EN_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_WIGIG_CLKREF_EN_ADDR, m)
#define HWIO_GCC_PCIE_WIGIG_CLKREF_EN_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_WIGIG_CLKREF_EN_ADDR,v)
#define HWIO_GCC_PCIE_WIGIG_CLKREF_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_WIGIG_CLKREF_EN_ADDR,m,v,HWIO_GCC_PCIE_WIGIG_CLKREF_EN_IN)
#define HWIO_GCC_PCIE_WIGIG_CLKREF_EN_PCIE_STATUS_BMSK                                             0x80000000
#define HWIO_GCC_PCIE_WIGIG_CLKREF_EN_PCIE_STATUS_SHFT                                                   0x1f
#define HWIO_GCC_PCIE_WIGIG_CLKREF_EN_PCIE_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_PCIE_WIGIG_CLKREF_EN_PCIE_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_PCIE_MDM_CLKREF_EN_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0008c00c)
#define HWIO_GCC_PCIE_MDM_CLKREF_EN_RMSK                                                           0x80000001
#define HWIO_GCC_PCIE_MDM_CLKREF_EN_IN          \
        in_dword(HWIO_GCC_PCIE_MDM_CLKREF_EN_ADDR)
#define HWIO_GCC_PCIE_MDM_CLKREF_EN_INM(m)      \
        in_dword_masked(HWIO_GCC_PCIE_MDM_CLKREF_EN_ADDR, m)
#define HWIO_GCC_PCIE_MDM_CLKREF_EN_OUT(v)      \
        out_dword(HWIO_GCC_PCIE_MDM_CLKREF_EN_ADDR,v)
#define HWIO_GCC_PCIE_MDM_CLKREF_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PCIE_MDM_CLKREF_EN_ADDR,m,v,HWIO_GCC_PCIE_MDM_CLKREF_EN_IN)
#define HWIO_GCC_PCIE_MDM_CLKREF_EN_PCIE_STATUS_BMSK                                               0x80000000
#define HWIO_GCC_PCIE_MDM_CLKREF_EN_PCIE_STATUS_SHFT                                                     0x1f
#define HWIO_GCC_PCIE_MDM_CLKREF_EN_PCIE_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_PCIE_MDM_CLKREF_EN_PCIE_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_USB3_SEC_CLKREF_EN_ADDR                                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0008c010)
#define HWIO_GCC_USB3_SEC_CLKREF_EN_RMSK                                                           0x80000001
#define HWIO_GCC_USB3_SEC_CLKREF_EN_IN          \
        in_dword(HWIO_GCC_USB3_SEC_CLKREF_EN_ADDR)
#define HWIO_GCC_USB3_SEC_CLKREF_EN_INM(m)      \
        in_dword_masked(HWIO_GCC_USB3_SEC_CLKREF_EN_ADDR, m)
#define HWIO_GCC_USB3_SEC_CLKREF_EN_OUT(v)      \
        out_dword(HWIO_GCC_USB3_SEC_CLKREF_EN_ADDR,v)
#define HWIO_GCC_USB3_SEC_CLKREF_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_USB3_SEC_CLKREF_EN_ADDR,m,v,HWIO_GCC_USB3_SEC_CLKREF_EN_IN)
#define HWIO_GCC_USB3_SEC_CLKREF_EN_USB3_STATUS_BMSK                                               0x80000000
#define HWIO_GCC_USB3_SEC_CLKREF_EN_USB3_STATUS_SHFT                                                     0x1f
#define HWIO_GCC_USB3_SEC_CLKREF_EN_USB3_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_USB3_SEC_CLKREF_EN_USB3_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_GPU_IREF_EN_ADDR                                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0008c014)
#define HWIO_GCC_GPU_IREF_EN_RMSK                                                                  0x80000001
#define HWIO_GCC_GPU_IREF_EN_IN          \
        in_dword(HWIO_GCC_GPU_IREF_EN_ADDR)
#define HWIO_GCC_GPU_IREF_EN_INM(m)      \
        in_dword_masked(HWIO_GCC_GPU_IREF_EN_ADDR, m)
#define HWIO_GCC_GPU_IREF_EN_OUT(v)      \
        out_dword(HWIO_GCC_GPU_IREF_EN_ADDR,v)
#define HWIO_GCC_GPU_IREF_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPU_IREF_EN_ADDR,m,v,HWIO_GCC_GPU_IREF_EN_IN)
#define HWIO_GCC_GPU_IREF_EN_GPU_STATUS_BMSK                                                       0x80000000
#define HWIO_GCC_GPU_IREF_EN_GPU_STATUS_SHFT                                                             0x1f
#define HWIO_GCC_GPU_IREF_EN_GPU_ENABLE_BMSK                                                              0x1
#define HWIO_GCC_GPU_IREF_EN_GPU_ENABLE_SHFT                                                              0x0

#define HWIO_GCC_CXO2_TX1_CLKREF_EN1_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0008c018)
#define HWIO_GCC_CXO2_TX1_CLKREF_EN1_RMSK                                                          0x80000001
#define HWIO_GCC_CXO2_TX1_CLKREF_EN1_IN          \
        in_dword(HWIO_GCC_CXO2_TX1_CLKREF_EN1_ADDR)
#define HWIO_GCC_CXO2_TX1_CLKREF_EN1_INM(m)      \
        in_dword_masked(HWIO_GCC_CXO2_TX1_CLKREF_EN1_ADDR, m)
#define HWIO_GCC_CXO2_TX1_CLKREF_EN1_OUT(v)      \
        out_dword(HWIO_GCC_CXO2_TX1_CLKREF_EN1_ADDR,v)
#define HWIO_GCC_CXO2_TX1_CLKREF_EN1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CXO2_TX1_CLKREF_EN1_ADDR,m,v,HWIO_GCC_CXO2_TX1_CLKREF_EN1_IN)
#define HWIO_GCC_CXO2_TX1_CLKREF_EN1_CXO2_TX1_STATUS_BMSK                                          0x80000000
#define HWIO_GCC_CXO2_TX1_CLKREF_EN1_CXO2_TX1_STATUS_SHFT                                                0x1f
#define HWIO_GCC_CXO2_TX1_CLKREF_EN1_CXO2_TX1_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_CXO2_TX1_CLKREF_EN1_CXO2_TX1_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_CLKREF_SPARE_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0008c01c)
#define HWIO_GCC_CLKREF_SPARE_RMSK                                                                       0xff
#define HWIO_GCC_CLKREF_SPARE_IN          \
        in_dword(HWIO_GCC_CLKREF_SPARE_ADDR)
#define HWIO_GCC_CLKREF_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_CLKREF_SPARE_ADDR, m)
#define HWIO_GCC_CLKREF_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_CLKREF_SPARE_ADDR,v)
#define HWIO_GCC_CLKREF_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CLKREF_SPARE_ADDR,m,v,HWIO_GCC_CLKREF_SPARE_IN)
#define HWIO_GCC_CLKREF_SPARE_SPARE_BMSK                                                                 0xff
#define HWIO_GCC_CLKREF_SPARE_SPARE_SHFT                                                                  0x0

#define HWIO_GCC_MMNOC_GDS_HW_CTRL_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0000915c)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_RMSK                                                            0xffffdfff
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IN          \
        in_dword(HWIO_GCC_MMNOC_GDS_HW_CTRL_ADDR)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_ADDR, m)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_GDS_HW_CTRL_ADDR,v)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_GDS_HW_CTRL_ADDR,m,v,HWIO_GCC_MMNOC_GDS_HW_CTRL_IN)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_PWR_ON_STATUS_BMSK                                              0x80000000
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_PWR_ON_STATUS_SHFT                                                    0x1f
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_RESERVE_30_15_BMSK                                              0x7fff8000
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_RESERVE_30_15_SHFT                                                     0xf
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_COLLAPSE_OUT_BMSK                                                   0x4000
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_COLLAPSE_OUT_SHFT                                                      0xe
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_HALT_ACK_TIMEOUT_BMSK                                               0x1fe0
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_HALT_ACK_TIMEOUT_SHFT                                                  0x5
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_GDS_HW_STATE_BMSK                                                     0x1e
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_GDS_HW_STATE_SHFT                                                      0x1
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SW_OVERRIDE_BMSK                                                       0x1
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SW_OVERRIDE_SHFT                                                       0x0

#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00009160)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_RMSK                                                     0xffffffff
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_IN          \
        in_dword(HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_ADDR)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_ADDR, m)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_ADDR,v)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_ADDR,m,v,HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_IN)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_RESERVE_24_31_BMSK                                       0xff000000
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_RESERVE_24_31_SHFT                                             0x18
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_ACK_STATUS_BMSK                         0xf00000
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_DOWN_ACK_STATUS_SHFT                             0x14
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_UP_ACK_STATUS_BMSK                            0xf0000
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_DVM_HALT1_PWR_UP_ACK_STATUS_SHFT                               0x10
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_ACK_STATUS_BMSK                               0xf000
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT1_PWR_DOWN_ACK_STATUS_SHFT                                  0xc
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT1_PWR_UP_ACK_STATUS_BMSK                                  0xf00
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT1_PWR_UP_ACK_STATUS_SHFT                                    0x8
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_RESERVE_7_5_BMSK                                               0xe0
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_RESERVE_7_5_SHFT                                                0x5
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_ACK_STATUS_BMSK                                 0x10
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT2_PWR_DOWN_ACK_STATUS_SHFT                                  0x4
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_RESERVE_3_1_BMSK                                                0xe
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_RESERVE_3_1_SHFT                                                0x1
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT2_PWR_UP_ACK_STATUS_BMSK                                    0x1
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_HALT2_PWR_UP_ACK_STATUS_SHFT                                    0x0

#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00009464)
#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_RMSK                                                        0x1ff
#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_IN          \
        in_dword(HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_ADDR)
#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_ADDR, m)
#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_ADDR,v)
#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_ADDR,m,v,HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_IN)
#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_DVM_HALT_REQ_BMSK                                           0x1e0
#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_DVM_HALT_REQ_SHFT                                             0x5
#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_MMU_TBU_HALT_REQ_BMSK                                        0x1e
#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_MMU_TBU_HALT_REQ_SHFT                                         0x1
#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_NOC_HALT_REQ_BMSK                                             0x1
#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_NOC_HALT_REQ_SHFT                                             0x0

#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00009468)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_RMSK                                                        0x1
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_IN          \
        in_dword(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_ADDR)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_ADDR, m)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_STATUS_BMSK                                                 0x1
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_STATUS_SHFT                                                 0x0

#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0000946c)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_RMSK                                                          0x1
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_IN          \
        in_dword(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_ADDR)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_ADDR, m)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_ADDR,v)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_ADDR,m,v,HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_IN)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_MASK_BMSK                                                     0x1
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_MASK_SHFT                                                     0x0

#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00009470)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_RMSK                                                         0x1
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_IN          \
        in_dword(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_ADDR)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_ADDR, m)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_ADDR,v)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_ADDR,m,v,HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_IN)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_CLEAR_BMSK                                                   0x1
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_CLEAR_SHFT                                                   0x0

#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00009474)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_RMSK                                                            0xff
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_IN          \
        in_dword(HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_ADDR)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_ADDR, m)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_ADDR,v)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_ADDR,m,v,HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_IN)
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_SPARE_BMSK                                                      0xff
#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_SPARE_SHFT                                                       0x0

#define HWIO_GCC_MMNOC_TBU_TIMEOUT_ADDR                                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00009478)
#define HWIO_GCC_MMNOC_TBU_TIMEOUT_RMSK                                                                   0xf
#define HWIO_GCC_MMNOC_TBU_TIMEOUT_IN          \
        in_dword(HWIO_GCC_MMNOC_TBU_TIMEOUT_ADDR)
#define HWIO_GCC_MMNOC_TBU_TIMEOUT_INM(m)      \
        in_dword_masked(HWIO_GCC_MMNOC_TBU_TIMEOUT_ADDR, m)
#define HWIO_GCC_MMNOC_TBU_TIMEOUT_TBU_HF1_TIMEOUT_BMSK                                                   0x8
#define HWIO_GCC_MMNOC_TBU_TIMEOUT_TBU_HF1_TIMEOUT_SHFT                                                   0x3
#define HWIO_GCC_MMNOC_TBU_TIMEOUT_TBU_HF0_TIMEOUT_BMSK                                                   0x4
#define HWIO_GCC_MMNOC_TBU_TIMEOUT_TBU_HF0_TIMEOUT_SHFT                                                   0x2
#define HWIO_GCC_MMNOC_TBU_TIMEOUT_TBU_SF1_TIMEOUT_BMSK                                                   0x2
#define HWIO_GCC_MMNOC_TBU_TIMEOUT_TBU_SF1_TIMEOUT_SHFT                                                   0x1
#define HWIO_GCC_MMNOC_TBU_TIMEOUT_TBU_SF0_TIMEOUT_BMSK                                                   0x1
#define HWIO_GCC_MMNOC_TBU_TIMEOUT_TBU_SF0_TIMEOUT_SHFT                                                   0x0

#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_STATUS_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00082884)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_STATUS_RMSK                                                     0x1
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_STATUS_IN          \
        in_dword(HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_STATUS_ADDR)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_STATUS_ADDR, m)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_STATUS_STATUS_BMSK                                              0x1
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_STATUS_STATUS_SHFT                                              0x0

#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00082888)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_RMSK                                                       0x1
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_IN          \
        in_dword(HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_ADDR)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_INM(m)      \
        in_dword_masked(HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_ADDR, m)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_OUT(v)      \
        out_dword(HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_ADDR,v)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_ADDR,m,v,HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_IN)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_MASK_BMSK                                                  0x1
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_MASK_SHFT                                                  0x0

#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0008288c)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_RMSK                                                      0x1
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_IN          \
        in_dword(HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_ADDR)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_INM(m)      \
        in_dword_masked(HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_ADDR, m)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_OUT(v)      \
        out_dword(HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_ADDR,v)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_ADDR,m,v,HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_IN)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_CLEAR_BMSK                                                0x1
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_CLEAR_SHFT                                                0x0

#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00082890)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_RMSK                                                         0xff
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_IN          \
        in_dword(HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_ADDR)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_ADDR, m)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_ADDR,v)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_ADDR,m,v,HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_IN)
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_SPARE_BMSK                                                   0xff
#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_SPARE_SHFT                                                    0x0

#define HWIO_GCC_ANOC_TBU_RESET_CNTR_VALUE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00082894)
#define HWIO_GCC_ANOC_TBU_RESET_CNTR_VALUE_RMSK                                                         0x3ff
#define HWIO_GCC_ANOC_TBU_RESET_CNTR_VALUE_IN          \
        in_dword(HWIO_GCC_ANOC_TBU_RESET_CNTR_VALUE_ADDR)
#define HWIO_GCC_ANOC_TBU_RESET_CNTR_VALUE_INM(m)      \
        in_dword_masked(HWIO_GCC_ANOC_TBU_RESET_CNTR_VALUE_ADDR, m)
#define HWIO_GCC_ANOC_TBU_RESET_CNTR_VALUE_OUT(v)      \
        out_dword(HWIO_GCC_ANOC_TBU_RESET_CNTR_VALUE_ADDR,v)
#define HWIO_GCC_ANOC_TBU_RESET_CNTR_VALUE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_ANOC_TBU_RESET_CNTR_VALUE_ADDR,m,v,HWIO_GCC_ANOC_TBU_RESET_CNTR_VALUE_IN)
#define HWIO_GCC_ANOC_TBU_RESET_CNTR_VALUE_COUNT_BMSK                                                   0x3ff
#define HWIO_GCC_ANOC_TBU_RESET_CNTR_VALUE_COUNT_SHFT                                                     0x0

#define HWIO_GCC_ANOC_TBU_TIMEOUT_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00082898)
#define HWIO_GCC_ANOC_TBU_TIMEOUT_RMSK                                                                    0xf
#define HWIO_GCC_ANOC_TBU_TIMEOUT_IN          \
        in_dword(HWIO_GCC_ANOC_TBU_TIMEOUT_ADDR)
#define HWIO_GCC_ANOC_TBU_TIMEOUT_INM(m)      \
        in_dword_masked(HWIO_GCC_ANOC_TBU_TIMEOUT_ADDR, m)
#define HWIO_GCC_ANOC_TBU_TIMEOUT_TBU1_GCC_TIMEOUT_BMSK                                                   0x8
#define HWIO_GCC_ANOC_TBU_TIMEOUT_TBU1_GCC_TIMEOUT_SHFT                                                   0x3
#define HWIO_GCC_ANOC_TBU_TIMEOUT_TBU0_GCC_TIMEOUT_BMSK                                                   0x4
#define HWIO_GCC_ANOC_TBU_TIMEOUT_TBU0_GCC_TIMEOUT_SHFT                                                   0x2
#define HWIO_GCC_ANOC_TBU_TIMEOUT_PCIE_TBU_GCC_TIMEOUT_BMSK                                               0x2
#define HWIO_GCC_ANOC_TBU_TIMEOUT_PCIE_TBU_GCC_TIMEOUT_SHFT                                               0x1
#define HWIO_GCC_ANOC_TBU_TIMEOUT_AUDIO_TBU_GCC_TIMEOUT_BMSK                                              0x1
#define HWIO_GCC_ANOC_TBU_TIMEOUT_AUDIO_TBU_GCC_TIMEOUT_SHFT                                              0x0

#define HWIO_GCC_ANOC_TBU_PWR_QCHANNEL_HANDSHAKE_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0008289c)
#define HWIO_GCC_ANOC_TBU_PWR_QCHANNEL_HANDSHAKE_RMSK                                                    0x1f
#define HWIO_GCC_ANOC_TBU_PWR_QCHANNEL_HANDSHAKE_IN          \
        in_dword(HWIO_GCC_ANOC_TBU_PWR_QCHANNEL_HANDSHAKE_ADDR)
#define HWIO_GCC_ANOC_TBU_PWR_QCHANNEL_HANDSHAKE_INM(m)      \
        in_dword_masked(HWIO_GCC_ANOC_TBU_PWR_QCHANNEL_HANDSHAKE_ADDR, m)
#define HWIO_GCC_ANOC_TBU_PWR_QCHANNEL_HANDSHAKE_FSM_STATE_BMSK                                          0x1f
#define HWIO_GCC_ANOC_TBU_PWR_QCHANNEL_HANDSHAKE_FSM_STATE_SHFT                                           0x0

#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_STATUS_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00045384)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_STATUS_RMSK                                                 0x1
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_STATUS_IN          \
        in_dword(HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_STATUS_ADDR)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_STATUS_ADDR, m)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_STATUS_STATUS_BMSK                                          0x1
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_STATUS_STATUS_SHFT                                          0x0

#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_MASK_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00045388)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_MASK_RMSK                                                   0x1
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_MASK_IN          \
        in_dword(HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_MASK_ADDR)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_MASK_INM(m)      \
        in_dword_masked(HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_MASK_ADDR, m)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_MASK_OUT(v)      \
        out_dword(HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_MASK_ADDR,v)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_MASK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_MASK_ADDR,m,v,HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_MASK_IN)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_MASK_MASK_BMSK                                              0x1
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_MASK_MASK_SHFT                                              0x0

#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0004538c)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_RMSK                                                  0x1
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_IN          \
        in_dword(HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_ADDR)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_INM(m)      \
        in_dword_masked(HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_ADDR, m)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_OUT(v)      \
        out_dword(HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_ADDR,v)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_ADDR,m,v,HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_IN)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_CLEAR_BMSK                                            0x1
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_CLEAR_SHFT                                            0x0

#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_SPARE_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00045390)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_SPARE_RMSK                                                     0xff
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_SPARE_IN          \
        in_dword(HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_SPARE_ADDR)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_SPARE_INM(m)      \
        in_dword_masked(HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_SPARE_ADDR, m)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_SPARE_OUT(v)      \
        out_dword(HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_SPARE_ADDR,v)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_SPARE_ADDR,m,v,HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_SPARE_IN)
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_SPARE_SPARE_BMSK                                               0xff
#define HWIO_GCC_CDSP_NOC_TBU_GDS_HW_CTRL_SPARE_SPARE_SHFT                                                0x0

#define HWIO_GCC_CDSP_NOC_TBU_RESET_CNTR_VALUE_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00045394)
#define HWIO_GCC_CDSP_NOC_TBU_RESET_CNTR_VALUE_RMSK                                                     0x3ff
#define HWIO_GCC_CDSP_NOC_TBU_RESET_CNTR_VALUE_IN          \
        in_dword(HWIO_GCC_CDSP_NOC_TBU_RESET_CNTR_VALUE_ADDR)
#define HWIO_GCC_CDSP_NOC_TBU_RESET_CNTR_VALUE_INM(m)      \
        in_dword_masked(HWIO_GCC_CDSP_NOC_TBU_RESET_CNTR_VALUE_ADDR, m)
#define HWIO_GCC_CDSP_NOC_TBU_RESET_CNTR_VALUE_OUT(v)      \
        out_dword(HWIO_GCC_CDSP_NOC_TBU_RESET_CNTR_VALUE_ADDR,v)
#define HWIO_GCC_CDSP_NOC_TBU_RESET_CNTR_VALUE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CDSP_NOC_TBU_RESET_CNTR_VALUE_ADDR,m,v,HWIO_GCC_CDSP_NOC_TBU_RESET_CNTR_VALUE_IN)
#define HWIO_GCC_CDSP_NOC_TBU_RESET_CNTR_VALUE_COUNT_BMSK                                               0x3ff
#define HWIO_GCC_CDSP_NOC_TBU_RESET_CNTR_VALUE_COUNT_SHFT                                                 0x0

#define HWIO_GCC_CDSP_NOC_TBU_TIMEOUT_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00045398)
#define HWIO_GCC_CDSP_NOC_TBU_TIMEOUT_RMSK                                                                0x3
#define HWIO_GCC_CDSP_NOC_TBU_TIMEOUT_IN          \
        in_dword(HWIO_GCC_CDSP_NOC_TBU_TIMEOUT_ADDR)
#define HWIO_GCC_CDSP_NOC_TBU_TIMEOUT_INM(m)      \
        in_dword_masked(HWIO_GCC_CDSP_NOC_TBU_TIMEOUT_ADDR, m)
#define HWIO_GCC_CDSP_NOC_TBU_TIMEOUT_TBU1_GCC_TIMEOUT_BMSK                                               0x2
#define HWIO_GCC_CDSP_NOC_TBU_TIMEOUT_TBU1_GCC_TIMEOUT_SHFT                                               0x1
#define HWIO_GCC_CDSP_NOC_TBU_TIMEOUT_TBU0_GCC_TIMEOUT_BMSK                                               0x1
#define HWIO_GCC_CDSP_NOC_TBU_TIMEOUT_TBU0_GCC_TIMEOUT_SHFT                                               0x0

#define HWIO_GCC_CDSP_NOC_PWR_QCHANNEL_HANDSHAKE_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0004539c)
#define HWIO_GCC_CDSP_NOC_PWR_QCHANNEL_HANDSHAKE_RMSK                                                    0x1f
#define HWIO_GCC_CDSP_NOC_PWR_QCHANNEL_HANDSHAKE_IN          \
        in_dword(HWIO_GCC_CDSP_NOC_PWR_QCHANNEL_HANDSHAKE_ADDR)
#define HWIO_GCC_CDSP_NOC_PWR_QCHANNEL_HANDSHAKE_INM(m)      \
        in_dword_masked(HWIO_GCC_CDSP_NOC_PWR_QCHANNEL_HANDSHAKE_ADDR, m)
#define HWIO_GCC_CDSP_NOC_PWR_QCHANNEL_HANDSHAKE_FSM_STATE_BMSK                                          0x1f
#define HWIO_GCC_CDSP_NOC_PWR_QCHANNEL_HANDSHAKE_FSM_STATE_SHFT                                           0x0

#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00086000)
#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_RMSK                                                         0x80000001
#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_IN          \
        in_dword(HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_ADDR)
#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_ADDR, m)
#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_ADDR,v)
#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_IN)
#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00086004)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_RMSK                                          0x80000001
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_IN          \
        in_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR, m)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR,v)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_IN)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_OFF_BMSK                                  0x80000000
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_OFF_SHFT                                        0x1f
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_ENABLE_BMSK                                      0x1
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_ENABLE_SHFT                                      0x0

#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00086008)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK                                               0x80000001
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN          \
        in_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, m)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,v)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0008600c)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK                                               0x80000001
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN          \
        in_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, m)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,v)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00086010)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_RMSK                                           0x80000001
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_IN          \
        in_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR, m)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR,v)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_IN)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_OFF_BMSK                                   0x80000000
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_OFF_SHFT                                         0x1f
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_ENABLE_BMSK                                       0x1
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_ENABLE_SHFT                                       0x0

#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00086014)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_CLK_RMSK                                                0x80000001
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_CLK_IN          \
        in_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR, m)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR,v)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_CLK_IN)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_OFF_BMSK                                        0x80000000
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_OFF_SHFT                                              0x1f
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_ENABLE_BMSK                                            0x1
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_ENABLE_SHFT                                            0x0

#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00086018)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_RMSK                                                0x80000001
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_IN          \
        in_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR, m)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR,v)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_IN)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_OFF_BMSK                                        0x80000000
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_OFF_SHFT                                              0x1f
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_ENABLE_BMSK                                            0x1
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_ENABLE_SHFT                                            0x0

#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0008601c)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_RMSK                                                0x80000001
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_IN          \
        in_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR, m)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR,v)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_IN)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_OFF_BMSK                                        0x80000000
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_OFF_SHFT                                              0x1f
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_ENABLE_BMSK                                            0x1
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_ENABLE_SHFT                                            0x0

#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00086020)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_RMSK                                                  0x80000001
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_IN          \
        in_dword(HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_ADDR)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_ADDR, m)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_ADDR,v)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_IN)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_CLK_OFF_BMSK                                          0x80000000
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_CLK_OFF_SHFT                                                0x1f
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_CLK_ENABLE_BMSK                                              0x1
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_CLK_ENABLE_SHFT                                              0x0

#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00086024)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_RMSK                                                  0x80000001
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_IN          \
        in_dword(HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_ADDR)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_ADDR, m)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_ADDR,v)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_IN)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_CLK_OFF_BMSK                                          0x80000000
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_CLK_OFF_SHFT                                                0x1f
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_CLK_ENABLE_BMSK                                              0x1
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_CLK_ENABLE_SHFT                                              0x0

#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00086028)
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_RMSK                                                     0x80000001
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_IN          \
        in_dword(HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_ADDR)
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_ADDR, m)
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_ADDR,v)
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_IN)
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0008602c)
#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_RMSK                                                          0x80000001
#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_IN          \
        in_dword(HWIO_GCC_SP_VOTE_MMU_TCU_CLK_ADDR)
#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_MMU_TCU_CLK_ADDR, m)
#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_MMU_TCU_CLK_ADDR,v)
#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_MMU_TCU_CLK_IN)
#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK                                                  0x80000000
#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT                                                        0x1f
#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK                                                      0x1
#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT                                                      0x0

#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00086030)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_CLK_RMSK                                                0x80000001
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_CLK_IN          \
        in_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR, m)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR,v)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR,m,v,HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_CLK_IN)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_OFF_BMSK                                        0x80000000
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_OFF_SHFT                                              0x1f
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_ENABLE_BMSK                                            0x1
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_ENABLE_SHFT                                            0x0

#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0008603c)
#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_RMSK                                                         0x80000001
#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_IN          \
        in_dword(HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_ADDR)
#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_ADDR, m)
#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_ADDR,v)
#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_IN)
#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_PWR_ON_BMSK                                                  0x80000000
#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_PWR_ON_SHFT                                                        0x1f
#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_BMSK                                                    0x1
#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_SHFT                                                    0x0

#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00086040)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_RMSK                                          0x80000001
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_IN          \
        in_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR, m)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR,v)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_IN)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PWR_ON_BMSK                                   0x80000000
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PWR_ON_SHFT                                         0x1f
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_SW_COLLAPSE_BMSK                                     0x1
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_SW_COLLAPSE_SHFT                                     0x0

#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00086044)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_RMSK                                               0x80000001
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_IN          \
        in_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR, m)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR,v)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_IN)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PWR_ON_BMSK                                        0x80000000
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PWR_ON_SHFT                                              0x1f
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_SW_COLLAPSE_BMSK                                          0x1
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_SW_COLLAPSE_SHFT                                          0x0

#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00086048)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_RMSK                                               0x80000001
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_IN          \
        in_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR, m)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR,v)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_IN)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PWR_ON_BMSK                                        0x80000000
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PWR_ON_SHFT                                              0x1f
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_SW_COLLAPSE_BMSK                                          0x1
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_SW_COLLAPSE_SHFT                                          0x0

#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0008604c)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_RMSK                                           0x80000001
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_IN          \
        in_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR, m)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR,v)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_IN)
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PWR_ON_BMSK                                    0x80000000
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PWR_ON_SHFT                                          0x1f
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_SW_COLLAPSE_BMSK                                      0x1
#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_SW_COLLAPSE_SHFT                                      0x0

#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00086050)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_RMSK                                                0x80000001
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_IN          \
        in_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR, m)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR,v)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_IN)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_PWR_ON_BMSK                                         0x80000000
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_PWR_ON_SHFT                                               0x1f
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_SW_COLLAPSE_BMSK                                           0x1
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_SW_COLLAPSE_SHFT                                           0x0

#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00086054)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_GDS_RMSK                                                0x80000001
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_GDS_IN          \
        in_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR, m)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR,v)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_GDS_IN)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_GDS_PWR_ON_BMSK                                         0x80000000
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_GDS_PWR_ON_SHFT                                               0x1f
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_GDS_SW_COLLAPSE_BMSK                                           0x1
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF0_GDS_SW_COLLAPSE_SHFT                                           0x0

#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x00086058)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_RMSK                                                0x80000001
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_IN          \
        in_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR, m)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR,v)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_IN)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_PWR_ON_BMSK                                         0x80000000
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_PWR_ON_SHFT                                               0x1f
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_SW_COLLAPSE_BMSK                                           0x1
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_SW_COLLAPSE_SHFT                                           0x0

#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0008605c)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_RMSK                                                  0x80000001
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_IN          \
        in_dword(HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_ADDR)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_ADDR, m)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_ADDR,v)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_IN)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_PWR_ON_BMSK                                           0x80000000
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_PWR_ON_SHFT                                                 0x1f
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_SW_COLLAPSE_BMSK                                             0x1
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_SW_COLLAPSE_SHFT                                             0x0

#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00086060)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_RMSK                                                  0x80000001
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_IN          \
        in_dword(HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_ADDR)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_ADDR, m)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_ADDR,v)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_IN)
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_PWR_ON_BMSK                                           0x80000000
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_PWR_ON_SHFT                                                 0x1f
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_SW_COLLAPSE_BMSK                                             0x1
#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_SW_COLLAPSE_SHFT                                             0x0

#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00086064)
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_RMSK                                                     0x80000001
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_IN          \
        in_dword(HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_ADDR)
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_ADDR, m)
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_ADDR,v)
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_IN)
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_BMSK                                              0x80000000
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_SHFT                                                    0x1f
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_BMSK                                                0x1
#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_SHFT                                                0x0

#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_ADDR                                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00086068)
#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_RMSK                                                          0x80000001
#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_IN          \
        in_dword(HWIO_GCC_SP_VOTE_MMU_TCU_GDS_ADDR)
#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_MMU_TCU_GDS_ADDR, m)
#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_MMU_TCU_GDS_ADDR,v)
#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMU_TCU_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_MMU_TCU_GDS_IN)
#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_PWR_ON_BMSK                                                   0x80000000
#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_PWR_ON_SHFT                                                         0x1f
#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_BMSK                                                     0x1
#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_SHFT                                                     0x0

#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0008606c)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_GDS_RMSK                                                0x80000001
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_GDS_IN          \
        in_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR, m)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR,v)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR,m,v,HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_GDS_IN)
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_GDS_PWR_ON_BMSK                                         0x80000000
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_GDS_PWR_ON_SHFT                                               0x1f
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_GDS_SW_COLLAPSE_BMSK                                           0x1
#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF1_GDS_SW_COLLAPSE_SHFT                                           0x0

#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00087000)
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_RMSK                                                        0x80000001
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_ADDR)
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_ADDR, m)
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_ADDR,v)
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_IN)
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00087004)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_RMSK                                         0x80000001
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR, m)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR,v)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_IN)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_OFF_BMSK                                 0x80000000
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_OFF_SHFT                                       0x1f
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_ENABLE_BMSK                                     0x1
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_ENABLE_SHFT                                     0x0

#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00087008)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK                                              0x80000001
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, m)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,v)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_BMSK                                      0x80000000
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_SHFT                                            0x1f
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_BMSK                                          0x1
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_SHFT                                          0x0

#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0008700c)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK                                              0x80000001
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, m)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,v)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_BMSK                                      0x80000000
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_SHFT                                            0x1f
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_BMSK                                          0x1
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_SHFT                                          0x0

#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00087010)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_RMSK                                          0x80000001
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR, m)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR,v)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_IN)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_OFF_BMSK                                  0x80000000
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_OFF_SHFT                                        0x1f
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_ENABLE_BMSK                                      0x1
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_ENABLE_SHFT                                      0x0

#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00087014)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_CLK_RMSK                                               0x80000001
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_CLK_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR, m)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR,v)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_CLK_IN)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00087018)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_RMSK                                               0x80000001
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR, m)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR,v)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_IN)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0008701c)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_RMSK                                               0x80000001
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR, m)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR,v)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_IN)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00087020)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_RMSK                                                 0x80000001
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_ADDR)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_ADDR, m)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_ADDR,v)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_IN)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_CLK_OFF_BMSK                                         0x80000000
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_CLK_OFF_SHFT                                               0x1f
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_CLK_ENABLE_BMSK                                             0x1
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_CLK_ENABLE_SHFT                                             0x0

#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00087024)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_RMSK                                                 0x80000001
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_ADDR)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_ADDR, m)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_ADDR,v)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_IN)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_CLK_OFF_BMSK                                         0x80000000
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_CLK_OFF_SHFT                                               0x1f
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_CLK_ENABLE_BMSK                                             0x1
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_CLK_ENABLE_SHFT                                             0x0

#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00087028)
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_RMSK                                                    0x80000001
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR)
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR, m)
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR,v)
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_IN)
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x0008702c)
#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_RMSK                                                         0x80000001
#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR)
#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR, m)
#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR,v)
#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_IN)
#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT                                                       0x1f
#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT                                                     0x0

#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00087030)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_CLK_RMSK                                               0x80000001
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_CLK_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR, m)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR,v)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_CLK_IN)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_OFF_BMSK                                       0x80000000
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_OFF_SHFT                                             0x1f
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_ENABLE_BMSK                                           0x1
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_ENABLE_SHFT                                           0x0

#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0008703c)
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_RMSK                                                        0x80000001
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_ADDR)
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_ADDR, m)
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_ADDR,v)
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_IN)
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_PWR_ON_BMSK                                                 0x80000000
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_PWR_ON_SHFT                                                       0x1f
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_BMSK                                                   0x1
#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_SHFT                                                   0x0

#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00087040)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_RMSK                                         0x80000001
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR, m)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR,v)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_IN)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PWR_ON_BMSK                                  0x80000000
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PWR_ON_SHFT                                        0x1f
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_SW_COLLAPSE_BMSK                                    0x1
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_SW_COLLAPSE_SHFT                                    0x0

#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00087044)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_RMSK                                              0x80000001
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR, m)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR,v)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_IN)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PWR_ON_BMSK                                       0x80000000
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PWR_ON_SHFT                                             0x1f
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_SW_COLLAPSE_BMSK                                         0x1
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_SW_COLLAPSE_SHFT                                         0x0

#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00087048)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_RMSK                                              0x80000001
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR, m)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR,v)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_IN)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PWR_ON_BMSK                                       0x80000000
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PWR_ON_SHFT                                             0x1f
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_SW_COLLAPSE_BMSK                                         0x1
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_SW_COLLAPSE_SHFT                                         0x0

#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0008704c)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_RMSK                                          0x80000001
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR, m)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR,v)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_IN)
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PWR_ON_BMSK                                   0x80000000
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PWR_ON_SHFT                                         0x1f
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_SW_COLLAPSE_BMSK                                     0x1
#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_SW_COLLAPSE_SHFT                                     0x0

#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00087050)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_RMSK                                               0x80000001
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR, m)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR,v)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_IN)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_PWR_ON_BMSK                                        0x80000000
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_PWR_ON_SHFT                                              0x1f
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_SW_COLLAPSE_BMSK                                          0x1
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_SW_COLLAPSE_SHFT                                          0x0

#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00087054)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_GDS_RMSK                                               0x80000001
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_GDS_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR, m)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR,v)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_GDS_IN)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_GDS_PWR_ON_BMSK                                        0x80000000
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_GDS_PWR_ON_SHFT                                              0x1f
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_GDS_SW_COLLAPSE_BMSK                                          0x1
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF0_GDS_SW_COLLAPSE_SHFT                                          0x0

#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00087058)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_RMSK                                               0x80000001
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR, m)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR,v)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_IN)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_PWR_ON_BMSK                                        0x80000000
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_PWR_ON_SHFT                                              0x1f
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_SW_COLLAPSE_BMSK                                          0x1
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_SW_COLLAPSE_SHFT                                          0x0

#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0008705c)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_RMSK                                                 0x80000001
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_ADDR)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_ADDR, m)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_ADDR,v)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_IN)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_PWR_ON_BMSK                                          0x80000000
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_PWR_ON_SHFT                                                0x1f
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_SW_COLLAPSE_BMSK                                            0x1
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_SW_COLLAPSE_SHFT                                            0x0

#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00087060)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_RMSK                                                 0x80000001
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_ADDR)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_ADDR, m)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_ADDR,v)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_IN)
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_PWR_ON_BMSK                                          0x80000000
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_PWR_ON_SHFT                                                0x1f
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_SW_COLLAPSE_BMSK                                            0x1
#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_SW_COLLAPSE_SHFT                                            0x0

#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00087064)
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_RMSK                                                    0x80000001
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_ADDR)
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_ADDR, m)
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_ADDR,v)
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_IN)
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_BMSK                                             0x80000000
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_SHFT                                                   0x1f
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_BMSK                                               0x1
#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_SHFT                                               0x0

#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00087068)
#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_RMSK                                                         0x80000001
#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_ADDR)
#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_ADDR, m)
#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_ADDR,v)
#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_IN)
#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_PWR_ON_BMSK                                                  0x80000000
#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_PWR_ON_SHFT                                                        0x1f
#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_SW_COLLAPSE_BMSK                                                    0x1
#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_SW_COLLAPSE_SHFT                                                    0x0

#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0008706c)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_GDS_RMSK                                               0x80000001
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_GDS_IN          \
        in_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR, m)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR,v)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR,m,v,HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_GDS_IN)
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_GDS_PWR_ON_BMSK                                        0x80000000
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_GDS_PWR_ON_SHFT                                              0x1f
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_GDS_SW_COLLAPSE_BMSK                                          0x1
#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF1_GDS_SW_COLLAPSE_SHFT                                          0x0

#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00019000)
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_RMSK                                                 0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_IN)
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_CLK_OFF_BMSK                                         0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_CLK_OFF_SHFT                                               0x1f
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_BMSK                                             0x1
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_CLK_ENABLE_SHFT                                             0x0

#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00019004)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_RMSK                                  0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_IN)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_OFF_BMSK                          0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_OFF_SHFT                                0x1f
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_ENABLE_BMSK                              0x1
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_CLK_ENABLE_SHFT                              0x0

#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00019008)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_RMSK                                       0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_IN)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_BMSK                               0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_OFF_SHFT                                     0x1f
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_BMSK                                   0x1
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_CLK_ENABLE_SHFT                                   0x0

#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0001900c)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_RMSK                                       0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_IN)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_BMSK                               0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_OFF_SHFT                                     0x1f
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_BMSK                                   0x1
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_CLK_ENABLE_SHFT                                   0x0

#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00019010)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_RMSK                                   0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_IN)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_OFF_BMSK                           0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_OFF_SHFT                                 0x1f
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_ENABLE_BMSK                               0x1
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_CLK_ENABLE_SHFT                               0x0

#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00019014)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_CLK_RMSK                                        0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_CLK_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_CLK_IN)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_OFF_BMSK                                0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_OFF_SHFT                                      0x1f
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_ENABLE_BMSK                                    0x1
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_CLK_CLK_ENABLE_SHFT                                    0x0

#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00019018)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_RMSK                                        0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_IN)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_OFF_BMSK                                0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_OFF_SHFT                                      0x1f
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_ENABLE_BMSK                                    0x1
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_CLK_ENABLE_SHFT                                    0x0

#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0001901c)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_RMSK                                        0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_IN)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_OFF_BMSK                                0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_OFF_SHFT                                      0x1f
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_ENABLE_BMSK                                    0x1
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_CLK_ENABLE_SHFT                                    0x0

#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00019020)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_RMSK                                          0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_IN)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_CLK_OFF_BMSK                                  0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_CLK_OFF_SHFT                                        0x1f
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_CLK_ENABLE_BMSK                                      0x1
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_CLK_ENABLE_SHFT                                      0x0

#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00019024)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_RMSK                                          0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_IN)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_CLK_OFF_BMSK                                  0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_CLK_OFF_SHFT                                        0x1f
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_CLK_ENABLE_BMSK                                      0x1
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_CLK_ENABLE_SHFT                                      0x0

#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00019028)
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_RMSK                                             0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_IN)
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_BMSK                                     0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_CLK_OFF_SHFT                                           0x1f
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_BMSK                                         0x1
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_CLK_ENABLE_SHFT                                         0x0

#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0001902c)
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_RMSK                                                  0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_IN)
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_CLK_OFF_BMSK                                          0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_CLK_OFF_SHFT                                                0x1f
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_CLK_ENABLE_BMSK                                              0x1
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_CLK_ENABLE_SHFT                                              0x0

#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00019030)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_CLK_RMSK                                        0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_CLK_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_CLK_IN)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_OFF_BMSK                                0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_OFF_SHFT                                      0x1f
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_ENABLE_BMSK                                    0x1
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_CLK_CLK_ENABLE_SHFT                                    0x0

#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0001903c)
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_RMSK                                                 0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_IN)
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_PWR_ON_BMSK                                          0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_PWR_ON_SHFT                                                0x1f
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_BMSK                                            0x1
#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_SW_COLLAPSE_SHFT                                            0x0

#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00019040)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_RMSK                                  0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_IN)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PWR_ON_BMSK                           0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PWR_ON_SHFT                                 0x1f
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_SW_COLLAPSE_BMSK                             0x1
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_SW_COLLAPSE_SHFT                             0x0

#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00019044)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_RMSK                                       0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_IN)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PWR_ON_BMSK                                0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PWR_ON_SHFT                                      0x1f
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_SW_COLLAPSE_BMSK                                  0x1
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_SW_COLLAPSE_SHFT                                  0x0

#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00019048)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_RMSK                                       0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_IN)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PWR_ON_BMSK                                0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PWR_ON_SHFT                                      0x1f
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_SW_COLLAPSE_BMSK                                  0x1
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_SW_COLLAPSE_SHFT                                  0x0

#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0001904c)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_RMSK                                   0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_IN)
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PWR_ON_BMSK                            0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PWR_ON_SHFT                                  0x1f
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_SW_COLLAPSE_BMSK                              0x1
#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_SW_COLLAPSE_SHFT                              0x0

#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00019050)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_RMSK                                        0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_IN)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_PWR_ON_BMSK                                 0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_PWR_ON_SHFT                                       0x1f
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_SW_COLLAPSE_BMSK                                   0x1
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_SW_COLLAPSE_SHFT                                   0x0

#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00019054)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_GDS_RMSK                                        0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_GDS_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_GDS_IN)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_GDS_PWR_ON_BMSK                                 0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_GDS_PWR_ON_SHFT                                       0x1f
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_GDS_SW_COLLAPSE_BMSK                                   0x1
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF0_GDS_SW_COLLAPSE_SHFT                                   0x0

#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00019058)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_RMSK                                        0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_IN)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_PWR_ON_BMSK                                 0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_PWR_ON_SHFT                                       0x1f
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_SW_COLLAPSE_BMSK                                   0x1
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_SW_COLLAPSE_SHFT                                   0x0

#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x0001905c)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_RMSK                                          0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_IN)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_PWR_ON_BMSK                                   0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_PWR_ON_SHFT                                         0x1f
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_SW_COLLAPSE_BMSK                                     0x1
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_SW_COLLAPSE_SHFT                                     0x0

#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_ADDR                                          (GCC_CLK_CTL_REG_REG_BASE      + 0x00019060)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_RMSK                                          0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_IN)
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_PWR_ON_BMSK                                   0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_PWR_ON_SHFT                                         0x1f
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_SW_COLLAPSE_BMSK                                     0x1
#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_SW_COLLAPSE_SHFT                                     0x0

#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00019064)
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_RMSK                                             0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_IN)
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_BMSK                                      0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_PWR_ON_SHFT                                            0x1f
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_BMSK                                        0x1
#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_SW_COLLAPSE_SHFT                                        0x0

#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00019068)
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_RMSK                                                  0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_IN)
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_PWR_ON_BMSK                                           0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_PWR_ON_SHFT                                                 0x1f
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_BMSK                                             0x1
#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_SW_COLLAPSE_SHFT                                             0x0

#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0001906c)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_GDS_RMSK                                        0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_GDS_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_GDS_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_GDS_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_GDS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_GDS_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_GDS_IN)
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_GDS_PWR_ON_BMSK                                 0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_GDS_PWR_ON_SHFT                                       0x1f
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_GDS_SW_COLLAPSE_BMSK                                   0x1
#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF1_GDS_SW_COLLAPSE_SHFT                                   0x0

#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00051124)
#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_RMSK                                                        0x80000001
#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_IN          \
        in_dword(HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR)
#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR, m)
#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_OUT(v)      \
        out_dword(HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR,v)
#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_IN)
#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00035124)
#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_RMSK                                                     0x80000001
#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_IN          \
        in_dword(HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR)
#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR, m)
#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_OUT(v)      \
        out_dword(HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR,v)
#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_IN)
#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00052124)
#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_RMSK                                                       0x80000001
#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_IN          \
        in_dword(HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR)
#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR, m)
#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_OUT(v)      \
        out_dword(HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR,v)
#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_IN)
#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK                                               0x80000000
#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT                                                     0x1f
#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00053124)
#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_RMSK                                                    0x80000001
#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_IN          \
        in_dword(HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR)
#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR, m)
#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_OUT(v)      \
        out_dword(HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR,v)
#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_IN)
#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK                                            0x80000000
#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT                                                  0x1f
#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK                                                0x1
#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT                                                0x0

#define HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00054124)
#define HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_RMSK                                                        0x80000001
#define HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_IN          \
        in_dword(HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_ADDR)
#define HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_ADDR, m)
#define HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_OUT(v)      \
        out_dword(HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_ADDR,v)
#define HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_IN)
#define HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00055124)
#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_RMSK                                                  0x80000001
#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_IN          \
        in_dword(HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_ADDR)
#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_ADDR, m)
#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_OUT(v)      \
        out_dword(HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_ADDR,v)
#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_IN)
#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK                                          0x80000000
#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT                                                0x1f
#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK                                              0x1
#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT                                              0x0

#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00056124)
#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_RMSK                                                        0x80000001
#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_IN          \
        in_dword(HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR)
#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR, m)
#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_OUT(v)      \
        out_dword(HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR,v)
#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_IN)
#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK                                                0x80000000
#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT                                                      0x1f
#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00057124)
#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_RMSK                                                 0x80000001
#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_IN          \
        in_dword(HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_ADDR)
#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_ADDR, m)
#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_OUT(v)      \
        out_dword(HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_ADDR,v)
#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_IN)
#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK                                         0x80000000
#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT                                               0x1f
#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK                                             0x1
#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT                                             0x0

#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0005a124)
#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_RMSK                                                     0x80000001
#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_IN          \
        in_dword(HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR)
#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR, m)
#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_OUT(v)      \
        out_dword(HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR,v)
#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_IN)
#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_NPU_Q6_VOTE_QDSS_APB_CLK_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00069124)
#define HWIO_GCC_NPU_Q6_VOTE_QDSS_APB_CLK_RMSK                                                     0x80000001
#define HWIO_GCC_NPU_Q6_VOTE_QDSS_APB_CLK_IN          \
        in_dword(HWIO_GCC_NPU_Q6_VOTE_QDSS_APB_CLK_ADDR)
#define HWIO_GCC_NPU_Q6_VOTE_QDSS_APB_CLK_INM(m)      \
        in_dword_masked(HWIO_GCC_NPU_Q6_VOTE_QDSS_APB_CLK_ADDR, m)
#define HWIO_GCC_NPU_Q6_VOTE_QDSS_APB_CLK_OUT(v)      \
        out_dword(HWIO_GCC_NPU_Q6_VOTE_QDSS_APB_CLK_ADDR,v)
#define HWIO_GCC_NPU_Q6_VOTE_QDSS_APB_CLK_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_NPU_Q6_VOTE_QDSS_APB_CLK_ADDR,m,v,HWIO_GCC_NPU_Q6_VOTE_QDSS_APB_CLK_IN)
#define HWIO_GCC_NPU_Q6_VOTE_QDSS_APB_CLK_CLK_OFF_BMSK                                             0x80000000
#define HWIO_GCC_NPU_Q6_VOTE_QDSS_APB_CLK_CLK_OFF_SHFT                                                   0x1f
#define HWIO_GCC_NPU_Q6_VOTE_QDSS_APB_CLK_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_GCC_NPU_Q6_VOTE_QDSS_APB_CLK_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_GCC_JBIST_MODE_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00080000)
#define HWIO_GCC_JBIST_MODE_RMSK                                                                   0xffffffff
#define HWIO_GCC_JBIST_MODE_IN          \
        in_dword(HWIO_GCC_JBIST_MODE_ADDR)
#define HWIO_GCC_JBIST_MODE_INM(m)      \
        in_dword_masked(HWIO_GCC_JBIST_MODE_ADDR, m)
#define HWIO_GCC_JBIST_MODE_OUT(v)      \
        out_dword(HWIO_GCC_JBIST_MODE_ADDR,v)
#define HWIO_GCC_JBIST_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_JBIST_MODE_ADDR,m,v,HWIO_GCC_JBIST_MODE_IN)
#define HWIO_GCC_JBIST_MODE_RESERVE_BITS31_9_BMSK                                                  0xfffffe00
#define HWIO_GCC_JBIST_MODE_RESERVE_BITS31_9_SHFT                                                         0x9
#define HWIO_GCC_JBIST_MODE_DLL_CLK_EXT2_MUX_SEL_BMSK                                                   0x180
#define HWIO_GCC_JBIST_MODE_DLL_CLK_EXT2_MUX_SEL_SHFT                                                     0x7
#define HWIO_GCC_JBIST_MODE_DLL_CLK_EXT1_MUX_SEL_BMSK                                                    0x60
#define HWIO_GCC_JBIST_MODE_DLL_CLK_EXT1_MUX_SEL_SHFT                                                     0x5
#define HWIO_GCC_JBIST_MODE_PLL_LOCK_DET_BMSK                                                            0x10
#define HWIO_GCC_JBIST_MODE_PLL_LOCK_DET_SHFT                                                             0x4
#define HWIO_GCC_JBIST_MODE_START_MEAS_BMSK                                                               0x8
#define HWIO_GCC_JBIST_MODE_START_MEAS_SHFT                                                               0x3
#define HWIO_GCC_JBIST_MODE_JBIST_TEST_BMSK                                                               0x4
#define HWIO_GCC_JBIST_MODE_JBIST_TEST_SHFT                                                               0x2
#define HWIO_GCC_JBIST_MODE_RESET_N_BMSK                                                                  0x2
#define HWIO_GCC_JBIST_MODE_RESET_N_SHFT                                                                  0x1
#define HWIO_GCC_JBIST_MODE_SLEEP_N_BMSK                                                                  0x1
#define HWIO_GCC_JBIST_MODE_SLEEP_N_SHFT                                                                  0x0

#define HWIO_GCC_JBIST_CONFIG_CTL_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00080004)
#define HWIO_GCC_JBIST_CONFIG_CTL_RMSK                                                             0xffffffff
#define HWIO_GCC_JBIST_CONFIG_CTL_IN          \
        in_dword(HWIO_GCC_JBIST_CONFIG_CTL_ADDR)
#define HWIO_GCC_JBIST_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_JBIST_CONFIG_CTL_ADDR, m)
#define HWIO_GCC_JBIST_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_GCC_JBIST_CONFIG_CTL_ADDR,v)
#define HWIO_GCC_JBIST_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_JBIST_CONFIG_CTL_ADDR,m,v,HWIO_GCC_JBIST_CONFIG_CTL_IN)
#define HWIO_GCC_JBIST_CONFIG_CTL_JBIST_CONFIG_CTL_BMSK                                            0xffffffff
#define HWIO_GCC_JBIST_CONFIG_CTL_JBIST_CONFIG_CTL_SHFT                                                   0x0

#define HWIO_GCC_JBIST_USER_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00080008)
#define HWIO_GCC_JBIST_USER_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_JBIST_USER_CTL_IN          \
        in_dword(HWIO_GCC_JBIST_USER_CTL_ADDR)
#define HWIO_GCC_JBIST_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_JBIST_USER_CTL_ADDR, m)
#define HWIO_GCC_JBIST_USER_CTL_OUT(v)      \
        out_dword(HWIO_GCC_JBIST_USER_CTL_ADDR,v)
#define HWIO_GCC_JBIST_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_JBIST_USER_CTL_ADDR,m,v,HWIO_GCC_JBIST_USER_CTL_IN)
#define HWIO_GCC_JBIST_USER_CTL_JBIST_USER_CTL_BMSK                                                0xffffffff
#define HWIO_GCC_JBIST_USER_CTL_JBIST_USER_CTL_SHFT                                                       0x0

#define HWIO_GCC_JBIST_USER_CTL_U_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0008000c)
#define HWIO_GCC_JBIST_USER_CTL_U_RMSK                                                             0xffffffff
#define HWIO_GCC_JBIST_USER_CTL_U_IN          \
        in_dword(HWIO_GCC_JBIST_USER_CTL_U_ADDR)
#define HWIO_GCC_JBIST_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_GCC_JBIST_USER_CTL_U_ADDR, m)
#define HWIO_GCC_JBIST_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_GCC_JBIST_USER_CTL_U_ADDR,v)
#define HWIO_GCC_JBIST_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_JBIST_USER_CTL_U_ADDR,m,v,HWIO_GCC_JBIST_USER_CTL_U_IN)
#define HWIO_GCC_JBIST_USER_CTL_U_JBIST_USER_CTL_U_BMSK                                            0xffffffff
#define HWIO_GCC_JBIST_USER_CTL_U_JBIST_USER_CTL_U_SHFT                                                   0x0

#define HWIO_GCC_JBIST_TEST_CTL_ADDR                                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00080010)
#define HWIO_GCC_JBIST_TEST_CTL_RMSK                                                               0xffffffff
#define HWIO_GCC_JBIST_TEST_CTL_IN          \
        in_dword(HWIO_GCC_JBIST_TEST_CTL_ADDR)
#define HWIO_GCC_JBIST_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_GCC_JBIST_TEST_CTL_ADDR, m)
#define HWIO_GCC_JBIST_TEST_CTL_OUT(v)      \
        out_dword(HWIO_GCC_JBIST_TEST_CTL_ADDR,v)
#define HWIO_GCC_JBIST_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_JBIST_TEST_CTL_ADDR,m,v,HWIO_GCC_JBIST_TEST_CTL_IN)
#define HWIO_GCC_JBIST_TEST_CTL_JBIST_TEST_CTL_BMSK                                                0xffffffff
#define HWIO_GCC_JBIST_TEST_CTL_JBIST_TEST_CTL_SHFT                                                       0x0

#define HWIO_GCC_JBIST_STATUS_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00080014)
#define HWIO_GCC_JBIST_STATUS_RMSK                                                                 0xffffffff
#define HWIO_GCC_JBIST_STATUS_IN          \
        in_dword(HWIO_GCC_JBIST_STATUS_ADDR)
#define HWIO_GCC_JBIST_STATUS_INM(m)      \
        in_dword_masked(HWIO_GCC_JBIST_STATUS_ADDR, m)
#define HWIO_GCC_JBIST_STATUS_JBIST_STATUS_BMSK                                                    0xffffffff
#define HWIO_GCC_JBIST_STATUS_JBIST_STATUS_SHFT                                                           0x0

#define HWIO_GCC_JBIST_MEAS_DONE_ADDR                                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00080018)
#define HWIO_GCC_JBIST_MEAS_DONE_RMSK                                                              0xffffffff
#define HWIO_GCC_JBIST_MEAS_DONE_IN          \
        in_dword(HWIO_GCC_JBIST_MEAS_DONE_ADDR)
#define HWIO_GCC_JBIST_MEAS_DONE_INM(m)      \
        in_dword_masked(HWIO_GCC_JBIST_MEAS_DONE_ADDR, m)
#define HWIO_GCC_JBIST_MEAS_DONE_OUT(v)      \
        out_dword(HWIO_GCC_JBIST_MEAS_DONE_ADDR,v)
#define HWIO_GCC_JBIST_MEAS_DONE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_JBIST_MEAS_DONE_ADDR,m,v,HWIO_GCC_JBIST_MEAS_DONE_IN)
#define HWIO_GCC_JBIST_MEAS_DONE_RESERVE_BITS31_1_BMSK                                             0xfffffffe
#define HWIO_GCC_JBIST_MEAS_DONE_RESERVE_BITS31_1_SHFT                                                    0x1
#define HWIO_GCC_JBIST_MEAS_DONE_JBIST_DATA_STREAM_RDY_BMSK                                               0x1
#define HWIO_GCC_JBIST_MEAS_DONE_JBIST_DATA_STREAM_RDY_SHFT                                               0x0

#define HWIO_GCC_GLOBAL_EN_ADDR                                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0008f000)
#define HWIO_GCC_GLOBAL_EN_RMSK                                                                    0xffffffff
#define HWIO_GCC_GLOBAL_EN_IN          \
        in_dword(HWIO_GCC_GLOBAL_EN_ADDR)
#define HWIO_GCC_GLOBAL_EN_INM(m)      \
        in_dword_masked(HWIO_GCC_GLOBAL_EN_ADDR, m)
#define HWIO_GCC_GLOBAL_EN_OUT(v)      \
        out_dword(HWIO_GCC_GLOBAL_EN_ADDR,v)
#define HWIO_GCC_GLOBAL_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GLOBAL_EN_ADDR,m,v,HWIO_GCC_GLOBAL_EN_IN)
#define HWIO_GCC_GLOBAL_EN_SPARE_ENABLE_BMSK                                                       0xffff0000
#define HWIO_GCC_GLOBAL_EN_SPARE_ENABLE_SHFT                                                             0x10
#define HWIO_GCC_GLOBAL_EN_CDBGPWRUPREQ_BMSK                                                           0x8000
#define HWIO_GCC_GLOBAL_EN_CDBGPWRUPREQ_SHFT                                                              0xf
#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_7_BMSK                                                           0x4000
#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_7_SHFT                                                              0xe
#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_6_BMSK                                                           0x2000
#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_6_SHFT                                                              0xd
#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_5_BMSK                                                           0x1000
#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_5_SHFT                                                              0xc
#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_4_BMSK                                                            0x800
#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_4_SHFT                                                              0xb
#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_3_BMSK                                                            0x400
#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_3_SHFT                                                              0xa
#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_2_BMSK                                                            0x200
#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_2_SHFT                                                              0x9
#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_1_BMSK                                                            0x100
#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_1_SHFT                                                              0x8
#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_0_BMSK                                                             0x80
#define HWIO_GCC_GLOBAL_EN_MEM_ENABLE_0_SHFT                                                              0x7
#define HWIO_GCC_GLOBAL_EN_REST_ENABLE_BMSK                                                              0x40
#define HWIO_GCC_GLOBAL_EN_REST_ENABLE_SHFT                                                               0x6
#define HWIO_GCC_GLOBAL_EN_PERIPHERALS_ENABLE_BMSK                                                       0x20
#define HWIO_GCC_GLOBAL_EN_PERIPHERALS_ENABLE_SHFT                                                        0x5
#define HWIO_GCC_GLOBAL_EN_CENTER_ENABLE_BMSK                                                            0x10
#define HWIO_GCC_GLOBAL_EN_CENTER_ENABLE_SHFT                                                             0x4
#define HWIO_GCC_GLOBAL_EN_SOUTH_ENABLE_BMSK                                                              0x8
#define HWIO_GCC_GLOBAL_EN_SOUTH_ENABLE_SHFT                                                              0x3
#define HWIO_GCC_GLOBAL_EN_NORTH_ENABLE_BMSK                                                              0x4
#define HWIO_GCC_GLOBAL_EN_NORTH_ENABLE_SHFT                                                              0x2
#define HWIO_GCC_GLOBAL_EN_WEST_ENABLE_BMSK                                                               0x2
#define HWIO_GCC_GLOBAL_EN_WEST_ENABLE_SHFT                                                               0x1
#define HWIO_GCC_GLOBAL_EN_EAST_ENABLE_BMSK                                                               0x1
#define HWIO_GCC_GLOBAL_EN_EAST_ENABLE_SHFT                                                               0x0

#define HWIO_GCC_CAM_CC_GDSCR_ADDR                                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00006100)
#define HWIO_GCC_CAM_CC_GDSCR_RMSK                                                                 0xffffffff
#define HWIO_GCC_CAM_CC_GDSCR_IN          \
        in_dword(HWIO_GCC_CAM_CC_GDSCR_ADDR)
#define HWIO_GCC_CAM_CC_GDSCR_INM(m)      \
        in_dword_masked(HWIO_GCC_CAM_CC_GDSCR_ADDR, m)
#define HWIO_GCC_CAM_CC_GDSCR_OUT(v)      \
        out_dword(HWIO_GCC_CAM_CC_GDSCR_ADDR,v)
#define HWIO_GCC_CAM_CC_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_CAM_CC_GDSCR_ADDR,m,v,HWIO_GCC_CAM_CC_GDSCR_IN)
#define HWIO_GCC_CAM_CC_GDSCR_SECURE_BUS_BMSK                                                      0xffffffff
#define HWIO_GCC_CAM_CC_GDSCR_SECURE_BUS_SHFT                                                             0x0

#define HWIO_GCC_WCSS_MISC_ADDR                                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00011100)
#define HWIO_GCC_WCSS_MISC_RMSK                                                                           0x3
#define HWIO_GCC_WCSS_MISC_IN          \
        in_dword(HWIO_GCC_WCSS_MISC_ADDR)
#define HWIO_GCC_WCSS_MISC_INM(m)      \
        in_dword_masked(HWIO_GCC_WCSS_MISC_ADDR, m)
#define HWIO_GCC_WCSS_MISC_OUT(v)      \
        out_dword(HWIO_GCC_WCSS_MISC_ADDR,v)
#define HWIO_GCC_WCSS_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_WCSS_MISC_ADDR,m,v,HWIO_GCC_WCSS_MISC_IN)
#define HWIO_GCC_WCSS_MISC_WCSS_SHDREG_SW_ARES_BMSK                                                       0x2
#define HWIO_GCC_WCSS_MISC_WCSS_SHDREG_SW_ARES_SHFT                                                       0x1
#define HWIO_GCC_WCSS_MISC_WCSS_DBG_SW_ARES_BMSK                                                          0x1
#define HWIO_GCC_WCSS_MISC_WCSS_DBG_SW_ARES_SHFT                                                          0x0

#define HWIO_GCC_GPLL0_CONFIG_CTL_FUSE_REG_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00000100)
#define HWIO_GCC_GPLL0_CONFIG_CTL_FUSE_REG_RMSK                                                    0xffffffff
#define HWIO_GCC_GPLL0_CONFIG_CTL_FUSE_REG_IN          \
        in_dword(HWIO_GCC_GPLL0_CONFIG_CTL_FUSE_REG_ADDR)
#define HWIO_GCC_GPLL0_CONFIG_CTL_FUSE_REG_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_CONFIG_CTL_FUSE_REG_ADDR, m)
#define HWIO_GCC_GPLL0_CONFIG_CTL_FUSE_REG_FUSE_BITS_BMSK                                          0xffffffff
#define HWIO_GCC_GPLL0_CONFIG_CTL_FUSE_REG_FUSE_BITS_SHFT                                                 0x0

#define HWIO_GCC_GPLL0_CONFIG_CTL_U_FUSE_REG_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00000104)
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_FUSE_REG_RMSK                                                  0xffffffff
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_FUSE_REG_IN          \
        in_dword(HWIO_GCC_GPLL0_CONFIG_CTL_U_FUSE_REG_ADDR)
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_FUSE_REG_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_CONFIG_CTL_U_FUSE_REG_ADDR, m)
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_FUSE_REG_FUSE_BITS_BMSK                                        0xffffffff
#define HWIO_GCC_GPLL0_CONFIG_CTL_U_FUSE_REG_FUSE_BITS_SHFT                                               0x0

#define HWIO_GCC_GPLL0_TEST_CTL_FUSE_REG_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00000108)
#define HWIO_GCC_GPLL0_TEST_CTL_FUSE_REG_RMSK                                                      0xffffffff
#define HWIO_GCC_GPLL0_TEST_CTL_FUSE_REG_IN          \
        in_dword(HWIO_GCC_GPLL0_TEST_CTL_FUSE_REG_ADDR)
#define HWIO_GCC_GPLL0_TEST_CTL_FUSE_REG_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_TEST_CTL_FUSE_REG_ADDR, m)
#define HWIO_GCC_GPLL0_TEST_CTL_FUSE_REG_FUSE_BITS_BMSK                                            0xffffffff
#define HWIO_GCC_GPLL0_TEST_CTL_FUSE_REG_FUSE_BITS_SHFT                                                   0x0

#define HWIO_GCC_GPLL0_TEST_CTL_U_FUSE_REG_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0000010c)
#define HWIO_GCC_GPLL0_TEST_CTL_U_FUSE_REG_RMSK                                                    0xffffffff
#define HWIO_GCC_GPLL0_TEST_CTL_U_FUSE_REG_IN          \
        in_dword(HWIO_GCC_GPLL0_TEST_CTL_U_FUSE_REG_ADDR)
#define HWIO_GCC_GPLL0_TEST_CTL_U_FUSE_REG_INM(m)      \
        in_dword_masked(HWIO_GCC_GPLL0_TEST_CTL_U_FUSE_REG_ADDR, m)
#define HWIO_GCC_GPLL0_TEST_CTL_U_FUSE_REG_FUSE_BITS_BMSK                                          0xffffffff
#define HWIO_GCC_GPLL0_TEST_CTL_U_FUSE_REG_FUSE_BITS_SHFT                                                 0x0

#define HWIO_GCC_PLL0_CDIVR_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00000114)
#define HWIO_GCC_PLL0_CDIVR_RMSK                                                                          0x3
#define HWIO_GCC_PLL0_CDIVR_IN          \
        in_dword(HWIO_GCC_PLL0_CDIVR_ADDR)
#define HWIO_GCC_PLL0_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_PLL0_CDIVR_ADDR, m)
#define HWIO_GCC_PLL0_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_PLL0_CDIVR_ADDR,v)
#define HWIO_GCC_PLL0_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PLL0_CDIVR_ADDR,m,v,HWIO_GCC_PLL0_CDIVR_IN)
#define HWIO_GCC_PLL0_CDIVR_CLK_DIV_BMSK                                                                  0x3
#define HWIO_GCC_PLL0_CDIVR_CLK_DIV_SHFT                                                                  0x0

#define HWIO_GCC_PLL1_CDIVR_ADDR                                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00001114)
#define HWIO_GCC_PLL1_CDIVR_RMSK                                                                          0x3
#define HWIO_GCC_PLL1_CDIVR_IN          \
        in_dword(HWIO_GCC_PLL1_CDIVR_ADDR)
#define HWIO_GCC_PLL1_CDIVR_INM(m)      \
        in_dword_masked(HWIO_GCC_PLL1_CDIVR_ADDR, m)
#define HWIO_GCC_PLL1_CDIVR_OUT(v)      \
        out_dword(HWIO_GCC_PLL1_CDIVR_ADDR,v)
#define HWIO_GCC_PLL1_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PLL1_CDIVR_ADDR,m,v,HWIO_GCC_PLL1_CDIVR_IN)
#define HWIO_GCC_PLL1_CDIVR_CLK_DIV_BMSK                                                                  0x3
#define HWIO_GCC_PLL1_CDIVR_CLK_DIV_SHFT                                                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00094000)
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_RMSK                                                       0x7ff
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL11_BMSK                                                0x400
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL11_SHFT                                                  0xa
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL10_BMSK                                                0x200
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL10_SHFT                                                  0x9
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL9_BMSK                                                 0x100
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL9_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL8_BMSK                                                  0x80
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL8_SHFT                                                   0x7
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL7_BMSK                                                  0x40
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL7_SHFT                                                   0x6
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL6_BMSK                                                  0x20
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL6_SHFT                                                   0x5
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL5_BMSK                                                  0x10
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL5_SHFT                                                   0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL4_BMSK                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL4_SHFT                                                   0x3
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL2_3_BMSK                                                 0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL2_3_SHFT                                                 0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL1_BMSK                                                   0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL1_SHFT                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL0_BMSK                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_GPLL0_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00091004)
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_RMSK                                                       0x7ff
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL11_BMSK                                                0x400
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL11_SHFT                                                  0xa
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL10_BMSK                                                0x200
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL10_SHFT                                                  0x9
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL9_BMSK                                                 0x100
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL9_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL8_BMSK                                                  0x80
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL8_SHFT                                                   0x7
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL7_BMSK                                                  0x40
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL7_SHFT                                                   0x6
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL6_BMSK                                                  0x20
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL6_SHFT                                                   0x5
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL5_BMSK                                                  0x10
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL5_SHFT                                                   0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL4_BMSK                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL4_SHFT                                                   0x3
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL2_3_BMSK                                                 0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL2_3_SHFT                                                 0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL1_BMSK                                                   0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL1_SHFT                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL0_BMSK                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_GPLL0_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00091008)
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_RMSK                                                       0x7ff
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL11_BMSK                                                0x400
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL11_SHFT                                                  0xa
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL10_BMSK                                                0x200
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL10_SHFT                                                  0x9
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL9_BMSK                                                 0x100
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL9_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL8_BMSK                                                  0x80
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL8_SHFT                                                   0x7
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL7_BMSK                                                  0x40
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL7_SHFT                                                   0x6
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL6_BMSK                                                  0x20
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL6_SHFT                                                   0x5
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL5_BMSK                                                  0x10
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL5_SHFT                                                   0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL4_BMSK                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL4_SHFT                                                   0x3
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL2_3_BMSK                                                 0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL2_3_SHFT                                                 0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL1_BMSK                                                   0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL1_SHFT                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL0_BMSK                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_GPLL0_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0009100c)
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_RMSK                                                       0x7ff
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL11_BMSK                                                0x400
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL11_SHFT                                                  0xa
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL10_BMSK                                                0x200
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL10_SHFT                                                  0x9
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL9_BMSK                                                 0x100
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL9_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL8_BMSK                                                  0x80
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL8_SHFT                                                   0x7
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL7_BMSK                                                  0x40
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL7_SHFT                                                   0x6
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL6_BMSK                                                  0x20
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL6_SHFT                                                   0x5
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL5_BMSK                                                  0x10
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL5_SHFT                                                   0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL4_BMSK                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL4_SHFT                                                   0x3
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL2_3_BMSK                                                 0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL2_3_SHFT                                                 0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL1_BMSK                                                   0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL1_SHFT                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL0_BMSK                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_GPLL0_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00091010)
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_RMSK                                                       0x7ff
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL11_BMSK                                                0x400
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL11_SHFT                                                  0xa
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL10_BMSK                                                0x200
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL10_SHFT                                                  0x9
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL9_BMSK                                                 0x100
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL9_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL8_BMSK                                                  0x80
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL8_SHFT                                                   0x7
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL7_BMSK                                                  0x40
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL7_SHFT                                                   0x6
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL6_BMSK                                                  0x20
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL6_SHFT                                                   0x5
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL5_BMSK                                                  0x10
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL5_SHFT                                                   0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL4_BMSK                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL4_SHFT                                                   0x3
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL2_3_BMSK                                                 0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL2_3_SHFT                                                 0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL1_BMSK                                                   0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL1_SHFT                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL0_BMSK                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_GPLL0_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00091014)
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_RMSK                                                       0x7ff
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL11_BMSK                                                0x400
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL11_SHFT                                                  0xa
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL10_BMSK                                                0x200
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL10_SHFT                                                  0x9
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL9_BMSK                                                 0x100
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL9_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL8_BMSK                                                  0x80
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL8_SHFT                                                   0x7
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL7_BMSK                                                  0x40
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL7_SHFT                                                   0x6
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL6_BMSK                                                  0x20
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL6_SHFT                                                   0x5
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL5_BMSK                                                  0x10
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL5_SHFT                                                   0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL4_BMSK                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL4_SHFT                                                   0x3
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL2_3_BMSK                                                 0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL2_3_SHFT                                                 0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL1_BMSK                                                   0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL1_SHFT                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL0_BMSK                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_GPLL0_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00091018)
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_RMSK                                                       0x7ff
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL11_BMSK                                                0x400
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL11_SHFT                                                  0xa
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL10_BMSK                                                0x200
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL10_SHFT                                                  0x9
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL9_BMSK                                                 0x100
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL9_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL8_BMSK                                                  0x80
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL8_SHFT                                                   0x7
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL7_BMSK                                                  0x40
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL7_SHFT                                                   0x6
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL6_BMSK                                                  0x20
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL6_SHFT                                                   0x5
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL5_BMSK                                                  0x10
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL5_SHFT                                                   0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL4_BMSK                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL4_SHFT                                                   0x3
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL2_3_BMSK                                                 0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL2_3_SHFT                                                 0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL1_BMSK                                                   0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL1_SHFT                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL0_BMSK                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_GPLL0_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0009101c)
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_RMSK                                                       0x7ff
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL11_BMSK                                                0x400
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL11_SHFT                                                  0xa
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL10_BMSK                                                0x200
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL10_SHFT                                                  0x9
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL9_BMSK                                                 0x100
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL9_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL8_BMSK                                                  0x80
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL8_SHFT                                                   0x7
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL7_BMSK                                                  0x40
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL7_SHFT                                                   0x6
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL6_BMSK                                                  0x20
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL6_SHFT                                                   0x5
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL5_BMSK                                                  0x10
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL5_SHFT                                                   0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL4_BMSK                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL4_SHFT                                                   0x3
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL2_3_BMSK                                                 0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL2_3_SHFT                                                 0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL1_BMSK                                                   0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL1_SHFT                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL0_BMSK                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_GPLL0_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00091020)
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_RMSK                                                       0x7ff
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL11_BMSK                                                0x400
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL11_SHFT                                                  0xa
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL10_BMSK                                                0x200
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL10_SHFT                                                  0x9
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL9_BMSK                                                 0x100
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL9_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL8_BMSK                                                  0x80
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL8_SHFT                                                   0x7
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL7_BMSK                                                  0x40
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL7_SHFT                                                   0x6
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL6_BMSK                                                  0x20
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL6_SHFT                                                   0x5
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL5_BMSK                                                  0x10
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL5_SHFT                                                   0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL4_BMSK                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL4_SHFT                                                   0x3
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL2_3_BMSK                                                 0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL2_3_SHFT                                                 0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL1_BMSK                                                   0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL1_SHFT                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL0_BMSK                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_GPLL0_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x00091024)
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_RMSK                                                       0x7ff
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL11_BMSK                                                0x400
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL11_SHFT                                                  0xa
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL10_BMSK                                                0x200
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL10_SHFT                                                  0x9
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL9_BMSK                                                 0x100
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL9_SHFT                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL8_BMSK                                                  0x80
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL8_SHFT                                                   0x7
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL7_BMSK                                                  0x40
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL7_SHFT                                                   0x6
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL6_BMSK                                                  0x20
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL6_SHFT                                                   0x5
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL5_BMSK                                                  0x10
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL5_SHFT                                                   0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL4_BMSK                                                   0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL4_SHFT                                                   0x3
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL2_3_BMSK                                                 0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL2_3_SHFT                                                 0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL1_BMSK                                                   0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL1_SHFT                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL0_BMSK                                                   0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_GPLL0_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00091028)
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_RMSK                                                      0x7ff
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL11_BMSK                                               0x400
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL11_SHFT                                                 0xa
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL10_BMSK                                               0x200
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL10_SHFT                                                 0x9
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL9_BMSK                                                0x100
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL9_SHFT                                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL8_BMSK                                                 0x80
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL8_SHFT                                                  0x7
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL7_BMSK                                                 0x40
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL7_SHFT                                                  0x6
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL6_BMSK                                                 0x20
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL6_SHFT                                                  0x5
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL5_BMSK                                                 0x10
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL5_SHFT                                                  0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL4_BMSK                                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL4_SHFT                                                  0x3
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL2_3_BMSK                                                0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL2_3_SHFT                                                0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0009102c)
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_RMSK                                                      0x7ff
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL11_BMSK                                               0x400
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL11_SHFT                                                 0xa
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL10_BMSK                                               0x200
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL10_SHFT                                                 0x9
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL9_BMSK                                                0x100
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL9_SHFT                                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL8_BMSK                                                 0x80
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL8_SHFT                                                  0x7
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL7_BMSK                                                 0x40
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL7_SHFT                                                  0x6
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL6_BMSK                                                 0x20
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL6_SHFT                                                  0x5
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL5_BMSK                                                 0x10
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL5_SHFT                                                  0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL4_BMSK                                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL4_SHFT                                                  0x3
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL2_3_BMSK                                                0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL2_3_SHFT                                                0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00091030)
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_RMSK                                                      0x7ff
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL11_BMSK                                               0x400
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL11_SHFT                                                 0xa
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL10_BMSK                                               0x200
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL10_SHFT                                                 0x9
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL9_BMSK                                                0x100
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL9_SHFT                                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL8_BMSK                                                 0x80
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL8_SHFT                                                  0x7
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL7_BMSK                                                 0x40
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL7_SHFT                                                  0x6
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL6_BMSK                                                 0x20
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL6_SHFT                                                  0x5
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL5_BMSK                                                 0x10
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL5_SHFT                                                  0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL4_BMSK                                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL4_SHFT                                                  0x3
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL2_3_BMSK                                                0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL2_3_SHFT                                                0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00091034)
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_RMSK                                                      0x7ff
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL11_BMSK                                               0x400
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL11_SHFT                                                 0xa
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL10_BMSK                                               0x200
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL10_SHFT                                                 0x9
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL9_BMSK                                                0x100
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL9_SHFT                                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL8_BMSK                                                 0x80
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL8_SHFT                                                  0x7
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL7_BMSK                                                 0x40
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL7_SHFT                                                  0x6
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL6_BMSK                                                 0x20
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL6_SHFT                                                  0x5
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL5_BMSK                                                 0x10
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL5_SHFT                                                  0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL4_BMSK                                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL4_SHFT                                                  0x3
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL2_3_BMSK                                                0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL2_3_SHFT                                                0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00091038)
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_RMSK                                                      0x7ff
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL11_BMSK                                               0x400
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL11_SHFT                                                 0xa
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL10_BMSK                                               0x200
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL10_SHFT                                                 0x9
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL9_BMSK                                                0x100
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL9_SHFT                                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL8_BMSK                                                 0x80
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL8_SHFT                                                  0x7
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL7_BMSK                                                 0x40
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL7_SHFT                                                  0x6
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL6_BMSK                                                 0x20
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL6_SHFT                                                  0x5
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL5_BMSK                                                 0x10
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL5_SHFT                                                  0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL4_BMSK                                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL4_SHFT                                                  0x3
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL2_3_BMSK                                                0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL2_3_SHFT                                                0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0009103c)
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_RMSK                                                      0x7ff
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL11_BMSK                                               0x400
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL11_SHFT                                                 0xa
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL10_BMSK                                               0x200
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL10_SHFT                                                 0x9
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL9_BMSK                                                0x100
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL9_SHFT                                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL8_BMSK                                                 0x80
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL8_SHFT                                                  0x7
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL7_BMSK                                                 0x40
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL7_SHFT                                                  0x6
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL6_BMSK                                                 0x20
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL6_SHFT                                                  0x5
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL5_BMSK                                                 0x10
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL5_SHFT                                                  0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL4_BMSK                                                  0x8
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL4_SHFT                                                  0x3
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL2_3_BMSK                                                0x4
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL2_3_SHFT                                                0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00091100)
#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_RMSK                                                         0x1f
#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_IN          \
        in_dword(HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_ADDR)
#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_ADDR, m)
#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_FSM_STATE_BMSK                                               0x1f
#define HWIO_GCC_RPMH_SYS_NOC_INTERFACE_FSM_FSM_STATE_SHFT                                                0x0

#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00092004)
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00092008)
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0009200c)
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00092010)
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00092014)
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00092018)
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0009201c)
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00092020)
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00092024)
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00092028)
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009202c)
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00092030)
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00092034)
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00092038)
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009203c)
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00092040)
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00092100)
#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_RMSK                                                            0x1f
#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_IN          \
        in_dword(HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_ADDR)
#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_ADDR, m)
#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_FSM_STATE_BMSK                                                  0x1f
#define HWIO_GCC_RPMH_CNOC_INTERFACE_FSM_FSM_STATE_SHFT                                                   0x0

#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00093004)
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_RMSK                                                           0x7ff
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL11_BMSK                                                    0x400
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL11_SHFT                                                      0xa
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL10_BMSK                                                    0x200
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL10_SHFT                                                      0x9
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL9_BMSK                                                     0x100
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL9_SHFT                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL8_BMSK                                                      0x80
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL8_SHFT                                                       0x7
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL7_BMSK                                                      0x40
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL7_SHFT                                                       0x6
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL6_BMSK                                                      0x20
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL6_SHFT                                                       0x5
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL5_BMSK                                                      0x10
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL5_SHFT                                                       0x4
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL4_BMSK                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL4_SHFT                                                       0x3
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL2_3_BMSK                                                     0x4
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL2_3_SHFT                                                     0x2
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00093008)
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_RMSK                                                           0x7ff
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL11_BMSK                                                    0x400
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL11_SHFT                                                      0xa
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL10_BMSK                                                    0x200
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL10_SHFT                                                      0x9
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL9_BMSK                                                     0x100
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL9_SHFT                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL8_BMSK                                                      0x80
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL8_SHFT                                                       0x7
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL7_BMSK                                                      0x40
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL7_SHFT                                                       0x6
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL6_BMSK                                                      0x20
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL6_SHFT                                                       0x5
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL5_BMSK                                                      0x10
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL5_SHFT                                                       0x4
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL4_BMSK                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL4_SHFT                                                       0x3
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL2_3_BMSK                                                     0x4
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL2_3_SHFT                                                     0x2
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0009300c)
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_RMSK                                                           0x7ff
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL11_BMSK                                                    0x400
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL11_SHFT                                                      0xa
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL10_BMSK                                                    0x200
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL10_SHFT                                                      0x9
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL9_BMSK                                                     0x100
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL9_SHFT                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL8_BMSK                                                      0x80
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL8_SHFT                                                       0x7
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL7_BMSK                                                      0x40
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL7_SHFT                                                       0x6
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL6_BMSK                                                      0x20
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL6_SHFT                                                       0x5
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL5_BMSK                                                      0x10
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL5_SHFT                                                       0x4
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL4_BMSK                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL4_SHFT                                                       0x3
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL2_3_BMSK                                                     0x4
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL2_3_SHFT                                                     0x2
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00093010)
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_RMSK                                                           0x7ff
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL11_BMSK                                                    0x400
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL11_SHFT                                                      0xa
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL10_BMSK                                                    0x200
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL10_SHFT                                                      0x9
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL9_BMSK                                                     0x100
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL9_SHFT                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL8_BMSK                                                      0x80
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL8_SHFT                                                       0x7
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL7_BMSK                                                      0x40
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL7_SHFT                                                       0x6
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL6_BMSK                                                      0x20
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL6_SHFT                                                       0x5
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL5_BMSK                                                      0x10
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL5_SHFT                                                       0x4
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL4_BMSK                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL4_SHFT                                                       0x3
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL2_3_BMSK                                                     0x4
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL2_3_SHFT                                                     0x2
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00093014)
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_RMSK                                                           0x7ff
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL11_BMSK                                                    0x400
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL11_SHFT                                                      0xa
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL10_BMSK                                                    0x200
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL10_SHFT                                                      0x9
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL9_BMSK                                                     0x100
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL9_SHFT                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL8_BMSK                                                      0x80
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL8_SHFT                                                       0x7
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL7_BMSK                                                      0x40
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL7_SHFT                                                       0x6
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL6_BMSK                                                      0x20
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL6_SHFT                                                       0x5
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL5_BMSK                                                      0x10
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL5_SHFT                                                       0x4
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL4_BMSK                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL4_SHFT                                                       0x3
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL2_3_BMSK                                                     0x4
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL2_3_SHFT                                                     0x2
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00093018)
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_RMSK                                                           0x7ff
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL11_BMSK                                                    0x400
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL11_SHFT                                                      0xa
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL10_BMSK                                                    0x200
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL10_SHFT                                                      0x9
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL9_BMSK                                                     0x100
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL9_SHFT                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL8_BMSK                                                      0x80
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL8_SHFT                                                       0x7
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL7_BMSK                                                      0x40
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL7_SHFT                                                       0x6
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL6_BMSK                                                      0x20
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL6_SHFT                                                       0x5
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL5_BMSK                                                      0x10
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL5_SHFT                                                       0x4
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL4_BMSK                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL4_SHFT                                                       0x3
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL2_3_BMSK                                                     0x4
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL2_3_SHFT                                                     0x2
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0009301c)
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_RMSK                                                           0x7ff
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL11_BMSK                                                    0x400
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL11_SHFT                                                      0xa
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL10_BMSK                                                    0x200
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL10_SHFT                                                      0x9
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL9_BMSK                                                     0x100
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL9_SHFT                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL8_BMSK                                                      0x80
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL8_SHFT                                                       0x7
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL7_BMSK                                                      0x40
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL7_SHFT                                                       0x6
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL6_BMSK                                                      0x20
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL6_SHFT                                                       0x5
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL5_BMSK                                                      0x10
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL5_SHFT                                                       0x4
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL4_BMSK                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL4_SHFT                                                       0x3
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL2_3_BMSK                                                     0x4
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL2_3_SHFT                                                     0x2
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00093020)
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_RMSK                                                           0x7ff
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL11_BMSK                                                    0x400
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL11_SHFT                                                      0xa
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL10_BMSK                                                    0x200
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL10_SHFT                                                      0x9
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL9_BMSK                                                     0x100
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL9_SHFT                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL8_BMSK                                                      0x80
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL8_SHFT                                                       0x7
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL7_BMSK                                                      0x40
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL7_SHFT                                                       0x6
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL6_BMSK                                                      0x20
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL6_SHFT                                                       0x5
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL5_BMSK                                                      0x10
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL5_SHFT                                                       0x4
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL4_BMSK                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL4_SHFT                                                       0x3
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL2_3_BMSK                                                     0x4
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL2_3_SHFT                                                     0x2
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00093024)
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_RMSK                                                           0x7ff
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL11_BMSK                                                    0x400
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL11_SHFT                                                      0xa
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL10_BMSK                                                    0x200
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL10_SHFT                                                      0x9
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL9_BMSK                                                     0x100
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL9_SHFT                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL8_BMSK                                                      0x80
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL8_SHFT                                                       0x7
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL7_BMSK                                                      0x40
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL7_SHFT                                                       0x6
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL6_BMSK                                                      0x20
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL6_SHFT                                                       0x5
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL5_BMSK                                                      0x10
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL5_SHFT                                                       0x4
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL4_BMSK                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL4_SHFT                                                       0x3
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL2_3_BMSK                                                     0x4
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL2_3_SHFT                                                     0x2
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00093028)
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_RMSK                                                           0x7ff
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL11_BMSK                                                    0x400
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL11_SHFT                                                      0xa
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL10_BMSK                                                    0x200
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL10_SHFT                                                      0x9
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL9_BMSK                                                     0x100
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL9_SHFT                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL8_BMSK                                                      0x80
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL8_SHFT                                                       0x7
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL7_BMSK                                                      0x40
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL7_SHFT                                                       0x6
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL6_BMSK                                                      0x20
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL6_SHFT                                                       0x5
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL5_BMSK                                                      0x10
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL5_SHFT                                                       0x4
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL4_BMSK                                                       0x8
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL4_SHFT                                                       0x3
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL2_3_BMSK                                                     0x4
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL2_3_SHFT                                                     0x2
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0009302c)
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00093030)
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00093034)
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00093038)
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0009303c)
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00093040)
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00093100)
#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_RMSK                                                             0x1f
#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_IN          \
        in_dword(HWIO_GCC_RPMH_IPA_INTERFACE_FSM_ADDR)
#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_IPA_INTERFACE_FSM_ADDR, m)
#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_FSM_STATE_BMSK                                                   0x1f
#define HWIO_GCC_RPMH_IPA_INTERFACE_FSM_FSM_STATE_SHFT                                                    0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b004)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_RMSK                                                 0x7ff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL11_BMSK                                          0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL11_SHFT                                            0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL10_BMSK                                          0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL10_SHFT                                            0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL9_BMSK                                           0x100
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL9_SHFT                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL8_BMSK                                            0x80
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL8_SHFT                                             0x7
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL7_BMSK                                            0x40
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL7_SHFT                                             0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL6_BMSK                                            0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL6_SHFT                                             0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL5_BMSK                                            0x10
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL5_SHFT                                             0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL4_BMSK                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL4_SHFT                                             0x3
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL2_3_BMSK                                           0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL2_3_SHFT                                           0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL1_BMSK                                             0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL1_SHFT                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL0_BMSK                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_GPLL0_SHFT                                             0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b008)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_RMSK                                                 0x7ff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL11_BMSK                                          0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL11_SHFT                                            0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL10_BMSK                                          0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL10_SHFT                                            0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL9_BMSK                                           0x100
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL9_SHFT                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL8_BMSK                                            0x80
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL8_SHFT                                             0x7
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL7_BMSK                                            0x40
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL7_SHFT                                             0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL6_BMSK                                            0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL6_SHFT                                             0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL5_BMSK                                            0x10
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL5_SHFT                                             0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL4_BMSK                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL4_SHFT                                             0x3
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL2_3_BMSK                                           0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL2_3_SHFT                                           0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL1_BMSK                                             0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL1_SHFT                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL0_BMSK                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_GPLL0_SHFT                                             0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b00c)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_RMSK                                                 0x7ff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL11_BMSK                                          0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL11_SHFT                                            0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL10_BMSK                                          0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL10_SHFT                                            0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL9_BMSK                                           0x100
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL9_SHFT                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL8_BMSK                                            0x80
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL8_SHFT                                             0x7
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL7_BMSK                                            0x40
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL7_SHFT                                             0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL6_BMSK                                            0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL6_SHFT                                             0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL5_BMSK                                            0x10
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL5_SHFT                                             0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL4_BMSK                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL4_SHFT                                             0x3
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL2_3_BMSK                                           0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL2_3_SHFT                                           0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL1_BMSK                                             0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL1_SHFT                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL0_BMSK                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_GPLL0_SHFT                                             0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b010)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_RMSK                                                 0x7ff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL11_BMSK                                          0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL11_SHFT                                            0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL10_BMSK                                          0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL10_SHFT                                            0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL9_BMSK                                           0x100
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL9_SHFT                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL8_BMSK                                            0x80
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL8_SHFT                                             0x7
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL7_BMSK                                            0x40
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL7_SHFT                                             0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL6_BMSK                                            0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL6_SHFT                                             0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL5_BMSK                                            0x10
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL5_SHFT                                             0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL4_BMSK                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL4_SHFT                                             0x3
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL2_3_BMSK                                           0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL2_3_SHFT                                           0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL1_BMSK                                             0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL1_SHFT                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL0_BMSK                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_GPLL0_SHFT                                             0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b014)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_RMSK                                                 0x7ff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL11_BMSK                                          0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL11_SHFT                                            0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL10_BMSK                                          0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL10_SHFT                                            0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL9_BMSK                                           0x100
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL9_SHFT                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL8_BMSK                                            0x80
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL8_SHFT                                             0x7
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL7_BMSK                                            0x40
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL7_SHFT                                             0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL6_BMSK                                            0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL6_SHFT                                             0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL5_BMSK                                            0x10
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL5_SHFT                                             0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL4_BMSK                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL4_SHFT                                             0x3
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL2_3_BMSK                                           0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL2_3_SHFT                                           0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL1_BMSK                                             0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL1_SHFT                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL0_BMSK                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_GPLL0_SHFT                                             0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b018)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_RMSK                                                 0x7ff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL11_BMSK                                          0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL11_SHFT                                            0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL10_BMSK                                          0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL10_SHFT                                            0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL9_BMSK                                           0x100
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL9_SHFT                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL8_BMSK                                            0x80
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL8_SHFT                                             0x7
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL7_BMSK                                            0x40
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL7_SHFT                                             0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL6_BMSK                                            0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL6_SHFT                                             0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL5_BMSK                                            0x10
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL5_SHFT                                             0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL4_BMSK                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL4_SHFT                                             0x3
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL2_3_BMSK                                           0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL2_3_SHFT                                           0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL1_BMSK                                             0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL1_SHFT                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL0_BMSK                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_GPLL0_SHFT                                             0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b01c)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_RMSK                                                 0x7ff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL11_BMSK                                          0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL11_SHFT                                            0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL10_BMSK                                          0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL10_SHFT                                            0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL9_BMSK                                           0x100
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL9_SHFT                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL8_BMSK                                            0x80
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL8_SHFT                                             0x7
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL7_BMSK                                            0x40
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL7_SHFT                                             0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL6_BMSK                                            0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL6_SHFT                                             0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL5_BMSK                                            0x10
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL5_SHFT                                             0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL4_BMSK                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL4_SHFT                                             0x3
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL2_3_BMSK                                           0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL2_3_SHFT                                           0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL1_BMSK                                             0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL1_SHFT                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL0_BMSK                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_GPLL0_SHFT                                             0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b020)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_RMSK                                                 0x7ff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL11_BMSK                                          0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL11_SHFT                                            0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL10_BMSK                                          0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL10_SHFT                                            0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL9_BMSK                                           0x100
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL9_SHFT                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL8_BMSK                                            0x80
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL8_SHFT                                             0x7
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL7_BMSK                                            0x40
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL7_SHFT                                             0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL6_BMSK                                            0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL6_SHFT                                             0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL5_BMSK                                            0x10
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL5_SHFT                                             0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL4_BMSK                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL4_SHFT                                             0x3
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL2_3_BMSK                                           0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL2_3_SHFT                                           0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL1_BMSK                                             0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL1_SHFT                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL0_BMSK                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_GPLL0_SHFT                                             0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b024)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_RMSK                                                 0x7ff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL11_BMSK                                          0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL11_SHFT                                            0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL10_BMSK                                          0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL10_SHFT                                            0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL9_BMSK                                           0x100
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL9_SHFT                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL8_BMSK                                            0x80
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL8_SHFT                                             0x7
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL7_BMSK                                            0x40
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL7_SHFT                                             0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL6_BMSK                                            0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL6_SHFT                                             0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL5_BMSK                                            0x10
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL5_SHFT                                             0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL4_BMSK                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL4_SHFT                                             0x3
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL2_3_BMSK                                           0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL2_3_SHFT                                           0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL1_BMSK                                             0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL1_SHFT                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL0_BMSK                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_GPLL0_SHFT                                             0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b028)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_RMSK                                                 0x7ff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL11_BMSK                                          0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL11_SHFT                                            0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL10_BMSK                                          0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL10_SHFT                                            0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL9_BMSK                                           0x100
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL9_SHFT                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL8_BMSK                                            0x80
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL8_SHFT                                             0x7
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL7_BMSK                                            0x40
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL7_SHFT                                             0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL6_BMSK                                            0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL6_SHFT                                             0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL5_BMSK                                            0x10
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL5_SHFT                                             0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL4_BMSK                                             0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL4_SHFT                                             0x3
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL2_3_BMSK                                           0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL2_3_SHFT                                           0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL1_BMSK                                             0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL1_SHFT                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL0_BMSK                                             0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_GPLL0_SHFT                                             0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b02c)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_RMSK                                                0x7ff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL11_BMSK                                         0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL11_SHFT                                           0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL10_BMSK                                         0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL10_SHFT                                           0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL9_BMSK                                          0x100
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL9_SHFT                                            0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL8_BMSK                                           0x80
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL8_SHFT                                            0x7
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL7_BMSK                                           0x40
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL7_SHFT                                            0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL6_BMSK                                           0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL6_SHFT                                            0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL5_BMSK                                           0x10
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL5_SHFT                                            0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL4_BMSK                                            0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL4_SHFT                                            0x3
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL2_3_BMSK                                          0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL2_3_SHFT                                          0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL1_BMSK                                            0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL1_SHFT                                            0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL0_BMSK                                            0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_GPLL0_SHFT                                            0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b030)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_RMSK                                                0x7ff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL11_BMSK                                         0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL11_SHFT                                           0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL10_BMSK                                         0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL10_SHFT                                           0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL9_BMSK                                          0x100
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL9_SHFT                                            0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL8_BMSK                                           0x80
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL8_SHFT                                            0x7
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL7_BMSK                                           0x40
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL7_SHFT                                            0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL6_BMSK                                           0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL6_SHFT                                            0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL5_BMSK                                           0x10
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL5_SHFT                                            0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL4_BMSK                                            0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL4_SHFT                                            0x3
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL2_3_BMSK                                          0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL2_3_SHFT                                          0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL1_BMSK                                            0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL1_SHFT                                            0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL0_BMSK                                            0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_GPLL0_SHFT                                            0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b034)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_RMSK                                                0x7ff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL11_BMSK                                         0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL11_SHFT                                           0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL10_BMSK                                         0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL10_SHFT                                           0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL9_BMSK                                          0x100
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL9_SHFT                                            0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL8_BMSK                                           0x80
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL8_SHFT                                            0x7
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL7_BMSK                                           0x40
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL7_SHFT                                            0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL6_BMSK                                           0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL6_SHFT                                            0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL5_BMSK                                           0x10
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL5_SHFT                                            0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL4_BMSK                                            0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL4_SHFT                                            0x3
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL2_3_BMSK                                          0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL2_3_SHFT                                          0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL1_BMSK                                            0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL1_SHFT                                            0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL0_BMSK                                            0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_GPLL0_SHFT                                            0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b038)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_RMSK                                                0x7ff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL11_BMSK                                         0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL11_SHFT                                           0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL10_BMSK                                         0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL10_SHFT                                           0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL9_BMSK                                          0x100
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL9_SHFT                                            0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL8_BMSK                                           0x80
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL8_SHFT                                            0x7
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL7_BMSK                                           0x40
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL7_SHFT                                            0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL6_BMSK                                           0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL6_SHFT                                            0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL5_BMSK                                           0x10
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL5_SHFT                                            0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL4_BMSK                                            0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL4_SHFT                                            0x3
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL2_3_BMSK                                          0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL2_3_SHFT                                          0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL1_BMSK                                            0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL1_SHFT                                            0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL0_BMSK                                            0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_GPLL0_SHFT                                            0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b03c)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_RMSK                                                0x7ff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL11_BMSK                                         0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL11_SHFT                                           0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL10_BMSK                                         0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL10_SHFT                                           0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL9_BMSK                                          0x100
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL9_SHFT                                            0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL8_BMSK                                           0x80
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL8_SHFT                                            0x7
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL7_BMSK                                           0x40
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL7_SHFT                                            0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL6_BMSK                                           0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL6_SHFT                                            0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL5_BMSK                                           0x10
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL5_SHFT                                            0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL4_BMSK                                            0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL4_SHFT                                            0x3
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL2_3_BMSK                                          0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL2_3_SHFT                                          0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL1_BMSK                                            0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL1_SHFT                                            0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL0_BMSK                                            0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_GPLL0_SHFT                                            0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b040)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_RMSK                                                0x7ff
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL11_BMSK                                         0x400
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL11_SHFT                                           0xa
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL10_BMSK                                         0x200
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL10_SHFT                                           0x9
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL9_BMSK                                          0x100
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL9_SHFT                                            0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL8_BMSK                                           0x80
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL8_SHFT                                            0x7
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL7_BMSK                                           0x40
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL7_SHFT                                            0x6
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL6_BMSK                                           0x20
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL6_SHFT                                            0x5
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL5_BMSK                                           0x10
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL5_SHFT                                            0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL4_BMSK                                            0x8
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL4_SHFT                                            0x3
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL2_3_BMSK                                          0x4
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL2_3_SHFT                                          0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL1_BMSK                                            0x2
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL1_SHFT                                            0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL0_BMSK                                            0x1
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_GPLL0_SHFT                                            0x0

#define HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_ADDR                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x0009b100)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_RMSK                                                   0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_IN          \
        in_dword(HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_ADDR)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_ADDR, m)
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_FSM_STATE_BMSK                                         0x1f
#define HWIO_GCC_RPMH_QUPV3_CORE_2X_INTERFACE_FSM_FSM_STATE_SHFT                                          0x0

#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00094004)
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_RMSK                                                            0x7ff
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL11_BMSK                                                     0x400
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL11_SHFT                                                       0xa
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL10_BMSK                                                     0x200
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL10_SHFT                                                       0x9
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL9_BMSK                                                      0x100
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL9_SHFT                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL8_BMSK                                                       0x80
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL8_SHFT                                                        0x7
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL7_BMSK                                                       0x40
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL7_SHFT                                                        0x6
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL6_BMSK                                                       0x20
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL6_SHFT                                                        0x5
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL5_BMSK                                                       0x10
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL5_SHFT                                                        0x4
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL4_BMSK                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL4_SHFT                                                        0x3
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL2_3_BMSK                                                      0x4
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL2_3_SHFT                                                      0x2
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL1_BMSK                                                        0x2
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL1_SHFT                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL0_BMSK                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_GPLL0_SHFT                                                        0x0

#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00094008)
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_RMSK                                                            0x7ff
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL11_BMSK                                                     0x400
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL11_SHFT                                                       0xa
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL10_BMSK                                                     0x200
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL10_SHFT                                                       0x9
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL9_BMSK                                                      0x100
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL9_SHFT                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL8_BMSK                                                       0x80
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL8_SHFT                                                        0x7
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL7_BMSK                                                       0x40
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL7_SHFT                                                        0x6
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL6_BMSK                                                       0x20
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL6_SHFT                                                        0x5
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL5_BMSK                                                       0x10
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL5_SHFT                                                        0x4
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL4_BMSK                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL4_SHFT                                                        0x3
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL2_3_BMSK                                                      0x4
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL2_3_SHFT                                                      0x2
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL1_BMSK                                                        0x2
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL1_SHFT                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL0_BMSK                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_GPLL0_SHFT                                                        0x0

#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0009400c)
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_RMSK                                                            0x7ff
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL11_BMSK                                                     0x400
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL11_SHFT                                                       0xa
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL10_BMSK                                                     0x200
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL10_SHFT                                                       0x9
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL9_BMSK                                                      0x100
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL9_SHFT                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL8_BMSK                                                       0x80
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL8_SHFT                                                        0x7
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL7_BMSK                                                       0x40
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL7_SHFT                                                        0x6
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL6_BMSK                                                       0x20
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL6_SHFT                                                        0x5
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL5_BMSK                                                       0x10
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL5_SHFT                                                        0x4
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL4_BMSK                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL4_SHFT                                                        0x3
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL2_3_BMSK                                                      0x4
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL2_3_SHFT                                                      0x2
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL1_BMSK                                                        0x2
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL1_SHFT                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL0_BMSK                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_GPLL0_SHFT                                                        0x0

#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00094010)
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_RMSK                                                            0x7ff
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL11_BMSK                                                     0x400
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL11_SHFT                                                       0xa
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL10_BMSK                                                     0x200
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL10_SHFT                                                       0x9
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL9_BMSK                                                      0x100
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL9_SHFT                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL8_BMSK                                                       0x80
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL8_SHFT                                                        0x7
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL7_BMSK                                                       0x40
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL7_SHFT                                                        0x6
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL6_BMSK                                                       0x20
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL6_SHFT                                                        0x5
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL5_BMSK                                                       0x10
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL5_SHFT                                                        0x4
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL4_BMSK                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL4_SHFT                                                        0x3
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL2_3_BMSK                                                      0x4
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL2_3_SHFT                                                      0x2
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL1_BMSK                                                        0x2
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL1_SHFT                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL0_BMSK                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_GPLL0_SHFT                                                        0x0

#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00094014)
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_RMSK                                                            0x7ff
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL11_BMSK                                                     0x400
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL11_SHFT                                                       0xa
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL10_BMSK                                                     0x200
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL10_SHFT                                                       0x9
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL9_BMSK                                                      0x100
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL9_SHFT                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL8_BMSK                                                       0x80
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL8_SHFT                                                        0x7
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL7_BMSK                                                       0x40
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL7_SHFT                                                        0x6
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL6_BMSK                                                       0x20
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL6_SHFT                                                        0x5
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL5_BMSK                                                       0x10
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL5_SHFT                                                        0x4
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL4_BMSK                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL4_SHFT                                                        0x3
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL2_3_BMSK                                                      0x4
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL2_3_SHFT                                                      0x2
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL1_BMSK                                                        0x2
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL1_SHFT                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL0_BMSK                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_GPLL0_SHFT                                                        0x0

#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00094018)
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_RMSK                                                            0x7ff
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL11_BMSK                                                     0x400
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL11_SHFT                                                       0xa
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL10_BMSK                                                     0x200
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL10_SHFT                                                       0x9
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL9_BMSK                                                      0x100
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL9_SHFT                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL8_BMSK                                                       0x80
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL8_SHFT                                                        0x7
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL7_BMSK                                                       0x40
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL7_SHFT                                                        0x6
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL6_BMSK                                                       0x20
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL6_SHFT                                                        0x5
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL5_BMSK                                                       0x10
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL5_SHFT                                                        0x4
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL4_BMSK                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL4_SHFT                                                        0x3
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL2_3_BMSK                                                      0x4
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL2_3_SHFT                                                      0x2
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL1_BMSK                                                        0x2
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL1_SHFT                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL0_BMSK                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_GPLL0_SHFT                                                        0x0

#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x0009401c)
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_RMSK                                                            0x7ff
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL11_BMSK                                                     0x400
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL11_SHFT                                                       0xa
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL10_BMSK                                                     0x200
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL10_SHFT                                                       0x9
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL9_BMSK                                                      0x100
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL9_SHFT                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL8_BMSK                                                       0x80
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL8_SHFT                                                        0x7
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL7_BMSK                                                       0x40
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL7_SHFT                                                        0x6
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL6_BMSK                                                       0x20
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL6_SHFT                                                        0x5
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL5_BMSK                                                       0x10
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL5_SHFT                                                        0x4
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL4_BMSK                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL4_SHFT                                                        0x3
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL2_3_BMSK                                                      0x4
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL2_3_SHFT                                                      0x2
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL1_BMSK                                                        0x2
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL1_SHFT                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL0_BMSK                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_GPLL0_SHFT                                                        0x0

#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00094020)
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_RMSK                                                            0x7ff
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL11_BMSK                                                     0x400
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL11_SHFT                                                       0xa
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL10_BMSK                                                     0x200
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL10_SHFT                                                       0x9
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL9_BMSK                                                      0x100
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL9_SHFT                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL8_BMSK                                                       0x80
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL8_SHFT                                                        0x7
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL7_BMSK                                                       0x40
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL7_SHFT                                                        0x6
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL6_BMSK                                                       0x20
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL6_SHFT                                                        0x5
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL5_BMSK                                                       0x10
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL5_SHFT                                                        0x4
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL4_BMSK                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL4_SHFT                                                        0x3
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL2_3_BMSK                                                      0x4
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL2_3_SHFT                                                      0x2
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL1_BMSK                                                        0x2
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL1_SHFT                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL0_BMSK                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_GPLL0_SHFT                                                        0x0

#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00094024)
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_RMSK                                                            0x7ff
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL11_BMSK                                                     0x400
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL11_SHFT                                                       0xa
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL10_BMSK                                                     0x200
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL10_SHFT                                                       0x9
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL9_BMSK                                                      0x100
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL9_SHFT                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL8_BMSK                                                       0x80
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL8_SHFT                                                        0x7
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL7_BMSK                                                       0x40
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL7_SHFT                                                        0x6
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL6_BMSK                                                       0x20
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL6_SHFT                                                        0x5
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL5_BMSK                                                       0x10
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL5_SHFT                                                        0x4
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL4_BMSK                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL4_SHFT                                                        0x3
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL2_3_BMSK                                                      0x4
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL2_3_SHFT                                                      0x2
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL1_BMSK                                                        0x2
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL1_SHFT                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL0_BMSK                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_GPLL0_SHFT                                                        0x0

#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR                                                       (GCC_CLK_CTL_REG_REG_BASE      + 0x00094028)
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_RMSK                                                            0x7ff
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL11_BMSK                                                     0x400
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL11_SHFT                                                       0xa
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL10_BMSK                                                     0x200
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL10_SHFT                                                       0x9
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL9_BMSK                                                      0x100
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL9_SHFT                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL8_BMSK                                                       0x80
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL8_SHFT                                                        0x7
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL7_BMSK                                                       0x40
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL7_SHFT                                                        0x6
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL6_BMSK                                                       0x20
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL6_SHFT                                                        0x5
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL5_BMSK                                                       0x10
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL5_SHFT                                                        0x4
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL4_BMSK                                                        0x8
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL4_SHFT                                                        0x3
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL2_3_BMSK                                                      0x4
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL2_3_SHFT                                                      0x2
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL1_BMSK                                                        0x2
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL1_SHFT                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL0_BMSK                                                        0x1
#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_GPLL0_SHFT                                                        0x0

#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0009402c)
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_RMSK                                                           0x7ff
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL11_BMSK                                                    0x400
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL11_SHFT                                                      0xa
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL10_BMSK                                                    0x200
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL10_SHFT                                                      0x9
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL9_BMSK                                                     0x100
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL9_SHFT                                                       0x8
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL8_BMSK                                                      0x80
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL8_SHFT                                                       0x7
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL7_BMSK                                                      0x40
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL7_SHFT                                                       0x6
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL6_BMSK                                                      0x20
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL6_SHFT                                                       0x5
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL5_BMSK                                                      0x10
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL5_SHFT                                                       0x4
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL4_BMSK                                                       0x8
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL4_SHFT                                                       0x3
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL2_3_BMSK                                                     0x4
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL2_3_SHFT                                                     0x2
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00094030)
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_RMSK                                                           0x7ff
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL11_BMSK                                                    0x400
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL11_SHFT                                                      0xa
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL10_BMSK                                                    0x200
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL10_SHFT                                                      0x9
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL9_BMSK                                                     0x100
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL9_SHFT                                                       0x8
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL8_BMSK                                                      0x80
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL8_SHFT                                                       0x7
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL7_BMSK                                                      0x40
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL7_SHFT                                                       0x6
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL6_BMSK                                                      0x20
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL6_SHFT                                                       0x5
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL5_BMSK                                                      0x10
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL5_SHFT                                                       0x4
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL4_BMSK                                                       0x8
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL4_SHFT                                                       0x3
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL2_3_BMSK                                                     0x4
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL2_3_SHFT                                                     0x2
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00094034)
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_RMSK                                                           0x7ff
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL11_BMSK                                                    0x400
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL11_SHFT                                                      0xa
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL10_BMSK                                                    0x200
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL10_SHFT                                                      0x9
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL9_BMSK                                                     0x100
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL9_SHFT                                                       0x8
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL8_BMSK                                                      0x80
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL8_SHFT                                                       0x7
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL7_BMSK                                                      0x40
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL7_SHFT                                                       0x6
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL6_BMSK                                                      0x20
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL6_SHFT                                                       0x5
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL5_BMSK                                                      0x10
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL5_SHFT                                                       0x4
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL4_BMSK                                                       0x8
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL4_SHFT                                                       0x3
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL2_3_BMSK                                                     0x4
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL2_3_SHFT                                                     0x2
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00094038)
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_RMSK                                                           0x7ff
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL11_BMSK                                                    0x400
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL11_SHFT                                                      0xa
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL10_BMSK                                                    0x200
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL10_SHFT                                                      0x9
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL9_BMSK                                                     0x100
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL9_SHFT                                                       0x8
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL8_BMSK                                                      0x80
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL8_SHFT                                                       0x7
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL7_BMSK                                                      0x40
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL7_SHFT                                                       0x6
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL6_BMSK                                                      0x20
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL6_SHFT                                                       0x5
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL5_BMSK                                                      0x10
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL5_SHFT                                                       0x4
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL4_BMSK                                                       0x8
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL4_SHFT                                                       0x3
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL2_3_BMSK                                                     0x4
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL2_3_SHFT                                                     0x2
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x0009403c)
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_RMSK                                                           0x7ff
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL11_BMSK                                                    0x400
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL11_SHFT                                                      0xa
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL10_BMSK                                                    0x200
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL10_SHFT                                                      0x9
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL9_BMSK                                                     0x100
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL9_SHFT                                                       0x8
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL8_BMSK                                                      0x80
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL8_SHFT                                                       0x7
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL7_BMSK                                                      0x40
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL7_SHFT                                                       0x6
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL6_BMSK                                                      0x20
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL6_SHFT                                                       0x5
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL5_BMSK                                                      0x10
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL5_SHFT                                                       0x4
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL4_BMSK                                                       0x8
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL4_SHFT                                                       0x3
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL2_3_BMSK                                                     0x4
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL2_3_SHFT                                                     0x2
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00094040)
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_RMSK                                                           0x7ff
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL11_BMSK                                                    0x400
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL11_SHFT                                                      0xa
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL10_BMSK                                                    0x200
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL10_SHFT                                                      0x9
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL9_BMSK                                                     0x100
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL9_SHFT                                                       0x8
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL8_BMSK                                                      0x80
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL8_SHFT                                                       0x7
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL7_BMSK                                                      0x40
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL7_SHFT                                                       0x6
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL6_BMSK                                                      0x20
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL6_SHFT                                                       0x5
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL5_BMSK                                                      0x10
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL5_SHFT                                                       0x4
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL4_BMSK                                                       0x8
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL4_SHFT                                                       0x3
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL2_3_BMSK                                                     0x4
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL2_3_SHFT                                                     0x2
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL1_BMSK                                                       0x2
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL1_SHFT                                                       0x1
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL0_BMSK                                                       0x1
#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_GPLL0_SHFT                                                       0x0

#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00094100)
#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_RMSK                                                              0x1f
#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_IN          \
        in_dword(HWIO_GCC_RPMH_CE_INTERFACE_FSM_ADDR)
#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CE_INTERFACE_FSM_ADDR, m)
#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_FSM_STATE_BMSK                                                    0x1f
#define HWIO_GCC_RPMH_CE_INTERFACE_FSM_FSM_STATE_SHFT                                                     0x0

#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c004)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_RMSK                                                      0x7ff
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL11_BMSK                                               0x400
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL11_SHFT                                                 0xa
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL10_BMSK                                               0x200
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL10_SHFT                                                 0x9
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL9_BMSK                                                0x100
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL9_SHFT                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL8_BMSK                                                 0x80
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL8_SHFT                                                  0x7
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL7_BMSK                                                 0x40
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL7_SHFT                                                  0x6
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL6_BMSK                                                 0x20
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL6_SHFT                                                  0x5
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL5_BMSK                                                 0x10
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL5_SHFT                                                  0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL4_BMSK                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL4_SHFT                                                  0x3
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL2_3_BMSK                                                0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL2_3_SHFT                                                0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c008)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_RMSK                                                      0x7ff
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL11_BMSK                                               0x400
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL11_SHFT                                                 0xa
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL10_BMSK                                               0x200
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL10_SHFT                                                 0x9
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL9_BMSK                                                0x100
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL9_SHFT                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL8_BMSK                                                 0x80
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL8_SHFT                                                  0x7
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL7_BMSK                                                 0x40
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL7_SHFT                                                  0x6
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL6_BMSK                                                 0x20
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL6_SHFT                                                  0x5
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL5_BMSK                                                 0x10
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL5_SHFT                                                  0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL4_BMSK                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL4_SHFT                                                  0x3
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL2_3_BMSK                                                0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL2_3_SHFT                                                0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c00c)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_RMSK                                                      0x7ff
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL11_BMSK                                               0x400
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL11_SHFT                                                 0xa
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL10_BMSK                                               0x200
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL10_SHFT                                                 0x9
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL9_BMSK                                                0x100
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL9_SHFT                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL8_BMSK                                                 0x80
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL8_SHFT                                                  0x7
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL7_BMSK                                                 0x40
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL7_SHFT                                                  0x6
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL6_BMSK                                                 0x20
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL6_SHFT                                                  0x5
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL5_BMSK                                                 0x10
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL5_SHFT                                                  0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL4_BMSK                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL4_SHFT                                                  0x3
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL2_3_BMSK                                                0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL2_3_SHFT                                                0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c010)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_RMSK                                                      0x7ff
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL11_BMSK                                               0x400
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL11_SHFT                                                 0xa
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL10_BMSK                                               0x200
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL10_SHFT                                                 0x9
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL9_BMSK                                                0x100
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL9_SHFT                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL8_BMSK                                                 0x80
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL8_SHFT                                                  0x7
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL7_BMSK                                                 0x40
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL7_SHFT                                                  0x6
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL6_BMSK                                                 0x20
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL6_SHFT                                                  0x5
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL5_BMSK                                                 0x10
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL5_SHFT                                                  0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL4_BMSK                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL4_SHFT                                                  0x3
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL2_3_BMSK                                                0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL2_3_SHFT                                                0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c014)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_RMSK                                                      0x7ff
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL11_BMSK                                               0x400
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL11_SHFT                                                 0xa
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL10_BMSK                                               0x200
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL10_SHFT                                                 0x9
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL9_BMSK                                                0x100
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL9_SHFT                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL8_BMSK                                                 0x80
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL8_SHFT                                                  0x7
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL7_BMSK                                                 0x40
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL7_SHFT                                                  0x6
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL6_BMSK                                                 0x20
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL6_SHFT                                                  0x5
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL5_BMSK                                                 0x10
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL5_SHFT                                                  0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL4_BMSK                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL4_SHFT                                                  0x3
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL2_3_BMSK                                                0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL2_3_SHFT                                                0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c018)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_RMSK                                                      0x7ff
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL11_BMSK                                               0x400
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL11_SHFT                                                 0xa
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL10_BMSK                                               0x200
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL10_SHFT                                                 0x9
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL9_BMSK                                                0x100
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL9_SHFT                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL8_BMSK                                                 0x80
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL8_SHFT                                                  0x7
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL7_BMSK                                                 0x40
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL7_SHFT                                                  0x6
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL6_BMSK                                                 0x20
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL6_SHFT                                                  0x5
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL5_BMSK                                                 0x10
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL5_SHFT                                                  0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL4_BMSK                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL4_SHFT                                                  0x3
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL2_3_BMSK                                                0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL2_3_SHFT                                                0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c01c)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_RMSK                                                      0x7ff
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL11_BMSK                                               0x400
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL11_SHFT                                                 0xa
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL10_BMSK                                               0x200
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL10_SHFT                                                 0x9
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL9_BMSK                                                0x100
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL9_SHFT                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL8_BMSK                                                 0x80
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL8_SHFT                                                  0x7
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL7_BMSK                                                 0x40
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL7_SHFT                                                  0x6
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL6_BMSK                                                 0x20
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL6_SHFT                                                  0x5
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL5_BMSK                                                 0x10
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL5_SHFT                                                  0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL4_BMSK                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL4_SHFT                                                  0x3
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL2_3_BMSK                                                0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL2_3_SHFT                                                0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c020)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_RMSK                                                      0x7ff
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL11_BMSK                                               0x400
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL11_SHFT                                                 0xa
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL10_BMSK                                               0x200
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL10_SHFT                                                 0x9
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL9_BMSK                                                0x100
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL9_SHFT                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL8_BMSK                                                 0x80
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL8_SHFT                                                  0x7
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL7_BMSK                                                 0x40
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL7_SHFT                                                  0x6
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL6_BMSK                                                 0x20
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL6_SHFT                                                  0x5
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL5_BMSK                                                 0x10
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL5_SHFT                                                  0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL4_BMSK                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL4_SHFT                                                  0x3
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL2_3_BMSK                                                0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL2_3_SHFT                                                0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c024)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_RMSK                                                      0x7ff
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL11_BMSK                                               0x400
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL11_SHFT                                                 0xa
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL10_BMSK                                               0x200
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL10_SHFT                                                 0x9
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL9_BMSK                                                0x100
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL9_SHFT                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL8_BMSK                                                 0x80
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL8_SHFT                                                  0x7
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL7_BMSK                                                 0x40
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL7_SHFT                                                  0x6
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL6_BMSK                                                 0x20
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL6_SHFT                                                  0x5
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL5_BMSK                                                 0x10
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL5_SHFT                                                  0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL4_BMSK                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL4_SHFT                                                  0x3
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL2_3_BMSK                                                0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL2_3_SHFT                                                0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c028)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_RMSK                                                      0x7ff
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL11_BMSK                                               0x400
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL11_SHFT                                                 0xa
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL10_BMSK                                               0x200
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL10_SHFT                                                 0x9
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL9_BMSK                                                0x100
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL9_SHFT                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL8_BMSK                                                 0x80
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL8_SHFT                                                  0x7
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL7_BMSK                                                 0x40
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL7_SHFT                                                  0x6
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL6_BMSK                                                 0x20
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL6_SHFT                                                  0x5
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL5_BMSK                                                 0x10
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL5_SHFT                                                  0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL4_BMSK                                                  0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL4_SHFT                                                  0x3
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL2_3_BMSK                                                0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL2_3_SHFT                                                0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL1_BMSK                                                  0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL1_SHFT                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL0_BMSK                                                  0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_GPLL0_SHFT                                                  0x0

#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c02c)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_RMSK                                                     0x7ff
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL11_BMSK                                              0x400
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL11_SHFT                                                0xa
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL10_BMSK                                              0x200
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL10_SHFT                                                0x9
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL9_BMSK                                               0x100
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL9_SHFT                                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL8_BMSK                                                0x80
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL8_SHFT                                                 0x7
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL7_BMSK                                                0x40
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL7_SHFT                                                 0x6
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL6_BMSK                                                0x20
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL6_SHFT                                                 0x5
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL5_BMSK                                                0x10
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL5_SHFT                                                 0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL4_BMSK                                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL4_SHFT                                                 0x3
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL2_3_BMSK                                               0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL2_3_SHFT                                               0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL1_BMSK                                                 0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL1_SHFT                                                 0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL0_BMSK                                                 0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_GPLL0_SHFT                                                 0x0

#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c030)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_RMSK                                                     0x7ff
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL11_BMSK                                              0x400
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL11_SHFT                                                0xa
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL10_BMSK                                              0x200
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL10_SHFT                                                0x9
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL9_BMSK                                               0x100
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL9_SHFT                                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL8_BMSK                                                0x80
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL8_SHFT                                                 0x7
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL7_BMSK                                                0x40
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL7_SHFT                                                 0x6
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL6_BMSK                                                0x20
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL6_SHFT                                                 0x5
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL5_BMSK                                                0x10
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL5_SHFT                                                 0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL4_BMSK                                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL4_SHFT                                                 0x3
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL2_3_BMSK                                               0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL2_3_SHFT                                               0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL1_BMSK                                                 0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL1_SHFT                                                 0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL0_BMSK                                                 0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_GPLL0_SHFT                                                 0x0

#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c034)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_RMSK                                                     0x7ff
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL11_BMSK                                              0x400
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL11_SHFT                                                0xa
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL10_BMSK                                              0x200
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL10_SHFT                                                0x9
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL9_BMSK                                               0x100
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL9_SHFT                                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL8_BMSK                                                0x80
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL8_SHFT                                                 0x7
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL7_BMSK                                                0x40
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL7_SHFT                                                 0x6
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL6_BMSK                                                0x20
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL6_SHFT                                                 0x5
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL5_BMSK                                                0x10
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL5_SHFT                                                 0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL4_BMSK                                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL4_SHFT                                                 0x3
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL2_3_BMSK                                               0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL2_3_SHFT                                               0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL1_BMSK                                                 0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL1_SHFT                                                 0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL0_BMSK                                                 0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_GPLL0_SHFT                                                 0x0

#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c038)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_RMSK                                                     0x7ff
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL11_BMSK                                              0x400
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL11_SHFT                                                0xa
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL10_BMSK                                              0x200
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL10_SHFT                                                0x9
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL9_BMSK                                               0x100
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL9_SHFT                                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL8_BMSK                                                0x80
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL8_SHFT                                                 0x7
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL7_BMSK                                                0x40
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL7_SHFT                                                 0x6
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL6_BMSK                                                0x20
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL6_SHFT                                                 0x5
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL5_BMSK                                                0x10
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL5_SHFT                                                 0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL4_BMSK                                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL4_SHFT                                                 0x3
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL2_3_BMSK                                               0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL2_3_SHFT                                               0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL1_BMSK                                                 0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL1_SHFT                                                 0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL0_BMSK                                                 0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_GPLL0_SHFT                                                 0x0

#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c03c)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_RMSK                                                     0x7ff
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL11_BMSK                                              0x400
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL11_SHFT                                                0xa
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL10_BMSK                                              0x200
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL10_SHFT                                                0x9
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL9_BMSK                                               0x100
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL9_SHFT                                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL8_BMSK                                                0x80
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL8_SHFT                                                 0x7
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL7_BMSK                                                0x40
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL7_SHFT                                                 0x6
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL6_BMSK                                                0x20
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL6_SHFT                                                 0x5
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL5_BMSK                                                0x10
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL5_SHFT                                                 0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL4_BMSK                                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL4_SHFT                                                 0x3
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL2_3_BMSK                                               0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL2_3_SHFT                                               0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL1_BMSK                                                 0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL1_SHFT                                                 0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL0_BMSK                                                 0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_GPLL0_SHFT                                                 0x0

#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_ADDR                                                (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c040)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_RMSK                                                     0x7ff
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL11_BMSK                                              0x400
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL11_SHFT                                                0xa
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL10_BMSK                                              0x200
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL10_SHFT                                                0x9
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL9_BMSK                                               0x100
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL9_SHFT                                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL8_BMSK                                                0x80
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL8_SHFT                                                 0x7
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL7_BMSK                                                0x40
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL7_SHFT                                                 0x6
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL6_BMSK                                                0x20
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL6_SHFT                                                 0x5
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL5_BMSK                                                0x10
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL5_SHFT                                                 0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL4_BMSK                                                 0x8
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL4_SHFT                                                 0x3
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL2_3_BMSK                                               0x4
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL2_3_SHFT                                               0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL1_BMSK                                                 0x2
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL1_SHFT                                                 0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL0_BMSK                                                 0x1
#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_GPLL0_SHFT                                                 0x0

#define HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_ADDR                                                  (GCC_CLK_CTL_REG_REG_BASE      + 0x0009c100)
#define HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_RMSK                                                        0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_IN          \
        in_dword(HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_ADDR)
#define HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_ADDR, m)
#define HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_FSM_STATE_BMSK                                              0x1f
#define HWIO_GCC_RPMH_CDSP_NOC_INTERFACE_FSM_FSM_STATE_SHFT                                               0x0

#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00095004)
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00095008)
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009500c)
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00095010)
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00095014)
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00095018)
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009501c)
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00095020)
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00095024)
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00095028)
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0009502c)
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_RMSK                                                        0x7ff
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL11_BMSK                                                 0x400
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL11_SHFT                                                   0xa
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL10_BMSK                                                 0x200
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL10_SHFT                                                   0x9
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL9_BMSK                                                  0x100
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL9_SHFT                                                    0x8
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL8_BMSK                                                   0x80
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL8_SHFT                                                    0x7
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL7_BMSK                                                   0x40
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL7_SHFT                                                    0x6
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL6_BMSK                                                   0x20
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL6_SHFT                                                    0x5
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL5_BMSK                                                   0x10
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL5_SHFT                                                    0x4
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL4_BMSK                                                    0x8
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL4_SHFT                                                    0x3
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL2_3_BMSK                                                  0x4
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL2_3_SHFT                                                  0x2
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL1_BMSK                                                    0x2
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL1_SHFT                                                    0x1
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL0_BMSK                                                    0x1
#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_GPLL0_SHFT                                                    0x0

#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00095030)
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_RMSK                                                        0x7ff
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL11_BMSK                                                 0x400
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL11_SHFT                                                   0xa
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL10_BMSK                                                 0x200
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL10_SHFT                                                   0x9
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL9_BMSK                                                  0x100
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL9_SHFT                                                    0x8
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL8_BMSK                                                   0x80
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL8_SHFT                                                    0x7
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL7_BMSK                                                   0x40
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL7_SHFT                                                    0x6
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL6_BMSK                                                   0x20
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL6_SHFT                                                    0x5
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL5_BMSK                                                   0x10
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL5_SHFT                                                    0x4
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL4_BMSK                                                    0x8
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL4_SHFT                                                    0x3
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL2_3_BMSK                                                  0x4
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL2_3_SHFT                                                  0x2
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL1_BMSK                                                    0x2
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL1_SHFT                                                    0x1
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL0_BMSK                                                    0x1
#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_GPLL0_SHFT                                                    0x0

#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00095034)
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_RMSK                                                        0x7ff
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL11_BMSK                                                 0x400
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL11_SHFT                                                   0xa
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL10_BMSK                                                 0x200
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL10_SHFT                                                   0x9
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL9_BMSK                                                  0x100
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL9_SHFT                                                    0x8
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL8_BMSK                                                   0x80
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL8_SHFT                                                    0x7
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL7_BMSK                                                   0x40
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL7_SHFT                                                    0x6
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL6_BMSK                                                   0x20
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL6_SHFT                                                    0x5
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL5_BMSK                                                   0x10
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL5_SHFT                                                    0x4
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL4_BMSK                                                    0x8
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL4_SHFT                                                    0x3
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL2_3_BMSK                                                  0x4
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL2_3_SHFT                                                  0x2
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL1_BMSK                                                    0x2
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL1_SHFT                                                    0x1
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL0_BMSK                                                    0x1
#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_GPLL0_SHFT                                                    0x0

#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00095038)
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_RMSK                                                        0x7ff
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL11_BMSK                                                 0x400
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL11_SHFT                                                   0xa
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL10_BMSK                                                 0x200
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL10_SHFT                                                   0x9
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL9_BMSK                                                  0x100
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL9_SHFT                                                    0x8
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL8_BMSK                                                   0x80
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL8_SHFT                                                    0x7
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL7_BMSK                                                   0x40
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL7_SHFT                                                    0x6
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL6_BMSK                                                   0x20
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL6_SHFT                                                    0x5
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL5_BMSK                                                   0x10
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL5_SHFT                                                    0x4
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL4_BMSK                                                    0x8
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL4_SHFT                                                    0x3
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL2_3_BMSK                                                  0x4
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL2_3_SHFT                                                  0x2
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL1_BMSK                                                    0x2
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL1_SHFT                                                    0x1
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL0_BMSK                                                    0x1
#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_GPLL0_SHFT                                                    0x0

#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0009503c)
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_RMSK                                                        0x7ff
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL11_BMSK                                                 0x400
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL11_SHFT                                                   0xa
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL10_BMSK                                                 0x200
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL10_SHFT                                                   0x9
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL9_BMSK                                                  0x100
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL9_SHFT                                                    0x8
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL8_BMSK                                                   0x80
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL8_SHFT                                                    0x7
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL7_BMSK                                                   0x40
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL7_SHFT                                                    0x6
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL6_BMSK                                                   0x20
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL6_SHFT                                                    0x5
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL5_BMSK                                                   0x10
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL5_SHFT                                                    0x4
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL4_BMSK                                                    0x8
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL4_SHFT                                                    0x3
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL2_3_BMSK                                                  0x4
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL2_3_SHFT                                                  0x2
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL1_BMSK                                                    0x2
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL1_SHFT                                                    0x1
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL0_BMSK                                                    0x1
#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_GPLL0_SHFT                                                    0x0

#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00095040)
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_RMSK                                                        0x7ff
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL11_BMSK                                                 0x400
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL11_SHFT                                                   0xa
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL10_BMSK                                                 0x200
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL10_SHFT                                                   0x9
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL9_BMSK                                                  0x100
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL9_SHFT                                                    0x8
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL8_BMSK                                                   0x80
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL8_SHFT                                                    0x7
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL7_BMSK                                                   0x40
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL7_SHFT                                                    0x6
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL6_BMSK                                                   0x20
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL6_SHFT                                                    0x5
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL5_BMSK                                                   0x10
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL5_SHFT                                                    0x4
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL4_BMSK                                                    0x8
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL4_SHFT                                                    0x3
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL2_3_BMSK                                                  0x4
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL2_3_SHFT                                                  0x2
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL1_BMSK                                                    0x2
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL1_SHFT                                                    0x1
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL0_BMSK                                                    0x1
#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_GPLL0_SHFT                                                    0x0

#define HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00095100)
#define HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_RMSK                                                           0x1f
#define HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_IN          \
        in_dword(HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_ADDR)
#define HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_ADDR, m)
#define HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_FSM_STATE_BMSK                                                 0x1f
#define HWIO_GCC_RPMH_MMNOC_INTERFACE_FSM_FSM_STATE_SHFT                                                  0x0

#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00096004)
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00096008)
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0009600c)
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00096010)
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00096014)
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00096018)
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0009601c)
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00096020)
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00096024)
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00096028)
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009602c)
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00096030)
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00096034)
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00096038)
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009603c)
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00096040)
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00096100)
#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_RMSK                                                            0x1f
#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_IN          \
        in_dword(HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_ADDR)
#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_ADDR, m)
#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_FSM_STATE_BMSK                                                  0x1f
#define HWIO_GCC_RPMH_SHUB_INTERFACE_FSM_FSM_STATE_SHFT                                                   0x0

#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00097004)
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00097008)
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0009700c)
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00097010)
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00097014)
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00097018)
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x0009701c)
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00097020)
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00097024)
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00097028)
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_RMSK                                                          0x7ff
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL11_BMSK                                                   0x400
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL11_SHFT                                                     0xa
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL10_BMSK                                                   0x200
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL10_SHFT                                                     0x9
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL9_BMSK                                                    0x100
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL9_SHFT                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL8_BMSK                                                     0x80
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL8_SHFT                                                      0x7
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL7_BMSK                                                     0x40
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL7_SHFT                                                      0x6
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL6_BMSK                                                     0x20
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL6_SHFT                                                      0x5
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL5_BMSK                                                     0x10
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL5_SHFT                                                      0x4
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL4_BMSK                                                      0x8
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL4_SHFT                                                      0x3
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL2_3_BMSK                                                    0x4
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL2_3_SHFT                                                    0x2
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL1_BMSK                                                      0x2
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL1_SHFT                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL0_BMSK                                                      0x1
#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_GPLL0_SHFT                                                      0x0

#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009702c)
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00097030)
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00097034)
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00097038)
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009703c)
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x00097040)
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_RMSK                                                         0x7ff
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_ADDR                                                      (GCC_CLK_CTL_REG_REG_BASE      + 0x00097100)
#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_RMSK                                                            0x1f
#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_IN          \
        in_dword(HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_ADDR)
#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_ADDR, m)
#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_FSM_STATE_BMSK                                                  0x1f
#define HWIO_GCC_RPMH_SHRM_INTERFACE_FSM_FSM_STATE_SHFT                                                   0x0

#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009a004)
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_RMSK                                                         0xfff
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GCC_MODE_BMSK                                                0x800
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GCC_MODE_SHFT                                                  0xb
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009a008)
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_RMSK                                                         0xfff
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GCC_MODE_BMSK                                                0x800
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GCC_MODE_SHFT                                                  0xb
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009a00c)
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_RMSK                                                         0xfff
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GCC_MODE_BMSK                                                0x800
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GCC_MODE_SHFT                                                  0xb
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009a010)
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_RMSK                                                         0xfff
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GCC_MODE_BMSK                                                0x800
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GCC_MODE_SHFT                                                  0xb
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009a014)
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_RMSK                                                         0xfff
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GCC_MODE_BMSK                                                0x800
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GCC_MODE_SHFT                                                  0xb
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009a018)
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_RMSK                                                         0xfff
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GCC_MODE_BMSK                                                0x800
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GCC_MODE_SHFT                                                  0xb
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009a01c)
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_RMSK                                                         0xfff
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GCC_MODE_BMSK                                                0x800
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GCC_MODE_SHFT                                                  0xb
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009a020)
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_RMSK                                                         0xfff
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GCC_MODE_BMSK                                                0x800
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GCC_MODE_SHFT                                                  0xb
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009a024)
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_RMSK                                                         0xfff
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GCC_MODE_BMSK                                                0x800
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GCC_MODE_SHFT                                                  0xb
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_ADDR                                                    (GCC_CLK_CTL_REG_REG_BASE      + 0x0009a028)
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_RMSK                                                         0xfff
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GCC_MODE_BMSK                                                0x800
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GCC_MODE_SHFT                                                  0xb
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL11_BMSK                                                  0x400
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL11_SHFT                                                    0xa
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL10_BMSK                                                  0x200
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL10_SHFT                                                    0x9
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL9_BMSK                                                   0x100
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL9_SHFT                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL8_BMSK                                                    0x80
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL8_SHFT                                                     0x7
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL7_BMSK                                                    0x40
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL7_SHFT                                                     0x6
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL6_BMSK                                                    0x20
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL6_SHFT                                                     0x5
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL5_BMSK                                                    0x10
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL5_SHFT                                                     0x4
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL4_BMSK                                                     0x8
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL4_SHFT                                                     0x3
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL2_3_BMSK                                                   0x4
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL2_3_SHFT                                                   0x2
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL1_BMSK                                                     0x2
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL1_SHFT                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL0_BMSK                                                     0x1
#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_GPLL0_SHFT                                                     0x0

#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0009a02c)
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_RMSK                                                        0xfff
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GCC_MODE_BMSK                                               0x800
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GCC_MODE_SHFT                                                 0xb
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL11_BMSK                                                 0x400
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL11_SHFT                                                   0xa
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL10_BMSK                                                 0x200
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL10_SHFT                                                   0x9
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL9_BMSK                                                  0x100
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL9_SHFT                                                    0x8
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL8_BMSK                                                   0x80
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL8_SHFT                                                    0x7
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL7_BMSK                                                   0x40
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL7_SHFT                                                    0x6
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL6_BMSK                                                   0x20
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL6_SHFT                                                    0x5
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL5_BMSK                                                   0x10
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL5_SHFT                                                    0x4
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL4_BMSK                                                    0x8
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL4_SHFT                                                    0x3
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL2_3_BMSK                                                  0x4
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL2_3_SHFT                                                  0x2
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL1_BMSK                                                    0x2
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL1_SHFT                                                    0x1
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL0_BMSK                                                    0x1
#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_GPLL0_SHFT                                                    0x0

#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0009a030)
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_RMSK                                                        0xfff
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GCC_MODE_BMSK                                               0x800
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GCC_MODE_SHFT                                                 0xb
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL11_BMSK                                                 0x400
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL11_SHFT                                                   0xa
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL10_BMSK                                                 0x200
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL10_SHFT                                                   0x9
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL9_BMSK                                                  0x100
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL9_SHFT                                                    0x8
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL8_BMSK                                                   0x80
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL8_SHFT                                                    0x7
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL7_BMSK                                                   0x40
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL7_SHFT                                                    0x6
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL6_BMSK                                                   0x20
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL6_SHFT                                                    0x5
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL5_BMSK                                                   0x10
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL5_SHFT                                                    0x4
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL4_BMSK                                                    0x8
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL4_SHFT                                                    0x3
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL2_3_BMSK                                                  0x4
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL2_3_SHFT                                                  0x2
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL1_BMSK                                                    0x2
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL1_SHFT                                                    0x1
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL0_BMSK                                                    0x1
#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_GPLL0_SHFT                                                    0x0

#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0009a034)
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_RMSK                                                        0xfff
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GCC_MODE_BMSK                                               0x800
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GCC_MODE_SHFT                                                 0xb
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL11_BMSK                                                 0x400
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL11_SHFT                                                   0xa
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL10_BMSK                                                 0x200
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL10_SHFT                                                   0x9
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL9_BMSK                                                  0x100
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL9_SHFT                                                    0x8
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL8_BMSK                                                   0x80
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL8_SHFT                                                    0x7
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL7_BMSK                                                   0x40
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL7_SHFT                                                    0x6
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL6_BMSK                                                   0x20
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL6_SHFT                                                    0x5
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL5_BMSK                                                   0x10
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL5_SHFT                                                    0x4
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL4_BMSK                                                    0x8
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL4_SHFT                                                    0x3
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL2_3_BMSK                                                  0x4
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL2_3_SHFT                                                  0x2
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL1_BMSK                                                    0x2
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL1_SHFT                                                    0x1
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL0_BMSK                                                    0x1
#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_GPLL0_SHFT                                                    0x0

#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0009a038)
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_RMSK                                                        0xfff
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GCC_MODE_BMSK                                               0x800
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GCC_MODE_SHFT                                                 0xb
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL11_BMSK                                                 0x400
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL11_SHFT                                                   0xa
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL10_BMSK                                                 0x200
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL10_SHFT                                                   0x9
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL9_BMSK                                                  0x100
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL9_SHFT                                                    0x8
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL8_BMSK                                                   0x80
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL8_SHFT                                                    0x7
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL7_BMSK                                                   0x40
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL7_SHFT                                                    0x6
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL6_BMSK                                                   0x20
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL6_SHFT                                                    0x5
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL5_BMSK                                                   0x10
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL5_SHFT                                                    0x4
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL4_BMSK                                                    0x8
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL4_SHFT                                                    0x3
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL2_3_BMSK                                                  0x4
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL2_3_SHFT                                                  0x2
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL1_BMSK                                                    0x2
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL1_SHFT                                                    0x1
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL0_BMSK                                                    0x1
#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_GPLL0_SHFT                                                    0x0

#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0009a03c)
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_RMSK                                                        0xfff
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GCC_MODE_BMSK                                               0x800
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GCC_MODE_SHFT                                                 0xb
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL11_BMSK                                                 0x400
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL11_SHFT                                                   0xa
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL10_BMSK                                                 0x200
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL10_SHFT                                                   0x9
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL9_BMSK                                                  0x100
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL9_SHFT                                                    0x8
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL8_BMSK                                                   0x80
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL8_SHFT                                                    0x7
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL7_BMSK                                                   0x40
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL7_SHFT                                                    0x6
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL6_BMSK                                                   0x20
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL6_SHFT                                                    0x5
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL5_BMSK                                                   0x10
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL5_SHFT                                                    0x4
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL4_BMSK                                                    0x8
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL4_SHFT                                                    0x3
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL2_3_BMSK                                                  0x4
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL2_3_SHFT                                                  0x2
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL1_BMSK                                                    0x2
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL1_SHFT                                                    0x1
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL0_BMSK                                                    0x1
#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_GPLL0_SHFT                                                    0x0

#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x0009a040)
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_RMSK                                                        0xfff
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GCC_MODE_BMSK                                               0x800
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GCC_MODE_SHFT                                                 0xb
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL11_BMSK                                                 0x400
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL11_SHFT                                                   0xa
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL10_BMSK                                                 0x200
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL10_SHFT                                                   0x9
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL9_BMSK                                                  0x100
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL9_SHFT                                                    0x8
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL8_BMSK                                                   0x80
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL8_SHFT                                                    0x7
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL7_BMSK                                                   0x40
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL7_SHFT                                                    0x6
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL6_BMSK                                                   0x20
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL6_SHFT                                                    0x5
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL5_BMSK                                                   0x10
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL5_SHFT                                                    0x4
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL4_BMSK                                                    0x8
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL4_SHFT                                                    0x3
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL2_3_BMSK                                                  0x4
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL2_3_SHFT                                                  0x2
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL1_BMSK                                                    0x2
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL1_SHFT                                                    0x1
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL0_BMSK                                                    0x1
#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_GPLL0_SHFT                                                    0x0

#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00098004)
#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_RMSK                                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_PLL_L_BMSK                                             0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_PLL_L_SHFT                                                0x0

#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00098008)
#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_RMSK                                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_PLL_L_BMSK                                             0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_PLL_L_SHFT                                                0x0

#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0009800c)
#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_RMSK                                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_PLL_L_BMSK                                             0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_PLL_L_SHFT                                                0x0

#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00098010)
#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_RMSK                                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_PLL_L_BMSK                                             0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_PLL_L_SHFT                                                0x0

#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00098014)
#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_RMSK                                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_PLL_L_BMSK                                             0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_PLL_L_SHFT                                                0x0

#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00098018)
#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_RMSK                                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_PLL_L_BMSK                                             0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_PLL_L_SHFT                                                0x0

#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x0009801c)
#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_RMSK                                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_PLL_L_BMSK                                             0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_PLL_L_SHFT                                                0x0

#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00098020)
#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_RMSK                                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_PLL_L_BMSK                                             0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_PLL_L_SHFT                                                0x0

#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00098024)
#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_RMSK                                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_PLL_L_BMSK                                             0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_PLL_L_SHFT                                                0x0

#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_ADDR                                               (GCC_CLK_CTL_REG_REG_BASE      + 0x00098028)
#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_RMSK                                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_PLL_L_BMSK                                             0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_PLL_L_SHFT                                                0x0

#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0009802c)
#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_RMSK                                                  0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_PLL_L_BMSK                                            0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_PLL_L_SHFT                                               0x0

#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00098030)
#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_RMSK                                                  0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_PLL_L_BMSK                                            0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_PLL_L_SHFT                                               0x0

#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00098034)
#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_RMSK                                                  0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_PLL_L_BMSK                                            0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_PLL_L_SHFT                                               0x0

#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00098038)
#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_RMSK                                                  0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_PLL_L_BMSK                                            0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_PLL_L_SHFT                                               0x0

#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x0009803c)
#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_RMSK                                                  0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_PLL_L_BMSK                                            0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_PLL_L_SHFT                                               0x0

#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_ADDR                                              (GCC_CLK_CTL_REG_REG_BASE      + 0x00098040)
#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_RMSK                                                  0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_PLL_L_BMSK                                            0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_PLL_L_SHFT                                               0x0

#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00099004)
#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_RMSK                                                0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT                                      0x0

#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00099008)
#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_RMSK                                                0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT                                      0x0

#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0009900c)
#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_RMSK                                                0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT                                      0x0

#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00099010)
#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_RMSK                                                0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT                                      0x0

#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00099014)
#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_RMSK                                                0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT                                      0x0

#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00099018)
#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_RMSK                                                0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT                                      0x0

#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x0009901c)
#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_RMSK                                                0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT                                      0x0

#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00099020)
#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_RMSK                                                0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT                                      0x0

#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00099024)
#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_RMSK                                                0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT                                      0x0

#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_ADDR                                            (GCC_CLK_CTL_REG_REG_BASE      + 0x00099028)
#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_RMSK                                                0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK                                   0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT                                      0x0

#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0009902c)
#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_RMSK                                               0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK                                  0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT                                     0x0

#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00099030)
#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_RMSK                                               0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK                                  0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT                                     0x0

#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00099034)
#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_RMSK                                               0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK                                  0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT                                     0x0

#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00099038)
#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_RMSK                                               0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK                                  0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT                                     0x0

#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x0009903c)
#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_RMSK                                               0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK                                  0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT                                     0x0

#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_ADDR                                           (GCC_CLK_CTL_REG_REG_BASE      + 0x00099040)
#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_RMSK                                               0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_ADDR)
#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_IN)
#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_BMSK                                  0xffff
#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_PLL_FRAC_VAL_SHFT                                     0x0

#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00099080)
#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_RMSK                                                        0x3
#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_ADDR)
#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_IN)
#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_RCG_TOGGLE_EN_BMSK                                          0x2
#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_RCG_TOGGLE_EN_SHFT                                          0x1
#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_PLL_TOGGLE_EN_BMSK                                          0x1
#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_PLL_TOGGLE_EN_SHFT                                          0x0

#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_ADDR                                                 (GCC_CLK_CTL_REG_REG_BASE      + 0x00044530)
#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_RMSK                                                 0xffffffff
#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_IN          \
        in_dword(HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_ADDR)
#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_ADDR, m)
#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_ADDR,v)
#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_ADDR,m,v,HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_IN)
#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_RESERVE_BIT31_7_BMSK                                 0xffffff80
#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_RESERVE_BIT31_7_SHFT                                        0x7
#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_PLL_PP_STATE_STATUS_BMSK                                   0x40
#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_PLL_PP_STATE_STATUS_SHFT                                    0x6
#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_RCG_PP_STATE_STATUS_BMSK                                   0x20
#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_RCG_PP_STATE_STATUS_SHFT                                    0x5
#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_CLOCK_SWITCH_FSM_STATUS_BMSK                               0x1f
#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_CLOCK_SWITCH_FSM_STATUS_SHFT                                0x0

#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00071250)
#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_RMSK                                                               0x3
#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_IN          \
        in_dword(HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_ADDR)
#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_INM(m)      \
        in_dword_masked(HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_ADDR, m)
#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_OUT(v)      \
        out_dword(HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_ADDR,v)
#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_ADDR,m,v,HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_IN)
#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_MUX_SELECT_BMSK                                                    0x3
#define HWIO_GCC_GPU_MEMNOC_GFX_CLK_EN_MUX_SELECT_SHFT                                                    0x0

#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x0008323c)
#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_RMSK                                                               0x3
#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_IN          \
        in_dword(HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_ADDR)
#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_INM(m)      \
        in_dword_masked(HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_ADDR, m)
#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_OUT(v)      \
        out_dword(HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_ADDR,v)
#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_ADDR,m,v,HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_IN)
#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_MUX_SELECT_BMSK                                                    0x3
#define HWIO_GCC_MMU_MEMNOC_TCU_CLK_EN_MUX_SELECT_SHFT                                                    0x0

#define HWIO_GCC_MEMNOC_TURING_CLK_EN_ADDR                                                         (GCC_CLK_CTL_REG_REG_BASE      + 0x00045490)
#define HWIO_GCC_MEMNOC_TURING_CLK_EN_RMSK                                                                0x3
#define HWIO_GCC_MEMNOC_TURING_CLK_EN_IN          \
        in_dword(HWIO_GCC_MEMNOC_TURING_CLK_EN_ADDR)
#define HWIO_GCC_MEMNOC_TURING_CLK_EN_INM(m)      \
        in_dword_masked(HWIO_GCC_MEMNOC_TURING_CLK_EN_ADDR, m)
#define HWIO_GCC_MEMNOC_TURING_CLK_EN_OUT(v)      \
        out_dword(HWIO_GCC_MEMNOC_TURING_CLK_EN_ADDR,v)
#define HWIO_GCC_MEMNOC_TURING_CLK_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_MEMNOC_TURING_CLK_EN_ADDR,m,v,HWIO_GCC_MEMNOC_TURING_CLK_EN_IN)
#define HWIO_GCC_MEMNOC_TURING_CLK_EN_MUX_SELECT_BMSK                                                     0x3
#define HWIO_GCC_MEMNOC_TURING_CLK_EN_MUX_SELECT_SHFT                                                     0x0

#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_ADDR                                                   (GCC_CLK_CTL_REG_REG_BASE      + 0x00047110)
#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_RMSK                                                          0x1
#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_IN          \
        in_dword(HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_ADDR)
#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_INM(m)      \
        in_dword_masked(HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_ADDR, m)
#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_OUT(v)      \
        out_dword(HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_ADDR,v)
#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_ADDR,m,v,HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_IN)
#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_MUX_SEL_BMSK                                                  0x1
#define HWIO_GCC_LPASS_Q6SS_BOOT_GPLL0_MUXR_MUX_SEL_SHFT                                                  0x0

#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_ADDR                                                        (GCC_CLK_CTL_REG_REG_BASE      + 0x00021000)
#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_RMSK                                                        0xffffffff
#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_IN          \
        in_dword(HWIO_GCC_ACA_FAL10_VETO_ENABLE_ADDR)
#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_INM(m)      \
        in_dword_masked(HWIO_GCC_ACA_FAL10_VETO_ENABLE_ADDR, m)
#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_OUT(v)      \
        out_dword(HWIO_GCC_ACA_FAL10_VETO_ENABLE_ADDR,v)
#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_ACA_FAL10_VETO_ENABLE_ADDR,m,v,HWIO_GCC_ACA_FAL10_VETO_ENABLE_IN)
#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_BMSK                                     0xffffffff
#define HWIO_GCC_ACA_FAL10_VETO_ENABLE_CLK_ON_VETO_ENABLE_SHFT                                            0x0

#define HWIO_GCC_PLL_MISC_ADDR                                                                     (GCC_CLK_CTL_REG_REG_BASE      + 0x00020000)
#define HWIO_GCC_PLL_MISC_RMSK                                                                            0x1
#define HWIO_GCC_PLL_MISC_IN          \
        in_dword(HWIO_GCC_PLL_MISC_ADDR)
#define HWIO_GCC_PLL_MISC_INM(m)      \
        in_dword_masked(HWIO_GCC_PLL_MISC_ADDR, m)
#define HWIO_GCC_PLL_MISC_OUT(v)      \
        out_dword(HWIO_GCC_PLL_MISC_ADDR,v)
#define HWIO_GCC_PLL_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_PLL_MISC_ADDR,m,v,HWIO_GCC_PLL_MISC_IN)
#define HWIO_GCC_PLL_MISC_HW_TRIGGERED_PLL_STBY_DIS_BMSK                                                  0x1
#define HWIO_GCC_PLL_MISC_HW_TRIGGERED_PLL_STBY_DIS_SHFT                                                  0x0

#define HWIO_GCC_RPMH_ALL_CLK_OFF_ADDR                                                             (GCC_CLK_CTL_REG_REG_BASE      + 0x00020004)
#define HWIO_GCC_RPMH_ALL_CLK_OFF_RMSK                                                                    0x1
#define HWIO_GCC_RPMH_ALL_CLK_OFF_IN          \
        in_dword(HWIO_GCC_RPMH_ALL_CLK_OFF_ADDR)
#define HWIO_GCC_RPMH_ALL_CLK_OFF_INM(m)      \
        in_dword_masked(HWIO_GCC_RPMH_ALL_CLK_OFF_ADDR, m)
#define HWIO_GCC_RPMH_ALL_CLK_OFF_OUT(v)      \
        out_dword(HWIO_GCC_RPMH_ALL_CLK_OFF_ADDR,v)
#define HWIO_GCC_RPMH_ALL_CLK_OFF_OUTM(m,v) \
        out_dword_masked_ns(HWIO_GCC_RPMH_ALL_CLK_OFF_ADDR,m,v,HWIO_GCC_RPMH_ALL_CLK_OFF_IN)
#define HWIO_GCC_RPMH_ALL_CLK_OFF_MUX_SEL_BMSK                                                            0x1
#define HWIO_GCC_RPMH_ALL_CLK_OFF_MUX_SEL_SHFT                                                            0x0

/*----------------------------------------------------------------------------
 * MODULE: AOSS_PERIPHERALS
 *--------------------------------------------------------------------------*/

#define AOSS_PERIPHERALS_REG_BASE (AOSS_BASE      + 0x01210000)
#define AOSS_PERIPHERALS_REG_BASE_SIZE 0x80000
#define AOSS_PERIPHERALS_REG_BASE_USED 0x0

/*----------------------------------------------------------------------------
 * MODULE: TCSR_TCSR_REGS
 *--------------------------------------------------------------------------*/

#define TCSR_TCSR_REGS_REG_BASE                                                                                         (CORE_TOP_CSR_BASE      + 0x000c0000)
#define TCSR_TCSR_REGS_REG_BASE_SIZE                                                                                    0x30000
#define TCSR_TCSR_REGS_REG_BASE_USED                                                                                    0x2e014

#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x0000d000)
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_RMSK                                                                                 0x7
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_IN          \
        in_dword(HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_ADDR)
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_ADDR, m)
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDMMCX_READ_BMSK                                                     0x4
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDMMCX_READ_SHFT                                                     0x2
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDGFX_READ_BMSK                                                      0x2
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDGFX_READ_SHFT                                                      0x1
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDCX_READ_BMSK                                                       0x1
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDCX_READ_SHFT                                                       0x0

#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x00022000)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_RMSK                                                                      0xff
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_ADDR)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_IN)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_DBGOVR_COMPILER_MEM_ACC_SEL_0_BMSK                                        0xff
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_0_REG_DBGOVR_COMPILER_MEM_ACC_SEL_0_SHFT                                         0x0

#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00022004)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_RMSK                                                                  0xffffffff
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_ADDR)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_IN)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_DBGOVR_CUSTOM_MEM_ACC_SEL_0_BMSK                                      0xffffffff
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_0_REG_DBGOVR_CUSTOM_MEM_ACC_SEL_0_SHFT                                             0x0

#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00022008)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_RMSK                                                                        0xff
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_ADDR)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_IN)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_DBGOVR_CUSTOM_MEM_ACC_SEL_1_BMSK                                            0xff
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_1_REG_DBGOVR_CUSTOM_MEM_ACC_SEL_1_SHFT                                             0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00022010)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_7_BMSK                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_7_SHFT                                     0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00022014)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_6_BMSK                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_6_SHFT                                     0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00022018)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_5_BMSK                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_5_SHFT                                     0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002201c)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_4_BMSK                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_4_SHFT                                     0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00022020)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_3_BMSK                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_3_SHFT                                     0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00022024)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_2_BMSK                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_2_SHFT                                     0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00022028)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_1_BMSK                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_1_SHFT                                     0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002202c)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_0_BMSK                                   0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_0_SHFT                                     0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022030)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022034)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022038)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0002203c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022040)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022044)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022048)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0002204c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022050)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_RMSK                                                                 0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_BMSK                               0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_SHFT                                 0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022054)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022058)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0002205c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022060)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022064)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022068)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0002206c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022070)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022074)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022078)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0002207c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022080)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022084)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022088)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0002208c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022090)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022094)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022098)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE27_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0002209c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE28_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220a0)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE29_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220a4)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE30_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220a8)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE31_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220ac)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE32_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220b0)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE33_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220b4)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE34_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220b8)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE35_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220bc)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE36_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220c0)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE37_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220c4)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE38_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220c8)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE39_SHFT                               0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x000220cc)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_RMSK                                                                0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_IN          \
        in_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_ADDR)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_BMSK                             0x3ff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE40_SHFT                               0x0

#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000d004)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_RMSK                                                                 0xffffffff
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_FUSE_COMPILER_MEM_ACC_0_READ_BMSK                                    0xffffffff
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_FUSE_COMPILER_MEM_ACC_0_READ_SHFT                                           0x0

#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000d008)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_RMSK                                                                 0xffffffff
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_FUSE_COMPILER_MEM_ACC_1_READ_BMSK                                    0xffffffff
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_FUSE_COMPILER_MEM_ACC_1_READ_SHFT                                           0x0

#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000d00c)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_RMSK                                                                     0xffff
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_FUSE_COMPILER_MEM_ACC_2_READ_BMSK                                        0xffff
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_2_READ_REG_FUSE_COMPILER_MEM_ACC_2_READ_SHFT                                           0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d010)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d014)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d018)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d01c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d020)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d024)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d028)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d02c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000d030)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_RMSK                                                                    0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_BMSK                                     0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_SHFT                                       0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d034)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d038)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d03c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d040)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d044)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d048)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d04c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d050)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d054)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d058)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d05c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d060)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d064)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d068)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d06c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d070)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d074)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d078)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE27_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d07c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE28_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d080)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE29_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d084)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE30_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d088)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE31_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d08c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE32_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d090)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE33_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d094)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE34_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d098)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE35_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d09c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE36_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d0a0)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE37_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d0a4)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE38_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d0a8)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE39_READ_SHFT                                     0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d0ac)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_RMSK                                                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_IN          \
        in_dword(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_ADDR)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_BMSK                                   0x3ff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE40_READ_SHFT                                     0x0

#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022800)
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_RMSK                                                                            0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_IN          \
        in_dword(HWIO_TCSR_MBIST_DBG_STATUS0_REG_ADDR)
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_MBIST_DBG_STATUS0_REG_ADDR, m)
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_MBIST_DBG_STATUS0_BMSK                                                          0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_MBIST_DBG_STATUS0_SHFT                                                                 0x0

#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022804)
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_RMSK                                                                            0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_IN          \
        in_dword(HWIO_TCSR_MBIST_DBG_STATUS1_REG_ADDR)
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_MBIST_DBG_STATUS1_REG_ADDR, m)
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_MBIST_DBG_STATUS1_BMSK                                                          0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_MBIST_DBG_STATUS1_SHFT                                                                 0x0

#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00022808)
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_RMSK                                                                            0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_IN          \
        in_dword(HWIO_TCSR_MBIST_DBG_STATUS2_REG_ADDR)
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_MBIST_DBG_STATUS2_REG_ADDR, m)
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_MBIST_DBG_STATUS2_BMSK                                                          0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_MBIST_DBG_STATUS2_SHFT                                                                 0x0

#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0002280c)
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_RMSK                                                                            0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_IN          \
        in_dword(HWIO_TCSR_MBIST_DBG_STATUS3_REG_ADDR)
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_MBIST_DBG_STATUS3_REG_ADDR, m)
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_MBIST_DBG_STATUS3_BMSK                                                          0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_MBIST_DBG_STATUS3_SHFT                                                                 0x0

#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_ADDR                                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x00000800)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_RMSK                                                                                    0x1
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_IN          \
        in_dword(HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_ADDR)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_ADDR, m)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_OUT(v)      \
        out_dword(HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_ADDR,v)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_ADDR,m,v,HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_IN)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_TIMEOUT_SLAVE_GLB_EN_BMSK                                                               0x1
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_TIMEOUT_SLAVE_GLB_EN_SHFT                                                               0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_ADDR                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x00021010)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_RMSK                                                                        0xffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_BMSK                                                 0xffc0
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_SHFT                                                    0x6
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_BMSK                                                    0x3f
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_SHFT                                                     0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_ADDR                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x00021014)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_RMSK                                                                        0xffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_BMSK                                                 0xffc0
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_SHFT                                                    0x6
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_BMSK                                                    0x3f
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_SHFT                                                     0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_ADDR                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x00021018)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_RMSK                                                                      0x7fffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_BMSK                                               0x7fff00
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_SHFT                                                    0x8
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_BMSK                                                    0xff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_SHFT                                                     0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x0002101c)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_RMSK                                                                      0xffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                        0xffc0
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                           0x6
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                           0x3f
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                            0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00021020)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_RMSK                                                                      0xffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                        0xffc0
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                           0x6
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                           0x3f
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                            0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00021024)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_RMSK                                                                    0x7fffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                      0x7fff00
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                           0x8
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                           0xff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                            0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00021028)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_RMSK                                                                      0xffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                        0xffc0
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                           0x6
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                           0x3f
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                            0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x0002102c)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_RMSK                                                                      0xffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                        0xffc0
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                           0x6
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                           0x3f
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                            0x0

#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00021030)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_RMSK                                                                    0x7fffff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                      0x7fff00
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                           0x8
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                           0xff
#define HWIO_TCSR_TOP_QUPV3_SP_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                            0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_ADDR                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0000b000)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_RMSK                                                                       0xffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_BMSK                                                0xffc0
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_SHFT                                                   0x6
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_BMSK                                                   0x3f
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_SHFT                                                    0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_ADDR                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0000b004)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_RMSK                                                                       0xffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_BMSK                                                0xffc0
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_SHFT                                                   0x6
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_BMSK                                                   0x3f
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_SHFT                                                    0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_ADDR                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0000b008)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_RMSK                                                                     0x7fffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_BMSK                                              0x7fff00
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_SHFT                                                   0x8
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_BMSK                                                   0xff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_SHFT                                                    0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b00c)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_RMSK                                                                     0xffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                       0xffc0
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                          0x6
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                          0x3f
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b010)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_RMSK                                                                     0xffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                       0xffc0
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                          0x6
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                          0x3f
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b014)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_RMSK                                                                   0x7fffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                     0x7fff00
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                          0x8
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                          0xff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b018)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_RMSK                                                                     0xffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                       0xffc0
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                          0x6
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                          0x3f
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b01c)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_RMSK                                                                     0xffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                       0xffc0
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                          0x6
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                          0x3f
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b020)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_RMSK                                                                   0x7fffff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                     0x7fff00
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                          0x8
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                          0xff
#define HWIO_TCSR_TOP_QUPV3_SSC_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x00029004)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_RMSK                                                                     0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_BMSK                                              0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_SHFT                                                 0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_BMSK                                                 0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_SHFT                                                  0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x00029008)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_RMSK                                                                     0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_BMSK                                              0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_SHFT                                                 0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_BMSK                                                 0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_SHFT                                                  0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0002900c)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_RMSK                                                                   0x7fffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_BMSK                                            0x7fff00
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_SHFT                                                 0x8
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_BMSK                                                 0xff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_SHFT                                                  0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029010)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029014)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029018)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_RMSK                                                                 0x7fffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                   0x7fff00
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0002901c)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029020)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029024)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_RMSK                                                                 0x7fffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                   0x7fff00
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029028)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0002902c)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029030)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_RMSK                                                                 0x7fffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                   0x7fff00
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_2_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029034)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029038)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0002903c)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_RMSK                                                                 0x7fffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                   0x7fff00
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_3_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029040)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029044)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029048)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_RMSK                                                                 0x7fffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                   0x7fff00
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_4_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0002904c)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029050)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_RMSK                                                                   0xffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                     0xffc0
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029054)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_RMSK                                                                 0x7fffff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                   0x7fff00
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_TOP_QUPV3_LPASS_IRQ_ENABLE_5_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0002b004)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_RMSK                                                                    0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_BMSK                                             0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_SHFT                                                0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_BMSK                                                0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_SHFT                                                 0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0002b008)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_RMSK                                                                    0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_BMSK                                             0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_SHFT                                                0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_BMSK                                                0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_SHFT                                                 0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0002b00c)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_RMSK                                                                  0x7fffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_BMSK                                           0x7fff00
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_SHFT                                                0x8
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_BMSK                                                0xff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_SHFT                                                 0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b010)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b014)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b018)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_RMSK                                                                0x7fffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0x7fff00
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b01c)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b020)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b024)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_RMSK                                                                0x7fffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0x7fff00
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_1_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b028)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b02c)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b030)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_RMSK                                                                0x7fffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0x7fff00
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_2_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b034)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b038)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b03c)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_RMSK                                                                0x7fffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0x7fff00
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_3_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b040)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b044)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b048)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_RMSK                                                                0x7fffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0x7fff00
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_4_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b04c)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b050)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b054)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_RMSK                                                                0x7fffff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0x7fff00
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_TOP_QUPV3_TURING_IRQ_ENABLE_5_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0002d000)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_RMSK                                                                    0xffff
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_BMSK                                             0xffc0
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_SHFT                                                0x6
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_BMSK                                                0x3f
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_SHFT                                                 0x0

#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0002d004)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_RMSK                                                                    0xffff
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_BMSK                                             0xffc0
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_SHFT                                                0x6
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_BMSK                                                0x3f
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_SHFT                                                 0x0

#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0002d008)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_RMSK                                                                  0x7fffff
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_BMSK                                           0x7fff00
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_SHFT                                                0x8
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_BMSK                                                0xff
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_SHFT                                                 0x0

#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002d00c)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002d010)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_RMSK                                                                  0xffff
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                    0xffc0
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                       0x3f
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002d014)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_RMSK                                                                0x7fffff
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0x7fff00
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_TOP_QUPV3_CAMERA_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_ADDR                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0002e000)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_RMSK                                                                       0xffff
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_BMSK                                                0xffc0
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_GSI_INTR_SHFT                                                   0x6
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_BMSK                                                   0x3f
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_0_I_TOP_QUPV3_2_SE_INTR_SHFT                                                    0x0

#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_ADDR                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0002e004)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_RMSK                                                                       0xffff
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_BMSK                                                0xffc0
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_GSI_INTR_SHFT                                                   0x6
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_BMSK                                                   0x3f
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_1_I_TOP_QUPV3_1_SE_INTR_SHFT                                                    0x0

#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_ADDR                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0002e008)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_RMSK                                                                     0x7fffff
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_BMSK                                              0x7fff00
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_GSI_INTR_SHFT                                                   0x8
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_BMSK                                                   0xff
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_STATUS_REG_2_I_TOP_QUPV3_0_SE_INTR_SHFT                                                    0x0

#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0002e00c)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_RMSK                                                                     0xffff
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_BMSK                                       0xffc0
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_GSI_INTR_ENABLE_SHFT                                          0x6
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_BMSK                                          0x3f
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_0_I_TOP_QUPV3_2_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0002e010)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_RMSK                                                                     0xffff
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_BMSK                                       0xffc0
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_GSI_INTR_ENABLE_SHFT                                          0x6
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_BMSK                                          0x3f
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_1_I_TOP_QUPV3_1_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0002e014)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_RMSK                                                                   0x7fffff
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_IN          \
        in_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_ADDR)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_IN)
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_BMSK                                     0x7fff00
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_GSI_INTR_ENABLE_SHFT                                          0x8
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_BMSK                                          0xff
#define HWIO_TCSR_TOP_QUPV3_NPU_IRQ_ENABLE_0_REG_2_I_TOP_QUPV3_0_SE_INTR_ENABLE_SHFT                                           0x0

#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x00029060)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_RMSK                                                                   0xffffff
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_I_SSC_QUPV3_0_GSI_INTR_BMSK                                            0xffff00
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_I_SSC_QUPV3_0_GSI_INTR_SHFT                                                 0x8
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_I_SSC_QUPV3_0_SE_INTR_BMSK                                                 0xff
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_STATUS_REG_0_I_SSC_QUPV3_0_SE_INTR_SHFT                                                  0x0

#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029064)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_RMSK                                                                 0xffffff
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_I_SSC_QUPV3_0_GSI_INTR_ENABLE_BMSK                                   0xffff00
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_I_SSC_QUPV3_0_GSI_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_I_SSC_QUPV3_0_SE_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_0_REG_0_I_SSC_QUPV3_0_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029068)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_RMSK                                                                 0xffffff
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_IN          \
        in_dword(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR,v)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_ADDR,m,v,HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_IN)
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_I_SSC_QUPV3_0_GSI_INTR_ENABLE_BMSK                                   0xffff00
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_I_SSC_QUPV3_0_GSI_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_I_SSC_QUPV3_0_SE_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_SSC_QUPV3_LPASS_IRQ_ENABLE_1_REG_0_I_SSC_QUPV3_0_SE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0002b060)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_RMSK                                                                  0xffffff
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_I_SSC_QUPV3_0_GSI_INTR_BMSK                                           0xffff00
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_I_SSC_QUPV3_0_GSI_INTR_SHFT                                                0x8
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_I_SSC_QUPV3_0_SE_INTR_BMSK                                                0xff
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_STATUS_REG_0_I_SSC_QUPV3_0_SE_INTR_SHFT                                                 0x0

#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b064)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_RMSK                                                                0xffffff
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_I_SSC_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0xffff00
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_I_SSC_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_I_SSC_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_0_REG_0_I_SSC_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b068)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_RMSK                                                                0xffffff
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_IN          \
        in_dword(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR,v)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_ADDR,m,v,HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_IN)
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_I_SSC_QUPV3_0_GSI_INTR_ENABLE_BMSK                                  0xffff00
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_I_SSC_QUPV3_0_GSI_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_I_SSC_QUPV3_0_SE_INTR_ENABLE_BMSK                                       0xff
#define HWIO_TCSR_SSC_QUPV3_TURING_IRQ_ENABLE_1_REG_0_I_SSC_QUPV3_0_SE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00004000)
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_RMSK                                                                        0xffffffff
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SEC_INTR_BMSK                           0x80000000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SEC_INTR_SHFT                                 0x1f
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_BOOT_ROM_XPU_SEC_INTR_BMSK                                                  0x40000000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_BOOT_ROM_XPU_SEC_INTR_SHFT                                                        0x1e
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SEC_INTR_BMSK                               0x20000000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SEC_INTR_SHFT                                     0x1d
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_LLCC3_XPU_SEC_INTR_BMSK                                                     0x10000000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_LLCC3_XPU_SEC_INTR_SHFT                                                           0x1c
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_LLCC2_XPU_SEC_INTR_BMSK                                                      0x8000000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_LLCC2_XPU_SEC_INTR_SHFT                                                           0x1b
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_LLCC1_XPU_SEC_INTR_BMSK                                                      0x4000000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_LLCC1_XPU_SEC_INTR_SHFT                                                           0x1a
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_LLCC0_XPU_SEC_INTR_BMSK                                                      0x2000000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_LLCC0_XPU_SEC_INTR_SHFT                                                           0x19
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_UFS_XPU_SEC_INTR_BMSK                                                        0x1000000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_UFS_XPU_SEC_INTR_SHFT                                                             0x18
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_SEC_INTR_BMSK                                        0x800000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_SEC_INTR_SHFT                                            0x17
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SSC_SDC_XPU_SEC_INTR_BMSK                                                     0x400000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SSC_SDC_XPU_SEC_INTR_SHFT                                                         0x16
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_GCC_XPU_SEC_INTR_BMSK                                                         0x200000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_GCC_XPU_SEC_INTR_SHFT                                                             0x15
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_AOP_MPU_XPU_SEC_INTR_BMSK                                                     0x100000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_AOP_MPU_XPU_SEC_INTR_SHFT                                                         0x14
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QM_XPU_SEC_INTR_BMSK                                                           0x80000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QM_XPU_SEC_INTR_SHFT                                                              0x13
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QNM_SNOC_XPU_SEC_INTR_BMSK                                                     0x40000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QNM_SNOC_XPU_SEC_INTR_SHFT                                                        0x12
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QHS_CNOC_XPU_SEC_INTR_BMSK                                                     0x20000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QHS_CNOC_XPU_SEC_INTR_SHFT                                                        0x11
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QHM_AOSS_XPU_SEC_INTR_BMSK                                                     0x10000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QHM_AOSS_XPU_SEC_INTR_SHFT                                                        0x10
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SP_XPU_SEC_INTR_BMSK                                                            0x8000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SP_XPU_SEC_INTR_SHFT                                                               0xf
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_PIMEM_MPU_XPU_SEC_INTR_BMSK                                                     0x4000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_PIMEM_MPU_XPU_SEC_INTR_SHFT                                                        0xe
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_PIMEM_APU_XPU_SEC_INTR_BMSK                                                     0x2000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_PIMEM_APU_XPU_SEC_INTR_SHFT                                                        0xd
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SSC_Q6_XPU_SEC_INTR_BMSK                                                        0x1000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SSC_Q6_XPU_SEC_INTR_SHFT                                                           0xc
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SSC_XPU_SEC_INTR_BMSK                                                            0x800
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SSC_XPU_SEC_INTR_SHFT                                                              0xb
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SSC_QUP_XPU_SEC_INTR_BMSK                                                        0x400
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SSC_QUP_XPU_SEC_INTR_SHFT                                                          0xa
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SEC_CTRL_XPU_SEC_INTR_BMSK                                                       0x200
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_SEC_CTRL_XPU_SEC_INTR_SHFT                                                         0x9
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_DCC_XPU_SEC_INTR_BMSK                                                            0x100
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_DCC_XPU_SEC_INTR_SHFT                                                              0x8
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_OCIMEM_RPU_XPU_SEC_INTR_BMSK                                                      0x80
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_OCIMEM_RPU_XPU_SEC_INTR_SHFT                                                       0x7
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_CRYPTO0_XPU_SEC_INTR_BMSK                                                         0x40
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_CRYPTO0_XPU_SEC_INTR_SHFT                                                          0x6
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_TCSR_MUTEX_XPU_SEC_INTR_BMSK                                                      0x20
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_TCSR_MUTEX_XPU_SEC_INTR_SHFT                                                       0x5
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QUPV3_1_XPU_SEC_INTR_BMSK                                                         0x10
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QUPV3_1_XPU_SEC_INTR_SHFT                                                          0x4
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_TCSR_REGS_XPU_SEC_INTR_BMSK                                                        0x8
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_TCSR_REGS_XPU_SEC_INTR_SHFT                                                        0x3
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QUPV3_0_XPU_SEC_INTR_BMSK                                                          0x4
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_QUPV3_0_XPU_SEC_INTR_SHFT                                                          0x2
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_AOSS_MPU_XPU_SEC_INTR_BMSK                                                         0x2
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_AOSS_MPU_XPU_SEC_INTR_SHFT                                                         0x1
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_PMIC_ARB_XPU_SEC_INTR_BMSK                                                         0x1
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_PMIC_ARB_XPU_SEC_INTR_SHFT                                                         0x0

#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00004004)
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RMSK                                                                          0xffffff
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RESERVE_55_XPU_SEC_INTR_BMSK                                                  0x800000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RESERVE_55_XPU_SEC_INTR_SHFT                                                      0x17
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_4_SEC_INTR_BMSK                                                     0x400000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_4_SEC_INTR_SHFT                                                         0x16
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_3_SEC_INTR_BMSK                                                     0x200000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_3_SEC_INTR_SHFT                                                         0x15
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_2_SEC_INTR_BMSK                                                     0x100000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_2_SEC_INTR_SHFT                                                         0x14
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_1_SEC_INTR_BMSK                                                      0x80000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_1_SEC_INTR_SHFT                                                         0x13
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_0_SEC_INTR_BMSK                                                      0x40000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_LPASS_XPU_0_SEC_INTR_SHFT                                                         0x12
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_QSPI_XPU_SEC_INTR_BMSK                                                         0x20000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_QSPI_XPU_SEC_INTR_SHFT                                                            0x11
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_IPC_ROUTER_XPU_SEC_INTR_BMSK                                                   0x10000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_IPC_ROUTER_XPU_SEC_INTR_SHFT                                                      0x10
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_TLMM_NORTH_XPU_SEC_INTR_BMSK                                                    0x8000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_TLMM_NORTH_XPU_SEC_INTR_SHFT                                                       0xf
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RESERVE_46_XPU_SEC_INTR_BMSK                                                    0x4000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RESERVE_46_XPU_SEC_INTR_SHFT                                                       0xe
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_DDRSS_SHRM_XPU_SEC_INTR_BMSK                                                    0x2000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_DDRSS_SHRM_XPU_SEC_INTR_SHFT                                                       0xd
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_QUPV3_2_XPU_SEC_INTR_BMSK                                                       0x1000
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_QUPV3_2_XPU_SEC_INTR_SHFT                                                          0xc
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_IPA_XPU_SEC_INTR_BMSK                                                            0x800
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_IPA_XPU_SEC_INTR_SHFT                                                              0xb
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RESERVE_42_XPU_SEC_INTR_BMSK                                                     0x400
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RESERVE_42_XPU_SEC_INTR_SHFT                                                       0xa
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_TLMM_SOUTH_XPU_SEC_INTR_BMSK                                                     0x200
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_TLMM_SOUTH_XPU_SEC_INTR_SHFT                                                       0x9
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_TLMM_WEST_XPU_SEC_INTR_BMSK                                                      0x100
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_TLMM_WEST_XPU_SEC_INTR_SHFT                                                        0x8
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_MDSS_XPU_SEC_INTR_BMSK                                                            0x80
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_MDSS_XPU_SEC_INTR_SHFT                                                             0x7
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_UFS_CARD_ICE_XPU_SEC_INTR_BMSK                                                    0x40
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_UFS_CARD_ICE_XPU_SEC_INTR_SHFT                                                     0x6
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_TITAN_XPU_SEC_INTR_BMSK                                                           0x20
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_TITAN_XPU_SEC_INTR_SHFT                                                            0x5
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_SPDM_XPU_SEC_INTR_BMSK                                                            0x10
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_SPDM_XPU_SEC_INTR_SHFT                                                             0x4
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RESERVE_35_XPU_SEC_INTR_BMSK                                                       0x8
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RESERVE_35_XPU_SEC_INTR_SHFT                                                       0x3
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_QNM_AGGRE2_XPU_SEC_INTR_BMSK                                                       0x4
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_QNM_AGGRE2_XPU_SEC_INTR_SHFT                                                       0x2
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_QNM_AGGRE1_XPU_SEC_INTR_BMSK                                                       0x2
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_QNM_AGGRE1_XPU_SEC_INTR_SHFT                                                       0x1
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_OCIMEM_XPU3_XPU_SEC_INTR_BMSK                                                      0x1
#define HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_OCIMEM_XPU3_XPU_SEC_INTR_SHFT                                                      0x0

#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_ADDR                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x00004040)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_RMSK                                                                      0xffffffff
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SEC_INTR_ENABLE_BMSK                  0x80000000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SEC_INTR_ENABLE_SHFT                        0x1f
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_BOOT_ROM_XPU_SEC_INTR_ENABLE_BMSK                                         0x40000000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_BOOT_ROM_XPU_SEC_INTR_ENABLE_SHFT                                               0x1e
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SEC_INTR_ENABLE_BMSK                      0x20000000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SEC_INTR_ENABLE_SHFT                            0x1d
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_LLCC3_XPU_SEC_INTR_ENABLE_BMSK                                            0x10000000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_LLCC3_XPU_SEC_INTR_ENABLE_SHFT                                                  0x1c
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_LLCC2_XPU_SEC_INTR_ENABLE_BMSK                                             0x8000000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_LLCC2_XPU_SEC_INTR_ENABLE_SHFT                                                  0x1b
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_LLCC1_XPU_SEC_INTR_ENABLE_BMSK                                             0x4000000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_LLCC1_XPU_SEC_INTR_ENABLE_SHFT                                                  0x1a
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_LLCC0_XPU_SEC_INTR_ENABLE_BMSK                                             0x2000000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_LLCC0_XPU_SEC_INTR_ENABLE_SHFT                                                  0x19
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_UFS_XPU_SEC_INTR_ENABLE_BMSK                                               0x1000000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_UFS_XPU_SEC_INTR_ENABLE_SHFT                                                    0x18
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_SEC_INTR_ENABLE_BMSK                               0x800000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_SEC_INTR_ENABLE_SHFT                                   0x17
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_XPU_SEC_INTR_ENABLE_BMSK                                            0x400000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_XPU_SEC_INTR_ENABLE_SHFT                                                0x16
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_GCC_XPU_SEC_INTR_ENABLE_BMSK                                                0x200000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_GCC_XPU_SEC_INTR_ENABLE_SHFT                                                    0x15
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_AOP_MPU_XPU_SEC_INTR_ENABLE_BMSK                                            0x100000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_AOP_MPU_XPU_SEC_INTR_ENABLE_SHFT                                                0x14
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QM_XPU_SEC_INTR_ENABLE_BMSK                                                  0x80000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QM_XPU_SEC_INTR_ENABLE_SHFT                                                     0x13
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QNM_SNOC_XPU_SEC_INTR_ENABLE_BMSK                                            0x40000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QNM_SNOC_XPU_SEC_INTR_ENABLE_SHFT                                               0x12
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QHS_CNOC_XPU_SEC_INTR_ENABLE_BMSK                                            0x20000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QHS_CNOC_XPU_SEC_INTR_ENABLE_SHFT                                               0x11
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QHM_AOSS_XPU_SEC_INTR_ENABLE_BMSK                                            0x10000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QHM_AOSS_XPU_SEC_INTR_ENABLE_SHFT                                               0x10
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SP_XPU_SEC_INTR_ENABLE_BMSK                                                   0x8000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SP_XPU_SEC_INTR_ENABLE_SHFT                                                      0xf
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_PIMEM_MPU_XPU_SEC_INTR_ENABLE_BMSK                                            0x4000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_PIMEM_MPU_XPU_SEC_INTR_ENABLE_SHFT                                               0xe
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_PIMEM_APU_XPU_SEC_INTR_ENABLE_BMSK                                            0x2000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_PIMEM_APU_XPU_SEC_INTR_ENABLE_SHFT                                               0xd
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SSC_Q6_XPU_SEC_INTR_ENABLE_BMSK                                               0x1000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SSC_Q6_XPU_SEC_INTR_ENABLE_SHFT                                                  0xc
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SSC_XPU_SEC_INTR_ENABLE_BMSK                                                   0x800
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SSC_XPU_SEC_INTR_ENABLE_SHFT                                                     0xb
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SSC_QUP_XPU_SEC_INTR_ENABLE_BMSK                                               0x400
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SSC_QUP_XPU_SEC_INTR_ENABLE_SHFT                                                 0xa
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SEC_CTRL_XPU_SEC_INTR_ENABLE_BMSK                                              0x200
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_SEC_CTRL_XPU_SEC_INTR_ENABLE_SHFT                                                0x9
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_DCC_XPU_SEC_INTR_ENABLE_BMSK                                                   0x100
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_DCC_XPU_SEC_INTR_ENABLE_SHFT                                                     0x8
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_OCIMEM_RPU_XPU_SEC_INTR_ENABLE_BMSK                                             0x80
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_OCIMEM_RPU_XPU_SEC_INTR_ENABLE_SHFT                                              0x7
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_XPU_SEC_INTR_ENABLE_BMSK                                                0x40
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_XPU_SEC_INTR_ENABLE_SHFT                                                 0x6
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_TCSR_MUTEX_XPU_SEC_INTR_ENABLE_BMSK                                             0x20
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_TCSR_MUTEX_XPU_SEC_INTR_ENABLE_SHFT                                              0x5
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_XPU_SEC_INTR_ENABLE_BMSK                                                0x10
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_XPU_SEC_INTR_ENABLE_SHFT                                                 0x4
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_TCSR_REGS_XPU_SEC_INTR_ENABLE_BMSK                                               0x8
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_TCSR_REGS_XPU_SEC_INTR_ENABLE_SHFT                                               0x3
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_XPU_SEC_INTR_ENABLE_BMSK                                                 0x4
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_XPU_SEC_INTR_ENABLE_SHFT                                                 0x2
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_AOSS_MPU_XPU_SEC_INTR_ENABLE_BMSK                                                0x2
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_AOSS_MPU_XPU_SEC_INTR_ENABLE_SHFT                                                0x1
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_PMIC_ARB_XPU_SEC_INTR_ENABLE_BMSK                                                0x1
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_PMIC_ARB_XPU_SEC_INTR_ENABLE_SHFT                                                0x0

#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_ADDR                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x00004044)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RMSK                                                                        0xffffff
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RESERVE_55_XPU_SEC_INTR_ENABLE_BMSK                                         0x800000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RESERVE_55_XPU_SEC_INTR_ENABLE_SHFT                                             0x17
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_4_SEC_INTR_ENABLE_BMSK                                            0x400000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_4_SEC_INTR_ENABLE_SHFT                                                0x16
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_3_SEC_INTR_ENABLE_BMSK                                            0x200000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_3_SEC_INTR_ENABLE_SHFT                                                0x15
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_2_SEC_INTR_ENABLE_BMSK                                            0x100000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_2_SEC_INTR_ENABLE_SHFT                                                0x14
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_1_SEC_INTR_ENABLE_BMSK                                             0x80000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_1_SEC_INTR_ENABLE_SHFT                                                0x13
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_0_SEC_INTR_ENABLE_BMSK                                             0x40000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_0_SEC_INTR_ENABLE_SHFT                                                0x12
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_QSPI_XPU_SEC_INTR_ENABLE_BMSK                                                0x20000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_QSPI_XPU_SEC_INTR_ENABLE_SHFT                                                   0x11
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_IPC_ROUTER_XPU_SEC_INTR_ENABLE_BMSK                                          0x10000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_IPC_ROUTER_XPU_SEC_INTR_ENABLE_SHFT                                             0x10
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_TLMM_NORTH_XPU_SEC_INTR_ENABLE_BMSK                                           0x8000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_TLMM_NORTH_XPU_SEC_INTR_ENABLE_SHFT                                              0xf
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RESERVE_46_XPU_SEC_INTR_ENABLE_BMSK                                           0x4000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RESERVE_46_XPU_SEC_INTR_ENABLE_SHFT                                              0xe
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_DDRSS_SHRM_XPU_SEC_INTR_ENABLE_BMSK                                           0x2000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_DDRSS_SHRM_XPU_SEC_INTR_ENABLE_SHFT                                              0xd
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_QUPV3_2_XPU_SEC_INTR_ENABLE_BMSK                                              0x1000
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_QUPV3_2_XPU_SEC_INTR_ENABLE_SHFT                                                 0xc
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_IPA_XPU_SEC_INTR_ENABLE_BMSK                                                   0x800
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_IPA_XPU_SEC_INTR_ENABLE_SHFT                                                     0xb
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RESERVE_42_XPU_SEC_INTR_ENABLE_BMSK                                            0x400
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RESERVE_42_XPU_SEC_INTR_ENABLE_SHFT                                              0xa
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_TLMM_SOUTH_XPU_SEC_INTR_ENABLE_BMSK                                            0x200
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_TLMM_SOUTH_XPU_SEC_INTR_ENABLE_SHFT                                              0x9
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_TLMM_WEST_XPU_SEC_INTR_ENABLE_BMSK                                             0x100
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_TLMM_WEST_XPU_SEC_INTR_ENABLE_SHFT                                               0x8
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_MDSS_XPU_SEC_INTR_ENABLE_BMSK                                                   0x80
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_MDSS_XPU_SEC_INTR_ENABLE_SHFT                                                    0x7
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_UFS_CARD_ICE_XPU_SEC_INTR_ENABLE_BMSK                                           0x40
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_UFS_CARD_ICE_XPU_SEC_INTR_ENABLE_SHFT                                            0x6
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_TITAN_XPU_SEC_INTR_ENABLE_BMSK                                                  0x20
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_TITAN_XPU_SEC_INTR_ENABLE_SHFT                                                   0x5
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_SPDM_XPU_SEC_INTR_ENABLE_BMSK                                                   0x10
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_SPDM_XPU_SEC_INTR_ENABLE_SHFT                                                    0x4
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RESERVE_35_XPU_SEC_INTR_ENABLE_BMSK                                              0x8
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RESERVE_35_XPU_SEC_INTR_ENABLE_SHFT                                              0x3
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_QNM_AGGRE2_XPU_SEC_INTR_ENABLE_BMSK                                              0x4
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_QNM_AGGRE2_XPU_SEC_INTR_ENABLE_SHFT                                              0x2
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_QNM_AGGRE1_XPU_SEC_INTR_ENABLE_BMSK                                              0x2
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_QNM_AGGRE1_XPU_SEC_INTR_ENABLE_SHFT                                              0x1
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_OCIMEM_XPU3_XPU_SEC_INTR_ENABLE_BMSK                                             0x1
#define HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_OCIMEM_XPU3_XPU_SEC_INTR_ENABLE_SHFT                                             0x0

#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_ADDR                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x00002000)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_RMSK                                                                    0xffffffff
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR_BMSK                   0x80000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR_SHFT                         0x1f
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_BOOT_ROM_XPU_NON_SEC_INTR_BMSK                                          0x40000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_BOOT_ROM_XPU_NON_SEC_INTR_SHFT                                                0x1e
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR_BMSK                       0x20000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR_SHFT                             0x1d
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_LLCC3_XPU_NON_SEC_INTR_BMSK                                             0x10000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_LLCC3_XPU_NON_SEC_INTR_SHFT                                                   0x1c
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_LLCC2_XPU_NON_SEC_INTR_BMSK                                              0x8000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_LLCC2_XPU_NON_SEC_INTR_SHFT                                                   0x1b
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_LLCC1_XPU_NON_SEC_INTR_BMSK                                              0x4000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_LLCC1_XPU_NON_SEC_INTR_SHFT                                                   0x1a
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_LLCC0_XPU_NON_SEC_INTR_BMSK                                              0x2000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_LLCC0_XPU_NON_SEC_INTR_SHFT                                                   0x19
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_UFS_XPU_NON_SEC_INTR_BMSK                                                0x1000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_UFS_XPU_NON_SEC_INTR_SHFT                                                     0x18
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_NON_SEC_INTR_BMSK                                0x800000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_NON_SEC_INTR_SHFT                                    0x17
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SSC_SDC_XPU_NON_SEC_INTR_BMSK                                             0x400000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SSC_SDC_XPU_NON_SEC_INTR_SHFT                                                 0x16
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_GCC_XPU_NON_SEC_INTR_BMSK                                                 0x200000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_GCC_XPU_NON_SEC_INTR_SHFT                                                     0x15
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_AOP_MPU_XPU_NON_SEC_INTR_BMSK                                             0x100000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_AOP_MPU_XPU_NON_SEC_INTR_SHFT                                                 0x14
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QM_XPU_NON_SEC_INTR_BMSK                                                   0x80000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QM_XPU_NON_SEC_INTR_SHFT                                                      0x13
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QNM_SNOC_XPU_NON_SEC_INTR_BMSK                                             0x40000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QNM_SNOC_XPU_NON_SEC_INTR_SHFT                                                0x12
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QHS_CNOC_XPU_NON_SEC_INTR_BMSK                                             0x20000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QHS_CNOC_XPU_NON_SEC_INTR_SHFT                                                0x11
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QHM_AOSS_XPU_NON_SEC_INTR_BMSK                                             0x10000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QHM_AOSS_XPU_NON_SEC_INTR_SHFT                                                0x10
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SP_XPU_NON_SEC_INTR_BMSK                                                    0x8000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SP_XPU_NON_SEC_INTR_SHFT                                                       0xf
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_PIMEM_MPU_XPU_NON_SEC_INTR_BMSK                                             0x4000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_PIMEM_MPU_XPU_NON_SEC_INTR_SHFT                                                0xe
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_PIMEM_APU_XPU_NON_SEC_INTR_BMSK                                             0x2000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_PIMEM_APU_XPU_NON_SEC_INTR_SHFT                                                0xd
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SSC_Q6_XPU_NON_SEC_INTR_BMSK                                                0x1000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SSC_Q6_XPU_NON_SEC_INTR_SHFT                                                   0xc
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SSC_XPU_NON_SEC_INTR_BMSK                                                    0x800
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SSC_XPU_NON_SEC_INTR_SHFT                                                      0xb
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SSC_QUP_XPU_NON_SEC_INTR_BMSK                                                0x400
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SSC_QUP_XPU_NON_SEC_INTR_SHFT                                                  0xa
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SEC_CTRL_XPU_NON_SEC_INTR_BMSK                                               0x200
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_SEC_CTRL_XPU_NON_SEC_INTR_SHFT                                                 0x9
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_DCC_XPU_NON_SEC_INTR_BMSK                                                    0x100
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_DCC_XPU_NON_SEC_INTR_SHFT                                                      0x8
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_OCIMEM_RPU_XPU_NON_SEC_INTR_BMSK                                              0x80
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_OCIMEM_RPU_XPU_NON_SEC_INTR_SHFT                                               0x7
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_CRYPTO0_XPU_NON_SEC_INTR_BMSK                                                 0x40
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_CRYPTO0_XPU_NON_SEC_INTR_SHFT                                                  0x6
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_TCSR_MUTEX_XPU_NON_SEC_INTR_BMSK                                              0x20
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_TCSR_MUTEX_XPU_NON_SEC_INTR_SHFT                                               0x5
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QUPV3_1_XPU_NON_SEC_INTR_BMSK                                                 0x10
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QUPV3_1_XPU_NON_SEC_INTR_SHFT                                                  0x4
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_TCSR_REGS_XPU_NON_SEC_INTR_BMSK                                                0x8
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_TCSR_REGS_XPU_NON_SEC_INTR_SHFT                                                0x3
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QUPV3_0_XPU_NON_SEC_INTR_BMSK                                                  0x4
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_QUPV3_0_XPU_NON_SEC_INTR_SHFT                                                  0x2
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_AOSS_MPU_XPU_NON_SEC_INTR_BMSK                                                 0x2
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_AOSS_MPU_XPU_NON_SEC_INTR_SHFT                                                 0x1
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_PMIC_ARB_XPU_NON_SEC_INTR_BMSK                                                 0x1
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_PMIC_ARB_XPU_NON_SEC_INTR_SHFT                                                 0x0

#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_ADDR                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x00002004)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RMSK                                                                      0xffffff
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RESERVE_55_XPU_NON_SEC_INTR_BMSK                                          0x800000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RESERVE_55_XPU_NON_SEC_INTR_SHFT                                              0x17
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_4_NON_SEC_INTR_BMSK                                             0x400000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_4_NON_SEC_INTR_SHFT                                                 0x16
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_3_NON_SEC_INTR_BMSK                                             0x200000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_3_NON_SEC_INTR_SHFT                                                 0x15
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_2_NON_SEC_INTR_BMSK                                             0x100000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_2_NON_SEC_INTR_SHFT                                                 0x14
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_1_NON_SEC_INTR_BMSK                                              0x80000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_1_NON_SEC_INTR_SHFT                                                 0x13
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_0_NON_SEC_INTR_BMSK                                              0x40000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_LPASS_XPU_0_NON_SEC_INTR_SHFT                                                 0x12
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_QSPI_XPU_NON_SEC_INTR_BMSK                                                 0x20000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_QSPI_XPU_NON_SEC_INTR_SHFT                                                    0x11
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_IPC_ROUTER_XPU_NON_SEC_INTR_BMSK                                           0x10000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_IPC_ROUTER_XPU_NON_SEC_INTR_SHFT                                              0x10
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_TLMM_NORTH_XPU_NON_SEC_INTR_BMSK                                            0x8000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_TLMM_NORTH_XPU_NON_SEC_INTR_SHFT                                               0xf
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RESERVE_46_XPU_NON_SEC_INTR_BMSK                                            0x4000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RESERVE_46_XPU_NON_SEC_INTR_SHFT                                               0xe
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_DDRSS_SHRM_XPU_NON_SEC_INTR_BMSK                                            0x2000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_DDRSS_SHRM_XPU_NON_SEC_INTR_SHFT                                               0xd
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_QUPV3_2_XPU_NON_SEC_INTR_BMSK                                               0x1000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_QUPV3_2_XPU_NON_SEC_INTR_SHFT                                                  0xc
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_IPA_XPU_NON_SEC_INTR_BMSK                                                    0x800
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_IPA_XPU_NON_SEC_INTR_SHFT                                                      0xb
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RESERVE_42_XPU_NON_SEC_INTR_BMSK                                             0x400
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RESERVE_42_XPU_NON_SEC_INTR_SHFT                                               0xa
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_TLMM_SOUTH_XPU_NON_SEC_INTR_BMSK                                             0x200
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_TLMM_SOUTH_XPU_NON_SEC_INTR_SHFT                                               0x9
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_TLMM_WEST_XPU_NON_SEC_INTR_BMSK                                              0x100
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_TLMM_WEST_XPU_NON_SEC_INTR_SHFT                                                0x8
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_MDSS_XPU_NON_SEC_INTR_BMSK                                                    0x80
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_MDSS_XPU_NON_SEC_INTR_SHFT                                                     0x7
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_UFS_CARD_ICE_XPU_NON_SEC_INTR_BMSK                                            0x40
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_UFS_CARD_ICE_XPU_NON_SEC_INTR_SHFT                                             0x6
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_TITAN_XPU_NON_SEC_INTR_BMSK                                                   0x20
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_TITAN_XPU_NON_SEC_INTR_SHFT                                                    0x5
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_SPDM_XPU_NON_SEC_INTR_BMSK                                                    0x10
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_SPDM_XPU_NON_SEC_INTR_SHFT                                                     0x4
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RESERVE_35_XPU_NON_SEC_INTR_BMSK                                               0x8
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RESERVE_35_XPU_NON_SEC_INTR_SHFT                                               0x3
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_QNM_AGGRE2_XPU_NON_SEC_INTR_BMSK                                               0x4
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_QNM_AGGRE2_XPU_NON_SEC_INTR_SHFT                                               0x2
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_QNM_AGGRE1_XPU_NON_SEC_INTR_BMSK                                               0x2
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_QNM_AGGRE1_XPU_NON_SEC_INTR_SHFT                                               0x1
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_OCIMEM_XPU3_XPU_NON_SEC_INTR_BMSK                                              0x1
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_OCIMEM_XPU3_XPU_NON_SEC_INTR_SHFT                                              0x0

#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00002040)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_RMSK                                                                  0xffffffff
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR_ENABLE_BMSK          0x80000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR_ENABLE_SHFT                0x1f
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_BOOT_ROM_XPU_NON_SEC_INTR_ENABLE_BMSK                                 0x40000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_BOOT_ROM_XPU_NON_SEC_INTR_ENABLE_SHFT                                       0x1e
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR_ENABLE_BMSK              0x20000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR_ENABLE_SHFT                    0x1d
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_LLCC3_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x10000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_LLCC3_XPU_NON_SEC_INTR_ENABLE_SHFT                                          0x1c
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_LLCC2_XPU_NON_SEC_INTR_ENABLE_BMSK                                     0x8000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_LLCC2_XPU_NON_SEC_INTR_ENABLE_SHFT                                          0x1b
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_LLCC1_XPU_NON_SEC_INTR_ENABLE_BMSK                                     0x4000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_LLCC1_XPU_NON_SEC_INTR_ENABLE_SHFT                                          0x1a
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_LLCC0_XPU_NON_SEC_INTR_ENABLE_BMSK                                     0x2000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_LLCC0_XPU_NON_SEC_INTR_ENABLE_SHFT                                          0x19
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_UFS_XPU_NON_SEC_INTR_ENABLE_BMSK                                       0x1000000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_UFS_XPU_NON_SEC_INTR_ENABLE_SHFT                                            0x18
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_NON_SEC_INTR_ENABLE_BMSK                       0x800000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_NON_SEC_INTR_ENABLE_SHFT                           0x17
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x400000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_XPU_NON_SEC_INTR_ENABLE_SHFT                                        0x16
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_GCC_XPU_NON_SEC_INTR_ENABLE_BMSK                                        0x200000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_GCC_XPU_NON_SEC_INTR_ENABLE_SHFT                                            0x15
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_AOP_MPU_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x100000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_AOP_MPU_XPU_NON_SEC_INTR_ENABLE_SHFT                                        0x14
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QM_XPU_NON_SEC_INTR_ENABLE_BMSK                                          0x80000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QM_XPU_NON_SEC_INTR_ENABLE_SHFT                                             0x13
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QNM_SNOC_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x40000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QNM_SNOC_XPU_NON_SEC_INTR_ENABLE_SHFT                                       0x12
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QHS_CNOC_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x20000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QHS_CNOC_XPU_NON_SEC_INTR_ENABLE_SHFT                                       0x11
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QHM_AOSS_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x10000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QHM_AOSS_XPU_NON_SEC_INTR_ENABLE_SHFT                                       0x10
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SP_XPU_NON_SEC_INTR_ENABLE_BMSK                                           0x8000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SP_XPU_NON_SEC_INTR_ENABLE_SHFT                                              0xf
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_PIMEM_MPU_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x4000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_PIMEM_MPU_XPU_NON_SEC_INTR_ENABLE_SHFT                                       0xe
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_PIMEM_APU_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x2000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_PIMEM_APU_XPU_NON_SEC_INTR_ENABLE_SHFT                                       0xd
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_Q6_XPU_NON_SEC_INTR_ENABLE_BMSK                                       0x1000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_Q6_XPU_NON_SEC_INTR_ENABLE_SHFT                                          0xc
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_XPU_NON_SEC_INTR_ENABLE_BMSK                                           0x800
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_XPU_NON_SEC_INTR_ENABLE_SHFT                                             0xb
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_QUP_XPU_NON_SEC_INTR_ENABLE_BMSK                                       0x400
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_QUP_XPU_NON_SEC_INTR_ENABLE_SHFT                                         0xa
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SEC_CTRL_XPU_NON_SEC_INTR_ENABLE_BMSK                                      0x200
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_SEC_CTRL_XPU_NON_SEC_INTR_ENABLE_SHFT                                        0x9
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_DCC_XPU_NON_SEC_INTR_ENABLE_BMSK                                           0x100
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_DCC_XPU_NON_SEC_INTR_ENABLE_SHFT                                             0x8
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_OCIMEM_RPU_XPU_NON_SEC_INTR_ENABLE_BMSK                                     0x80
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_OCIMEM_RPU_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0x7
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_XPU_NON_SEC_INTR_ENABLE_BMSK                                        0x40
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_XPU_NON_SEC_INTR_ENABLE_SHFT                                         0x6
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_TCSR_MUTEX_XPU_NON_SEC_INTR_ENABLE_BMSK                                     0x20
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_TCSR_MUTEX_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0x5
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_XPU_NON_SEC_INTR_ENABLE_BMSK                                        0x10
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_XPU_NON_SEC_INTR_ENABLE_SHFT                                         0x4
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_TCSR_REGS_XPU_NON_SEC_INTR_ENABLE_BMSK                                       0x8
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_TCSR_REGS_XPU_NON_SEC_INTR_ENABLE_SHFT                                       0x3
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_XPU_NON_SEC_INTR_ENABLE_BMSK                                         0x4
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_XPU_NON_SEC_INTR_ENABLE_SHFT                                         0x2
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_AOSS_MPU_XPU_NON_SEC_INTR_ENABLE_BMSK                                        0x2
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_AOSS_MPU_XPU_NON_SEC_INTR_ENABLE_SHFT                                        0x1
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_PMIC_ARB_XPU_NON_SEC_INTR_ENABLE_BMSK                                        0x1
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_PMIC_ARB_XPU_NON_SEC_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00002044)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RMSK                                                                    0xffffff
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RESERVE_55_XPU_NON_SEC_INTR_ENABLE_BMSK                                 0x800000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RESERVE_55_XPU_NON_SEC_INTR_ENABLE_SHFT                                     0x17
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_4_NON_SEC_INTR_ENABLE_BMSK                                    0x400000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_4_NON_SEC_INTR_ENABLE_SHFT                                        0x16
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_3_NON_SEC_INTR_ENABLE_BMSK                                    0x200000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_3_NON_SEC_INTR_ENABLE_SHFT                                        0x15
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_2_NON_SEC_INTR_ENABLE_BMSK                                    0x100000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_2_NON_SEC_INTR_ENABLE_SHFT                                        0x14
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_1_NON_SEC_INTR_ENABLE_BMSK                                     0x80000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_1_NON_SEC_INTR_ENABLE_SHFT                                        0x13
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_0_NON_SEC_INTR_ENABLE_BMSK                                     0x40000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_LPASS_XPU_0_NON_SEC_INTR_ENABLE_SHFT                                        0x12
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_QSPI_XPU_NON_SEC_INTR_ENABLE_BMSK                                        0x20000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_QSPI_XPU_NON_SEC_INTR_ENABLE_SHFT                                           0x11
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_IPC_ROUTER_XPU_NON_SEC_INTR_ENABLE_BMSK                                  0x10000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_IPC_ROUTER_XPU_NON_SEC_INTR_ENABLE_SHFT                                     0x10
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_TLMM_NORTH_XPU_NON_SEC_INTR_ENABLE_BMSK                                   0x8000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_TLMM_NORTH_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0xf
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RESERVE_46_XPU_NON_SEC_INTR_ENABLE_BMSK                                   0x4000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RESERVE_46_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0xe
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_DDRSS_SHRM_XPU_NON_SEC_INTR_ENABLE_BMSK                                   0x2000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_DDRSS_SHRM_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0xd
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_QUPV3_2_XPU_NON_SEC_INTR_ENABLE_BMSK                                      0x1000
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_QUPV3_2_XPU_NON_SEC_INTR_ENABLE_SHFT                                         0xc
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_IPA_XPU_NON_SEC_INTR_ENABLE_BMSK                                           0x800
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_IPA_XPU_NON_SEC_INTR_ENABLE_SHFT                                             0xb
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RESERVE_42_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x400
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RESERVE_42_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0xa
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_TLMM_SOUTH_XPU_NON_SEC_INTR_ENABLE_BMSK                                    0x200
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_TLMM_SOUTH_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0x9
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_TLMM_WEST_XPU_NON_SEC_INTR_ENABLE_BMSK                                     0x100
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_TLMM_WEST_XPU_NON_SEC_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_MDSS_XPU_NON_SEC_INTR_ENABLE_BMSK                                           0x80
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_MDSS_XPU_NON_SEC_INTR_ENABLE_SHFT                                            0x7
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_UFS_CARD_ICE_XPU_NON_SEC_INTR_ENABLE_BMSK                                   0x40
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_UFS_CARD_ICE_XPU_NON_SEC_INTR_ENABLE_SHFT                                    0x6
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_TITAN_XPU_NON_SEC_INTR_ENABLE_BMSK                                          0x20
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_TITAN_XPU_NON_SEC_INTR_ENABLE_SHFT                                           0x5
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_SPDM_XPU_NON_SEC_INTR_ENABLE_BMSK                                           0x10
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_SPDM_XPU_NON_SEC_INTR_ENABLE_SHFT                                            0x4
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RESERVE_35_XPU_NON_SEC_INTR_ENABLE_BMSK                                      0x8
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RESERVE_35_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0x3
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_QNM_AGGRE2_XPU_NON_SEC_INTR_ENABLE_BMSK                                      0x4
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_QNM_AGGRE2_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0x2
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_QNM_AGGRE1_XPU_NON_SEC_INTR_ENABLE_BMSK                                      0x2
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_QNM_AGGRE1_XPU_NON_SEC_INTR_ENABLE_SHFT                                      0x1
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_OCIMEM_XPU3_XPU_NON_SEC_INTR_ENABLE_BMSK                                     0x1
#define HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_OCIMEM_XPU3_XPU_NON_SEC_INTR_ENABLE_SHFT                                     0x0

#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00006000)
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_RMSK                                                                        0xffffffff
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_MSA_INTR_BMSK                           0x80000000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_MSA_INTR_SHFT                                 0x1f
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_BOOT_ROM_XPU_MSA_INTR_BMSK                                                  0x40000000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_BOOT_ROM_XPU_MSA_INTR_SHFT                                                        0x1e
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_MSA_INTR_BMSK                               0x20000000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_MSA_INTR_SHFT                                     0x1d
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_LLCC3_XPU_MSA_INTR_BMSK                                                     0x10000000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_LLCC3_XPU_MSA_INTR_SHFT                                                           0x1c
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_LLCC2_XPU_MSA_INTR_BMSK                                                      0x8000000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_LLCC2_XPU_MSA_INTR_SHFT                                                           0x1b
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_LLCC1_XPU_MSA_INTR_BMSK                                                      0x4000000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_LLCC1_XPU_MSA_INTR_SHFT                                                           0x1a
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_LLCC0_XPU_MSA_INTR_BMSK                                                      0x2000000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_LLCC0_XPU_MSA_INTR_SHFT                                                           0x19
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_UFS_XPU_MSA_INTR_BMSK                                                        0x1000000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_UFS_XPU_MSA_INTR_SHFT                                                             0x18
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_MSA_INTR_BMSK                                        0x800000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_MSA_INTR_SHFT                                            0x17
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SSC_SDC_XPU_MSA_INTR_BMSK                                                     0x400000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SSC_SDC_XPU_MSA_INTR_SHFT                                                         0x16
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_GCC_XPU_MSA_INTR_BMSK                                                         0x200000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_GCC_XPU_MSA_INTR_SHFT                                                             0x15
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_AOP_MPU_XPU_MSA_INTR_BMSK                                                     0x100000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_AOP_MPU_XPU_MSA_INTR_SHFT                                                         0x14
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QM_XPU_MSA_INTR_BMSK                                                           0x80000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QM_XPU_MSA_INTR_SHFT                                                              0x13
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QNM_SNOC_XPU_MSA_INTR_BMSK                                                     0x40000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QNM_SNOC_XPU_MSA_INTR_SHFT                                                        0x12
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QHS_CNOC_XPU_MSA_INTR_BMSK                                                     0x20000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QHS_CNOC_XPU_MSA_INTR_SHFT                                                        0x11
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QHM_AOSS_XPU_MSA_INTR_BMSK                                                     0x10000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QHM_AOSS_XPU_MSA_INTR_SHFT                                                        0x10
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SP_XPU_MSA_INTR_BMSK                                                            0x8000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SP_XPU_MSA_INTR_SHFT                                                               0xf
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_PIMEM_MPU_XPU_MSA_INTR_BMSK                                                     0x4000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_PIMEM_MPU_XPU_MSA_INTR_SHFT                                                        0xe
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_PIMEM_APU_XPU_MSA_INTR_BMSK                                                     0x2000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_PIMEM_APU_XPU_MSA_INTR_SHFT                                                        0xd
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SSC_Q6_XPU_MSA_INTR_BMSK                                                        0x1000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SSC_Q6_XPU_MSA_INTR_SHFT                                                           0xc
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SSC_XPU_MSA_INTR_BMSK                                                            0x800
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SSC_XPU_MSA_INTR_SHFT                                                              0xb
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SSC_QUP_XPU_MSA_INTR_BMSK                                                        0x400
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SSC_QUP_XPU_MSA_INTR_SHFT                                                          0xa
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SEC_CTRL_XPU_MSA_INTR_BMSK                                                       0x200
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_SEC_CTRL_XPU_MSA_INTR_SHFT                                                         0x9
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_DCC_XPU_MSA_INTR_BMSK                                                            0x100
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_DCC_XPU_MSA_INTR_SHFT                                                              0x8
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_OCIMEM_RPU_XPU_MSA_INTR_BMSK                                                      0x80
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_OCIMEM_RPU_XPU_MSA_INTR_SHFT                                                       0x7
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_CRYPTO0_XPU_MSA_INTR_BMSK                                                         0x40
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_CRYPTO0_XPU_MSA_INTR_SHFT                                                          0x6
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_TCSR_MUTEX_XPU_MSA_INTR_BMSK                                                      0x20
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_TCSR_MUTEX_XPU_MSA_INTR_SHFT                                                       0x5
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QUPV3_1_XPU_MSA_INTR_BMSK                                                         0x10
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QUPV3_1_XPU_MSA_INTR_SHFT                                                          0x4
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_TCSR_REGS_XPU_MSA_INTR_BMSK                                                        0x8
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_TCSR_REGS_XPU_MSA_INTR_SHFT                                                        0x3
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QUPV3_0_XPU_MSA_INTR_BMSK                                                          0x4
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_QUPV3_0_XPU_MSA_INTR_SHFT                                                          0x2
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_AOSS_MPU_XPU_MSA_INTR_BMSK                                                         0x2
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_AOSS_MPU_XPU_MSA_INTR_SHFT                                                         0x1
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_PMIC_ARB_XPU_MSA_INTR_BMSK                                                         0x1
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_0_PMIC_ARB_XPU_MSA_INTR_SHFT                                                         0x0

#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00006004)
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RMSK                                                                          0xffffff
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RESERVE_55_XPU_MSA_INTR_BMSK                                                  0x800000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RESERVE_55_XPU_MSA_INTR_SHFT                                                      0x17
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_4_MSA_INTR_BMSK                                                     0x400000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_4_MSA_INTR_SHFT                                                         0x16
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_3_MSA_INTR_BMSK                                                     0x200000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_3_MSA_INTR_SHFT                                                         0x15
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_2_MSA_INTR_BMSK                                                     0x100000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_2_MSA_INTR_SHFT                                                         0x14
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_1_MSA_INTR_BMSK                                                      0x80000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_1_MSA_INTR_SHFT                                                         0x13
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_0_MSA_INTR_BMSK                                                      0x40000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_LPASS_XPU_0_MSA_INTR_SHFT                                                         0x12
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_QSPI_XPU_MSA_INTR_BMSK                                                         0x20000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_QSPI_XPU_MSA_INTR_SHFT                                                            0x11
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_IPC_ROUTER_XPU_MSA_INTR_BMSK                                                   0x10000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_IPC_ROUTER_XPU_MSA_INTR_SHFT                                                      0x10
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_TLMM_NORTH_XPU_MSA_INTR_BMSK                                                    0x8000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_TLMM_NORTH_XPU_MSA_INTR_SHFT                                                       0xf
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RESERVE_46_XPU_MSA_INTR_BMSK                                                    0x4000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RESERVE_46_XPU_MSA_INTR_SHFT                                                       0xe
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_DDRSS_SHRM_XPU_MSA_INTR_BMSK                                                    0x2000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_DDRSS_SHRM_XPU_MSA_INTR_SHFT                                                       0xd
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_QUPV3_2_XPU_MSA_INTR_BMSK                                                       0x1000
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_QUPV3_2_XPU_MSA_INTR_SHFT                                                          0xc
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_IPA_XPU_MSA_INTR_BMSK                                                            0x800
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_IPA_XPU_MSA_INTR_SHFT                                                              0xb
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RESERVE_42_XPU_MSA_INTR_BMSK                                                     0x400
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RESERVE_42_XPU_MSA_INTR_SHFT                                                       0xa
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_TLMM_SOUTH_XPU_MSA_INTR_BMSK                                                     0x200
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_TLMM_SOUTH_XPU_MSA_INTR_SHFT                                                       0x9
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_TLMM_WEST_XPU_MSA_INTR_BMSK                                                      0x100
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_TLMM_WEST_XPU_MSA_INTR_SHFT                                                        0x8
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_MDSS_XPU_MSA_INTR_BMSK                                                            0x80
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_MDSS_XPU_MSA_INTR_SHFT                                                             0x7
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_UFS_CARD_ICE_XPU_MSA_INTR_BMSK                                                    0x40
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_UFS_CARD_ICE_XPU_MSA_INTR_SHFT                                                     0x6
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_TITAN_XPU_MSA_INTR_BMSK                                                           0x20
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_TITAN_XPU_MSA_INTR_SHFT                                                            0x5
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_SPDM_XPU_MSA_INTR_BMSK                                                            0x10
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_SPDM_XPU_MSA_INTR_SHFT                                                             0x4
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RESERVE_35_XPU_MSA_INTR_BMSK                                                       0x8
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_RESERVE_35_XPU_MSA_INTR_SHFT                                                       0x3
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_QNM_AGGRE2_XPU_MSA_INTR_BMSK                                                       0x4
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_QNM_AGGRE2_XPU_MSA_INTR_SHFT                                                       0x2
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_QNM_AGGRE1_XPU_MSA_INTR_BMSK                                                       0x2
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_QNM_AGGRE1_XPU_MSA_INTR_SHFT                                                       0x1
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_OCIMEM_XPU3_XPU_MSA_INTR_BMSK                                                      0x1
#define HWIO_TCSR_XPU3_MSA_IRQ_STATUS_REG_1_OCIMEM_XPU3_XPU_MSA_INTR_SHFT                                                      0x0

#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_ADDR                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x00006040)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_RMSK                                                                      0xffffffff
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_MSA_INTR_ENABLE_BMSK                  0x80000000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_MSA_INTR_ENABLE_SHFT                        0x1f
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_BOOT_ROM_XPU_MSA_INTR_ENABLE_BMSK                                         0x40000000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_BOOT_ROM_XPU_MSA_INTR_ENABLE_SHFT                                               0x1e
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_MSA_INTR_ENABLE_BMSK                      0x20000000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_MSA_INTR_ENABLE_SHFT                            0x1d
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_LLCC3_XPU_MSA_INTR_ENABLE_BMSK                                            0x10000000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_LLCC3_XPU_MSA_INTR_ENABLE_SHFT                                                  0x1c
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_LLCC2_XPU_MSA_INTR_ENABLE_BMSK                                             0x8000000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_LLCC2_XPU_MSA_INTR_ENABLE_SHFT                                                  0x1b
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_LLCC1_XPU_MSA_INTR_ENABLE_BMSK                                             0x4000000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_LLCC1_XPU_MSA_INTR_ENABLE_SHFT                                                  0x1a
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_LLCC0_XPU_MSA_INTR_ENABLE_BMSK                                             0x2000000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_LLCC0_XPU_MSA_INTR_ENABLE_SHFT                                                  0x19
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_UFS_XPU_MSA_INTR_ENABLE_BMSK                                               0x1000000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_UFS_XPU_MSA_INTR_ENABLE_SHFT                                                    0x18
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_MSA_INTR_ENABLE_BMSK                               0x800000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_MSA_INTR_ENABLE_SHFT                                   0x17
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SSC_SDC_XPU_MSA_INTR_ENABLE_BMSK                                            0x400000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SSC_SDC_XPU_MSA_INTR_ENABLE_SHFT                                                0x16
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_GCC_XPU_MSA_INTR_ENABLE_BMSK                                                0x200000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_GCC_XPU_MSA_INTR_ENABLE_SHFT                                                    0x15
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_AOP_MPU_XPU_MSA_INTR_ENABLE_BMSK                                            0x100000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_AOP_MPU_XPU_MSA_INTR_ENABLE_SHFT                                                0x14
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QM_XPU_MSA_INTR_ENABLE_BMSK                                                  0x80000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QM_XPU_MSA_INTR_ENABLE_SHFT                                                     0x13
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QNM_SNOC_XPU_MSA_INTR_ENABLE_BMSK                                            0x40000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QNM_SNOC_XPU_MSA_INTR_ENABLE_SHFT                                               0x12
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QHS_CNOC_XPU_MSA_INTR_ENABLE_BMSK                                            0x20000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QHS_CNOC_XPU_MSA_INTR_ENABLE_SHFT                                               0x11
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QHM_AOSS_XPU_MSA_INTR_ENABLE_BMSK                                            0x10000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QHM_AOSS_XPU_MSA_INTR_ENABLE_SHFT                                               0x10
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SP_XPU_MSA_INTR_ENABLE_BMSK                                                   0x8000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SP_XPU_MSA_INTR_ENABLE_SHFT                                                      0xf
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_PIMEM_MPU_XPU_MSA_INTR_ENABLE_BMSK                                            0x4000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_PIMEM_MPU_XPU_MSA_INTR_ENABLE_SHFT                                               0xe
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_PIMEM_APU_XPU_MSA_INTR_ENABLE_BMSK                                            0x2000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_PIMEM_APU_XPU_MSA_INTR_ENABLE_SHFT                                               0xd
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SSC_Q6_XPU_MSA_INTR_ENABLE_BMSK                                               0x1000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SSC_Q6_XPU_MSA_INTR_ENABLE_SHFT                                                  0xc
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SSC_XPU_MSA_INTR_ENABLE_BMSK                                                   0x800
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SSC_XPU_MSA_INTR_ENABLE_SHFT                                                     0xb
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SSC_QUP_XPU_MSA_INTR_ENABLE_BMSK                                               0x400
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SSC_QUP_XPU_MSA_INTR_ENABLE_SHFT                                                 0xa
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SEC_CTRL_XPU_MSA_INTR_ENABLE_BMSK                                              0x200
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_SEC_CTRL_XPU_MSA_INTR_ENABLE_SHFT                                                0x9
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_DCC_XPU_MSA_INTR_ENABLE_BMSK                                                   0x100
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_DCC_XPU_MSA_INTR_ENABLE_SHFT                                                     0x8
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_OCIMEM_RPU_XPU_MSA_INTR_ENABLE_BMSK                                             0x80
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_OCIMEM_RPU_XPU_MSA_INTR_ENABLE_SHFT                                              0x7
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_CRYPTO0_XPU_MSA_INTR_ENABLE_BMSK                                                0x40
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_CRYPTO0_XPU_MSA_INTR_ENABLE_SHFT                                                 0x6
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_TCSR_MUTEX_XPU_MSA_INTR_ENABLE_BMSK                                             0x20
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_TCSR_MUTEX_XPU_MSA_INTR_ENABLE_SHFT                                              0x5
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QUPV3_1_XPU_MSA_INTR_ENABLE_BMSK                                                0x10
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QUPV3_1_XPU_MSA_INTR_ENABLE_SHFT                                                 0x4
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_TCSR_REGS_XPU_MSA_INTR_ENABLE_BMSK                                               0x8
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_TCSR_REGS_XPU_MSA_INTR_ENABLE_SHFT                                               0x3
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QUPV3_0_XPU_MSA_INTR_ENABLE_BMSK                                                 0x4
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_QUPV3_0_XPU_MSA_INTR_ENABLE_SHFT                                                 0x2
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_AOSS_MPU_XPU_MSA_INTR_ENABLE_BMSK                                                0x2
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_AOSS_MPU_XPU_MSA_INTR_ENABLE_SHFT                                                0x1
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_PMIC_ARB_XPU_MSA_INTR_ENABLE_BMSK                                                0x1
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_0_PMIC_ARB_XPU_MSA_INTR_ENABLE_SHFT                                                0x0

#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_ADDR                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x00006044)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RMSK                                                                        0xffffff
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RESERVE_55_XPU_MSA_INTR_ENABLE_BMSK                                         0x800000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RESERVE_55_XPU_MSA_INTR_ENABLE_SHFT                                             0x17
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_4_MSA_INTR_ENABLE_BMSK                                            0x400000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_4_MSA_INTR_ENABLE_SHFT                                                0x16
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_3_MSA_INTR_ENABLE_BMSK                                            0x200000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_3_MSA_INTR_ENABLE_SHFT                                                0x15
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_2_MSA_INTR_ENABLE_BMSK                                            0x100000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_2_MSA_INTR_ENABLE_SHFT                                                0x14
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_1_MSA_INTR_ENABLE_BMSK                                             0x80000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_1_MSA_INTR_ENABLE_SHFT                                                0x13
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_0_MSA_INTR_ENABLE_BMSK                                             0x40000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_LPASS_XPU_0_MSA_INTR_ENABLE_SHFT                                                0x12
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_QSPI_XPU_MSA_INTR_ENABLE_BMSK                                                0x20000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_QSPI_XPU_MSA_INTR_ENABLE_SHFT                                                   0x11
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_IPC_ROUTER_XPU_MSA_INTR_ENABLE_BMSK                                          0x10000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_IPC_ROUTER_XPU_MSA_INTR_ENABLE_SHFT                                             0x10
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_TLMM_NORTH_XPU_MSA_INTR_ENABLE_BMSK                                           0x8000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_TLMM_NORTH_XPU_MSA_INTR_ENABLE_SHFT                                              0xf
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RESERVE_46_XPU_MSA_INTR_ENABLE_BMSK                                           0x4000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RESERVE_46_XPU_MSA_INTR_ENABLE_SHFT                                              0xe
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_DDRSS_SHRM_XPU_MSA_INTR_ENABLE_BMSK                                           0x2000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_DDRSS_SHRM_XPU_MSA_INTR_ENABLE_SHFT                                              0xd
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_QUPV3_2_XPU_MSA_INTR_ENABLE_BMSK                                              0x1000
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_QUPV3_2_XPU_MSA_INTR_ENABLE_SHFT                                                 0xc
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_IPA_XPU_MSA_INTR_ENABLE_BMSK                                                   0x800
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_IPA_XPU_MSA_INTR_ENABLE_SHFT                                                     0xb
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RESERVE_42_XPU_MSA_INTR_ENABLE_BMSK                                            0x400
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RESERVE_42_XPU_MSA_INTR_ENABLE_SHFT                                              0xa
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_TLMM_SOUTH_XPU_MSA_INTR_ENABLE_BMSK                                            0x200
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_TLMM_SOUTH_XPU_MSA_INTR_ENABLE_SHFT                                              0x9
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_TLMM_WEST_XPU_MSA_INTR_ENABLE_BMSK                                             0x100
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_TLMM_WEST_XPU_MSA_INTR_ENABLE_SHFT                                               0x8
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_MDSS_XPU_MSA_INTR_ENABLE_BMSK                                                   0x80
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_MDSS_XPU_MSA_INTR_ENABLE_SHFT                                                    0x7
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_UFS_CARD_ICE_XPU_MSA_INTR_ENABLE_BMSK                                           0x40
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_UFS_CARD_ICE_XPU_MSA_INTR_ENABLE_SHFT                                            0x6
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_TITAN_XPU_MSA_INTR_ENABLE_BMSK                                                  0x20
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_TITAN_XPU_MSA_INTR_ENABLE_SHFT                                                   0x5
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_SPDM_XPU_MSA_INTR_ENABLE_BMSK                                                   0x10
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_SPDM_XPU_MSA_INTR_ENABLE_SHFT                                                    0x4
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RESERVE_35_XPU_MSA_INTR_ENABLE_BMSK                                              0x8
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_RESERVE_35_XPU_MSA_INTR_ENABLE_SHFT                                              0x3
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_QNM_AGGRE2_XPU_MSA_INTR_ENABLE_BMSK                                              0x4
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_QNM_AGGRE2_XPU_MSA_INTR_ENABLE_SHFT                                              0x2
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_QNM_AGGRE1_XPU_MSA_INTR_ENABLE_BMSK                                              0x2
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_QNM_AGGRE1_XPU_MSA_INTR_ENABLE_SHFT                                              0x1
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_OCIMEM_XPU3_XPU_MSA_INTR_ENABLE_BMSK                                             0x1
#define HWIO_TCSR_XPU3_MSA_IRQ_ENABLE_0_REG_1_OCIMEM_XPU3_XPU_MSA_INTR_ENABLE_SHFT                                             0x0

#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_ADDR                                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00021000)
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_RMSK                                                                         0xffffffff
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SP_INTR_BMSK                             0x80000000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SP_INTR_SHFT                                   0x1f
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_BOOT_ROM_XPU_SP_INTR_BMSK                                                    0x40000000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_BOOT_ROM_XPU_SP_INTR_SHFT                                                          0x1e
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SP_INTR_BMSK                                 0x20000000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SP_INTR_SHFT                                       0x1d
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_LLCC3_XPU_SP_INTR_BMSK                                                       0x10000000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_LLCC3_XPU_SP_INTR_SHFT                                                             0x1c
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_LLCC2_XPU_SP_INTR_BMSK                                                        0x8000000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_LLCC2_XPU_SP_INTR_SHFT                                                             0x1b
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_LLCC1_XPU_SP_INTR_BMSK                                                        0x4000000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_LLCC1_XPU_SP_INTR_SHFT                                                             0x1a
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_LLCC0_XPU_SP_INTR_BMSK                                                        0x2000000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_LLCC0_XPU_SP_INTR_SHFT                                                             0x19
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_UFS_XPU_SP_INTR_BMSK                                                          0x1000000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_UFS_XPU_SP_INTR_SHFT                                                               0x18
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_SP_INTR_BMSK                                          0x800000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_SP_INTR_SHFT                                              0x17
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SSC_SDC_XPU_SP_INTR_BMSK                                                       0x400000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SSC_SDC_XPU_SP_INTR_SHFT                                                           0x16
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_GCC_XPU_SP_INTR_BMSK                                                           0x200000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_GCC_XPU_SP_INTR_SHFT                                                               0x15
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_AOP_MPU_XPU_SP_INTR_BMSK                                                       0x100000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_AOP_MPU_XPU_SP_INTR_SHFT                                                           0x14
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QM_XPU_SP_INTR_BMSK                                                             0x80000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QM_XPU_SP_INTR_SHFT                                                                0x13
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QNM_SNOC_XPU_SP_INTR_BMSK                                                       0x40000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QNM_SNOC_XPU_SP_INTR_SHFT                                                          0x12
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QHS_CNOC_XPU_SP_INTR_BMSK                                                       0x20000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QHS_CNOC_XPU_SP_INTR_SHFT                                                          0x11
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QHM_AOSS_XPU_SP_INTR_BMSK                                                       0x10000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QHM_AOSS_XPU_SP_INTR_SHFT                                                          0x10
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SP_XPU_SP_INTR_BMSK                                                              0x8000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SP_XPU_SP_INTR_SHFT                                                                 0xf
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_PIMEM_MPU_XPU_SP_INTR_BMSK                                                       0x4000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_PIMEM_MPU_XPU_SP_INTR_SHFT                                                          0xe
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_PIMEM_APU_XPU_SP_INTR_BMSK                                                       0x2000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_PIMEM_APU_XPU_SP_INTR_SHFT                                                          0xd
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SSC_Q6_XPU_SP_INTR_BMSK                                                          0x1000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SSC_Q6_XPU_SP_INTR_SHFT                                                             0xc
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SSC_XPU_SP_INTR_BMSK                                                              0x800
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SSC_XPU_SP_INTR_SHFT                                                                0xb
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SSC_QUP_XPU_SP_INTR_BMSK                                                          0x400
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SSC_QUP_XPU_SP_INTR_SHFT                                                            0xa
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SEC_CTRL_XPU_SP_INTR_BMSK                                                         0x200
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_SEC_CTRL_XPU_SP_INTR_SHFT                                                           0x9
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_DCC_XPU_SP_INTR_BMSK                                                              0x100
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_DCC_XPU_SP_INTR_SHFT                                                                0x8
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_OCIMEM_RPU_XPU_SP_INTR_BMSK                                                        0x80
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_OCIMEM_RPU_XPU_SP_INTR_SHFT                                                         0x7
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_CRYPTO0_XPU_SP_INTR_BMSK                                                           0x40
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_CRYPTO0_XPU_SP_INTR_SHFT                                                            0x6
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_TCSR_MUTEX_XPU_SP_INTR_BMSK                                                        0x20
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_TCSR_MUTEX_XPU_SP_INTR_SHFT                                                         0x5
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QUPV3_1_XPU_SP_INTR_BMSK                                                           0x10
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QUPV3_1_XPU_SP_INTR_SHFT                                                            0x4
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_TCSR_REGS_XPU_SP_INTR_BMSK                                                          0x8
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_TCSR_REGS_XPU_SP_INTR_SHFT                                                          0x3
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QUPV3_0_XPU_SP_INTR_BMSK                                                            0x4
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_QUPV3_0_XPU_SP_INTR_SHFT                                                            0x2
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_AOSS_MPU_XPU_SP_INTR_BMSK                                                           0x2
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_AOSS_MPU_XPU_SP_INTR_SHFT                                                           0x1
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_PMIC_ARB_XPU_SP_INTR_BMSK                                                           0x1
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_0_PMIC_ARB_XPU_SP_INTR_SHFT                                                           0x0

#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_ADDR                                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00021004)
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RMSK                                                                           0xffffff
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_IN          \
        in_dword(HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_ADDR)
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_ADDR, m)
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RESERVE_55_XPU_SP_INTR_BMSK                                                    0x800000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RESERVE_55_XPU_SP_INTR_SHFT                                                        0x17
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_4_SP_INTR_BMSK                                                       0x400000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_4_SP_INTR_SHFT                                                           0x16
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_3_SP_INTR_BMSK                                                       0x200000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_3_SP_INTR_SHFT                                                           0x15
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_2_SP_INTR_BMSK                                                       0x100000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_2_SP_INTR_SHFT                                                           0x14
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_1_SP_INTR_BMSK                                                        0x80000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_1_SP_INTR_SHFT                                                           0x13
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_0_SP_INTR_BMSK                                                        0x40000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_LPASS_XPU_0_SP_INTR_SHFT                                                           0x12
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_QSPI_XPU_SP_INTR_BMSK                                                           0x20000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_QSPI_XPU_SP_INTR_SHFT                                                              0x11
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_IPC_ROUTER_XPU_SP_INTR_BMSK                                                     0x10000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_IPC_ROUTER_XPU_SP_INTR_SHFT                                                        0x10
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_TLMM_NORTH_XPU_SP_INTR_BMSK                                                      0x8000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_TLMM_NORTH_XPU_SP_INTR_SHFT                                                         0xf
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RESERVE_46_XPU_SP_INTR_BMSK                                                      0x4000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RESERVE_46_XPU_SP_INTR_SHFT                                                         0xe
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_DDRSS_SHRM_XPU_SP_INTR_BMSK                                                      0x2000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_DDRSS_SHRM_XPU_SP_INTR_SHFT                                                         0xd
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_QUPV3_2_XPU_SP_INTR_BMSK                                                         0x1000
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_QUPV3_2_XPU_SP_INTR_SHFT                                                            0xc
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_IPA_XPU_SP_INTR_BMSK                                                              0x800
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_IPA_XPU_SP_INTR_SHFT                                                                0xb
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RESERVE_42_XPU_SP_INTR_BMSK                                                       0x400
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RESERVE_42_XPU_SP_INTR_SHFT                                                         0xa
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_TLMM_SOUTH_XPU_SP_INTR_BMSK                                                       0x200
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_TLMM_SOUTH_XPU_SP_INTR_SHFT                                                         0x9
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_TLMM_WEST_XPU_SP_INTR_BMSK                                                        0x100
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_TLMM_WEST_XPU_SP_INTR_SHFT                                                          0x8
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_MDSS_XPU_SP_INTR_BMSK                                                              0x80
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_MDSS_XPU_SP_INTR_SHFT                                                               0x7
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_UFS_CARD_ICE_XPU_SP_INTR_BMSK                                                      0x40
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_UFS_CARD_ICE_XPU_SP_INTR_SHFT                                                       0x6
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_TITAN_XPU_SP_INTR_BMSK                                                             0x20
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_TITAN_XPU_SP_INTR_SHFT                                                              0x5
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_SPDM_XPU_SP_INTR_BMSK                                                              0x10
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_SPDM_XPU_SP_INTR_SHFT                                                               0x4
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RESERVE_35_XPU_SP_INTR_BMSK                                                         0x8
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_RESERVE_35_XPU_SP_INTR_SHFT                                                         0x3
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_QNM_AGGRE2_XPU_SP_INTR_BMSK                                                         0x4
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_QNM_AGGRE2_XPU_SP_INTR_SHFT                                                         0x2
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_QNM_AGGRE1_XPU_SP_INTR_BMSK                                                         0x2
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_QNM_AGGRE1_XPU_SP_INTR_SHFT                                                         0x1
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_OCIMEM_XPU3_XPU_SP_INTR_BMSK                                                        0x1
#define HWIO_TCSR_XPU3_SP_IRQ_STATUS_REG_1_OCIMEM_XPU3_XPU_SP_INTR_SHFT                                                        0x0

#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_ADDR                                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x00021008)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_RMSK                                                                       0xffffffff
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SP_INTR_ENABLE_BMSK                    0x80000000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SP_INTR_ENABLE_SHFT                          0x1f
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_BOOT_ROM_XPU_SP_INTR_ENABLE_BMSK                                           0x40000000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_BOOT_ROM_XPU_SP_INTR_ENABLE_SHFT                                                 0x1e
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SP_INTR_ENABLE_BMSK                        0x20000000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SP_INTR_ENABLE_SHFT                              0x1d
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_LLCC3_XPU_SP_INTR_ENABLE_BMSK                                              0x10000000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_LLCC3_XPU_SP_INTR_ENABLE_SHFT                                                    0x1c
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_LLCC2_XPU_SP_INTR_ENABLE_BMSK                                               0x8000000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_LLCC2_XPU_SP_INTR_ENABLE_SHFT                                                    0x1b
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_LLCC1_XPU_SP_INTR_ENABLE_BMSK                                               0x4000000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_LLCC1_XPU_SP_INTR_ENABLE_SHFT                                                    0x1a
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_LLCC0_XPU_SP_INTR_ENABLE_BMSK                                               0x2000000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_LLCC0_XPU_SP_INTR_ENABLE_SHFT                                                    0x19
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_UFS_XPU_SP_INTR_ENABLE_BMSK                                                 0x1000000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_UFS_XPU_SP_INTR_ENABLE_SHFT                                                      0x18
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_SP_INTR_ENABLE_BMSK                                 0x800000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QXS_BOOT_IMEM_SS_MPU_XPU_SP_INTR_ENABLE_SHFT                                     0x17
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SSC_SDC_XPU_SP_INTR_ENABLE_BMSK                                              0x400000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SSC_SDC_XPU_SP_INTR_ENABLE_SHFT                                                  0x16
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_GCC_XPU_SP_INTR_ENABLE_BMSK                                                  0x200000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_GCC_XPU_SP_INTR_ENABLE_SHFT                                                      0x15
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_AOP_MPU_XPU_SP_INTR_ENABLE_BMSK                                              0x100000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_AOP_MPU_XPU_SP_INTR_ENABLE_SHFT                                                  0x14
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QM_XPU_SP_INTR_ENABLE_BMSK                                                    0x80000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QM_XPU_SP_INTR_ENABLE_SHFT                                                       0x13
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QNM_SNOC_XPU_SP_INTR_ENABLE_BMSK                                              0x40000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QNM_SNOC_XPU_SP_INTR_ENABLE_SHFT                                                 0x12
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QHS_CNOC_XPU_SP_INTR_ENABLE_BMSK                                              0x20000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QHS_CNOC_XPU_SP_INTR_ENABLE_SHFT                                                 0x11
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QHM_AOSS_XPU_SP_INTR_ENABLE_BMSK                                              0x10000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QHM_AOSS_XPU_SP_INTR_ENABLE_SHFT                                                 0x10
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SP_XPU_SP_INTR_ENABLE_BMSK                                                     0x8000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SP_XPU_SP_INTR_ENABLE_SHFT                                                        0xf
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_PIMEM_MPU_XPU_SP_INTR_ENABLE_BMSK                                              0x4000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_PIMEM_MPU_XPU_SP_INTR_ENABLE_SHFT                                                 0xe
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_PIMEM_APU_XPU_SP_INTR_ENABLE_BMSK                                              0x2000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_PIMEM_APU_XPU_SP_INTR_ENABLE_SHFT                                                 0xd
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SSC_Q6_XPU_SP_INTR_ENABLE_BMSK                                                 0x1000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SSC_Q6_XPU_SP_INTR_ENABLE_SHFT                                                    0xc
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SSC_XPU_SP_INTR_ENABLE_BMSK                                                     0x800
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SSC_XPU_SP_INTR_ENABLE_SHFT                                                       0xb
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SSC_QUP_XPU_SP_INTR_ENABLE_BMSK                                                 0x400
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SSC_QUP_XPU_SP_INTR_ENABLE_SHFT                                                   0xa
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SEC_CTRL_XPU_SP_INTR_ENABLE_BMSK                                                0x200
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_SEC_CTRL_XPU_SP_INTR_ENABLE_SHFT                                                  0x9
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_DCC_XPU_SP_INTR_ENABLE_BMSK                                                     0x100
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_DCC_XPU_SP_INTR_ENABLE_SHFT                                                       0x8
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_OCIMEM_RPU_XPU_SP_INTR_ENABLE_BMSK                                               0x80
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_OCIMEM_RPU_XPU_SP_INTR_ENABLE_SHFT                                                0x7
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_CRYPTO0_XPU_SP_INTR_ENABLE_BMSK                                                  0x40
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_CRYPTO0_XPU_SP_INTR_ENABLE_SHFT                                                   0x6
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_TCSR_MUTEX_XPU_SP_INTR_ENABLE_BMSK                                               0x20
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_TCSR_MUTEX_XPU_SP_INTR_ENABLE_SHFT                                                0x5
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QUPV3_1_XPU_SP_INTR_ENABLE_BMSK                                                  0x10
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QUPV3_1_XPU_SP_INTR_ENABLE_SHFT                                                   0x4
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_TCSR_REGS_XPU_SP_INTR_ENABLE_BMSK                                                 0x8
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_TCSR_REGS_XPU_SP_INTR_ENABLE_SHFT                                                 0x3
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QUPV3_0_XPU_SP_INTR_ENABLE_BMSK                                                   0x4
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_QUPV3_0_XPU_SP_INTR_ENABLE_SHFT                                                   0x2
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_AOSS_MPU_XPU_SP_INTR_ENABLE_BMSK                                                  0x2
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_AOSS_MPU_XPU_SP_INTR_ENABLE_SHFT                                                  0x1
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_PMIC_ARB_XPU_SP_INTR_ENABLE_BMSK                                                  0x1
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_0_PMIC_ARB_XPU_SP_INTR_ENABLE_SHFT                                                  0x0

#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_ADDR                                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x0002100c)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RMSK                                                                         0xffffff
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_IN          \
        in_dword(HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_ADDR)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_ADDR, m)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_OUT(v)      \
        out_dword(HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_ADDR,v)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_ADDR,m,v,HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_IN)
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RESERVE_55_XPU_SP_INTR_ENABLE_BMSK                                           0x800000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RESERVE_55_XPU_SP_INTR_ENABLE_SHFT                                               0x17
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_4_SP_INTR_ENABLE_BMSK                                              0x400000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_4_SP_INTR_ENABLE_SHFT                                                  0x16
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_3_SP_INTR_ENABLE_BMSK                                              0x200000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_3_SP_INTR_ENABLE_SHFT                                                  0x15
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_2_SP_INTR_ENABLE_BMSK                                              0x100000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_2_SP_INTR_ENABLE_SHFT                                                  0x14
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_1_SP_INTR_ENABLE_BMSK                                               0x80000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_1_SP_INTR_ENABLE_SHFT                                                  0x13
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_0_SP_INTR_ENABLE_BMSK                                               0x40000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_LPASS_XPU_0_SP_INTR_ENABLE_SHFT                                                  0x12
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_QSPI_XPU_SP_INTR_ENABLE_BMSK                                                  0x20000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_QSPI_XPU_SP_INTR_ENABLE_SHFT                                                     0x11
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_IPC_ROUTER_XPU_SP_INTR_ENABLE_BMSK                                            0x10000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_IPC_ROUTER_XPU_SP_INTR_ENABLE_SHFT                                               0x10
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_TLMM_NORTH_XPU_SP_INTR_ENABLE_BMSK                                             0x8000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_TLMM_NORTH_XPU_SP_INTR_ENABLE_SHFT                                                0xf
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RESERVE_46_XPU_SP_INTR_ENABLE_BMSK                                             0x4000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RESERVE_46_XPU_SP_INTR_ENABLE_SHFT                                                0xe
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_DDRSS_SHRM_XPU_SP_INTR_ENABLE_BMSK                                             0x2000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_DDRSS_SHRM_XPU_SP_INTR_ENABLE_SHFT                                                0xd
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_QUPV3_2_XPU_SP_INTR_ENABLE_BMSK                                                0x1000
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_QUPV3_2_XPU_SP_INTR_ENABLE_SHFT                                                   0xc
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_IPA_XPU_SP_INTR_ENABLE_BMSK                                                     0x800
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_IPA_XPU_SP_INTR_ENABLE_SHFT                                                       0xb
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RESERVE_42_XPU_SP_INTR_ENABLE_BMSK                                              0x400
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RESERVE_42_XPU_SP_INTR_ENABLE_SHFT                                                0xa
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_TLMM_SOUTH_XPU_SP_INTR_ENABLE_BMSK                                              0x200
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_TLMM_SOUTH_XPU_SP_INTR_ENABLE_SHFT                                                0x9
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_TLMM_WEST_XPU_SP_INTR_ENABLE_BMSK                                               0x100
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_TLMM_WEST_XPU_SP_INTR_ENABLE_SHFT                                                 0x8
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_MDSS_XPU_SP_INTR_ENABLE_BMSK                                                     0x80
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_MDSS_XPU_SP_INTR_ENABLE_SHFT                                                      0x7
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_UFS_CARD_ICE_XPU_SP_INTR_ENABLE_BMSK                                             0x40
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_UFS_CARD_ICE_XPU_SP_INTR_ENABLE_SHFT                                              0x6
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_TITAN_XPU_SP_INTR_ENABLE_BMSK                                                    0x20
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_TITAN_XPU_SP_INTR_ENABLE_SHFT                                                     0x5
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_SPDM_XPU_SP_INTR_ENABLE_BMSK                                                     0x10
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_SPDM_XPU_SP_INTR_ENABLE_SHFT                                                      0x4
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RESERVE_35_XPU_SP_INTR_ENABLE_BMSK                                                0x8
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_RESERVE_35_XPU_SP_INTR_ENABLE_SHFT                                                0x3
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_QNM_AGGRE2_XPU_SP_INTR_ENABLE_BMSK                                                0x4
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_QNM_AGGRE2_XPU_SP_INTR_ENABLE_SHFT                                                0x2
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_QNM_AGGRE1_XPU_SP_INTR_ENABLE_BMSK                                                0x2
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_QNM_AGGRE1_XPU_SP_INTR_ENABLE_SHFT                                                0x1
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_OCIMEM_XPU3_XPU_SP_INTR_ENABLE_BMSK                                               0x1
#define HWIO_TCSR_XPU3_SP_IRQ_ENABLE_0_REG_1_OCIMEM_XPU3_XPU_SP_INTR_ENABLE_SHFT                                               0x0

#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00002010)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_RMSK                                                              0x3ffff
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_RESERVE_17_VMIDMT_NSGIRPT_BMSK                                    0x20000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_RESERVE_17_VMIDMT_NSGIRPT_SHFT                                       0x11
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_RESERVE_16_VMIDMT_NSGIRPT_BMSK                                    0x10000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_RESERVE_16_VMIDMT_NSGIRPT_SHFT                                       0x10
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_RESERVE_15_VMIDMT_NSGIRPT_BMSK                                     0x8000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_RESERVE_15_VMIDMT_NSGIRPT_SHFT                                        0xf
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_LPASS_2_VMIDMT_NSGIRPT_BMSK                                        0x4000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_LPASS_2_VMIDMT_NSGIRPT_SHFT                                           0xe
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QSPI_VMIDMT_NSGIRPT_BMSK                                           0x2000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QSPI_VMIDMT_NSGIRPT_SHFT                                              0xd
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_SPDM_VMIDMT_NSGIRPT_BMSK                                           0x1000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_SPDM_VMIDMT_NSGIRPT_SHFT                                              0xc
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QDSS_DAP_VMIDMT_NSGIRPT_BMSK                                        0x800
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QDSS_DAP_VMIDMT_NSGIRPT_SHFT                                          0xb
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QDSS_TRACE_VMIDMT_NSGIRPT_BMSK                                      0x400
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QDSS_TRACE_VMIDMT_NSGIRPT_SHFT                                        0xa
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_IPA_VMIDMT_NSGIRPT_BMSK                                             0x200
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_IPA_VMIDMT_NSGIRPT_SHFT                                               0x9
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_LPASS_1_VMIDMT_NSGIRPT_BMSK                                         0x100
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_LPASS_1_VMIDMT_NSGIRPT_SHFT                                           0x8
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_LPASS_0_VMIDMT_NSGIRPT_BMSK                                          0x80
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_LPASS_0_VMIDMT_NSGIRPT_SHFT                                           0x7
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_SSC_VMIDMT_NSGIRPT_BMSK                                              0x40
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_SSC_VMIDMT_NSGIRPT_SHFT                                               0x6
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QUPV3_2_VMIDMT_NSGIRPT_BMSK                                          0x20
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QUPV3_2_VMIDMT_NSGIRPT_SHFT                                           0x5
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QUPV3_1_VMIDMT_NSGIRPT_BMSK                                          0x10
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QUPV3_1_VMIDMT_NSGIRPT_SHFT                                           0x4
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_SSC_SDC_VMIDMT_NSGIRPT_BMSK                                           0x8
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_SSC_SDC_VMIDMT_NSGIRPT_SHFT                                           0x3
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QUPV3_0_VMIDMT_NSGIRPT_BMSK                                           0x4
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_QUPV3_0_VMIDMT_NSGIRPT_SHFT                                           0x2
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_AOP_VMIDMT_NSGIRPT_BMSK                                               0x2
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_AOP_VMIDMT_NSGIRPT_SHFT                                               0x1
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_CRYPTO0_VMIDMT_NSGIRPT_BMSK                                           0x1
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_STATUS_REG_0_CRYPTO0_VMIDMT_NSGIRPT_SHFT                                           0x0

#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00002050)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_RMSK                                                            0x3ffff
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_17_VMIDMT_NSGIRPT_ENABLE_BMSK                           0x20000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_17_VMIDMT_NSGIRPT_ENABLE_SHFT                              0x11
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_16_VMIDMT_NSGIRPT_ENABLE_BMSK                           0x10000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_16_VMIDMT_NSGIRPT_ENABLE_SHFT                              0x10
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_15_VMIDMT_NSGIRPT_ENABLE_BMSK                            0x8000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_15_VMIDMT_NSGIRPT_ENABLE_SHFT                               0xf
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_2_VMIDMT_NSGIRPT_ENABLE_BMSK                               0x4000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_2_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0xe
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QSPI_VMIDMT_NSGIRPT_ENABLE_BMSK                                  0x2000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QSPI_VMIDMT_NSGIRPT_ENABLE_SHFT                                     0xd
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_SPDM_VMIDMT_NSGIRPT_ENABLE_BMSK                                  0x1000
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_SPDM_VMIDMT_NSGIRPT_ENABLE_SHFT                                     0xc
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QDSS_DAP_VMIDMT_NSGIRPT_ENABLE_BMSK                               0x800
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QDSS_DAP_VMIDMT_NSGIRPT_ENABLE_SHFT                                 0xb
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QDSS_TRACE_VMIDMT_NSGIRPT_ENABLE_BMSK                             0x400
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QDSS_TRACE_VMIDMT_NSGIRPT_ENABLE_SHFT                               0xa
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_IPA_VMIDMT_NSGIRPT_ENABLE_BMSK                                    0x200
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_IPA_VMIDMT_NSGIRPT_ENABLE_SHFT                                      0x9
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_1_VMIDMT_NSGIRPT_ENABLE_BMSK                                0x100
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_1_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0x8
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_0_VMIDMT_NSGIRPT_ENABLE_BMSK                                 0x80
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_0_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0x7
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_VMIDMT_NSGIRPT_ENABLE_BMSK                                     0x40
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_VMIDMT_NSGIRPT_ENABLE_SHFT                                      0x6
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_2_VMIDMT_NSGIRPT_ENABLE_BMSK                                 0x20
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_2_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0x5
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_VMIDMT_NSGIRPT_ENABLE_BMSK                                 0x10
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0x4
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_VMIDMT_NSGIRPT_ENABLE_BMSK                                  0x8
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0x3
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_VMIDMT_NSGIRPT_ENABLE_BMSK                                  0x4
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0x2
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_AOP_VMIDMT_NSGIRPT_ENABLE_BMSK                                      0x2
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_AOP_VMIDMT_NSGIRPT_ENABLE_SHFT                                      0x1
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_VMIDMT_NSGIRPT_ENABLE_BMSK                                  0x1
#define HWIO_TCSR_VMIDMT_CLIENT_NON_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0x0

#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00003000)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_RMSK                                                                 0x3ffff
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_RESERVE_17_VMIDMT_NSGCFGIRPT_BMSK                                    0x20000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_RESERVE_17_VMIDMT_NSGCFGIRPT_SHFT                                       0x11
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_RESERVE_16_VMIDMT_NSGCFGIRPT_BMSK                                    0x10000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_RESERVE_16_VMIDMT_NSGCFGIRPT_SHFT                                       0x10
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_RESERVE_15_VMIDMT_NSGCFGIRPT_BMSK                                     0x8000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_RESERVE_15_VMIDMT_NSGCFGIRPT_SHFT                                        0xf
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_LPASS_2_VMIDMT_NSGCFGIRPT_BMSK                                        0x4000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_LPASS_2_VMIDMT_NSGCFGIRPT_SHFT                                           0xe
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QSPI_VMIDMT_NSGCFGIRPT_BMSK                                           0x2000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QSPI_VMIDMT_NSGCFGIRPT_SHFT                                              0xd
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_SPDM_VMIDMT_NSGCFGIRPT_BMSK                                           0x1000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_SPDM_VMIDMT_NSGCFGIRPT_SHFT                                              0xc
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QDSS_DAP_VMIDMT_NSGCFGIRPT_BMSK                                        0x800
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QDSS_DAP_VMIDMT_NSGCFGIRPT_SHFT                                          0xb
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QDSS_TRACE_VMIDMT_NSGCFGIRPT_BMSK                                      0x400
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QDSS_TRACE_VMIDMT_NSGCFGIRPT_SHFT                                        0xa
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_IPA_VMIDMT_NSGCFGIRPT_BMSK                                             0x200
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_IPA_VMIDMT_NSGCFGIRPT_SHFT                                               0x9
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_LPASS_1_VMIDMT_NSGCFGIRPT_BMSK                                         0x100
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_LPASS_1_VMIDMT_NSGCFGIRPT_SHFT                                           0x8
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_LPASS_0_VMIDMT_NSGCFGIRPT_BMSK                                          0x80
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_LPASS_0_VMIDMT_NSGCFGIRPT_SHFT                                           0x7
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_SSC_VMIDMT_NSGCFGIRPT_BMSK                                              0x40
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_SSC_VMIDMT_NSGCFGIRPT_SHFT                                               0x6
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QUPV3_2_VMIDMT_NSGCFGIRPT_BMSK                                          0x20
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QUPV3_2_VMIDMT_NSGCFGIRPT_SHFT                                           0x5
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QUPV3_1_VMIDMT_NSGCFGIRPT_BMSK                                          0x10
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QUPV3_1_VMIDMT_NSGCFGIRPT_SHFT                                           0x4
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_SSC_SDC_VMIDMT_NSGCFGIRPT_BMSK                                           0x8
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_SSC_SDC_VMIDMT_NSGCFGIRPT_SHFT                                           0x3
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QUPV3_0_VMIDMT_NSGCFGIRPT_BMSK                                           0x4
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_QUPV3_0_VMIDMT_NSGCFGIRPT_SHFT                                           0x2
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_AOP_VMIDMT_NSGCFGIRPT_BMSK                                               0x2
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_AOP_VMIDMT_NSGCFGIRPT_SHFT                                               0x1
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_CRYPTO0_VMIDMT_NSGCFGIRPT_BMSK                                           0x1
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_STATUS_REG_0_CRYPTO0_VMIDMT_NSGCFGIRPT_SHFT                                           0x0

#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00003040)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_RMSK                                                               0x3ffff
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_17_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                           0x20000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_17_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                              0x11
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_16_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                           0x10000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_16_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                              0x10
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_15_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                            0x8000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_RESERVE_15_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                               0xf
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_2_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                               0x4000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_2_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0xe
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QSPI_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                  0x2000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QSPI_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                     0xd
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_SPDM_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                  0x1000
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_SPDM_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                     0xc
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QDSS_DAP_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                               0x800
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QDSS_DAP_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                 0xb
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QDSS_TRACE_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                             0x400
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QDSS_TRACE_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                               0xa
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_IPA_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                    0x200
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_IPA_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                      0x9
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_1_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                0x100
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_1_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0x8
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_0_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                 0x80
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_LPASS_0_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0x7
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                     0x40
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                      0x6
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_2_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                 0x20
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_2_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0x5
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                 0x10
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0x4
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                  0x8
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0x3
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                  0x4
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0x2
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_AOP_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                      0x2
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_AOP_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                      0x1
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                  0x1
#define HWIO_TCSR_VMIDMT_CFG_NON_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0x0

#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00004010)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_RMSK                                                                  0x3ffff
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_RESERVE_17_VMIDMT_GIRPT_BMSK                                          0x20000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_RESERVE_17_VMIDMT_GIRPT_SHFT                                             0x11
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_RESERVE_16_VMIDMT_GIRPT_BMSK                                          0x10000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_RESERVE_16_VMIDMT_GIRPT_SHFT                                             0x10
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_RESERVE_15_VMIDMT_GIRPT_BMSK                                           0x8000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_RESERVE_15_VMIDMT_GIRPT_SHFT                                              0xf
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_LPASS_2_VMIDMT_GIRPT_BMSK                                              0x4000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_LPASS_2_VMIDMT_GIRPT_SHFT                                                 0xe
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QSPI_VMIDMT_GIRPT_BMSK                                                 0x2000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QSPI_VMIDMT_GIRPT_SHFT                                                    0xd
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_SPDM_VMIDMT_GIRPT_BMSK                                                 0x1000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_SPDM_VMIDMT_GIRPT_SHFT                                                    0xc
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QDSS_DAP_VMIDMT_GIRPT_BMSK                                              0x800
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QDSS_DAP_VMIDMT_GIRPT_SHFT                                                0xb
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QDSS_TRACE_VMIDMT_GIRPT_BMSK                                            0x400
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QDSS_TRACE_VMIDMT_GIRPT_SHFT                                              0xa
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_IPA_VMIDMT_GIRPT_BMSK                                                   0x200
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_IPA_VMIDMT_GIRPT_SHFT                                                     0x9
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_LPASS_1_VMIDMT_GIRPT_BMSK                                               0x100
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_LPASS_1_VMIDMT_GIRPT_SHFT                                                 0x8
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_LPASS_0_VMIDMT_GIRPT_BMSK                                                0x80
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_LPASS_0_VMIDMT_GIRPT_SHFT                                                 0x7
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_SSC_VMIDMT_GIRPT_BMSK                                                    0x40
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_SSC_VMIDMT_GIRPT_SHFT                                                     0x6
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QUPV3_2_VMIDMT_GIRPT_BMSK                                                0x20
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QUPV3_2_VMIDMT_GIRPT_SHFT                                                 0x5
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QUPV3_1_VMIDMT_GIRPT_BMSK                                                0x10
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QUPV3_1_VMIDMT_GIRPT_SHFT                                                 0x4
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_SSC_SDC_VMIDMT_GIRPT_BMSK                                                 0x8
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_SSC_SDC_VMIDMT_GIRPT_SHFT                                                 0x3
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QUPV3_0_VMIDMT_GIRPT_BMSK                                                 0x4
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_QUPV3_0_VMIDMT_GIRPT_SHFT                                                 0x2
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_AOP_VMIDMT_GIRPT_BMSK                                                     0x2
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_AOP_VMIDMT_GIRPT_SHFT                                                     0x1
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_CRYPTO0_VMIDMT_GIRPT_BMSK                                                 0x1
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_STATUS_REG_0_CRYPTO0_VMIDMT_GIRPT_SHFT                                                 0x0

#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_ADDR                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x00004050)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_RMSK                                                                0x3ffff
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_RESERVE_17_VMIDMT_GIRPT_ENABLE_BMSK                                 0x20000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_RESERVE_17_VMIDMT_GIRPT_ENABLE_SHFT                                    0x11
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_RESERVE_16_VMIDMT_GIRPT_ENABLE_BMSK                                 0x10000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_RESERVE_16_VMIDMT_GIRPT_ENABLE_SHFT                                    0x10
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_RESERVE_15_VMIDMT_GIRPT_ENABLE_BMSK                                  0x8000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_RESERVE_15_VMIDMT_GIRPT_ENABLE_SHFT                                     0xf
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_LPASS_2_VMIDMT_GIRPT_ENABLE_BMSK                                     0x4000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_LPASS_2_VMIDMT_GIRPT_ENABLE_SHFT                                        0xe
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QSPI_VMIDMT_GIRPT_ENABLE_BMSK                                        0x2000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QSPI_VMIDMT_GIRPT_ENABLE_SHFT                                           0xd
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_SPDM_VMIDMT_GIRPT_ENABLE_BMSK                                        0x1000
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_SPDM_VMIDMT_GIRPT_ENABLE_SHFT                                           0xc
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QDSS_DAP_VMIDMT_GIRPT_ENABLE_BMSK                                     0x800
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QDSS_DAP_VMIDMT_GIRPT_ENABLE_SHFT                                       0xb
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QDSS_TRACE_VMIDMT_GIRPT_ENABLE_BMSK                                   0x400
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QDSS_TRACE_VMIDMT_GIRPT_ENABLE_SHFT                                     0xa
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_IPA_VMIDMT_GIRPT_ENABLE_BMSK                                          0x200
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_IPA_VMIDMT_GIRPT_ENABLE_SHFT                                            0x9
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_LPASS_1_VMIDMT_GIRPT_ENABLE_BMSK                                      0x100
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_LPASS_1_VMIDMT_GIRPT_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_LPASS_0_VMIDMT_GIRPT_ENABLE_BMSK                                       0x80
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_LPASS_0_VMIDMT_GIRPT_ENABLE_SHFT                                        0x7
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_SSC_VMIDMT_GIRPT_ENABLE_BMSK                                           0x40
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_SSC_VMIDMT_GIRPT_ENABLE_SHFT                                            0x6
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QUPV3_2_VMIDMT_GIRPT_ENABLE_BMSK                                       0x20
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QUPV3_2_VMIDMT_GIRPT_ENABLE_SHFT                                        0x5
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_VMIDMT_GIRPT_ENABLE_BMSK                                       0x10
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_VMIDMT_GIRPT_ENABLE_SHFT                                        0x4
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_VMIDMT_GIRPT_ENABLE_BMSK                                        0x8
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_VMIDMT_GIRPT_ENABLE_SHFT                                        0x3
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_VMIDMT_GIRPT_ENABLE_BMSK                                        0x4
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_VMIDMT_GIRPT_ENABLE_SHFT                                        0x2
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_AOP_VMIDMT_GIRPT_ENABLE_BMSK                                            0x2
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_AOP_VMIDMT_GIRPT_ENABLE_SHFT                                            0x1
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_VMIDMT_GIRPT_ENABLE_BMSK                                        0x1
#define HWIO_TCSR_VMIDMT_CLIENT_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_VMIDMT_GIRPT_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00005000)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_RMSK                                                                     0x3ffff
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_RESERVE_17_VMIDMT_GCFGIRPT_BMSK                                          0x20000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_RESERVE_17_VMIDMT_GCFGIRPT_SHFT                                             0x11
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_RESERVE_16_VMIDMT_GCFGIRPT_BMSK                                          0x10000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_RESERVE_16_VMIDMT_GCFGIRPT_SHFT                                             0x10
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_RESERVE_15_VMIDMT_GCFGIRPT_BMSK                                           0x8000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_RESERVE_15_VMIDMT_GCFGIRPT_SHFT                                              0xf
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_LPASS_2_VMIDMT_GCFGIRPT_BMSK                                              0x4000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_LPASS_2_VMIDMT_GCFGIRPT_SHFT                                                 0xe
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QSPI_VMIDMT_GCFGIRPT_BMSK                                                 0x2000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QSPI_VMIDMT_GCFGIRPT_SHFT                                                    0xd
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_SPDM_VMIDMT_GCFGIRPT_BMSK                                                 0x1000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_SPDM_VMIDMT_GCFGIRPT_SHFT                                                    0xc
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QDSS_DAP_VMIDMT_GCFGIRPT_BMSK                                              0x800
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QDSS_DAP_VMIDMT_GCFGIRPT_SHFT                                                0xb
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QDSS_TRACE_VMIDMT_GCFGIRPT_BMSK                                            0x400
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QDSS_TRACE_VMIDMT_GCFGIRPT_SHFT                                              0xa
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_IPA_VMIDMT_GCFGIRPT_BMSK                                                   0x200
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_IPA_VMIDMT_GCFGIRPT_SHFT                                                     0x9
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_LPASS_1_VMIDMT_GCFGIRPT_BMSK                                               0x100
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_LPASS_1_VMIDMT_GCFGIRPT_SHFT                                                 0x8
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_LPASS_0_VMIDMT_GCFGIRPT_BMSK                                                0x80
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_LPASS_0_VMIDMT_GCFGIRPT_SHFT                                                 0x7
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_SSC_VMIDMT_GCFGIRPT_BMSK                                                    0x40
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_SSC_VMIDMT_GCFGIRPT_SHFT                                                     0x6
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QUPV3_2_VMIDMT_GCFGIRPT_BMSK                                                0x20
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QUPV3_2_VMIDMT_GCFGIRPT_SHFT                                                 0x5
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QUPV3_1_VMIDMT_GCFGIRPT_BMSK                                                0x10
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QUPV3_1_VMIDMT_GCFGIRPT_SHFT                                                 0x4
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_SSC_SDC_VMIDMT_GCFGIRPT_BMSK                                                 0x8
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_SSC_SDC_VMIDMT_GCFGIRPT_SHFT                                                 0x3
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QUPV3_0_VMIDMT_GCFGIRPT_BMSK                                                 0x4
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_QUPV3_0_VMIDMT_GCFGIRPT_SHFT                                                 0x2
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_AOP_VMIDMT_GCFGIRPT_BMSK                                                     0x2
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_AOP_VMIDMT_GCFGIRPT_SHFT                                                     0x1
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_CRYPTO0_VMIDMT_GCFGIRPT_BMSK                                                 0x1
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_STATUS_REG_0_CRYPTO0_VMIDMT_GCFGIRPT_SHFT                                                 0x0

#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x00005040)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_RMSK                                                                   0x3ffff
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_RESERVE_17_VMIDMT_GCFGIRPT_ENABLE_BMSK                                 0x20000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_RESERVE_17_VMIDMT_GCFGIRPT_ENABLE_SHFT                                    0x11
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_RESERVE_16_VMIDMT_GCFGIRPT_ENABLE_BMSK                                 0x10000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_RESERVE_16_VMIDMT_GCFGIRPT_ENABLE_SHFT                                    0x10
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_RESERVE_15_VMIDMT_GCFGIRPT_ENABLE_BMSK                                  0x8000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_RESERVE_15_VMIDMT_GCFGIRPT_ENABLE_SHFT                                     0xf
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_LPASS_2_VMIDMT_GCFGIRPT_ENABLE_BMSK                                     0x4000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_LPASS_2_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0xe
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QSPI_VMIDMT_GCFGIRPT_ENABLE_BMSK                                        0x2000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QSPI_VMIDMT_GCFGIRPT_ENABLE_SHFT                                           0xd
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_SPDM_VMIDMT_GCFGIRPT_ENABLE_BMSK                                        0x1000
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_SPDM_VMIDMT_GCFGIRPT_ENABLE_SHFT                                           0xc
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QDSS_DAP_VMIDMT_GCFGIRPT_ENABLE_BMSK                                     0x800
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QDSS_DAP_VMIDMT_GCFGIRPT_ENABLE_SHFT                                       0xb
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QDSS_TRACE_VMIDMT_GCFGIRPT_ENABLE_BMSK                                   0x400
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QDSS_TRACE_VMIDMT_GCFGIRPT_ENABLE_SHFT                                     0xa
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_IPA_VMIDMT_GCFGIRPT_ENABLE_BMSK                                          0x200
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_IPA_VMIDMT_GCFGIRPT_ENABLE_SHFT                                            0x9
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_LPASS_1_VMIDMT_GCFGIRPT_ENABLE_BMSK                                      0x100
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_LPASS_1_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_LPASS_0_VMIDMT_GCFGIRPT_ENABLE_BMSK                                       0x80
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_LPASS_0_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0x7
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_SSC_VMIDMT_GCFGIRPT_ENABLE_BMSK                                           0x40
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_SSC_VMIDMT_GCFGIRPT_ENABLE_SHFT                                            0x6
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QUPV3_2_VMIDMT_GCFGIRPT_ENABLE_BMSK                                       0x20
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QUPV3_2_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0x5
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_VMIDMT_GCFGIRPT_ENABLE_BMSK                                       0x10
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QUPV3_1_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0x4
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_VMIDMT_GCFGIRPT_ENABLE_BMSK                                        0x8
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_SSC_SDC_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0x3
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_VMIDMT_GCFGIRPT_ENABLE_BMSK                                        0x4
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_QUPV3_0_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0x2
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_AOP_VMIDMT_GCFGIRPT_ENABLE_BMSK                                            0x2
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_AOP_VMIDMT_GCFGIRPT_ENABLE_SHFT                                            0x1
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_VMIDMT_GCFGIRPT_ENABLE_BMSK                                        0x1
#define HWIO_TCSR_VMIDMT_CFG_SEC_IRQ_ENABLE_0_REG_0_CRYPTO0_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_ADDR                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x00008020)
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RMSK                                                                    0xffffffff
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_BMSK                                      0x80000000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_SHFT                                            0x1f
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_BMSK                                      0x40000000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_SHFT                                            0x1e
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_BMSK                                      0x20000000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_SHFT                                            0x1d
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_BMSK                                      0x10000000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_SHFT                                            0x1c
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_BMSK                                       0x8000000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_SHFT                                            0x1b
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_BMSK                                       0x4000000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_SHFT                                            0x1a
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_BMSK                                       0x2000000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_SHFT                                            0x19
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_BMSK                                       0x1000000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_SHFT                                            0x18
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_BMSK                                           0x800000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_SHFT                                               0x17
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_BMSK                                           0x400000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_SHFT                                               0x16
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_BMSK                                           0x200000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_SHFT                                               0x15
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_BMSK                                        0x100000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_SHFT                                            0x14
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_BMSK                                           0x80000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_SHFT                                              0x13
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_BMSK                                           0x40000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_SHFT                                              0x12
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_BMSK                                         0x20000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_SHFT                                            0x11
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_BMSK                                         0x10000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_SHFT                                            0x10
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_BMSK                                          0x8000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_SHFT                                             0xf
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_BMSK                                          0x4000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_SHFT                                             0xe
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_BMSK                                          0x2000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_SHFT                                             0xd
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_BMSK                                          0x1000
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_SHFT                                             0xc
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_BMSK                                           0x800
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_SHFT                                             0xb
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_BMSK                                           0x400
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_SHFT                                             0xa
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_BMSK                                            0x200
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_SHFT                                              0x9
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_BMSK                                            0x100
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_SHFT                                              0x8
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_BMSK                                             0x80
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_SHFT                                              0x7
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_BMSK                                             0x40
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_SHFT                                              0x6
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_BMSK                                             0x20
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_SHFT                                              0x5
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_BMSK                                             0x10
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_SHFT                                              0x4
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_BMSK                                              0x8
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_SHFT                                              0x3
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_BMSK                                                0x4
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_SHFT                                                0x2
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_BMSK                                                0x2
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_SHFT                                                0x1
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_BMSK                                                  0x1
#define HWIO_TCSR_TIMEOUT_INTR_IRQ_STATUS_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_SHFT                                                  0x0

#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00027000)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RMSK                                                              0xffffffff
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x80000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x1f
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x40000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x1e
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x20000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x1d
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x10000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x1c
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x8000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x1b
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x4000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x1a
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x2000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x19
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x1000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x18
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_BMSK                              0x800000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_SHFT                                  0x17
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                              0x400000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                                  0x16
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                              0x200000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                  0x15
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x100000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x14
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                              0x80000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                                 0x13
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                              0x40000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                 0x12
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x20000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x11
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x10000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x10
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x8000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0xf
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x4000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0xe
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x2000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0xd
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x1000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0xc
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x800
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0xb
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x400
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0xa
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x200
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                 0x9
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x100
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                 0x8
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x80
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                 0x7
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x40
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                 0x6
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x20
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                 0x5
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x10
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                 0x4
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                 0x8
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                 0x3
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_ENABLE_BMSK                                   0x4
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_ENABLE_SHFT                                   0x2
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_ENABLE_BMSK                                   0x2
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_ENABLE_SHFT                                   0x1
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                     0x1
#define HWIO_TCSR_TIMEOUT_INTR_RPM_IRQ_ENABLE_0_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                     0x0

#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_ADDR                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x00028000)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RMSK                                                             0xffffffff
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x80000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x1f
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x40000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x1e
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x20000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x1d
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x10000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x1c
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x8000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x1b
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x4000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x1a
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x2000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x19
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x1000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x18
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_BMSK                             0x800000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_SHFT                                 0x17
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                             0x400000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                                 0x16
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                             0x200000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                 0x15
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x100000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x14
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                             0x80000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                                0x13
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                             0x40000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                0x12
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x20000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x11
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x10000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x10
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x8000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0xf
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x4000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0xe
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x2000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0xd
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x1000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0xc
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x800
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0xb
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x400
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0xa
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x200
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0x9
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x100
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0x8
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x80
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0x7
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x40
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0x6
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x20
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0x5
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x10
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0x4
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x8
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                0x3
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_ENABLE_BMSK                                  0x4
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_ENABLE_SHFT                                  0x2
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_ENABLE_BMSK                                  0x2
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_ENABLE_SHFT                                  0x1
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                    0x1
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_IRQ_ENABLE_0_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                    0x0

#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00029000)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RMSK                                                            0xffffffff
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                       0x80000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x1f
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                       0x40000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x1e
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                       0x20000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x1d
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                       0x10000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x1c
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x8000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x1b
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x4000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x1a
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x2000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x19
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x1000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x18
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_BMSK                            0x800000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_SHFT                                0x17
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                            0x400000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                                0x16
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                            0x200000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                0x15
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x100000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x14
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                            0x80000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                               0x13
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                            0x40000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                               0x12
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x20000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x11
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x10000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0x10
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x8000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0xf
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x4000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0xe
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x2000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0xd
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x1000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0xc
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x800
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0xb
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x400
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0xa
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x200
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x9
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x100
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x8
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x80
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x7
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x40
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x6
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x20
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x5
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x10
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x4
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x8
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                               0x3
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_ENABLE_BMSK                                 0x4
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_ENABLE_SHFT                                 0x2
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_ENABLE_BMSK                                 0x2
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_ENABLE_SHFT                                 0x1
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                   0x1
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_IRQ_ENABLE_0_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                   0x0

#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0002b000)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RMSK                                                           0xffffffff
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                      0x80000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x1f
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                      0x40000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x1e
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                      0x20000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x1d
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                      0x10000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x1c
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                       0x8000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x1b
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                       0x4000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x1a
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                       0x2000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x19
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                       0x1000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_24_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x18
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_BMSK                           0x800000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_SHFT                               0x17
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                           0x400000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                               0x16
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                           0x200000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                               0x15
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                        0x100000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_20_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x14
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                           0x80000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                              0x13
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                           0x40000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                              0x12
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x20000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x11
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                         0x10000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                            0x10
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x8000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0xf
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x4000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0xe
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x2000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0xd
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                          0x1000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0xc
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x800
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_11_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0xb
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                           0x400
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_10_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                             0xa
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x200
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x9
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                            0x100
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x8
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x80
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x7
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x40
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_6_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x6
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x20
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x5
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                             0x10
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x4
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                              0x8
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                              0x3
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_ENABLE_BMSK                                0x4
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT4_ENABLE_SHFT                                0x2
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_ENABLE_BMSK                                0x2
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_LPASS_IRQ_OUT_AHB_TIMEOUT3_ENABLE_SHFT                                0x1
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                  0x1
#define HWIO_TCSR_TIMEOUT_INTR_TURING_IRQ_ENABLE_0_REG_0_SSC_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                  0x0

#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002d060)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_RMSK                                                                    0xff
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_ADDR)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_I_TOP_IBI_I3C_INTR_BMSK                                                 0xff
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_STATUS_REG_0_I_TOP_IBI_I3C_INTR_SHFT                                                  0x0

#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0002d064)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_RMSK                                                                  0xff
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_IN          \
        in_dword(HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_ADDR)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_ADDR, m)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_ADDR,v)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_ADDR,m,v,HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_IN)
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_I_TOP_IBI_I3C_INTR_ENABLE_BMSK                                        0xff
#define HWIO_TCSR_TOP_IBI_I3C_CAMERA_IRQ_ENABLE_0_REG_0_I_TOP_IBI_I3C_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_SOC_HW_VERSION_ADDR                                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x00008000)
#define HWIO_TCSR_SOC_HW_VERSION_RMSK                                                                                   0xffffffff
#define HWIO_TCSR_SOC_HW_VERSION_IN          \
        in_dword(HWIO_TCSR_SOC_HW_VERSION_ADDR)
#define HWIO_TCSR_SOC_HW_VERSION_INM(m)      \
        in_dword_masked(HWIO_TCSR_SOC_HW_VERSION_ADDR, m)
#define HWIO_TCSR_SOC_HW_VERSION_FAMILY_NUMBER_BMSK                                                                     0xf0000000
#define HWIO_TCSR_SOC_HW_VERSION_FAMILY_NUMBER_SHFT                                                                           0x1c
#define HWIO_TCSR_SOC_HW_VERSION_DEVICE_NUMBER_BMSK                                                                      0xfff0000
#define HWIO_TCSR_SOC_HW_VERSION_DEVICE_NUMBER_SHFT                                                                           0x10
#define HWIO_TCSR_SOC_HW_VERSION_MAJOR_VERSION_BMSK                                                                         0xff00
#define HWIO_TCSR_SOC_HW_VERSION_MAJOR_VERSION_SHFT                                                                            0x8
#define HWIO_TCSR_SOC_HW_VERSION_MINOR_VERSION_BMSK                                                                           0xff
#define HWIO_TCSR_SOC_HW_VERSION_MINOR_VERSION_SHFT                                                                            0x0

#define HWIO_TCSR_SOC_EMULATION_TYPE_ADDR                                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00008004)
#define HWIO_TCSR_SOC_EMULATION_TYPE_RMSK                                                                                      0x3
#define HWIO_TCSR_SOC_EMULATION_TYPE_IN          \
        in_dword(HWIO_TCSR_SOC_EMULATION_TYPE_ADDR)
#define HWIO_TCSR_SOC_EMULATION_TYPE_INM(m)      \
        in_dword_masked(HWIO_TCSR_SOC_EMULATION_TYPE_ADDR, m)
#define HWIO_TCSR_SOC_EMULATION_TYPE_SOC_EMULATION_TYPE_BMSK                                                                   0x3
#define HWIO_TCSR_SOC_EMULATION_TYPE_SOC_EMULATION_TYPE_SHFT                                                                   0x0

#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x00008008)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_RMSK                                                                          0xffffffff
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_IN          \
        in_dword(HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_ADDR)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_INM(m)      \
        in_dword_masked(HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_ADDR, m)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_OUT(v)      \
        out_dword(HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_ADDR,v)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_ADDR,m,v,HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_IN)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_FAMILY_NUMBER_BMSK                                                   0xf0000000
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_FAMILY_NUMBER_SHFT                                                         0x1c
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_DEVICE_NUMBER_BMSK                                                    0xfff0000
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_DEVICE_NUMBER_SHFT                                                         0x10
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_MAJOR_VERSION_BMSK                                                       0xff00
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_MAJOR_VERSION_SHFT                                                          0x8
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_MINOR_VERSION_BMSK                                                         0xff
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_MINOR_VERSION_SHFT                                                          0x0

#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00008070)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_RMSK                                                                        0xffffffff
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_IN          \
        in_dword(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_ADDR)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_ADDR, m)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_SRAM_REDUNDANCY_CRC_ERR_BMSK                                                0xffffffff
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_0_SRAM_REDUNDANCY_CRC_ERR_SHFT                                                       0x0

#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00008074)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_RMSK                                                                        0xffffffff
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_IN          \
        in_dword(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_ADDR)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_ADDR, m)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_SRAM_REDUNDANCY_CRC_ERR_BMSK                                                0xffffffff
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_1_SRAM_REDUNDANCY_CRC_ERR_SHFT                                                       0x0

#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00008078)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_RMSK                                                                        0xffffffff
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_IN          \
        in_dword(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_ADDR)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_ADDR, m)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_SRAM_REDUNDANCY_CRC_ERR_BMSK                                                0xffffffff
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_2_SRAM_REDUNDANCY_CRC_ERR_SHFT                                                       0x0

#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x0000807c)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_RMSK                                                                        0xffffffff
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_IN          \
        in_dword(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_ADDR)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_INM(m)      \
        in_dword_masked(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_ADDR, m)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_SRAM_REDUNDANCY_CRC_ERR_BMSK                                                0xffffffff
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_3_SRAM_REDUNDANCY_CRC_ERR_SHFT                                                       0x0

#define HWIO_TCSR_TCSR_CLK_EN_ADDR                                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0000907c)
#define HWIO_TCSR_TCSR_CLK_EN_RMSK                                                                                             0x1
#define HWIO_TCSR_TCSR_CLK_EN_IN          \
        in_dword(HWIO_TCSR_TCSR_CLK_EN_ADDR)
#define HWIO_TCSR_TCSR_CLK_EN_INM(m)      \
        in_dword_masked(HWIO_TCSR_TCSR_CLK_EN_ADDR, m)
#define HWIO_TCSR_TCSR_CLK_EN_OUT(v)      \
        out_dword(HWIO_TCSR_TCSR_CLK_EN_ADDR,v)
#define HWIO_TCSR_TCSR_CLK_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TCSR_CLK_EN_ADDR,m,v,HWIO_TCSR_TCSR_CLK_EN_IN)
#define HWIO_TCSR_TCSR_CLK_EN_TCSR_CLK_EN_BMSK                                                                                 0x1
#define HWIO_TCSR_TCSR_CLK_EN_TCSR_CLK_EN_SHFT                                                                                 0x0

#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_ADDR                                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x0000a100)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_RMSK                                                                                    0x1
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_IN          \
        in_dword(HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_ADDR)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_INM(m)      \
        in_dword_masked(HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_ADDR, m)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_OUT(v)      \
        out_dword(HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_ADDR,v)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_ADDR,m,v,HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_IN)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_TCSR_IPA_WARMBOOT_EN_BMSK                                                               0x1
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_TCSR_IPA_WARMBOOT_EN_SHFT                                                               0x0

#define HWIO_TCSR_SYS_POWER_CTRL_ADDR                                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0000a000)
#define HWIO_TCSR_SYS_POWER_CTRL_RMSK                                                                                       0xffff
#define HWIO_TCSR_SYS_POWER_CTRL_IN          \
        in_dword(HWIO_TCSR_SYS_POWER_CTRL_ADDR)
#define HWIO_TCSR_SYS_POWER_CTRL_INM(m)      \
        in_dword_masked(HWIO_TCSR_SYS_POWER_CTRL_ADDR, m)
#define HWIO_TCSR_SYS_POWER_CTRL_OUT(v)      \
        out_dword(HWIO_TCSR_SYS_POWER_CTRL_ADDR,v)
#define HWIO_TCSR_SYS_POWER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SYS_POWER_CTRL_ADDR,m,v,HWIO_TCSR_SYS_POWER_CTRL_IN)
#define HWIO_TCSR_SYS_POWER_CTRL_SYS_POWER_CTRL_BMSK                                                                        0xffff
#define HWIO_TCSR_SYS_POWER_CTRL_SYS_POWER_CTRL_SHFT                                                                           0x0

#define HWIO_TCSR_USB_CORE_ID_ADDR                                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0000a004)
#define HWIO_TCSR_USB_CORE_ID_RMSK                                                                                             0x3
#define HWIO_TCSR_USB_CORE_ID_IN          \
        in_dword(HWIO_TCSR_USB_CORE_ID_ADDR)
#define HWIO_TCSR_USB_CORE_ID_INM(m)      \
        in_dword_masked(HWIO_TCSR_USB_CORE_ID_ADDR, m)
#define HWIO_TCSR_USB_CORE_ID_OUT(v)      \
        out_dword(HWIO_TCSR_USB_CORE_ID_ADDR,v)
#define HWIO_TCSR_USB_CORE_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_USB_CORE_ID_ADDR,m,v,HWIO_TCSR_USB_CORE_ID_IN)
#define HWIO_TCSR_USB_CORE_ID_USB_CORE_ID_BMSK                                                                                 0x3
#define HWIO_TCSR_USB_CORE_ID_USB_CORE_ID_SHFT                                                                                 0x0

#define HWIO_TCSR_SPARE0_REG0_ADDR                                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0000a044)
#define HWIO_TCSR_SPARE0_REG0_RMSK                                                                                      0xffffffff
#define HWIO_TCSR_SPARE0_REG0_IN          \
        in_dword(HWIO_TCSR_SPARE0_REG0_ADDR)
#define HWIO_TCSR_SPARE0_REG0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPARE0_REG0_ADDR, m)
#define HWIO_TCSR_SPARE0_REG0_OUT(v)      \
        out_dword(HWIO_TCSR_SPARE0_REG0_ADDR,v)
#define HWIO_TCSR_SPARE0_REG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPARE0_REG0_ADDR,m,v,HWIO_TCSR_SPARE0_REG0_IN)
#define HWIO_TCSR_SPARE0_REG0_SPARE0_REG0_BMSK                                                                          0xffffffff
#define HWIO_TCSR_SPARE0_REG0_SPARE0_REG0_SHFT                                                                                 0x0

#define HWIO_TCSR_SPARE0_REG1_ADDR                                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0000a048)
#define HWIO_TCSR_SPARE0_REG1_RMSK                                                                                      0xffffffff
#define HWIO_TCSR_SPARE0_REG1_IN          \
        in_dword(HWIO_TCSR_SPARE0_REG1_ADDR)
#define HWIO_TCSR_SPARE0_REG1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPARE0_REG1_ADDR, m)
#define HWIO_TCSR_SPARE0_REG1_OUT(v)      \
        out_dword(HWIO_TCSR_SPARE0_REG1_ADDR,v)
#define HWIO_TCSR_SPARE0_REG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPARE0_REG1_ADDR,m,v,HWIO_TCSR_SPARE0_REG1_IN)
#define HWIO_TCSR_SPARE0_REG1_SPARE0_REG1_BMSK                                                                          0xffffffff
#define HWIO_TCSR_SPARE0_REG1_SPARE0_REG1_SHFT                                                                                 0x0

#define HWIO_TCSR_SPARE1_REG0_ADDR                                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0000a04c)
#define HWIO_TCSR_SPARE1_REG0_RMSK                                                                                      0xffffffff
#define HWIO_TCSR_SPARE1_REG0_IN          \
        in_dword(HWIO_TCSR_SPARE1_REG0_ADDR)
#define HWIO_TCSR_SPARE1_REG0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPARE1_REG0_ADDR, m)
#define HWIO_TCSR_SPARE1_REG0_OUT(v)      \
        out_dword(HWIO_TCSR_SPARE1_REG0_ADDR,v)
#define HWIO_TCSR_SPARE1_REG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPARE1_REG0_ADDR,m,v,HWIO_TCSR_SPARE1_REG0_IN)
#define HWIO_TCSR_SPARE1_REG0_SPARE1_REG0_BMSK                                                                          0xffffffff
#define HWIO_TCSR_SPARE1_REG0_SPARE1_REG0_SHFT                                                                                 0x0

#define HWIO_TCSR_SPARE1_REG1_ADDR                                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0000a050)
#define HWIO_TCSR_SPARE1_REG1_RMSK                                                                                      0xffffffff
#define HWIO_TCSR_SPARE1_REG1_IN          \
        in_dword(HWIO_TCSR_SPARE1_REG1_ADDR)
#define HWIO_TCSR_SPARE1_REG1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPARE1_REG1_ADDR, m)
#define HWIO_TCSR_SPARE1_REG1_OUT(v)      \
        out_dword(HWIO_TCSR_SPARE1_REG1_ADDR,v)
#define HWIO_TCSR_SPARE1_REG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPARE1_REG1_ADDR,m,v,HWIO_TCSR_SPARE1_REG1_IN)
#define HWIO_TCSR_SPARE1_REG1_SPARE1_REG1_BMSK                                                                          0xffffffff
#define HWIO_TCSR_SPARE1_REG1_SPARE1_REG1_SHFT                                                                                 0x0

#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_ADDR                                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x00001010)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_RMSK                                                                                    0xffff
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_IN          \
        in_dword(HWIO_TCSR_SPDM_CNT_CLK_CTRL_ADDR)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPDM_CNT_CLK_CTRL_ADDR, m)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_OUT(v)      \
        out_dword(HWIO_TCSR_SPDM_CNT_CLK_CTRL_ADDR,v)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPDM_CNT_CLK_CTRL_ADDR,m,v,HWIO_TCSR_SPDM_CNT_CLK_CTRL_IN)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_SPDM_CNT_CLK_MUX_SEL_BMSK                                                               0xffff
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_SPDM_CNT_CLK_MUX_SEL_SHFT                                                                  0x0

#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_ADDR                                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x00001018)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_RMSK                                                                                0xffffffff
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_IN          \
        in_dword(HWIO_TCSR_SPDM_WRP_CTI_CTL0_ADDR)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPDM_WRP_CTI_CTL0_ADDR, m)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_OUT(v)      \
        out_dword(HWIO_TCSR_SPDM_WRP_CTI_CTL0_ADDR,v)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPDM_WRP_CTI_CTL0_ADDR,m,v,HWIO_TCSR_SPDM_WRP_CTI_CTL0_IN)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_SPDM_WRP_CTI_CTL0_BMSK                                                              0xffffffff
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_SPDM_WRP_CTI_CTL0_SHFT                                                                     0x0

#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_ADDR                                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0000101c)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_RMSK                                                                                0xffffffff
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_IN          \
        in_dword(HWIO_TCSR_SPDM_WRP_CTI_CTL1_ADDR)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPDM_WRP_CTI_CTL1_ADDR, m)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_OUT(v)      \
        out_dword(HWIO_TCSR_SPDM_WRP_CTI_CTL1_ADDR,v)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPDM_WRP_CTI_CTL1_ADDR,m,v,HWIO_TCSR_SPDM_WRP_CTI_CTL1_IN)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_SPDM_WRP_CTI_CTL1_BMSK                                                              0xffffffff
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_SPDM_WRP_CTI_CTL1_SHFT                                                                     0x0

#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00016000)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_RMSK                                                                               0x3
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_IN          \
        in_dword(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_ADDR)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_ADDR, m)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_OUT(v)      \
        out_dword(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_ADDR,v)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_ADDR,m,v,HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_IN)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_TEST_EN_1_BMSK                                                                     0x2
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_TEST_EN_1_SHFT                                                                     0x1
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_TEST_DATA_1_BMSK                                                                   0x1
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_TEST_DATA_1_SHFT                                                                   0x0

#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00016004)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_RMSK                                                                               0x3
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_IN          \
        in_dword(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_ADDR)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_ADDR, m)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_OUT(v)      \
        out_dword(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_ADDR,v)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_ADDR,m,v,HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_IN)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_TEST_EN_0_BMSK                                                                     0x2
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_TEST_EN_0_SHFT                                                                     0x1
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_TEST_DATA_0_BMSK                                                                   0x1
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_TEST_DATA_0_SHFT                                                                   0x0

#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_ADDR                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x00017000)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_RMSK                                                                             0x3
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_IN          \
        in_dword(HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_ADDR)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_INM(m)      \
        in_dword_masked(HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_ADDR, m)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_OUT(v)      \
        out_dword(HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_ADDR,v)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_ADDR,m,v,HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_IN)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_QDSS_NS_ENABLE_BACKPRESSURE_BMSK                                                 0x2
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_QDSS_NS_ENABLE_BACKPRESSURE_SHFT                                                 0x1
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_QDSS_NS_ENABLE_EVENT_IFACE_BMSK                                                  0x1
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_QDSS_NS_ENABLE_EVENT_IFACE_SHFT                                                  0x0

#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_ADDR                                                                     (TCSR_TCSR_REGS_REG_BASE      + 0x00017004)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_RMSK                                                                            0x3
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_IN          \
        in_dword(HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_ADDR)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_INM(m)      \
        in_dword_masked(HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_ADDR, m)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_OUT(v)      \
        out_dword(HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_ADDR,v)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_ADDR,m,v,HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_IN)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_QDSS_SEC_ENABLE_BACKPRESSURE_BMSK                                               0x2
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_QDSS_SEC_ENABLE_BACKPRESSURE_SHFT                                               0x1
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_QDSS_SEC_ENABLE_EVENT_IFACE_BMSK                                                0x1
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_QDSS_SEC_ENABLE_EVENT_IFACE_SHFT                                                0x0

#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_ADDR                                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00017008)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_RMSK                                                                                0x1
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_IN          \
        in_dword(HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_ADDR)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_INM(m)      \
        in_dword_masked(HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_ADDR, m)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_OUT(v)      \
        out_dword(HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_ADDR,v)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_ADDR,m,v,HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_IN)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_QDSS_NS_ETR_TRACE_BMSK                                                              0x1
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_QDSS_NS_ETR_TRACE_SHFT                                                              0x0

#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x00011000)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_RMSK                                                                       0x1
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_IN          \
        in_dword(HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_ADDR)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_INM(m)      \
        in_dword_masked(HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_ADDR, m)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_OUT(v)      \
        out_dword(HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_ADDR,v)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_ADDR,m,v,HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_IN)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_VSENSE_CONTROLLER_ENABLE_REGISTER_BMSK                                     0x1
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_VSENSE_CONTROLLER_ENABLE_REGISTER_SHFT                                     0x0

#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00012000)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_RMSK                                                                        0xffffffff
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_IN          \
        in_dword(HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_ADDR)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_INM(m)      \
        in_dword_masked(HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_ADDR, m)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_OUT(v)      \
        out_dword(HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_ADDR,v)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_ADDR,m,v,HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_IN)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_TCSR_RESET_DEBUG_SW_ENTRY_BMSK                                              0xffffffff
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_TCSR_RESET_DEBUG_SW_ENTRY_SHFT                                                     0x0

#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00013000)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_RMSK                                                                            0xffffffff
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_IN          \
        in_dword(HWIO_TCSR_TCSR_BOOT_MISC_DETECT_ADDR)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_INM(m)      \
        in_dword_masked(HWIO_TCSR_TCSR_BOOT_MISC_DETECT_ADDR, m)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_OUT(v)      \
        out_dword(HWIO_TCSR_TCSR_BOOT_MISC_DETECT_ADDR,v)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TCSR_BOOT_MISC_DETECT_ADDR,m,v,HWIO_TCSR_TCSR_BOOT_MISC_DETECT_IN)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_TCSR_BOOT_MISC_DETECT_BMSK                                                      0xffffffff
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_TCSR_BOOT_MISC_DETECT_SHFT                                                             0x0

#define HWIO_TCSR_TZ_WONCE_n_ADDR(n)                                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x00014000 + 0x4 * (n))
#define HWIO_TCSR_TZ_WONCE_n_RMSK                                                                                       0xffffffff
#define HWIO_TCSR_TZ_WONCE_n_MAXn                                                                                               15
#define HWIO_TCSR_TZ_WONCE_n_INI(n)        \
        in_dword_masked(HWIO_TCSR_TZ_WONCE_n_ADDR(n), HWIO_TCSR_TZ_WONCE_n_RMSK)
#define HWIO_TCSR_TZ_WONCE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_TCSR_TZ_WONCE_n_ADDR(n), mask)
#define HWIO_TCSR_TZ_WONCE_n_OUTI(n,val)    \
        out_dword(HWIO_TCSR_TZ_WONCE_n_ADDR(n),val)
#define HWIO_TCSR_TZ_WONCE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_TCSR_TZ_WONCE_n_ADDR(n),mask,val,HWIO_TCSR_TZ_WONCE_n_INI(n))
#define HWIO_TCSR_TZ_WONCE_n_TZ_WONCE_ADDRESS_BMSK                                                                      0xffffffff
#define HWIO_TCSR_TZ_WONCE_n_TZ_WONCE_ADDRESS_SHFT                                                                             0x0

#define HWIO_TCSR_QREFS_RPT_CONFIG_ADDR                                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x00015000)
#define HWIO_TCSR_QREFS_RPT_CONFIG_RMSK                                                                                     0xffff
#define HWIO_TCSR_QREFS_RPT_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_RPT_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_RPT_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_RPT_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_RPT_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_RPT_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_RPT_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_RPT_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_RPT_CONFIG_IN)
#define HWIO_TCSR_QREFS_RPT_CONFIG_QREFS_RPT_CONFIG_BUS_SELECT_BMSK                                                         0xffff
#define HWIO_TCSR_QREFS_RPT_CONFIG_QREFS_RPT_CONFIG_BUS_SELECT_SHFT                                                            0x0

#define HWIO_TCSR_QREFS_TXVBG_CONFIG_ADDR                                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00015004)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_RMSK                                                                                   0xffff
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_TXVBG_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_TXVBG_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_TXVBG_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_TXVBG_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_TXVBG_CONFIG_IN)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_QREFS_TXVBG_CONFIG_BMSK                                                                0xffff
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_QREFS_TXVBG_CONFIG_SHFT                                                                   0x0

#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_ADDR                                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x00015008)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_RMSK                                                                                   0xff
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO_RX3_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RX3_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO_RX3_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO_RX3_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO_RX3_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_QREFS_CXO_RX3_CONFIG_BMSK                                                              0xff
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_QREFS_CXO_RX3_CONFIG_SHFT                                                               0x0

#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_ADDR                                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x0001500c)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_RMSK                                                                                   0xff
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO_RX2_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RX2_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO_RX2_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO_RX2_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO_RX2_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_QREFS_CXO_RX2_CONFIG_BMSK                                                              0xff
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_QREFS_CXO_RX2_CONFIG_SHFT                                                               0x0

#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00015010)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_RMSK                                                                                  0xff
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_QREFS_CXO_RPT2_CONFIG_BMSK                                                            0xff
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_QREFS_CXO_RPT2_CONFIG_SHFT                                                             0x0

#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00015018)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_RMSK                                                                                  0xff
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_QREFS_CXO2_RX0_CONFIG_BMSK                                                            0xff
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_QREFS_CXO2_RX0_CONFIG_SHFT                                                             0x0

#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_ADDR                                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0001501c)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_RMSK                                                                                 0xff
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_QREFS_CXO2_RPT1_CONFIG_BMSK                                                          0xff
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_QREFS_CXO2_RPT1_CONFIG_SHFT                                                           0x0

#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_ADDR                                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00015020)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_RMSK                                                                                 0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_QREFS_CXO2_RPT0_CONFIG_BMSK                                                          0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_QREFS_CXO2_RPT0_CONFIG_SHFT                                                           0x0

#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_ADDR                                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00015024)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_RMSK                                                                             0xffff
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_QREFS_CXO2_TXVBG0_CONFIG_BMSK                                                    0xffff
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_QREFS_CXO2_TXVBG0_CONFIG_SHFT                                                       0x0

#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0001502c)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_RMSK                                                                                  0xff
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_QREFS_CXO_RPT3_CONFIG_BMSK                                                            0xff
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_QREFS_CXO_RPT3_CONFIG_SHFT                                                             0x0

#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x00015030)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_RMSK                                                                                0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_QREFS_CXO2_RPT0A_CONFIG_BMSK                                                        0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_QREFS_CXO2_RPT0A_CONFIG_SHFT                                                         0x0

#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x00015034)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_RMSK                                                                                0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_QREFS_CXO2_RPT0B_CONFIG_BMSK                                                        0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_QREFS_CXO2_RPT0B_CONFIG_SHFT                                                         0x0

#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_ADDR                                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x00015038)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_RMSK                                                                                   0xff
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_IN          \
        in_dword(HWIO_TCSR_QREFS_CXO_RX1_CONFIG_ADDR)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RX1_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO_RX1_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO_RX1_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO_RX1_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_QREFS_CXO_RX1_CONFIG_BMSK                                                              0xff
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_QREFS_CXO_RX1_CONFIG_SHFT                                                               0x0

#define HWIO_TCSR_QZIP_CTL_ST_ADDR                                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0000c000)
#define HWIO_TCSR_QZIP_CTL_ST_RMSK                                                                                            0xff
#define HWIO_TCSR_QZIP_CTL_ST_IN          \
        in_dword(HWIO_TCSR_QZIP_CTL_ST_ADDR)
#define HWIO_TCSR_QZIP_CTL_ST_INM(m)      \
        in_dword_masked(HWIO_TCSR_QZIP_CTL_ST_ADDR, m)
#define HWIO_TCSR_QZIP_CTL_ST_OUT(v)      \
        out_dword(HWIO_TCSR_QZIP_CTL_ST_ADDR,v)
#define HWIO_TCSR_QZIP_CTL_ST_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QZIP_CTL_ST_ADDR,m,v,HWIO_TCSR_QZIP_CTL_ST_IN)
#define HWIO_TCSR_QZIP_CTL_ST_QZIP_CTL_ST_BMSK                                                                                0xff
#define HWIO_TCSR_QZIP_CTL_ST_QZIP_CTL_ST_SHFT                                                                                 0x0

#define HWIO_TCSR_TIC_CNOC_NS_ADDR                                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0000c004)
#define HWIO_TCSR_TIC_CNOC_NS_RMSK                                                                                             0x1
#define HWIO_TCSR_TIC_CNOC_NS_IN          \
        in_dword(HWIO_TCSR_TIC_CNOC_NS_ADDR)
#define HWIO_TCSR_TIC_CNOC_NS_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIC_CNOC_NS_ADDR, m)
#define HWIO_TCSR_TIC_CNOC_NS_OUT(v)      \
        out_dword(HWIO_TCSR_TIC_CNOC_NS_ADDR,v)
#define HWIO_TCSR_TIC_CNOC_NS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIC_CNOC_NS_ADDR,m,v,HWIO_TCSR_TIC_CNOC_NS_IN)
#define HWIO_TCSR_TIC_CNOC_NS_TIC_CNOC_NS_BMSK                                                                                 0x1
#define HWIO_TCSR_TIC_CNOC_NS_TIC_CNOC_NS_SHFT                                                                                 0x0

#define HWIO_TCSR_CONN_BOX_SPARE_0_ADDR                                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000e000)
#define HWIO_TCSR_CONN_BOX_SPARE_0_RMSK                                                                                 0xffffffff
#define HWIO_TCSR_CONN_BOX_SPARE_0_IN          \
        in_dword(HWIO_TCSR_CONN_BOX_SPARE_0_ADDR)
#define HWIO_TCSR_CONN_BOX_SPARE_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_CONN_BOX_SPARE_0_ADDR, m)
#define HWIO_TCSR_CONN_BOX_SPARE_0_OUT(v)      \
        out_dword(HWIO_TCSR_CONN_BOX_SPARE_0_ADDR,v)
#define HWIO_TCSR_CONN_BOX_SPARE_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_CONN_BOX_SPARE_0_ADDR,m,v,HWIO_TCSR_CONN_BOX_SPARE_0_IN)
#define HWIO_TCSR_CONN_BOX_SPARE_0_CONN_BOX_SPARE_0_BMSK                                                                0xffffffff
#define HWIO_TCSR_CONN_BOX_SPARE_0_CONN_BOX_SPARE_0_SHFT                                                                       0x0

#define HWIO_TCSR_CONN_BOX_SPARE_1_ADDR                                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000f000)
#define HWIO_TCSR_CONN_BOX_SPARE_1_RMSK                                                                                 0xffffffff
#define HWIO_TCSR_CONN_BOX_SPARE_1_IN          \
        in_dword(HWIO_TCSR_CONN_BOX_SPARE_1_ADDR)
#define HWIO_TCSR_CONN_BOX_SPARE_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_CONN_BOX_SPARE_1_ADDR, m)
#define HWIO_TCSR_CONN_BOX_SPARE_1_OUT(v)      \
        out_dword(HWIO_TCSR_CONN_BOX_SPARE_1_ADDR,v)
#define HWIO_TCSR_CONN_BOX_SPARE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_CONN_BOX_SPARE_1_ADDR,m,v,HWIO_TCSR_CONN_BOX_SPARE_1_IN)
#define HWIO_TCSR_CONN_BOX_SPARE_1_CONN_BOX_SPARE_1_BMSK                                                                0xffffffff
#define HWIO_TCSR_CONN_BOX_SPARE_1_CONN_BOX_SPARE_1_SHFT                                                                       0x0

#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_ADDR                                                                     (TCSR_TCSR_REGS_REG_BASE      + 0x00018000)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_RMSK                                                                     0xffffffff
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_IN          \
        in_dword(HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_ADDR)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_INM(m)      \
        in_dword_masked(HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_ADDR, m)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_OUT(v)      \
        out_dword(HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_ADDR,v)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_ADDR,m,v,HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_IN)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_CFG_BITS_SHFT_BMSK                                                       0xffffffff
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_CFG_BITS_SHFT_SHFT                                                              0x0

#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00019000)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_RMSK                                                                  0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_IN          \
        in_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_ADDR)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_ADDR, m)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_OUT(v)      \
        out_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_ADDR,v)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_ADDR,m,v,HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_IN)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_USER_COMPUTE_SIGNALING_WRITE_STATUS_BMSK                              0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_USER_COMPUTE_SIGNALING_WRITE_STATUS_SHFT                                     0x0

#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00019004)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_RMSK                                                                  0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_IN          \
        in_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_ADDR)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_ADDR, m)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_OUT(v)      \
        out_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_ADDR,v)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_ADDR,m,v,HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_IN)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_USER_COMPUTE_SIGNALING_WRITE_STATUS_BMSK                              0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_USER_COMPUTE_SIGNALING_WRITE_STATUS_SHFT                                     0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0001a000)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_RMSK                                                           0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_ADDR)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_0_STATUS_USER_BMSK                                   0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_0_STATUS_USER_SHFT                                          0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0001a400)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_RMSK                                                            0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_0_CLEAR_USER_BMSK                                     0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_0_CLEAR_USER_SHFT                                            0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_ADDR                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x0001a800)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_RMSK                                                             0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_ADDR)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_ADDR,m,v,HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_IN)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_0_MASK_USER_BMSK                                       0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_0_MASK_USER_SHFT                                              0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0001b000)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_RMSK                                                           0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_ADDR)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_1_STATUS_USER_BMSK                                   0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_1_STATUS_USER_SHFT                                          0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0001b400)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_RMSK                                                            0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_1_CLEAR_USER_BMSK                                     0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_1_CLEAR_USER_SHFT                                            0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_ADDR                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x0001b800)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_RMSK                                                             0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_ADDR)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_ADDR,m,v,HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_IN)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_1_MASK_USER_BMSK                                       0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_1_MASK_USER_SHFT                                              0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0001c000)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_RMSK                                                           0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_ADDR)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_2_STATUS_USER_BMSK                                   0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_2_STATUS_USER_SHFT                                          0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0001c400)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_RMSK                                                            0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_2_CLEAR_USER_BMSK                                     0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_2_CLEAR_USER_SHFT                                            0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_ADDR                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x0001c800)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_RMSK                                                             0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_ADDR)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_ADDR,m,v,HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_IN)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_2_MASK_USER_BMSK                                       0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_2_MASK_USER_SHFT                                              0x0

#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0001d000)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_RMSK                                                                0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_IN          \
        in_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_ADDR)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_ADDR, m)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_OUT(v)      \
        out_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_ADDR,v)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_ADDR,m,v,HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_IN)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_KERNEL_COMPUTE_SIGNALING_WRITE_STATUS_BMSK                          0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_KERNEL_COMPUTE_SIGNALING_WRITE_STATUS_SHFT                                 0x0

#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_ADDR                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0001d004)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_RMSK                                                                0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_IN          \
        in_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_ADDR)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_ADDR, m)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_OUT(v)      \
        out_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_ADDR,v)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_ADDR,m,v,HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_IN)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_KERNEL_COMPUTE_SIGNALING_WRITE_STATUS_BMSK                          0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_KERNEL_COMPUTE_SIGNALING_WRITE_STATUS_SHFT                                 0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x0001e000)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_RMSK                                                         0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_0_STATUS_KERNEL_BMSK                               0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_0_STATUS_KERNEL_SHFT                                      0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x0001e400)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_RMSK                                                          0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_0_CLEAR_KERNEL_BMSK                                 0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_0_CLEAR_KERNEL_SHFT                                        0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0001e800)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_RMSK                                                           0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_ADDR)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,m,v,HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_IN)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_0_MASK_KERNEL_BMSK                                   0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_0_MASK_KERNEL_SHFT                                          0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x0001f000)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_RMSK                                                         0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_1_STATUS_KERNEL_BMSK                               0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_1_STATUS_KERNEL_SHFT                                      0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x0001f400)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_RMSK                                                          0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_1_CLEAR_KERNEL_BMSK                                 0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_1_CLEAR_KERNEL_SHFT                                        0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0001f800)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_RMSK                                                           0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_ADDR)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,m,v,HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_IN)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_1_MASK_KERNEL_BMSK                                   0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_1_MASK_KERNEL_SHFT                                          0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00020000)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_RMSK                                                         0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_2_STATUS_KERNEL_BMSK                               0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_2_STATUS_KERNEL_SHFT                                      0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x00020400)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_RMSK                                                          0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_2_CLEAR_KERNEL_BMSK                                 0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_2_CLEAR_KERNEL_SHFT                                        0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00020800)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_RMSK                                                           0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_IN          \
        in_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_ADDR)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,m,v,HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_IN)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_2_MASK_KERNEL_BMSK                                   0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_2_MASK_KERNEL_SHFT                                          0x0

#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_ADDR                                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00023000)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_RMSK                                                                                  0x3
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_IN          \
        in_dword(HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_ADDR)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_INM(m)      \
        in_dword_masked(HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_ADDR, m)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_OUT(v)      \
        out_dword(HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_ADDR,v)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_ADDR,m,v,HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_IN)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_A1NOC_SP_BYPASS_CHECK_TYPE_BMSK                                                       0x2
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_A1NOC_SP_BYPASS_CHECK_TYPE_SHFT                                                       0x1
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_A1NOC_MSA_BYPASS_CHECK_TYPE_BMSK                                                      0x1
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_A1NOC_MSA_BYPASS_CHECK_TYPE_SHFT                                                      0x0

#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_ADDR                                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00023004)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_RMSK                                                                                  0x3
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_IN          \
        in_dword(HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_ADDR)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_INM(m)      \
        in_dword_masked(HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_ADDR, m)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_OUT(v)      \
        out_dword(HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_ADDR,v)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_ADDR,m,v,HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_IN)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_A2NOC_SP_BYPASS_CHECK_TYPE_BMSK                                                       0x2
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_A2NOC_SP_BYPASS_CHECK_TYPE_SHFT                                                       0x1
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_A2NOC_MSA_BYPASS_CHECK_TYPE_BMSK                                                      0x1
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_A2NOC_MSA_BYPASS_CHECK_TYPE_SHFT                                                      0x0

#define HWIO_TCSR_WCSS_TESTBUS_SEL_ADDR                                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x00024000)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_RMSK                                                                                       0xff
#define HWIO_TCSR_WCSS_TESTBUS_SEL_IN          \
        in_dword(HWIO_TCSR_WCSS_TESTBUS_SEL_ADDR)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_WCSS_TESTBUS_SEL_ADDR, m)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_OUT(v)      \
        out_dword(HWIO_TCSR_WCSS_TESTBUS_SEL_ADDR,v)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_WCSS_TESTBUS_SEL_ADDR,m,v,HWIO_TCSR_WCSS_TESTBUS_SEL_IN)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_WCSS_TESTBUS_SEL_BMSK                                                                      0xff
#define HWIO_TCSR_WCSS_TESTBUS_SEL_WCSS_TESTBUS_SEL_SHFT                                                                       0x0

#define HWIO_TCSR_WCSS_AHBBM_CTRL_ADDR                                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00024004)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_RMSK                                                                                         0x7
#define HWIO_TCSR_WCSS_AHBBM_CTRL_IN          \
        in_dword(HWIO_TCSR_WCSS_AHBBM_CTRL_ADDR)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_INM(m)      \
        in_dword_masked(HWIO_TCSR_WCSS_AHBBM_CTRL_ADDR, m)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_OUT(v)      \
        out_dword(HWIO_TCSR_WCSS_AHBBM_CTRL_ADDR,v)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_WCSS_AHBBM_CTRL_ADDR,m,v,HWIO_TCSR_WCSS_AHBBM_CTRL_IN)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_SOFT_RESET_BMSK                                                                        0x4
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_SOFT_RESET_SHFT                                                                        0x2
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_CLKGATE_DISABLE_BMSK                                                                   0x2
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_CLKGATE_DISABLE_SHFT                                                                   0x1
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_ROOT_CLK_ENABLE_BMSK                                                                   0x1
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_ROOT_CLK_ENABLE_SHFT                                                                   0x0

#define HWIO_TCSR_APSS_SPARE_REG0_ADDR                                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00025014)
#define HWIO_TCSR_APSS_SPARE_REG0_RMSK                                                                                  0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG0_IN          \
        in_dword(HWIO_TCSR_APSS_SPARE_REG0_ADDR)
#define HWIO_TCSR_APSS_SPARE_REG0_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG0_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG0_OUT(v)      \
        out_dword(HWIO_TCSR_APSS_SPARE_REG0_ADDR,v)
#define HWIO_TCSR_APSS_SPARE_REG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_APSS_SPARE_REG0_ADDR,m,v,HWIO_TCSR_APSS_SPARE_REG0_IN)
#define HWIO_TCSR_APSS_SPARE_REG0_SPARE_REG0_BMSK                                                                       0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG0_SPARE_REG0_SHFT                                                                              0x0

#define HWIO_TCSR_APSS_SPARE_REG1_ADDR                                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00025018)
#define HWIO_TCSR_APSS_SPARE_REG1_RMSK                                                                                  0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG1_IN          \
        in_dword(HWIO_TCSR_APSS_SPARE_REG1_ADDR)
#define HWIO_TCSR_APSS_SPARE_REG1_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG1_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG1_OUT(v)      \
        out_dword(HWIO_TCSR_APSS_SPARE_REG1_ADDR,v)
#define HWIO_TCSR_APSS_SPARE_REG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_APSS_SPARE_REG1_ADDR,m,v,HWIO_TCSR_APSS_SPARE_REG1_IN)
#define HWIO_TCSR_APSS_SPARE_REG1_SPARE_REG1_BMSK                                                                       0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG1_SPARE_REG1_SHFT                                                                              0x0

#define HWIO_TCSR_APSS_SPARE_REG2_ADDR                                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x0002501c)
#define HWIO_TCSR_APSS_SPARE_REG2_RMSK                                                                                  0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG2_IN          \
        in_dword(HWIO_TCSR_APSS_SPARE_REG2_ADDR)
#define HWIO_TCSR_APSS_SPARE_REG2_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG2_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG2_OUT(v)      \
        out_dword(HWIO_TCSR_APSS_SPARE_REG2_ADDR,v)
#define HWIO_TCSR_APSS_SPARE_REG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_APSS_SPARE_REG2_ADDR,m,v,HWIO_TCSR_APSS_SPARE_REG2_IN)
#define HWIO_TCSR_APSS_SPARE_REG2_SPARE_REG2_BMSK                                                                       0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG2_SPARE_REG2_SHFT                                                                              0x0

#define HWIO_TCSR_APSS_SPARE_REG3_ADDR                                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00025020)
#define HWIO_TCSR_APSS_SPARE_REG3_RMSK                                                                                  0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG3_IN          \
        in_dword(HWIO_TCSR_APSS_SPARE_REG3_ADDR)
#define HWIO_TCSR_APSS_SPARE_REG3_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG3_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG3_OUT(v)      \
        out_dword(HWIO_TCSR_APSS_SPARE_REG3_ADDR,v)
#define HWIO_TCSR_APSS_SPARE_REG3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_APSS_SPARE_REG3_ADDR,m,v,HWIO_TCSR_APSS_SPARE_REG3_IN)
#define HWIO_TCSR_APSS_SPARE_REG3_SPARE_REG3_BMSK                                                                       0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG3_SPARE_REG3_SHFT                                                                              0x0

#define HWIO_TCSR_APSS_SPARE_REG_RD_0_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00025024)
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_RMSK                                                                              0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_IN          \
        in_dword(HWIO_TCSR_APSS_SPARE_REG_RD_0_ADDR)
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG_RD_0_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_SPARE_REG_RD_0_BMSK                                                               0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_SPARE_REG_RD_0_SHFT                                                                      0x0

#define HWIO_TCSR_APSS_SPARE_REG_RD_1_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00025028)
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_RMSK                                                                              0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_IN          \
        in_dword(HWIO_TCSR_APSS_SPARE_REG_RD_1_ADDR)
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG_RD_1_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_SPARE_REG_RD_1_BMSK                                                               0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_SPARE_REG_RD_1_SHFT                                                                      0x0

#define HWIO_TCSR_APSS_SPARE_REG_RD_2_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002502c)
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_RMSK                                                                              0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_IN          \
        in_dword(HWIO_TCSR_APSS_SPARE_REG_RD_2_ADDR)
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG_RD_2_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_SPARE_REG_RD_2_BMSK                                                               0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_SPARE_REG_RD_2_SHFT                                                                      0x0

#define HWIO_TCSR_APSS_SPARE_REG_RD_3_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00025030)
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_RMSK                                                                              0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_IN          \
        in_dword(HWIO_TCSR_APSS_SPARE_REG_RD_3_ADDR)
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG_RD_3_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_SPARE_REG_RD_3_BMSK                                                               0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_SPARE_REG_RD_3_SHFT                                                                      0x0

#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x00013100)
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_RMSK                                                                          0xffffffff
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_IN          \
        in_dword(HWIO_TCSR_BOOT_IMEM_START_ADDRESS_ADDR)
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_INM(m)      \
        in_dword_masked(HWIO_TCSR_BOOT_IMEM_START_ADDRESS_ADDR, m)
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_BOOT_IMEM_START_ADDRESS_BMSK                                                  0xffffffff
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_BOOT_IMEM_START_ADDRESS_SHFT                                                         0x0

#define HWIO_TCSR_BOOT_IMEM_SIZE_ADDR                                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x00013200)
#define HWIO_TCSR_BOOT_IMEM_SIZE_RMSK                                                                                   0xffffffff
#define HWIO_TCSR_BOOT_IMEM_SIZE_IN          \
        in_dword(HWIO_TCSR_BOOT_IMEM_SIZE_ADDR)
#define HWIO_TCSR_BOOT_IMEM_SIZE_INM(m)      \
        in_dword_masked(HWIO_TCSR_BOOT_IMEM_SIZE_ADDR, m)
#define HWIO_TCSR_BOOT_IMEM_SIZE_BOOT_IMEM_SIZE_BMSK                                                                    0xffffffff
#define HWIO_TCSR_BOOT_IMEM_SIZE_BOOT_IMEM_SIZE_SHFT                                                                           0x0

#define HWIO_TCSR_BOOT_IMEM_DISABLE_ADDR                                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x00013300)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_RMSK                                                                                       0x1
#define HWIO_TCSR_BOOT_IMEM_DISABLE_IN          \
        in_dword(HWIO_TCSR_BOOT_IMEM_DISABLE_ADDR)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_BOOT_IMEM_DISABLE_ADDR, m)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_OUT(v)      \
        out_dword(HWIO_TCSR_BOOT_IMEM_DISABLE_ADDR,v)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_BOOT_IMEM_DISABLE_ADDR,m,v,HWIO_TCSR_BOOT_IMEM_DISABLE_IN)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_BOOT_IMEM_DISABLE_BMSK                                                                     0x1
#define HWIO_TCSR_BOOT_IMEM_DISABLE_BOOT_IMEM_DISABLE_SHFT                                                                     0x0

#define HWIO_TCSR_BIAS_REF_LS_EN_ADDR                                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x00026000)
#define HWIO_TCSR_BIAS_REF_LS_EN_RMSK                                                                                         0x3f
#define HWIO_TCSR_BIAS_REF_LS_EN_IN          \
        in_dword(HWIO_TCSR_BIAS_REF_LS_EN_ADDR)
#define HWIO_TCSR_BIAS_REF_LS_EN_INM(m)      \
        in_dword_masked(HWIO_TCSR_BIAS_REF_LS_EN_ADDR, m)
#define HWIO_TCSR_BIAS_REF_LS_EN_OUT(v)      \
        out_dword(HWIO_TCSR_BIAS_REF_LS_EN_ADDR,v)
#define HWIO_TCSR_BIAS_REF_LS_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_BIAS_REF_LS_EN_ADDR,m,v,HWIO_TCSR_BIAS_REF_LS_EN_IN)
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_3_AUXBUF_EN_BMSK                                                                 0x20
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_3_AUXBUF_EN_SHFT                                                                  0x5
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_3_ATEST_EN_BMSK                                                                  0x10
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_3_ATEST_EN_SHFT                                                                   0x4
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_2_AUXBUF_EN_BMSK                                                                  0x8
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_2_AUXBUF_EN_SHFT                                                                  0x3
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_2_ATEST_EN_BMSK                                                                   0x4
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_2_ATEST_EN_SHFT                                                                   0x2
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_1_AUXBUF_EN_BMSK                                                                  0x2
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_1_AUXBUF_EN_SHFT                                                                  0x1
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_1_ATEST_EN_BMSK                                                                   0x1
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_1_ATEST_EN_SHFT                                                                   0x0

#define HWIO_TCSR_REFGEN_QLINK_ENABLE_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002c000)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_RMSK                                                                                     0x1
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_IN          \
        in_dword(HWIO_TCSR_REFGEN_QLINK_ENABLE_ADDR)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_REFGEN_QLINK_ENABLE_ADDR, m)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_REFGEN_QLINK_ENABLE_ADDR,v)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_REFGEN_QLINK_ENABLE_ADDR,m,v,HWIO_TCSR_REFGEN_QLINK_ENABLE_IN)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_REFGEN_QLINK_ENABLE_BMSK                                                                 0x1
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_REFGEN_QLINK_ENABLE_SHFT                                                                 0x0

/*----------------------------------------------------------------------------
 * MODULE: PSHOLD
 *--------------------------------------------------------------------------*/

#define PSHOLD_REG_BASE                       (AOSS_BASE      + 0x01264000)
#define PSHOLD_REG_BASE_SIZE                  0x1000
#define PSHOLD_REG_BASE_USED                  0x0

#define HWIO_MPM_PS_HOLD_ADDR                 (PSHOLD_REG_BASE      + 0x00000000)
#define HWIO_MPM_PS_HOLD_RMSK                        0x1
#define HWIO_MPM_PS_HOLD_IN          \
        in_dword(HWIO_MPM_PS_HOLD_ADDR)
#define HWIO_MPM_PS_HOLD_INM(m)      \
        in_dword_masked(HWIO_MPM_PS_HOLD_ADDR, m)
#define HWIO_MPM_PS_HOLD_OUT(v)      \
        out_dword(HWIO_MPM_PS_HOLD_ADDR,v)
#define HWIO_MPM_PS_HOLD_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MPM_PS_HOLD_ADDR,m,v,HWIO_MPM_PS_HOLD_IN)
#define HWIO_MPM_PS_HOLD_PSHOLD_BMSK                 0x1
#define HWIO_MPM_PS_HOLD_PSHOLD_SHFT                 0x0

/*----------------------------------------------------------------------------
 * MODULE: SLP_CNTR
 *--------------------------------------------------------------------------*/

#define SLP_CNTR_REG_BASE                                    (AOSS_BASE      + 0x01221000)
#define SLP_CNTR_REG_BASE_SIZE                               0x1000
#define SLP_CNTR_REG_BASE_USED                               0x0

#define HWIO_MPM_SLEEP_TIMETICK_COUNT_VAL_ADDR               (SLP_CNTR_REG_BASE      + 0x00000000)
#define HWIO_MPM_SLEEP_TIMETICK_COUNT_VAL_RMSK               0xffffffff
#define HWIO_MPM_SLEEP_TIMETICK_COUNT_VAL_IN          \
        in_dword(HWIO_MPM_SLEEP_TIMETICK_COUNT_VAL_ADDR)
#define HWIO_MPM_SLEEP_TIMETICK_COUNT_VAL_INM(m)      \
        in_dword_masked(HWIO_MPM_SLEEP_TIMETICK_COUNT_VAL_ADDR, m)
#define HWIO_MPM_SLEEP_TIMETICK_COUNT_VAL_DATA_BMSK          0xffffffff
#define HWIO_MPM_SLEEP_TIMETICK_COUNT_VAL_DATA_SHFT                 0x0

/*----------------------------------------------------------------------------
 * MODULE: AOSS_CC_AOSS_CC_REG
 *--------------------------------------------------------------------------*/

#define AOSS_CC_AOSS_CC_REG_REG_BASE                                                      (AOSS_BASE      + 0x012a0000)
#define AOSS_CC_AOSS_CC_REG_REG_BASE_SIZE                                                 0x60000
#define AOSS_CC_AOSS_CC_REG_REG_BASE_USED                                                 0x51000

#define HWIO_AOSS_CC_PLL0_MODE_ADDR                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000000)
#define HWIO_AOSS_CC_PLL0_MODE_RMSK                                                       0xffffffff
#define HWIO_AOSS_CC_PLL0_MODE_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_MODE_ADDR)
#define HWIO_AOSS_CC_PLL0_MODE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_MODE_ADDR, m)
#define HWIO_AOSS_CC_PLL0_MODE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_MODE_ADDR,v)
#define HWIO_AOSS_CC_PLL0_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_MODE_ADDR,m,v,HWIO_AOSS_CC_PLL0_MODE_IN)
#define HWIO_AOSS_CC_PLL0_MODE_PLL_LOCK_DET_BMSK                                          0x80000000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_LOCK_DET_SHFT                                                0x1f
#define HWIO_AOSS_CC_PLL0_MODE_PLL_ACTIVE_FLAG_BMSK                                       0x40000000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_ACTIVE_FLAG_SHFT                                             0x1e
#define HWIO_AOSS_CC_PLL0_MODE_PLL_ACK_LATCH_BMSK                                         0x20000000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_ACK_LATCH_SHFT                                               0x1d
#define HWIO_AOSS_CC_PLL0_MODE_PLL_LOCK_DET_FINE_BMSK                                     0x10000000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_LOCK_DET_FINE_SHFT                                           0x1c
#define HWIO_AOSS_CC_PLL0_MODE_PCAL_DONE_BMSK                                              0x8000000
#define HWIO_AOSS_CC_PLL0_MODE_PCAL_DONE_SHFT                                                   0x1b
#define HWIO_AOSS_CC_PLL0_MODE_RESERVE_BITS26_25_BMSK                                      0x6000000
#define HWIO_AOSS_CC_PLL0_MODE_RESERVE_BITS26_25_SHFT                                           0x19
#define HWIO_AOSS_CC_PLL0_MODE_FSM_LEGACY_MODE_BMSK                                        0x1000000
#define HWIO_AOSS_CC_PLL0_MODE_FSM_LEGACY_MODE_SHFT                                             0x18
#define HWIO_AOSS_CC_PLL0_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_BMSK                              0x800000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_HW_UPDATE_LOGIC_BYPASS_SHFT                                  0x17
#define HWIO_AOSS_CC_PLL0_MODE_PLL_UPDATE_BMSK                                              0x400000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_UPDATE_SHFT                                                  0x16
#define HWIO_AOSS_CC_PLL0_MODE_PLL_VOTE_FSM_RESET_BMSK                                      0x200000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_VOTE_FSM_RESET_SHFT                                          0x15
#define HWIO_AOSS_CC_PLL0_MODE_PLL_VOTE_FSM_ENA_BMSK                                        0x100000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_VOTE_FSM_ENA_SHFT                                            0x14
#define HWIO_AOSS_CC_PLL0_MODE_PLL_BIAS_COUNT_BMSK                                           0xfc000
#define HWIO_AOSS_CC_PLL0_MODE_PLL_BIAS_COUNT_SHFT                                               0xe
#define HWIO_AOSS_CC_PLL0_MODE_PLL_LOCK_COUNT_BMSK                                            0x3f00
#define HWIO_AOSS_CC_PLL0_MODE_PLL_LOCK_COUNT_SHFT                                               0x8
#define HWIO_AOSS_CC_PLL0_MODE_RESERVE_BIT7_BMSK                                                0x80
#define HWIO_AOSS_CC_PLL0_MODE_RESERVE_BIT7_SHFT                                                 0x7
#define HWIO_AOSS_CC_PLL0_MODE_OUT_TEST_HW_CTL_BMSK                                             0x40
#define HWIO_AOSS_CC_PLL0_MODE_OUT_TEST_HW_CTL_SHFT                                              0x6
#define HWIO_AOSS_CC_PLL0_MODE_OUT_ODD_HW_CTL_BMSK                                              0x20
#define HWIO_AOSS_CC_PLL0_MODE_OUT_ODD_HW_CTL_SHFT                                               0x5
#define HWIO_AOSS_CC_PLL0_MODE_OUT_EVEN_HW_CTL_BMSK                                             0x10
#define HWIO_AOSS_CC_PLL0_MODE_OUT_EVEN_HW_CTL_SHFT                                              0x4
#define HWIO_AOSS_CC_PLL0_MODE_OUT_MAIN_HW_CTL_BMSK                                              0x8
#define HWIO_AOSS_CC_PLL0_MODE_OUT_MAIN_HW_CTL_SHFT                                              0x3
#define HWIO_AOSS_CC_PLL0_MODE_PLL_RESET_N_BMSK                                                  0x4
#define HWIO_AOSS_CC_PLL0_MODE_PLL_RESET_N_SHFT                                                  0x2
#define HWIO_AOSS_CC_PLL0_MODE_RESERVE_BIT1_BMSK                                                 0x2
#define HWIO_AOSS_CC_PLL0_MODE_RESERVE_BIT1_SHFT                                                 0x1
#define HWIO_AOSS_CC_PLL0_MODE_PLL_OUTCTRL_BMSK                                                  0x1
#define HWIO_AOSS_CC_PLL0_MODE_PLL_OUTCTRL_SHFT                                                  0x0

#define HWIO_AOSS_CC_PLL0_L_VAL_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000004)
#define HWIO_AOSS_CC_PLL0_L_VAL_RMSK                                                          0xffff
#define HWIO_AOSS_CC_PLL0_L_VAL_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_L_VAL_ADDR)
#define HWIO_AOSS_CC_PLL0_L_VAL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_L_VAL_ADDR, m)
#define HWIO_AOSS_CC_PLL0_L_VAL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_L_VAL_ADDR,v)
#define HWIO_AOSS_CC_PLL0_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_L_VAL_ADDR,m,v,HWIO_AOSS_CC_PLL0_L_VAL_IN)
#define HWIO_AOSS_CC_PLL0_L_VAL_PLL_L_BMSK                                                    0xffff
#define HWIO_AOSS_CC_PLL0_L_VAL_PLL_L_SHFT                                                       0x0

#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000008)
#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_RMSK                                                      0xffff
#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_CAL_L_VAL_ADDR)
#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_CAL_L_VAL_ADDR, m)
#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_CAL_L_VAL_ADDR,v)
#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_CAL_L_VAL_ADDR,m,v,HWIO_AOSS_CC_PLL0_CAL_L_VAL_IN)
#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_PLL_CAL_L_BMSK                                            0xffff
#define HWIO_AOSS_CC_PLL0_CAL_L_VAL_PLL_CAL_L_SHFT                                               0x0

#define HWIO_AOSS_CC_PLL0_USER_CTL_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000000c)
#define HWIO_AOSS_CC_PLL0_USER_CTL_RMSK                                                   0xffffffff
#define HWIO_AOSS_CC_PLL0_USER_CTL_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_USER_CTL_ADDR)
#define HWIO_AOSS_CC_PLL0_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_USER_CTL_ADDR, m)
#define HWIO_AOSS_CC_PLL0_USER_CTL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_USER_CTL_ADDR,v)
#define HWIO_AOSS_CC_PLL0_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_USER_CTL_ADDR,m,v,HWIO_AOSS_CC_PLL0_USER_CTL_IN)
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT31_BMSK                                     0x80000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT31_SHFT                                           0x1f
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT30_BMSK                                     0x40000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT30_SHFT                                           0x1e
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT29_BMSK                                     0x20000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT29_SHFT                                           0x1d
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT28_BMSK                                     0x10000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT28_SHFT                                           0x1c
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT27_BMSK                                      0x8000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT27_SHFT                                           0x1b
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT26_BMSK                                      0x4000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT26_SHFT                                           0x1a
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT25_BMSK                                      0x2000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT25_SHFT                                           0x19
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT24_BMSK                                      0x1000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT24_SHFT                                           0x18
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT23_BMSK                                       0x800000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT23_SHFT                                           0x17
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT22_BMSK                                       0x400000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT22_SHFT                                           0x16
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT21_BMSK                                       0x200000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT21_SHFT                                           0x15
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT20_BMSK                                       0x100000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT20_SHFT                                           0x14
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT19_BMSK                                        0x80000
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT19_SHFT                                           0x13
#define HWIO_AOSS_CC_PLL0_USER_CTL_PRE_DIV_RATIO_BMSK                                        0x70000
#define HWIO_AOSS_CC_PLL0_USER_CTL_PRE_DIV_RATIO_SHFT                                           0x10
#define HWIO_AOSS_CC_PLL0_USER_CTL_POST_DIV_RATIO_ODD_BMSK                                    0xf000
#define HWIO_AOSS_CC_PLL0_USER_CTL_POST_DIV_RATIO_ODD_SHFT                                       0xc
#define HWIO_AOSS_CC_PLL0_USER_CTL_POST_DIV_RATIO_EVEN_BMSK                                    0xf00
#define HWIO_AOSS_CC_PLL0_USER_CTL_POST_DIV_RATIO_EVEN_SHFT                                      0x8
#define HWIO_AOSS_CC_PLL0_USER_CTL_OUT_CLK_POLARITY_BMSK                                        0x80
#define HWIO_AOSS_CC_PLL0_USER_CTL_OUT_CLK_POLARITY_SHFT                                         0x7
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT6_BMSK                                            0x40
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT6_SHFT                                             0x6
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT5_BMSK                                            0x20
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT5_SHFT                                             0x5
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_TEST_BMSK                                             0x10
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_TEST_SHFT                                              0x4
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT3_BMSK                                             0x8
#define HWIO_AOSS_CC_PLL0_USER_CTL_RESERVE_BIT3_SHFT                                             0x3
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_ODD_BMSK                                               0x4
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_ODD_SHFT                                               0x2
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_EVEN_BMSK                                              0x2
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_EVEN_SHFT                                              0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_MAIN_BMSK                                              0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_PLLOUT_MAIN_SHFT                                              0x0

#define HWIO_AOSS_CC_PLL0_USER_CTL_U_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000010)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RMSK                                                 0xffffffff
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_USER_CTL_U_ADDR)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_USER_CTL_U_ADDR, m)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_USER_CTL_U_ADDR,v)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_USER_CTL_U_ADDR,m,v,HWIO_AOSS_CC_PLL0_USER_CTL_U_IN)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT63_BMSK                                   0x80000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT63_SHFT                                         0x1f
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT62_BMSK                                   0x40000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT62_SHFT                                         0x1e
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT61_BMSK                                   0x20000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT61_SHFT                                         0x1d
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT60_BMSK                                   0x10000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT60_SHFT                                         0x1c
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT59_BMSK                                    0x8000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT59_SHFT                                         0x1b
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT58_BMSK                                    0x4000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT58_SHFT                                         0x1a
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT57_BMSK                                    0x2000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT57_SHFT                                         0x19
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT56_BMSK                                    0x1000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT56_SHFT                                         0x18
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT55_BMSK                                     0x800000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT55_SHFT                                         0x17
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT54_BMSK                                     0x400000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT54_SHFT                                         0x16
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT53_BMSK                                     0x200000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT53_SHFT                                         0x15
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT52_BMSK                                     0x100000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT52_SHFT                                         0x14
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT51_BMSK                                      0x80000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT51_SHFT                                         0x13
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_LOCK_DETECTOR_SELECTION_BMSK                            0x40000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_LOCK_DETECTOR_SELECTION_SHFT                               0x12
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_TYPE_2_MODE_SELECTION_BMSK                              0x20000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_TYPE_2_MODE_SELECTION_SHFT                                 0x11
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_BANG_BANG_MODE_SELECTION_BMSK                           0x10000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_BANG_BANG_MODE_SELECTION_SHFT                              0x10
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_FRAC_FORMAT_SEL_BMSK                                     0x8000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_FRAC_FORMAT_SEL_SHFT                                        0xf
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT46_BMSK                                       0x4000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_RESERVE_BIT46_SHFT                                          0xe
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_REF_CLK_AT_OUT_BMSK                                      0x2000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_REF_CLK_AT_OUT_SHFT                                         0xd
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_SCALE_FREQ_ON_RESTART_BMSK                               0x1800
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_SCALE_FREQ_ON_RESTART_SHFT                                  0xb
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_LATCH_INTERFACE_BYPASS_BMSK                               0x400
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_LATCH_INTERFACE_BYPASS_SHFT                                 0xa
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_STATUS_REGISTER_BMSK                                      0x3e0
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_STATUS_REGISTER_SHFT                                        0x5
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_WRITE_STATE_EN_BMSK                                        0x10
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_WRITE_STATE_EN_SHFT                                         0x4
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_CALIB_CTRL_BMSK                                             0xe
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_CALIB_CTRL_SHFT                                             0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_BMSK                                 0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_U_USE_ONLY_FINE_LOCK_DET_SHFT                                 0x0

#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000014)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RMSK                                                0xffffffff
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_USER_CTL_U1_ADDR)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_USER_CTL_U1_ADDR, m)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_USER_CTL_U1_ADDR,v)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_USER_CTL_U1_ADDR,m,v,HWIO_AOSS_CC_PLL0_USER_CTL_U1_IN)
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT95_BMSK                                  0x80000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT95_SHFT                                        0x1f
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT94_BMSK                                  0x40000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT94_SHFT                                        0x1e
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT93_BMSK                                  0x20000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT93_SHFT                                        0x1d
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT92_BMSK                                  0x10000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT92_SHFT                                        0x1c
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT91_BMSK                                   0x8000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT91_SHFT                                        0x1b
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT90_BMSK                                   0x4000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT90_SHFT                                        0x1a
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT89_BMSK                                   0x2000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT89_SHFT                                        0x19
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT88_BMSK                                   0x1000000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT88_SHFT                                        0x18
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT87_BMSK                                    0x800000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT87_SHFT                                        0x17
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT86_BMSK                                    0x400000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT86_SHFT                                        0x16
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT85_BMSK                                    0x200000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT85_SHFT                                        0x15
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT84_BMSK                                    0x100000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT84_SHFT                                        0x14
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT83_BMSK                                     0x80000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT83_SHFT                                        0x13
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT82_BMSK                                     0x40000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT82_SHFT                                        0x12
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT81_BMSK                                     0x20000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT81_SHFT                                        0x11
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT80_BMSK                                     0x10000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT80_SHFT                                        0x10
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT79_BMSK                                      0x8000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT79_SHFT                                         0xf
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT78_BMSK                                      0x4000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT78_SHFT                                         0xe
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT77_BMSK                                      0x2000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT77_SHFT                                         0xd
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT76_BMSK                                      0x1000
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT76_SHFT                                         0xc
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT75_BMSK                                       0x800
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT75_SHFT                                         0xb
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT74_BMSK                                       0x400
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT74_SHFT                                         0xa
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT73_BMSK                                       0x200
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT73_SHFT                                         0x9
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT72_BMSK                                       0x100
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT72_SHFT                                         0x8
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT71_BMSK                                        0x80
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT71_SHFT                                         0x7
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT70_BMSK                                        0x40
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT70_SHFT                                         0x6
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT69_BMSK                                        0x20
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT69_SHFT                                         0x5
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT68_BMSK                                        0x10
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT68_SHFT                                         0x4
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT67_BMSK                                         0x8
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT67_SHFT                                         0x3
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT66_BMSK                                         0x4
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT66_SHFT                                         0x2
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT65_BMSK                                         0x2
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT65_SHFT                                         0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT64_BMSK                                         0x1
#define HWIO_AOSS_CC_PLL0_USER_CTL_U1_RESERVE_BIT64_SHFT                                         0x0

#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000018)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_RMSK                                                 0xffffffff
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_CONFIG_CTL_ADDR)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_CONFIG_CTL_ADDR, m)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_CONFIG_CTL_ADDR,v)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_CONFIG_CTL_ADDR,m,v,HWIO_AOSS_CC_PLL0_CONFIG_CTL_IN)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FINE_LDC_THRESHOLD_BMSK                              0xfc000000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FINE_LDC_THRESHOLD_SHFT                                    0x1a
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_COARSE_LDC_THRESHOLD_BMSK                             0x3c00000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_COARSE_LDC_THRESHOLD_SHFT                                  0x16
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_BMSK                     0x3c0000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_COARSE_LOCK_DET_NEG_THRESHOLD_SHFT                         0x12
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_BMSK                      0x3c000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_COARSE_LOCK_DET_POS_THRESHOLD_SHFT                          0xe
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_BMSK                             0x3800
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FINE_LOCK_DET_THRESHOLD_SHFT                                0xb
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_BMSK                            0x700
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FINE_LOCK_DET_SAMPLE_SIZE_SHFT                              0x8
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_BMSK                                  0xf0
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FWD_GAIN_SLEWING_KFN_SHFT                                   0x4
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FWD_GAIN_KFN_BMSK                                           0xf
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_FWD_GAIN_KFN_SHFT                                           0x0

#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_ADDR                                               (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000001c)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_RMSK                                               0xffffffff
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_ADDR)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_ADDR, m)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_ADDR,v)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_ADDR,m,v,HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_IN)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_BIST_CFG_BMSK                                      0xffff0000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_BIST_CFG_SHFT                                            0x10
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_BMSK                           0xc000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_CASCODE_FREEZE_LOCK_DET_SHFT                              0xe
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_OSC_SETTLING_TIME_BMSK                                 0x3000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_OSC_SETTLING_TIME_SHFT                                    0xc
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_BMSK                                0xc00
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_NUM_STEPS_FAST_LOCK_SHFT                                  0xa
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_CASC_CURRENT_CTL_B_BMSK                                 0x380
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_CASC_CURRENT_CTL_B_SHFT                                   0x7
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_BMSK                         0x40
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_SHFT                          0x6
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_BMSK                                0x30
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_SHFT                                 0x4
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_LDET_THRESH_SCALE_BMSK                                    0x8
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_LDET_THRESH_SCALE_SHFT                                    0x3
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_DCO_STARTUP_CONFIG_BMSK                                   0x6
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_DCO_STARTUP_CONFIG_SHFT                                   0x1
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_BMSK                              0x1
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U_DIV_LOCK_DET_THRESHOLDS_SHFT                              0x0

#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_ADDR                                              (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000020)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_RMSK                                              0xffffffff
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_ADDR)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_ADDR, m)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_ADDR,v)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_ADDR,m,v,HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_IN)
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_THRESHOLD_BMSK                             0xc0000000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_THRESHOLD_SHFT                                   0x1e
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_PCODE_OFFSET_BMSK                                 0x38000000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_PCODE_OFFSET_SHFT                                       0x1b
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_COUNTER_BLANK_BMSK                                 0x4000000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_COUNTER_BLANK_SHFT                                      0x1a
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_RESYNC_EDGE_BMSK                                0x2000000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_RESYNC_EDGE_SHFT                                     0x19
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_RESYNC_SEL_BMSK                                 0x1000000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_RESYNC_SEL_SHFT                                      0x18
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_BMSK                            0xc00000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_LOCK_NUM_SAMPLES_SHFT                                0x16
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_LOCK_THRESH_BMSK                                 0x380000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_LOCK_THRESH_SHFT                                     0x13
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_RESERVE_BIT82_BMSK                                   0x40000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_RESERVE_BIT82_SHFT                                      0x12
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_BMSK                              0x30000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_NUM_SAMPLES_SHFT                                 0x10
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_BMSK                                0xc000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_CORR_INDEX_SHFT                                   0xe
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_EN_BMSK                                        0x2000
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BB_CAL_EN_SHFT                                           0xd
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_BMSK                          0x1800
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_DELAY_AFTER_FLL_LOCKDET_SHFT                             0xb
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BBMODE_INT_GAIN_BMSK                                   0x780
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BBMODE_INT_GAIN_SHFT                                     0x7
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BBMODE_PROP_GAIN_BMSK                                   0x78
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_BBMODE_PROP_GAIN_SHFT                                    0x3
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_TDC_SELECTION_BMSK                                       0x4
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_TDC_SELECTION_SHFT                                       0x2
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_RESERVE_BIT65_BMSK                                       0x2
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_RESERVE_BIT65_SHFT                                       0x1
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_FORCE_DSM_ON_BMSK                                        0x1
#define HWIO_AOSS_CC_PLL0_CONFIG_CTL_U1_FORCE_DSM_ON_SHFT                                        0x0

#define HWIO_AOSS_CC_PLL0_TEST_CTL_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000024)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_RMSK                                                   0xffffffff
#define HWIO_AOSS_CC_PLL0_TEST_CTL_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_TEST_CTL_ADDR)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_TEST_CTL_ADDR, m)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_TEST_CTL_ADDR,v)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_TEST_CTL_ADDR,m,v,HWIO_AOSS_CC_PLL0_TEST_CTL_IN)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_BMSK                           0xc0000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ADD_REF_CYC_CALIB_STEPS_SHFT                                 0x1e
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_FIRST_ORDER_DSM_BMSK                            0x20000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_FIRST_ORDER_DSM_SHFT                                  0x1d
#define HWIO_AOSS_CC_PLL0_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_BMSK                       0x18000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_GLITCH_DETECTOR_COUNT_LIMIT_SHFT                             0x1b
#define HWIO_AOSS_CC_PLL0_TEST_CTL_GLITCH_PREVENTION_DIS_BMSK                              0x4000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_GLITCH_PREVENTION_DIS_SHFT                                   0x1a
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ATEST_ISCALE_BMSK                                       0x3000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ATEST_ISCALE_SHFT                                            0x18
#define HWIO_AOSS_CC_PLL0_TEST_CTL_PLL_TEST_OUT_SEL_BMSK                                    0xf00000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_PLL_TEST_OUT_SEL_SHFT                                        0x14
#define HWIO_AOSS_CC_PLL0_TEST_CTL_RESERVE_BIT19_BMSK                                        0x80000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_RESERVE_BIT19_SHFT                                           0x13
#define HWIO_AOSS_CC_PLL0_TEST_CTL_DIV2_NMO_EN_BMSK                                          0x40000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_DIV2_NMO_EN_SHFT                                             0x12
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NMO_OSC_SEL_BMSK                                          0x30000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NMO_OSC_SEL_SHFT                                             0x10
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NOISE_MAG_BMSK                                             0xe000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NOISE_MAG_SHFT                                                0xd
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NOISE_GEN_EN_BMSK                                          0x1000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_NOISE_GEN_EN_SHFT                                             0xc
#define HWIO_AOSS_CC_PLL0_TEST_CTL_DISABLE_DCAPS_BMSK                                          0x800
#define HWIO_AOSS_CC_PLL0_TEST_CTL_DISABLE_DCAPS_SHFT                                            0xb
#define HWIO_AOSS_CC_PLL0_TEST_CTL_RESERVE_BIT10_BMSK                                          0x400
#define HWIO_AOSS_CC_PLL0_TEST_CTL_RESERVE_BIT10_SHFT                                            0xa
#define HWIO_AOSS_CC_PLL0_TEST_CTL_RESERVE_BIT9_BMSK                                           0x200
#define HWIO_AOSS_CC_PLL0_TEST_CTL_RESERVE_BIT9_SHFT                                             0x9
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_BMSK                                0x100
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_MODE_FOR_BIAS_EN_SHFT                                  0x8
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VDD_TEST_BMSK                                             0x80
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VDD_TEST_SHFT                                              0x7
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VREG_TEST_BMSK                                            0x40
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VREG_TEST_SHFT                                             0x6
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VREF_TEST_BMSK                                            0x20
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VREF_TEST_SHFT                                             0x5
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VDCO_TEST_BMSK                                            0x10
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_VDCO_TEST_SHFT                                             0x4
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_ATEST_BUFFER_BMSK                                      0x8
#define HWIO_AOSS_CC_PLL0_TEST_CTL_BYPASS_ATEST_BUFFER_SHFT                                      0x3
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_IVCO_TEST_BMSK                                             0x4
#define HWIO_AOSS_CC_PLL0_TEST_CTL_EN_IVCO_TEST_SHFT                                             0x2
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ATEST1_EN_BMSK                                                0x2
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ATEST1_EN_SHFT                                                0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ATEST0_EN_BMSK                                                0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_ATEST0_EN_SHFT                                                0x0

#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000028)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_RMSK                                                 0xffffffff
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_TEST_CTL_U_ADDR)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_TEST_CTL_U_ADDR, m)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_TEST_CTL_U_ADDR,v)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_TEST_CTL_U_ADDR,m,v,HWIO_AOSS_CC_PLL0_TEST_CTL_U_IN)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_CASC_DAC_FCW_LSBS_BMSK                               0xe0000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_CASC_DAC_FCW_LSBS_SHFT                                     0x1d
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_CASC_DAC_BMSK                               0x10000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_CASC_DAC_SHFT                                     0x1c
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_COMP_COARSE_FCW_BMSK                                  0xe000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_COMP_COARSE_FCW_SHFT                                       0x19
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_BMSK                         0x1800000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_COMP_COARSE_FCW_SHFT                              0x17
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_FINE_FCW_BMSK                                          0x7e0000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_FINE_FCW_SHFT                                              0x11
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_FINE_FCW_BMSK                                  0x10000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_FINE_FCW_SHFT                                     0x10
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_REG_COARSE_FCW_BMSK                                      0xfe00
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_REG_COARSE_FCW_SHFT                                         0x9
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_BMSK                              0x100
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_REG_COARSE_FCW_SHFT                                0x8
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_PROCESS_CALIB_WORD_BMSK                                    0xe0
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_PROCESS_CALIB_WORD_SHFT                                     0x5
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_CALIB_WORD_BMSK                                   0x10
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_OVERRIDE_CALIB_WORD_SHFT                                    0x4
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_BMSK                                 0x8
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_DISABLE_CASC_DAC_LATCH_SHFT                                 0x3
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_DISABLE_LFSR_BMSK                                           0x4
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_DISABLE_LFSR_SHFT                                           0x2
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_SKIP_FINE_TUNE_BMSK                                         0x2
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_SKIP_FINE_TUNE_SHFT                                         0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_SKIP_FAST_LOCK_BMSK                                         0x1
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U_SKIP_FAST_LOCK_SHFT                                         0x0

#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000002c)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RMSK                                                0xffffffff
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_TEST_CTL_U1_ADDR)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_TEST_CTL_U1_ADDR, m)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_TEST_CTL_U1_ADDR,v)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_TEST_CTL_U1_ADDR,m,v,HWIO_AOSS_CC_PLL0_TEST_CTL_U1_IN)
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT95_BMSK                                  0x80000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT95_SHFT                                        0x1f
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT94_BMSK                                  0x40000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT94_SHFT                                        0x1e
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_FLL_COUNT_DISABLE_BMSK                              0x20000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_FLL_COUNT_DISABLE_SHFT                                    0x1d
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_FLL_COUNT_IN_DIV2_BMSK                              0x10000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_FLL_COUNT_IN_DIV2_SHFT                                    0x1c
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT91_BMSK                                   0x8000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT91_SHFT                                        0x1b
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT90_BMSK                                   0x4000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT90_SHFT                                        0x1a
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT89_BMSK                                   0x2000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT89_SHFT                                        0x19
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT88_BMSK                                   0x1000000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT88_SHFT                                        0x18
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT87_BMSK                                    0x800000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT87_SHFT                                        0x17
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_SILENCE_REF_OUTBUF_BMSK                               0x400000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_SILENCE_REF_OUTBUF_SHFT                                   0x16
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT85_BMSK                                    0x200000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT85_SHFT                                        0x15
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT84_BMSK                                    0x100000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT84_SHFT                                        0x14
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT83_BMSK                                     0x80000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT83_SHFT                                        0x13
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_BMSK                             0x40000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_OSCBUF_DYN_SW_SHFT                                0x12
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_REF_CLK_SEL_BMSK                                       0x20000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_REF_CLK_SEL_SHFT                                          0x11
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_BMSK                         0x10000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DIS_DAC_AMP_STARTUP_LATCH_SHFT                            0x10
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DIS_AMP_STARTUP_BMSK                                    0x8000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DIS_AMP_STARTUP_SHFT                                       0xf
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_CLAMP_BMSK                                      0x4000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_CLAMP_SHFT                                         0xe
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_BMSK                            0x2000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_DISABLE_DAC_AMP_CASCODE_SHFT                               0xd
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT76_BMSK                                      0x1000
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT76_SHFT                                         0xc
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT75_BMSK                                       0x800
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT75_SHFT                                         0xb
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT74_BMSK                                       0x400
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT74_SHFT                                         0xa
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT73_BMSK                                       0x200
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT73_SHFT                                         0x9
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT72_BMSK                                       0x100
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT72_SHFT                                         0x8
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_BMSK                              0x80
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_COARSE_BIN_OVERRIDE_LOC_SHFT                               0x7
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_ENABLE_TRAINING_SEQ_BMSK                                  0x40
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_ENABLE_TRAINING_SEQ_SHFT                                   0x6
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_STATUS_REG_EN_BMSK                                        0x20
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_STATUS_REG_EN_SHFT                                         0x5
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT68_BMSK                                        0x10
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT68_SHFT                                         0x4
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT67_BMSK                                         0x8
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT67_SHFT                                         0x3
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT66_BMSK                                         0x4
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_RESERVE_BIT66_SHFT                                         0x2
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_CASC_DAC_FCW_MSBS_BMSK                                     0x3
#define HWIO_AOSS_CC_PLL0_TEST_CTL_U1_CASC_DAC_FCW_MSBS_SHFT                                     0x0

#define HWIO_AOSS_CC_PLL0_STATUS_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000030)
#define HWIO_AOSS_CC_PLL0_STATUS_RMSK                                                     0xffffffff
#define HWIO_AOSS_CC_PLL0_STATUS_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_STATUS_ADDR)
#define HWIO_AOSS_CC_PLL0_STATUS_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_STATUS_ADDR, m)
#define HWIO_AOSS_CC_PLL0_STATUS_STATUS_31_0_BMSK                                         0xffffffff
#define HWIO_AOSS_CC_PLL0_STATUS_STATUS_31_0_SHFT                                                0x0

#define HWIO_AOSS_CC_PLL0_FREQ_CTL_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000034)
#define HWIO_AOSS_CC_PLL0_FREQ_CTL_RMSK                                                   0xffffffff
#define HWIO_AOSS_CC_PLL0_FREQ_CTL_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_FREQ_CTL_ADDR)
#define HWIO_AOSS_CC_PLL0_FREQ_CTL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_FREQ_CTL_ADDR, m)
#define HWIO_AOSS_CC_PLL0_FREQ_CTL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_FREQ_CTL_ADDR,v)
#define HWIO_AOSS_CC_PLL0_FREQ_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_FREQ_CTL_ADDR,m,v,HWIO_AOSS_CC_PLL0_FREQ_CTL_IN)
#define HWIO_AOSS_CC_PLL0_FREQ_CTL_FREQUENCY_CTL_WORD_BMSK                                0xffffffff
#define HWIO_AOSS_CC_PLL0_FREQ_CTL_FREQUENCY_CTL_WORD_SHFT                                       0x0

#define HWIO_AOSS_CC_PLL0_OPMODE_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000038)
#define HWIO_AOSS_CC_PLL0_OPMODE_RMSK                                                            0x7
#define HWIO_AOSS_CC_PLL0_OPMODE_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_OPMODE_ADDR)
#define HWIO_AOSS_CC_PLL0_OPMODE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_OPMODE_ADDR, m)
#define HWIO_AOSS_CC_PLL0_OPMODE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_OPMODE_ADDR,v)
#define HWIO_AOSS_CC_PLL0_OPMODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_OPMODE_ADDR,m,v,HWIO_AOSS_CC_PLL0_OPMODE_IN)
#define HWIO_AOSS_CC_PLL0_OPMODE_PLL_OPMODE_BMSK                                                 0x7
#define HWIO_AOSS_CC_PLL0_OPMODE_PLL_OPMODE_SHFT                                                 0x0

#define HWIO_AOSS_CC_PLL0_STATE_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000003c)
#define HWIO_AOSS_CC_PLL0_STATE_RMSK                                                             0x7
#define HWIO_AOSS_CC_PLL0_STATE_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_STATE_ADDR)
#define HWIO_AOSS_CC_PLL0_STATE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_STATE_ADDR, m)
#define HWIO_AOSS_CC_PLL0_STATE_PLL_STATE_BMSK                                                   0x7
#define HWIO_AOSS_CC_PLL0_STATE_PLL_STATE_SHFT                                                   0x0

#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000040)
#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_RMSK                                                      0xffff
#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_ALPHA_VAL_ADDR)
#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_ALPHA_VAL_ADDR, m)
#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_ALPHA_VAL_ADDR,v)
#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_ALPHA_VAL_ADDR,m,v,HWIO_AOSS_CC_PLL0_ALPHA_VAL_IN)
#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_PLL_ALPHA_VAL_BMSK                                        0xffff
#define HWIO_AOSS_CC_PLL0_ALPHA_VAL_PLL_ALPHA_VAL_SHFT                                           0x0

#define HWIO_AOSS_CC_PLL0_SPARE_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000044)
#define HWIO_AOSS_CC_PLL0_SPARE_RMSK                                                            0xff
#define HWIO_AOSS_CC_PLL0_SPARE_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_SPARE_ADDR)
#define HWIO_AOSS_CC_PLL0_SPARE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_SPARE_ADDR, m)
#define HWIO_AOSS_CC_PLL0_SPARE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_SPARE_ADDR,v)
#define HWIO_AOSS_CC_PLL0_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_SPARE_ADDR,m,v,HWIO_AOSS_CC_PLL0_SPARE_IN)
#define HWIO_AOSS_CC_PLL0_SPARE_SPARE_OUTPUTS_BMSK                                              0xf0
#define HWIO_AOSS_CC_PLL0_SPARE_SPARE_OUTPUTS_SHFT                                               0x4
#define HWIO_AOSS_CC_PLL0_SPARE_SPARE_INPUTS_BMSK                                                0xf
#define HWIO_AOSS_CC_PLL0_SPARE_SPARE_INPUTS_SHFT                                                0x0

#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_ADDR                                            (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000048)
#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_RMSK                                                  0xff
#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_ADDR)
#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_ADDR, m)
#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_ADDR,v)
#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_ADDR,m,v,HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_IN)
#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_BMSK                                  0xff
#define HWIO_AOSS_CC_PLL0_SSC_DELTA_ALPHA_SSC_DELTA_ALPHA_SHFT                                   0x0

#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_ADDR                                              (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000004c)
#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_RMSK                                                     0xf
#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_ADDR)
#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_ADDR, m)
#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_ADDR,v)
#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_ADDR,m,v,HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_IN)
#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_SSC_NUM_STEPS_BMSK                                       0xf
#define HWIO_AOSS_CC_PLL0_SSC_NUM_STEPS_SSC_NUM_STEPS_SHFT                                       0x0

#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_ADDR                                            (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000050)
#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_RMSK                                                   0xf
#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_ADDR)
#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_ADDR, m)
#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_ADDR,v)
#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_ADDR,m,v,HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_IN)
#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_SSC_UPDATE_RATE_BMSK                                   0xf
#define HWIO_AOSS_CC_PLL0_SSC_UPDATE_RATE_SSC_UPDATE_RATE_SHFT                                   0x0

#define HWIO_AOSS_CC_PLL1_MODE_ADDR                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001000)
#define HWIO_AOSS_CC_PLL1_MODE_RMSK                                                       0xffffffff
#define HWIO_AOSS_CC_PLL1_MODE_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_MODE_ADDR)
#define HWIO_AOSS_CC_PLL1_MODE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_MODE_ADDR, m)
#define HWIO_AOSS_CC_PLL1_MODE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_MODE_ADDR,v)
#define HWIO_AOSS_CC_PLL1_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_MODE_ADDR,m,v,HWIO_AOSS_CC_PLL1_MODE_IN)
#define HWIO_AOSS_CC_PLL1_MODE_PLL_LOCK_DET_BMSK                                          0x80000000
#define HWIO_AOSS_CC_PLL1_MODE_PLL_LOCK_DET_SHFT                                                0x1f
#define HWIO_AOSS_CC_PLL1_MODE_PLL_ACTIVE_FLAG_BMSK                                       0x40000000
#define HWIO_AOSS_CC_PLL1_MODE_PLL_ACTIVE_FLAG_SHFT                                             0x1e
#define HWIO_AOSS_CC_PLL1_MODE_RESERVE_BITS29_22_BMSK                                     0x3fc00000
#define HWIO_AOSS_CC_PLL1_MODE_RESERVE_BITS29_22_SHFT                                           0x16
#define HWIO_AOSS_CC_PLL1_MODE_PLL_VOTE_FSM_RESET_BMSK                                      0x200000
#define HWIO_AOSS_CC_PLL1_MODE_PLL_VOTE_FSM_RESET_SHFT                                          0x15
#define HWIO_AOSS_CC_PLL1_MODE_PLL_VOTE_FSM_ENA_BMSK                                        0x100000
#define HWIO_AOSS_CC_PLL1_MODE_PLL_VOTE_FSM_ENA_SHFT                                            0x14
#define HWIO_AOSS_CC_PLL1_MODE_PLL_BIAS_COUNT_BMSK                                           0xfc000
#define HWIO_AOSS_CC_PLL1_MODE_PLL_BIAS_COUNT_SHFT                                               0xe
#define HWIO_AOSS_CC_PLL1_MODE_PLL_LOCK_COUNT_BMSK                                            0x3f00
#define HWIO_AOSS_CC_PLL1_MODE_PLL_LOCK_COUNT_SHFT                                               0x8
#define HWIO_AOSS_CC_PLL1_MODE_RESERVE_BIT7_BMSK                                                0x80
#define HWIO_AOSS_CC_PLL1_MODE_RESERVE_BIT7_SHFT                                                 0x7
#define HWIO_AOSS_CC_PLL1_MODE_PLL_CLOCK_SELECT_BMSK                                            0x40
#define HWIO_AOSS_CC_PLL1_MODE_PLL_CLOCK_SELECT_SHFT                                             0x6
#define HWIO_AOSS_CC_PLL1_MODE_PLL_REQUESTS_CAL_BMSK                                            0x20
#define HWIO_AOSS_CC_PLL1_MODE_PLL_REQUESTS_CAL_SHFT                                             0x5
#define HWIO_AOSS_CC_PLL1_MODE_PLL_CLK_XO_PRESENT_BMSK                                          0x10
#define HWIO_AOSS_CC_PLL1_MODE_PLL_CLK_XO_PRESENT_SHFT                                           0x4
#define HWIO_AOSS_CC_PLL1_MODE_PLL_IN_CALIBRATION_BMSK                                           0x8
#define HWIO_AOSS_CC_PLL1_MODE_PLL_IN_CALIBRATION_SHFT                                           0x3
#define HWIO_AOSS_CC_PLL1_MODE_PLL_RESET_N_BMSK                                                  0x4
#define HWIO_AOSS_CC_PLL1_MODE_PLL_RESET_N_SHFT                                                  0x2
#define HWIO_AOSS_CC_PLL1_MODE_RESERVE_BIT1_BMSK                                                 0x2
#define HWIO_AOSS_CC_PLL1_MODE_RESERVE_BIT1_SHFT                                                 0x1
#define HWIO_AOSS_CC_PLL1_MODE_PLL_OUTCTRL_BMSK                                                  0x1
#define HWIO_AOSS_CC_PLL1_MODE_PLL_OUTCTRL_SHFT                                                  0x0

#define HWIO_AOSS_CC_PLL1_L_VAL_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001004)
#define HWIO_AOSS_CC_PLL1_L_VAL_RMSK                                                           0xfff
#define HWIO_AOSS_CC_PLL1_L_VAL_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_L_VAL_ADDR)
#define HWIO_AOSS_CC_PLL1_L_VAL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_L_VAL_ADDR, m)
#define HWIO_AOSS_CC_PLL1_L_VAL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_L_VAL_ADDR,v)
#define HWIO_AOSS_CC_PLL1_L_VAL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_L_VAL_ADDR,m,v,HWIO_AOSS_CC_PLL1_L_VAL_IN)
#define HWIO_AOSS_CC_PLL1_L_VAL_PLL_L_BMSK                                                     0xfff
#define HWIO_AOSS_CC_PLL1_L_VAL_PLL_L_SHFT                                                       0x0

#define HWIO_AOSS_CC_PLL1_USER_CTL_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001008)
#define HWIO_AOSS_CC_PLL1_USER_CTL_RMSK                                                   0xffffffff
#define HWIO_AOSS_CC_PLL1_USER_CTL_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_USER_CTL_ADDR)
#define HWIO_AOSS_CC_PLL1_USER_CTL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_USER_CTL_ADDR, m)
#define HWIO_AOSS_CC_PLL1_USER_CTL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_USER_CTL_ADDR,v)
#define HWIO_AOSS_CC_PLL1_USER_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_USER_CTL_ADDR,m,v,HWIO_AOSS_CC_PLL1_USER_CTL_IN)
#define HWIO_AOSS_CC_PLL1_USER_CTL_RESERVE_BITS31_17_BMSK                                 0xfffe0000
#define HWIO_AOSS_CC_PLL1_USER_CTL_RESERVE_BITS31_17_SHFT                                       0x11
#define HWIO_AOSS_CC_PLL1_USER_CTL_POST_DIV_RATIO_EVEN_BMSK                                  0x10000
#define HWIO_AOSS_CC_PLL1_USER_CTL_POST_DIV_RATIO_EVEN_SHFT                                     0x10
#define HWIO_AOSS_CC_PLL1_USER_CTL_RESERVE_BITS15_12_BMSK                                     0xf000
#define HWIO_AOSS_CC_PLL1_USER_CTL_RESERVE_BITS15_12_SHFT                                        0xc
#define HWIO_AOSS_CC_PLL1_USER_CTL_POST_DIV_RATIO_BMSK                                         0xf00
#define HWIO_AOSS_CC_PLL1_USER_CTL_POST_DIV_RATIO_SHFT                                           0x8
#define HWIO_AOSS_CC_PLL1_USER_CTL_OUT_CLK_POLARITY_BMSK                                        0x80
#define HWIO_AOSS_CC_PLL1_USER_CTL_OUT_CLK_POLARITY_SHFT                                         0x7
#define HWIO_AOSS_CC_PLL1_USER_CTL_RESERVE_BITS6_5_BMSK                                         0x60
#define HWIO_AOSS_CC_PLL1_USER_CTL_RESERVE_BITS6_5_SHFT                                          0x5
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_TEST_BMSK                                             0x10
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_TEST_SHFT                                              0x4
#define HWIO_AOSS_CC_PLL1_USER_CTL_RESERVE_BITS3_2_BMSK                                          0xc
#define HWIO_AOSS_CC_PLL1_USER_CTL_RESERVE_BITS3_2_SHFT                                          0x2
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_EVEN_BMSK                                              0x2
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_EVEN_SHFT                                              0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_MAIN_BMSK                                              0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_PLLOUT_MAIN_SHFT                                              0x0

#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000100c)
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_RMSK                                                 0xffffffff
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_USER_CTL_U_ADDR)
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_USER_CTL_U_ADDR, m)
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_USER_CTL_U_ADDR,v)
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_USER_CTL_U_ADDR,m,v,HWIO_AOSS_CC_PLL1_USER_CTL_U_IN)
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_RESERVE_BITS63_59_BMSK                               0xf8000000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_RESERVE_BITS63_59_SHFT                                     0x1b
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_LOW_LATENCY_CLK_BMSK                           0x4000000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_LOW_LATENCY_CLK_SHFT                                0x1a
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_STANDBY_CLK_BMSK                               0x2000000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_STANDBY_CLK_SHFT                                    0x19
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_SET_MAX_COMP_RATE_BMSK                                0x1000000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_SET_MAX_COMP_RATE_SHFT                                     0x18
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_CONT_CAL_BMSK                                   0x800000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_ENABLE_CONT_CAL_SHFT                                       0x17
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_XO_FREQUENCY_SELECT_BMSK                               0x400000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_XO_FREQUENCY_SELECT_SHFT                                   0x16
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_INTERNAL_CLOCK_SELECTION_BMSK                          0x300000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_INTERNAL_CLOCK_SELECTION_SHFT                              0x14
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_RESERVE_BITS51_49_BMSK                                  0xe0000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_RESERVE_BITS51_49_SHFT                                     0x11
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_INITIAL_OUTPUT_CLOCK_MUX_BMSK                           0x18000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_INITIAL_OUTPUT_CLOCK_MUX_SHFT                               0xf
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_KEEP_BIAS_ON_IN_STBY_BMSK                                0x4000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_KEEP_BIAS_ON_IN_STBY_SHFT                                   0xe
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_XO_CLK_AT_OUT_BMSK                                       0x2000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_XO_CLK_AT_OUT_SHFT                                          0xd
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_CALIBRATION_SETTING_BMSK                                 0x1000
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_CALIBRATION_SETTING_SHFT                                    0xc
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_USE_RESTORE_BMSK                                          0x800
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_USE_RESTORE_SHFT                                            0xb
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_REQUEST_CAL_BMSK                                          0x400
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_REQUEST_CAL_SHFT                                            0xa
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_STATUS_REGISTER_BMSK                                      0x3e0
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_STATUS_REGISTER_SHFT                                        0x5
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_RESERVE_BITS36_35_BMSK                                     0x18
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_RESERVE_BITS36_35_SHFT                                      0x3
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_CAL_SCALING_BMSK                                            0x6
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_CAL_SCALING_SHFT                                            0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_USE_EXTERNAL_CLK_REF_BMSK                                   0x1
#define HWIO_AOSS_CC_PLL1_USER_CTL_U_USE_EXTERNAL_CLK_REF_SHFT                                   0x0

#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001010)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_RMSK                                                 0xffffffff
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_CONFIG_CTL_ADDR)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_CONFIG_CTL_ADDR, m)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_CONFIG_CTL_ADDR,v)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_CONFIG_CTL_ADDR,m,v,HWIO_AOSS_CC_PLL1_CONFIG_CTL_IN)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FINE_LD_UNMASK_TIMER_BMSK                            0xc0000000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FINE_LD_UNMASK_TIMER_SHFT                                  0x1e
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FINE_LD_RELOCK_SAMPLE_SIZE_BMSK                      0x30000000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FINE_LD_RELOCK_SAMPLE_SIZE_SHFT                            0x1c
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FCW_BMSK                                              0xffc0000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FCW_SHFT                                                   0x12
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_OVERRIDE_FCW_BMSK                                       0x20000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_OVERRIDE_FCW_SHFT                                          0x11
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FINE_LD_THRESHOLD_BMSK                                  0x1c000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FINE_LD_THRESHOLD_SHFT                                      0xe
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FINE_LD_SAMPLE_SIZE_BMSK                                 0x3f00
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FINE_LD_SAMPLE_SIZE_SHFT                                    0x8
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FWD_GAIN_KFN_SLEW_BMSK                                     0xf0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FWD_GAIN_KFN_SLEW_SHFT                                      0x4
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FWD_GAIN_KFN_BMSK                                           0xf
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_FWD_GAIN_KFN_SHFT                                           0x0

#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_ADDR                                               (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001014)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_RMSK                                               0xffffffff
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_ADDR)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_ADDR, m)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_ADDR,v)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_ADDR,m,v,HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_IN)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_THRESHOLD_1_BMSK                          0xfc000000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_THRESHOLD_1_SHFT                                0x1a
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_THRESHOLD_0_BMSK                           0x3f00000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_THRESHOLD_0_SHFT                                0x14
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_RESERVE_BIT51_BMSK                                    0x80000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_RESERVE_BIT51_SHFT                                       0x13
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_SKIP_FIRST_TEMPCOMP_RELOCK_BMSK                       0x40000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_SKIP_FIRST_TEMPCOMP_RELOCK_SHFT                          0x12
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_FIRST_TEMPCOMP_RELOCK_NUM_OUT_CYCLES_BMSK             0x30000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_FIRST_TEMPCOMP_RELOCK_NUM_OUT_CYCLES_SHFT                0x10
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_FIRST_TEMPCOMP_RELOCK_BMSK                             0x8000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_FIRST_TEMPCOMP_RELOCK_SHFT                                0xf
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_NUM_OUT_CYCLES_BMSK                           0x7000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_TEMPCOMP_NUM_OUT_CYCLES_SHFT                              0xc
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_CAL_NUM_XO_CYCLES_BMSK                                  0xe00
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_CAL_NUM_XO_CYCLES_SHFT                                    0x9
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_GLITCH_DETECTOR_COUNT_LIMIT_BMSK                        0x180
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_GLITCH_DETECTOR_COUNT_LIMIT_SHFT                          0x7
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_GLITCH_PREVENTION_DIS_BMSK                               0x40
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_GLITCH_PREVENTION_DIS_SHFT                                0x6
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_BMSK                         0x20
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_INC_MIN_GLITCH_THRESHOLD_4X_SHFT                          0x5
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_BMSK                                0x18
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_MIN_GLITCH_THRESHOLD_SHFT                                 0x3
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_RQ_LFSR_DISABLE_BMSK                                 0x4
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_RQ_LFSR_DISABLE_SHFT                                 0x2
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_RQ_BYPASS_BMSK                                       0x2
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_RQ_BYPASS_SHFT                                       0x1
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_LFSR_DISABLE_BMSK                                    0x1
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U_DFLL_LFSR_DISABLE_SHFT                                    0x0

#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_ADDR                                              (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001018)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_RMSK                                              0xffffffff
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_ADDR)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_ADDR, m)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_ADDR,v)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_ADDR,m,v,HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_IN)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_RESERVE_BITS95_94_BMSK                            0xc0000000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_RESERVE_BITS95_94_SHFT                                  0x1e
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_6_BMSK                         0x3f000000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_6_SHFT                               0x18
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_5_BMSK                           0xfc0000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_5_SHFT                               0x12
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_4_BMSK                            0x3f000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_4_SHFT                                0xc
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_3_BMSK                              0xfc0
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_3_SHFT                                0x6
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_2_BMSK                               0x3f
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U1_TEMPCOMP_THRESHOLD_2_SHFT                                0x0

#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_ADDR                                              (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000101c)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_RMSK                                              0xffffffff
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_ADDR)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_ADDR, m)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_ADDR,v)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_ADDR,m,v,HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_IN)
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_RESERVE_BITS127_126_BMSK                          0xc0000000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_RESERVE_BITS127_126_SHFT                                0x1e
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_TEMPCOMP_CORRFACTOR_CLAMP_BMSK                    0x3fc00000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_TEMPCOMP_CORRFACTOR_CLAMP_SHFT                          0x16
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_TEMPCOMP_MIN_DIST_OF_SEP_BMSK                       0x3f0000
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_TEMPCOMP_MIN_DIST_OF_SEP_SHFT                           0x10
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_TEMPCOMP_K_DEFAULT_BMSK                               0xffff
#define HWIO_AOSS_CC_PLL1_CONFIG_CTL_U2_TEMPCOMP_K_DEFAULT_SHFT                                  0x0

#define HWIO_AOSS_CC_PLL1_TEST_CTL_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001020)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_RMSK                                                   0xffffffff
#define HWIO_AOSS_CC_PLL1_TEST_CTL_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_TEST_CTL_ADDR)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_TEST_CTL_ADDR, m)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_TEST_CTL_ADDR,v)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_TEST_CTL_ADDR,m,v,HWIO_AOSS_CC_PLL1_TEST_CTL_IN)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_SOSC_ON_BMSK                                     0x80000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_SOSC_ON_SHFT                                           0x1f
#define HWIO_AOSS_CC_PLL1_TEST_CTL_KEEP_SOSC_ON_IN_STBY_BMSK                              0x40000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_KEEP_SOSC_ON_IN_STBY_SHFT                                    0x1e
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_STAY_IN_FREERUN_BMSK                             0x20000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_STAY_IN_FREERUN_SHFT                                   0x1d
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_STAY_IN_LOCKED_BMSK                              0x10000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_STAY_IN_LOCKED_SHFT                                    0x1c
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_FREERUN_BMSK                                 0x8000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_FREERUN_SHFT                                      0x1b
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_LOCKED_BMSK                                  0x4000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_LOCKED_SHFT                                       0x1a
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_TEMPCOMP_BMSK                                0x2000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_TEMPCOMP_SHFT                                     0x19
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_CAL_AFTER_FIRST_BMSK                         0x1000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FORCE_EXIT_CAL_AFTER_FIRST_SHFT                              0x18
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FREERUNTIMER_BMSK                                        0xe00000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_FREERUNTIMER_SHFT                                            0x15
#define HWIO_AOSS_CC_PLL1_TEST_CTL_LOCKEDTIMER_BMSK                                         0x1c0000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_LOCKEDTIMER_SHFT                                             0x12
#define HWIO_AOSS_CC_PLL1_TEST_CTL_DCOTIMER_BMSK                                             0x38000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_DCOTIMER_SHFT                                                 0xf
#define HWIO_AOSS_CC_PLL1_TEST_CTL_BIASTIMER_BMSK                                             0x7000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_BIASTIMER_SHFT                                                0xc
#define HWIO_AOSS_CC_PLL1_TEST_CTL_TDOTIMER2_BMSK                                              0xe00
#define HWIO_AOSS_CC_PLL1_TEST_CTL_TDOTIMER2_SHFT                                                0x9
#define HWIO_AOSS_CC_PLL1_TEST_CTL_TDOTIMER1_BMSK                                              0x1c0
#define HWIO_AOSS_CC_PLL1_TEST_CTL_TDOTIMER1_SHFT                                                0x6
#define HWIO_AOSS_CC_PLL1_TEST_CTL_TDOTIMER0_BMSK                                               0x38
#define HWIO_AOSS_CC_PLL1_TEST_CTL_TDOTIMER0_SHFT                                                0x3
#define HWIO_AOSS_CC_PLL1_TEST_CTL_TSENSTIMER_BMSK                                               0x7
#define HWIO_AOSS_CC_PLL1_TEST_CTL_TSENSTIMER_SHFT                                               0x0

#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001024)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_RMSK                                                 0xffffffff
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_TEST_CTL_U_ADDR)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_TEST_CTL_U_ADDR, m)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_TEST_CTL_U_ADDR,v)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_TEST_CTL_U_ADDR,m,v,HWIO_AOSS_CC_PLL1_TEST_CTL_U_IN)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_TDO_PCAL_TARGET_BMSK                                 0xf0000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_TDO_PCAL_TARGET_SHFT                                       0x1c
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_LD_UNMASK_BMSK                                  0x8000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_LD_UNMASK_SHFT                                       0x1b
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_STATUS_SEL_CAL_RAM_ROW_BMSK                           0x7000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_STATUS_SEL_CAL_RAM_ROW_SHFT                                0x18
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_DISABLE_TSENS_IN_STBY_BMSK                             0x800000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_DISABLE_TSENS_IN_STBY_SHFT                                 0x17
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_RESERVE_BITS54_51_BMSK                                 0x780000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_RESERVE_BITS54_51_SHFT                                     0x13
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_BIST_CFG_BMSK                                           0x7ff80
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_BIST_CFG_SHFT                                               0x7
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_ENABLE_TEST_SEQ_BMSK                                       0x40
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_ENABLE_TEST_SEQ_SHFT                                        0x6
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_STATUS_REG_EN_BMSK                                         0x20
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_STATUS_REG_EN_SHFT                                          0x5
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_BIAS_AND_DCO_ON_BMSK                                 0x10
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_BIAS_AND_DCO_ON_SHFT                                  0x4
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_SET_TDO_MODE_BMSK                                           0x8
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_SET_TDO_MODE_SHFT                                           0x3
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TDO_MODE_BMSK                                         0x4
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TDO_MODE_SHFT                                         0x2
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TDO_ON_BMSK                                           0x2
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TDO_ON_SHFT                                           0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TSENS_ON_BMSK                                         0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U_FORCE_TSENS_ON_SHFT                                         0x0

#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001028)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_RMSK                                                0xffffffff
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_TEST_CTL_U1_ADDR)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_TEST_CTL_U1_ADDR, m)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_TEST_CTL_U1_ADDR,v)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_TEST_CTL_U1_ADDR,m,v,HWIO_AOSS_CC_PLL1_TEST_CTL_U1_IN)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INITIAL_INPUT_MUX_CLK_CAL_BMSK                      0xc0000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INITIAL_INPUT_MUX_CLK_CAL_SHFT                            0x1e
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INITIAL_INPUT_MUX_CLK_DIG_BMSK                      0x3e000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_INITIAL_INPUT_MUX_CLK_DIG_SHFT                            0x19
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_ATEST1_VOLT_SEL_BMSK                             0x1800000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_ATEST1_VOLT_SEL_SHFT                                  0x17
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_REG_BIAS_BMSK                                     0x600000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_REG_BIAS_SHFT                                         0x15
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_VREF_SEL_BMSK                                     0x180000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_VREF_SEL_SHFT                                         0x13
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_ENABLEVMUXPROBE_BMSK                               0x40000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_ENABLEVMUXPROBE_SHFT                                  0x12
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_ENABLEVLDOPROBE_BMSK                               0x20000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_ENABLEVLDOPROBE_SHFT                                  0x11
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_CHOPSELECT_BMSK                                    0x10000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_CHOPSELECT_SHFT                                       0x10
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_BIAS_ENABLEATESTSOURCE_BMSK                             0x8000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_BIAS_ENABLEATESTSOURCE_SHFT                                0xf
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_BIAS_ENABLEIOUTATEST_BMSK                               0x4000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_BIAS_ENABLEIOUTATEST_SHFT                                  0xe
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_DISABLE_RESYNC_BMSK                                 0x2000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_DISABLE_RESYNC_SHFT                                    0xd
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_RESISTOR_ADJUST_BMSK                                0x1800
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_RESISTOR_ADJUST_SHFT                                   0xb
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_INCREASE_GAIN_BMSK                                   0x400
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_TDO_INCREASE_GAIN_SHFT                                     0xa
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_RESERVE_BIT73_BMSK                                       0x200
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_RESERVE_BIT73_SHFT                                         0x9
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_SELECT_FWD_GAIN_TEMPCOMP_BMSK                            0x100
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_SELECT_FWD_GAIN_TEMPCOMP_SHFT                              0x8
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_PCAL_DIV_EN_BMSK                                      0x80
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DCO_PCAL_DIV_EN_SHFT                                       0x7
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_FORCE_BOTH_DCO_ENABLES_TOGETHER_BMSK                      0x40
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_FORCE_BOTH_DCO_ENABLES_TOGETHER_SHFT                       0x6
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_FORCE_DCO_PCAL_VALUE_BMSK                                 0x20
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_FORCE_DCO_PCAL_VALUE_SHFT                                  0x5
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DISABLE_DCO_PCAL_BMSK                                     0x10
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DISABLE_DCO_PCAL_SHFT                                      0x4
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_FORCE_TDO_PCAL_VALUE_BMSK                                  0xe
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_FORCE_TDO_PCAL_VALUE_SHFT                                  0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DISABLE_TDO_PCAL_BMSK                                      0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U1_DISABLE_TDO_PCAL_SHFT                                      0x0

#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000102c)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_RMSK                                                0xffffffff
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ADDR)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ADDR, m)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ADDR,v)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ADDR,m,v,HWIO_AOSS_CC_PLL1_TEST_CTL_U2_IN)
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_PLL_TEST_OUT_SEL_BMSK                               0xf0000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_PLL_TEST_OUT_SEL_SHFT                                     0x1c
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_OVERRIDE_XO_BMSK                                     0x8000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_OVERRIDE_XO_SHFT                                          0x1b
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NMO_EN_DIV2_BMSK                                     0x4000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NMO_EN_DIV2_SHFT                                          0x1a
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NMO_OSC_SEL_BMSK                                     0x3000000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NMO_OSC_SEL_SHFT                                          0x18
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NG_NOISE_MAG_BMSK                                     0xe00000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NG_NOISE_MAG_SHFT                                         0x15
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NG_EN_BMSK                                            0x100000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_NG_EN_SHFT                                                0x14
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST1_BUFFER_CHOP_BMSK                                0x80000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST1_BUFFER_CHOP_SHFT                                   0x13
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST1_BUFFER_EN_BMSK                                  0x40000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST1_BUFFER_EN_SHFT                                     0x12
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST_EN_BMSK                                          0x20000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_ATEST_EN_SHFT                                             0x11
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_RESERVE_BITS112_110_BMSK                               0x1c000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_RESERVE_BITS112_110_SHFT                                   0xe
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_SOSC_CAL_THRSHLD_BMSK                                   0x3000
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_SOSC_CAL_THRSHLD_SHFT                                      0xc
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_OVERRIDE_SOSC_CAL_DIV_BMSK                               0x800
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_OVERRIDE_SOSC_CAL_DIV_SHFT                                 0xb
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_FREERUN_BMSK                               0x780
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_FREERUN_SHFT                                 0x7
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_SPEEDUP_CLKDIG_TEMPCOMP_BMSK                              0x40
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_SPEEDUP_CLKDIG_TEMPCOMP_SHFT                               0x6
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_ACQ_LOCKED_BMSK                             0x38
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_CLKDIG_ACQ_LOCKED_SHFT                              0x3
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_SOSC_BMSK                                           0x6
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_SOSC_SHFT                                           0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_TDO_BMSK                                            0x1
#define HWIO_AOSS_CC_PLL1_TEST_CTL_U2_DIVIDE_TDO_SHFT                                            0x0

#define HWIO_AOSS_CC_PLL1_FREQ_CTL_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001030)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_RMSK                                                   0xffffffff
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_FREQ_CTL_ADDR)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_FREQ_CTL_ADDR, m)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_FREQ_CTL_ADDR,v)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_FREQ_CTL_ADDR,m,v,HWIO_AOSS_CC_PLL1_FREQ_CTL_IN)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_FREQUENCY_CTL_WORD_LOWER_BMSK                          0xffffffff
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_FREQUENCY_CTL_WORD_LOWER_SHFT                                 0x0

#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001034)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_RMSK                                                 0xffffffff
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_FREQ_CTL_U_ADDR)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_FREQ_CTL_U_ADDR, m)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_FREQ_CTL_U_ADDR,v)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_FREQ_CTL_U_ADDR,m,v,HWIO_AOSS_CC_PLL1_FREQ_CTL_U_IN)
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_FREQUENCY_CTL_WORD_UPPER_BMSK                        0xffffffff
#define HWIO_AOSS_CC_PLL1_FREQ_CTL_U_FREQUENCY_CTL_WORD_UPPER_SHFT                               0x0

#define HWIO_AOSS_CC_PLL1_STATUS_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001038)
#define HWIO_AOSS_CC_PLL1_STATUS_RMSK                                                     0xffffffff
#define HWIO_AOSS_CC_PLL1_STATUS_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_STATUS_ADDR)
#define HWIO_AOSS_CC_PLL1_STATUS_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_STATUS_ADDR, m)
#define HWIO_AOSS_CC_PLL1_STATUS_STATUS_31_0_BMSK                                         0xffffffff
#define HWIO_AOSS_CC_PLL1_STATUS_STATUS_31_0_SHFT                                                0x0

#define HWIO_AOSS_CC_PLL1_STATE_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000103c)
#define HWIO_AOSS_CC_PLL1_STATE_RMSK                                                             0x7
#define HWIO_AOSS_CC_PLL1_STATE_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_STATE_ADDR)
#define HWIO_AOSS_CC_PLL1_STATE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_STATE_ADDR, m)
#define HWIO_AOSS_CC_PLL1_STATE_PLL_STATE_BMSK                                                   0x7
#define HWIO_AOSS_CC_PLL1_STATE_PLL_STATE_SHFT                                                   0x0

#define HWIO_AOSS_CC_PLL1_OPMODE_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001040)
#define HWIO_AOSS_CC_PLL1_OPMODE_RMSK                                                            0x7
#define HWIO_AOSS_CC_PLL1_OPMODE_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_OPMODE_ADDR)
#define HWIO_AOSS_CC_PLL1_OPMODE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_OPMODE_ADDR, m)
#define HWIO_AOSS_CC_PLL1_OPMODE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_OPMODE_ADDR,v)
#define HWIO_AOSS_CC_PLL1_OPMODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_OPMODE_ADDR,m,v,HWIO_AOSS_CC_PLL1_OPMODE_IN)
#define HWIO_AOSS_CC_PLL1_OPMODE_PLL_OPMODE_BMSK                                                 0x7
#define HWIO_AOSS_CC_PLL1_OPMODE_PLL_OPMODE_SHFT                                                 0x0

#define HWIO_AOSS_CC_PLL1_SPARE_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00001044)
#define HWIO_AOSS_CC_PLL1_SPARE_RMSK                                                            0xff
#define HWIO_AOSS_CC_PLL1_SPARE_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_SPARE_ADDR)
#define HWIO_AOSS_CC_PLL1_SPARE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_SPARE_ADDR, m)
#define HWIO_AOSS_CC_PLL1_SPARE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_SPARE_ADDR,v)
#define HWIO_AOSS_CC_PLL1_SPARE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_SPARE_ADDR,m,v,HWIO_AOSS_CC_PLL1_SPARE_IN)
#define HWIO_AOSS_CC_PLL1_SPARE_SPARE_OUTPUTS_BMSK                                              0xf0
#define HWIO_AOSS_CC_PLL1_SPARE_SPARE_OUTPUTS_SHFT                                               0x4
#define HWIO_AOSS_CC_PLL1_SPARE_SPARE_INPUTS_BMSK                                                0xf
#define HWIO_AOSS_CC_PLL1_SPARE_SPARE_INPUTS_SHFT                                                0x0

#define HWIO_AOSS_CC_AOP_BCR_ADDR                                                         (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002000)
#define HWIO_AOSS_CC_AOP_BCR_RMSK                                                                0x1
#define HWIO_AOSS_CC_AOP_BCR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_BCR_ADDR)
#define HWIO_AOSS_CC_AOP_BCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_BCR_ADDR, m)
#define HWIO_AOSS_CC_AOP_BCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_BCR_ADDR,v)
#define HWIO_AOSS_CC_AOP_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_BCR_ADDR,m,v,HWIO_AOSS_CC_AOP_BCR_IN)
#define HWIO_AOSS_CC_AOP_BCR_BLK_ARES_BMSK                                                       0x1
#define HWIO_AOSS_CC_AOP_BCR_BLK_ARES_SHFT                                                       0x0

#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_ADDR                                           (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002004)
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_RMSK                                           0x80000005
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_ADDR)
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_ADDR, m)
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_ADDR,v)
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_ADDR,m,v,HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_IN)
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_CLK_OFF_BMSK                                   0x80000000
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_CLK_OFF_SHFT                                         0x1f
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_CLK_ARES_BMSK                                         0x4
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_CLK_ARES_SHFT                                         0x2
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_CLK_ENABLE_BMSK                                       0x1
#define HWIO_AOSS_CC_AOP_PROC_FREERUN_CBCR_CLK_ENABLE_SHFT                                       0x0

#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_ADDR                                         (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002008)
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_RMSK                                         0x80000004
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_ADDR)
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_ADDR, m)
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_ADDR,v)
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_ADDR,m,v,HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_IN)
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_CLK_OFF_BMSK                                 0x80000000
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_CLK_OFF_SHFT                                       0x1f
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_CLK_ARES_BMSK                                       0x4
#define HWIO_AOSS_CC_AOP_PROC_RISCV_AHB_CBCR_CLK_ARES_SHFT                                       0x2

#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_ADDR                                               (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000200c)
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_RMSK                                               0x80000004
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_ADDR)
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_ADDR, m)
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_ADDR,v)
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_ADDR,m,v,HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_IN)
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_CLK_OFF_BMSK                                       0x80000000
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_CLK_OFF_SHFT                                             0x1f
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_CLK_ARES_BMSK                                             0x4
#define HWIO_AOSS_CC_AOP_PROC_AHB_CBCR_CLK_ARES_SHFT                                             0x2

#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002010)
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_RMSK                                                0x80007ff4
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_ADDR)
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_ADDR, m)
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_ADDR,v)
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_ADDR,m,v,HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_IN)
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_CORE_ON_BMSK                                  0x4000
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_CORE_ON_SHFT                                     0xe
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                0x2000
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                   0xd
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                               0x1000
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                  0xc
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_BMSK                                              0xf00
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_WAKEUP_SHFT                                                0x8
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_BMSK                                                0xf0
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_SLEEP_SHFT                                                 0x4
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_AOSS_CC_AOP_BUS_AHB_CBCR_CLK_ARES_SHFT                                              0x2

#define HWIO_AOSS_CC_BUS_CBCR_ADDR                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002014)
#define HWIO_AOSS_CC_BUS_CBCR_RMSK                                                        0x80000004
#define HWIO_AOSS_CC_BUS_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_BUS_CBCR_ADDR)
#define HWIO_AOSS_CC_BUS_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_BUS_CBCR_ADDR, m)
#define HWIO_AOSS_CC_BUS_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_BUS_CBCR_ADDR,v)
#define HWIO_AOSS_CC_BUS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_BUS_CBCR_ADDR,m,v,HWIO_AOSS_CC_BUS_CBCR_IN)
#define HWIO_AOSS_CC_BUS_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_AOSS_CC_BUS_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_AOSS_CC_BUS_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_AOSS_CC_BUS_CBCR_CLK_ARES_SHFT                                                      0x2

#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002018)
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_RMSK                                                0x80007ff5
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_MESSAGE_RAM_CBCR_ADDR)
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_MESSAGE_RAM_CBCR_ADDR, m)
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_MESSAGE_RAM_CBCR_ADDR,v)
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_MESSAGE_RAM_CBCR_ADDR,m,v,HWIO_AOSS_CC_MESSAGE_RAM_CBCR_IN)
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_CLK_OFF_BMSK                                        0x80000000
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_CLK_OFF_SHFT                                              0x1f
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_CORE_ON_BMSK                                  0x4000
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_CORE_ON_SHFT                                     0xe
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                0x2000
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                   0xd
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                               0x1000
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                  0xc
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_BMSK                                              0xf00
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_WAKEUP_SHFT                                                0x8
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_BMSK                                                0xf0
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_SLEEP_SHFT                                                 0x4
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_CLK_ARES_BMSK                                              0x4
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_CLK_ARES_SHFT                                              0x2
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_CLK_ENABLE_BMSK                                            0x1
#define HWIO_AOSS_CC_MESSAGE_RAM_CBCR_CLK_ENABLE_SHFT                                            0x0

#define HWIO_AOSS_CC_AOP_RO_CBCR_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000201c)
#define HWIO_AOSS_CC_AOP_RO_CBCR_RMSK                                                     0x80000005
#define HWIO_AOSS_CC_AOP_RO_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_RO_CBCR_ADDR)
#define HWIO_AOSS_CC_AOP_RO_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_RO_CBCR_ADDR, m)
#define HWIO_AOSS_CC_AOP_RO_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_RO_CBCR_ADDR,v)
#define HWIO_AOSS_CC_AOP_RO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_RO_CBCR_ADDR,m,v,HWIO_AOSS_CC_AOP_RO_CBCR_IN)
#define HWIO_AOSS_CC_AOP_RO_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_AOSS_CC_AOP_RO_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_AOSS_CC_AOP_RO_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_AOSS_CC_AOP_RO_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_AOSS_CC_AOP_RO_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_AOSS_CC_AOP_RO_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_ADDR                                               (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002020)
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_RMSK                                               0x80000005
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_ADDR)
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_ADDR, m)
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_ADDR,v)
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_ADDR,m,v,HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_IN)
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_CLK_OFF_BMSK                                       0x80000000
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_CLK_OFF_SHFT                                             0x1f
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_CLK_ARES_BMSK                                             0x4
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_CLK_ARES_SHFT                                             0x2
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_CLK_ENABLE_BMSK                                           0x1
#define HWIO_AOSS_CC_PWR_MUX_CTRL_CBCR_CLK_ENABLE_SHFT                                           0x0

#define HWIO_AOSS_CC_AO_DAP_CBCR_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002024)
#define HWIO_AOSS_CC_AO_DAP_CBCR_RMSK                                                     0x80000005
#define HWIO_AOSS_CC_AO_DAP_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_AO_DAP_CBCR_ADDR)
#define HWIO_AOSS_CC_AO_DAP_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AO_DAP_CBCR_ADDR, m)
#define HWIO_AOSS_CC_AO_DAP_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AO_DAP_CBCR_ADDR,v)
#define HWIO_AOSS_CC_AO_DAP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AO_DAP_CBCR_ADDR,m,v,HWIO_AOSS_CC_AO_DAP_CBCR_IN)
#define HWIO_AOSS_CC_AO_DAP_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_AOSS_CC_AO_DAP_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_AOSS_CC_AO_DAP_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_AOSS_CC_AO_DAP_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_AOSS_CC_AO_DAP_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_AOSS_CC_AO_DAP_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_AOSS_CC_AOP_DAP_CBCR_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002028)
#define HWIO_AOSS_CC_AOP_DAP_CBCR_RMSK                                                    0x80000005
#define HWIO_AOSS_CC_AOP_DAP_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_DAP_CBCR_ADDR)
#define HWIO_AOSS_CC_AOP_DAP_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_DAP_CBCR_ADDR, m)
#define HWIO_AOSS_CC_AOP_DAP_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_DAP_CBCR_ADDR,v)
#define HWIO_AOSS_CC_AOP_DAP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_DAP_CBCR_ADDR,m,v,HWIO_AOSS_CC_AOP_DAP_CBCR_IN)
#define HWIO_AOSS_CC_AOP_DAP_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_AOSS_CC_AOP_DAP_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_AOSS_CC_AOP_DAP_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_AOSS_CC_AOP_DAP_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_AOSS_CC_AOP_DAP_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_AOSS_CC_AOP_DAP_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_AOSS_CC_WCSS_TS_CBCR_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000202c)
#define HWIO_AOSS_CC_WCSS_TS_CBCR_RMSK                                                    0x80000005
#define HWIO_AOSS_CC_WCSS_TS_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_WCSS_TS_CBCR_ADDR)
#define HWIO_AOSS_CC_WCSS_TS_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_WCSS_TS_CBCR_ADDR, m)
#define HWIO_AOSS_CC_WCSS_TS_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_WCSS_TS_CBCR_ADDR,v)
#define HWIO_AOSS_CC_WCSS_TS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_WCSS_TS_CBCR_ADDR,m,v,HWIO_AOSS_CC_WCSS_TS_CBCR_IN)
#define HWIO_AOSS_CC_WCSS_TS_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_AOSS_CC_WCSS_TS_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_AOSS_CC_WCSS_TS_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_AOSS_CC_WCSS_TS_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_AOSS_CC_WCSS_TS_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_AOSS_CC_WCSS_TS_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_AOSS_CC_RO_CBCR_ADDR                                                         (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002030)
#define HWIO_AOSS_CC_RO_CBCR_RMSK                                                         0x80000005
#define HWIO_AOSS_CC_RO_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_RO_CBCR_ADDR)
#define HWIO_AOSS_CC_RO_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RO_CBCR_ADDR, m)
#define HWIO_AOSS_CC_RO_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RO_CBCR_ADDR,v)
#define HWIO_AOSS_CC_RO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RO_CBCR_ADDR,m,v,HWIO_AOSS_CC_RO_CBCR_IN)
#define HWIO_AOSS_CC_RO_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_AOSS_CC_RO_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_AOSS_CC_RO_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_AOSS_CC_RO_CBCR_CLK_ARES_SHFT                                                       0x2
#define HWIO_AOSS_CC_RO_CBCR_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_AOSS_CC_RO_CBCR_CLK_ENABLE_SHFT                                                     0x0

#define HWIO_AOSS_CC_EUD_AT_CBCR_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002034)
#define HWIO_AOSS_CC_EUD_AT_CBCR_RMSK                                                     0x80000005
#define HWIO_AOSS_CC_EUD_AT_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_EUD_AT_CBCR_ADDR)
#define HWIO_AOSS_CC_EUD_AT_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_EUD_AT_CBCR_ADDR, m)
#define HWIO_AOSS_CC_EUD_AT_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_EUD_AT_CBCR_ADDR,v)
#define HWIO_AOSS_CC_EUD_AT_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_EUD_AT_CBCR_ADDR,m,v,HWIO_AOSS_CC_EUD_AT_CBCR_IN)
#define HWIO_AOSS_CC_EUD_AT_CBCR_CLK_OFF_BMSK                                             0x80000000
#define HWIO_AOSS_CC_EUD_AT_CBCR_CLK_OFF_SHFT                                                   0x1f
#define HWIO_AOSS_CC_EUD_AT_CBCR_CLK_ARES_BMSK                                                   0x4
#define HWIO_AOSS_CC_EUD_AT_CBCR_CLK_ARES_SHFT                                                   0x2
#define HWIO_AOSS_CC_EUD_AT_CBCR_CLK_ENABLE_BMSK                                                 0x1
#define HWIO_AOSS_CC_EUD_AT_CBCR_CLK_ENABLE_SHFT                                                 0x0

#define HWIO_AOSS_CC_XO_CBCR_ADDR                                                         (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002038)
#define HWIO_AOSS_CC_XO_CBCR_RMSK                                                         0x80000005
#define HWIO_AOSS_CC_XO_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_XO_CBCR_ADDR)
#define HWIO_AOSS_CC_XO_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_XO_CBCR_ADDR, m)
#define HWIO_AOSS_CC_XO_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_XO_CBCR_ADDR,v)
#define HWIO_AOSS_CC_XO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_XO_CBCR_ADDR,m,v,HWIO_AOSS_CC_XO_CBCR_IN)
#define HWIO_AOSS_CC_XO_CBCR_CLK_OFF_BMSK                                                 0x80000000
#define HWIO_AOSS_CC_XO_CBCR_CLK_OFF_SHFT                                                       0x1f
#define HWIO_AOSS_CC_XO_CBCR_CLK_ARES_BMSK                                                       0x4
#define HWIO_AOSS_CC_XO_CBCR_CLK_ARES_SHFT                                                       0x2
#define HWIO_AOSS_CC_XO_CBCR_CLK_ENABLE_BMSK                                                     0x1
#define HWIO_AOSS_CC_XO_CBCR_CLK_ENABLE_SHFT                                                     0x0

#define HWIO_AOSS_CC_GDSC_CBCR_ADDR                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000203c)
#define HWIO_AOSS_CC_GDSC_CBCR_RMSK                                                       0x80000005
#define HWIO_AOSS_CC_GDSC_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_GDSC_CBCR_ADDR)
#define HWIO_AOSS_CC_GDSC_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_GDSC_CBCR_ADDR, m)
#define HWIO_AOSS_CC_GDSC_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_GDSC_CBCR_ADDR,v)
#define HWIO_AOSS_CC_GDSC_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_GDSC_CBCR_ADDR,m,v,HWIO_AOSS_CC_GDSC_CBCR_IN)
#define HWIO_AOSS_CC_GDSC_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_AOSS_CC_GDSC_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_AOSS_CC_GDSC_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_AOSS_CC_GDSC_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_AOSS_CC_GDSC_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_AOSS_CC_GDSC_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_AOSS_CC_TSENS_HW_CBCR_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002040)
#define HWIO_AOSS_CC_TSENS_HW_CBCR_RMSK                                                   0x80000004
#define HWIO_AOSS_CC_TSENS_HW_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_TSENS_HW_CBCR_ADDR)
#define HWIO_AOSS_CC_TSENS_HW_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_TSENS_HW_CBCR_ADDR, m)
#define HWIO_AOSS_CC_TSENS_HW_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_TSENS_HW_CBCR_ADDR,v)
#define HWIO_AOSS_CC_TSENS_HW_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_TSENS_HW_CBCR_ADDR,m,v,HWIO_AOSS_CC_TSENS_HW_CBCR_IN)
#define HWIO_AOSS_CC_TSENS_HW_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_AOSS_CC_TSENS_HW_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_AOSS_CC_TSENS_HW_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_AOSS_CC_TSENS_HW_CBCR_CLK_ARES_SHFT                                                 0x2

#define HWIO_AOSS_CC_PDC_CBCR_ADDR                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002044)
#define HWIO_AOSS_CC_PDC_CBCR_RMSK                                                        0x80000005
#define HWIO_AOSS_CC_PDC_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_PDC_CBCR_ADDR)
#define HWIO_AOSS_CC_PDC_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PDC_CBCR_ADDR, m)
#define HWIO_AOSS_CC_PDC_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PDC_CBCR_ADDR,v)
#define HWIO_AOSS_CC_PDC_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PDC_CBCR_ADDR,m,v,HWIO_AOSS_CC_PDC_CBCR_IN)
#define HWIO_AOSS_CC_PDC_CBCR_CLK_OFF_BMSK                                                0x80000000
#define HWIO_AOSS_CC_PDC_CBCR_CLK_OFF_SHFT                                                      0x1f
#define HWIO_AOSS_CC_PDC_CBCR_CLK_ARES_BMSK                                                      0x4
#define HWIO_AOSS_CC_PDC_CBCR_CLK_ARES_SHFT                                                      0x2
#define HWIO_AOSS_CC_PDC_CBCR_CLK_ENABLE_BMSK                                                    0x1
#define HWIO_AOSS_CC_PDC_CBCR_CLK_ENABLE_SHFT                                                    0x0

#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_ADDR                                            (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002048)
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_RMSK                                            0x80000005
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_ADDR)
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_ADDR, m)
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_ADDR,v)
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_ADDR,m,v,HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_IN)
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_CLK_OFF_BMSK                                    0x80000000
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_CLK_OFF_SHFT                                          0x1f
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_CLK_ARES_BMSK                                          0x4
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_CLK_ARES_SHFT                                          0x2
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_CLK_ENABLE_BMSK                                        0x1
#define HWIO_AOSS_CC_PDC_GLOBAL_CNTR_CBCR_CLK_ENABLE_SHFT                                        0x0

#define HWIO_AOSS_CC_AOP_CMD_RCGR_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000204c)
#define HWIO_AOSS_CC_AOP_CMD_RCGR_RMSK                                                    0x80000013
#define HWIO_AOSS_CC_AOP_CMD_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_CMD_RCGR_ADDR)
#define HWIO_AOSS_CC_AOP_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_CMD_RCGR_ADDR, m)
#define HWIO_AOSS_CC_AOP_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_CMD_RCGR_ADDR,v)
#define HWIO_AOSS_CC_AOP_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_CMD_RCGR_ADDR,m,v,HWIO_AOSS_CC_AOP_CMD_RCGR_IN)
#define HWIO_AOSS_CC_AOP_CMD_RCGR_ROOT_OFF_BMSK                                           0x80000000
#define HWIO_AOSS_CC_AOP_CMD_RCGR_ROOT_OFF_SHFT                                                 0x1f
#define HWIO_AOSS_CC_AOP_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                           0x10
#define HWIO_AOSS_CC_AOP_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                            0x4
#define HWIO_AOSS_CC_AOP_CMD_RCGR_ROOT_EN_BMSK                                                   0x2
#define HWIO_AOSS_CC_AOP_CMD_RCGR_ROOT_EN_SHFT                                                   0x1
#define HWIO_AOSS_CC_AOP_CMD_RCGR_UPDATE_BMSK                                                    0x1
#define HWIO_AOSS_CC_AOP_CMD_RCGR_UPDATE_SHFT                                                    0x0

#define HWIO_AOSS_CC_AOP_CFG_RCGR_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002050)
#define HWIO_AOSS_CC_AOP_CFG_RCGR_RMSK                                                      0x11071f
#define HWIO_AOSS_CC_AOP_CFG_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_CFG_RCGR_ADDR)
#define HWIO_AOSS_CC_AOP_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_CFG_RCGR_ADDR, m)
#define HWIO_AOSS_CC_AOP_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_CFG_RCGR_ADDR,v)
#define HWIO_AOSS_CC_AOP_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_CFG_RCGR_ADDR,m,v,HWIO_AOSS_CC_AOP_CFG_RCGR_IN)
#define HWIO_AOSS_CC_AOP_CFG_RCGR_HW_CLK_CONTROL_BMSK                                       0x100000
#define HWIO_AOSS_CC_AOP_CFG_RCGR_HW_CLK_CONTROL_SHFT                                           0x14
#define HWIO_AOSS_CC_AOP_CFG_RCGR_RCGLITE_DISABLE_BMSK                                       0x10000
#define HWIO_AOSS_CC_AOP_CFG_RCGR_RCGLITE_DISABLE_SHFT                                          0x10
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_SEL_BMSK                                                 0x700
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_SEL_SHFT                                                   0x8
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_AOSS_CC_AOP_CFG_RCGR_SRC_DIV_SHFT                                                   0x0

#define HWIO_AOSS_CC_AOP_DIV_CDIVR_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000208c)
#define HWIO_AOSS_CC_AOP_DIV_CDIVR_RMSK                                                          0xf
#define HWIO_AOSS_CC_AOP_DIV_CDIVR_IN          \
        in_dword(HWIO_AOSS_CC_AOP_DIV_CDIVR_ADDR)
#define HWIO_AOSS_CC_AOP_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_DIV_CDIVR_ADDR, m)
#define HWIO_AOSS_CC_AOP_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_DIV_CDIVR_ADDR,v)
#define HWIO_AOSS_CC_AOP_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_DIV_CDIVR_ADDR,m,v,HWIO_AOSS_CC_AOP_DIV_CDIVR_IN)
#define HWIO_AOSS_CC_AOP_DIV_CDIVR_CLK_DIV_BMSK                                                  0xf
#define HWIO_AOSS_CC_AOP_DIV_CDIVR_CLK_DIV_SHFT                                                  0x0

#define HWIO_AOSS_CC_RO_CMD_RCGR_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002090)
#define HWIO_AOSS_CC_RO_CMD_RCGR_RMSK                                                     0x80000013
#define HWIO_AOSS_CC_RO_CMD_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_RO_CMD_RCGR_ADDR)
#define HWIO_AOSS_CC_RO_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RO_CMD_RCGR_ADDR, m)
#define HWIO_AOSS_CC_RO_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RO_CMD_RCGR_ADDR,v)
#define HWIO_AOSS_CC_RO_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RO_CMD_RCGR_ADDR,m,v,HWIO_AOSS_CC_RO_CMD_RCGR_IN)
#define HWIO_AOSS_CC_RO_CMD_RCGR_ROOT_OFF_BMSK                                            0x80000000
#define HWIO_AOSS_CC_RO_CMD_RCGR_ROOT_OFF_SHFT                                                  0x1f
#define HWIO_AOSS_CC_RO_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                            0x10
#define HWIO_AOSS_CC_RO_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                             0x4
#define HWIO_AOSS_CC_RO_CMD_RCGR_ROOT_EN_BMSK                                                    0x2
#define HWIO_AOSS_CC_RO_CMD_RCGR_ROOT_EN_SHFT                                                    0x1
#define HWIO_AOSS_CC_RO_CMD_RCGR_UPDATE_BMSK                                                     0x1
#define HWIO_AOSS_CC_RO_CMD_RCGR_UPDATE_SHFT                                                     0x0

#define HWIO_AOSS_CC_RO_CFG_RCGR_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002094)
#define HWIO_AOSS_CC_RO_CFG_RCGR_RMSK                                                       0x11071f
#define HWIO_AOSS_CC_RO_CFG_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_RO_CFG_RCGR_ADDR)
#define HWIO_AOSS_CC_RO_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RO_CFG_RCGR_ADDR, m)
#define HWIO_AOSS_CC_RO_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RO_CFG_RCGR_ADDR,v)
#define HWIO_AOSS_CC_RO_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RO_CFG_RCGR_ADDR,m,v,HWIO_AOSS_CC_RO_CFG_RCGR_IN)
#define HWIO_AOSS_CC_RO_CFG_RCGR_HW_CLK_CONTROL_BMSK                                        0x100000
#define HWIO_AOSS_CC_RO_CFG_RCGR_HW_CLK_CONTROL_SHFT                                            0x14
#define HWIO_AOSS_CC_RO_CFG_RCGR_RCGLITE_DISABLE_BMSK                                        0x10000
#define HWIO_AOSS_CC_RO_CFG_RCGR_RCGLITE_DISABLE_SHFT                                           0x10
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_SEL_BMSK                                                  0x700
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_SEL_SHFT                                                    0x8
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_BMSK                                                   0x1f
#define HWIO_AOSS_CC_RO_CFG_RCGR_SRC_DIV_SHFT                                                    0x0

#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000020d0)
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_RMSK                                                 0x80000013
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ADDR)
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ADDR, m)
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ADDR,v)
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ADDR,m,v,HWIO_AOSS_CC_EUD_AT_CMD_RCGR_IN)
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ROOT_OFF_BMSK                                        0x80000000
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ROOT_OFF_SHFT                                              0x1f
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                        0x10
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                         0x4
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ROOT_EN_BMSK                                                0x2
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_ROOT_EN_SHFT                                                0x1
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_UPDATE_BMSK                                                 0x1
#define HWIO_AOSS_CC_EUD_AT_CMD_RCGR_UPDATE_SHFT                                                 0x0

#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000020d4)
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_RMSK                                                   0x11071f
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_EUD_AT_CFG_RCGR_ADDR)
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_EUD_AT_CFG_RCGR_ADDR, m)
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_EUD_AT_CFG_RCGR_ADDR,v)
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_EUD_AT_CFG_RCGR_ADDR,m,v,HWIO_AOSS_CC_EUD_AT_CFG_RCGR_IN)
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_HW_CLK_CONTROL_BMSK                                    0x100000
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_HW_CLK_CONTROL_SHFT                                        0x14
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_RCGLITE_DISABLE_BMSK                                    0x10000
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_RCGLITE_DISABLE_SHFT                                       0x10
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_SEL_BMSK                                              0x700
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_SEL_SHFT                                                0x8
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_BMSK                                               0x1f
#define HWIO_AOSS_CC_EUD_AT_CFG_RCGR_SRC_DIV_SHFT                                                0x0

#define HWIO_AOSS_CC_IBI_BCR_ADDR                                                         (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002110)
#define HWIO_AOSS_CC_IBI_BCR_RMSK                                                                0x1
#define HWIO_AOSS_CC_IBI_BCR_IN          \
        in_dword(HWIO_AOSS_CC_IBI_BCR_ADDR)
#define HWIO_AOSS_CC_IBI_BCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_IBI_BCR_ADDR, m)
#define HWIO_AOSS_CC_IBI_BCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_IBI_BCR_ADDR,v)
#define HWIO_AOSS_CC_IBI_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_IBI_BCR_ADDR,m,v,HWIO_AOSS_CC_IBI_BCR_IN)
#define HWIO_AOSS_CC_IBI_BCR_BLK_ARES_BMSK                                                       0x1
#define HWIO_AOSS_CC_IBI_BCR_BLK_ARES_SHFT                                                       0x0

#define HWIO_AOSS_CC_IBI_CMD_RCGR_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002114)
#define HWIO_AOSS_CC_IBI_CMD_RCGR_RMSK                                                    0x80000013
#define HWIO_AOSS_CC_IBI_CMD_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_IBI_CMD_RCGR_ADDR)
#define HWIO_AOSS_CC_IBI_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_IBI_CMD_RCGR_ADDR, m)
#define HWIO_AOSS_CC_IBI_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_IBI_CMD_RCGR_ADDR,v)
#define HWIO_AOSS_CC_IBI_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_IBI_CMD_RCGR_ADDR,m,v,HWIO_AOSS_CC_IBI_CMD_RCGR_IN)
#define HWIO_AOSS_CC_IBI_CMD_RCGR_ROOT_OFF_BMSK                                           0x80000000
#define HWIO_AOSS_CC_IBI_CMD_RCGR_ROOT_OFF_SHFT                                                 0x1f
#define HWIO_AOSS_CC_IBI_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                           0x10
#define HWIO_AOSS_CC_IBI_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                            0x4
#define HWIO_AOSS_CC_IBI_CMD_RCGR_ROOT_EN_BMSK                                                   0x2
#define HWIO_AOSS_CC_IBI_CMD_RCGR_ROOT_EN_SHFT                                                   0x1
#define HWIO_AOSS_CC_IBI_CMD_RCGR_UPDATE_BMSK                                                    0x1
#define HWIO_AOSS_CC_IBI_CMD_RCGR_UPDATE_SHFT                                                    0x0

#define HWIO_AOSS_CC_IBI_CFG_RCGR_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002118)
#define HWIO_AOSS_CC_IBI_CFG_RCGR_RMSK                                                      0x11071f
#define HWIO_AOSS_CC_IBI_CFG_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_IBI_CFG_RCGR_ADDR)
#define HWIO_AOSS_CC_IBI_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_IBI_CFG_RCGR_ADDR, m)
#define HWIO_AOSS_CC_IBI_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_IBI_CFG_RCGR_ADDR,v)
#define HWIO_AOSS_CC_IBI_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_IBI_CFG_RCGR_ADDR,m,v,HWIO_AOSS_CC_IBI_CFG_RCGR_IN)
#define HWIO_AOSS_CC_IBI_CFG_RCGR_HW_CLK_CONTROL_BMSK                                       0x100000
#define HWIO_AOSS_CC_IBI_CFG_RCGR_HW_CLK_CONTROL_SHFT                                           0x14
#define HWIO_AOSS_CC_IBI_CFG_RCGR_RCGLITE_DISABLE_BMSK                                       0x10000
#define HWIO_AOSS_CC_IBI_CFG_RCGR_RCGLITE_DISABLE_SHFT                                          0x10
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_SEL_BMSK                                                 0x700
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_SEL_SHFT                                                   0x8
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_BMSK                                                  0x1f
#define HWIO_AOSS_CC_IBI_CFG_RCGR_SRC_DIV_SHFT                                                   0x0

#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002154)
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_RMSK                                                  0x80000005
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_IBI_CTRL0_CBCR_ADDR)
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_IBI_CTRL0_CBCR_ADDR, m)
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_IBI_CTRL0_CBCR_ADDR,v)
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_IBI_CTRL0_CBCR_ADDR,m,v,HWIO_AOSS_CC_IBI_CTRL0_CBCR_IN)
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_AOSS_CC_IBI_CTRL0_CBCR_CLK_ENABLE_SHFT                                              0x0

#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002158)
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_RMSK                                                  0x80000005
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_IBI_CTRL1_CBCR_ADDR)
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_IBI_CTRL1_CBCR_ADDR, m)
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_IBI_CTRL1_CBCR_ADDR,v)
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_IBI_CTRL1_CBCR_ADDR,m,v,HWIO_AOSS_CC_IBI_CTRL1_CBCR_IN)
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_AOSS_CC_IBI_CTRL1_CBCR_CLK_ENABLE_SHFT                                              0x0

#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000215c)
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_RMSK                                                  0x80000005
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_IBI_CTRL2_CBCR_ADDR)
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_IBI_CTRL2_CBCR_ADDR, m)
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_IBI_CTRL2_CBCR_ADDR,v)
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_IBI_CTRL2_CBCR_ADDR,m,v,HWIO_AOSS_CC_IBI_CTRL2_CBCR_IN)
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_AOSS_CC_IBI_CTRL2_CBCR_CLK_ENABLE_SHFT                                              0x0

#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002160)
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_RMSK                                                  0x80000005
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_IBI_CTRL3_CBCR_ADDR)
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_IBI_CTRL3_CBCR_ADDR, m)
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_IBI_CTRL3_CBCR_ADDR,v)
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_IBI_CTRL3_CBCR_ADDR,m,v,HWIO_AOSS_CC_IBI_CTRL3_CBCR_IN)
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_CLK_OFF_BMSK                                          0x80000000
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_CLK_OFF_SHFT                                                0x1f
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_CLK_ARES_BMSK                                                0x4
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_CLK_ARES_SHFT                                                0x2
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_CLK_ENABLE_BMSK                                              0x1
#define HWIO_AOSS_CC_IBI_CTRL3_CBCR_CLK_ENABLE_SHFT                                              0x0

#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000021a8)
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_RMSK                                                  0x80000013
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_SLEEP_CMD_RCGR_ADDR)
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SLEEP_CMD_RCGR_ADDR, m)
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SLEEP_CMD_RCGR_ADDR,v)
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SLEEP_CMD_RCGR_ADDR,m,v,HWIO_AOSS_CC_SLEEP_CMD_RCGR_IN)
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_ROOT_OFF_BMSK                                         0x80000000
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_ROOT_OFF_SHFT                                               0x1f
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                         0x10
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                          0x4
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_ROOT_EN_BMSK                                                 0x2
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_ROOT_EN_SHFT                                                 0x1
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_UPDATE_BMSK                                                  0x1
#define HWIO_AOSS_CC_SLEEP_CMD_RCGR_UPDATE_SHFT                                                  0x0

#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000021ac)
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_RMSK                                                    0x11071f
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_SLEEP_CFG_RCGR_ADDR)
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SLEEP_CFG_RCGR_ADDR, m)
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SLEEP_CFG_RCGR_ADDR,v)
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SLEEP_CFG_RCGR_ADDR,m,v,HWIO_AOSS_CC_SLEEP_CFG_RCGR_IN)
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_HW_CLK_CONTROL_BMSK                                     0x100000
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_HW_CLK_CONTROL_SHFT                                         0x14
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_RCGLITE_DISABLE_BMSK                                     0x10000
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_RCGLITE_DISABLE_SHFT                                        0x10
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_SEL_BMSK                                               0x700
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_SEL_SHFT                                                 0x8
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_BMSK                                                0x1f
#define HWIO_AOSS_CC_SLEEP_CFG_RCGR_SRC_DIV_SHFT                                                 0x0

#define HWIO_AOSS_CC_SLEEP_CBCR_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000021e8)
#define HWIO_AOSS_CC_SLEEP_CBCR_RMSK                                                      0x80000005
#define HWIO_AOSS_CC_SLEEP_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SLEEP_CBCR_ADDR)
#define HWIO_AOSS_CC_SLEEP_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SLEEP_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SLEEP_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SLEEP_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SLEEP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SLEEP_CBCR_ADDR,m,v,HWIO_AOSS_CC_SLEEP_CBCR_IN)
#define HWIO_AOSS_CC_SLEEP_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_AOSS_CC_SLEEP_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_AOSS_CC_SLEEP_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_AOSS_CC_SLEEP_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_AOSS_CC_SLEEP_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_AOSS_CC_SLEEP_CBCR_CLK_ENABLE_SHFT                                                  0x0

#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002228)
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_RMSK                                                 0x80000005
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_PERIPH_SLP_CBCR_ADDR)
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PERIPH_SLP_CBCR_ADDR, m)
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PERIPH_SLP_CBCR_ADDR,v)
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PERIPH_SLP_CBCR_ADDR,m,v,HWIO_AOSS_CC_PERIPH_SLP_CBCR_IN)
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_CLK_OFF_BMSK                                         0x80000000
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_CLK_OFF_SHFT                                               0x1f
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_CLK_ARES_BMSK                                               0x4
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_CLK_ARES_SHFT                                               0x2
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_CLK_ENABLE_BMSK                                             0x1
#define HWIO_AOSS_CC_PERIPH_SLP_CBCR_CLK_ENABLE_SHFT                                             0x0

#define HWIO_AOSS_CC_SWAO_BCR_ADDR                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000222c)
#define HWIO_AOSS_CC_SWAO_BCR_RMSK                                                               0x1
#define HWIO_AOSS_CC_SWAO_BCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_BCR_ADDR)
#define HWIO_AOSS_CC_SWAO_BCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_BCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_BCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_BCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_BCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_BCR_IN)
#define HWIO_AOSS_CC_SWAO_BCR_BLK_ARES_BMSK                                                      0x1
#define HWIO_AOSS_CC_SWAO_BCR_BLK_ARES_SHFT                                                      0x0

#define HWIO_AOSS_CC_SWAO_GDSCR_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002230)
#define HWIO_AOSS_CC_SWAO_GDSCR_RMSK                                                      0xf8ffffff
#define HWIO_AOSS_CC_SWAO_GDSCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_GDSCR_ADDR)
#define HWIO_AOSS_CC_SWAO_GDSCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_GDSCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_GDSCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_GDSCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_GDSCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_GDSCR_IN)
#define HWIO_AOSS_CC_SWAO_GDSCR_PWR_ON_BMSK                                               0x80000000
#define HWIO_AOSS_CC_SWAO_GDSCR_PWR_ON_SHFT                                                     0x1f
#define HWIO_AOSS_CC_SWAO_GDSCR_GDSC_STATE_BMSK                                           0x78000000
#define HWIO_AOSS_CC_SWAO_GDSCR_GDSC_STATE_SHFT                                                 0x1b
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_REST_WAIT_BMSK                                           0xf00000
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_REST_WAIT_SHFT                                               0x14
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_FEW_WAIT_BMSK                                             0xf0000
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_FEW_WAIT_SHFT                                                0x10
#define HWIO_AOSS_CC_SWAO_GDSCR_CLK_DIS_WAIT_BMSK                                             0xf000
#define HWIO_AOSS_CC_SWAO_GDSCR_CLK_DIS_WAIT_SHFT                                                0xc
#define HWIO_AOSS_CC_SWAO_GDSCR_RETAIN_FF_ENABLE_BMSK                                          0x800
#define HWIO_AOSS_CC_SWAO_GDSCR_RETAIN_FF_ENABLE_SHFT                                            0xb
#define HWIO_AOSS_CC_SWAO_GDSCR_RESTORE_BMSK                                                   0x400
#define HWIO_AOSS_CC_SWAO_GDSCR_RESTORE_SHFT                                                     0xa
#define HWIO_AOSS_CC_SWAO_GDSCR_SAVE_BMSK                                                      0x200
#define HWIO_AOSS_CC_SWAO_GDSCR_SAVE_SHFT                                                        0x9
#define HWIO_AOSS_CC_SWAO_GDSCR_RETAIN_BMSK                                                    0x100
#define HWIO_AOSS_CC_SWAO_GDSCR_RETAIN_SHFT                                                      0x8
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_REST_BMSK                                                    0x80
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_REST_SHFT                                                     0x7
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_FEW_BMSK                                                     0x40
#define HWIO_AOSS_CC_SWAO_GDSCR_EN_FEW_SHFT                                                      0x6
#define HWIO_AOSS_CC_SWAO_GDSCR_CLAMP_IO_BMSK                                                   0x20
#define HWIO_AOSS_CC_SWAO_GDSCR_CLAMP_IO_SHFT                                                    0x5
#define HWIO_AOSS_CC_SWAO_GDSCR_CLK_DISABLE_BMSK                                                0x10
#define HWIO_AOSS_CC_SWAO_GDSCR_CLK_DISABLE_SHFT                                                 0x4
#define HWIO_AOSS_CC_SWAO_GDSCR_PD_ARES_BMSK                                                     0x8
#define HWIO_AOSS_CC_SWAO_GDSCR_PD_ARES_SHFT                                                     0x3
#define HWIO_AOSS_CC_SWAO_GDSCR_SW_OVERRIDE_BMSK                                                 0x4
#define HWIO_AOSS_CC_SWAO_GDSCR_SW_OVERRIDE_SHFT                                                 0x2
#define HWIO_AOSS_CC_SWAO_GDSCR_HW_CONTROL_BMSK                                                  0x2
#define HWIO_AOSS_CC_SWAO_GDSCR_HW_CONTROL_SHFT                                                  0x1
#define HWIO_AOSS_CC_SWAO_GDSCR_SW_COLLAPSE_BMSK                                                 0x1
#define HWIO_AOSS_CC_SWAO_GDSCR_SW_COLLAPSE_SHFT                                                 0x0

#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002234)
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_RMSK                                                  0xffffffff
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_CFG_GDSCR_ADDR)
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_CFG_GDSCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_CFG_GDSCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_CFG_GDSCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_CFG_GDSCR_IN)
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_SPARE_CTRL_IN_BMSK                               0xf0000000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_SPARE_CTRL_IN_SHFT                                     0x1c
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK                               0xc000000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT                                    0x1a
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK                                0x2000000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT                                     0x19
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PWR_UP_START_BMSK                                 0x1000000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PWR_UP_START_SHFT                                      0x18
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK                          0xf00000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT                              0x14
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                             0x80000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                                0x13
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK                                 0x40000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT                                    0x12
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK                                 0x20000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT                                    0x11
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK                              0x10000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT                                 0x10
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                             0x8000
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                                0xf
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                            0x7800
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                               0xb
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK                                    0x400
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT                                      0xa
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                             0x200
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                               0x9
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                             0x100
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                               0x8
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                                 0x80
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                                  0x7
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                        0x60
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                         0x5
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                                  0x10
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                                   0x4
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                            0x8
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                            0x3
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                          0x4
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                          0x2
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                              0x2
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                              0x1
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                           0x1
#define HWIO_AOSS_CC_SWAO_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                           0x0

#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002238)
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_RMSK                                                    0x1ffff
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_CFG2_GDSCR_ADDR)
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_CFG2_GDSCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_CFG2_GDSCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_CFG2_GDSCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_CFG2_GDSCR_IN)
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK                                  0x10000
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT                                     0x10
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK                                      0xf000
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT                                         0xc
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                               0xf00
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                                 0x8
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                                  0xf0
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                                   0x4
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                                    0xf
#define HWIO_AOSS_CC_SWAO_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                                    0x0

#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_ADDR                                            (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000223c)
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_RMSK                                            0x80000005
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_ADDR)
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_IN)
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_CLK_OFF_BMSK                                    0x80000000
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_CLK_OFF_SHFT                                          0x1f
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_CLK_ARES_BMSK                                          0x4
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_CLK_ARES_SHFT                                          0x2
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_CLK_ENABLE_BMSK                                        0x1
#define HWIO_AOSS_CC_SWAO_RPMH_DEBUG_CBCR_CLK_ENABLE_SHFT                                        0x0

#define HWIO_AOSS_CC_SWAO_CBCR_ADDR                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002240)
#define HWIO_AOSS_CC_SWAO_CBCR_RMSK                                                       0x80000005
#define HWIO_AOSS_CC_SWAO_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_CBCR_ADDR)
#define HWIO_AOSS_CC_SWAO_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_CBCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_CBCR_IN)
#define HWIO_AOSS_CC_SWAO_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_AOSS_CC_SWAO_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_AOSS_CC_SWAO_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_AOSS_CC_SWAO_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_AOSS_CC_SWAO_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_AOSS_CC_SWAO_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_AOSS_CC_SWAO_AO_CBCR_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002244)
#define HWIO_AOSS_CC_SWAO_AO_CBCR_RMSK                                                    0x80000005
#define HWIO_AOSS_CC_SWAO_AO_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_AO_CBCR_ADDR)
#define HWIO_AOSS_CC_SWAO_AO_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_AO_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_AO_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_AO_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_AO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_AO_CBCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_AO_CBCR_IN)
#define HWIO_AOSS_CC_SWAO_AO_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_AOSS_CC_SWAO_AO_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_AOSS_CC_SWAO_AO_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_AOSS_CC_SWAO_AO_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_AOSS_CC_SWAO_AO_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_AOSS_CC_SWAO_AO_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_AOSS_CC_SWAO_MEM_CBCR_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002248)
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_RMSK                                                   0x80007ff5
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_MEM_CBCR_ADDR)
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_MEM_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_MEM_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_MEM_CBCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_MEM_CBCR_IN)
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_CORE_ON_BMSK                                     0x4000
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_CORE_ON_SHFT                                        0xe
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_PERIPH_ON_BMSK                                   0x2000
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_PERIPH_ON_SHFT                                      0xd
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_PERIPH_OFF_BMSK                                  0x1000
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_FORCE_MEM_PERIPH_OFF_SHFT                                     0xc
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_BMSK                                                 0xf00
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_WAKEUP_SHFT                                                   0x8
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_BMSK                                                   0xf0
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_SLEEP_SHFT                                                    0x4
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_AOSS_CC_SWAO_MEM_CBCR_CLK_ENABLE_SHFT                                               0x0

#define HWIO_AOSS_CC_SWAO_TS_CBCR_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000224c)
#define HWIO_AOSS_CC_SWAO_TS_CBCR_RMSK                                                    0x80000005
#define HWIO_AOSS_CC_SWAO_TS_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_TS_CBCR_ADDR)
#define HWIO_AOSS_CC_SWAO_TS_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_TS_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_TS_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_TS_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_TS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_TS_CBCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_TS_CBCR_IN)
#define HWIO_AOSS_CC_SWAO_TS_CBCR_CLK_OFF_BMSK                                            0x80000000
#define HWIO_AOSS_CC_SWAO_TS_CBCR_CLK_OFF_SHFT                                                  0x1f
#define HWIO_AOSS_CC_SWAO_TS_CBCR_CLK_ARES_BMSK                                                  0x4
#define HWIO_AOSS_CC_SWAO_TS_CBCR_CLK_ARES_SHFT                                                  0x2
#define HWIO_AOSS_CC_SWAO_TS_CBCR_CLK_ENABLE_BMSK                                                0x1
#define HWIO_AOSS_CC_SWAO_TS_CBCR_CLK_ENABLE_SHFT                                                0x0

#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002250)
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_RMSK                                                 0x80000005
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_TS_AO_CBCR_ADDR)
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_TS_AO_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_TS_AO_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_TS_AO_CBCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_TS_AO_CBCR_IN)
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_CLK_OFF_BMSK                                         0x80000000
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_CLK_OFF_SHFT                                               0x1f
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_CLK_ARES_BMSK                                               0x4
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_CLK_ARES_SHFT                                               0x2
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_CLK_ENABLE_BMSK                                             0x1
#define HWIO_AOSS_CC_SWAO_TS_AO_CBCR_CLK_ENABLE_SHFT                                             0x0

#define HWIO_AOSS_CC_SWAO_BUS_CBCR_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002254)
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_RMSK                                                   0x80000005
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_BUS_CBCR_ADDR)
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_BUS_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_BUS_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_BUS_CBCR_ADDR,m,v,HWIO_AOSS_CC_SWAO_BUS_CBCR_IN)
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_AOSS_CC_SWAO_BUS_CBCR_CLK_ENABLE_SHFT                                               0x0

#define HWIO_AOSS_CC_SWAO_CMD_RCGR_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002258)
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_RMSK                                                   0x80000013
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_CMD_RCGR_ADDR)
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_CMD_RCGR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_CMD_RCGR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_CMD_RCGR_ADDR,m,v,HWIO_AOSS_CC_SWAO_CMD_RCGR_IN)
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_ROOT_OFF_BMSK                                          0x80000000
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_ROOT_OFF_SHFT                                                0x1f
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                          0x10
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                           0x4
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_ROOT_EN_BMSK                                                  0x2
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_ROOT_EN_SHFT                                                  0x1
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_UPDATE_BMSK                                                   0x1
#define HWIO_AOSS_CC_SWAO_CMD_RCGR_UPDATE_SHFT                                                   0x0

#define HWIO_AOSS_CC_SWAO_CFG_RCGR_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000225c)
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_RMSK                                                     0x11071f
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_CFG_RCGR_ADDR)
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_CFG_RCGR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_CFG_RCGR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_CFG_RCGR_ADDR,m,v,HWIO_AOSS_CC_SWAO_CFG_RCGR_IN)
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_HW_CLK_CONTROL_BMSK                                      0x100000
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_HW_CLK_CONTROL_SHFT                                          0x14
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_RCGLITE_DISABLE_BMSK                                      0x10000
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_RCGLITE_DISABLE_SHFT                                         0x10
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_SEL_BMSK                                                0x700
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_SEL_SHFT                                                  0x8
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_BMSK                                                 0x1f
#define HWIO_AOSS_CC_SWAO_CFG_RCGR_SRC_DIV_SHFT                                                  0x0

#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002298)
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_RMSK                                                0x80000013
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ADDR)
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ADDR,m,v,HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_IN)
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ROOT_OFF_BMSK                                       0x80000000
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ROOT_OFF_SHFT                                             0x1f
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                       0x10
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                        0x4
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ROOT_EN_BMSK                                               0x2
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_ROOT_EN_SHFT                                               0x1
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_UPDATE_BMSK                                                0x1
#define HWIO_AOSS_CC_SWAO_TS_CMD_RCGR_UPDATE_SHFT                                                0x0

#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000229c)
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_RMSK                                                  0x11071f
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_ADDR)
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_ADDR, m)
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_ADDR,v)
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_ADDR,m,v,HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_IN)
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_HW_CLK_CONTROL_BMSK                                   0x100000
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_HW_CLK_CONTROL_SHFT                                       0x14
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_RCGLITE_DISABLE_BMSK                                   0x10000
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_RCGLITE_DISABLE_SHFT                                      0x10
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_SEL_BMSK                                             0x700
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_SEL_SHFT                                               0x8
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_BMSK                                              0x1f
#define HWIO_AOSS_CC_SWAO_TS_CFG_RCGR_SRC_DIV_SHFT                                               0x0

#define HWIO_AOSS_CC_SPMI_BCR_ADDR                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000022d8)
#define HWIO_AOSS_CC_SPMI_BCR_RMSK                                                               0x1
#define HWIO_AOSS_CC_SPMI_BCR_IN          \
        in_dword(HWIO_AOSS_CC_SPMI_BCR_ADDR)
#define HWIO_AOSS_CC_SPMI_BCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPMI_BCR_ADDR, m)
#define HWIO_AOSS_CC_SPMI_BCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPMI_BCR_ADDR,v)
#define HWIO_AOSS_CC_SPMI_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPMI_BCR_ADDR,m,v,HWIO_AOSS_CC_SPMI_BCR_IN)
#define HWIO_AOSS_CC_SPMI_BCR_BLK_ARES_BMSK                                                      0x1
#define HWIO_AOSS_CC_SPMI_BCR_BLK_ARES_SHFT                                                      0x0

#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_ADDR                                               (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000022dc)
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_RMSK                                               0x80000005
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_ADDR)
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_ADDR,m,v,HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_IN)
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_CLK_OFF_BMSK                                       0x80000000
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_CLK_OFF_SHFT                                             0x1f
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_CLK_ARES_BMSK                                             0x4
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_CLK_ARES_SHFT                                             0x2
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_CLK_ENABLE_BMSK                                           0x1
#define HWIO_AOSS_CC_SPMI_CFG_AHB_CBCR_CLK_ENABLE_SHFT                                           0x0

#define HWIO_AOSS_CC_SPMI_SER_CBCR_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000022e0)
#define HWIO_AOSS_CC_SPMI_SER_CBCR_RMSK                                                   0x80000005
#define HWIO_AOSS_CC_SPMI_SER_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SPMI_SER_CBCR_ADDR)
#define HWIO_AOSS_CC_SPMI_SER_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPMI_SER_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SPMI_SER_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPMI_SER_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SPMI_SER_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPMI_SER_CBCR_ADDR,m,v,HWIO_AOSS_CC_SPMI_SER_CBCR_IN)
#define HWIO_AOSS_CC_SPMI_SER_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_AOSS_CC_SPMI_SER_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_AOSS_CC_SPMI_SER_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_AOSS_CC_SPMI_SER_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_AOSS_CC_SPMI_SER_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_AOSS_CC_SPMI_SER_CBCR_CLK_ENABLE_SHFT                                               0x0

#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_ADDR                                               (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000022e4)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_RMSK                                               0x80000005
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_ADDR)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_ADDR, m)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_ADDR,v)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_ADDR,m,v,HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_IN)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_CLK_OFF_BMSK                                       0x80000000
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_CLK_OFF_SHFT                                             0x1f
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_CLK_ARES_BMSK                                             0x4
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_CLK_ARES_SHFT                                             0x2
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_CLK_ENABLE_BMSK                                           0x1
#define HWIO_AOSS_CC_SPMI_AOD_SER_CBCR_CLK_ENABLE_SHFT                                           0x0

#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ADDR                                           (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000022e8)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_RMSK                                           0x80000013
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ADDR)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ADDR, m)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ADDR,v)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ADDR,m,v,HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_IN)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ROOT_OFF_BMSK                                  0x80000000
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ROOT_OFF_SHFT                                        0x1f
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_DIRTY_CFG_RCGR_BMSK                                  0x10
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_DIRTY_CFG_RCGR_SHFT                                   0x4
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ROOT_EN_BMSK                                          0x2
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_ROOT_EN_SHFT                                          0x1
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_UPDATE_BMSK                                           0x1
#define HWIO_AOSS_CC_SPMI_AOD_SER_CMD_RCGR_UPDATE_SHFT                                           0x0

#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_ADDR                                           (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000022ec)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_RMSK                                             0x11071f
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_IN          \
        in_dword(HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_ADDR)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_ADDR, m)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_ADDR,v)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_ADDR,m,v,HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_IN)
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_HW_CLK_CONTROL_BMSK                              0x100000
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_HW_CLK_CONTROL_SHFT                                  0x14
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_RCGLITE_DISABLE_BMSK                              0x10000
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_RCGLITE_DISABLE_SHFT                                 0x10
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_SEL_BMSK                                        0x700
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_SEL_SHFT                                          0x8
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_BMSK                                         0x1f
#define HWIO_AOSS_CC_SPMI_AOD_SER_CFG_RCGR_SRC_DIV_SHFT                                          0x0

#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002328)
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_RMSK                                                        0x1
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_IN          \
        in_dword(HWIO_AOSS_CC_GLOBAL_CNTR_BCR_ADDR)
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_GLOBAL_CNTR_BCR_ADDR, m)
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_GLOBAL_CNTR_BCR_ADDR,v)
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_GLOBAL_CNTR_BCR_ADDR,m,v,HWIO_AOSS_CC_GLOBAL_CNTR_BCR_IN)
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_BLK_ARES_BMSK                                               0x1
#define HWIO_AOSS_CC_GLOBAL_CNTR_BCR_BLK_ARES_SHFT                                               0x0

#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002340)
#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_RMSK                                                        0x3
#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_IN          \
        in_dword(HWIO_AOSS_CC_DEBUG_DIV_CDIVR_ADDR)
#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_DEBUG_DIV_CDIVR_ADDR, m)
#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_DEBUG_DIV_CDIVR_ADDR,v)
#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_DEBUG_DIV_CDIVR_ADDR,m,v,HWIO_AOSS_CC_DEBUG_DIV_CDIVR_IN)
#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_CLK_DIV_BMSK                                                0x3
#define HWIO_AOSS_CC_DEBUG_DIV_CDIVR_CLK_DIV_SHFT                                                0x0

#define HWIO_AOSS_CC_DEBUG_CBCR_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002344)
#define HWIO_AOSS_CC_DEBUG_CBCR_RMSK                                                      0x80000005
#define HWIO_AOSS_CC_DEBUG_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_DEBUG_CBCR_ADDR)
#define HWIO_AOSS_CC_DEBUG_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_DEBUG_CBCR_ADDR, m)
#define HWIO_AOSS_CC_DEBUG_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_DEBUG_CBCR_ADDR,v)
#define HWIO_AOSS_CC_DEBUG_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_DEBUG_CBCR_ADDR,m,v,HWIO_AOSS_CC_DEBUG_CBCR_IN)
#define HWIO_AOSS_CC_DEBUG_CBCR_CLK_OFF_BMSK                                              0x80000000
#define HWIO_AOSS_CC_DEBUG_CBCR_CLK_OFF_SHFT                                                    0x1f
#define HWIO_AOSS_CC_DEBUG_CBCR_CLK_ARES_BMSK                                                    0x4
#define HWIO_AOSS_CC_DEBUG_CBCR_CLK_ARES_SHFT                                                    0x2
#define HWIO_AOSS_CC_DEBUG_CBCR_CLK_ENABLE_BMSK                                                  0x1
#define HWIO_AOSS_CC_DEBUG_CBCR_CLK_ENABLE_SHFT                                                  0x0

#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_ADDR                                              (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000234c)
#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_RMSK                                                     0x3
#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_IN          \
        in_dword(HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_ADDR)
#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_ADDR, m)
#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_ADDR,v)
#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_ADDR,m,v,HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_IN)
#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_CLK_DIV_BMSK                                             0x3
#define HWIO_AOSS_CC_PLL_TEST_DIV_CDIVR_CLK_DIV_SHFT                                             0x0

#define HWIO_AOSS_CC_PLL_TEST_CBCR_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002350)
#define HWIO_AOSS_CC_PLL_TEST_CBCR_RMSK                                                   0x80000005
#define HWIO_AOSS_CC_PLL_TEST_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_PLL_TEST_CBCR_ADDR)
#define HWIO_AOSS_CC_PLL_TEST_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL_TEST_CBCR_ADDR, m)
#define HWIO_AOSS_CC_PLL_TEST_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL_TEST_CBCR_ADDR,v)
#define HWIO_AOSS_CC_PLL_TEST_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL_TEST_CBCR_ADDR,m,v,HWIO_AOSS_CC_PLL_TEST_CBCR_IN)
#define HWIO_AOSS_CC_PLL_TEST_CBCR_CLK_OFF_BMSK                                           0x80000000
#define HWIO_AOSS_CC_PLL_TEST_CBCR_CLK_OFF_SHFT                                                 0x1f
#define HWIO_AOSS_CC_PLL_TEST_CBCR_CLK_ARES_BMSK                                                 0x4
#define HWIO_AOSS_CC_PLL_TEST_CBCR_CLK_ARES_SHFT                                                 0x2
#define HWIO_AOSS_CC_PLL_TEST_CBCR_CLK_ENABLE_BMSK                                               0x1
#define HWIO_AOSS_CC_PLL_TEST_CBCR_CLK_ENABLE_SHFT                                               0x0

#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002354)
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_RMSK                                                         0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_IN          \
        in_dword(HWIO_AOSS_CC_RPMH_ACCEL_BCR_ADDR)
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RPMH_ACCEL_BCR_ADDR, m)
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RPMH_ACCEL_BCR_ADDR,v)
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RPMH_ACCEL_BCR_ADDR,m,v,HWIO_AOSS_CC_RPMH_ACCEL_BCR_IN)
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_BLK_ARES_BMSK                                                0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_BCR_BLK_ARES_SHFT                                                0x0

#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002358)
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RMSK                                                0xf8ffffff
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_IN          \
        in_dword(HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_ADDR)
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_ADDR, m)
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_ADDR,v)
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_ADDR,m,v,HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_IN)
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_PWR_ON_BMSK                                         0x80000000
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_PWR_ON_SHFT                                               0x1f
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_GDSC_STATE_BMSK                                     0x78000000
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_GDSC_STATE_SHFT                                           0x1b
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_REST_WAIT_BMSK                                     0xf00000
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_REST_WAIT_SHFT                                         0x14
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_FEW_WAIT_BMSK                                       0xf0000
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_FEW_WAIT_SHFT                                          0x10
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_CLK_DIS_WAIT_BMSK                                       0xf000
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_CLK_DIS_WAIT_SHFT                                          0xc
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RETAIN_FF_ENABLE_BMSK                                    0x800
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RETAIN_FF_ENABLE_SHFT                                      0xb
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RESTORE_BMSK                                             0x400
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RESTORE_SHFT                                               0xa
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SAVE_BMSK                                                0x200
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SAVE_SHFT                                                  0x9
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RETAIN_BMSK                                              0x100
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_RETAIN_SHFT                                                0x8
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_REST_BMSK                                              0x80
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_REST_SHFT                                               0x7
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_FEW_BMSK                                               0x40
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_EN_FEW_SHFT                                                0x6
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_CLAMP_IO_BMSK                                             0x20
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_CLAMP_IO_SHFT                                              0x5
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_CLK_DISABLE_BMSK                                          0x10
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_CLK_DISABLE_SHFT                                           0x4
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_PD_ARES_BMSK                                               0x8
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_PD_ARES_SHFT                                               0x3
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SW_OVERRIDE_BMSK                                           0x4
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SW_OVERRIDE_SHFT                                           0x2
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_HW_CONTROL_BMSK                                            0x2
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_HW_CONTROL_SHFT                                            0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SW_COLLAPSE_BMSK                                           0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_GDSCR_SW_COLLAPSE_SHFT                                           0x0

#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_ADDR                                            (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000235c)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_RMSK                                            0xffffffff
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_IN          \
        in_dword(HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_ADDR)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_ADDR, m)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_ADDR,v)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_ADDR,m,v,HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_IN)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_SPARE_CTRL_IN_BMSK                         0xf0000000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_SPARE_CTRL_IN_SHFT                               0x1c
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_BMSK                         0xc000000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_SPARE_CTRL_OUT_SHFT                              0x1a
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PWR_DWN_START_BMSK                          0x2000000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PWR_DWN_START_SHFT                               0x19
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PWR_UP_START_BMSK                           0x1000000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PWR_UP_START_SHFT                                0x18
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_BMSK                    0xf00000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_CFG_FSM_STATE_STATUS_SHFT                        0x14
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_BMSK                       0x80000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_MEM_PWR_ACK_STATUS_SHFT                          0x13
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_ENR_ACK_STATUS_BMSK                           0x40000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_ENR_ACK_STATUS_SHFT                              0x12
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_ENF_ACK_STATUS_BMSK                           0x20000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_ENF_ACK_STATUS_SHFT                              0x11
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_BMSK                        0x10000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_POWER_UP_COMPLETE_SHFT                           0x10
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_BMSK                       0x8000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_POWER_DOWN_COMPLETE_SHFT                          0xf
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_BMSK                      0x7800
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_SOFTWARE_CONTROL_OVERRIDE_SHFT                         0xb
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_HANDSHAKE_DIS_BMSK                              0x400
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_HANDSHAKE_DIS_SHFT                                0xa
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_BMSK                       0x200
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_MEM_PERI_FORCE_IN_SW_SHFT                         0x9
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_BMSK                       0x100
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_MEM_CORE_FORCE_IN_SW_SHFT                         0x8
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_BMSK                           0x80
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PHASE_RESET_EN_SW_SHFT                            0x7
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_BMSK                  0x60
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PHASE_RESET_DELAY_COUNT_SW_SHFT                   0x5
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_BMSK                            0x10
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_GDSC_PSCBC_PWR_DWN_SW_SHFT                             0x4
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_BMSK                      0x8
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_UNCLAMP_IO_SOFTWARE_OVERRIDE_SHFT                      0x3
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_BMSK                    0x4
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_SAVE_RESTORE_SOFTWARE_OVERRIDE_SHFT                    0x2
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_BMSK                        0x2
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_CLAMP_IO_SOFTWARE_OVERRIDE_SHFT                        0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_BMSK                     0x1
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG_GDSCR_DISABLE_CLK_SOFTWARE_OVERRIDE_SHFT                     0x0

#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_ADDR                                           (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002360)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_RMSK                                              0x1ffff
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_IN          \
        in_dword(HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_ADDR)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_ADDR, m)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_ADDR,v)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_ADDR,m,v,HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_IN)
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_BMSK                            0x10000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_GDSC_CLAMP_MEM_SW_SHFT                               0x10
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_DLY_MEM_PWR_UP_BMSK                                0xf000
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_DLY_MEM_PWR_UP_SHFT                                   0xc
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_BMSK                         0xf00
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_DLY_DEASSERT_CLAMP_MEM_SHFT                           0x8
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_BMSK                            0xf0
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_DLY_ASSERT_CLAMP_MEM_SHFT                             0x4
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_BMSK                              0xf
#define HWIO_AOSS_CC_RPMH_ACCEL_CFG2_GDSCR_MEM_PWR_DWN_TIMEOUT_SHFT                              0x0

#define HWIO_AOSS_CC_RPMH_CBCR_ADDR                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00002364)
#define HWIO_AOSS_CC_RPMH_CBCR_RMSK                                                       0x80000005
#define HWIO_AOSS_CC_RPMH_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_RPMH_CBCR_ADDR)
#define HWIO_AOSS_CC_RPMH_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RPMH_CBCR_ADDR, m)
#define HWIO_AOSS_CC_RPMH_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RPMH_CBCR_ADDR,v)
#define HWIO_AOSS_CC_RPMH_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RPMH_CBCR_ADDR,m,v,HWIO_AOSS_CC_RPMH_CBCR_IN)
#define HWIO_AOSS_CC_RPMH_CBCR_CLK_OFF_BMSK                                               0x80000000
#define HWIO_AOSS_CC_RPMH_CBCR_CLK_OFF_SHFT                                                     0x1f
#define HWIO_AOSS_CC_RPMH_CBCR_CLK_ARES_BMSK                                                     0x4
#define HWIO_AOSS_CC_RPMH_CBCR_CLK_ARES_SHFT                                                     0x2
#define HWIO_AOSS_CC_RPMH_CBCR_CLK_ENABLE_BMSK                                                   0x1
#define HWIO_AOSS_CC_RPMH_CBCR_CLK_ENABLE_SHFT                                                   0x0

#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_ADDR                                           (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x000023a4)
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_RMSK                                           0x80000005
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_IN          \
        in_dword(HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_ADDR)
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_ADDR, m)
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_ADDR,v)
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_ADDR,m,v,HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_IN)
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_CLK_OFF_BMSK                                   0x80000000
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_CLK_OFF_SHFT                                         0x1f
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_CLK_ARES_BMSK                                         0x4
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_CLK_ARES_SHFT                                         0x2
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_CLK_ENABLE_BMSK                                       0x1
#define HWIO_AOSS_CC_RPMH_GLOBAL_CNTR_CBCR_CLK_ENABLE_SHFT                                       0x0

#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003004)
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_RMSK                                                        0xff
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_IN          \
        in_dword(HWIO_AOSS_CC_DEBUG_MUX_MUXR_ADDR)
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_DEBUG_MUX_MUXR_ADDR, m)
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_DEBUG_MUX_MUXR_ADDR,v)
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_DEBUG_MUX_MUXR_ADDR,m,v,HWIO_AOSS_CC_DEBUG_MUX_MUXR_IN)
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_BMSK                                                0xff
#define HWIO_AOSS_CC_DEBUG_MUX_MUXR_MUX_SEL_SHFT                                                 0x0

#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_ADDR                                               (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003008)
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_RMSK                                                      0x7
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_IN          \
        in_dword(HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_ADDR)
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_ADDR, m)
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_ADDR,v)
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_ADDR,m,v,HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_IN)
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_MUX_SEL_BMSK                                              0x7
#define HWIO_AOSS_CC_PLL_TEST_MUX_MUXR_MUX_SEL_SHFT                                              0x0

#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000300c)
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_RMSK                                                       0x7
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_IN          \
        in_dword(HWIO_AOSS_CC_PLL_RESET_N_MUXR_ADDR)
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL_RESET_N_MUXR_ADDR, m)
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL_RESET_N_MUXR_ADDR,v)
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL_RESET_N_MUXR_ADDR,m,v,HWIO_AOSS_CC_PLL_RESET_N_MUXR_IN)
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_MUX_SEL_BMSK                                               0x7
#define HWIO_AOSS_CC_PLL_RESET_N_MUXR_MUX_SEL_SHFT                                               0x0

#define HWIO_AOSS_CC_PLL_STATUS_MUXR_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003010)
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_RMSK                                                        0x7
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_IN          \
        in_dword(HWIO_AOSS_CC_PLL_STATUS_MUXR_ADDR)
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL_STATUS_MUXR_ADDR, m)
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL_STATUS_MUXR_ADDR,v)
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL_STATUS_MUXR_ADDR,m,v,HWIO_AOSS_CC_PLL_STATUS_MUXR_IN)
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_MUX_SEL_BMSK                                                0x7
#define HWIO_AOSS_CC_PLL_STATUS_MUXR_MUX_SEL_SHFT                                                0x0

#define HWIO_AOSS_CC_PLL_CLK_SEL_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003014)
#define HWIO_AOSS_CC_PLL_CLK_SEL_RMSK                                                            0x7
#define HWIO_AOSS_CC_PLL_CLK_SEL_IN          \
        in_dword(HWIO_AOSS_CC_PLL_CLK_SEL_ADDR)
#define HWIO_AOSS_CC_PLL_CLK_SEL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL_CLK_SEL_ADDR, m)
#define HWIO_AOSS_CC_PLL_CLK_SEL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL_CLK_SEL_ADDR,v)
#define HWIO_AOSS_CC_PLL_CLK_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL_CLK_SEL_ADDR,m,v,HWIO_AOSS_CC_PLL_CLK_SEL_IN)
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL1_CLK_REF_SEL_BMSK                                           0x4
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL1_CLK_REF_SEL_SHFT                                           0x2
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL1_CLK_XO_SEL_BMSK                                            0x2
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL1_CLK_XO_SEL_SHFT                                            0x1
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL0_CLK_REF_SEL_BMSK                                           0x1
#define HWIO_AOSS_CC_PLL_CLK_SEL_PLL0_CLK_REF_SEL_SHFT                                           0x0

#define HWIO_AOSS_CC_CDBGPWRUPREQ_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003018)
#define HWIO_AOSS_CC_CDBGPWRUPREQ_RMSK                                                    0x80000001
#define HWIO_AOSS_CC_CDBGPWRUPREQ_IN          \
        in_dword(HWIO_AOSS_CC_CDBGPWRUPREQ_ADDR)
#define HWIO_AOSS_CC_CDBGPWRUPREQ_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_CDBGPWRUPREQ_ADDR, m)
#define HWIO_AOSS_CC_CDBGPWRUPREQ_OUT(v)      \
        out_dword(HWIO_AOSS_CC_CDBGPWRUPREQ_ADDR,v)
#define HWIO_AOSS_CC_CDBGPWRUPREQ_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_CDBGPWRUPREQ_ADDR,m,v,HWIO_AOSS_CC_CDBGPWRUPREQ_IN)
#define HWIO_AOSS_CC_CDBGPWRUPREQ_STATUS_BMSK                                             0x80000000
#define HWIO_AOSS_CC_CDBGPWRUPREQ_STATUS_SHFT                                                   0x1f
#define HWIO_AOSS_CC_CDBGPWRUPREQ_REQ_BMSK                                                       0x1
#define HWIO_AOSS_CC_CDBGPWRUPREQ_REQ_SHFT                                                       0x0

#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ADDR                                              (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050000)
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_RMSK                                                  0x3fff
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_IN          \
        in_dword(HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ADDR)
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ADDR, m)
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ADDR,v)
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ADDR,m,v,HWIO_AOSS_CC_RESET_DEBUG_ENABLE_IN)
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PCIE_RESET_SEP_EN_BMSK                                0x2000
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PCIE_RESET_SEP_EN_SHFT                                   0xd
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_SW_BASED_PRE_ARES_BMSK                                0x1000
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_SW_BASED_PRE_ARES_SHFT                                   0xc
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ALLOW_SW_BASED_RST_DBG_EN_BMSK                         0x800
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ALLOW_SW_BASED_RST_DBG_EN_SHFT                           0xb
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PRE_SW_SRST_TMR_EN_BMSK                                0x400
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PRE_SW_SRST_TMR_EN_SHFT                                  0xa
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_EUD_T32_SRST_EN_BMSK                                   0x200
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_EUD_T32_SRST_EN_SHFT                                     0x9
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_EUD_RESET_SECOND_PASS_EN_BMSK                          0x100
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_EUD_RESET_SECOND_PASS_EN_SHFT                            0x8
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_DISABLE_APCS_ALT_ARES_BMSK                              0x80
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_DISABLE_APCS_ALT_ARES_SHFT                               0x7
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_SECURE_WDOG_RESET_DEBUG_EN_BMSK                         0x40
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_SECURE_WDOG_RESET_DEBUG_EN_SHFT                          0x6
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_MSM_TSENSE_RESET_DEBUG_EN_BMSK                          0x20
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_MSM_TSENSE_RESET_DEBUG_EN_SHFT                           0x5
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PMIC_RESIN_RESET_DEBUG_EN_BMSK                          0x10
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PMIC_RESIN_RESET_DEBUG_EN_SHFT                           0x4
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PROC_HALT_EN_BMSK                                        0x8
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_PROC_HALT_EN_SHFT                                        0x3
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_AUTO_PS_HOLD_SET_EN_BMSK                                 0x4
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_AUTO_PS_HOLD_SET_EN_SHFT                                 0x2
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ACCESS_RESET_FIRST_PASS_EN_BMSK                          0x2
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_ACCESS_RESET_FIRST_PASS_EN_SHFT                          0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_DEBUG_RESET_FIRST_PASS_EN_BMSK                           0x1
#define HWIO_AOSS_CC_RESET_DEBUG_ENABLE_DEBUG_RESET_FIRST_PASS_EN_SHFT                           0x0

#define HWIO_AOSS_CC_RESET_FSM_CTRL_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050004)
#define HWIO_AOSS_CC_RESET_FSM_CTRL_RMSK                                                        0x7f
#define HWIO_AOSS_CC_RESET_FSM_CTRL_IN          \
        in_dword(HWIO_AOSS_CC_RESET_FSM_CTRL_ADDR)
#define HWIO_AOSS_CC_RESET_FSM_CTRL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RESET_FSM_CTRL_ADDR, m)
#define HWIO_AOSS_CC_RESET_FSM_CTRL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RESET_FSM_CTRL_ADDR,v)
#define HWIO_AOSS_CC_RESET_FSM_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RESET_FSM_CTRL_ADDR,m,v,HWIO_AOSS_CC_RESET_FSM_CTRL_IN)
#define HWIO_AOSS_CC_RESET_FSM_CTRL_BLOCK_PCIE_ARES_BMSK                                        0x40
#define HWIO_AOSS_CC_RESET_FSM_CTRL_BLOCK_PCIE_ARES_SHFT                                         0x6
#define HWIO_AOSS_CC_RESET_FSM_CTRL_PCIE_LINK_TMR_EN_BMSK                                       0x20
#define HWIO_AOSS_CC_RESET_FSM_CTRL_PCIE_LINK_TMR_EN_SHFT                                        0x5
#define HWIO_AOSS_CC_RESET_FSM_CTRL_WKUP_TMR_EN_BMSK                                            0x10
#define HWIO_AOSS_CC_RESET_FSM_CTRL_WKUP_TMR_EN_SHFT                                             0x4
#define HWIO_AOSS_CC_RESET_FSM_CTRL_NORMAL_WKUP_EN_BMSK                                          0x8
#define HWIO_AOSS_CC_RESET_FSM_CTRL_NORMAL_WKUP_EN_SHFT                                          0x3
#define HWIO_AOSS_CC_RESET_FSM_CTRL_FIRST_PASS_TMR_EN_BMSK                                       0x4
#define HWIO_AOSS_CC_RESET_FSM_CTRL_FIRST_PASS_TMR_EN_SHFT                                       0x2
#define HWIO_AOSS_CC_RESET_FSM_CTRL_FIRST_PASS_COMPLETE_BMSK                                     0x2
#define HWIO_AOSS_CC_RESET_FSM_CTRL_FIRST_PASS_COMPLETE_SHFT                                     0x1
#define HWIO_AOSS_CC_RESET_FSM_CTRL_BLOCK_RESIN_BMSK                                             0x1
#define HWIO_AOSS_CC_RESET_FSM_CTRL_BLOCK_RESIN_SHFT                                             0x0

#define HWIO_AOSS_CC_WIND_DOWN_TIMER_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050008)
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_RMSK                                                 0xffffffff
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_IN          \
        in_dword(HWIO_AOSS_CC_WIND_DOWN_TIMER_ADDR)
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_WIND_DOWN_TIMER_ADDR, m)
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_OUT(v)      \
        out_dword(HWIO_AOSS_CC_WIND_DOWN_TIMER_ADDR,v)
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_WIND_DOWN_TIMER_ADDR,m,v,HWIO_AOSS_CC_WIND_DOWN_TIMER_IN)
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_RESERVE_BITS31_16_BMSK                               0xffff0000
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_RESERVE_BITS31_16_SHFT                                     0x10
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_TIMER_VAL_BMSK                                           0xffff
#define HWIO_AOSS_CC_WIND_DOWN_TIMER_TIMER_VAL_SHFT                                              0x0

#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_ADDR                                             (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0005000c)
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_RMSK                                             0xffffffff
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_IN          \
        in_dword(HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_ADDR)
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_ADDR, m)
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_ADDR,v)
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_ADDR,m,v,HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_IN)
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_RESERVE_BITS31_16_BMSK                           0xffff0000
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_RESERVE_BITS31_16_SHFT                                 0x10
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_TIMER_VAL_BMSK                                       0xffff
#define HWIO_AOSS_CC_SAVE_CONTENTS_TIMER_TIMER_VAL_SHFT                                          0x0

#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_ADDR                                              (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050010)
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_RMSK                                              0xffffffff
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_IN          \
        in_dword(HWIO_AOSS_CC_STOP_CAPTURE_TIMER_ADDR)
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_STOP_CAPTURE_TIMER_ADDR, m)
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_OUT(v)      \
        out_dword(HWIO_AOSS_CC_STOP_CAPTURE_TIMER_ADDR,v)
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_STOP_CAPTURE_TIMER_ADDR,m,v,HWIO_AOSS_CC_STOP_CAPTURE_TIMER_IN)
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_RESERVE_BITS31_16_BMSK                            0xffff0000
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_RESERVE_BITS31_16_SHFT                                  0x10
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_TIMER_VAL_BMSK                                        0xffff
#define HWIO_AOSS_CC_STOP_CAPTURE_TIMER_TIMER_VAL_SHFT                                           0x0

#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_ADDR                                         (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050014)
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_RMSK                                         0xffffffff
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_IN          \
        in_dword(HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_ADDR)
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_ADDR, m)
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_ADDR,v)
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_ADDR,m,v,HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_IN)
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_RESERVE_BITS31_16_BMSK                       0xffff0000
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_RESERVE_BITS31_16_SHFT                             0x10
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_TIMER_VAL_BMSK                                   0xffff
#define HWIO_AOSS_CC_PREPARE_FOR_RESET_TIMER_TIMER_VAL_SHFT                                      0x0

#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_ADDR                                              (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050018)
#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_RMSK                                              0xffffffff
#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_IN          \
        in_dword(HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_ADDR)
#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_ADDR, m)
#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_OUT(v)      \
        out_dword(HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_ADDR,v)
#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_ADDR,m,v,HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_IN)
#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_TIMER_VAL_BMSK                                    0xffffffff
#define HWIO_AOSS_CC_FIRST_PASS_TIMEOUT_TIMER_VAL_SHFT                                           0x0

#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_ADDR                                             (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0005001c)
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_RMSK                                             0xffffffff
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_IN          \
        in_dword(HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_ADDR)
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_ADDR, m)
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_ADDR,v)
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_ADDR,m,v,HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_IN)
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_RESERVE_BITS31_8_BMSK                            0xffffff00
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_RESERVE_BITS31_8_SHFT                                   0x8
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_TIMER_VAL_BMSK                                         0xff
#define HWIO_AOSS_CC_PRE_SW_SRST_TIMEOUT_TIMER_VAL_SHFT                                          0x0

#define HWIO_AOSS_CC_RESET_STATUS_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050020)
#define HWIO_AOSS_CC_RESET_STATUS_RMSK                                                        0x3fff
#define HWIO_AOSS_CC_RESET_STATUS_IN          \
        in_dword(HWIO_AOSS_CC_RESET_STATUS_ADDR)
#define HWIO_AOSS_CC_RESET_STATUS_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RESET_STATUS_ADDR, m)
#define HWIO_AOSS_CC_RESET_STATUS_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RESET_STATUS_ADDR,v)
#define HWIO_AOSS_CC_RESET_STATUS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RESET_STATUS_ADDR,m,v,HWIO_AOSS_CC_RESET_STATUS_IN)
#define HWIO_AOSS_CC_RESET_STATUS_PCIE_MIMO_BASED_RESET_STATUS_BMSK                           0x2000
#define HWIO_AOSS_CC_RESET_STATUS_PCIE_MIMO_BASED_RESET_STATUS_SHFT                              0xd
#define HWIO_AOSS_CC_RESET_STATUS_PERST_TIMEOUT_RESET_STATUS_BMSK                             0x1000
#define HWIO_AOSS_CC_RESET_STATUS_PERST_TIMEOUT_RESET_STATUS_SHFT                                0xc
#define HWIO_AOSS_CC_RESET_STATUS_PERST_RAW_RESET_STATUS_BMSK                                  0x800
#define HWIO_AOSS_CC_RESET_STATUS_PERST_RAW_RESET_STATUS_SHFT                                    0xb
#define HWIO_AOSS_CC_RESET_STATUS_PERST_RESET_STATUS_BMSK                                      0x400
#define HWIO_AOSS_CC_RESET_STATUS_PERST_RESET_STATUS_SHFT                                        0xa
#define HWIO_AOSS_CC_RESET_STATUS_PS_HOLD_STATUS_BMSK                                          0x200
#define HWIO_AOSS_CC_RESET_STATUS_PS_HOLD_STATUS_SHFT                                            0x9
#define HWIO_AOSS_CC_RESET_STATUS_QDSS_SW_SRST_RESET_STATUS_BMSK                               0x100
#define HWIO_AOSS_CC_RESET_STATUS_QDSS_SW_SRST_RESET_STATUS_SHFT                                 0x8
#define HWIO_AOSS_CC_RESET_STATUS_EUD_SRST_RESET_STATUS_BMSK                                    0x80
#define HWIO_AOSS_CC_RESET_STATUS_EUD_SRST_RESET_STATUS_SHFT                                     0x7
#define HWIO_AOSS_CC_RESET_STATUS_PMIC_ABNORMAL_RESIN_RESET_STATUS_BMSK                         0x40
#define HWIO_AOSS_CC_RESET_STATUS_PMIC_ABNORMAL_RESIN_RESET_STATUS_SHFT                          0x6
#define HWIO_AOSS_CC_RESET_STATUS_MSM_TSENSE1_RESET_STATUS_BMSK                                 0x20
#define HWIO_AOSS_CC_RESET_STATUS_MSM_TSENSE1_RESET_STATUS_SHFT                                  0x5
#define HWIO_AOSS_CC_RESET_STATUS_PROC_HALT_CTI_STATUS_BMSK                                     0x10
#define HWIO_AOSS_CC_RESET_STATUS_PROC_HALT_CTI_STATUS_SHFT                                      0x4
#define HWIO_AOSS_CC_RESET_STATUS_SRST_RESET_STATUS_BMSK                                         0x8
#define HWIO_AOSS_CC_RESET_STATUS_SRST_RESET_STATUS_SHFT                                         0x3
#define HWIO_AOSS_CC_RESET_STATUS_MSM_TSENSE0_RESET_STATUS_BMSK                                  0x4
#define HWIO_AOSS_CC_RESET_STATUS_MSM_TSENSE0_RESET_STATUS_SHFT                                  0x2
#define HWIO_AOSS_CC_RESET_STATUS_PMIC_RESIN_RESET_STATUS_BMSK                                   0x2
#define HWIO_AOSS_CC_RESET_STATUS_PMIC_RESIN_RESET_STATUS_SHFT                                   0x1
#define HWIO_AOSS_CC_RESET_STATUS_SECURE_WDOG_EXPIRE_RESET_STATUS_BMSK                           0x1
#define HWIO_AOSS_CC_RESET_STATUS_SECURE_WDOG_EXPIRE_RESET_STATUS_SHFT                           0x0

#define HWIO_AOSS_CC_RESET_FSM_STATUS_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050024)
#define HWIO_AOSS_CC_RESET_FSM_STATUS_RMSK                                                   0xfffff
#define HWIO_AOSS_CC_RESET_FSM_STATUS_IN          \
        in_dword(HWIO_AOSS_CC_RESET_FSM_STATUS_ADDR)
#define HWIO_AOSS_CC_RESET_FSM_STATUS_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_RESET_FSM_STATUS_ADDR, m)
#define HWIO_AOSS_CC_RESET_FSM_STATUS_OUT(v)      \
        out_dword(HWIO_AOSS_CC_RESET_FSM_STATUS_ADDR,v)
#define HWIO_AOSS_CC_RESET_FSM_STATUS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_RESET_FSM_STATUS_ADDR,m,v,HWIO_AOSS_CC_RESET_FSM_STATUS_IN)
#define HWIO_AOSS_CC_RESET_FSM_STATUS_PCIE_LINK_DN_REQ_BMSK                                  0x80000
#define HWIO_AOSS_CC_RESET_FSM_STATUS_PCIE_LINK_DN_REQ_SHFT                                     0x13
#define HWIO_AOSS_CC_RESET_FSM_STATUS_PCIE_LINK_DN_ACK_BMSK                                  0x40000
#define HWIO_AOSS_CC_RESET_FSM_STATUS_PCIE_LINK_DN_ACK_SHFT                                     0x12
#define HWIO_AOSS_CC_RESET_FSM_STATUS_BLOCK_PCIE_ARES_BMSK                                   0x20000
#define HWIO_AOSS_CC_RESET_FSM_STATUS_BLOCK_PCIE_ARES_SHFT                                      0x11
#define HWIO_AOSS_CC_RESET_FSM_STATUS_ALLOW_PCIE_ARES_BMSK                                   0x10000
#define HWIO_AOSS_CC_RESET_FSM_STATUS_ALLOW_PCIE_ARES_SHFT                                      0x10
#define HWIO_AOSS_CC_RESET_FSM_STATUS_PCIE_LINK_TMR_LD_BMSK                                   0x8000
#define HWIO_AOSS_CC_RESET_FSM_STATUS_PCIE_LINK_TMR_LD_SHFT                                      0xf
#define HWIO_AOSS_CC_RESET_FSM_STATUS_PCIE_LINK_TMR_EXPIRE_BMSK                               0x4000
#define HWIO_AOSS_CC_RESET_FSM_STATUS_PCIE_LINK_TMR_EXPIRE_SHFT                                  0xe
#define HWIO_AOSS_CC_RESET_FSM_STATUS_DBG_PDC_HANG_STATUS_BMSK                                0x2000
#define HWIO_AOSS_CC_RESET_FSM_STATUS_DBG_PDC_HANG_STATUS_SHFT                                   0xd
#define HWIO_AOSS_CC_RESET_FSM_STATUS_DBG_PDC_TRIGGER_BMSK                                    0x1000
#define HWIO_AOSS_CC_RESET_FSM_STATUS_DBG_PDC_TRIGGER_SHFT                                       0xc
#define HWIO_AOSS_CC_RESET_FSM_STATUS_NORM_WKUP_HANG_STATUS_BMSK                               0x800
#define HWIO_AOSS_CC_RESET_FSM_STATUS_NORM_WKUP_HANG_STATUS_SHFT                                 0xb
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FIRST_PASS_EXPIRE_BMSK                                   0x400
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FIRST_PASS_EXPIRE_SHFT                                     0xa
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FIRST_PASS_TIMER_LD_BMSK                                 0x200
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FIRST_PASS_TIMER_LD_SHFT                                   0x9
#define HWIO_AOSS_CC_RESET_FSM_STATUS_BLOCK_RESIN_ASET_BMSK                                    0x100
#define HWIO_AOSS_CC_RESET_FSM_STATUS_BLOCK_RESIN_ASET_SHFT                                      0x8
#define HWIO_AOSS_CC_RESET_FSM_STATUS_BLOCK_RESIN_ARES_BMSK                                     0x80
#define HWIO_AOSS_CC_RESET_FSM_STATUS_BLOCK_RESIN_ARES_SHFT                                      0x7
#define HWIO_AOSS_CC_RESET_FSM_STATUS_DBG_TIMER_TRIGGER_BMSK                                    0x40
#define HWIO_AOSS_CC_RESET_FSM_STATUS_DBG_TIMER_TRIGGER_SHFT                                     0x6
#define HWIO_AOSS_CC_RESET_FSM_STATUS_RESET_DEBUG_READY_BMSK                                    0x20
#define HWIO_AOSS_CC_RESET_FSM_STATUS_RESET_DEBUG_READY_SHFT                                     0x5
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FIRST_PASS_BMSK                                           0x10
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FIRST_PASS_SHFT                                            0x4
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FSM_STATE_BMSK                                             0xf
#define HWIO_AOSS_CC_RESET_FSM_STATUS_FSM_STATE_SHFT                                             0x0

#define HWIO_AOSS_CC_TIC_MISC_ADDR                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050028)
#define HWIO_AOSS_CC_TIC_MISC_RMSK                                                               0x3
#define HWIO_AOSS_CC_TIC_MISC_IN          \
        in_dword(HWIO_AOSS_CC_TIC_MISC_ADDR)
#define HWIO_AOSS_CC_TIC_MISC_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_TIC_MISC_ADDR, m)
#define HWIO_AOSS_CC_TIC_MISC_OUT(v)      \
        out_dword(HWIO_AOSS_CC_TIC_MISC_ADDR,v)
#define HWIO_AOSS_CC_TIC_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_TIC_MISC_ADDR,m,v,HWIO_AOSS_CC_TIC_MISC_IN)
#define HWIO_AOSS_CC_TIC_MISC_APCS_SANS_BOOT_PROC_RESET_IN_TIC_BMSK                              0x2
#define HWIO_AOSS_CC_TIC_MISC_APCS_SANS_BOOT_PROC_RESET_IN_TIC_SHFT                              0x1
#define HWIO_AOSS_CC_TIC_MISC_BOOT_PROC_RESET_IN_TIC_BMSK                                        0x1
#define HWIO_AOSS_CC_TIC_MISC_BOOT_PROC_RESET_IN_TIC_SHFT                                        0x0

#define HWIO_AOSS_CC_APCS_MISC_ADDR                                                       (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00051000)
#define HWIO_AOSS_CC_APCS_MISC_RMSK                                                              0x1
#define HWIO_AOSS_CC_APCS_MISC_IN          \
        in_dword(HWIO_AOSS_CC_APCS_MISC_ADDR)
#define HWIO_AOSS_CC_APCS_MISC_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_APCS_MISC_ADDR, m)
#define HWIO_AOSS_CC_APCS_MISC_OUT(v)      \
        out_dword(HWIO_AOSS_CC_APCS_MISC_ADDR,v)
#define HWIO_AOSS_CC_APCS_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_APCS_MISC_ADDR,m,v,HWIO_AOSS_CC_APCS_MISC_IN)
#define HWIO_AOSS_CC_APCS_MISC_AOP_RESET_BMSK                                                    0x1
#define HWIO_AOSS_CC_APCS_MISC_AOP_RESET_SHFT                                                    0x0

#define HWIO_AOSS_CC_APCS_RESET_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0005002c)
#define HWIO_AOSS_CC_APCS_RESET_RMSK                                                             0x3
#define HWIO_AOSS_CC_APCS_RESET_IN          \
        in_dword(HWIO_AOSS_CC_APCS_RESET_ADDR)
#define HWIO_AOSS_CC_APCS_RESET_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_APCS_RESET_ADDR, m)
#define HWIO_AOSS_CC_APCS_RESET_OUT(v)      \
        out_dword(HWIO_AOSS_CC_APCS_RESET_ADDR,v)
#define HWIO_AOSS_CC_APCS_RESET_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_APCS_RESET_ADDR,m,v,HWIO_AOSS_CC_APCS_RESET_IN)
#define HWIO_AOSS_CC_APCS_RESET_APCS_SANS_BOOT_PROC_RESET_BMSK                                   0x2
#define HWIO_AOSS_CC_APCS_RESET_APCS_SANS_BOOT_PROC_RESET_SHFT                                   0x1
#define HWIO_AOSS_CC_APCS_RESET_BOOT_PROC_RESET_BMSK                                             0x1
#define HWIO_AOSS_CC_APCS_RESET_BOOT_PROC_RESET_SHFT                                             0x0

#define HWIO_AOSS_CC_MSS_RESTART_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00010000)
#define HWIO_AOSS_CC_MSS_RESTART_RMSK                                                            0x1
#define HWIO_AOSS_CC_MSS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_MSS_RESTART_ADDR)
#define HWIO_AOSS_CC_MSS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_MSS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_MSS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_MSS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_MSS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_MSS_RESTART_ADDR,m,v,HWIO_AOSS_CC_MSS_RESTART_IN)
#define HWIO_AOSS_CC_MSS_RESTART_SS_RESTART_BMSK                                                 0x1
#define HWIO_AOSS_CC_MSS_RESTART_SS_RESTART_SHFT                                                 0x0

#define HWIO_AOSS_CC_CAMSS_RESTART_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00011000)
#define HWIO_AOSS_CC_CAMSS_RESTART_RMSK                                                          0x1
#define HWIO_AOSS_CC_CAMSS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_CAMSS_RESTART_ADDR)
#define HWIO_AOSS_CC_CAMSS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_CAMSS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_CAMSS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_CAMSS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_CAMSS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_CAMSS_RESTART_ADDR,m,v,HWIO_AOSS_CC_CAMSS_RESTART_IN)
#define HWIO_AOSS_CC_CAMSS_RESTART_SS_RESTART_BMSK                                               0x1
#define HWIO_AOSS_CC_CAMSS_RESTART_SS_RESTART_SHFT                                               0x0

#define HWIO_AOSS_CC_VENUS_RESTART_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00012000)
#define HWIO_AOSS_CC_VENUS_RESTART_RMSK                                                          0x1
#define HWIO_AOSS_CC_VENUS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_VENUS_RESTART_ADDR)
#define HWIO_AOSS_CC_VENUS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_VENUS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_VENUS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_VENUS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_VENUS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_VENUS_RESTART_ADDR,m,v,HWIO_AOSS_CC_VENUS_RESTART_IN)
#define HWIO_AOSS_CC_VENUS_RESTART_SS_RESTART_BMSK                                               0x1
#define HWIO_AOSS_CC_VENUS_RESTART_SS_RESTART_SHFT                                               0x0

#define HWIO_AOSS_CC_GPU_RESTART_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00013000)
#define HWIO_AOSS_CC_GPU_RESTART_RMSK                                                            0x1
#define HWIO_AOSS_CC_GPU_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_GPU_RESTART_ADDR)
#define HWIO_AOSS_CC_GPU_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_GPU_RESTART_ADDR, m)
#define HWIO_AOSS_CC_GPU_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_GPU_RESTART_ADDR,v)
#define HWIO_AOSS_CC_GPU_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_GPU_RESTART_ADDR,m,v,HWIO_AOSS_CC_GPU_RESTART_IN)
#define HWIO_AOSS_CC_GPU_RESTART_SS_RESTART_BMSK                                                 0x1
#define HWIO_AOSS_CC_GPU_RESTART_SS_RESTART_SHFT                                                 0x0

#define HWIO_AOSS_CC_DISPSS_RESTART_ADDR                                                  (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00014000)
#define HWIO_AOSS_CC_DISPSS_RESTART_RMSK                                                         0x1
#define HWIO_AOSS_CC_DISPSS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_DISPSS_RESTART_ADDR)
#define HWIO_AOSS_CC_DISPSS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_DISPSS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_DISPSS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_DISPSS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_DISPSS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_DISPSS_RESTART_ADDR,m,v,HWIO_AOSS_CC_DISPSS_RESTART_IN)
#define HWIO_AOSS_CC_DISPSS_RESTART_SS_RESTART_BMSK                                              0x1
#define HWIO_AOSS_CC_DISPSS_RESTART_SS_RESTART_SHFT                                              0x0

#define HWIO_AOSS_CC_WCSS_RESTART_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00020000)
#define HWIO_AOSS_CC_WCSS_RESTART_RMSK                                                           0x1
#define HWIO_AOSS_CC_WCSS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_WCSS_RESTART_ADDR)
#define HWIO_AOSS_CC_WCSS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_WCSS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_WCSS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_WCSS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_WCSS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_WCSS_RESTART_ADDR,m,v,HWIO_AOSS_CC_WCSS_RESTART_IN)
#define HWIO_AOSS_CC_WCSS_RESTART_SS_RESTART_BMSK                                                0x1
#define HWIO_AOSS_CC_WCSS_RESTART_SS_RESTART_SHFT                                                0x0

#define HWIO_AOSS_CC_GSS_RESTART_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00021000)
#define HWIO_AOSS_CC_GSS_RESTART_RMSK                                                            0x1
#define HWIO_AOSS_CC_GSS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_GSS_RESTART_ADDR)
#define HWIO_AOSS_CC_GSS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_GSS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_GSS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_GSS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_GSS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_GSS_RESTART_ADDR,m,v,HWIO_AOSS_CC_GSS_RESTART_IN)
#define HWIO_AOSS_CC_GSS_RESTART_SS_RESTART_BMSK                                                 0x1
#define HWIO_AOSS_CC_GSS_RESTART_SS_RESTART_SHFT                                                 0x0

#define HWIO_AOSS_CC_LPASS_RESTART_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00030000)
#define HWIO_AOSS_CC_LPASS_RESTART_RMSK                                                          0x1
#define HWIO_AOSS_CC_LPASS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_LPASS_RESTART_ADDR)
#define HWIO_AOSS_CC_LPASS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_LPASS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_LPASS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_LPASS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_LPASS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_LPASS_RESTART_ADDR,m,v,HWIO_AOSS_CC_LPASS_RESTART_IN)
#define HWIO_AOSS_CC_LPASS_RESTART_SS_RESTART_BMSK                                               0x1
#define HWIO_AOSS_CC_LPASS_RESTART_SS_RESTART_SHFT                                               0x0

#define HWIO_AOSS_CC_NPU_RESTART_ADDR                                                     (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00030004)
#define HWIO_AOSS_CC_NPU_RESTART_RMSK                                                            0x1
#define HWIO_AOSS_CC_NPU_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_NPU_RESTART_ADDR)
#define HWIO_AOSS_CC_NPU_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_NPU_RESTART_ADDR, m)
#define HWIO_AOSS_CC_NPU_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_NPU_RESTART_ADDR,v)
#define HWIO_AOSS_CC_NPU_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_NPU_RESTART_ADDR,m,v,HWIO_AOSS_CC_NPU_RESTART_IN)
#define HWIO_AOSS_CC_NPU_RESTART_SS_RESTART_BMSK                                                 0x1
#define HWIO_AOSS_CC_NPU_RESTART_SS_RESTART_SHFT                                                 0x0

#define HWIO_AOSS_CC_SENSORS_RESTART_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00031000)
#define HWIO_AOSS_CC_SENSORS_RESTART_RMSK                                                        0x1
#define HWIO_AOSS_CC_SENSORS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_SENSORS_RESTART_ADDR)
#define HWIO_AOSS_CC_SENSORS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SENSORS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_SENSORS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SENSORS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_SENSORS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SENSORS_RESTART_ADDR,m,v,HWIO_AOSS_CC_SENSORS_RESTART_IN)
#define HWIO_AOSS_CC_SENSORS_RESTART_SS_RESTART_BMSK                                             0x1
#define HWIO_AOSS_CC_SENSORS_RESTART_SS_RESTART_SHFT                                             0x0

#define HWIO_AOSS_CC_SPSS_RESTART_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00032000)
#define HWIO_AOSS_CC_SPSS_RESTART_RMSK                                                           0x1
#define HWIO_AOSS_CC_SPSS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_SPSS_RESTART_ADDR)
#define HWIO_AOSS_CC_SPSS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPSS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_SPSS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPSS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_SPSS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPSS_RESTART_ADDR,m,v,HWIO_AOSS_CC_SPSS_RESTART_IN)
#define HWIO_AOSS_CC_SPSS_RESTART_SS_RESTART_BMSK                                                0x1
#define HWIO_AOSS_CC_SPSS_RESTART_SS_RESTART_SHFT                                                0x0

#define HWIO_AOSS_CC_COMPUTESS_RESTART_ADDR                                               (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00040000)
#define HWIO_AOSS_CC_COMPUTESS_RESTART_RMSK                                                      0x1
#define HWIO_AOSS_CC_COMPUTESS_RESTART_IN          \
        in_dword(HWIO_AOSS_CC_COMPUTESS_RESTART_ADDR)
#define HWIO_AOSS_CC_COMPUTESS_RESTART_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_COMPUTESS_RESTART_ADDR, m)
#define HWIO_AOSS_CC_COMPUTESS_RESTART_OUT(v)      \
        out_dword(HWIO_AOSS_CC_COMPUTESS_RESTART_ADDR,v)
#define HWIO_AOSS_CC_COMPUTESS_RESTART_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_COMPUTESS_RESTART_ADDR,m,v,HWIO_AOSS_CC_COMPUTESS_RESTART_IN)
#define HWIO_AOSS_CC_COMPUTESS_RESTART_SS_RESTART_BMSK                                           0x1
#define HWIO_AOSS_CC_COMPUTESS_RESTART_SS_RESTART_SHFT                                           0x0

#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_ADDR                                             (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050034)
#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_RMSK                                             0xffffffff
#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_IN          \
        in_dword(HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_ADDR)
#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_ADDR, m)
#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_OUT(v)      \
        out_dword(HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_ADDR,v)
#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_ADDR,m,v,HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_IN)
#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_TIMER_VAL_BMSK                                   0xffffffff
#define HWIO_AOSS_CC_ABNORM_WKUP_TIMEOUT_TIMER_VAL_SHFT                                          0x0

#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_ADDR                                                 (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000301c)
#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_RMSK                                                        0x1
#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_IN          \
        in_dword(HWIO_AOSS_CC_DEBUG_HW_EVENTS_ADDR)
#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_DEBUG_HW_EVENTS_ADDR, m)
#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_OUT(v)      \
        out_dword(HWIO_AOSS_CC_DEBUG_HW_EVENTS_ADDR,v)
#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_DEBUG_HW_EVENTS_ADDR,m,v,HWIO_AOSS_CC_DEBUG_HW_EVENTS_IN)
#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_MUX_SEL_BMSK                                                0x1
#define HWIO_AOSS_CC_DEBUG_HW_EVENTS_MUX_SEL_SHFT                                                0x0

#define HWIO_AOSS_CC_AOP_MISC_ADDR                                                        (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003020)
#define HWIO_AOSS_CC_AOP_MISC_RMSK                                                               0x1
#define HWIO_AOSS_CC_AOP_MISC_IN          \
        in_dword(HWIO_AOSS_CC_AOP_MISC_ADDR)
#define HWIO_AOSS_CC_AOP_MISC_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_AOP_MISC_ADDR, m)
#define HWIO_AOSS_CC_AOP_MISC_OUT(v)      \
        out_dword(HWIO_AOSS_CC_AOP_MISC_ADDR,v)
#define HWIO_AOSS_CC_AOP_MISC_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_AOP_MISC_ADDR,m,v,HWIO_AOSS_CC_AOP_MISC_IN)
#define HWIO_AOSS_CC_AOP_MISC_AUTO_SCALE_DIS_BMSK                                                0x1
#define HWIO_AOSS_CC_AOP_MISC_AUTO_SCALE_DIS_SHFT                                                0x0

#define HWIO_AOSS_CC_PLL0_MODE_SEL_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003000)
#define HWIO_AOSS_CC_PLL0_MODE_SEL_RMSK                                                   0xffffffff
#define HWIO_AOSS_CC_PLL0_MODE_SEL_IN          \
        in_dword(HWIO_AOSS_CC_PLL0_MODE_SEL_ADDR)
#define HWIO_AOSS_CC_PLL0_MODE_SEL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL0_MODE_SEL_ADDR, m)
#define HWIO_AOSS_CC_PLL0_MODE_SEL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL0_MODE_SEL_ADDR,v)
#define HWIO_AOSS_CC_PLL0_MODE_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL0_MODE_SEL_ADDR,m,v,HWIO_AOSS_CC_PLL0_MODE_SEL_IN)
#define HWIO_AOSS_CC_PLL0_MODE_SEL_RESERVE_BITS31_1_BMSK                                  0xfffffffe
#define HWIO_AOSS_CC_PLL0_MODE_SEL_RESERVE_BITS31_1_SHFT                                         0x1
#define HWIO_AOSS_CC_PLL0_MODE_SEL_SELECT_BIT0_BMSK                                              0x1
#define HWIO_AOSS_CC_PLL0_MODE_SEL_SELECT_BIT0_SHFT                                              0x0

#define HWIO_AOSS_CC_PLL1_OUTCTRL_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003024)
#define HWIO_AOSS_CC_PLL1_OUTCTRL_RMSK                                                           0x1
#define HWIO_AOSS_CC_PLL1_OUTCTRL_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_OUTCTRL_ADDR)
#define HWIO_AOSS_CC_PLL1_OUTCTRL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_OUTCTRL_ADDR, m)
#define HWIO_AOSS_CC_PLL1_OUTCTRL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_OUTCTRL_ADDR,v)
#define HWIO_AOSS_CC_PLL1_OUTCTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_OUTCTRL_ADDR,m,v,HWIO_AOSS_CC_PLL1_OUTCTRL_IN)
#define HWIO_AOSS_CC_PLL1_OUTCTRL_SEL_BMSK                                                       0x1
#define HWIO_AOSS_CC_PLL1_OUTCTRL_SEL_SHFT                                                       0x0

#define HWIO_AOSS_CC_PLL1_MODE_SEL_ADDR                                                   (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003028)
#define HWIO_AOSS_CC_PLL1_MODE_SEL_RMSK                                                   0xffffffff
#define HWIO_AOSS_CC_PLL1_MODE_SEL_IN          \
        in_dword(HWIO_AOSS_CC_PLL1_MODE_SEL_ADDR)
#define HWIO_AOSS_CC_PLL1_MODE_SEL_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PLL1_MODE_SEL_ADDR, m)
#define HWIO_AOSS_CC_PLL1_MODE_SEL_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PLL1_MODE_SEL_ADDR,v)
#define HWIO_AOSS_CC_PLL1_MODE_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PLL1_MODE_SEL_ADDR,m,v,HWIO_AOSS_CC_PLL1_MODE_SEL_IN)
#define HWIO_AOSS_CC_PLL1_MODE_SEL_RESERVE_BITS31_1_BMSK                                  0xfffffffe
#define HWIO_AOSS_CC_PLL1_MODE_SEL_RESERVE_BITS31_1_SHFT                                         0x1
#define HWIO_AOSS_CC_PLL1_MODE_SEL_SELECT_BIT0_BMSK                                              0x1
#define HWIO_AOSS_CC_PLL1_MODE_SEL_SELECT_BIT0_SHFT                                              0x0

#define HWIO_AOSS_CC_SPARE2_REG_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x0000302c)
#define HWIO_AOSS_CC_SPARE2_REG_RMSK                                                      0xffffffff
#define HWIO_AOSS_CC_SPARE2_REG_IN          \
        in_dword(HWIO_AOSS_CC_SPARE2_REG_ADDR)
#define HWIO_AOSS_CC_SPARE2_REG_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPARE2_REG_ADDR, m)
#define HWIO_AOSS_CC_SPARE2_REG_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPARE2_REG_ADDR,v)
#define HWIO_AOSS_CC_SPARE2_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPARE2_REG_ADDR,m,v,HWIO_AOSS_CC_SPARE2_REG_IN)
#define HWIO_AOSS_CC_SPARE2_REG_SPARE2_BITS_BMSK                                          0xffffffff
#define HWIO_AOSS_CC_SPARE2_REG_SPARE2_BITS_SHFT                                                 0x0

#define HWIO_AOSS_CC_CSYSPWRUPREQ_ADDR                                                    (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00003030)
#define HWIO_AOSS_CC_CSYSPWRUPREQ_RMSK                                                    0x80000000
#define HWIO_AOSS_CC_CSYSPWRUPREQ_IN          \
        in_dword(HWIO_AOSS_CC_CSYSPWRUPREQ_ADDR)
#define HWIO_AOSS_CC_CSYSPWRUPREQ_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_CSYSPWRUPREQ_ADDR, m)
#define HWIO_AOSS_CC_CSYSPWRUPREQ_STATUS_BMSK                                             0x80000000
#define HWIO_AOSS_CC_CSYSPWRUPREQ_STATUS_SHFT                                                   0x1f

#define HWIO_AOSS_CC_SPARE3_REG_ADDR                                                      (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050038)
#define HWIO_AOSS_CC_SPARE3_REG_RMSK                                                      0xffffffff
#define HWIO_AOSS_CC_SPARE3_REG_IN          \
        in_dword(HWIO_AOSS_CC_SPARE3_REG_ADDR)
#define HWIO_AOSS_CC_SPARE3_REG_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_SPARE3_REG_ADDR, m)
#define HWIO_AOSS_CC_SPARE3_REG_OUT(v)      \
        out_dword(HWIO_AOSS_CC_SPARE3_REG_ADDR,v)
#define HWIO_AOSS_CC_SPARE3_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_SPARE3_REG_ADDR,m,v,HWIO_AOSS_CC_SPARE3_REG_IN)
#define HWIO_AOSS_CC_SPARE3_REG_SPARE2_BITS_BMSK                                          0xffffffff
#define HWIO_AOSS_CC_SPARE3_REG_SPARE2_BITS_SHFT                                                 0x0

#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_ADDR                                            (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00050040)
#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_RMSK                                            0xffffffff
#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_IN          \
        in_dword(HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_ADDR)
#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_ADDR, m)
#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_OUT(v)      \
        out_dword(HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_ADDR,v)
#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_ADDR,m,v,HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_IN)
#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_TIMER_VAL_BMSK                                  0xffffffff
#define HWIO_AOSS_CC_PCIE_LINK_DN_TIMEOUT_TIMER_VAL_SHFT                                         0x0

#define HWIO_AOSS_CC_ALT_RESET_ENABLE_ADDR                                                (AOSS_CC_AOSS_CC_REG_REG_BASE      + 0x00000458)
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_RMSK                                                       0x3
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_IN          \
        in_dword(HWIO_AOSS_CC_ALT_RESET_ENABLE_ADDR)
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_INM(m)      \
        in_dword_masked(HWIO_AOSS_CC_ALT_RESET_ENABLE_ADDR, m)
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_OUT(v)      \
        out_dword(HWIO_AOSS_CC_ALT_RESET_ENABLE_ADDR,v)
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_AOSS_CC_ALT_RESET_ENABLE_ADDR,m,v,HWIO_AOSS_CC_ALT_RESET_ENABLE_IN)
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_ALLOW_GEMNOC_ALT_ARES_BMSK                                 0x2
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_ALLOW_GEMNOC_ALT_ARES_SHFT                                 0x1
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_ALLOW_BIMC_ALT_ARES_BMSK                                   0x1
#define HWIO_AOSS_CC_ALT_RESET_ENABLE_ALLOW_BIMC_ALT_ARES_SHFT                                   0x0


#endif /* __HALBOOTHWIO_H__ */