#ifndef __HALCLKPLLSETTINGS_H__
#define __HALCLKPLLSETTINGS_H__

/*
==============================================================================

FILE:         HALclkPLLSettings.h

DESCRIPTION:
  PLL CONFIG/TEST/USER_CTL settings auto-generated from PLL HSRs...
    SM8250v1 (kona_1.0): 13.0
    SM8250v2 (kona_2.0): 5.0


==============================================================================

$Header: //components/rel/boot.xf/3.2/QcomPkg/SocPkg/8250/Library/ClockTargetLib/HALclkPLLSettings.h#8 $

==============================================================================
            Copyright (c) 2019 QUALCOMM Technologies Incorporated.
                    All Rights Reserved.
                  QUALCOMM Proprietary/GTDR
==============================================================================

*/

/*=========================================================================
      Definitions
==========================================================================*/

#define HAL_CLK_AOSS_CC_AOSS_CC_PLL0_CONFIG_CTL                           0x20485699
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL0_CONFIG_CTL_U                         0x00002261
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL0_CONFIG_CTL_U1                        0x329A699C
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL0_TEST_CTL                             0x00000000
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL0_TEST_CTL_U                           0x00000000
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL0_TEST_CTL_U1                          0x00000000
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL0_USER_CTL                             0x00000000
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL0_USER_CTL_U                           0x00000805
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL0_USER_CTL_U1                          0x00000000
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL0_L_VALUE                              0x0000001F
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL0_ALPHA_VALUE                          0x00004000
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL1_CONFIG_CTL                           0x60008F64
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL1_CONFIG_CTL_U                         0x0001C808
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL1_CONFIG_CTL_U1                        0x00000000
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL1_CONFIG_CTL_U2                        0x04000780
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL1_TEST_CTL                             0x0088C496
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL1_TEST_CTL_U                           0x60000000
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL1_TEST_CTL_U1                          0x44210030
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL1_TEST_CTL_U2                          0x00000398
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL1_USER_CTL                             0x00000000
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL1_USER_CTL_U                           0x00250002
#define HAL_CLK_AOSS_CC_AOSS_CC_PLL1_L_VALUE                              0x00000002
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_V1_CONFIG_CTL                        0x08200920
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_V1_CONFIG_CTL_U                      0x05008001
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_V1_CONFIG_CTL_U1                     0x00000010
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_V1_TEST_CTL                          0x00010000
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_V1_TEST_CTL_U                        0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_V1_TEST_CTL_U1                       0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_V1_USER_CTL                          0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_V1_USER_CTL_U                        0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_V1_USER_CTL_U1                       0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_CONFIG_CTL                           0x08200920
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_CONFIG_CTL_U                         0x05002005
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_CONFIG_CTL_U1                        0x00000010
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_TEST_CTL                             0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_TEST_CTL_U                           0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_TEST_CTL_U1                          0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_USER_CTL                             0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_USER_CTL_U                           0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL0_USER_CTL_U1                          0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_V1_CONFIG_CTL                        0x08200920
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_V1_CONFIG_CTL_U                      0x05008001
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_V1_CONFIG_CTL_U1                     0x00000010
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_V1_TEST_CTL                          0x00010000
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_V1_TEST_CTL_U                        0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_V1_TEST_CTL_U1                       0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_V1_USER_CTL                          0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_V1_USER_CTL_U                        0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_V1_USER_CTL_U1                       0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_CONFIG_CTL                           0x08200920
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_CONFIG_CTL_U                         0x05002005
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_CONFIG_CTL_U1                        0x00000010
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_TEST_CTL                             0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_TEST_CTL_U                           0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_TEST_CTL_U1                          0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_USER_CTL                             0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_USER_CTL_U                           0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL1_USER_CTL_U1                          0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_V1_CONFIG_CTL                        0x08200920
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_V1_CONFIG_CTL_U                      0x05008001
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_V1_CONFIG_CTL_U1                     0x00000010
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_V1_TEST_CTL                          0x00010000
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_V1_TEST_CTL_U                        0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_V1_TEST_CTL_U1                       0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_V1_USER_CTL                          0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_V1_USER_CTL_U                        0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_V1_USER_CTL_U1                       0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_CONFIG_CTL                           0x08200920
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_CONFIG_CTL_U                         0x05002005
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_CONFIG_CTL_U1                        0x00000010
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_TEST_CTL                             0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_TEST_CTL_U                           0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_TEST_CTL_U1                          0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_USER_CTL                             0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_USER_CTL_U                           0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL2_USER_CTL_U1                          0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_V1_CONFIG_CTL                        0x08200920
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_V1_CONFIG_CTL_U                      0x05008001
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_V1_CONFIG_CTL_U1                     0x00000010
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_V1_TEST_CTL                          0x00010000
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_V1_TEST_CTL_U                        0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_V1_TEST_CTL_U1                       0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_V1_USER_CTL                          0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_V1_USER_CTL_U                        0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_V1_USER_CTL_U1                       0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_CONFIG_CTL                           0x08200920
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_CONFIG_CTL_U                         0x05002005
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_CONFIG_CTL_U1                        0x00000010
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_TEST_CTL                             0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_TEST_CTL_U                           0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_TEST_CTL_U1                          0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_USER_CTL                             0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_USER_CTL_U                           0x00000000
#define HAL_CLK_APSS_CC_APSS_CC_PLL3_USER_CTL_U1                          0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL0_CONFIG_CTL                             0x20485699
#define HAL_CLK_CAM_CC_CAM_CC_PLL0_CONFIG_CTL_U                           0x00002261
#define HAL_CLK_CAM_CC_CAM_CC_PLL0_CONFIG_CTL_U1                          0x329A699C
#define HAL_CLK_CAM_CC_CAM_CC_PLL0_TEST_CTL                               0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL0_TEST_CTL_U                             0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL0_TEST_CTL_U1                            0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL0_USER_CTL                               0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL0_USER_CTL_U                             0x00000805
#define HAL_CLK_CAM_CC_CAM_CC_PLL0_USER_CTL_U1                            0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL0_L_VALUE                                0x0000003E
#define HAL_CLK_CAM_CC_CAM_CC_PLL0_ALPHA_VALUE                            0x00008000
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_CONFIG_CTL                             0x20485699
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_CONFIG_CTL_U                           0x00002261
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_CONFIG_CTL_U1                          0x329A699C
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_TEST_CTL                               0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_TEST_CTL_U                             0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_TEST_CTL_U1                            0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_USER_CTL                               0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_USER_CTL_U                             0x00000805
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_USER_CTL_U1                            0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_L_VALUE_LOWSVS                         0x0000001F
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_ALPHA_VALUE_LOWSVS                     0x00004000
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_L_VALUE_SVS                            0x00000031
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_ALPHA_VALUE_SVS                        0x00007AAA
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_L_VALUE_SVS_L1                         0x00000036
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_ALPHA_VALUE_SVS_L1                     0x0000B000
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_L_VALUE_NOMINAL                        0x00000048
#define HAL_CLK_CAM_CC_CAM_CC_PLL1_ALPHA_VALUE_NOMINAL                    0x0000EAAA
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_V1_CONFIG_CTL                          0x08200920
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_V1_CONFIG_CTL_U                        0x05008011
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_V1_CONFIG_CTL_U1                       0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_V1_TEST_CTL                            0x00010000
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_V1_TEST_CTL_U                          0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_V1_TEST_CTL_U1                         0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_V1_USER_CTL                            0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_V1_USER_CTL_U                          0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_V1_USER_CTL_U1                         0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_CONFIG_CTL                             0x08200920
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_CONFIG_CTL_U                           0x05002015
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_CONFIG_CTL_U1                          0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_TEST_CTL                               0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_TEST_CTL_U                             0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_TEST_CTL_U1                            0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_USER_CTL                               0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_USER_CTL_U                             0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_USER_CTL_U1                            0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_V1_L_VALUE                             0x00000032
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_V1_ALPHA_VALUE                         0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_V2_L_VALUE                             0x0000004B
#define HAL_CLK_CAM_CC_CAM_CC_PLL2_V2_ALPHA_VALUE                         0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_CONFIG_CTL                             0x20485699
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_CONFIG_CTL_U                           0x00002261
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_CONFIG_CTL_U1                          0x329A699C
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_TEST_CTL                               0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_TEST_CTL_U                             0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_TEST_CTL_U1                            0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_USER_CTL                               0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_USER_CTL_U                             0x00000805
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_USER_CTL_U1                            0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_L_VALUE_LOWSVS                         0x00000024
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_ALPHA_VALUE_LOWSVS                     0x00007555
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_L_VALUE_SVS                            0x00000031
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_ALPHA_VALUE_SVS                        0x00007AAA
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_L_VALUE_SVS_L1                         0x0000003C
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_ALPHA_VALUE_SVS_L1                     0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_L_VALUE_NOMINAL                        0x00000046
#define HAL_CLK_CAM_CC_CAM_CC_PLL3_ALPHA_VALUE_NOMINAL                    0x0000D555
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_CONFIG_CTL                             0x20485699
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_CONFIG_CTL_U                           0x00002261
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_CONFIG_CTL_U1                          0x329A699C
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_TEST_CTL                               0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_TEST_CTL_U                             0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_TEST_CTL_U1                            0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_USER_CTL                               0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_USER_CTL_U                             0x00000805
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_USER_CTL_U1                            0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_L_VALUE_LOWSVS                         0x00000024
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_ALPHA_VALUE_LOWSVS                     0x00007555
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_L_VALUE_SVS                            0x00000031
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_ALPHA_VALUE_SVS                        0x00007AAA
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_L_VALUE_SVS_L1                         0x0000003C
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_ALPHA_VALUE_SVS_L1                     0x00000000
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_L_VALUE_NOMINAL                        0x00000046
#define HAL_CLK_CAM_CC_CAM_CC_PLL4_ALPHA_VALUE_NOMINAL                    0x0000D555
#define HAL_CLK_DISP_CC_DISP_CC_PLL0_CONFIG_CTL                           0x20485699
#define HAL_CLK_DISP_CC_DISP_CC_PLL0_CONFIG_CTL_U                         0x00002261
#define HAL_CLK_DISP_CC_DISP_CC_PLL0_CONFIG_CTL_U1                        0x329A699C
#define HAL_CLK_DISP_CC_DISP_CC_PLL0_TEST_CTL                             0x00000000
#define HAL_CLK_DISP_CC_DISP_CC_PLL0_TEST_CTL_U                           0x00000000
#define HAL_CLK_DISP_CC_DISP_CC_PLL0_TEST_CTL_U1                          0x00000000
#define HAL_CLK_DISP_CC_DISP_CC_PLL0_USER_CTL                             0x00000000
#define HAL_CLK_DISP_CC_DISP_CC_PLL0_USER_CTL_U                           0x00000805
#define HAL_CLK_DISP_CC_DISP_CC_PLL0_USER_CTL_U1                          0x00000000
#define HAL_CLK_DISP_CC_DISP_CC_PLL0_L_VALUE                              0x00000047
#define HAL_CLK_DISP_CC_DISP_CC_PLL0_ALPHA_VALUE                          0x0000E000
#define HAL_CLK_DISP_CC_DISP_CC_PLL1_CONFIG_CTL                           0x20485699
#define HAL_CLK_DISP_CC_DISP_CC_PLL1_CONFIG_CTL_U                         0x00002261
#define HAL_CLK_DISP_CC_DISP_CC_PLL1_CONFIG_CTL_U1                        0x329A699C
#define HAL_CLK_DISP_CC_DISP_CC_PLL1_TEST_CTL                             0x00000000
#define HAL_CLK_DISP_CC_DISP_CC_PLL1_TEST_CTL_U                           0x00000000
#define HAL_CLK_DISP_CC_DISP_CC_PLL1_TEST_CTL_U1                          0x00000000
#define HAL_CLK_DISP_CC_DISP_CC_PLL1_USER_CTL                             0x00000000
#define HAL_CLK_DISP_CC_DISP_CC_PLL1_USER_CTL_U                           0x00000805
#define HAL_CLK_DISP_CC_DISP_CC_PLL1_USER_CTL_U1                          0x00000000
#define HAL_CLK_DISP_CC_DISP_CC_PLL1_L_VALUE                              0x0000001F
#define HAL_CLK_DISP_CC_DISP_CC_PLL1_ALPHA_VALUE                          0x00004000
#define HAL_CLK_GCC_GPLL0_CONFIG_CTL                                      0x20485699
#define HAL_CLK_GCC_GPLL0_CONFIG_CTL_U                                    0x00002261
#define HAL_CLK_GCC_GPLL0_CONFIG_CTL_U1                                   0x329A699C
#define HAL_CLK_GCC_GPLL0_TEST_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL0_TEST_CTL_U                                      0x00000000
#define HAL_CLK_GCC_GPLL0_TEST_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL0_USER_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL0_USER_CTL_U                                      0x00000805
#define HAL_CLK_GCC_GPLL0_USER_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL0_L_VALUE                                         0x0000001F
#define HAL_CLK_GCC_GPLL0_ALPHA_VALUE                                     0x00004000
#define HAL_CLK_GCC_GPLL1_CONFIG_CTL                                      0x20485699
#define HAL_CLK_GCC_GPLL1_CONFIG_CTL_U                                    0x00002261
#define HAL_CLK_GCC_GPLL1_CONFIG_CTL_U1                                   0x329A699C
#define HAL_CLK_GCC_GPLL1_TEST_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL1_TEST_CTL_U                                      0x00000000
#define HAL_CLK_GCC_GPLL1_TEST_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL1_USER_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL1_USER_CTL_U                                      0x00000805
#define HAL_CLK_GCC_GPLL1_USER_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL1_L_VALUE                                         0x00000037
#define HAL_CLK_GCC_GPLL1_ALPHA_VALUE                                     0x00008555
#define HAL_CLK_GCC_GPLL10_CONFIG_CTL                                     0x20485699
#define HAL_CLK_GCC_GPLL10_CONFIG_CTL_U                                   0x00002261
#define HAL_CLK_GCC_GPLL10_CONFIG_CTL_U1                                  0x329A699C
#define HAL_CLK_GCC_GPLL10_TEST_CTL                                       0x00000000
#define HAL_CLK_GCC_GPLL10_TEST_CTL_U                                     0x00000000
#define HAL_CLK_GCC_GPLL10_TEST_CTL_U1                                    0x00000000
#define HAL_CLK_GCC_GPLL10_USER_CTL                                       0x00000000
#define HAL_CLK_GCC_GPLL10_USER_CTL_U                                     0x00000805
#define HAL_CLK_GCC_GPLL10_USER_CTL_U1                                    0x00000000
#define HAL_CLK_GCC_GPLL10_V1_L_VALUE                                     0x00000034
#define HAL_CLK_GCC_GPLL10_V1_ALPHA_VALUE                                 0x00001555
#define HAL_CLK_GCC_GPLL10_V2_L_VALUE                                     0x00000035
#define HAL_CLK_GCC_GPLL10_V2_ALPHA_VALUE                                 0x00002000
#define HAL_CLK_GCC_GPLL11_CONFIG_CTL                                     0x20485699
#define HAL_CLK_GCC_GPLL11_CONFIG_CTL_U                                   0x00002261
#define HAL_CLK_GCC_GPLL11_CONFIG_CTL_U1                                  0x329A699C
#define HAL_CLK_GCC_GPLL11_TEST_CTL                                       0x00000000
#define HAL_CLK_GCC_GPLL11_TEST_CTL_U                                     0x00000000
#define HAL_CLK_GCC_GPLL11_TEST_CTL_U1                                    0x00000000
#define HAL_CLK_GCC_GPLL11_USER_CTL                                       0x00000000
#define HAL_CLK_GCC_GPLL11_USER_CTL_U                                     0x00000805
#define HAL_CLK_GCC_GPLL11_USER_CTL_U1                                    0x00000000
#define HAL_CLK_GCC_GPLL2_CONFIG_CTL                                      0x20485699
#define HAL_CLK_GCC_GPLL2_CONFIG_CTL_U                                    0x00002261
#define HAL_CLK_GCC_GPLL2_CONFIG_CTL_U1                                   0x329A699C
#define HAL_CLK_GCC_GPLL2_TEST_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL2_TEST_CTL_U                                      0x00000000
#define HAL_CLK_GCC_GPLL2_TEST_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL2_USER_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL2_USER_CTL_U                                      0x00000805
#define HAL_CLK_GCC_GPLL2_USER_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL2_L_VALUE_LOWSVS                                  0x00000017
#define HAL_CLK_GCC_GPLL2_ALPHA_VALUE_LOWSVS                              0x00008000
#define HAL_CLK_GCC_GPLL2_L_VALUE_SVS                                     0x0000001C
#define HAL_CLK_GCC_GPLL2_ALPHA_VALUE_SVS                                 0x00008000
#define HAL_CLK_GCC_GPLL3_CONFIG_CTL                                      0x20485699
#define HAL_CLK_GCC_GPLL3_CONFIG_CTL_U                                    0x00002261
#define HAL_CLK_GCC_GPLL3_CONFIG_CTL_U1                                   0x329A699C
#define HAL_CLK_GCC_GPLL3_TEST_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL3_TEST_CTL_U                                      0x00000000
#define HAL_CLK_GCC_GPLL3_TEST_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL3_USER_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL3_USER_CTL_U                                      0x00000805
#define HAL_CLK_GCC_GPLL3_USER_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL3_L_VALUE_LOWSVS                                  0x00000017
#define HAL_CLK_GCC_GPLL3_ALPHA_VALUE_LOWSVS                              0x00008000
#define HAL_CLK_GCC_GPLL3_L_VALUE_SVS                                     0x0000001C
#define HAL_CLK_GCC_GPLL3_ALPHA_VALUE_SVS                                 0x00008000
#define HAL_CLK_GCC_GPLL4_CONFIG_CTL                                      0x20485699
#define HAL_CLK_GCC_GPLL4_CONFIG_CTL_U                                    0x00002261
#define HAL_CLK_GCC_GPLL4_CONFIG_CTL_U1                                   0x329A699C
#define HAL_CLK_GCC_GPLL4_TEST_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL4_TEST_CTL_U                                      0x00000000
#define HAL_CLK_GCC_GPLL4_TEST_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL4_USER_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL4_USER_CTL_U                                      0x00000805
#define HAL_CLK_GCC_GPLL4_USER_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL4_L_VALUE                                         0x00000029
#define HAL_CLK_GCC_GPLL4_ALPHA_VALUE                                     0x0000FAAA
#define HAL_CLK_GCC_GPLL5_CONFIG_CTL                                      0x20485699
#define HAL_CLK_GCC_GPLL5_CONFIG_CTL_U                                    0x00002261
#define HAL_CLK_GCC_GPLL5_CONFIG_CTL_U1                                   0x329A699C
#define HAL_CLK_GCC_GPLL5_TEST_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL5_TEST_CTL_U                                      0x00000000
#define HAL_CLK_GCC_GPLL5_TEST_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL5_USER_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL5_USER_CTL_U                                      0x00000805
#define HAL_CLK_GCC_GPLL5_USER_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL5_L_VALUE                                         0x00000030
#define HAL_CLK_GCC_GPLL5_ALPHA_VALUE                                     0x00009800
#define HAL_CLK_GCC_GPLL6_CONFIG_CTL                                      0x20485699
#define HAL_CLK_GCC_GPLL6_CONFIG_CTL_U                                    0x00002261
#define HAL_CLK_GCC_GPLL6_CONFIG_CTL_U1                                   0x329A699C
#define HAL_CLK_GCC_GPLL6_TEST_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL6_TEST_CTL_U                                      0x00000000
#define HAL_CLK_GCC_GPLL6_TEST_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL6_USER_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL6_USER_CTL_U                                      0x00000805
#define HAL_CLK_GCC_GPLL6_USER_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL6_L_VALUE                                         0x0000002D
#define HAL_CLK_GCC_GPLL6_ALPHA_VALUE                                     0x0000D555
#define HAL_CLK_GCC_GPLL7_CONFIG_CTL                                      0x20485699
#define HAL_CLK_GCC_GPLL7_CONFIG_CTL_U                                    0x00002261
#define HAL_CLK_GCC_GPLL7_CONFIG_CTL_U1                                   0x329A699C
#define HAL_CLK_GCC_GPLL7_TEST_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL7_TEST_CTL_U                                      0x00000000
#define HAL_CLK_GCC_GPLL7_TEST_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL7_USER_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL7_USER_CTL_U                                      0x00000805
#define HAL_CLK_GCC_GPLL7_USER_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL7_L_VALUE                                         0x00000035
#define HAL_CLK_GCC_GPLL7_ALPHA_VALUE                                     0x0000F555
#define HAL_CLK_GCC_GPLL8_CONFIG_CTL                                      0x20485699
#define HAL_CLK_GCC_GPLL8_CONFIG_CTL_U                                    0x00002261
#define HAL_CLK_GCC_GPLL8_CONFIG_CTL_U1                                   0x329A699C
#define HAL_CLK_GCC_GPLL8_TEST_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL8_TEST_CTL_U                                      0x00000000
#define HAL_CLK_GCC_GPLL8_TEST_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL8_USER_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL8_USER_CTL_U                                      0x00000805
#define HAL_CLK_GCC_GPLL8_USER_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL8_L_VALUE                                         0x00000024
#define HAL_CLK_GCC_GPLL8_ALPHA_VALUE                                     0x00007555
#define HAL_CLK_GCC_GPLL9_CONFIG_CTL                                      0x20485699
#define HAL_CLK_GCC_GPLL9_CONFIG_CTL_U                                    0x00002261
#define HAL_CLK_GCC_GPLL9_CONFIG_CTL_U1                                   0x329A699C
#define HAL_CLK_GCC_GPLL9_TEST_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL9_TEST_CTL_U                                      0x00000000
#define HAL_CLK_GCC_GPLL9_TEST_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL9_USER_CTL                                        0x00000000
#define HAL_CLK_GCC_GPLL9_USER_CTL_U                                      0x00000805
#define HAL_CLK_GCC_GPLL9_USER_CTL_U1                                     0x00000000
#define HAL_CLK_GCC_GPLL9_L_VALUE                                         0x0000002A
#define HAL_CLK_GCC_GPLL9_ALPHA_VALUE                                     0x00001555
#define HAL_CLK_GPU_CC_GPU_CC_PLL0_CONFIG_CTL                             0x20485699
#define HAL_CLK_GPU_CC_GPU_CC_PLL0_CONFIG_CTL_U                           0x00002261
#define HAL_CLK_GPU_CC_GPU_CC_PLL0_CONFIG_CTL_U1                          0x329A699C
#define HAL_CLK_GPU_CC_GPU_CC_PLL0_TEST_CTL                               0x00000000
#define HAL_CLK_GPU_CC_GPU_CC_PLL0_TEST_CTL_U                             0x00000000
#define HAL_CLK_GPU_CC_GPU_CC_PLL0_TEST_CTL_U1                            0x00000000
#define HAL_CLK_GPU_CC_GPU_CC_PLL0_USER_CTL                               0x00000000
#define HAL_CLK_GPU_CC_GPU_CC_PLL0_USER_CTL_U                             0x00000805
#define HAL_CLK_GPU_CC_GPU_CC_PLL0_USER_CTL_U1                            0x00000000
#define HAL_CLK_GPU_CC_GPU_CC_PLL0_L_VALUE_NOMINAL                        0x0000003D
#define HAL_CLK_GPU_CC_GPU_CC_PLL0_ALPHA_VALUE_NOMINAL                    0x00002555
#define HAL_CLK_GPU_CC_GPU_CC_PLL1_CONFIG_CTL                             0x20485699
#define HAL_CLK_GPU_CC_GPU_CC_PLL1_CONFIG_CTL_U                           0x00002261
#define HAL_CLK_GPU_CC_GPU_CC_PLL1_CONFIG_CTL_U1                          0x329A699C
#define HAL_CLK_GPU_CC_GPU_CC_PLL1_TEST_CTL                               0x00000000
#define HAL_CLK_GPU_CC_GPU_CC_PLL1_TEST_CTL_U                             0x00000000
#define HAL_CLK_GPU_CC_GPU_CC_PLL1_TEST_CTL_U1                            0x00000000
#define HAL_CLK_GPU_CC_GPU_CC_PLL1_USER_CTL                               0x00000000
#define HAL_CLK_GPU_CC_GPU_CC_PLL1_USER_CTL_U                             0x00000805
#define HAL_CLK_GPU_CC_GPU_CC_PLL1_USER_CTL_U1                            0x00000000
#define HAL_CLK_GPU_CC_GPU_CC_PLL1_L_VALUE                                0x0000001A
#define HAL_CLK_GPU_CC_GPU_CC_PLL1_ALPHA_VALUE                            0x00000AAA
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_PLL_CONFIG_CTL                  0x20485699
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_PLL_CONFIG_CTL_U                0x00002261
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_PLL_CONFIG_CTL_U1               0x329A699C
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_PLL_TEST_CTL                    0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_PLL_TEST_CTL_U                  0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_PLL_TEST_CTL_U1                 0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_PLL_USER_CTL                    0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_PLL_USER_CTL_U                  0x00000805
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_PLL_USER_CTL_U1                 0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_PLL_L_VALUE                     0x00000020
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_PLL_ALPHA_VALUE                 0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_RO_PLL_CONFIG_CTL               0x60008F64
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_RO_PLL_CONFIG_CTL_U             0x0001C808
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_RO_PLL_CONFIG_CTL_U1            0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_RO_PLL_CONFIG_CTL_U2            0x04000780
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_RO_PLL_TEST_CTL                 0x0088C496
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_RO_PLL_TEST_CTL_U               0x60000000
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_RO_PLL_TEST_CTL_U1              0x44210030
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_RO_PLL_TEST_CTL_U2              0x00000398
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_RO_PLL_USER_CTL                 0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_RO_PLL_USER_CTL_U               0x00E50002
#define HAL_CLK_LPASS_AON_CC_LPASS_AON_CC_RO_PLL_L_VALUE                  0x00000493
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_CONFIG_CTL                 0x20485699
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_CONFIG_CTL_U               0x00002261
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_CONFIG_CTL_U1              0x329A699C
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_TEST_CTL                   0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_TEST_CTL_U                 0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_TEST_CTL_U1                0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_USER_CTL                   0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_USER_CTL_U                 0x00000805
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_USER_CTL_U1                0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_L_VALUE_MINSVS             0x00000014
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_ALPHA_VALUE_MINSVS         0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_L_VALUE_LOWSVS             0x0000001E
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_ALPHA_VALUE_LOWSVS         0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_L_VALUE_SVS                0x00000028
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_ALPHA_VALUE_SVS            0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_L_VALUE_SVS_L1             0x00000031
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_ALPHA_VALUE_SVS_L1         0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_L_VALUE_NOMINAL            0x0000003D
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_ALPHA_VALUE_NOMINAL        0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_L_VALUE_NOMINAL_L1         0x00000045
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_ALPHA_VALUE_NOMINAL_L1     0x00000000
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_L_VALUE_TURBO              0x00000049
#define HAL_CLK_LPASS_AON_CC_LPASS_QDSP6SS_PLL_ALPHA_VALUE_TURBO          0x00000000
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_V1_CONFIG_CTL           0x08200920
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_V1_CONFIG_CTL_U         0x05008001
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_V1_CONFIG_CTL_U1        0x00000000
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_V1_TEST_CTL             0x00000000
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_V1_TEST_CTL_U           0x00000000
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_V1_TEST_CTL_U1          0x00000000
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_V1_USER_CTL             0x00000000
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_V1_USER_CTL_U           0x00000000
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_V1_USER_CTL_U1          0x00000000
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_CONFIG_CTL              0x08200920
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_CONFIG_CTL_U            0x05002005
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_CONFIG_CTL_U1           0x00000000
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_TEST_CTL                0x00000000
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_TEST_CTL_U              0x00000000
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_TEST_CTL_U1             0x00000000
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_USER_CTL                0x00000000
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_USER_CTL_U              0x00000000
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_USER_CTL_U1             0x00000000
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_L_VALUE                 0x0000003B
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_M_VALUE                 0x000000FF
#define HAL_CLK_LPASS_AUDIO_CC_LPASS_AUDIO_CC_PLL_N_VALUE                 0x00000005
#define HAL_CLK_LPASS_CORE_CC_LPASS_LPAAUDIO_DIG_PLL_CONFIG_CTL           0x20485699
#define HAL_CLK_LPASS_CORE_CC_LPASS_LPAAUDIO_DIG_PLL_CONFIG_CTL_U         0x00002261
#define HAL_CLK_LPASS_CORE_CC_LPASS_LPAAUDIO_DIG_PLL_CONFIG_CTL_U1        0x329A699C
#define HAL_CLK_LPASS_CORE_CC_LPASS_LPAAUDIO_DIG_PLL_TEST_CTL             0x00000000
#define HAL_CLK_LPASS_CORE_CC_LPASS_LPAAUDIO_DIG_PLL_TEST_CTL_U           0x00000000
#define HAL_CLK_LPASS_CORE_CC_LPASS_LPAAUDIO_DIG_PLL_TEST_CTL_U1          0x00000000
#define HAL_CLK_LPASS_CORE_CC_LPASS_LPAAUDIO_DIG_PLL_USER_CTL             0x00000000
#define HAL_CLK_LPASS_CORE_CC_LPASS_LPAAUDIO_DIG_PLL_USER_CTL_U           0x00000805
#define HAL_CLK_LPASS_CORE_CC_LPASS_LPAAUDIO_DIG_PLL_USER_CTL_U1          0x00000000
#define HAL_CLK_LPASS_CORE_CC_LPASS_LPAAUDIO_DIG_PLL_L_VALUE              0x00000020
#define HAL_CLK_LPASS_CORE_CC_LPASS_LPAAUDIO_DIG_PLL_ALPHA_VALUE          0x00000000
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_CONFIG_CTL                             0x20485699
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_CONFIG_CTL_U                           0x00002261
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_CONFIG_CTL_U1                          0x329A699C
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_TEST_CTL                               0x00000000
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_TEST_CTL_U                             0x00000000
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_TEST_CTL_U1                            0x00000000
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_USER_CTL                               0x00000000
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_USER_CTL_U                             0x00000805
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_USER_CTL_U1                            0x00000000
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_L_VALUE_LOWSVS                         0x0000001F
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_ALPHA_VALUE_LOWSVS                     0x00004000
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_V2_L_VALUE_SVS                         0x0000002A
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_V2_ALPHA_VALUE_SVS                     0x00004AAA
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_V1_L_VALUE_SVS                         0x00000030
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_V1_ALPHA_VALUE_SVS                     0x00008AAA
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_L_VALUE_SVS_L1                         0x00000037
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_ALPHA_VALUE_SVS_L1                     0x00008555
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_V2_L_VALUE_NOMINAL                     0x0000004C
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_V2_ALPHA_VALUE_NOMINAL                 0x00000AAA
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_V1_L_VALUE_NOMINAL                     0x00000058
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_V1_ALPHA_VALUE_NOMINAL                 0x00008AAA
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_V2_L_VALUE_TURBO                       0x0000005F
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_V2_ALPHA_VALUE_TURBO                   0x0000D555
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_L_VALUE_TURBO                          0x00000068
#define HAL_CLK_NPU_CC_NPU_CC_PLL0_ALPHA_VALUE_TURBO                      0x00002AAA
#define HAL_CLK_NPU_CC_NPU_CC_PLL1_CONFIG_CTL                             0x20485699
#define HAL_CLK_NPU_CC_NPU_CC_PLL1_CONFIG_CTL_U                           0x00002261
#define HAL_CLK_NPU_CC_NPU_CC_PLL1_CONFIG_CTL_U1                          0x329A699C
#define HAL_CLK_NPU_CC_NPU_CC_PLL1_TEST_CTL                               0x00000000
#define HAL_CLK_NPU_CC_NPU_CC_PLL1_TEST_CTL_U                             0x00000000
#define HAL_CLK_NPU_CC_NPU_CC_PLL1_TEST_CTL_U1                            0x00000000
#define HAL_CLK_NPU_CC_NPU_CC_PLL1_USER_CTL                               0x00000000
#define HAL_CLK_NPU_CC_NPU_CC_PLL1_USER_CTL_U                             0x00000805
#define HAL_CLK_NPU_CC_NPU_CC_PLL1_USER_CTL_U1                            0x00000000
#define HAL_CLK_NPU_CC_NPU_CC_PLL1_L_VALUE                                0x0000004E
#define HAL_CLK_NPU_CC_NPU_CC_PLL1_ALPHA_VALUE                            0x00002000
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_CONFIG_CTL                            0x20485699
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_CONFIG_CTL_U                          0x00002261
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_CONFIG_CTL_U1                         0x329A699C
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_TEST_CTL                              0x00000000
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_TEST_CTL_U                            0x00000000
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_TEST_CTL_U1                           0x00000000
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_USER_CTL                              0x00000000
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_USER_CTL_U                            0x00000805
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_USER_CTL_U1                           0x00000000
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_L_VALUE_LOWSVS                        0x0000000F
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_ALPHA_VALUE_LOWSVS                    0x0000A000
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_L_VALUE_SVS                           0x00000014
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_ALPHA_VALUE_SVS                       0x0000D555
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_L_VALUE_SVS_L1                        0x0000001A
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_ALPHA_VALUE_SVS_L1                    0x00000AAA
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_L_VALUE_NOMINAL                       0x00000022
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_ALPHA_VALUE_NOMINAL                   0x00006000
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_L_VALUE_TURBO                         0x00000029
#define HAL_CLK_NPU_CC_NPU_Q6SS_PLL_ALPHA_VALUE_TURBO                     0x0000AAAA
#define HAL_CLK_SCC_SCC_PLL_CONFIG_CTL                                    0x20485699
#define HAL_CLK_SCC_SCC_PLL_CONFIG_CTL_U                                  0x00002261
#define HAL_CLK_SCC_SCC_PLL_CONFIG_CTL_U1                                 0x329A699C
#define HAL_CLK_SCC_SCC_PLL_TEST_CTL                                      0x00000000
#define HAL_CLK_SCC_SCC_PLL_TEST_CTL_U                                    0x00000000
#define HAL_CLK_SCC_SCC_PLL_TEST_CTL_U1                                   0x00000000
#define HAL_CLK_SCC_SCC_PLL_USER_CTL                                      0x00000000
#define HAL_CLK_SCC_SCC_PLL_USER_CTL_U                                    0x00000805
#define HAL_CLK_SCC_SCC_PLL_USER_CTL_U1                                   0x00000000
#define HAL_CLK_SCC_SCC_PLL_L_VALUE                                       0x0000001F
#define HAL_CLK_SCC_SCC_PLL_ALPHA_VALUE                                   0x00004000
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_CONFIG_CTL                            0x20485699
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_CONFIG_CTL_U                          0x00002261
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_CONFIG_CTL_U1                         0x329A699C
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_TEST_CTL                              0x00000000
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_TEST_CTL_U                            0x00000000
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_TEST_CTL_U1                           0x00000000
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_USER_CTL                              0x00000000
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_USER_CTL_U                            0x00000805
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_USER_CTL_U1                           0x00000000
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_L_VALUE_MINSVS                        0x0000000E
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_ALPHA_VALUE_MINSVS                    0x000002AA
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_L_VALUE_LOWSVS                        0x00000014
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_ALPHA_VALUE_LOWSVS                    0x00000000
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_L_VALUE_SVS                           0x00000019
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_ALPHA_VALUE_SVS                       0x0000FD55
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_L_VALUE_SVS_L1                        0x00000021
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_ALPHA_VALUE_SVS_L1                    0x00000555
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_L_VALUE_NOMINAL                       0x00000029
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_ALPHA_VALUE_NOMINAL                   0x0000FAAA
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_L_VALUE_NOMINAL_L1                    0x00000030
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_ALPHA_VALUE_NOMINAL_L1                0x00000555
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_L_VALUE_TURBO                         0x00000033
#define HAL_CLK_SCC_SSC_QDSP6SS_PLL_ALPHA_VALUE_TURBO                     0x0000FAAA
#define HAL_CLK_TURING_CC_PLL2_CONFIG_CTL                                 0x20485699
#define HAL_CLK_TURING_CC_PLL2_CONFIG_CTL_U                               0x00002261
#define HAL_CLK_TURING_CC_PLL2_CONFIG_CTL_U1                              0x329A699C
#define HAL_CLK_TURING_CC_PLL2_TEST_CTL                                   0x00000000
#define HAL_CLK_TURING_CC_PLL2_TEST_CTL_U                                 0x00000000
#define HAL_CLK_TURING_CC_PLL2_TEST_CTL_U1                                0x00000000
#define HAL_CLK_TURING_CC_PLL2_USER_CTL                                   0x00000000
#define HAL_CLK_TURING_CC_PLL2_USER_CTL_U                                 0x00000805
#define HAL_CLK_TURING_CC_PLL2_USER_CTL_U1                                0x00000000
#define HAL_CLK_TURING_CC_PLL2_L_VALUE_LOWSVS                             0x00000015
#define HAL_CLK_TURING_CC_PLL2_ALPHA_VALUE_LOWSVS                         0x00000000
#define HAL_CLK_TURING_CC_PLL2_L_VALUE_SVS                                0x0000001C
#define HAL_CLK_TURING_CC_PLL2_ALPHA_VALUE_SVS                            0x00000000
#define HAL_CLK_TURING_CC_PLL2_L_VALUE_SVS_L1                             0x00000022
#define HAL_CLK_TURING_CC_PLL2_ALPHA_VALUE_SVS_L1                         0x00000000
#define HAL_CLK_TURING_CC_PLL2_L_VALUE_NOMINAL                            0x0000002B
#define HAL_CLK_TURING_CC_PLL2_ALPHA_VALUE_NOMINAL                        0x00000000
#define HAL_CLK_TURING_CC_TURING_DIG_PLL_CONFIG_CTL                       0x20485699
#define HAL_CLK_TURING_CC_TURING_DIG_PLL_CONFIG_CTL_U                     0x00002261
#define HAL_CLK_TURING_CC_TURING_DIG_PLL_CONFIG_CTL_U1                    0x329A699C
#define HAL_CLK_TURING_CC_TURING_DIG_PLL_TEST_CTL                         0x00000000
#define HAL_CLK_TURING_CC_TURING_DIG_PLL_TEST_CTL_U                       0x00000000
#define HAL_CLK_TURING_CC_TURING_DIG_PLL_TEST_CTL_U1                      0x00000000
#define HAL_CLK_TURING_CC_TURING_DIG_PLL_USER_CTL                         0x00000000
#define HAL_CLK_TURING_CC_TURING_DIG_PLL_USER_CTL_U                       0x00000805
#define HAL_CLK_TURING_CC_TURING_DIG_PLL_USER_CTL_U1                      0x00000000
#define HAL_CLK_TURING_CC_TURING_DIG_PLL_L_VALUE                          0x00000020
#define HAL_CLK_TURING_CC_TURING_DIG_PLL_ALPHA_VALUE                      0x00000000
#define HAL_CLK_TURING_CC_TURING_DIG_PLL1_CONFIG_CTL                      0x20485699
#define HAL_CLK_TURING_CC_TURING_DIG_PLL1_CONFIG_CTL_U                    0x00002261
#define HAL_CLK_TURING_CC_TURING_DIG_PLL1_CONFIG_CTL_U1                   0x329A699C
#define HAL_CLK_TURING_CC_TURING_DIG_PLL1_TEST_CTL                        0x00000000
#define HAL_CLK_TURING_CC_TURING_DIG_PLL1_TEST_CTL_U                      0x00000000
#define HAL_CLK_TURING_CC_TURING_DIG_PLL1_TEST_CTL_U1                     0x00000000
#define HAL_CLK_TURING_CC_TURING_DIG_PLL1_USER_CTL                        0x00000000
#define HAL_CLK_TURING_CC_TURING_DIG_PLL1_USER_CTL_U                      0x00000805
#define HAL_CLK_TURING_CC_TURING_DIG_PLL1_USER_CTL_U1                     0x00000000
#define HAL_CLK_TURING_CC_TURING_DIG_PLL1_L_VALUE                         0x0000001B
#define HAL_CLK_TURING_CC_TURING_DIG_PLL1_ALPHA_VALUE                     0x00005800
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_CONFIG_CTL                   0x20485699
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_CONFIG_CTL_U                 0x00002261
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_CONFIG_CTL_U1                0x329A699C
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_TEST_CTL                     0x00000000
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_TEST_CTL_U                   0x00000000
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_TEST_CTL_U1                  0x00000000
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_USER_CTL                     0x00000000
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_USER_CTL_U                   0x00000805
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_USER_CTL_U1                  0x00000000
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_L_VALUE_MINSVS               0x00000013
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_ALPHA_VALUE_MINSVS           0x00000000
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_L_VALUE_LOWSVS               0x0000001E
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_ALPHA_VALUE_LOWSVS           0x00000000
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_L_VALUE_SVS                  0x00000028
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_ALPHA_VALUE_SVS              0x00000000
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_L_VALUE_SVS_L1               0x00000032
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_ALPHA_VALUE_SVS_L1           0x00000000
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_L_VALUE_NOMINAL              0x0000003D
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_ALPHA_VALUE_NOMINAL          0x00000000
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_L_VALUE_NOMINAL_L1           0x00000045
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_ALPHA_VALUE_NOMINAL_L1       0x00000000
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_L_VALUE_TURBO                0x00000049
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_ALPHA_VALUE_TURBO            0x00000000
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_L_VALUE_TURBO_L1             0x0000004E
#define HAL_CLK_TURING_CC_TURING_QDSP6SS_PLL_ALPHA_VALUE_TURBO_L1         0x00000000
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_CONFIG_CTL                            0x20485699
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_CONFIG_CTL_U                          0x00002261
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_CONFIG_CTL_U1                         0x329A699C
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_TEST_CTL                              0x00000000
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_TEST_CTL_U                            0x00000000
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_TEST_CTL_U1                           0x00000000
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_USER_CTL                              0x00000000
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_USER_CTL_U                            0x00000805
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_USER_CTL_U1                           0x00000000
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_L_VALUE_LOWSVS                        0x00000025
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_ALPHA_VALUE_LOWSVS                    0x00008000
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_L_VALUE_SVS                           0x00000034
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_ALPHA_VALUE_SVS                       0x0000D000
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_L_VALUE_SVS_L1                        0x00000039
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_ALPHA_VALUE_SVS_L1                    0x00003000
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_L_VALUE_NOMINAL                       0x00000045
#define HAL_CLK_VIDEO_CC_VIDEO_PLL0_ALPHA_VALUE_NOMINAL                   0x00006000
#define HAL_CLK_VIDEO_CC_VIDEO_PLL1_CONFIG_CTL                            0x20485699
#define HAL_CLK_VIDEO_CC_VIDEO_PLL1_CONFIG_CTL_U                          0x00002261
#define HAL_CLK_VIDEO_CC_VIDEO_PLL1_CONFIG_CTL_U1                         0x329A699C
#define HAL_CLK_VIDEO_CC_VIDEO_PLL1_TEST_CTL                              0x00000000
#define HAL_CLK_VIDEO_CC_VIDEO_PLL1_TEST_CTL_U                            0x00000000
#define HAL_CLK_VIDEO_CC_VIDEO_PLL1_TEST_CTL_U1                           0x00000000
#define HAL_CLK_VIDEO_CC_VIDEO_PLL1_USER_CTL                              0x00000000
#define HAL_CLK_VIDEO_CC_VIDEO_PLL1_USER_CTL_U                            0x00000805
#define HAL_CLK_VIDEO_CC_VIDEO_PLL1_USER_CTL_U1                           0x00000000
#define HAL_CLK_VIDEO_CC_VIDEO_PLL1_V1_L_VALUE_SVS                        0x00000036
#define HAL_CLK_VIDEO_CC_VIDEO_PLL1_V1_ALPHA_VALUE_SVS                    0x00002AAA
#define HAL_CLK_VIDEO_CC_VIDEO_PLL1_L_VALUE_SVS_L1                        0x00000039
#define HAL_CLK_VIDEO_CC_VIDEO_PLL1_ALPHA_VALUE_SVS_L1                    0x00003000
#define HAL_CLK_VIDEO_CC_VIDEO_PLL1_L_VALUE_NOMINAL                       0x00000045
#define HAL_CLK_VIDEO_CC_VIDEO_PLL1_ALPHA_VALUE_NOMINAL                   0x00006000

#endif /* __HALCLKPLLSETTINGS_H__ */

