#ifndef __SECBOOT_HWIO_H__
#define __SECBOOT_HWIO_H__
/*
===========================================================================
*/
/**
  @file secboot_hwio.h
  @brief Auto-generated HWIO interface include file.

  Reference chip release:
    SDM855 (Hana) [hana_v1.0_p1q0r10]
 
  This file contains HWIO register definitions for the following modules:
    SECURITY_CONTROL_CORE
    TCSR_TCSR_REGS

  'Include' filters applied: 
  'Exclude' filters applied: DUMMY RESERVED 
*/
/*
  ===========================================================================

  Copyright (c) 2017 Qualcomm Technologies, Inc.
  All Rights Reserved.
  Confidential and Proprietary - Qualcomm Technologies, Inc.

  Export of this technology or software is regulated by the U.S. Government.
  Diversion contrary to U.S. law prohibited.

  All ideas, data and information contained in or disclosed by
  this document are confidential and proprietary information of
  Qualcomm Technologies, Inc. and all rights therein are expressly reserved.
  By accepting this material the recipient agrees that this material
  and the information contained therein are held in confidence and in
  trust and will not be used, copied, reproduced in whole or in part,
  nor its contents revealed in any manner to others without the express
  written permission of Qualcomm Technologies, Inc.

  ===========================================================================

  $Header: //components/rel/boot.xf/3.2/QcomPkg/SocPkg/Include/secboot_hwio.h#3 $
  $DateTime: 2018/08/09 14:39:37 $
  $Author: pwbldsvc $

  ===========================================================================
*/

#include "msmhwiobase.h"

/*----------------------------------------------------------------------------
 * MODULE: SECURITY_CONTROL_CORE
 *--------------------------------------------------------------------------*/

#define SECURITY_CONTROL_CORE_REG_BASE                                                        (SECURITY_CONTROL_BASE      + 0x00000000)
#define SECURITY_CONTROL_CORE_REG_BASE_PHYS                                                   (SECURITY_CONTROL_BASE_PHYS + 0x00000000)

#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_ADDR(n)                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000000 + 0x4 * (n))
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_PHYS(n)                                               (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000000 + 0x4 * (n))
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_MAXn                                                          71
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_ADDR(n), HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_RMSK)
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_ADDR(n), mask)
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_CRI_CM_PRIVATE_BMSK                                   0xffffffff
#define HWIO_QFPROM_RAW_CRI_CM_PRIVATEn_CRI_CM_PRIVATE_SHFT                                          0x0

#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000120)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000120)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR, HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_RMSK)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_IN)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_RSVD0_BMSK                                           0xfffffff0
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_RSVD0_SHFT                                                  0x4
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ROOT_CERT_ACTIVATION_LIST_BMSK                              0xf
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ROOT_CERT_ACTIVATION_LIST_SHFT                              0x0

#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000124)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000124)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR, HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_RMSK)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_IN)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_RSVD1_BMSK                                           0xfffffffe
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_RSVD1_SHFT                                                  0x1
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_CURRENT_UIE_KEY_SEL_BMSK                                    0x1
#define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_CURRENT_UIE_KEY_SEL_SHFT                                    0x0

#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000128)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000128)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR, HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_RMSK)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_IN)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_RSVD0_BMSK                                           0xfffffff0
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_RSVD0_SHFT                                                  0x4
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ROOT_CERT_REVOCATION_LIST_BMSK                              0xf
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ROOT_CERT_REVOCATION_LIST_SHFT                              0x0

#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000012c)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000012c)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR, HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_RMSK)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_IN)
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_RSVD0_BMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_RSVD0_SHFT                                                  0x0

#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000130)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_PHYS                                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000130)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR, HWIO_QFPROM_RAW_PTE_ROW0_LSB_RMSK)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW0_LSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_PTE_DATA0_BMSK                                           0xe0000000
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_PTE_DATA0_SHFT                                                 0x1d
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_MACCHIATO_EN_BMSK                                        0x10000000
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_MACCHIATO_EN_SHFT                                              0x1c
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_FEATURE_ID_BMSK                                           0xff00000
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_FEATURE_ID_SHFT                                                0x14
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_JTAG_ID_BMSK                                                0xfffff
#define HWIO_QFPROM_RAW_PTE_ROW0_LSB_JTAG_ID_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000134)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_PHYS                                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000134)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR, HWIO_QFPROM_RAW_PTE_ROW0_MSB_RMSK)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW0_MSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_PTE_DATA1_BMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW0_MSB_PTE_DATA1_SHFT                                                  0x0

#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000138)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_PHYS                                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000138)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR, HWIO_QFPROM_RAW_PTE_ROW1_LSB_RMSK)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW1_LSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_SERIAL_NUM_BMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW1_LSB_SERIAL_NUM_SHFT                                                 0x0

#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000013c)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_PHYS                                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000013c)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR, HWIO_QFPROM_RAW_PTE_ROW1_MSB_RMSK)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW1_MSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_PTE_DATA1_BMSK                                           0xffff0000
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_PTE_DATA1_SHFT                                                 0x10
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_CHIP_ID_BMSK                                                 0xffff
#define HWIO_QFPROM_RAW_PTE_ROW1_MSB_CHIP_ID_SHFT                                                    0x0

#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000140)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_PHYS                                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000140)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR, HWIO_QFPROM_RAW_PTE_ROW2_LSB_RMSK)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_PTE_DATA0_BMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW2_LSB_PTE_DATA0_SHFT                                                  0x0

#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000144)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_PHYS                                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000144)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR, HWIO_QFPROM_RAW_PTE_ROW2_MSB_RMSK)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_PTE_DATA1_BMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW2_MSB_PTE_DATA1_SHFT                                                  0x0

#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000148)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_PHYS                                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000148)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR, HWIO_QFPROM_RAW_PTE_ROW3_LSB_RMSK)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW3_LSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_PTE_DATA0_BMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW3_LSB_PTE_DATA0_SHFT                                                  0x0

#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000014c)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_PHYS                                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000014c)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR, HWIO_QFPROM_RAW_PTE_ROW3_MSB_RMSK)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW3_MSB_IN)
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_PTE_DATA1_BMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_PTE_ROW3_MSB_PTE_DATA1_SHFT                                                  0x0

#define HWIO_QFPROM_RAW_RD_PERM_LSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000150)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PHYS                                                      (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000150)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_RAW_RD_PERM_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_RD_PERM_LSB_ADDR, HWIO_QFPROM_RAW_RD_PERM_LSB_RMSK)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_RD_PERM_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_RD_PERM_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_RD_PERM_LSB_ADDR,m,v,HWIO_QFPROM_RAW_RD_PERM_LSB_IN)
#define HWIO_QFPROM_RAW_RD_PERM_LSB_RSVD0_BMSK                                                0x80000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_RSVD0_SHFT                                                      0x1f
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG30_BMSK                                      0x40000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG30_SHFT                                            0x1e
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG29_BMSK                                      0x20000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG29_SHFT                                            0x1d
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG28_BMSK                                      0x10000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG28_SHFT                                            0x1c
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG27_BMSK                                       0x8000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG27_SHFT                                            0x1b
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG26_BMSK                                       0x4000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SPARE_REG26_SHFT                                            0x1a
#define HWIO_QFPROM_RAW_RD_PERM_LSB_USER_DATA_KEY_BMSK                                         0x2000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_USER_DATA_KEY_SHFT                                              0x19
#define HWIO_QFPROM_RAW_RD_PERM_LSB_IMAGE_ENCR_KEY1_BMSK                                       0x1000000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_IMAGE_ENCR_KEY1_SHFT                                            0x18
#define HWIO_QFPROM_RAW_RD_PERM_LSB_BOOT_ROM_PATCH_BMSK                                         0x800000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_BOOT_ROM_PATCH_SHFT                                             0x17
#define HWIO_QFPROM_RAW_RD_PERM_LSB_SEC_KEY_DERIVATION_KEY_BMSK                                 0x400000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_SEC_KEY_DERIVATION_KEY_SHFT                                     0x16
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PRI_KEY_DERIVATION_KEY_BMSK                                 0x200000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PRI_KEY_DERIVATION_KEY_SHFT                                     0x15
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SEC_BOOT_BMSK                                           0x100000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_SEC_BOOT_SHFT                                               0x14
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_IMAGE_ENCR_KEY_BMSK                                      0x80000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_IMAGE_ENCR_KEY_SHFT                                         0x13
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG18_BMSK                                          0x40000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG18_SHFT                                             0x12
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG17_BMSK                                          0x20000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG17_SHFT                                             0x11
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG16_BMSK                                          0x10000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_QC_SPARE_REG16_SHFT                                             0x10
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CM_FEAT_CONFIG_BMSK                                           0x8000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CM_FEAT_CONFIG_SHFT                                              0xf
#define HWIO_QFPROM_RAW_RD_PERM_LSB_MEM_CONFIG_BMSK                                               0x4000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_MEM_CONFIG_SHFT                                                  0xe
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CALIB_BMSK                                                    0x2000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CALIB_SHFT                                                       0xd
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PK_HASH0_BMSK                                                 0x1000
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PK_HASH0_SHFT                                                    0xc
#define HWIO_QFPROM_RAW_RD_PERM_LSB_FEAT_CONFIG_BMSK                                               0x800
#define HWIO_QFPROM_RAW_RD_PERM_LSB_FEAT_CONFIG_SHFT                                                 0xb
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_CONFIG_BMSK                                                0x400
#define HWIO_QFPROM_RAW_RD_PERM_LSB_OEM_CONFIG_SHFT                                                  0xa
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_4_BMSK                                           0x200
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_4_SHFT                                             0x9
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_3_BMSK                                           0x100
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_3_SHFT                                             0x8
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_2_BMSK                                            0x80
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_2_SHFT                                             0x7
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_1_BMSK                                            0x40
#define HWIO_QFPROM_RAW_RD_PERM_LSB_ANTI_ROLLBACK_1_SHFT                                             0x6
#define HWIO_QFPROM_RAW_RD_PERM_LSB_FEC_EN_BMSK                                                     0x20
#define HWIO_QFPROM_RAW_RD_PERM_LSB_FEC_EN_SHFT                                                      0x5
#define HWIO_QFPROM_RAW_RD_PERM_LSB_WR_PERM_BMSK                                                    0x10
#define HWIO_QFPROM_RAW_RD_PERM_LSB_WR_PERM_SHFT                                                     0x4
#define HWIO_QFPROM_RAW_RD_PERM_LSB_RD_PERM_BMSK                                                     0x8
#define HWIO_QFPROM_RAW_RD_PERM_LSB_RD_PERM_SHFT                                                     0x3
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PTE_BMSK                                                         0x4
#define HWIO_QFPROM_RAW_RD_PERM_LSB_PTE_SHFT                                                         0x2
#define HWIO_QFPROM_RAW_RD_PERM_LSB_MRC_2_0_BMSK                                                     0x2
#define HWIO_QFPROM_RAW_RD_PERM_LSB_MRC_2_0_SHFT                                                     0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CRI_CM_PRIVATE_BMSK                                              0x1
#define HWIO_QFPROM_RAW_RD_PERM_LSB_CRI_CM_PRIVATE_SHFT                                              0x0

#define HWIO_QFPROM_RAW_RD_PERM_MSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000154)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_PHYS                                                      (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000154)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_RAW_RD_PERM_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_RD_PERM_MSB_ADDR, HWIO_QFPROM_RAW_RD_PERM_MSB_RMSK)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_RD_PERM_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_RD_PERM_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_RD_PERM_MSB_ADDR,m,v,HWIO_QFPROM_RAW_RD_PERM_MSB_IN)
#define HWIO_QFPROM_RAW_RD_PERM_MSB_RSVD0_BMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_RD_PERM_MSB_RSVD0_SHFT                                                       0x0

#define HWIO_QFPROM_RAW_WR_PERM_LSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000158)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PHYS                                                      (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000158)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_RAW_WR_PERM_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_WR_PERM_LSB_ADDR, HWIO_QFPROM_RAW_WR_PERM_LSB_RMSK)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_WR_PERM_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_WR_PERM_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_WR_PERM_LSB_ADDR,m,v,HWIO_QFPROM_RAW_WR_PERM_LSB_IN)
#define HWIO_QFPROM_RAW_WR_PERM_LSB_RSVD0_BMSK                                                0x80000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_RSVD0_SHFT                                                      0x1f
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG30_BMSK                                      0x40000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG30_SHFT                                            0x1e
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG29_BMSK                                      0x20000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG29_SHFT                                            0x1d
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG28_BMSK                                      0x10000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG28_SHFT                                            0x1c
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG27_BMSK                                       0x8000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG27_SHFT                                            0x1b
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG26_BMSK                                       0x4000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SPARE_REG26_SHFT                                            0x1a
#define HWIO_QFPROM_RAW_WR_PERM_LSB_USER_DATA_KEY_BMSK                                         0x2000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_USER_DATA_KEY_SHFT                                              0x19
#define HWIO_QFPROM_RAW_WR_PERM_LSB_IMAGE_ENCR_KEY1_BMSK                                       0x1000000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_IMAGE_ENCR_KEY1_SHFT                                            0x18
#define HWIO_QFPROM_RAW_WR_PERM_LSB_BOOT_ROM_PATCH_BMSK                                         0x800000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_BOOT_ROM_PATCH_SHFT                                             0x17
#define HWIO_QFPROM_RAW_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_BMSK                                 0x400000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_SHFT                                     0x16
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PRI_KEY_DERIVATION_KEY_BMSK                                 0x200000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PRI_KEY_DERIVATION_KEY_SHFT                                     0x15
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SEC_BOOT_BMSK                                           0x100000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SEC_BOOT_SHFT                                               0x14
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_IMAGE_ENCR_KEY_BMSK                                      0x80000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_IMAGE_ENCR_KEY_SHFT                                         0x13
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG18_BMSK                                          0x40000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG18_SHFT                                             0x12
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG17_BMSK                                          0x20000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG17_SHFT                                             0x11
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG16_BMSK                                          0x10000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_QC_SPARE_REG16_SHFT                                             0x10
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CM_FEAT_CONFIG_BMSK                                           0x8000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CM_FEAT_CONFIG_SHFT                                              0xf
#define HWIO_QFPROM_RAW_WR_PERM_LSB_MEM_CONFIG_BMSK                                               0x4000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_MEM_CONFIG_SHFT                                                  0xe
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CALIB_BMSK                                                    0x2000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CALIB_SHFT                                                       0xd
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PK_HASH0_BMSK                                                 0x1000
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PK_HASH0_SHFT                                                    0xc
#define HWIO_QFPROM_RAW_WR_PERM_LSB_FEAT_CONFIG_BMSK                                               0x800
#define HWIO_QFPROM_RAW_WR_PERM_LSB_FEAT_CONFIG_SHFT                                                 0xb
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_CONFIG_BMSK                                                0x400
#define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_CONFIG_SHFT                                                  0xa
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_4_BMSK                                           0x200
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_4_SHFT                                             0x9
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_3_BMSK                                           0x100
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_3_SHFT                                             0x8
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_2_BMSK                                            0x80
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_2_SHFT                                             0x7
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_1_BMSK                                            0x40
#define HWIO_QFPROM_RAW_WR_PERM_LSB_ANTI_ROLLBACK_1_SHFT                                             0x6
#define HWIO_QFPROM_RAW_WR_PERM_LSB_FEC_EN_BMSK                                                     0x20
#define HWIO_QFPROM_RAW_WR_PERM_LSB_FEC_EN_SHFT                                                      0x5
#define HWIO_QFPROM_RAW_WR_PERM_LSB_WR_PERM_BMSK                                                    0x10
#define HWIO_QFPROM_RAW_WR_PERM_LSB_WR_PERM_SHFT                                                     0x4
#define HWIO_QFPROM_RAW_WR_PERM_LSB_RD_PERM_BMSK                                                     0x8
#define HWIO_QFPROM_RAW_WR_PERM_LSB_RD_PERM_SHFT                                                     0x3
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PTE_BMSK                                                         0x4
#define HWIO_QFPROM_RAW_WR_PERM_LSB_PTE_SHFT                                                         0x2
#define HWIO_QFPROM_RAW_WR_PERM_LSB_MRC_2_0_BMSK                                                     0x2
#define HWIO_QFPROM_RAW_WR_PERM_LSB_MRC_2_0_SHFT                                                     0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CRI_CM_PRIVATE_BMSK                                              0x1
#define HWIO_QFPROM_RAW_WR_PERM_LSB_CRI_CM_PRIVATE_SHFT                                              0x0

#define HWIO_QFPROM_RAW_WR_PERM_MSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000015c)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_PHYS                                                      (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000015c)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_RAW_WR_PERM_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_WR_PERM_MSB_ADDR, HWIO_QFPROM_RAW_WR_PERM_MSB_RMSK)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_WR_PERM_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_WR_PERM_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_WR_PERM_MSB_ADDR,m,v,HWIO_QFPROM_RAW_WR_PERM_MSB_IN)
#define HWIO_QFPROM_RAW_WR_PERM_MSB_RSVD0_BMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_WR_PERM_MSB_RSVD0_SHFT                                                       0x0

#define HWIO_QFPROM_RAW_FEC_EN_LSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000160)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_PHYS                                                       (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000160)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_FEC_EN_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_FEC_EN_LSB_ADDR, HWIO_QFPROM_RAW_FEC_EN_LSB_RMSK)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEC_EN_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEC_EN_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEC_EN_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEC_EN_LSB_IN)
#define HWIO_QFPROM_RAW_FEC_EN_LSB_RSVD0_BMSK                                                 0x80000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_RSVD0_SHFT                                                       0x1f
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION30_FEC_EN_BMSK                                       0x40000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION30_FEC_EN_SHFT                                             0x1e
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION29_FEC_EN_BMSK                                       0x20000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION29_FEC_EN_SHFT                                             0x1d
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION28_FEC_EN_BMSK                                       0x10000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION28_FEC_EN_SHFT                                             0x1c
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION27_FEC_EN_BMSK                                        0x8000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION27_FEC_EN_SHFT                                             0x1b
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION26_FEC_EN_BMSK                                        0x4000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION26_FEC_EN_SHFT                                             0x1a
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION25_FEC_EN_BMSK                                        0x2000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION25_FEC_EN_SHFT                                             0x19
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION24_FEC_EN_BMSK                                        0x1000000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION24_FEC_EN_SHFT                                             0x18
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION23_FEC_EN_BMSK                                         0x800000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION23_FEC_EN_SHFT                                             0x17
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION22_FEC_EN_BMSK                                         0x400000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION22_FEC_EN_SHFT                                             0x16
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION21_FEC_EN_BMSK                                         0x200000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION21_FEC_EN_SHFT                                             0x15
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION20_FEC_EN_BMSK                                         0x100000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION20_FEC_EN_SHFT                                             0x14
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION19_FEC_EN_BMSK                                          0x80000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION19_FEC_EN_SHFT                                             0x13
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION18_FEC_EN_BMSK                                          0x40000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION18_FEC_EN_SHFT                                             0x12
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION17_FEC_EN_BMSK                                          0x20000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION17_FEC_EN_SHFT                                             0x11
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION16_FEC_EN_BMSK                                          0x10000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION16_FEC_EN_SHFT                                             0x10
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION15_FEC_EN_BMSK                                           0x8000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION15_FEC_EN_SHFT                                              0xf
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION14_FEC_EN_BMSK                                           0x4000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION14_FEC_EN_SHFT                                              0xe
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION13_FEC_EN_BMSK                                           0x2000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION13_FEC_EN_SHFT                                              0xd
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION12_FEC_EN_BMSK                                           0x1000
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION12_FEC_EN_SHFT                                              0xc
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION11_FEC_EN_BMSK                                            0x800
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION11_FEC_EN_SHFT                                              0xb
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION10_FEC_EN_BMSK                                            0x400
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION10_FEC_EN_SHFT                                              0xa
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION9_FEC_EN_BMSK                                             0x200
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION9_FEC_EN_SHFT                                               0x9
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION8_FEC_EN_BMSK                                             0x100
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION8_FEC_EN_SHFT                                               0x8
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION7_FEC_EN_BMSK                                              0x80
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION7_FEC_EN_SHFT                                               0x7
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION6_FEC_EN_BMSK                                              0x40
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION6_FEC_EN_SHFT                                               0x6
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION5_FEC_EN_BMSK                                              0x20
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION5_FEC_EN_SHFT                                               0x5
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION4_FEC_EN_BMSK                                              0x10
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION4_FEC_EN_SHFT                                               0x4
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION3_FEC_EN_BMSK                                               0x8
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION3_FEC_EN_SHFT                                               0x3
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION2_FEC_EN_BMSK                                               0x4
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION2_FEC_EN_SHFT                                               0x2
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION1_FEC_EN_BMSK                                               0x2
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION1_FEC_EN_SHFT                                               0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION0_FEC_EN_BMSK                                               0x1
#define HWIO_QFPROM_RAW_FEC_EN_LSB_REGION0_FEC_EN_SHFT                                               0x0

#define HWIO_QFPROM_RAW_FEC_EN_MSB_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000164)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_PHYS                                                       (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000164)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_RMSK                                                       0xffffffff
#define HWIO_QFPROM_RAW_FEC_EN_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_FEC_EN_MSB_ADDR, HWIO_QFPROM_RAW_FEC_EN_MSB_RMSK)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEC_EN_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEC_EN_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEC_EN_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEC_EN_MSB_IN)
#define HWIO_QFPROM_RAW_FEC_EN_MSB_RSVD0_BMSK                                                 0xffffffff
#define HWIO_QFPROM_RAW_FEC_EN_MSB_RSVD0_SHFT                                                        0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000168)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_PHYS                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000168)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR, HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_RMSK)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_XBL0_BMSK                                         0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_XBL0_SHFT                                                0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000016c)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_PHYS                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000016c)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR, HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_RMSK)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_XBL1_BMSK                                         0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_XBL1_SHFT                                                0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000170)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_PHYS                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000170)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR, HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_RMSK)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_PIL_SUBSYSTEM_31_0_BMSK                           0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_PIL_SUBSYSTEM_31_0_SHFT                                  0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000174)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_PHYS                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000174)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR, HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_RMSK)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_XBL_SEC_BMSK                                      0xfe000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_XBL_SEC_SHFT                                            0x19
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_RPM_BMSK                                           0x1fe0000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_RPM_SHFT                                                0x11
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_TZ_BMSK                                              0x1ffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_TZ_SHFT                                                  0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000178)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_PHYS                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000178)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR, HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RMSK)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RSVD1_BMSK                                        0xc0000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RSVD1_SHFT                                              0x1e
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_TQS_HASH_ACTIVE_BMSK                              0x3e000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_TQS_HASH_ACTIVE_SHFT                                    0x19
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_BMSK                          0x1000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_SHFT                               0x18
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_PIL_SUBSYSTEM_47_32_BMSK                            0xffff00
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_PIL_SUBSYSTEM_47_32_SHFT                                 0x8
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_SAFESWITCH_BMSK                                         0xff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_SAFESWITCH_SHFT                                          0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000017c)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_PHYS                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000017c)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR, HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_RMSK)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_RSVD1_BMSK                                        0xf0000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_RSVD1_SHFT                                              0x1c
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_DEVICE_CFG_BMSK                                    0xffe0000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_DEVICE_CFG_SHFT                                         0x11
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_DEBUG_POLICY_BMSK                                    0x1f000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_DEBUG_POLICY_SHFT                                        0xc
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_HYPERVISOR_BMSK                                        0xfff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_HYPERVISOR_SHFT                                          0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000180)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_PHYS                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000180)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR, HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_RMSK)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_MSS_BMSK                                          0xffff0000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_MSS_SHFT                                                0x10
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_MBA_BMSK                                              0xffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_MBA_SHFT                                                 0x0

#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000184)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_PHYS                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000184)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR, HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_RMSK)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_IN)
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_SIMLOCK_BMSK                                      0x80000000
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_SIMLOCK_SHFT                                            0x1f
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_RSVD0_BMSK                                        0x7fffffff
#define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_RSVD0_SHFT                                               0x0

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000188)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PHYS                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000188)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR, HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                  0x80000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                        0x1f
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_BMSK                   0x40000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_SHFT                         0x1e
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_BMSK                            0x20000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_SHFT                                  0x1d
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_BMSK                         0x10000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_SHFT                               0x1c
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SP_DISABLE_BMSK                                    0x8000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SP_DISABLE_SHFT                                         0x1b
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_BMSK                                   0x4000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_SHFT                                        0x1a
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_RSVD2_BMSK                                         0x2000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_RSVD2_SHFT                                              0x19
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_BMSK               0x1000000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_SHFT                    0x18
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_ENABLE_BMSK               0x800000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_ENABLE_SHFT                   0x17
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_BMSK                                 0x400000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_SHFT                                     0x16
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_BMSK                          0x200000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_SHFT                              0x15
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_BMSK                           0x100000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_SHFT                               0x14
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_IMAGE_ENCRYPTION_ENABLE_BMSK                         0x80000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_IMAGE_ENCRYPTION_ENABLE_SHFT                            0x13
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ROOT_CERT_TOTAL_NUM_BMSK                             0x60000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ROOT_CERT_TOTAL_NUM_SHFT                                0x11
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_USB_TYPE_C_DISABLE_BMSK                          0x10000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_USB_TYPE_C_DISABLE_SHFT                             0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_LOG_DISABLE_BMSK                                  0x8000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_LOG_DISABLE_SHFT                                     0xf
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_WDOG_EN_BMSK                                          0x4000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_WDOG_EN_SHFT                                             0xe
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_RSVD1_BMSK                                            0x2000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_RSVD1_SHFT                                               0xd
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_FUSE_PROG_DISABLE_BMSK                             0x1000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_FUSE_PROG_DISABLE_SHFT                                0xc
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_RSVD0_BMSK                                             0xc00
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_RSVD0_SHFT                                               0xa
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_BMSK                                         0x3e0
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SHFT                                           0x5
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SDCC_MCLK_BOOT_FREQ_BMSK                                0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SDCC_MCLK_BOOT_FREQ_SHFT                                 0x4
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_BMSK                              0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_SHFT                              0x3
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_BMSK                                 0x4
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_SHFT                                 0x2
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_BMSK                                        0x2
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_SHFT                                        0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_BMSK                                     0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_SHFT                                     0x0

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000018c)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_PHYS                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000018c)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR, HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_RSVD0_BMSK                                        0xffffff00
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_RSVD0_SHFT                                               0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_BMSK                                 0x80
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_SHFT                                  0x7
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_BMSK                                 0x40
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_SHFT                                  0x6
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_BMSK                            0x20
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_SHFT                             0x5
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_BMSK                            0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_SHFT                             0x4
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_BMSK                             0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_SHFT                             0x3
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_BMSK                             0x4
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_SHFT                             0x2
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_BMSK                            0x2
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_SHFT                            0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_BMSK                            0x1
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_SHFT                            0x0

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000190)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_PHYS                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000190)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR, HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_BMSK                                        0xffff8000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_SHFT                                               0xf
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG30_SECURE_BMSK                           0x4000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG30_SECURE_SHFT                              0xe
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG29_SECURE_BMSK                           0x2000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG29_SECURE_SHFT                              0xd
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG28_SECURE_BMSK                           0x1000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG28_SECURE_SHFT                              0xc
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG27_SECURE_BMSK                            0x800
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG27_SECURE_SHFT                              0xb
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG26_SECURE_BMSK                            0x400
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG26_SECURE_SHFT                              0xa
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD0_BMSK                                             0x3ff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD0_SHFT                                               0x0

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000194)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_PHYS                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000194)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR, HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OEM_PRODUCT_ID_BMSK                               0xffff0000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OEM_PRODUCT_ID_SHFT                                     0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OEM_HW_ID_BMSK                                        0xffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OEM_HW_ID_SHFT                                           0x0

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000198)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PHYS                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000198)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR, HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PERIPH_VID_BMSK                                   0xffff0000
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PERIPH_VID_SHFT                                         0x10
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PERIPH_PID_BMSK                                       0xffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PERIPH_PID_SHFT                                          0x0

#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000019c)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_PHYS                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000019c)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR, HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_RSVD0_BMSK                                        0xffffff00
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_RSVD0_SHFT                                               0x8
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ANTI_ROLLBACK_FEATURE_EN_BMSK                           0xff
#define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ANTI_ROLLBACK_FEATURE_EN_SHFT                            0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001a0)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001a0)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_ADDR, HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_RMSK)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_PCIE_PHY_DISABLE_UPPER_LANE_BMSK                 0x80000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_PCIE_PHY_DISABLE_UPPER_LANE_SHFT                       0x1f
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_BMSK                     0x40000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_SHFT                           0x1e
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_BMSK                               0x20000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_SHFT                                     0x1d
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_BMSK                        0x1fe00000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_SHFT                              0x15
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_BMSK                         0x180000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_SHFT                             0x13
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_BMSK                       0x40000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_SHFT                          0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_BMSK                       0x20000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_SHFT                          0x11
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_BMSK                                0x10000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_SHFT                                   0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_BMSK                                0x8000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_SHFT                                   0xf
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_BMSK                                0x4000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_SHFT                                   0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_BMSK                                      0x2000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_SHFT                                         0xd
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_BMSK                                    0x1000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_SHFT                                       0xc
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_BMSK                           0x800
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_SHFT                             0xb
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK                   0x400
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT                     0xa
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_BMSK                                    0x200
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_SHFT                                      0x9
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_BMSK                                    0x100
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_SHFT                                      0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_BMSK                                        0x80
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_SHFT                                         0x7
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_BMSK                              0x40
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_SHFT                               0x6
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_CAM_IPE_1_DISABLE_IF_BMSK                              0x20
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_CAM_IPE_1_DISABLE_IF_SHFT                               0x5
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_BMSK                                     0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_SHFT                                      0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_BMSK                                       0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_SHFT                                       0x3
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_BMSK                             0x7
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_SHFT                             0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001a4)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001a4)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ADDR, HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_RMSK)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_BMSK                           0x80000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_SHFT                                 0x1f
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_BMSK                           0x40000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_SHFT                                 0x1e
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_BMSK                                 0x20000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_SHFT                                       0x1d
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_LLCC_FUSE_CACHE_SIZE_ZERO_BMSK                   0x10000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_LLCC_FUSE_CACHE_SIZE_ZERO_SHFT                         0x1c
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_UFS_SINGLE_LANE_BMSK                              0x8000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_UFS_SINGLE_LANE_SHFT                                   0x1b
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_BMSK                                  0x4000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_SHFT                                       0x1a
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK               0x2000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT                    0x19
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_BMSK                   0x1000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_SHFT                        0x18
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_BMSK                   0x800000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_SHFT                       0x17
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_BMSK                             0x400000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_SHFT                                 0x16
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_BMSK                        0x200000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_SHFT                            0x15
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_BMSK                                     0x100000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_SHFT                                         0x14
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_BMSK                                 0x80000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_SHFT                                    0x13
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_BMSK                              0x7c000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_SHFT                                  0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_BMSK                           0x2000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_SHFT                              0xd
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_BMSK                              0x1000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_SHFT                                 0xc
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_BMSK                                       0x800
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_SHFT                                         0xb
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_NIDNT_DISABLE_BMSK                                    0x400
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_NIDNT_DISABLE_SHFT                                      0xa
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_BMSK                                     0x200
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_SHFT                                       0x9
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_BMSK                                      0x1e0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_SHFT                                        0x5
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_BMSK                            0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_SHFT                             0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_VFE_RESOLUTION_LIMIT_BMSK                               0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_VFE_RESOLUTION_LIMIT_SHFT                               0x3
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_BMSK                                     0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_SHFT                                     0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_BMSK                                     0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_SHFT                                     0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_BMSK                                     0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_SHFT                                     0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001a8)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001a8)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_ADDR, HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_RMSK)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_BMSK                  0xffffc000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_SHFT                         0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_BMSK                        0x3c00
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_SHFT                           0xa
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_BMSK                      0x3ff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_SHFT                        0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001ac)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001ac)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_ADDR, HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_RMSK)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_BMSK                         0xc0000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_SHFT                               0x1e
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_RSVD0_BMSK                                       0x3c000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_RSVD0_SHFT                                             0x1a
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_BMSK                       0x2000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_SHFT                            0x19
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_BMSK                                  0x1000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_SHFT                                       0x18
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_BMSK                    0xffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_SHFT                         0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001b0)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001b0)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_ADDR, HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_RMSK)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_TURING_Q6SS_PLL_L_MAX_9_0_BMSK                   0xffc00000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_TURING_Q6SS_PLL_L_MAX_9_0_SHFT                         0x16
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_RSVD0_BMSK                                         0x300000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_RSVD0_SHFT                                             0x14
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_BMSK                          0x80000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_SHFT                             0x13
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_BMSK                          0x40000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_SHFT                             0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_BMSK                     0x20000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_SHFT                        0x11
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_BMSK                     0x10000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_SHFT                        0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_BMSK                      0x8000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_SHFT                         0xf
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_BMSK                      0x4000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_SHFT                         0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_BMSK                     0x2000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_SHFT                        0xd
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_BMSK                     0x1000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_SHFT                        0xc
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                   0x800
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                     0xb
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK                    0x400
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT                      0xa
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_BMSK                         0x200
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_SHFT                           0x9
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_BMSK                         0x100
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_SHFT                           0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_BMSK                          0x80
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_SHFT                           0x7
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_BMSK                          0x40
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_SHFT                           0x6
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_BMSK                         0x20
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_SHFT                          0x5
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_BMSK                         0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_SHFT                          0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK                       0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT                       0x3
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK                        0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT                        0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_BMSK                                    0x2
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_SHFT                                    0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_BMSK                                        0x1
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_SHFT                                        0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001b4)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001b4)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_ADDR, HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_RMSK)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_BMSK                        0xff000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_SHFT                              0x18
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_RSVD1_BMSK                                         0x800000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_RSVD1_SHFT                                             0x17
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_BMSK                           0x400000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_SHFT                               0x16
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_BMSK                      0x200000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_SHFT                          0x15
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_BMSK                            0x1f8000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_SHFT                                 0xf
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_BMSK                          0x4000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_SHFT                             0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_BMSK                         0x3fc0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_SHFT                            0x6
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_TURING_Q6SS_PLL_L_MAX_15_10_BMSK                       0x3f
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW2_MSB_TURING_Q6SS_PLL_L_MAX_15_10_SHFT                        0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001b8)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001b8)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ADDR, HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_RMSK)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_TAP_GEN_SPARE_INSTR_DISABLE_13_0_BMSK            0xfffc0000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_TAP_GEN_SPARE_INSTR_DISABLE_13_0_SHFT                  0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_TAP_INSTR_DISABLE_BMSK                              0x3ffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_LSB_TAP_INSTR_DISABLE_SHFT                                  0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001bc)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001bc)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_ADDR, HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_RMSK)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_SEC_TAP_ACCESS_DISABLE_BMSK                      0xfffc0000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_SEC_TAP_ACCESS_DISABLE_SHFT                            0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_TAP_GEN_SPARE_INSTR_DISABLE_31_14_BMSK              0x3ffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW3_MSB_TAP_GEN_SPARE_INSTR_DISABLE_31_14_SHFT                  0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001c0)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001c0)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ADDR, HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_RMSK)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_MODEM_PBL_PATCH_VERSION_BMSK                     0xfe000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_MODEM_PBL_PATCH_VERSION_SHFT                           0x19
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_APPS_PBL_PATCH_VERSION_BMSK                       0x1fc0000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_APPS_PBL_PATCH_VERSION_SHFT                            0x12
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_APPS_PBL_BOOT_SPEED_BMSK                            0x30000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_APPS_PBL_BOOT_SPEED_SHFT                               0x10
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_MODEM_PBL_BOOT_BMSK                                  0x8000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_MODEM_PBL_BOOT_SHFT                                     0xf
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_RSVD1_BMSK                                           0x4000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_RSVD1_SHFT                                              0xe
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_APPS_BOOT_FROM_ROM_BMSK                              0x2000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_APPS_BOOT_FROM_ROM_SHFT                                 0xd
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_RSVD0_BMSK                                           0x1e00
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_RSVD0_SHFT                                              0x9
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ARM_CE_DISABLE_USAGE_BMSK                             0x100
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_ARM_CE_DISABLE_USAGE_SHFT                               0x8
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_BOOT_ROM_CFG_BMSK                                      0xff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_LSB_BOOT_ROM_CFG_SHFT                                       0x0

#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001c4)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001c4)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_ADDR, HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_RMSK)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_IN)
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_APPS_BOOT_TRIGGER_DISABLE_BMSK                   0x80000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_APPS_BOOT_TRIGGER_DISABLE_SHFT                         0x1f
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_PBL_QSEE_BOOT_FLOW_DISABLE_BMSK                  0x40000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_PBL_QSEE_BOOT_FLOW_DISABLE_SHFT                        0x1e
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_XBL_SEC_AUTH_DISABLE_BMSK                        0x20000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_XBL_SEC_AUTH_DISABLE_SHFT                              0x1d
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_MSM_PKG_TYPE_BMSK                                0x10000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_MSM_PKG_TYPE_SHFT                                      0x1c
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_LOAD_SPU_TEST_IMAGE_BMSK                          0x8000000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_LOAD_SPU_TEST_IMAGE_SHFT                               0x1b
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_RSVD3_BMSK                                        0x7f80000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_RSVD3_SHFT                                             0x13
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_FOUNDRY_ID_BMSK                                     0x78000
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_FOUNDRY_ID_SHFT                                         0xf
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_PLL_CFG_BMSK                                         0x7ff0
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_PLL_CFG_SHFT                                            0x4
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_APPS_PBL_PLL_CTRL_BMSK                                  0xf
#define HWIO_QFPROM_RAW_FEAT_CONFIG_ROW4_MSB_APPS_PBL_PLL_CTRL_SHFT                                  0x0

#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_ADDR(n)                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001c8 + 0x8 * (n))
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_PHYS(n)                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001c8 + 0x8 * (n))
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_MAXn                                                         5
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_HASH_DATA0_BMSK                                     0xffffffff
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_HASH_DATA0_SHFT                                            0x0

#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_ADDR(n)                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001cc + 0x8 * (n))
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_PHYS(n)                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001cc + 0x8 * (n))
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_MAXn                                                         5
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_HASH_DATA1_BMSK                                     0xffffffff
#define HWIO_QFPROM_RAW_PK_HASH0_ROWn_MSB_HASH_DATA1_SHFT                                            0x0

#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001f8)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001f8)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW0_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW0_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW0_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_LMH_CS_FUSES_SLOPE_16_0_BMSK                           0xffff8000
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_LMH_CS_FUSES_SLOPE_16_0_SHFT                                  0xf
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_LPASS_Q6SS1_LDO_VREF_TRIM_BMSK                             0x7f80
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_LPASS_Q6SS1_LDO_VREF_TRIM_SHFT                                0x7
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_LPASS_Q6SS1_LDO_ENABLE_BMSK                                  0x40
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_LPASS_Q6SS1_LDO_ENABLE_SHFT                                   0x6
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_MSS_Q6SS0_LDO_VREF_TRIM_BMSK                                 0x3e
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_MSS_Q6SS0_LDO_VREF_TRIM_SHFT                                  0x1
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_MSS_Q6SS0_LDO_ENABLE_BMSK                                     0x1
#define HWIO_QFPROM_RAW_CALIB_ROW0_LSB_MSS_Q6SS0_LDO_ENABLE_SHFT                                     0x0

#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x000001fc)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001fc)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW0_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW0_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW0_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW0_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_LMH_CS_FUSES_INTERCEPT_8_0_BMSK                        0xff800000
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_LMH_CS_FUSES_INTERCEPT_8_0_SHFT                              0x17
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_LMH_CS_FUSES_SLOPE_39_17_BMSK                            0x7fffff
#define HWIO_QFPROM_RAW_CALIB_ROW0_MSB_LMH_CS_FUSES_SLOPE_39_17_SHFT                                 0x0

#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000200)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000200)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW1_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW1_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW1_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW1_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_LMH_FUSES_AMP_COMP_0_BMSK                              0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_LMH_FUSES_AMP_COMP_0_SHFT                                    0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_LMH_CS_FUSES_INTERCEPT_39_9_BMSK                       0x7fffffff
#define HWIO_QFPROM_RAW_CALIB_ROW1_LSB_LMH_CS_FUSES_INTERCEPT_39_9_SHFT                              0x0

#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000204)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000204)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW1_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW1_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW1_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW1_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_LPASS_Q6SS1_HVX_LDO_ENABLE_BMSK                        0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_LPASS_Q6SS1_HVX_LDO_ENABLE_SHFT                              0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_REFGEN_WEST_BGV_TRIM_BMSK                              0x7f800000
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_REFGEN_WEST_BGV_TRIM_SHFT                                    0x17
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_REFGEN_EAST_BGV_TRIM_BMSK                                0x7f8000
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_REFGEN_EAST_BGV_TRIM_SHFT                                     0xf
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_BANDGAP_TRIM_BMSK                                          0x7f00
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_BANDGAP_TRIM_SHFT                                             0x8
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_SYS_APC1LDOVREFTRIM_BMSK                                     0xf8
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_SYS_APC1LDOVREFTRIM_SHFT                                      0x3
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_LMH_FUSES_AMP_COMP_3_1_BMSK                                   0x7
#define HWIO_QFPROM_RAW_CALIB_ROW1_MSB_LMH_FUSES_AMP_COMP_3_1_SHFT                                   0x0

#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000208)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000208)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW2_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW2_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_GPU_LMH_CS_FUSES_INTERCEPT_HM_1_0_BMSK                 0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_GPU_LMH_CS_FUSES_INTERCEPT_HM_1_0_SHFT                       0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_GPU_LMH_CS_FUSES_SLOPE_SPTP_BMSK                       0x3ff00000
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_GPU_LMH_CS_FUSES_SLOPE_SPTP_SHFT                             0x14
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_GPU_LMH_CS_FUSES_SLOPE_RAC_BMSK                           0xffc00
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_GPU_LMH_CS_FUSES_SLOPE_RAC_SHFT                               0xa
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_GPU_LMH_CS_FUSES_SLOPE_HM_BMSK                              0x3ff
#define HWIO_QFPROM_RAW_CALIB_ROW2_LSB_GPU_LMH_CS_FUSES_SLOPE_HM_SHFT                                0x0

#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000020c)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000020c)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW2_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW2_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_GPU_LMH_FUSES_AMP_COMP_BMSK                            0xf0000000
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_GPU_LMH_FUSES_AMP_COMP_SHFT                                  0x1c
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_GPU_LMH_CS_FUSES_INTERCEPT_SPTP_BMSK                    0xffc0000
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_GPU_LMH_CS_FUSES_INTERCEPT_SPTP_SHFT                         0x12
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_GPU_LMH_CS_FUSES_INTERCEPT_RAC_BMSK                       0x3ff00
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_GPU_LMH_CS_FUSES_INTERCEPT_RAC_SHFT                           0x8
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_GPU_LMH_CS_FUSES_INTERCEPT_HM_9_2_BMSK                       0xff
#define HWIO_QFPROM_RAW_CALIB_ROW2_MSB_GPU_LMH_CS_FUSES_INTERCEPT_HM_9_2_SHFT                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000210)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000210)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW3_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW3_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW3_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW3_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_CPR_FUSES_31_0_BMSK                                    0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW3_LSB_CPR_FUSES_31_0_SHFT                                           0x0

#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000214)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000214)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW3_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW3_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW3_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW3_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_CPR_FUSES_63_32_BMSK                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW3_MSB_CPR_FUSES_63_32_SHFT                                          0x0

#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000218)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000218)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW4_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW4_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW4_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR_FUSES_95_64_BMSK                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW4_LSB_CPR_FUSES_95_64_SHFT                                          0x0

#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000021c)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000021c)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW4_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW4_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW4_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR_FUSES_127_96_BMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW4_MSB_CPR_FUSES_127_96_SHFT                                         0x0

#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000220)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000220)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW5_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW5_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW5_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW5_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW5_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR_FUSES_159_128_BMSK                                 0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW5_LSB_CPR_FUSES_159_128_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000224)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000224)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW5_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW5_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW5_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW5_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW5_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_CPR_FUSES_191_160_BMSK                                 0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW5_MSB_CPR_FUSES_191_160_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000228)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000228)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW6_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW6_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW6_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW6_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW6_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW6_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR_FUSES_223_192_BMSK                                 0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW6_LSB_CPR_FUSES_223_192_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000022c)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000022c)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW6_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW6_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW6_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW6_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW6_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW6_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR_FUSES_255_224_BMSK                                 0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW6_MSB_CPR_FUSES_255_224_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000230)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000230)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW7_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW7_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW7_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW7_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW7_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW7_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_CPR_FUSES_287_256_BMSK                                 0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW7_LSB_CPR_FUSES_287_256_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000234)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000234)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW7_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW7_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW7_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW7_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW7_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW7_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_CPR_FUSES_319_288_BMSK                                 0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW7_MSB_CPR_FUSES_319_288_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000238)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000238)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW8_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW8_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW8_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW8_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW8_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW8_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_CPR_FUSES_351_320_BMSK                                 0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW8_LSB_CPR_FUSES_351_320_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000023c)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000023c)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW8_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW8_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW8_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW8_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW8_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW8_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_CPR_FUSES_383_352_BMSK                                 0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW8_MSB_CPR_FUSES_383_352_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000240)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000240)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW9_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW9_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW9_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW9_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW9_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW9_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_CPR_FUSES_415_384_BMSK                                 0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW9_LSB_CPR_FUSES_415_384_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_ADDR                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000244)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_PHYS                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000244)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_RMSK                                                   0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW9_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW9_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW9_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW9_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW9_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW9_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR_FUSES_447_416_BMSK                                 0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW9_MSB_CPR_FUSES_447_416_SHFT                                        0x0

#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000248)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000248)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW10_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW10_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW10_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW10_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW10_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW10_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_CPR_FUSES_479_448_BMSK                                0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW10_LSB_CPR_FUSES_479_448_SHFT                                       0x0

#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000024c)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000024c)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW10_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW10_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW10_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW10_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW10_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW10_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_SPARE0_BMSK                                           0xe0000000
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_SPARE0_SHFT                                                 0x1d
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_SW_CAL_REDUN_SEL_BMSK                                 0x1c000000
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_SW_CAL_REDUN_SEL_SHFT                                       0x1a
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_CPR_FUSES_505_480_BMSK                                 0x3ffffff
#define HWIO_QFPROM_RAW_CALIB_ROW10_MSB_CPR_FUSES_505_480_SHFT                                       0x0

#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000250)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000250)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW11_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW11_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW11_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW11_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW11_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW11_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_SPARE0_BMSK                                           0xc0000000
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_SPARE0_SHFT                                                 0x1e
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_QUSB_REFCLK_SEL_BMSK                                  0x20000000
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_QUSB_REFCLK_SEL_SHFT                                        0x1d
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_QUSB_PORT0_HSTX_TRIM_LSB_BMSK                         0x1e000000
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_QUSB_PORT0_HSTX_TRIM_LSB_SHFT                               0x19
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_SRAM_AGING_SENSOR_1_BMSK                               0x1fe0000
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_SRAM_AGING_SENSOR_1_SHFT                                    0x11
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_SRAM_AGING_SENSOR_0_BMSK                                 0x1fe00
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_SRAM_AGING_SENSOR_0_SHFT                                     0x9
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_GNSS_ADC_RSB_BMSK                                          0x1c0
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_GNSS_ADC_RSB_SHFT                                            0x6
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_GNSS_ADC_LDO_BMSK                                           0x38
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_GNSS_ADC_LDO_SHFT                                            0x3
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_GNSS_ADC_VREF_BMSK                                           0x7
#define HWIO_QFPROM_RAW_CALIB_ROW11_LSB_GNSS_ADC_VREF_SHFT                                           0x0

#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000254)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000254)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW11_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW11_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW11_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW11_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW11_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW11_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_TSENS1_BASE0_8_0_BMSK                                 0xff800000
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_TSENS1_BASE0_8_0_SHFT                                       0x17
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_TSENS0_BASE1_BMSK                                       0x7fe000
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_TSENS0_BASE1_SHFT                                            0xd
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_TSENS0_BASE0_BMSK                                         0x1ff8
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_TSENS0_BASE0_SHFT                                            0x3
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_TSENS_CAL_SEL_BMSK                                           0x7
#define HWIO_QFPROM_RAW_CALIB_ROW11_MSB_TSENS_CAL_SEL_SHFT                                           0x0

#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000258)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000258)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW12_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW12_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW12_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW12_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW12_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW12_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_TSENS5_OFFSET_0_BMSK                                  0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_TSENS5_OFFSET_0_SHFT                                        0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_TSENS4_OFFSET_BMSK                                    0x78000000
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_TSENS4_OFFSET_SHFT                                          0x1b
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_TSENS3_OFFSET_BMSK                                     0x7800000
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_TSENS3_OFFSET_SHFT                                          0x17
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_TSENS2_OFFSET_BMSK                                      0x780000
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_TSENS2_OFFSET_SHFT                                          0x13
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_TSENS1_OFFSET_BMSK                                       0x78000
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_TSENS1_OFFSET_SHFT                                           0xf
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_TSENS0_OFFSET_BMSK                                        0x7800
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_TSENS0_OFFSET_SHFT                                           0xb
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_TSENS1_BASE1_BMSK                                          0x7fe
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_TSENS1_BASE1_SHFT                                            0x1
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_TSENS1_BASE0_9_BMSK                                          0x1
#define HWIO_QFPROM_RAW_CALIB_ROW12_LSB_TSENS1_BASE0_9_SHFT                                          0x0

#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000025c)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000025c)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW12_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW12_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW12_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW12_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW12_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW12_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS13_OFFSET_0_BMSK                                 0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS13_OFFSET_0_SHFT                                       0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS12_OFFSET_BMSK                                   0x78000000
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS12_OFFSET_SHFT                                         0x1b
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS11_OFFSET_BMSK                                    0x7800000
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS11_OFFSET_SHFT                                         0x17
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS10_OFFSET_BMSK                                     0x780000
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS10_OFFSET_SHFT                                         0x13
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS9_OFFSET_BMSK                                       0x78000
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS9_OFFSET_SHFT                                           0xf
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS8_OFFSET_BMSK                                        0x7800
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS8_OFFSET_SHFT                                           0xb
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS7_OFFSET_BMSK                                         0x780
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS7_OFFSET_SHFT                                           0x7
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS6_OFFSET_BMSK                                          0x78
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS6_OFFSET_SHFT                                           0x3
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS5_OFFSET_3_1_BMSK                                       0x7
#define HWIO_QFPROM_RAW_CALIB_ROW12_MSB_TSENS5_OFFSET_3_1_SHFT                                       0x0

#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000260)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000260)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW13_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW13_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW13_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW13_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW13_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW13_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS21_OFFSET_0_BMSK                                 0x80000000
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS21_OFFSET_0_SHFT                                       0x1f
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS20_OFFSET_BMSK                                   0x78000000
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS20_OFFSET_SHFT                                         0x1b
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS19_OFFSET_BMSK                                    0x7800000
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS19_OFFSET_SHFT                                         0x17
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS18_OFFSET_BMSK                                     0x780000
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS18_OFFSET_SHFT                                         0x13
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS17_OFFSET_BMSK                                      0x78000
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS17_OFFSET_SHFT                                          0xf
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS16_OFFSET_BMSK                                       0x7800
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS16_OFFSET_SHFT                                          0xb
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS15_OFFSET_BMSK                                        0x780
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS15_OFFSET_SHFT                                          0x7
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS14_OFFSET_BMSK                                         0x78
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS14_OFFSET_SHFT                                          0x3
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS13_OFFSET_3_1_BMSK                                      0x7
#define HWIO_QFPROM_RAW_CALIB_ROW13_LSB_TSENS13_OFFSET_3_1_SHFT                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000264)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000264)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW13_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW13_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW13_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW13_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW13_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW13_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_SW_CAL_REDUN_20_0_BMSK                                0xfffff800
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_SW_CAL_REDUN_20_0_SHFT                                       0xb
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_TSENS23_OFFSET_BMSK                                        0x780
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_TSENS23_OFFSET_SHFT                                          0x7
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_TSENS22_OFFSET_BMSK                                         0x78
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_TSENS22_OFFSET_SHFT                                          0x3
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_TSENS21_OFFSET_3_1_BMSK                                      0x7
#define HWIO_QFPROM_RAW_CALIB_ROW13_MSB_TSENS21_OFFSET_3_1_SHFT                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000268)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000268)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW14_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW14_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW14_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW14_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW14_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW14_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_SW_CAL_REDUN_52_21_BMSK                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW14_LSB_SW_CAL_REDUN_52_21_SHFT                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000026c)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000026c)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW14_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW14_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW14_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW14_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW14_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW14_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_SW_CAL_REDUN_84_53_BMSK                               0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW14_MSB_SW_CAL_REDUN_84_53_SHFT                                      0x0

#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000270)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000270)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW15_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW15_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW15_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW15_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW15_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW15_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_SW_CAL_REDUN_116_85_BMSK                              0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW15_LSB_SW_CAL_REDUN_116_85_SHFT                                     0x0

#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000274)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000274)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW15_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW15_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW15_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW15_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW15_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW15_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_SW_CAL_REDUN_148_117_BMSK                             0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW15_MSB_SW_CAL_REDUN_148_117_SHFT                                    0x0

#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000278)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000278)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW16_LSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW16_LSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW16_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW16_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW16_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW16_LSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_SW_CAL_REDUN_180_149_BMSK                             0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW16_LSB_SW_CAL_REDUN_180_149_SHFT                                    0x0

#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000027c)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000027c)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW16_MSB_ADDR, HWIO_QFPROM_RAW_CALIB_ROW16_MSB_RMSK)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CALIB_ROW16_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_CALIB_ROW16_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_CALIB_ROW16_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIB_ROW16_MSB_IN)
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SW_CAL_REDUN_212_181_BMSK                             0xffffffff
#define HWIO_QFPROM_RAW_CALIB_ROW16_MSB_SW_CAL_REDUN_212_181_SHFT                                    0x0

#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_ADDR(n)                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000280 + 0x8 * (n))
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_PHYS(n)                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000280 + 0x8 * (n))
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_MAXn                                                      48
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_REDUN_DATA_BMSK                                   0xffffffff
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_LSB_REDUN_DATA_SHFT                                          0x0

#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_ADDR(n)                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000284 + 0x8 * (n))
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_PHYS(n)                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000284 + 0x8 * (n))
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_MAXn                                                      34
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_REDUN_DATA_BMSK                                   0xffffffff
#define HWIO_QFPROM_RAW_MEM_CONFIG_ROWn_MSB_REDUN_DATA_SHFT                                          0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_ADDR                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000408)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_PHYS                                          (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000408)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_ADDR, HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_RMSK)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_PCIE_PHY_DISABLE_UPPER_LANE_BMSK              0x80000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_PCIE_PHY_DISABLE_UPPER_LANE_SHFT                    0x1f
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_BMSK                  0x40000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_SHFT                        0x1e
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_BMSK                            0x20000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_SHFT                                  0x1d
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_BMSK                     0x1fe00000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_SHFT                           0x15
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_BMSK                      0x180000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_SHFT                          0x13
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_BMSK                    0x40000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_SHFT                       0x12
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_BMSK                    0x20000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_SHFT                       0x11
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_BMSK                             0x10000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_SHFT                                0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_BMSK                             0x8000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_SHFT                                0xf
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_BMSK                             0x4000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_SHFT                                0xe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_BMSK                                   0x2000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_SHFT                                      0xd
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_BMSK                                 0x1000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_SHFT                                    0xc
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_BMSK                        0x800
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_SHFT                          0xb
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK                0x400
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT                  0xa
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_BMSK                                 0x200
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_SHFT                                   0x9
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_BMSK                                 0x100
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_SHFT                                   0x8
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_BMSK                                     0x80
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_SHFT                                      0x7
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_BMSK                           0x40
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_SHFT                            0x6
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_CAM_IPE_1_DISABLE_IF_BMSK                           0x20
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_CAM_IPE_1_DISABLE_IF_SHFT                            0x5
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_BMSK                                  0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_SHFT                                   0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_BMSK                                    0x8
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_SHFT                                    0x3
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_BMSK                          0x7
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_SHFT                          0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ADDR                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000040c)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PHYS                                          (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000040c)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ADDR, HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_RMSK)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_BMSK                        0x80000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_SHFT                              0x1f
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_BMSK                        0x40000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_SHFT                              0x1e
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_BMSK                              0x20000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_SHFT                                    0x1d
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_LLCC_FUSE_CACHE_SIZE_ZERO_BMSK                0x10000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_LLCC_FUSE_CACHE_SIZE_ZERO_SHFT                      0x1c
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_UFS_SINGLE_LANE_BMSK                           0x8000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_UFS_SINGLE_LANE_SHFT                                0x1b
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_BMSK                               0x4000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_SHFT                                    0x1a
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK            0x2000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT                 0x19
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_BMSK                0x1000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_SHFT                     0x18
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_BMSK                0x800000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_SHFT                    0x17
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_BMSK                          0x400000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_SHFT                              0x16
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_BMSK                     0x200000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_SHFT                         0x15
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_BMSK                                  0x100000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_SHFT                                      0x14
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_BMSK                              0x80000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_SHFT                                 0x13
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_BMSK                           0x7c000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_SHFT                               0xe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_BMSK                        0x2000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_SHFT                           0xd
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_BMSK                           0x1000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_SHFT                              0xc
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_BMSK                                    0x800
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_SHFT                                      0xb
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_NIDNT_DISABLE_BMSK                                 0x400
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_NIDNT_DISABLE_SHFT                                   0xa
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_BMSK                                  0x200
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_SHFT                                    0x9
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_BMSK                                   0x1e0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_SHFT                                     0x5
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_BMSK                         0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_SHFT                          0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_VFE_RESOLUTION_LIMIT_BMSK                            0x8
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_VFE_RESOLUTION_LIMIT_SHFT                            0x3
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_BMSK                                  0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_SHFT                                  0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_BMSK                                  0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_SHFT                                  0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_BMSK                                  0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_SHFT                                  0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_ADDR                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000410)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_PHYS                                          (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000410)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_ADDR, HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_RMSK)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_BMSK               0xffffc000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_SHFT                      0xe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_BMSK                     0x3c00
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_SHFT                        0xa
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_BMSK                   0x3ff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_SHFT                     0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_ADDR                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000414)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_PHYS                                          (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000414)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_ADDR, HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_RMSK)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_BMSK                      0xc0000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_SHFT                            0x1e
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_RSVD0_BMSK                                    0x3c000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_RSVD0_SHFT                                          0x1a
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_BMSK                    0x2000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_SHFT                         0x19
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_BMSK                               0x1000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_SHFT                                    0x18
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_BMSK                 0xffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_SHFT                      0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_ADDR                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000418)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PHYS                                          (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000418)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_ADDR, HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_RMSK)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_TURING_Q6SS_PLL_L_MAX_9_0_BMSK                0xffc00000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_TURING_Q6SS_PLL_L_MAX_9_0_SHFT                      0x16
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_RSVD0_BMSK                                      0x300000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_RSVD0_SHFT                                          0x14
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_BMSK                       0x80000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_SHFT                          0x13
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_BMSK                       0x40000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_SHFT                          0x12
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_BMSK                  0x20000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_SHFT                     0x11
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_BMSK                  0x10000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_SHFT                     0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_BMSK                   0x8000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_SHFT                      0xf
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_BMSK                   0x4000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_SHFT                      0xe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_BMSK                  0x2000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_SHFT                     0xd
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_BMSK                  0x1000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_SHFT                     0xc
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                0x800
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                  0xb
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK                 0x400
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT                   0xa
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_BMSK                      0x200
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_SHFT                        0x9
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_BMSK                      0x100
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_SHFT                        0x8
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_BMSK                       0x80
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_SHFT                        0x7
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_BMSK                       0x40
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_SHFT                        0x6
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_BMSK                      0x20
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_SHFT                       0x5
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_BMSK                      0x10
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_SHFT                       0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK                    0x8
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT                    0x3
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK                     0x4
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT                     0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_BMSK                                 0x2
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_SHFT                                 0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_BMSK                                     0x1
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_SHFT                                     0x0

#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_ADDR                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000041c)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_PHYS                                          (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000041c)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_ADDR, HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_RMSK)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_BMSK                     0xff000000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_SHFT                           0x18
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_RSVD1_BMSK                                      0x800000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_RSVD1_SHFT                                          0x17
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_BMSK                        0x400000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_SHFT                            0x16
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_BMSK                   0x200000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_SHFT                       0x15
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_BMSK                         0x1f8000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_SHFT                              0xf
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_BMSK                       0x4000
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_SHFT                          0xe
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_BMSK                      0x3fc0
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_SHFT                         0x6
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_TURING_Q6SS_PLL_L_MAX_15_10_BMSK                    0x3f
#define HWIO_QFPROM_RAW_CM_FEAT_CONFIG_ROW2_MSB_TURING_Q6SS_PLL_L_MAX_15_10_SHFT                     0x0

#define HWIO_QFPROM_RAW_QC_SPARE_REGn_LSB_ADDR(n)                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000003a0 + 0x8 * (n))
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_LSB_PHYS(n)                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003a0 + 0x8 * (n))
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_LSB_MAXn                                                        18
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_QC_SPARE_REGn_LSB_ADDR(n), HWIO_QFPROM_RAW_QC_SPARE_REGn_LSB_RMSK)
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_QC_SPARE_REGn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_QC_SPARE_REGn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_QC_SPARE_REGn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_QC_SPARE_REGn_LSB_INI(n))
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_LSB_QC_SPARE_BMSK                                       0xffffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_LSB_QC_SPARE_SHFT                                              0x0

#define HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_ADDR(n)                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000003a4 + 0x8 * (n))
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_PHYS(n)                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003a4 + 0x8 * (n))
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_MAXn                                                        18
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_ADDR(n), HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_RMSK)
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_INI(n))
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_RSVD0_BMSK                                          0x80000000
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_RSVD0_SHFT                                                0x1f
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_FEC_VALUE_BMSK                                      0x7f000000
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_FEC_VALUE_SHFT                                            0x18
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_QC_SPARE_BMSK                                         0xffffff
#define HWIO_QFPROM_RAW_QC_SPARE_REGn_MSB_QC_SPARE_SHFT                                              0x0

#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n)                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000438 + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_PHYS(n)                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000438 + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_RMSK                                      0xffffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_MAXn                                               1
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_KEY_DATA0_BMSK                            0xffffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_LSB_KEY_DATA0_SHFT                                   0x0

#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n)                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000043c + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_PHYS(n)                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000043c + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RMSK                                      0xffffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_MAXn                                               1
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RSVD1_BMSK                                0x80000000
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RSVD1_SHFT                                      0x1f
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_FEC_VALUE_BMSK                            0x7f000000
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_FEC_VALUE_SHFT                                  0x18
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_KEY_DATA1_BMSK                              0xffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROWn_MSB_KEY_DATA1_SHFT                                   0x0

#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000448)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_PHYS                                      (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000448)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RMSK                                      0xffffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR, HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RSVD0_BMSK                                0xffff0000
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RSVD0_SHFT                                      0x10
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_KEY_DATA0_BMSK                                0xffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_LSB_KEY_DATA0_SHFT                                   0x0

#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000044c)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_PHYS                                      (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000044c)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RMSK                                      0xffffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR, HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD1_BMSK                                0x80000000
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD1_SHFT                                      0x1f
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_FEC_VALUE_BMSK                            0x7f000000
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_FEC_VALUE_SHFT                                  0x18
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD0_BMSK                                  0xffffff
#define HWIO_QFPROM_RAW_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD0_SHFT                                       0x0

#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_ADDR(n)                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000450 + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_PHYS(n)                                         (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000450 + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_MAXn                                                     1
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT4_BMSK                                  0xff000000
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT4_SHFT                                        0x18
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT3_BMSK                                    0xff0000
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT3_SHFT                                        0x10
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT2_BMSK                                      0xff00
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT2_SHFT                                         0x8
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT1_BMSK                                        0xff
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT1_SHFT                                         0x0

#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_ADDR(n)                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000454 + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_PHYS(n)                                         (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000454 + 0x8 * (n))
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_MAXn                                                     1
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_RSVD1_BMSK                                      0x80000000
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_RSVD1_SHFT                                            0x1f
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_FEC_VALUE_BMSK                                  0x7f000000
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_FEC_VALUE_SHFT                                        0x18
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT7_BMSK                                    0xff0000
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT7_SHFT                                        0x10
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT6_BMSK                                      0xff00
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT6_SHFT                                         0x8
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT5_BMSK                                        0xff
#define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT5_SHFT                                         0x0

#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n)                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000460 + 0x8 * (n))
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_PHYS(n)                               (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000460 + 0x8 * (n))
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_RMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_MAXn                                           3
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_BMSK                        0xffffffff
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_SHFT                               0x0

#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n)                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000464 + 0x8 * (n))
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_PHYS(n)                               (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000464 + 0x8 * (n))
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_MAXn                                           3
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RSVD1_BMSK                            0x80000000
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RSVD1_SHFT                                  0x1f
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_FEC_VALUE_BMSK                        0x7f000000
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_FEC_VALUE_SHFT                              0x18
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_BMSK                          0xffffff
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_SHFT                               0x0

#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_LSB_ADDR                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000480)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_LSB_PHYS                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000480)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_LSB_RMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_LSB_ADDR, HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_LSB_RMSK)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_LSB_IN)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_LSB_KEY_DATA0_BMSK                        0xffffffff
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_LSB_KEY_DATA0_SHFT                               0x0

#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_ADDR                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000484)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_PHYS                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000484)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_RMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_ADDR, HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_RMSK)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_IN)
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_RSVD1_BMSK                            0x80000000
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_RSVD1_SHFT                                  0x1f
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_FEC_VALUE_BMSK                        0x7f000000
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_FEC_VALUE_SHFT                              0x18
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_BMSK                              0xffffff
#define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_SHFT                                   0x0

#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n)                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000488 + 0x8 * (n))
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_PHYS(n)                               (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000488 + 0x8 * (n))
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_RMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_MAXn                                           3
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_BMSK                        0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_SHFT                               0x0

#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n)                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000048c + 0x8 * (n))
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_PHYS(n)                               (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000048c + 0x8 * (n))
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_MAXn                                           3
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RSVD1_BMSK                            0x80000000
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RSVD1_SHFT                                  0x1f
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_FEC_VALUE_BMSK                        0x7f000000
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_FEC_VALUE_SHFT                              0x18
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_BMSK                          0xffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_SHFT                               0x0

#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x000004a8)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_PHYS                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004a8)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_RMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR, HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_RMSK)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_IN)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_KEY_DATA0_BMSK                        0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_KEY_DATA0_SHFT                               0x0

#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x000004ac)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_PHYS                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004ac)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RMSK                                  0xffffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR, HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RMSK)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_IN)
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD1_BMSK                            0x80000000
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD1_SHFT                                  0x1f
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_FEC_VALUE_BMSK                        0x7f000000
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_FEC_VALUE_SHFT                              0x18
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_BMSK                              0xffffff
#define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_SHFT                                   0x0

#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_ADDR(n)                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000004b0 + 0x8 * (n))
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_PHYS(n)                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004b0 + 0x8 * (n))
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_MAXn                                                       55
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_PATCH_DATA_BMSK                                    0xffffffff
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_LSB_PATCH_DATA_SHFT                                           0x0

#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_ADDR(n)                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000004b4 + 0x8 * (n))
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_PHYS(n)                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004b4 + 0x8 * (n))
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_MAXn                                                       55
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RSVD1_BMSK                                         0x80000000
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RSVD1_SHFT                                               0x1f
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_FEC_VALUE_BMSK                                     0x7f000000
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_FEC_VALUE_SHFT                                           0x18
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RSVD0_BMSK                                           0xfe0000
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_RSVD0_SHFT                                               0x11
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_PATCH_ADDR_BMSK                                       0x1fffe
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_PATCH_ADDR_SHFT                                           0x1
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_PATCH_EN_BMSK                                             0x1
#define HWIO_QFPROM_RAW_ROM_PATCH_ROWn_MSB_PATCH_EN_SHFT                                             0x0

#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n)                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000670 + 0x8 * (n))
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_PHYS(n)                                      (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000670 + 0x8 * (n))
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_RMSK                                         0xffffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_MAXn                                                  1
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_KEY_DATA0_BMSK                               0xffffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_LSB_KEY_DATA0_SHFT                                      0x0

#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n)                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000674 + 0x8 * (n))
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_PHYS(n)                                      (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000674 + 0x8 * (n))
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_RMSK                                         0xffffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_MAXn                                                  1
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_RSVD1_BMSK                                   0x80000000
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_RSVD1_SHFT                                         0x1f
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_FEC_VALUE_BMSK                               0x7f000000
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_FEC_VALUE_SHFT                                     0x18
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_KEY_DATA1_BMSK                                 0xffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROWn_MSB_KEY_DATA1_SHFT                                      0x0

#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000680)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_PHYS                                         (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000680)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_RMSK                                         0xffffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR, HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_RMSK)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_IN)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_RSVD0_BMSK                                   0xffff0000
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_RSVD0_SHFT                                         0x10
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_KEY_DATA0_BMSK                                   0xffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_LSB_KEY_DATA0_SHFT                                      0x0

#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000684)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_PHYS                                         (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000684)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_RMSK                                         0xffffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR, HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_RMSK)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_IN)
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD1_BMSK                                   0x80000000
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD1_SHFT                                         0x1f
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_FEC_VALUE_BMSK                               0x7f000000
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_FEC_VALUE_SHFT                                     0x18
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD0_BMSK                                     0xffffff
#define HWIO_QFPROM_RAW_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD0_SHFT                                          0x0

#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000688 + 0x8 * (n))
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_PHYS(n)                                        (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000688 + 0x8 * (n))
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_MAXn                                                    3
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_INI(n))
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_KEY_DATA0_BMSK                                 0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_LSB_KEY_DATA0_SHFT                                        0x0

#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000068c + 0x8 * (n))
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_PHYS(n)                                        (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000068c + 0x8 * (n))
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_MAXn                                                    3
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_INI(n))
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_RSVD1_BMSK                                     0x80000000
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_RSVD1_SHFT                                           0x1f
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_FEC_VALUE_BMSK                                 0x7f000000
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_FEC_VALUE_SHFT                                       0x18
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_KEY_DATA1_BMSK                                   0xffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROWn_MSB_KEY_DATA1_SHFT                                        0x0

#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x000006a8)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_PHYS                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006a8)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_ADDR, HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_RMSK)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_ADDR,v)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_IN)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_KEY_DATA0_BMSK                                 0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_LSB_KEY_DATA0_SHFT                                        0x0

#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_ADDR                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x000006ac)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_PHYS                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006ac)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_ADDR, HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_RMSK)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_OUT(v)      \
        out_dword(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_ADDR,v)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_IN)
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_RSVD1_BMSK                                     0x80000000
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_RSVD1_SHFT                                           0x1f
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_FEC_VALUE_BMSK                                 0x7f000000
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_FEC_VALUE_SHFT                                       0x18
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_RSVD0_BMSK                                       0xffffff
#define HWIO_QFPROM_RAW_USER_DATA_KEY_ROW4_MSB_RSVD0_SHFT                                            0x0

#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_ADDR(n)                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000510 + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_PHYS(n)                                       (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000510 + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_MAXn                                                  30
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_OEM_SPARE_BMSK                                0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_OEM_SPARE_SHFT                                       0x0

#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_ADDR(n)                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000514 + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_PHYS(n)                                       (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000514 + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_MAXn                                                  30
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_OEM_SPARE_BMSK                                0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_OEM_SPARE_SHFT                                       0x0

#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_ADDR(n)                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00000518 + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_PHYS(n)                                       (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000518 + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_MAXn                                                  30
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_OEM_SPARE_BMSK                                0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_OEM_SPARE_SHFT                                       0x0

#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_ADDR(n)                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000051c + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_PHYS(n)                                       (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000051c + 0x10 * (n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_MAXn                                                  30
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_ADDR(n), HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_RMSK)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_ADDR(n), mask)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_OUTI(n,val)    \
        out_dword(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_ADDR(n),val)
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_ADDR(n),mask,val,HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_INI(n))
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_OEM_SPARE_BMSK                                0xffffffff
#define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_OEM_SPARE_SHFT                                       0x0

#define HWIO_QFPROM_BLOW_TIMER_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000203c)
#define HWIO_QFPROM_BLOW_TIMER_PHYS                                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000203c)
#define HWIO_QFPROM_BLOW_TIMER_RMSK                                                                0xfff
#define HWIO_QFPROM_BLOW_TIMER_IN          \
        in_dword_masked(HWIO_QFPROM_BLOW_TIMER_ADDR, HWIO_QFPROM_BLOW_TIMER_RMSK)
#define HWIO_QFPROM_BLOW_TIMER_INM(m)      \
        in_dword_masked(HWIO_QFPROM_BLOW_TIMER_ADDR, m)
#define HWIO_QFPROM_BLOW_TIMER_OUT(v)      \
        out_dword(HWIO_QFPROM_BLOW_TIMER_ADDR,v)
#define HWIO_QFPROM_BLOW_TIMER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_BLOW_TIMER_ADDR,m,v,HWIO_QFPROM_BLOW_TIMER_IN)
#define HWIO_QFPROM_BLOW_TIMER_BLOW_TIMER_BMSK                                                     0xfff
#define HWIO_QFPROM_BLOW_TIMER_BLOW_TIMER_SHFT                                                       0x0

#define HWIO_QFPROM_TEST_CTRL_ADDR                                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002040)
#define HWIO_QFPROM_TEST_CTRL_PHYS                                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002040)
#define HWIO_QFPROM_TEST_CTRL_RMSK                                                                   0xf
#define HWIO_QFPROM_TEST_CTRL_IN          \
        in_dword_masked(HWIO_QFPROM_TEST_CTRL_ADDR, HWIO_QFPROM_TEST_CTRL_RMSK)
#define HWIO_QFPROM_TEST_CTRL_INM(m)      \
        in_dword_masked(HWIO_QFPROM_TEST_CTRL_ADDR, m)
#define HWIO_QFPROM_TEST_CTRL_OUT(v)      \
        out_dword(HWIO_QFPROM_TEST_CTRL_ADDR,v)
#define HWIO_QFPROM_TEST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_TEST_CTRL_ADDR,m,v,HWIO_QFPROM_TEST_CTRL_IN)
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_ROM_BMSK                                                       0x8
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_ROM_SHFT                                                       0x3
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_WL_BMSK                                                        0x4
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_WL_SHFT                                                        0x2
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_BL_BMSK                                                        0x2
#define HWIO_QFPROM_TEST_CTRL_SEL_TST_BL_SHFT                                                        0x1
#define HWIO_QFPROM_TEST_CTRL_EN_FUSE_RES_MEAS_BMSK                                                  0x1
#define HWIO_QFPROM_TEST_CTRL_EN_FUSE_RES_MEAS_SHFT                                                  0x0

#define HWIO_QFPROM_ACCEL_ADDR                                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002044)
#define HWIO_QFPROM_ACCEL_PHYS                                                                (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002044)
#define HWIO_QFPROM_ACCEL_RMSK                                                                     0xfff
#define HWIO_QFPROM_ACCEL_IN          \
        in_dword_masked(HWIO_QFPROM_ACCEL_ADDR, HWIO_QFPROM_ACCEL_RMSK)
#define HWIO_QFPROM_ACCEL_INM(m)      \
        in_dword_masked(HWIO_QFPROM_ACCEL_ADDR, m)
#define HWIO_QFPROM_ACCEL_OUT(v)      \
        out_dword(HWIO_QFPROM_ACCEL_ADDR,v)
#define HWIO_QFPROM_ACCEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_ACCEL_ADDR,m,v,HWIO_QFPROM_ACCEL_IN)
#define HWIO_QFPROM_ACCEL_QFPROM_GATELAST_BMSK                                                     0x800
#define HWIO_QFPROM_ACCEL_QFPROM_GATELAST_SHFT                                                       0xb
#define HWIO_QFPROM_ACCEL_QFPROM_TRIPPT_SEL_BMSK                                                   0x700
#define HWIO_QFPROM_ACCEL_QFPROM_TRIPPT_SEL_SHFT                                                     0x8
#define HWIO_QFPROM_ACCEL_QFPROM_ACCEL_BMSK                                                         0xff
#define HWIO_QFPROM_ACCEL_QFPROM_ACCEL_SHFT                                                          0x0

#define HWIO_QFPROM_BLOW_STATUS_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002048)
#define HWIO_QFPROM_BLOW_STATUS_PHYS                                                          (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002048)
#define HWIO_QFPROM_BLOW_STATUS_RMSK                                                                 0x3
#define HWIO_QFPROM_BLOW_STATUS_IN          \
        in_dword_masked(HWIO_QFPROM_BLOW_STATUS_ADDR, HWIO_QFPROM_BLOW_STATUS_RMSK)
#define HWIO_QFPROM_BLOW_STATUS_INM(m)      \
        in_dword_masked(HWIO_QFPROM_BLOW_STATUS_ADDR, m)
#define HWIO_QFPROM_BLOW_STATUS_QFPROM_WR_ERR_BMSK                                                   0x2
#define HWIO_QFPROM_BLOW_STATUS_QFPROM_WR_ERR_SHFT                                                   0x1
#define HWIO_QFPROM_BLOW_STATUS_QFPROM_BUSY_BMSK                                                     0x1
#define HWIO_QFPROM_BLOW_STATUS_QFPROM_BUSY_SHFT                                                     0x0

#define HWIO_QFPROM_ROM_ERROR_ADDR                                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000204c)
#define HWIO_QFPROM_ROM_ERROR_PHYS                                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000204c)
#define HWIO_QFPROM_ROM_ERROR_RMSK                                                                   0x1
#define HWIO_QFPROM_ROM_ERROR_IN          \
        in_dword_masked(HWIO_QFPROM_ROM_ERROR_ADDR, HWIO_QFPROM_ROM_ERROR_RMSK)
#define HWIO_QFPROM_ROM_ERROR_INM(m)      \
        in_dword_masked(HWIO_QFPROM_ROM_ERROR_ADDR, m)
#define HWIO_QFPROM_ROM_ERROR_ERROR_BMSK                                                             0x1
#define HWIO_QFPROM_ROM_ERROR_ERROR_SHFT                                                             0x0

#define HWIO_QFPROM0_MATCH_STATUS_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002050)
#define HWIO_QFPROM0_MATCH_STATUS_PHYS                                                        (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002050)
#define HWIO_QFPROM0_MATCH_STATUS_RMSK                                                        0xffffffff
#define HWIO_QFPROM0_MATCH_STATUS_IN          \
        in_dword_masked(HWIO_QFPROM0_MATCH_STATUS_ADDR, HWIO_QFPROM0_MATCH_STATUS_RMSK)
#define HWIO_QFPROM0_MATCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_QFPROM0_MATCH_STATUS_ADDR, m)
#define HWIO_QFPROM0_MATCH_STATUS_FLAG_BMSK                                                   0xffffffff
#define HWIO_QFPROM0_MATCH_STATUS_FLAG_SHFT                                                          0x0

#define HWIO_QFPROM1_MATCH_STATUS_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002054)
#define HWIO_QFPROM1_MATCH_STATUS_PHYS                                                        (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002054)
#define HWIO_QFPROM1_MATCH_STATUS_RMSK                                                        0xffffffff
#define HWIO_QFPROM1_MATCH_STATUS_IN          \
        in_dword_masked(HWIO_QFPROM1_MATCH_STATUS_ADDR, HWIO_QFPROM1_MATCH_STATUS_RMSK)
#define HWIO_QFPROM1_MATCH_STATUS_INM(m)      \
        in_dword_masked(HWIO_QFPROM1_MATCH_STATUS_ADDR, m)
#define HWIO_QFPROM1_MATCH_STATUS_FLAG_BMSK                                                   0xffffffff
#define HWIO_QFPROM1_MATCH_STATUS_FLAG_SHFT                                                          0x0

#define HWIO_FEC_ESR_ADDR                                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002058)
#define HWIO_FEC_ESR_PHYS                                                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002058)
#define HWIO_FEC_ESR_RMSK                                                                         0x2fdf
#define HWIO_FEC_ESR_IN          \
        in_dword_masked(HWIO_FEC_ESR_ADDR, HWIO_FEC_ESR_RMSK)
#define HWIO_FEC_ESR_INM(m)      \
        in_dword_masked(HWIO_FEC_ESR_ADDR, m)
#define HWIO_FEC_ESR_OUT(v)      \
        out_dword(HWIO_FEC_ESR_ADDR,v)
#define HWIO_FEC_ESR_OUTM(m,v) \
        out_dword_masked_ns(HWIO_FEC_ESR_ADDR,m,v,HWIO_FEC_ESR_IN)
#define HWIO_FEC_ESR_CORR_SW_ACC_BMSK                                                             0x2000
#define HWIO_FEC_ESR_CORR_SW_ACC_SHFT                                                                0xd
#define HWIO_FEC_ESR_CORR_SECURE_CHANNEL_BMSK                                                      0x800
#define HWIO_FEC_ESR_CORR_SECURE_CHANNEL_SHFT                                                        0xb
#define HWIO_FEC_ESR_CORR_BOOT_ROM_BMSK                                                            0x400
#define HWIO_FEC_ESR_CORR_BOOT_ROM_SHFT                                                              0xa
#define HWIO_FEC_ESR_CORR_FUSE_SENSE_BMSK                                                          0x200
#define HWIO_FEC_ESR_CORR_FUSE_SENSE_SHFT                                                            0x9
#define HWIO_FEC_ESR_CORR_MULT_BMSK                                                                0x100
#define HWIO_FEC_ESR_CORR_MULT_SHFT                                                                  0x8
#define HWIO_FEC_ESR_CORR_SEEN_BMSK                                                                 0x80
#define HWIO_FEC_ESR_CORR_SEEN_SHFT                                                                  0x7
#define HWIO_FEC_ESR_ERR_SW_ACC_BMSK                                                                0x40
#define HWIO_FEC_ESR_ERR_SW_ACC_SHFT                                                                 0x6
#define HWIO_FEC_ESR_ERR_SECURE_CHANNEL_BMSK                                                        0x10
#define HWIO_FEC_ESR_ERR_SECURE_CHANNEL_SHFT                                                         0x4
#define HWIO_FEC_ESR_ERR_BOOT_ROM_BMSK                                                               0x8
#define HWIO_FEC_ESR_ERR_BOOT_ROM_SHFT                                                               0x3
#define HWIO_FEC_ESR_ERR_FUSE_SENSE_BMSK                                                             0x4
#define HWIO_FEC_ESR_ERR_FUSE_SENSE_SHFT                                                             0x2
#define HWIO_FEC_ESR_ERR_MULT_BMSK                                                                   0x2
#define HWIO_FEC_ESR_ERR_MULT_SHFT                                                                   0x1
#define HWIO_FEC_ESR_ERR_SEEN_BMSK                                                                   0x1
#define HWIO_FEC_ESR_ERR_SEEN_SHFT                                                                   0x0

#define HWIO_FEC_EAR_ADDR                                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000205c)
#define HWIO_FEC_EAR_PHYS                                                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000205c)
#define HWIO_FEC_EAR_RMSK                                                                     0xffffffff
#define HWIO_FEC_EAR_IN          \
        in_dword_masked(HWIO_FEC_EAR_ADDR, HWIO_FEC_EAR_RMSK)
#define HWIO_FEC_EAR_INM(m)      \
        in_dword_masked(HWIO_FEC_EAR_ADDR, m)
#define HWIO_FEC_EAR_CORR_ADDR_BMSK                                                           0xffff0000
#define HWIO_FEC_EAR_CORR_ADDR_SHFT                                                                 0x10
#define HWIO_FEC_EAR_ERR_ADDR_BMSK                                                                0xffff
#define HWIO_FEC_EAR_ERR_ADDR_SHFT                                                                   0x0

#define HWIO_QFPROM_BIST_CTRL_ADDR                                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002060)
#define HWIO_QFPROM_BIST_CTRL_PHYS                                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002060)
#define HWIO_QFPROM_BIST_CTRL_RMSK                                                                  0xff
#define HWIO_QFPROM_BIST_CTRL_IN          \
        in_dword_masked(HWIO_QFPROM_BIST_CTRL_ADDR, HWIO_QFPROM_BIST_CTRL_RMSK)
#define HWIO_QFPROM_BIST_CTRL_INM(m)      \
        in_dword_masked(HWIO_QFPROM_BIST_CTRL_ADDR, m)
#define HWIO_QFPROM_BIST_CTRL_OUT(v)      \
        out_dword(HWIO_QFPROM_BIST_CTRL_ADDR,v)
#define HWIO_QFPROM_BIST_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_BIST_CTRL_ADDR,m,v,HWIO_QFPROM_BIST_CTRL_IN)
#define HWIO_QFPROM_BIST_CTRL_AUTH_REGION_BMSK                                                      0xfc
#define HWIO_QFPROM_BIST_CTRL_AUTH_REGION_SHFT                                                       0x2
#define HWIO_QFPROM_BIST_CTRL_SHA_ENABLE_BMSK                                                        0x2
#define HWIO_QFPROM_BIST_CTRL_SHA_ENABLE_SHFT                                                        0x1
#define HWIO_QFPROM_BIST_CTRL_START_BMSK                                                             0x1
#define HWIO_QFPROM_BIST_CTRL_START_SHFT                                                             0x0

#define HWIO_QFPROM_BIST_ERROR0_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002064)
#define HWIO_QFPROM_BIST_ERROR0_PHYS                                                          (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002064)
#define HWIO_QFPROM_BIST_ERROR0_RMSK                                                          0xffffffff
#define HWIO_QFPROM_BIST_ERROR0_IN          \
        in_dword_masked(HWIO_QFPROM_BIST_ERROR0_ADDR, HWIO_QFPROM_BIST_ERROR0_RMSK)
#define HWIO_QFPROM_BIST_ERROR0_INM(m)      \
        in_dword_masked(HWIO_QFPROM_BIST_ERROR0_ADDR, m)
#define HWIO_QFPROM_BIST_ERROR0_ERROR_BMSK                                                    0xffffffff
#define HWIO_QFPROM_BIST_ERROR0_ERROR_SHFT                                                           0x0

#define HWIO_QFPROM_BIST_ERROR1_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002068)
#define HWIO_QFPROM_BIST_ERROR1_PHYS                                                          (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002068)
#define HWIO_QFPROM_BIST_ERROR1_RMSK                                                          0xffffffff
#define HWIO_QFPROM_BIST_ERROR1_IN          \
        in_dword_masked(HWIO_QFPROM_BIST_ERROR1_ADDR, HWIO_QFPROM_BIST_ERROR1_RMSK)
#define HWIO_QFPROM_BIST_ERROR1_INM(m)      \
        in_dword_masked(HWIO_QFPROM_BIST_ERROR1_ADDR, m)
#define HWIO_QFPROM_BIST_ERROR1_ERROR_BMSK                                                    0xffffffff
#define HWIO_QFPROM_BIST_ERROR1_ERROR_SHFT                                                           0x0

#define HWIO_QFPROM_HASH_SIGNATUREn_ADDR(n)                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000206c + 0x4 * (n))
#define HWIO_QFPROM_HASH_SIGNATUREn_PHYS(n)                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000206c + 0x4 * (n))
#define HWIO_QFPROM_HASH_SIGNATUREn_RMSK                                                      0xffffffff
#define HWIO_QFPROM_HASH_SIGNATUREn_MAXn                                                               7
#define HWIO_QFPROM_HASH_SIGNATUREn_INI(n)        \
        in_dword_masked(HWIO_QFPROM_HASH_SIGNATUREn_ADDR(n), HWIO_QFPROM_HASH_SIGNATUREn_RMSK)
#define HWIO_QFPROM_HASH_SIGNATUREn_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_HASH_SIGNATUREn_ADDR(n), mask)
#define HWIO_QFPROM_HASH_SIGNATUREn_HASH_VALUE_BMSK                                           0xffffffff
#define HWIO_QFPROM_HASH_SIGNATUREn_HASH_VALUE_SHFT                                                  0x0

#define HWIO_HW_KEY_STATUS_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000208c)
#define HWIO_HW_KEY_STATUS_PHYS                                                               (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000208c)
#define HWIO_HW_KEY_STATUS_RMSK                                                                    0x7ff
#define HWIO_HW_KEY_STATUS_IN          \
        in_dword_masked(HWIO_HW_KEY_STATUS_ADDR, HWIO_HW_KEY_STATUS_RMSK)
#define HWIO_HW_KEY_STATUS_INM(m)      \
        in_dword_masked(HWIO_HW_KEY_STATUS_ADDR, m)
#define HWIO_HW_KEY_STATUS_MSA_SECURE_BMSK                                                         0x400
#define HWIO_HW_KEY_STATUS_MSA_SECURE_SHFT                                                           0xa
#define HWIO_HW_KEY_STATUS_APPS_SECURE_BMSK                                                        0x200
#define HWIO_HW_KEY_STATUS_APPS_SECURE_SHFT                                                          0x9
#define HWIO_HW_KEY_STATUS_KDF_AND_HW_KEY_SHIFT_DONE_BMSK                                          0x100
#define HWIO_HW_KEY_STATUS_KDF_AND_HW_KEY_SHIFT_DONE_SHFT                                            0x8
#define HWIO_HW_KEY_STATUS_HW_KEY_SHIFT_DONE_BMSK                                                   0x80
#define HWIO_HW_KEY_STATUS_HW_KEY_SHIFT_DONE_SHFT                                                    0x7
#define HWIO_HW_KEY_STATUS_FUSE_SENSE_DONE_BMSK                                                     0x40
#define HWIO_HW_KEY_STATUS_FUSE_SENSE_DONE_SHFT                                                      0x6
#define HWIO_HW_KEY_STATUS_CRI_CM_BOOT_DONE_BMSK                                                    0x20
#define HWIO_HW_KEY_STATUS_CRI_CM_BOOT_DONE_SHFT                                                     0x5
#define HWIO_HW_KEY_STATUS_KDF_DONE_BMSK                                                            0x10
#define HWIO_HW_KEY_STATUS_KDF_DONE_SHFT                                                             0x4
#define HWIO_HW_KEY_STATUS_MSA_KEYS_BLOCKED_BMSK                                                     0x8
#define HWIO_HW_KEY_STATUS_MSA_KEYS_BLOCKED_SHFT                                                     0x3
#define HWIO_HW_KEY_STATUS_APPS_KEYS_BLOCKED_BMSK                                                    0x4
#define HWIO_HW_KEY_STATUS_APPS_KEYS_BLOCKED_SHFT                                                    0x2
#define HWIO_HW_KEY_STATUS_SEC_KEY_DERIVATION_KEY_BLOWN_BMSK                                         0x2
#define HWIO_HW_KEY_STATUS_SEC_KEY_DERIVATION_KEY_BLOWN_SHFT                                         0x1
#define HWIO_HW_KEY_STATUS_PRI_KEY_DERIVATION_KEY_BLOWN_BMSK                                         0x1
#define HWIO_HW_KEY_STATUS_PRI_KEY_DERIVATION_KEY_BLOWN_SHFT                                         0x0

#define HWIO_RESET_JDR_STATUS_ADDR                                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002090)
#define HWIO_RESET_JDR_STATUS_PHYS                                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002090)
#define HWIO_RESET_JDR_STATUS_RMSK                                                                   0x3
#define HWIO_RESET_JDR_STATUS_IN          \
        in_dword_masked(HWIO_RESET_JDR_STATUS_ADDR, HWIO_RESET_JDR_STATUS_RMSK)
#define HWIO_RESET_JDR_STATUS_INM(m)      \
        in_dword_masked(HWIO_RESET_JDR_STATUS_ADDR, m)
#define HWIO_RESET_JDR_STATUS_FORCE_RESET_BMSK                                                       0x2
#define HWIO_RESET_JDR_STATUS_FORCE_RESET_SHFT                                                       0x1
#define HWIO_RESET_JDR_STATUS_DISABLE_SYSTEM_RESET_BMSK                                              0x1
#define HWIO_RESET_JDR_STATUS_DISABLE_SYSTEM_RESET_SHFT                                              0x0

#define HWIO_ATPG_JDR_STATUS_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002094)
#define HWIO_ATPG_JDR_STATUS_PHYS                                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002094)
#define HWIO_ATPG_JDR_STATUS_RMSK                                                                    0x1
#define HWIO_ATPG_JDR_STATUS_IN          \
        in_dword_masked(HWIO_ATPG_JDR_STATUS_ADDR, HWIO_ATPG_JDR_STATUS_RMSK)
#define HWIO_ATPG_JDR_STATUS_INM(m)      \
        in_dword_masked(HWIO_ATPG_JDR_STATUS_ADDR, m)
#define HWIO_ATPG_JDR_STATUS_FUSE_SENSE_ATPG_CTL_BMSK                                                0x1
#define HWIO_ATPG_JDR_STATUS_FUSE_SENSE_ATPG_CTL_SHFT                                                0x0

#define HWIO_FEAT_PROV_OUTn_ADDR(n)                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002098 + 0x4 * (n))
#define HWIO_FEAT_PROV_OUTn_PHYS(n)                                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002098 + 0x4 * (n))
#define HWIO_FEAT_PROV_OUTn_RMSK                                                              0xffffffff
#define HWIO_FEAT_PROV_OUTn_MAXn                                                                       3
#define HWIO_FEAT_PROV_OUTn_INI(n)        \
        in_dword_masked(HWIO_FEAT_PROV_OUTn_ADDR(n), HWIO_FEAT_PROV_OUTn_RMSK)
#define HWIO_FEAT_PROV_OUTn_INMI(n,mask)    \
        in_dword_masked(HWIO_FEAT_PROV_OUTn_ADDR(n), mask)
#define HWIO_FEAT_PROV_OUTn_FEAT_PROV_OUT_VALUE_BMSK                                          0xffffffff
#define HWIO_FEAT_PROV_OUTn_FEAT_PROV_OUT_VALUE_SHFT                                                 0x0

#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_ADDR(n)                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000020a8 + 0x4 * (n))
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_PHYS(n)                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000020a8 + 0x4 * (n))
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_RMSK                                                0xffffffff
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_MAXn                                                         3
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_INI(n)        \
        in_dword_masked(HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_ADDR(n), HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_RMSK)
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_INMI(n,mask)    \
        in_dword_masked(HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_ADDR(n), mask)
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_SEC_CTRL_MISC_CONFIG_STATUS_VALUE_BMSK              0xffffffff
#define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_SEC_CTRL_MISC_CONFIG_STATUS_VALUE_SHFT                     0x0

#define HWIO_DEBUG_FUSE_STATUS_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x000020f0)
#define HWIO_DEBUG_FUSE_STATUS_PHYS                                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000020f0)
#define HWIO_DEBUG_FUSE_STATUS_RMSK                                                           0xffffffff
#define HWIO_DEBUG_FUSE_STATUS_IN          \
        in_dword_masked(HWIO_DEBUG_FUSE_STATUS_ADDR, HWIO_DEBUG_FUSE_STATUS_RMSK)
#define HWIO_DEBUG_FUSE_STATUS_INM(m)      \
        in_dword_masked(HWIO_DEBUG_FUSE_STATUS_ADDR, m)
#define HWIO_DEBUG_FUSE_STATUS_RSVD0_BMSK                                                     0xfffc0000
#define HWIO_DEBUG_FUSE_STATUS_RSVD0_SHFT                                                           0x12
#define HWIO_DEBUG_FUSE_STATUS_APPS_NIDEN_BMSK                                                   0x20000
#define HWIO_DEBUG_FUSE_STATUS_APPS_NIDEN_SHFT                                                      0x11
#define HWIO_DEBUG_FUSE_STATUS_APPS_DBGEN_BMSK                                                   0x10000
#define HWIO_DEBUG_FUSE_STATUS_APPS_DBGEN_SHFT                                                      0x10
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_QSEE_SPNIDEN_BMSK                                          0x8000
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_QSEE_SPNIDEN_SHFT                                             0xf
#define HWIO_DEBUG_FUSE_STATUS_SHARED_QSEE_SPNIDEN_BMSK                                           0x4000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_QSEE_SPNIDEN_SHFT                                              0xe
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_MSS_NIDEN_BMSK                                             0x2000
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_MSS_NIDEN_SHFT                                                0xd
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MSS_NIDEN_BMSK                                              0x1000
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MSS_NIDEN_SHFT                                                 0xc
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_CP_NIDEN_BMSK                                               0x800
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_CP_NIDEN_SHFT                                                 0xb
#define HWIO_DEBUG_FUSE_STATUS_SHARED_CP_NIDEN_BMSK                                                0x400
#define HWIO_DEBUG_FUSE_STATUS_SHARED_CP_NIDEN_SHFT                                                  0xa
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_NS_NIDEN_BMSK                                               0x200
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_NS_NIDEN_SHFT                                                 0x9
#define HWIO_DEBUG_FUSE_STATUS_SHARED_NS_NIDEN_BMSK                                                0x100
#define HWIO_DEBUG_FUSE_STATUS_SHARED_NS_NIDEN_SHFT                                                  0x8
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_QSEE_SPIDEN_BMSK                                             0x80
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_QSEE_SPIDEN_SHFT                                              0x7
#define HWIO_DEBUG_FUSE_STATUS_SHARED_QSEE_SPIDEN_BMSK                                              0x40
#define HWIO_DEBUG_FUSE_STATUS_SHARED_QSEE_SPIDEN_SHFT                                               0x6
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_MSS_DBGEN_BMSK                                               0x20
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_MSS_DBGEN_SHFT                                                0x5
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MSS_DBGEN_BMSK                                                0x10
#define HWIO_DEBUG_FUSE_STATUS_SHARED_MSS_DBGEN_SHFT                                                 0x4
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_CP_DBGEN_BMSK                                                 0x8
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_CP_DBGEN_SHFT                                                 0x3
#define HWIO_DEBUG_FUSE_STATUS_SHARED_CP_DBGEN_BMSK                                                  0x4
#define HWIO_DEBUG_FUSE_STATUS_SHARED_CP_DBGEN_SHFT                                                  0x2
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_NS_DBGEN_BMSK                                                 0x2
#define HWIO_DEBUG_FUSE_STATUS_PRIVATE_NS_DBGEN_SHFT                                                 0x1
#define HWIO_DEBUG_FUSE_STATUS_SHARED_NS_DBGEN_BMSK                                                  0x1
#define HWIO_DEBUG_FUSE_STATUS_SHARED_NS_DBGEN_SHFT                                                  0x0

#define HWIO_HW_ATTESTATION_CTRL0_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002100)
#define HWIO_HW_ATTESTATION_CTRL0_PHYS                                                        (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002100)
#define HWIO_HW_ATTESTATION_CTRL0_RMSK                                                        0x1fffffff
#define HWIO_HW_ATTESTATION_CTRL0_IN          \
        in_dword_masked(HWIO_HW_ATTESTATION_CTRL0_ADDR, HWIO_HW_ATTESTATION_CTRL0_RMSK)
#define HWIO_HW_ATTESTATION_CTRL0_INM(m)      \
        in_dword_masked(HWIO_HW_ATTESTATION_CTRL0_ADDR, m)
#define HWIO_HW_ATTESTATION_CTRL0_OUT(v)      \
        out_dword(HWIO_HW_ATTESTATION_CTRL0_ADDR,v)
#define HWIO_HW_ATTESTATION_CTRL0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_HW_ATTESTATION_CTRL0_ADDR,m,v,HWIO_HW_ATTESTATION_CTRL0_IN)
#define HWIO_HW_ATTESTATION_CTRL0_REGION_BMSK                                                 0x1f800000
#define HWIO_HW_ATTESTATION_CTRL0_REGION_SHFT                                                       0x17
#define HWIO_HW_ATTESTATION_CTRL0_CONTEXT_STRING_BMSK                                           0x7fff80
#define HWIO_HW_ATTESTATION_CTRL0_CONTEXT_STRING_SHFT                                                0x7
#define HWIO_HW_ATTESTATION_CTRL0_KEY_SELECT_BMSK                                                   0x78
#define HWIO_HW_ATTESTATION_CTRL0_KEY_SELECT_SHFT                                                    0x3
#define HWIO_HW_ATTESTATION_CTRL0_OPERATION_BMSK                                                     0x7
#define HWIO_HW_ATTESTATION_CTRL0_OPERATION_SHFT                                                     0x0

#define HWIO_HW_ATTESTATION_CTRL1_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002104)
#define HWIO_HW_ATTESTATION_CTRL1_PHYS                                                        (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002104)
#define HWIO_HW_ATTESTATION_CTRL1_RMSK                                                        0xffffffff
#define HWIO_HW_ATTESTATION_CTRL1_IN          \
        in_dword_masked(HWIO_HW_ATTESTATION_CTRL1_ADDR, HWIO_HW_ATTESTATION_CTRL1_RMSK)
#define HWIO_HW_ATTESTATION_CTRL1_INM(m)      \
        in_dword_masked(HWIO_HW_ATTESTATION_CTRL1_ADDR, m)
#define HWIO_HW_ATTESTATION_CTRL1_OUT(v)      \
        out_dword(HWIO_HW_ATTESTATION_CTRL1_ADDR,v)
#define HWIO_HW_ATTESTATION_CTRL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_HW_ATTESTATION_CTRL1_ADDR,m,v,HWIO_HW_ATTESTATION_CTRL1_IN)
#define HWIO_HW_ATTESTATION_CTRL1_NONCE_BMSK                                                  0xffffffff
#define HWIO_HW_ATTESTATION_CTRL1_NONCE_SHFT                                                         0x0

#define HWIO_HW_ATTESTATION_CMD_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002108)
#define HWIO_HW_ATTESTATION_CMD_PHYS                                                          (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002108)
#define HWIO_HW_ATTESTATION_CMD_RMSK                                                                 0x1
#define HWIO_HW_ATTESTATION_CMD_OUT(v)      \
        out_dword(HWIO_HW_ATTESTATION_CMD_ADDR,v)
#define HWIO_HW_ATTESTATION_CMD_OPERATION_COMMAND_BMSK                                               0x1
#define HWIO_HW_ATTESTATION_CMD_OPERATION_COMMAND_SHFT                                               0x0

#define HWIO_HW_ATTESTATION_STATUS_ADDR                                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000210c)
#define HWIO_HW_ATTESTATION_STATUS_PHYS                                                       (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000210c)
#define HWIO_HW_ATTESTATION_STATUS_RMSK                                                       0xffffffff
#define HWIO_HW_ATTESTATION_STATUS_IN          \
        in_dword_masked(HWIO_HW_ATTESTATION_STATUS_ADDR, HWIO_HW_ATTESTATION_STATUS_RMSK)
#define HWIO_HW_ATTESTATION_STATUS_INM(m)      \
        in_dword_masked(HWIO_HW_ATTESTATION_STATUS_ADDR, m)
#define HWIO_HW_ATTESTATION_STATUS_STATUS_BMSK                                                0xffffffff
#define HWIO_HW_ATTESTATION_STATUS_STATUS_SHFT                                                       0x0

#define HWIO_HW_ATTESTATION_ERROR_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002110)
#define HWIO_HW_ATTESTATION_ERROR_PHYS                                                        (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002110)
#define HWIO_HW_ATTESTATION_ERROR_RMSK                                                        0xffffffff
#define HWIO_HW_ATTESTATION_ERROR_IN          \
        in_dword_masked(HWIO_HW_ATTESTATION_ERROR_ADDR, HWIO_HW_ATTESTATION_ERROR_RMSK)
#define HWIO_HW_ATTESTATION_ERROR_INM(m)      \
        in_dword_masked(HWIO_HW_ATTESTATION_ERROR_ADDR, m)
#define HWIO_HW_ATTESTATION_ERROR_ERROR_BMSK                                                  0xffffffff
#define HWIO_HW_ATTESTATION_ERROR_ERROR_SHFT                                                         0x0

#define HWIO_HW_ATTESTATION_RESULTn_ADDR(n)                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00002120 + 0x4 * (n))
#define HWIO_HW_ATTESTATION_RESULTn_PHYS(n)                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002120 + 0x4 * (n))
#define HWIO_HW_ATTESTATION_RESULTn_RMSK                                                      0xffffffff
#define HWIO_HW_ATTESTATION_RESULTn_MAXn                                                               7
#define HWIO_HW_ATTESTATION_RESULTn_INI(n)        \
        in_dword_masked(HWIO_HW_ATTESTATION_RESULTn_ADDR(n), HWIO_HW_ATTESTATION_RESULTn_RMSK)
#define HWIO_HW_ATTESTATION_RESULTn_INMI(n,mask)    \
        in_dword_masked(HWIO_HW_ATTESTATION_RESULTn_ADDR(n), mask)
#define HWIO_HW_ATTESTATION_RESULTn_RESULT_BMSK                                               0xffffffff
#define HWIO_HW_ATTESTATION_RESULTn_RESULT_SHFT                                                      0x0

#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_ADDR(n)                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004000 + 0x4 * (n))
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_PHYS(n)                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004000 + 0x4 * (n))
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_MAXn                                                         71
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_ADDR(n), HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_RMSK)
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_ADDR(n), mask)
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_CRI_CM_PRIVATE_BMSK                                  0xffffffff
#define HWIO_QFPROM_CORR_CRI_CM_PRIVATEn_CRI_CM_PRIVATE_SHFT                                         0x0

#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004120)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_PHYS                                                (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004120)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ADDR, HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_RMSK)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_RSVD0_BMSK                                          0xfffffff0
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_RSVD0_SHFT                                                 0x4
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ROOT_CERT_ACTIVATION_LIST_BMSK                             0xf
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ROOT_CERT_ACTIVATION_LIST_SHFT                             0x0

#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004124)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_PHYS                                                (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004124)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_ADDR, HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_RMSK)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_RSVD1_BMSK                                          0xfffffffe
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_RSVD1_SHFT                                                 0x1
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_CURRENT_UIE_KEY_SEL_BMSK                                   0x1
#define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_CURRENT_UIE_KEY_SEL_SHFT                                   0x0

#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004128)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_PHYS                                                (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004128)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ADDR, HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_RMSK)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_RSVD0_BMSK                                          0xfffffff0
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_RSVD0_SHFT                                                 0x4
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ROOT_CERT_REVOCATION_LIST_BMSK                             0xf
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ROOT_CERT_REVOCATION_LIST_SHFT                             0x0

#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_ADDR                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000412c)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_PHYS                                                (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000412c)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_RMSK                                                0xffffffff
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_ADDR, HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_RMSK)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_RSVD0_BMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_RSVD0_SHFT                                                 0x0

#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004130)
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_PHYS                                                    (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004130)
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW0_LSB_ADDR, HWIO_QFPROM_CORR_PTE_ROW0_LSB_RMSK)
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_PTE_DATA0_BMSK                                          0xe0000000
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_PTE_DATA0_SHFT                                                0x1d
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_MACCHIATO_EN_BMSK                                       0x10000000
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_MACCHIATO_EN_SHFT                                             0x1c
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_FEATURE_ID_BMSK                                          0xff00000
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_FEATURE_ID_SHFT                                               0x14
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_JTAG_ID_BMSK                                               0xfffff
#define HWIO_QFPROM_CORR_PTE_ROW0_LSB_JTAG_ID_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004134)
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_PHYS                                                    (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004134)
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW0_MSB_ADDR, HWIO_QFPROM_CORR_PTE_ROW0_MSB_RMSK)
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_PTE_DATA1_BMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW0_MSB_PTE_DATA1_SHFT                                                 0x0

#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004138)
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_PHYS                                                    (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004138)
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW1_LSB_ADDR, HWIO_QFPROM_CORR_PTE_ROW1_LSB_RMSK)
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_SERIAL_NUM_BMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW1_LSB_SERIAL_NUM_SHFT                                                0x0

#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000413c)
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_PHYS                                                    (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000413c)
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW1_MSB_ADDR, HWIO_QFPROM_CORR_PTE_ROW1_MSB_RMSK)
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_PTE_DATA1_BMSK                                          0xffff0000
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_PTE_DATA1_SHFT                                                0x10
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_CHIP_ID_BMSK                                                0xffff
#define HWIO_QFPROM_CORR_PTE_ROW1_MSB_CHIP_ID_SHFT                                                   0x0

#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004140)
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_PHYS                                                    (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004140)
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW2_LSB_ADDR, HWIO_QFPROM_CORR_PTE_ROW2_LSB_RMSK)
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_PTE_DATA0_BMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW2_LSB_PTE_DATA0_SHFT                                                 0x0

#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004144)
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_PHYS                                                    (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004144)
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW2_MSB_ADDR, HWIO_QFPROM_CORR_PTE_ROW2_MSB_RMSK)
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_PTE_DATA1_BMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW2_MSB_PTE_DATA1_SHFT                                                 0x0

#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004148)
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_PHYS                                                    (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004148)
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW3_LSB_ADDR, HWIO_QFPROM_CORR_PTE_ROW3_LSB_RMSK)
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_PTE_DATA0_BMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW3_LSB_PTE_DATA0_SHFT                                                 0x0

#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_ADDR                                                    (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000414c)
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_PHYS                                                    (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000414c)
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_RMSK                                                    0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW3_MSB_ADDR, HWIO_QFPROM_CORR_PTE_ROW3_MSB_RMSK)
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_PTE_DATA1_BMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_PTE_ROW3_MSB_PTE_DATA1_SHFT                                                 0x0

#define HWIO_QFPROM_CORR_RD_PERM_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004150)
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PHYS                                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004150)
#define HWIO_QFPROM_CORR_RD_PERM_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_CORR_RD_PERM_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_RD_PERM_LSB_ADDR, HWIO_QFPROM_CORR_RD_PERM_LSB_RMSK)
#define HWIO_QFPROM_CORR_RD_PERM_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_RD_PERM_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_RD_PERM_LSB_RSVD0_BMSK                                               0x80000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_RSVD0_SHFT                                                     0x1f
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG30_BMSK                                     0x40000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG30_SHFT                                           0x1e
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG29_BMSK                                     0x20000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG29_SHFT                                           0x1d
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG28_BMSK                                     0x10000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG28_SHFT                                           0x1c
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG27_BMSK                                      0x8000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG27_SHFT                                           0x1b
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG26_BMSK                                      0x4000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SPARE_REG26_SHFT                                           0x1a
#define HWIO_QFPROM_CORR_RD_PERM_LSB_USER_DATA_KEY_BMSK                                        0x2000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_USER_DATA_KEY_SHFT                                             0x19
#define HWIO_QFPROM_CORR_RD_PERM_LSB_IMAGE_ENCR_KEY1_BMSK                                      0x1000000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_IMAGE_ENCR_KEY1_SHFT                                           0x18
#define HWIO_QFPROM_CORR_RD_PERM_LSB_BOOT_ROM_PATCH_BMSK                                        0x800000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_BOOT_ROM_PATCH_SHFT                                            0x17
#define HWIO_QFPROM_CORR_RD_PERM_LSB_SEC_KEY_DERIVATION_KEY_BMSK                                0x400000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_SEC_KEY_DERIVATION_KEY_SHFT                                    0x16
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PRI_KEY_DERIVATION_KEY_BMSK                                0x200000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PRI_KEY_DERIVATION_KEY_SHFT                                    0x15
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SEC_BOOT_BMSK                                          0x100000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_SEC_BOOT_SHFT                                              0x14
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_IMAGE_ENCR_KEY_BMSK                                     0x80000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_IMAGE_ENCR_KEY_SHFT                                        0x13
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG18_BMSK                                         0x40000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG18_SHFT                                            0x12
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG17_BMSK                                         0x20000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG17_SHFT                                            0x11
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG16_BMSK                                         0x10000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_QC_SPARE_REG16_SHFT                                            0x10
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CM_FEAT_CONFIG_BMSK                                          0x8000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CM_FEAT_CONFIG_SHFT                                             0xf
#define HWIO_QFPROM_CORR_RD_PERM_LSB_MEM_CONFIG_BMSK                                              0x4000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_MEM_CONFIG_SHFT                                                 0xe
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CALIB_BMSK                                                   0x2000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CALIB_SHFT                                                      0xd
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PK_HASH0_BMSK                                                0x1000
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PK_HASH0_SHFT                                                   0xc
#define HWIO_QFPROM_CORR_RD_PERM_LSB_FEAT_CONFIG_BMSK                                              0x800
#define HWIO_QFPROM_CORR_RD_PERM_LSB_FEAT_CONFIG_SHFT                                                0xb
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_CONFIG_BMSK                                               0x400
#define HWIO_QFPROM_CORR_RD_PERM_LSB_OEM_CONFIG_SHFT                                                 0xa
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_4_BMSK                                          0x200
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_4_SHFT                                            0x9
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_3_BMSK                                          0x100
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_3_SHFT                                            0x8
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_2_BMSK                                           0x80
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_2_SHFT                                            0x7
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_1_BMSK                                           0x40
#define HWIO_QFPROM_CORR_RD_PERM_LSB_ANTI_ROLLBACK_1_SHFT                                            0x6
#define HWIO_QFPROM_CORR_RD_PERM_LSB_FEC_EN_BMSK                                                    0x20
#define HWIO_QFPROM_CORR_RD_PERM_LSB_FEC_EN_SHFT                                                     0x5
#define HWIO_QFPROM_CORR_RD_PERM_LSB_WR_PERM_BMSK                                                   0x10
#define HWIO_QFPROM_CORR_RD_PERM_LSB_WR_PERM_SHFT                                                    0x4
#define HWIO_QFPROM_CORR_RD_PERM_LSB_RD_PERM_BMSK                                                    0x8
#define HWIO_QFPROM_CORR_RD_PERM_LSB_RD_PERM_SHFT                                                    0x3
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PTE_BMSK                                                        0x4
#define HWIO_QFPROM_CORR_RD_PERM_LSB_PTE_SHFT                                                        0x2
#define HWIO_QFPROM_CORR_RD_PERM_LSB_MRC_2_0_BMSK                                                    0x2
#define HWIO_QFPROM_CORR_RD_PERM_LSB_MRC_2_0_SHFT                                                    0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CRI_CM_PRIVATE_BMSK                                             0x1
#define HWIO_QFPROM_CORR_RD_PERM_LSB_CRI_CM_PRIVATE_SHFT                                             0x0

#define HWIO_QFPROM_CORR_RD_PERM_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004154)
#define HWIO_QFPROM_CORR_RD_PERM_MSB_PHYS                                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004154)
#define HWIO_QFPROM_CORR_RD_PERM_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_CORR_RD_PERM_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_RD_PERM_MSB_ADDR, HWIO_QFPROM_CORR_RD_PERM_MSB_RMSK)
#define HWIO_QFPROM_CORR_RD_PERM_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_RD_PERM_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_RD_PERM_MSB_RSVD0_BMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_RD_PERM_MSB_RSVD0_SHFT                                                      0x0

#define HWIO_QFPROM_CORR_WR_PERM_LSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004158)
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PHYS                                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004158)
#define HWIO_QFPROM_CORR_WR_PERM_LSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_CORR_WR_PERM_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_WR_PERM_LSB_ADDR, HWIO_QFPROM_CORR_WR_PERM_LSB_RMSK)
#define HWIO_QFPROM_CORR_WR_PERM_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_WR_PERM_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_WR_PERM_LSB_RSVD0_BMSK                                               0x80000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_RSVD0_SHFT                                                     0x1f
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG30_BMSK                                     0x40000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG30_SHFT                                           0x1e
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG29_BMSK                                     0x20000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG29_SHFT                                           0x1d
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG28_BMSK                                     0x10000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG28_SHFT                                           0x1c
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG27_BMSK                                      0x8000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG27_SHFT                                           0x1b
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG26_BMSK                                      0x4000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SPARE_REG26_SHFT                                           0x1a
#define HWIO_QFPROM_CORR_WR_PERM_LSB_USER_DATA_KEY_BMSK                                        0x2000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_USER_DATA_KEY_SHFT                                             0x19
#define HWIO_QFPROM_CORR_WR_PERM_LSB_IMAGE_ENCR_KEY1_BMSK                                      0x1000000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_IMAGE_ENCR_KEY1_SHFT                                           0x18
#define HWIO_QFPROM_CORR_WR_PERM_LSB_BOOT_ROM_PATCH_BMSK                                        0x800000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_BOOT_ROM_PATCH_SHFT                                            0x17
#define HWIO_QFPROM_CORR_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_BMSK                                0x400000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_SHFT                                    0x16
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PRI_KEY_DERIVATION_KEY_BMSK                                0x200000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PRI_KEY_DERIVATION_KEY_SHFT                                    0x15
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SEC_BOOT_BMSK                                          0x100000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_SEC_BOOT_SHFT                                              0x14
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_IMAGE_ENCR_KEY_BMSK                                     0x80000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_IMAGE_ENCR_KEY_SHFT                                        0x13
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG18_BMSK                                         0x40000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG18_SHFT                                            0x12
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG17_BMSK                                         0x20000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG17_SHFT                                            0x11
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG16_BMSK                                         0x10000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_QC_SPARE_REG16_SHFT                                            0x10
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CM_FEAT_CONFIG_BMSK                                          0x8000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CM_FEAT_CONFIG_SHFT                                             0xf
#define HWIO_QFPROM_CORR_WR_PERM_LSB_MEM_CONFIG_BMSK                                              0x4000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_MEM_CONFIG_SHFT                                                 0xe
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CALIB_BMSK                                                   0x2000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CALIB_SHFT                                                      0xd
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PK_HASH0_BMSK                                                0x1000
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PK_HASH0_SHFT                                                   0xc
#define HWIO_QFPROM_CORR_WR_PERM_LSB_FEAT_CONFIG_BMSK                                              0x800
#define HWIO_QFPROM_CORR_WR_PERM_LSB_FEAT_CONFIG_SHFT                                                0xb
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_CONFIG_BMSK                                               0x400
#define HWIO_QFPROM_CORR_WR_PERM_LSB_OEM_CONFIG_SHFT                                                 0xa
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_4_BMSK                                          0x200
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_4_SHFT                                            0x9
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_3_BMSK                                          0x100
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_3_SHFT                                            0x8
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_2_BMSK                                           0x80
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_2_SHFT                                            0x7
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_1_BMSK                                           0x40
#define HWIO_QFPROM_CORR_WR_PERM_LSB_ANTI_ROLLBACK_1_SHFT                                            0x6
#define HWIO_QFPROM_CORR_WR_PERM_LSB_FEC_EN_BMSK                                                    0x20
#define HWIO_QFPROM_CORR_WR_PERM_LSB_FEC_EN_SHFT                                                     0x5
#define HWIO_QFPROM_CORR_WR_PERM_LSB_WR_PERM_BMSK                                                   0x10
#define HWIO_QFPROM_CORR_WR_PERM_LSB_WR_PERM_SHFT                                                    0x4
#define HWIO_QFPROM_CORR_WR_PERM_LSB_RD_PERM_BMSK                                                    0x8
#define HWIO_QFPROM_CORR_WR_PERM_LSB_RD_PERM_SHFT                                                    0x3
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PTE_BMSK                                                        0x4
#define HWIO_QFPROM_CORR_WR_PERM_LSB_PTE_SHFT                                                        0x2
#define HWIO_QFPROM_CORR_WR_PERM_LSB_MRC_2_0_BMSK                                                    0x2
#define HWIO_QFPROM_CORR_WR_PERM_LSB_MRC_2_0_SHFT                                                    0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CRI_CM_PRIVATE_BMSK                                             0x1
#define HWIO_QFPROM_CORR_WR_PERM_LSB_CRI_CM_PRIVATE_SHFT                                             0x0

#define HWIO_QFPROM_CORR_WR_PERM_MSB_ADDR                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000415c)
#define HWIO_QFPROM_CORR_WR_PERM_MSB_PHYS                                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000415c)
#define HWIO_QFPROM_CORR_WR_PERM_MSB_RMSK                                                     0xffffffff
#define HWIO_QFPROM_CORR_WR_PERM_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_WR_PERM_MSB_ADDR, HWIO_QFPROM_CORR_WR_PERM_MSB_RMSK)
#define HWIO_QFPROM_CORR_WR_PERM_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_WR_PERM_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_WR_PERM_MSB_RSVD0_BMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_WR_PERM_MSB_RSVD0_SHFT                                                      0x0

#define HWIO_QFPROM_CORR_FEC_EN_LSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004160)
#define HWIO_QFPROM_CORR_FEC_EN_LSB_PHYS                                                      (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004160)
#define HWIO_QFPROM_CORR_FEC_EN_LSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_FEC_EN_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_FEC_EN_LSB_ADDR, HWIO_QFPROM_CORR_FEC_EN_LSB_RMSK)
#define HWIO_QFPROM_CORR_FEC_EN_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEC_EN_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEC_EN_LSB_RSVD0_BMSK                                                0x80000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_RSVD0_SHFT                                                      0x1f
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION30_FEC_EN_BMSK                                      0x40000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION30_FEC_EN_SHFT                                            0x1e
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION29_FEC_EN_BMSK                                      0x20000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION29_FEC_EN_SHFT                                            0x1d
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION28_FEC_EN_BMSK                                      0x10000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION28_FEC_EN_SHFT                                            0x1c
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION27_FEC_EN_BMSK                                       0x8000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION27_FEC_EN_SHFT                                            0x1b
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION26_FEC_EN_BMSK                                       0x4000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION26_FEC_EN_SHFT                                            0x1a
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION25_FEC_EN_BMSK                                       0x2000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION25_FEC_EN_SHFT                                            0x19
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION24_FEC_EN_BMSK                                       0x1000000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION24_FEC_EN_SHFT                                            0x18
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION23_FEC_EN_BMSK                                        0x800000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION23_FEC_EN_SHFT                                            0x17
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION22_FEC_EN_BMSK                                        0x400000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION22_FEC_EN_SHFT                                            0x16
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION21_FEC_EN_BMSK                                        0x200000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION21_FEC_EN_SHFT                                            0x15
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION20_FEC_EN_BMSK                                        0x100000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION20_FEC_EN_SHFT                                            0x14
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION19_FEC_EN_BMSK                                         0x80000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION19_FEC_EN_SHFT                                            0x13
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION18_FEC_EN_BMSK                                         0x40000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION18_FEC_EN_SHFT                                            0x12
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION17_FEC_EN_BMSK                                         0x20000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION17_FEC_EN_SHFT                                            0x11
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION16_FEC_EN_BMSK                                         0x10000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION16_FEC_EN_SHFT                                            0x10
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION15_FEC_EN_BMSK                                          0x8000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION15_FEC_EN_SHFT                                             0xf
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION14_FEC_EN_BMSK                                          0x4000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION14_FEC_EN_SHFT                                             0xe
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION13_FEC_EN_BMSK                                          0x2000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION13_FEC_EN_SHFT                                             0xd
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION12_FEC_EN_BMSK                                          0x1000
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION12_FEC_EN_SHFT                                             0xc
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION11_FEC_EN_BMSK                                           0x800
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION11_FEC_EN_SHFT                                             0xb
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION10_FEC_EN_BMSK                                           0x400
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION10_FEC_EN_SHFT                                             0xa
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION9_FEC_EN_BMSK                                            0x200
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION9_FEC_EN_SHFT                                              0x9
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION8_FEC_EN_BMSK                                            0x100
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION8_FEC_EN_SHFT                                              0x8
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION7_FEC_EN_BMSK                                             0x80
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION7_FEC_EN_SHFT                                              0x7
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION6_FEC_EN_BMSK                                             0x40
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION6_FEC_EN_SHFT                                              0x6
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION5_FEC_EN_BMSK                                             0x20
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION5_FEC_EN_SHFT                                              0x5
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION4_FEC_EN_BMSK                                             0x10
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION4_FEC_EN_SHFT                                              0x4
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION3_FEC_EN_BMSK                                              0x8
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION3_FEC_EN_SHFT                                              0x3
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION2_FEC_EN_BMSK                                              0x4
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION2_FEC_EN_SHFT                                              0x2
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION1_FEC_EN_BMSK                                              0x2
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION1_FEC_EN_SHFT                                              0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION0_FEC_EN_BMSK                                              0x1
#define HWIO_QFPROM_CORR_FEC_EN_LSB_REGION0_FEC_EN_SHFT                                              0x0

#define HWIO_QFPROM_CORR_FEC_EN_MSB_ADDR                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004164)
#define HWIO_QFPROM_CORR_FEC_EN_MSB_PHYS                                                      (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004164)
#define HWIO_QFPROM_CORR_FEC_EN_MSB_RMSK                                                      0xffffffff
#define HWIO_QFPROM_CORR_FEC_EN_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_FEC_EN_MSB_ADDR, HWIO_QFPROM_CORR_FEC_EN_MSB_RMSK)
#define HWIO_QFPROM_CORR_FEC_EN_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEC_EN_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEC_EN_MSB_RSVD0_BMSK                                                0xffffffff
#define HWIO_QFPROM_CORR_FEC_EN_MSB_RSVD0_SHFT                                                       0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004168)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004168)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_ADDR, HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_RMSK)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_XBL0_BMSK                                        0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_XBL0_SHFT                                               0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000416c)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000416c)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_ADDR, HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_RMSK)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_XBL1_BMSK                                        0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_XBL1_SHFT                                               0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004170)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004170)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_ADDR, HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_RMSK)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_PIL_SUBSYSTEM_31_0_BMSK                          0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_PIL_SUBSYSTEM_31_0_SHFT                                 0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004174)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004174)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_ADDR, HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_RMSK)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_XBL_SEC_BMSK                                     0xfe000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_XBL_SEC_SHFT                                           0x19
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_RPM_BMSK                                          0x1fe0000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_RPM_SHFT                                               0x11
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_TZ_BMSK                                             0x1ffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_TZ_SHFT                                                 0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004178)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004178)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_ADDR, HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RMSK)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RSVD1_BMSK                                       0xc0000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RSVD1_SHFT                                             0x1e
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_TQS_HASH_ACTIVE_BMSK                             0x3e000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_TQS_HASH_ACTIVE_SHFT                                   0x19
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_BMSK                         0x1000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_SHFT                              0x18
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_PIL_SUBSYSTEM_47_32_BMSK                           0xffff00
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_PIL_SUBSYSTEM_47_32_SHFT                                0x8
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_SAFESWITCH_BMSK                                        0xff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_SAFESWITCH_SHFT                                         0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000417c)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000417c)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_ADDR, HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_RMSK)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_RSVD1_BMSK                                       0xf0000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_RSVD1_SHFT                                             0x1c
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_DEVICE_CFG_BMSK                                   0xffe0000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_DEVICE_CFG_SHFT                                        0x11
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_DEBUG_POLICY_BMSK                                   0x1f000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_DEBUG_POLICY_SHFT                                       0xc
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_HYPERVISOR_BMSK                                       0xfff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_HYPERVISOR_SHFT                                         0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004180)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004180)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_ADDR, HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_RMSK)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_MSS_BMSK                                         0xffff0000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_MSS_SHFT                                               0x10
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_MBA_BMSK                                             0xffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_MBA_SHFT                                                0x0

#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004184)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004184)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ADDR, HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_RMSK)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_SIMLOCK_BMSK                                     0x80000000
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_SIMLOCK_SHFT                                           0x1f
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_RSVD0_BMSK                                       0x7fffffff
#define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_RSVD0_SHFT                                              0x0

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004188)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004188)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR, HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_OUT(v)      \
        out_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR,v)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_IN)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                 0x80000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                       0x1f
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_BMSK                  0x40000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_SHFT                        0x1e
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_BMSK                           0x20000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_SHFT                                 0x1d
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_BMSK                        0x10000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_SHFT                              0x1c
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SP_DISABLE_BMSK                                   0x8000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SP_DISABLE_SHFT                                        0x1b
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_BMSK                                  0x4000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_SHFT                                       0x1a
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_RSVD2_BMSK                                        0x2000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_RSVD2_SHFT                                             0x19
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_BMSK              0x1000000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_SHFT                   0x18
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_ENABLE_BMSK              0x800000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_ENABLE_SHFT                  0x17
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_BMSK                                0x400000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_SHFT                                    0x16
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_BMSK                         0x200000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_SHFT                             0x15
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_BMSK                          0x100000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_SHFT                              0x14
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_IMAGE_ENCRYPTION_ENABLE_BMSK                        0x80000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_IMAGE_ENCRYPTION_ENABLE_SHFT                           0x13
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ROOT_CERT_TOTAL_NUM_BMSK                            0x60000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ROOT_CERT_TOTAL_NUM_SHFT                               0x11
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_USB_TYPE_C_DISABLE_BMSK                         0x10000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_USB_TYPE_C_DISABLE_SHFT                            0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_LOG_DISABLE_BMSK                                 0x8000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_LOG_DISABLE_SHFT                                    0xf
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_WDOG_EN_BMSK                                         0x4000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_WDOG_EN_SHFT                                            0xe
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_RSVD1_BMSK                                           0x2000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_RSVD1_SHFT                                              0xd
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_FUSE_PROG_DISABLE_BMSK                            0x1000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_FUSE_PROG_DISABLE_SHFT                               0xc
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_RSVD0_BMSK                                            0xc00
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_RSVD0_SHFT                                              0xa
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_BMSK                                        0x3e0
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SHFT                                          0x5
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SDCC_MCLK_BOOT_FREQ_BMSK                               0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SDCC_MCLK_BOOT_FREQ_SHFT                                0x4
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_BMSK                             0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_SHFT                             0x3
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_BMSK                                0x4
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_SHFT                                0x2
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_BMSK                                       0x2
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_SHFT                                       0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_BMSK                                    0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_SHFT                                    0x0

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000418c)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000418c)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_ADDR, HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_RSVD0_BMSK                                       0xffffff00
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_RSVD0_SHFT                                              0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_BMSK                                0x80
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_SHFT                                 0x7
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_BMSK                                0x40
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_SHFT                                 0x6
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_BMSK                           0x20
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_SHFT                            0x5
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_BMSK                           0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_SHFT                            0x4
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_BMSK                            0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_SHFT                            0x3
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_BMSK                            0x4
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_SHFT                            0x2
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_BMSK                           0x2
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_SHFT                           0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_BMSK                           0x1
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_SHFT                           0x0

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004190)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004190)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_ADDR, HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_BMSK                                       0xffff8000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_SHFT                                              0xf
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG30_SECURE_BMSK                          0x4000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG30_SECURE_SHFT                             0xe
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG29_SECURE_BMSK                          0x2000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG29_SECURE_SHFT                             0xd
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG28_SECURE_BMSK                          0x1000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG28_SECURE_SHFT                             0xc
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG27_SECURE_BMSK                           0x800
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG27_SECURE_SHFT                             0xb
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG26_SECURE_BMSK                           0x400
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_OEM_SPARE_REG26_SECURE_SHFT                             0xa
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD0_BMSK                                            0x3ff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD0_SHFT                                              0x0

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004194)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004194)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_ADDR, HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OEM_PRODUCT_ID_BMSK                              0xffff0000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OEM_PRODUCT_ID_SHFT                                    0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OEM_HW_ID_BMSK                                       0xffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OEM_HW_ID_SHFT                                          0x0

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004198)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004198)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_ADDR, HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PERIPH_VID_BMSK                                  0xffff0000
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PERIPH_VID_SHFT                                        0x10
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PERIPH_PID_BMSK                                      0xffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PERIPH_PID_SHFT                                         0x0

#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ADDR                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000419c)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_PHYS                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000419c)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ADDR, HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_RSVD0_BMSK                                       0xffffff00
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_RSVD0_SHFT                                              0x8
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ANTI_ROLLBACK_FEATURE_EN_BMSK                          0xff
#define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ANTI_ROLLBACK_FEATURE_EN_SHFT                           0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041a0)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_PHYS                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041a0)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_ADDR, HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_RMSK)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_PCIE_PHY_DISABLE_UPPER_LANE_BMSK                0x80000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_PCIE_PHY_DISABLE_UPPER_LANE_SHFT                      0x1f
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_BMSK                    0x40000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_SHFT                          0x1e
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_BMSK                              0x20000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_SHFT                                    0x1d
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_BMSK                       0x1fe00000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_SHFT                             0x15
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_BMSK                        0x180000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_SHFT                            0x13
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_BMSK                      0x40000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_SHFT                         0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_BMSK                      0x20000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_SHFT                         0x11
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_BMSK                               0x10000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_SHFT                                  0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_BMSK                               0x8000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_SHFT                                  0xf
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_BMSK                               0x4000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_SHFT                                  0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_BMSK                                     0x2000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_SHFT                                        0xd
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_BMSK                                   0x1000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_SHFT                                      0xc
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_BMSK                          0x800
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_SHFT                            0xb
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK                  0x400
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT                    0xa
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_BMSK                                   0x200
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_SHFT                                     0x9
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_BMSK                                   0x100
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_SHFT                                     0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_BMSK                                       0x80
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_SHFT                                        0x7
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_BMSK                             0x40
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_SHFT                              0x6
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_CAM_IPE_1_DISABLE_IF_BMSK                             0x20
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_CAM_IPE_1_DISABLE_IF_SHFT                              0x5
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_BMSK                                    0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_SHFT                                     0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_BMSK                                      0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_SHFT                                      0x3
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_BMSK                            0x7
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_SHFT                            0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041a4)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PHYS                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041a4)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ADDR, HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_RMSK)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_BMSK                          0x80000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_SHFT                                0x1f
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_BMSK                          0x40000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_SHFT                                0x1e
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_BMSK                                0x20000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_SHFT                                      0x1d
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_LLCC_FUSE_CACHE_SIZE_ZERO_BMSK                  0x10000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_LLCC_FUSE_CACHE_SIZE_ZERO_SHFT                        0x1c
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_UFS_SINGLE_LANE_BMSK                             0x8000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_UFS_SINGLE_LANE_SHFT                                  0x1b
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_BMSK                                 0x4000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_SHFT                                      0x1a
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK              0x2000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT                   0x19
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_BMSK                  0x1000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_SHFT                       0x18
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_BMSK                  0x800000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_SHFT                      0x17
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_BMSK                            0x400000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_SHFT                                0x16
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_BMSK                       0x200000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_SHFT                           0x15
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_BMSK                                    0x100000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_SHFT                                        0x14
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_BMSK                                0x80000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_SHFT                                   0x13
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_BMSK                             0x7c000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_SHFT                                 0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_BMSK                          0x2000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_SHFT                             0xd
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_BMSK                             0x1000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_SHFT                                0xc
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_BMSK                                      0x800
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_SHFT                                        0xb
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_NIDNT_DISABLE_BMSK                                   0x400
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_NIDNT_DISABLE_SHFT                                     0xa
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_BMSK                                    0x200
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_SHFT                                      0x9
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_BMSK                                     0x1e0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_SHFT                                       0x5
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_BMSK                           0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_SHFT                            0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_VFE_RESOLUTION_LIMIT_BMSK                              0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_VFE_RESOLUTION_LIMIT_SHFT                              0x3
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_BMSK                                    0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_SHFT                                    0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_BMSK                                    0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_SHFT                                    0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_BMSK                                    0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_SHFT                                    0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041a8)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_PHYS                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041a8)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_ADDR, HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_RMSK)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_BMSK                 0xffffc000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_SHFT                        0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_BMSK                       0x3c00
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_SHFT                          0xa
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_BMSK                     0x3ff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_SHFT                       0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041ac)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_PHYS                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041ac)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_ADDR, HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_RMSK)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_BMSK                        0xc0000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_SHFT                              0x1e
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_RSVD0_BMSK                                      0x3c000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_RSVD0_SHFT                                            0x1a
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_BMSK                      0x2000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_SHFT                           0x19
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_BMSK                                 0x1000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_SHFT                                      0x18
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_BMSK                   0xffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_SHFT                        0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041b0)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PHYS                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041b0)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_ADDR, HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_RMSK)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_TURING_Q6SS_PLL_L_MAX_9_0_BMSK                  0xffc00000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_TURING_Q6SS_PLL_L_MAX_9_0_SHFT                        0x16
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_RSVD0_BMSK                                        0x300000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_RSVD0_SHFT                                            0x14
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_BMSK                         0x80000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_SHFT                            0x13
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_BMSK                         0x40000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_SHFT                            0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_BMSK                    0x20000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_SHFT                       0x11
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_BMSK                    0x10000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_SHFT                       0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_BMSK                     0x8000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_SHFT                        0xf
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_BMSK                     0x4000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_SHFT                        0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_BMSK                    0x2000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_SHFT                       0xd
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_BMSK                    0x1000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_SHFT                       0xc
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                  0x800
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                    0xb
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK                   0x400
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT                     0xa
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_BMSK                        0x200
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_SHFT                          0x9
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_BMSK                        0x100
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_SHFT                          0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_BMSK                         0x80
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_SHFT                          0x7
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_BMSK                         0x40
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_SHFT                          0x6
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_BMSK                        0x20
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_SHFT                         0x5
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_BMSK                        0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_SHFT                         0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK                      0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT                      0x3
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK                       0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT                       0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_BMSK                                   0x2
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_SHFT                                   0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_BMSK                                       0x1
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_SHFT                                       0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041b4)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_PHYS                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041b4)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_ADDR, HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_RMSK)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_BMSK                       0xff000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_SHFT                             0x18
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_RSVD1_BMSK                                        0x800000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_RSVD1_SHFT                                            0x17
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_BMSK                          0x400000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_SHFT                              0x16
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_BMSK                     0x200000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_SHFT                         0x15
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_BMSK                           0x1f8000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_SHFT                                0xf
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_BMSK                         0x4000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_SHFT                            0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_BMSK                        0x3fc0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_SHFT                           0x6
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_TURING_Q6SS_PLL_L_MAX_15_10_BMSK                      0x3f
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW2_MSB_TURING_Q6SS_PLL_L_MAX_15_10_SHFT                       0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041b8)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_PHYS                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041b8)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ADDR, HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_RMSK)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_TAP_GEN_SPARE_INSTR_DISABLE_13_0_BMSK           0xfffc0000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_TAP_GEN_SPARE_INSTR_DISABLE_13_0_SHFT                 0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_TAP_INSTR_DISABLE_BMSK                             0x3ffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_LSB_TAP_INSTR_DISABLE_SHFT                                 0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041bc)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_PHYS                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041bc)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_ADDR, HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_RMSK)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_SEC_TAP_ACCESS_DISABLE_BMSK                     0xfffc0000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_SEC_TAP_ACCESS_DISABLE_SHFT                           0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_TAP_GEN_SPARE_INSTR_DISABLE_31_14_BMSK             0x3ffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW3_MSB_TAP_GEN_SPARE_INSTR_DISABLE_31_14_SHFT                 0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041c0)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_PHYS                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041c0)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_ADDR, HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_RMSK)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_MODEM_PBL_PATCH_VERSION_BMSK                    0xfe000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_MODEM_PBL_PATCH_VERSION_SHFT                          0x19
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_APPS_PBL_PATCH_VERSION_BMSK                      0x1fc0000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_APPS_PBL_PATCH_VERSION_SHFT                           0x12
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_APPS_PBL_BOOT_SPEED_BMSK                           0x30000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_APPS_PBL_BOOT_SPEED_SHFT                              0x10
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_MODEM_PBL_BOOT_BMSK                                 0x8000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_MODEM_PBL_BOOT_SHFT                                    0xf
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_RSVD1_BMSK                                          0x4000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_RSVD1_SHFT                                             0xe
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_APPS_BOOT_FROM_ROM_BMSK                             0x2000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_APPS_BOOT_FROM_ROM_SHFT                                0xd
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_RSVD0_BMSK                                          0x1e00
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_RSVD0_SHFT                                             0x9
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_ARM_CE_DISABLE_USAGE_BMSK                            0x100
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_ARM_CE_DISABLE_USAGE_SHFT                              0x8
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_BOOT_ROM_CFG_BMSK                                     0xff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_LSB_BOOT_ROM_CFG_SHFT                                      0x0

#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041c4)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_PHYS                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041c4)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_RMSK                                            0xffffffff
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_ADDR, HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_RMSK)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_APPS_BOOT_TRIGGER_DISABLE_BMSK                  0x80000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_APPS_BOOT_TRIGGER_DISABLE_SHFT                        0x1f
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_PBL_QSEE_BOOT_FLOW_DISABLE_BMSK                 0x40000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_PBL_QSEE_BOOT_FLOW_DISABLE_SHFT                       0x1e
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_XBL_SEC_AUTH_DISABLE_BMSK                       0x20000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_XBL_SEC_AUTH_DISABLE_SHFT                             0x1d
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_MSM_PKG_TYPE_BMSK                               0x10000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_MSM_PKG_TYPE_SHFT                                     0x1c
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_LOAD_SPU_TEST_IMAGE_BMSK                         0x8000000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_LOAD_SPU_TEST_IMAGE_SHFT                              0x1b
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_RSVD3_BMSK                                       0x7f80000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_RSVD3_SHFT                                            0x13
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_FOUNDRY_ID_BMSK                                    0x78000
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_FOUNDRY_ID_SHFT                                        0xf
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_PLL_CFG_BMSK                                        0x7ff0
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_PLL_CFG_SHFT                                           0x4
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_APPS_PBL_PLL_CTRL_BMSK                                 0xf
#define HWIO_QFPROM_CORR_FEAT_CONFIG_ROW4_MSB_APPS_PBL_PLL_CTRL_SHFT                                 0x0

#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_ADDR(n)                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041c8 + 0x8 * (n))
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_PHYS(n)                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041c8 + 0x8 * (n))
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_MAXn                                                        3
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_HASH_DATA0_BMSK                                    0xffffffff
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_LSB_HASH_DATA0_SHFT                                           0x0

#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_ADDR(n)                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041cc + 0x8 * (n))
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_PHYS(n)                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041cc + 0x8 * (n))
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_MAXn                                                        3
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_HASH_DATA1_BMSK                                    0xffffffff
#define HWIO_QFPROM_CORR_PK_HASH0_ROWn_MSB_HASH_DATA1_SHFT                                           0x0

#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041f8)
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041f8)
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW0_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW0_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_LMH_CS_FUSES_SLOPE_16_0_BMSK                          0xffff8000
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_LMH_CS_FUSES_SLOPE_16_0_SHFT                                 0xf
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_LPASS_Q6SS1_LDO_VREF_TRIM_BMSK                            0x7f80
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_LPASS_Q6SS1_LDO_VREF_TRIM_SHFT                               0x7
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_LPASS_Q6SS1_LDO_ENABLE_BMSK                                 0x40
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_LPASS_Q6SS1_LDO_ENABLE_SHFT                                  0x6
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_MSS_Q6SS0_LDO_VREF_TRIM_BMSK                                0x3e
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_MSS_Q6SS0_LDO_VREF_TRIM_SHFT                                 0x1
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_MSS_Q6SS0_LDO_ENABLE_BMSK                                    0x1
#define HWIO_QFPROM_CORR_CALIB_ROW0_LSB_MSS_Q6SS0_LDO_ENABLE_SHFT                                    0x0

#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x000041fc)
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041fc)
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW0_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW0_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_LMH_CS_FUSES_INTERCEPT_8_0_BMSK                       0xff800000
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_LMH_CS_FUSES_INTERCEPT_8_0_SHFT                             0x17
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_LMH_CS_FUSES_SLOPE_39_17_BMSK                           0x7fffff
#define HWIO_QFPROM_CORR_CALIB_ROW0_MSB_LMH_CS_FUSES_SLOPE_39_17_SHFT                                0x0

#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004200)
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004200)
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW1_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW1_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_LMH_FUSES_AMP_COMP_0_BMSK                             0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_LMH_FUSES_AMP_COMP_0_SHFT                                   0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_LMH_CS_FUSES_INTERCEPT_39_9_BMSK                      0x7fffffff
#define HWIO_QFPROM_CORR_CALIB_ROW1_LSB_LMH_CS_FUSES_INTERCEPT_39_9_SHFT                             0x0

#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004204)
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004204)
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW1_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW1_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_LPASS_Q6SS1_HVX_LDO_ENABLE_BMSK                       0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_LPASS_Q6SS1_HVX_LDO_ENABLE_SHFT                             0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_REFGEN_WEST_BGV_TRIM_BMSK                             0x7f800000
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_REFGEN_WEST_BGV_TRIM_SHFT                                   0x17
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_REFGEN_EAST_BGV_TRIM_BMSK                               0x7f8000
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_REFGEN_EAST_BGV_TRIM_SHFT                                    0xf
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_BANDGAP_TRIM_BMSK                                         0x7f00
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_BANDGAP_TRIM_SHFT                                            0x8
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_SYS_APC1LDOVREFTRIM_BMSK                                    0xf8
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_SYS_APC1LDOVREFTRIM_SHFT                                     0x3
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_LMH_FUSES_AMP_COMP_3_1_BMSK                                  0x7
#define HWIO_QFPROM_CORR_CALIB_ROW1_MSB_LMH_FUSES_AMP_COMP_3_1_SHFT                                  0x0

#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004208)
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004208)
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW2_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW2_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_GPU_LMH_CS_FUSES_INTERCEPT_HM_1_0_BMSK                0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_GPU_LMH_CS_FUSES_INTERCEPT_HM_1_0_SHFT                      0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_GPU_LMH_CS_FUSES_SLOPE_SPTP_BMSK                      0x3ff00000
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_GPU_LMH_CS_FUSES_SLOPE_SPTP_SHFT                            0x14
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_GPU_LMH_CS_FUSES_SLOPE_RAC_BMSK                          0xffc00
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_GPU_LMH_CS_FUSES_SLOPE_RAC_SHFT                              0xa
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_GPU_LMH_CS_FUSES_SLOPE_HM_BMSK                             0x3ff
#define HWIO_QFPROM_CORR_CALIB_ROW2_LSB_GPU_LMH_CS_FUSES_SLOPE_HM_SHFT                               0x0

#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000420c)
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000420c)
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW2_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW2_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_GPU_LMH_FUSES_AMP_COMP_BMSK                           0xf0000000
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_GPU_LMH_FUSES_AMP_COMP_SHFT                                 0x1c
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_GPU_LMH_CS_FUSES_INTERCEPT_SPTP_BMSK                   0xffc0000
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_GPU_LMH_CS_FUSES_INTERCEPT_SPTP_SHFT                        0x12
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_GPU_LMH_CS_FUSES_INTERCEPT_RAC_BMSK                      0x3ff00
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_GPU_LMH_CS_FUSES_INTERCEPT_RAC_SHFT                          0x8
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_GPU_LMH_CS_FUSES_INTERCEPT_HM_9_2_BMSK                      0xff
#define HWIO_QFPROM_CORR_CALIB_ROW2_MSB_GPU_LMH_CS_FUSES_INTERCEPT_HM_9_2_SHFT                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004210)
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004210)
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW3_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW3_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW3_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_CPR_FUSES_31_0_BMSK                                   0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW3_LSB_CPR_FUSES_31_0_SHFT                                          0x0

#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004214)
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004214)
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW3_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW3_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW3_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_CPR_FUSES_63_32_BMSK                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW3_MSB_CPR_FUSES_63_32_SHFT                                         0x0

#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004218)
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004218)
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW4_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW4_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR_FUSES_95_64_BMSK                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW4_LSB_CPR_FUSES_95_64_SHFT                                         0x0

#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000421c)
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000421c)
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW4_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW4_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR_FUSES_127_96_BMSK                                 0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW4_MSB_CPR_FUSES_127_96_SHFT                                        0x0

#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004220)
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004220)
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW5_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW5_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW5_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR_FUSES_159_128_BMSK                                0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW5_LSB_CPR_FUSES_159_128_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004224)
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004224)
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW5_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW5_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW5_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_CPR_FUSES_191_160_BMSK                                0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW5_MSB_CPR_FUSES_191_160_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004228)
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004228)
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW6_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW6_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW6_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR_FUSES_223_192_BMSK                                0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW6_LSB_CPR_FUSES_223_192_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000422c)
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000422c)
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW6_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW6_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW6_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR_FUSES_255_224_BMSK                                0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW6_MSB_CPR_FUSES_255_224_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004230)
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004230)
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW7_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW7_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW7_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_CPR_FUSES_287_256_BMSK                                0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW7_LSB_CPR_FUSES_287_256_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004234)
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004234)
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW7_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW7_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW7_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_CPR_FUSES_319_288_BMSK                                0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW7_MSB_CPR_FUSES_319_288_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004238)
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004238)
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW8_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW8_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW8_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_CPR_FUSES_351_320_BMSK                                0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW8_LSB_CPR_FUSES_351_320_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000423c)
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000423c)
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW8_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW8_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW8_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_CPR_FUSES_383_352_BMSK                                0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW8_MSB_CPR_FUSES_383_352_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004240)
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004240)
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW9_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW9_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW9_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_CPR_FUSES_415_384_BMSK                                0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW9_LSB_CPR_FUSES_415_384_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_ADDR                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004244)
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_PHYS                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004244)
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_RMSK                                                  0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW9_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW9_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW9_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR_FUSES_447_416_BMSK                                0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW9_MSB_CPR_FUSES_447_416_SHFT                                       0x0

#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004248)
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004248)
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW10_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW10_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW10_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_CPR_FUSES_479_448_BMSK                               0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW10_LSB_CPR_FUSES_479_448_SHFT                                      0x0

#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000424c)
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000424c)
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW10_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW10_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW10_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_SPARE0_BMSK                                          0xe0000000
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_SPARE0_SHFT                                                0x1d
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_SW_CAL_REDUN_SEL_BMSK                                0x1c000000
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_SW_CAL_REDUN_SEL_SHFT                                      0x1a
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_CPR_FUSES_505_480_BMSK                                0x3ffffff
#define HWIO_QFPROM_CORR_CALIB_ROW10_MSB_CPR_FUSES_505_480_SHFT                                      0x0

#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004250)
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004250)
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW11_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW11_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW11_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_SPARE0_BMSK                                          0xc0000000
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_SPARE0_SHFT                                                0x1e
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_QUSB_REFCLK_SEL_BMSK                                 0x20000000
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_QUSB_REFCLK_SEL_SHFT                                       0x1d
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_QUSB_PORT0_HSTX_TRIM_LSB_BMSK                        0x1e000000
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_QUSB_PORT0_HSTX_TRIM_LSB_SHFT                              0x19
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_SRAM_AGING_SENSOR_1_BMSK                              0x1fe0000
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_SRAM_AGING_SENSOR_1_SHFT                                   0x11
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_SRAM_AGING_SENSOR_0_BMSK                                0x1fe00
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_SRAM_AGING_SENSOR_0_SHFT                                    0x9
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_GNSS_ADC_RSB_BMSK                                         0x1c0
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_GNSS_ADC_RSB_SHFT                                           0x6
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_GNSS_ADC_LDO_BMSK                                          0x38
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_GNSS_ADC_LDO_SHFT                                           0x3
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_GNSS_ADC_VREF_BMSK                                          0x7
#define HWIO_QFPROM_CORR_CALIB_ROW11_LSB_GNSS_ADC_VREF_SHFT                                          0x0

#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004254)
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004254)
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW11_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW11_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW11_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_TSENS1_BASE0_8_0_BMSK                                0xff800000
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_TSENS1_BASE0_8_0_SHFT                                      0x17
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_TSENS0_BASE1_BMSK                                      0x7fe000
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_TSENS0_BASE1_SHFT                                           0xd
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_TSENS0_BASE0_BMSK                                        0x1ff8
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_TSENS0_BASE0_SHFT                                           0x3
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_TSENS_CAL_SEL_BMSK                                          0x7
#define HWIO_QFPROM_CORR_CALIB_ROW11_MSB_TSENS_CAL_SEL_SHFT                                          0x0

#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004258)
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004258)
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW12_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW12_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW12_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_TSENS5_OFFSET_0_BMSK                                 0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_TSENS5_OFFSET_0_SHFT                                       0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_TSENS4_OFFSET_BMSK                                   0x78000000
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_TSENS4_OFFSET_SHFT                                         0x1b
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_TSENS3_OFFSET_BMSK                                    0x7800000
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_TSENS3_OFFSET_SHFT                                         0x17
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_TSENS2_OFFSET_BMSK                                     0x780000
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_TSENS2_OFFSET_SHFT                                         0x13
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_TSENS1_OFFSET_BMSK                                      0x78000
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_TSENS1_OFFSET_SHFT                                          0xf
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_TSENS0_OFFSET_BMSK                                       0x7800
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_TSENS0_OFFSET_SHFT                                          0xb
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_TSENS1_BASE1_BMSK                                         0x7fe
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_TSENS1_BASE1_SHFT                                           0x1
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_TSENS1_BASE0_9_BMSK                                         0x1
#define HWIO_QFPROM_CORR_CALIB_ROW12_LSB_TSENS1_BASE0_9_SHFT                                         0x0

#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000425c)
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000425c)
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW12_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW12_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW12_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS13_OFFSET_0_BMSK                                0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS13_OFFSET_0_SHFT                                      0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS12_OFFSET_BMSK                                  0x78000000
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS12_OFFSET_SHFT                                        0x1b
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS11_OFFSET_BMSK                                   0x7800000
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS11_OFFSET_SHFT                                        0x17
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS10_OFFSET_BMSK                                    0x780000
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS10_OFFSET_SHFT                                        0x13
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS9_OFFSET_BMSK                                      0x78000
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS9_OFFSET_SHFT                                          0xf
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS8_OFFSET_BMSK                                       0x7800
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS8_OFFSET_SHFT                                          0xb
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS7_OFFSET_BMSK                                        0x780
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS7_OFFSET_SHFT                                          0x7
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS6_OFFSET_BMSK                                         0x78
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS6_OFFSET_SHFT                                          0x3
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS5_OFFSET_3_1_BMSK                                      0x7
#define HWIO_QFPROM_CORR_CALIB_ROW12_MSB_TSENS5_OFFSET_3_1_SHFT                                      0x0

#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004260)
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004260)
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW13_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW13_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW13_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS21_OFFSET_0_BMSK                                0x80000000
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS21_OFFSET_0_SHFT                                      0x1f
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS20_OFFSET_BMSK                                  0x78000000
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS20_OFFSET_SHFT                                        0x1b
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS19_OFFSET_BMSK                                   0x7800000
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS19_OFFSET_SHFT                                        0x17
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS18_OFFSET_BMSK                                    0x780000
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS18_OFFSET_SHFT                                        0x13
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS17_OFFSET_BMSK                                     0x78000
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS17_OFFSET_SHFT                                         0xf
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS16_OFFSET_BMSK                                      0x7800
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS16_OFFSET_SHFT                                         0xb
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS15_OFFSET_BMSK                                       0x780
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS15_OFFSET_SHFT                                         0x7
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS14_OFFSET_BMSK                                        0x78
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS14_OFFSET_SHFT                                         0x3
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS13_OFFSET_3_1_BMSK                                     0x7
#define HWIO_QFPROM_CORR_CALIB_ROW13_LSB_TSENS13_OFFSET_3_1_SHFT                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004264)
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004264)
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW13_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW13_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW13_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_SW_CAL_REDUN_20_0_BMSK                               0xfffff800
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_SW_CAL_REDUN_20_0_SHFT                                      0xb
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_TSENS23_OFFSET_BMSK                                       0x780
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_TSENS23_OFFSET_SHFT                                         0x7
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_TSENS22_OFFSET_BMSK                                        0x78
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_TSENS22_OFFSET_SHFT                                         0x3
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_TSENS21_OFFSET_3_1_BMSK                                     0x7
#define HWIO_QFPROM_CORR_CALIB_ROW13_MSB_TSENS21_OFFSET_3_1_SHFT                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004268)
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004268)
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW14_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW14_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW14_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_SW_CAL_REDUN_52_21_BMSK                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW14_LSB_SW_CAL_REDUN_52_21_SHFT                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000426c)
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000426c)
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW14_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW14_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW14_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_SW_CAL_REDUN_84_53_BMSK                              0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW14_MSB_SW_CAL_REDUN_84_53_SHFT                                     0x0

#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004270)
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004270)
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW15_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW15_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW15_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_SW_CAL_REDUN_116_85_BMSK                             0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW15_LSB_SW_CAL_REDUN_116_85_SHFT                                    0x0

#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004274)
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004274)
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW15_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW15_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW15_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_SW_CAL_REDUN_148_117_BMSK                            0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW15_MSB_SW_CAL_REDUN_148_117_SHFT                                   0x0

#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004278)
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004278)
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW16_LSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW16_LSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW16_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_SW_CAL_REDUN_180_149_BMSK                            0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW16_LSB_SW_CAL_REDUN_180_149_SHFT                                   0x0

#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_ADDR                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000427c)
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_PHYS                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000427c)
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_RMSK                                                 0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW16_MSB_ADDR, HWIO_QFPROM_CORR_CALIB_ROW16_MSB_RMSK)
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CALIB_ROW16_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SW_CAL_REDUN_212_181_BMSK                            0xffffffff
#define HWIO_QFPROM_CORR_CALIB_ROW16_MSB_SW_CAL_REDUN_212_181_SHFT                                   0x0

#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_ADDR(n)                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004280 + 0x8 * (n))
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_PHYS(n)                                          (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004280 + 0x8 * (n))
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_MAXn                                                     34
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_REDUN_DATA_BMSK                                  0xffffffff
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_LSB_REDUN_DATA_SHFT                                         0x0

#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_ADDR(n)                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004284 + 0x8 * (n))
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_PHYS(n)                                          (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004284 + 0x8 * (n))
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_RMSK                                             0xffffffff
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_MAXn                                                     34
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_REDUN_DATA_BMSK                                  0xffffffff
#define HWIO_QFPROM_CORR_MEM_CONFIG_ROWn_MSB_REDUN_DATA_SHFT                                         0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_ADDR                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004408)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_PHYS                                         (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004408)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_RMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_ADDR, HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_RMSK)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_PCIE_PHY_DISABLE_UPPER_LANE_BMSK             0x80000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_PCIE_PHY_DISABLE_UPPER_LANE_SHFT                   0x1f
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_BMSK                 0x40000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_TURING_Q6SS_HVX_DISABLE_SHFT                       0x1e
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_BMSK                           0x20000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_QC_SP_DISABLE_SHFT                                 0x1d
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_BMSK                    0x1fe00000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_GFX3D_FREQ_LIMIT_VAL_SHFT                          0x15
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_BMSK                     0x180000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDSS_RESOLUTION_LIMIT_SHFT                         0x13
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_BMSK                   0x40000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_ENCODE_DISABLE_SHFT                      0x12
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_BMSK                   0x20000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_HEVC_DECODE_DISABLE_SHFT                      0x11
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_BMSK                            0x10000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_4K_DISABLE_SHFT                               0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_BMSK                            0x8000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_CVP_DISABLE_SHFT                               0xf
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_BMSK                            0x4000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_IRIS_DISABLE_VPX_SHFT                               0xe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_BMSK                                  0x2000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DP_DISABLE_SHFT                                     0xd
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_BMSK                                0x1000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_HDCP_DISABLE_SHFT                                   0xc
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_BMSK                       0x800
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_MDP_APICAL_LTC_DISABLE_SHFT                         0xb
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK               0x400
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT                 0xa
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_BMSK                                0x200
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DSI_1_DISABLE_SHFT                                  0x9
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_BMSK                                0x100
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_DSI_0_DISABLE_SHFT                                  0x8
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_BMSK                                    0x80
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_FD_DISABLE_SHFT                                     0x7
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_BMSK                          0x40
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_CSID_DPCM_14_DISABLE_SHFT                           0x6
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_CAM_IPE_1_DISABLE_IF_BMSK                          0x20
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_CAM_IPE_1_DISABLE_IF_SHFT                           0x5
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_BMSK                                 0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EUD_PORT1_SEL_SHFT                                  0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_BMSK                                   0x8
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_EUD_IGNR_CSR_SHFT                                   0x3
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_BMSK                         0x7
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_SHFT                         0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ADDR                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000440c)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PHYS                                         (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000440c)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_RMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ADDR, HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_RMSK)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_BMSK                       0x80000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY1_SHFT                             0x1f
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_BMSK                       0x40000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_FORCE_HW_KEY0_SHFT                             0x1e
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_BMSK                             0x20000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_ICE_DISABLE_SHFT                                   0x1d
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_LLCC_FUSE_CACHE_SIZE_ZERO_BMSK               0x10000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_LLCC_FUSE_CACHE_SIZE_ZERO_SHFT                     0x1c
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_UFS_SINGLE_LANE_BMSK                          0x8000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_UFS_SINGLE_LANE_SHFT                               0x1b
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_BMSK                              0x4000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_DISABLE_SHFT                                   0x1a
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK           0x2000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT                0x19
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_BMSK               0x1000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SSC_SW_ISLAND_MODE_DISABLE_SHFT                    0x18
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_BMSK               0x800000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_TCSR_SW_OVERRIDE_SOC_HW_VER_SHFT                   0x17
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_BMSK                         0x400000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_APS_RESET_DISABLE_SHFT                             0x16
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_BMSK                    0x200000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_IRIS_MULTIPIPE_DISABLE_SHFT                        0x15
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_BMSK                                 0x100000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_DOLBY_BIT_SHFT                                     0x14
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_BMSK                             0x80000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_QC_UDK_DISABLE_SHFT                                0x13
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_BMSK                          0x7c000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_STACKED_MEMORY_ID_SHFT                              0xe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_BMSK                       0x2000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PRNG_TESTMODE_DISABLE_SHFT                          0xd
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_BMSK                          0x1000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_MDSS_Q_CONFIG_FUSE_SHFT                             0xc
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_BMSK                                   0x800
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_MOCHA_PART_SHFT                                     0xb
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_NIDNT_DISABLE_BMSK                                0x400
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_NIDNT_DISABLE_SHFT                                  0xa
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_BMSK                                 0x200
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_SMMU_DISABLE_SHFT                                   0x9
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_BMSK                                  0x1e0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_VENDOR_LOCK_SHFT                                    0x5
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_BMSK                        0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_CM_FEAT_CONFIG_DISABLE_SHFT                         0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_VFE_RESOLUTION_LIMIT_BMSK                           0x8
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_VFE_RESOLUTION_LIMIT_SHFT                           0x3
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_BMSK                                 0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_2_DISABLE_SHFT                                 0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_BMSK                                 0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_1_DISABLE_SHFT                                 0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_BMSK                                 0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW0_MSB_PCIE_0_DISABLE_SHFT                                 0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_ADDR                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004410)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_PHYS                                         (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004410)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_RMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_ADDR, HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_RMSK)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_BMSK              0xffffc000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_HARD_SHFT                     0xe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_BMSK                    0x3c00
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_IU_SHFT                       0xa
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_BMSK                  0x3ff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SPARE_SHFT                    0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_ADDR                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004414)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_PHYS                                         (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004414)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_RMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_ADDR, HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_RMSK)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_BMSK                     0xc0000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_APSS_PDXWRPNTRDELAY_SHFT                           0x1e
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_RSVD0_BMSK                                   0x3c000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_RSVD0_SHFT                                         0x1a
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_BMSK                   0x2000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_MODEM_TCM_BOOT_DISABLE_SHFT                        0x19
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_BMSK                              0x1000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_NAV_DISABLE_SHFT                                   0x18
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_BMSK                0xffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_SHFT                     0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_ADDR                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004418)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PHYS                                         (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004418)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_RMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_ADDR, HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_RMSK)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_TURING_Q6SS_PLL_L_MAX_9_0_BMSK               0xffc00000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_TURING_Q6SS_PLL_L_MAX_9_0_SHFT                     0x16
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_RSVD0_BMSK                                     0x300000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_RSVD0_SHFT                                         0x14
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_BMSK                      0x80000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_NIDEN_DISABLE_SHFT                         0x13
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_BMSK                      0x40000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_APPS_DBGEN_DISABLE_SHFT                         0x12
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_BMSK                 0x20000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_NIDEN_DISABLE_SHFT                    0x11
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_BMSK                 0x10000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_NS_DBGEN_DISABLE_SHFT                    0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_BMSK                  0x8000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_NIDEN_DISABLE_SHFT                     0xf
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_BMSK                  0x4000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_CP_DBGEN_DISABLE_SHFT                     0xe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_BMSK                 0x2000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_NIDEN_DISABLE_SHFT                    0xd
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_BMSK                 0x1000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_MSS_DBGEN_DISABLE_SHFT                    0xc
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK               0x800
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                 0xb
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK                0x400
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT                  0xa
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_BMSK                     0x200
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_NIDEN_DISABLE_SHFT                       0x9
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_BMSK                     0x100
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_NS_DBGEN_DISABLE_SHFT                       0x8
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_BMSK                      0x80
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_NIDEN_DISABLE_SHFT                       0x7
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_BMSK                      0x40
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_CP_DBGEN_DISABLE_SHFT                       0x6
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_BMSK                     0x20
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_NIDEN_DISABLE_SHFT                      0x5
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_BMSK                     0x10
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_MSS_DBGEN_DISABLE_SHFT                      0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK                   0x8
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT                   0x3
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK                    0x4
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT                    0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_BMSK                                0x2
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_SM_BIST_DISABLE_SHFT                                0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_BMSK                                    0x1
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_LSB_TIC_DISABLE_SHFT                                    0x0

#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_ADDR                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000441c)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_PHYS                                         (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000441c)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_RMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_ADDR, HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_RMSK)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_BMSK                    0xff000000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_APC1PLL_LVAL_SHFT                          0x18
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_RSVD1_BMSK                                     0x800000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_RSVD1_SHFT                                         0x17
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_BMSK                       0x400000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_CFG_L3_SIZE_RED_SHFT                           0x16
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_BMSK                  0x200000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_AUTO_CCI_RCG_CFG_DISABLE_SHFT                      0x15
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_BMSK                        0x1f8000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_SHFT                             0xf
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_BMSK                      0x4000
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_SHFT                         0xe
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_BMSK                     0x3fc0
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_SHFT                        0x6
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_TURING_Q6SS_PLL_L_MAX_15_10_BMSK                   0x3f
#define HWIO_QFPROM_CORR_CM_FEAT_CONFIG_ROW2_MSB_TURING_Q6SS_PLL_L_MAX_15_10_SHFT                    0x0

#define HWIO_QFPROM_CORR_QC_SPARE_REGn_LSB_ADDR(n)                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000043a0 + 0x8 * (n))
#define HWIO_QFPROM_CORR_QC_SPARE_REGn_LSB_PHYS(n)                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043a0 + 0x8 * (n))
#define HWIO_QFPROM_CORR_QC_SPARE_REGn_LSB_RMSK                                               0xffffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REGn_LSB_MAXn                                                       18
#define HWIO_QFPROM_CORR_QC_SPARE_REGn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_QC_SPARE_REGn_LSB_ADDR(n), HWIO_QFPROM_CORR_QC_SPARE_REGn_LSB_RMSK)
#define HWIO_QFPROM_CORR_QC_SPARE_REGn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_QC_SPARE_REGn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_QC_SPARE_REGn_LSB_QC_SPARE_BMSK                                      0xffffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REGn_LSB_QC_SPARE_SHFT                                             0x0

#define HWIO_QFPROM_CORR_QC_SPARE_REGn_MSB_ADDR(n)                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000043a4 + 0x8 * (n))
#define HWIO_QFPROM_CORR_QC_SPARE_REGn_MSB_PHYS(n)                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043a4 + 0x8 * (n))
#define HWIO_QFPROM_CORR_QC_SPARE_REGn_MSB_RMSK                                                 0xffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REGn_MSB_MAXn                                                       18
#define HWIO_QFPROM_CORR_QC_SPARE_REGn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_QC_SPARE_REGn_MSB_ADDR(n), HWIO_QFPROM_CORR_QC_SPARE_REGn_MSB_RMSK)
#define HWIO_QFPROM_CORR_QC_SPARE_REGn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_QC_SPARE_REGn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_QC_SPARE_REGn_MSB_QC_SPARE_BMSK                                        0xffffff
#define HWIO_QFPROM_CORR_QC_SPARE_REGn_MSB_QC_SPARE_SHFT                                             0x0

#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n)                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004438 + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_PHYS(n)                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004438 + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_RMSK                                     0xffffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_MAXn                                              1
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_KEY_DATA0_BMSK                           0xffffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_LSB_KEY_DATA0_SHFT                                  0x0

#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n)                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000443c + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_PHYS(n)                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000443c + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RMSK                                       0xffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_MAXn                                              1
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_KEY_DATA1_BMSK                             0xffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROWn_MSB_KEY_DATA1_SHFT                                  0x0

#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004448)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_PHYS                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004448)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RMSK                                     0xffffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR, HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RSVD0_BMSK                               0xffff0000
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_RSVD0_SHFT                                     0x10
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_KEY_DATA0_BMSK                               0xffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_LSB_KEY_DATA0_SHFT                                  0x0

#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000444c)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_PHYS                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000444c)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RMSK                                       0xffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR, HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD0_BMSK                                 0xffffff
#define HWIO_QFPROM_CORR_OEM_IMAGE_ENCR_KEY_ROW2_MSB_RSVD0_SHFT                                      0x0

#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004450 + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_PHYS(n)                                        (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004450 + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_RMSK                                           0xffffffff
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_MAXn                                                    1
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT4_BMSK                                 0xff000000
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT4_SHFT                                       0x18
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT3_BMSK                                   0xff0000
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT3_SHFT                                       0x10
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT2_BMSK                                     0xff00
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT2_SHFT                                        0x8
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT1_BMSK                                       0xff
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_LSB_SEC_BOOT1_SHFT                                        0x0

#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_ADDR(n)                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004454 + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_PHYS(n)                                        (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004454 + 0x8 * (n))
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_RMSK                                             0xffffff
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_MAXn                                                    1
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT7_BMSK                                   0xff0000
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT7_SHFT                                       0x10
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT6_BMSK                                     0xff00
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT6_SHFT                                        0x8
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT5_BMSK                                       0xff
#define HWIO_QFPROM_CORR_OEM_SEC_BOOT_ROWn_MSB_SEC_BOOT5_SHFT                                        0x0

#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n)                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004460 + 0x8 * (n))
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_PHYS(n)                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004460 + 0x8 * (n))
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_RMSK                                 0xffffffff
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_MAXn                                          3
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_BMSK                       0xffffffff
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_SHFT                              0x0

#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n)                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004464 + 0x8 * (n))
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_PHYS(n)                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004464 + 0x8 * (n))
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RMSK                                   0xffffff
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_MAXn                                          3
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_BMSK                         0xffffff
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_SHFT                              0x0

#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_LSB_ADDR                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004480)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_LSB_PHYS                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004480)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_LSB_RMSK                                 0xffffffff
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_LSB_ADDR, HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_LSB_RMSK)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_LSB_KEY_DATA0_BMSK                       0xffffffff
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_LSB_KEY_DATA0_SHFT                              0x0

#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_MSB_ADDR                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004484)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_MSB_PHYS                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004484)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_MSB_RMSK                                   0xffffff
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_MSB_ADDR, HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_MSB_RMSK)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_BMSK                             0xffffff
#define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_SHFT                                  0x0

#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n)                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004488 + 0x8 * (n))
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_PHYS(n)                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004488 + 0x8 * (n))
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_RMSK                                 0xffffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_MAXn                                          3
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_BMSK                       0xffffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_LSB_KEY_DATA0_SHFT                              0x0

#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n)                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000448c + 0x8 * (n))
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_PHYS(n)                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000448c + 0x8 * (n))
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RMSK                                   0xffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_MAXn                                          3
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_BMSK                         0xffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROWn_MSB_KEY_DATA1_SHFT                              0x0

#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x000044a8)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_PHYS                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044a8)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_RMSK                                 0xffffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR, HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_RMSK)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_KEY_DATA0_BMSK                       0xffffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_KEY_DATA0_SHFT                              0x0

#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x000044ac)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_PHYS                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044ac)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RMSK                                   0xffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR, HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RMSK)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_BMSK                             0xffffff
#define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_SHFT                                  0x0

#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_ADDR(n)                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x000044b0 + 0x8 * (n))
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_PHYS(n)                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044b0 + 0x8 * (n))
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_RMSK                                              0xffffffff
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_MAXn                                                      55
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_PATCH_DATA_BMSK                                   0xffffffff
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_LSB_PATCH_DATA_SHFT                                          0x0

#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_ADDR(n)                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x000044b4 + 0x8 * (n))
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_PHYS(n)                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044b4 + 0x8 * (n))
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_RMSK                                                0xffffff
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_MAXn                                                      55
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_RSVD0_BMSK                                          0xfe0000
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_RSVD0_SHFT                                              0x11
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_PATCH_ADDR_BMSK                                      0x1fffe
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_PATCH_ADDR_SHFT                                          0x1
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_PATCH_EN_BMSK                                            0x1
#define HWIO_QFPROM_CORR_ROM_PATCH_ROWn_MSB_PATCH_EN_SHFT                                            0x0

#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n)                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004670 + 0x8 * (n))
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_PHYS(n)                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004670 + 0x8 * (n))
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_RMSK                                        0xffffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_MAXn                                                 1
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_KEY_DATA0_BMSK                              0xffffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_LSB_KEY_DATA0_SHFT                                     0x0

#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n)                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004674 + 0x8 * (n))
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_PHYS(n)                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004674 + 0x8 * (n))
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_RMSK                                          0xffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_MAXn                                                 1
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_KEY_DATA1_BMSK                                0xffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROWn_MSB_KEY_DATA1_SHFT                                     0x0

#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004680)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_PHYS                                        (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004680)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_RMSK                                        0xffffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR, HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_RMSK)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_RSVD0_BMSK                                  0xffff0000
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_RSVD0_SHFT                                        0x10
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_KEY_DATA0_BMSK                                  0xffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_LSB_KEY_DATA0_SHFT                                     0x0

#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004684)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_PHYS                                        (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004684)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_RMSK                                          0xffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR, HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_RMSK)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD0_BMSK                                    0xffffff
#define HWIO_QFPROM_CORR_IMAGE_ENCR_KEY1_ROW2_MSB_RSVD0_SHFT                                         0x0

#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_ADDR(n)                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004688 + 0x8 * (n))
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_PHYS(n)                                       (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004688 + 0x8 * (n))
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_MAXn                                                   3
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_ADDR(n), HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_RMSK)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_KEY_DATA0_BMSK                                0xffffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_LSB_KEY_DATA0_SHFT                                       0x0

#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_ADDR(n)                                       (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000468c + 0x8 * (n))
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_PHYS(n)                                       (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000468c + 0x8 * (n))
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_RMSK                                            0xffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_MAXn                                                   3
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_ADDR(n), HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_RMSK)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_KEY_DATA1_BMSK                                  0xffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROWn_MSB_KEY_DATA1_SHFT                                       0x0

#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_ADDR                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x000046a8)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_PHYS                                          (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046a8)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_RMSK                                          0xffffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_ADDR, HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_RMSK)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_ADDR, m)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_KEY_DATA0_BMSK                                0xffffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_LSB_KEY_DATA0_SHFT                                       0x0

#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_ADDR                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x000046ac)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_PHYS                                          (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046ac)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_RMSK                                            0xffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_IN          \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_ADDR, HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_RMSK)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_ADDR, m)
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_RSVD0_BMSK                                      0xffffff
#define HWIO_QFPROM_CORR_USER_DATA_KEY_ROW4_MSB_RSVD0_SHFT                                           0x0

#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_ADDR(n)                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004510 + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_PHYS(n)                                      (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004510 + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_RMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_MAXn                                                 30
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_OEM_SPARE_BMSK                               0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_LSB_OEM_SPARE_SHFT                                      0x0

#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_ADDR(n)                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004514 + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_PHYS(n)                                      (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004514 + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_RMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_MAXn                                                 30
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_OEM_SPARE_BMSK                               0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW0_MSB_OEM_SPARE_SHFT                                      0x0

#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_ADDR(n)                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x00004518 + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_PHYS(n)                                      (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004518 + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_RMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_MAXn                                                 30
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_OEM_SPARE_BMSK                               0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_LSB_OEM_SPARE_SHFT                                      0x0

#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_ADDR(n)                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000451c + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_PHYS(n)                                      (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000451c + 0x10 * (n))
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_RMSK                                         0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_MAXn                                                 30
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_INI(n)        \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_ADDR(n), HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_RMSK)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_INMI(n,mask)    \
        in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_ADDR(n), mask)
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_OEM_SPARE_BMSK                               0xffffffff
#define HWIO_QFPROM_CORR_OEM_SPARE_REGn_ROW1_MSB_OEM_SPARE_SHFT                                      0x0

#define HWIO_SEC_CTRL_HW_VERSION_ADDR                                                         (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006000)
#define HWIO_SEC_CTRL_HW_VERSION_PHYS                                                         (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006000)
#define HWIO_SEC_CTRL_HW_VERSION_RMSK                                                         0xffffffff
#define HWIO_SEC_CTRL_HW_VERSION_IN          \
        in_dword_masked(HWIO_SEC_CTRL_HW_VERSION_ADDR, HWIO_SEC_CTRL_HW_VERSION_RMSK)
#define HWIO_SEC_CTRL_HW_VERSION_INM(m)      \
        in_dword_masked(HWIO_SEC_CTRL_HW_VERSION_ADDR, m)
#define HWIO_SEC_CTRL_HW_VERSION_MAJOR_BMSK                                                   0xf0000000
#define HWIO_SEC_CTRL_HW_VERSION_MAJOR_SHFT                                                         0x1c
#define HWIO_SEC_CTRL_HW_VERSION_MINOR_BMSK                                                    0xfff0000
#define HWIO_SEC_CTRL_HW_VERSION_MINOR_SHFT                                                         0x10
#define HWIO_SEC_CTRL_HW_VERSION_STEP_BMSK                                                        0xffff
#define HWIO_SEC_CTRL_HW_VERSION_STEP_SHFT                                                           0x0

#define HWIO_FEATURE_CONFIG0_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006004)
#define HWIO_FEATURE_CONFIG0_PHYS                                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006004)
#define HWIO_FEATURE_CONFIG0_RMSK                                                             0xffffffff
#define HWIO_FEATURE_CONFIG0_IN          \
        in_dword_masked(HWIO_FEATURE_CONFIG0_ADDR, HWIO_FEATURE_CONFIG0_RMSK)
#define HWIO_FEATURE_CONFIG0_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG0_ADDR, m)
#define HWIO_FEATURE_CONFIG0_PCIE_PHY_DISABLE_UPPER_LANE_BMSK                                 0x80000000
#define HWIO_FEATURE_CONFIG0_PCIE_PHY_DISABLE_UPPER_LANE_SHFT                                       0x1f
#define HWIO_FEATURE_CONFIG0_TURING_Q6SS_HVX_DISABLE_BMSK                                     0x40000000
#define HWIO_FEATURE_CONFIG0_TURING_Q6SS_HVX_DISABLE_SHFT                                           0x1e
#define HWIO_FEATURE_CONFIG0_QC_SP_DISABLE_BMSK                                               0x20000000
#define HWIO_FEATURE_CONFIG0_QC_SP_DISABLE_SHFT                                                     0x1d
#define HWIO_FEATURE_CONFIG0_GFX3D_FREQ_LIMIT_VAL_BMSK                                        0x1fe00000
#define HWIO_FEATURE_CONFIG0_GFX3D_FREQ_LIMIT_VAL_SHFT                                              0x15
#define HWIO_FEATURE_CONFIG0_MDSS_RESOLUTION_LIMIT_BMSK                                         0x180000
#define HWIO_FEATURE_CONFIG0_MDSS_RESOLUTION_LIMIT_SHFT                                             0x13
#define HWIO_FEATURE_CONFIG0_IRIS_HEVC_ENCODE_DISABLE_BMSK                                       0x40000
#define HWIO_FEATURE_CONFIG0_IRIS_HEVC_ENCODE_DISABLE_SHFT                                          0x12
#define HWIO_FEATURE_CONFIG0_IRIS_HEVC_DECODE_DISABLE_BMSK                                       0x20000
#define HWIO_FEATURE_CONFIG0_IRIS_HEVC_DECODE_DISABLE_SHFT                                          0x11
#define HWIO_FEATURE_CONFIG0_IRIS_4K_DISABLE_BMSK                                                0x10000
#define HWIO_FEATURE_CONFIG0_IRIS_4K_DISABLE_SHFT                                                   0x10
#define HWIO_FEATURE_CONFIG0_IRIS_CVP_DISABLE_BMSK                                                0x8000
#define HWIO_FEATURE_CONFIG0_IRIS_CVP_DISABLE_SHFT                                                   0xf
#define HWIO_FEATURE_CONFIG0_IRIS_DISABLE_VPX_BMSK                                                0x4000
#define HWIO_FEATURE_CONFIG0_IRIS_DISABLE_VPX_SHFT                                                   0xe
#define HWIO_FEATURE_CONFIG0_DP_DISABLE_BMSK                                                      0x2000
#define HWIO_FEATURE_CONFIG0_DP_DISABLE_SHFT                                                         0xd
#define HWIO_FEATURE_CONFIG0_HDCP_DISABLE_BMSK                                                    0x1000
#define HWIO_FEATURE_CONFIG0_HDCP_DISABLE_SHFT                                                       0xc
#define HWIO_FEATURE_CONFIG0_MDP_APICAL_LTC_DISABLE_BMSK                                           0x800
#define HWIO_FEATURE_CONFIG0_MDP_APICAL_LTC_DISABLE_SHFT                                             0xb
#define HWIO_FEATURE_CONFIG0_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK                                   0x400
#define HWIO_FEATURE_CONFIG0_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT                                     0xa
#define HWIO_FEATURE_CONFIG0_DSI_1_DISABLE_BMSK                                                    0x200
#define HWIO_FEATURE_CONFIG0_DSI_1_DISABLE_SHFT                                                      0x9
#define HWIO_FEATURE_CONFIG0_DSI_0_DISABLE_BMSK                                                    0x100
#define HWIO_FEATURE_CONFIG0_DSI_0_DISABLE_SHFT                                                      0x8
#define HWIO_FEATURE_CONFIG0_FD_DISABLE_BMSK                                                        0x80
#define HWIO_FEATURE_CONFIG0_FD_DISABLE_SHFT                                                         0x7
#define HWIO_FEATURE_CONFIG0_CSID_DPCM_14_DISABLE_BMSK                                              0x40
#define HWIO_FEATURE_CONFIG0_CSID_DPCM_14_DISABLE_SHFT                                               0x6
#define HWIO_FEATURE_CONFIG0_CAM_IPE_1_DISABLE_IF_BMSK                                              0x20
#define HWIO_FEATURE_CONFIG0_CAM_IPE_1_DISABLE_IF_SHFT                                               0x5
#define HWIO_FEATURE_CONFIG0_EUD_PORT1_SEL_BMSK                                                     0x10
#define HWIO_FEATURE_CONFIG0_EUD_PORT1_SEL_SHFT                                                      0x4
#define HWIO_FEATURE_CONFIG0_EUD_IGNR_CSR_BMSK                                                       0x8
#define HWIO_FEATURE_CONFIG0_EUD_IGNR_CSR_SHFT                                                       0x3
#define HWIO_FEATURE_CONFIG0_BOOT_ROM_PATCH_DISABLE_BMSK                                             0x7
#define HWIO_FEATURE_CONFIG0_BOOT_ROM_PATCH_DISABLE_SHFT                                             0x0

#define HWIO_FEATURE_CONFIG1_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006008)
#define HWIO_FEATURE_CONFIG1_PHYS                                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006008)
#define HWIO_FEATURE_CONFIG1_RMSK                                                             0xffffffff
#define HWIO_FEATURE_CONFIG1_IN          \
        in_dword_masked(HWIO_FEATURE_CONFIG1_ADDR, HWIO_FEATURE_CONFIG1_RMSK)
#define HWIO_FEATURE_CONFIG1_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG1_ADDR, m)
#define HWIO_FEATURE_CONFIG1_ICE_FORCE_HW_KEY1_BMSK                                           0x80000000
#define HWIO_FEATURE_CONFIG1_ICE_FORCE_HW_KEY1_SHFT                                                 0x1f
#define HWIO_FEATURE_CONFIG1_ICE_FORCE_HW_KEY0_BMSK                                           0x40000000
#define HWIO_FEATURE_CONFIG1_ICE_FORCE_HW_KEY0_SHFT                                                 0x1e
#define HWIO_FEATURE_CONFIG1_ICE_DISABLE_BMSK                                                 0x20000000
#define HWIO_FEATURE_CONFIG1_ICE_DISABLE_SHFT                                                       0x1d
#define HWIO_FEATURE_CONFIG1_LLCC_FUSE_CACHE_SIZE_ZERO_BMSK                                   0x10000000
#define HWIO_FEATURE_CONFIG1_LLCC_FUSE_CACHE_SIZE_ZERO_SHFT                                         0x1c
#define HWIO_FEATURE_CONFIG1_UFS_SINGLE_LANE_BMSK                                              0x8000000
#define HWIO_FEATURE_CONFIG1_UFS_SINGLE_LANE_SHFT                                                   0x1b
#define HWIO_FEATURE_CONFIG1_SSC_DISABLE_BMSK                                                  0x4000000
#define HWIO_FEATURE_CONFIG1_SSC_DISABLE_SHFT                                                       0x1a
#define HWIO_FEATURE_CONFIG1_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK                               0x2000000
#define HWIO_FEATURE_CONFIG1_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT                                    0x19
#define HWIO_FEATURE_CONFIG1_SSC_SW_ISLAND_MODE_DISABLE_BMSK                                   0x1000000
#define HWIO_FEATURE_CONFIG1_SSC_SW_ISLAND_MODE_DISABLE_SHFT                                        0x18
#define HWIO_FEATURE_CONFIG1_TCSR_SW_OVERRIDE_SOC_HW_VER_BMSK                                   0x800000
#define HWIO_FEATURE_CONFIG1_TCSR_SW_OVERRIDE_SOC_HW_VER_SHFT                                       0x17
#define HWIO_FEATURE_CONFIG1_APS_RESET_DISABLE_BMSK                                             0x400000
#define HWIO_FEATURE_CONFIG1_APS_RESET_DISABLE_SHFT                                                 0x16
#define HWIO_FEATURE_CONFIG1_IRIS_MULTIPIPE_DISABLE_BMSK                                        0x200000
#define HWIO_FEATURE_CONFIG1_IRIS_MULTIPIPE_DISABLE_SHFT                                            0x15
#define HWIO_FEATURE_CONFIG1_DOLBY_BIT_BMSK                                                     0x100000
#define HWIO_FEATURE_CONFIG1_DOLBY_BIT_SHFT                                                         0x14
#define HWIO_FEATURE_CONFIG1_QC_UDK_DISABLE_BMSK                                                 0x80000
#define HWIO_FEATURE_CONFIG1_QC_UDK_DISABLE_SHFT                                                    0x13
#define HWIO_FEATURE_CONFIG1_STACKED_MEMORY_ID_BMSK                                              0x7c000
#define HWIO_FEATURE_CONFIG1_STACKED_MEMORY_ID_SHFT                                                  0xe
#define HWIO_FEATURE_CONFIG1_PRNG_TESTMODE_DISABLE_BMSK                                           0x2000
#define HWIO_FEATURE_CONFIG1_PRNG_TESTMODE_DISABLE_SHFT                                              0xd
#define HWIO_FEATURE_CONFIG1_MDSS_Q_CONFIG_FUSE_BMSK                                              0x1000
#define HWIO_FEATURE_CONFIG1_MDSS_Q_CONFIG_FUSE_SHFT                                                 0xc
#define HWIO_FEATURE_CONFIG1_MOCHA_PART_BMSK                                                       0x800
#define HWIO_FEATURE_CONFIG1_MOCHA_PART_SHFT                                                         0xb
#define HWIO_FEATURE_CONFIG1_NIDNT_DISABLE_BMSK                                                    0x400
#define HWIO_FEATURE_CONFIG1_NIDNT_DISABLE_SHFT                                                      0xa
#define HWIO_FEATURE_CONFIG1_SMMU_DISABLE_BMSK                                                     0x200
#define HWIO_FEATURE_CONFIG1_SMMU_DISABLE_SHFT                                                       0x9
#define HWIO_FEATURE_CONFIG1_VENDOR_LOCK_BMSK                                                      0x1e0
#define HWIO_FEATURE_CONFIG1_VENDOR_LOCK_SHFT                                                        0x5
#define HWIO_FEATURE_CONFIG1_CM_FEAT_CONFIG_DISABLE_BMSK                                            0x10
#define HWIO_FEATURE_CONFIG1_CM_FEAT_CONFIG_DISABLE_SHFT                                             0x4
#define HWIO_FEATURE_CONFIG1_VFE_RESOLUTION_LIMIT_BMSK                                               0x8
#define HWIO_FEATURE_CONFIG1_VFE_RESOLUTION_LIMIT_SHFT                                               0x3
#define HWIO_FEATURE_CONFIG1_PCIE_2_DISABLE_BMSK                                                     0x4
#define HWIO_FEATURE_CONFIG1_PCIE_2_DISABLE_SHFT                                                     0x2
#define HWIO_FEATURE_CONFIG1_PCIE_1_DISABLE_BMSK                                                     0x2
#define HWIO_FEATURE_CONFIG1_PCIE_1_DISABLE_SHFT                                                     0x1
#define HWIO_FEATURE_CONFIG1_PCIE_0_DISABLE_BMSK                                                     0x1
#define HWIO_FEATURE_CONFIG1_PCIE_0_DISABLE_SHFT                                                     0x0

#define HWIO_FEATURE_CONFIG2_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000600c)
#define HWIO_FEATURE_CONFIG2_PHYS                                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000600c)
#define HWIO_FEATURE_CONFIG2_RMSK                                                             0xffffffff
#define HWIO_FEATURE_CONFIG2_IN          \
        in_dword_masked(HWIO_FEATURE_CONFIG2_ADDR, HWIO_FEATURE_CONFIG2_RMSK)
#define HWIO_FEATURE_CONFIG2_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG2_ADDR, m)
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_HARD_BMSK                                  0xffffc000
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_HARD_SHFT                                         0xe
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_IU_BMSK                                        0x3c00
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_IU_SHFT                                           0xa
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_SPARE_BMSK                                      0x3ff
#define HWIO_FEATURE_CONFIG2_MODEM_FEATURE_DISABLE_SPARE_SHFT                                        0x0

#define HWIO_FEATURE_CONFIG3_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006010)
#define HWIO_FEATURE_CONFIG3_PHYS                                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006010)
#define HWIO_FEATURE_CONFIG3_RMSK                                                             0xffffffff
#define HWIO_FEATURE_CONFIG3_IN          \
        in_dword_masked(HWIO_FEATURE_CONFIG3_ADDR, HWIO_FEATURE_CONFIG3_RMSK)
#define HWIO_FEATURE_CONFIG3_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG3_ADDR, m)
#define HWIO_FEATURE_CONFIG3_APSS_PDXWRPNTRDELAY_BMSK                                         0xc0000000
#define HWIO_FEATURE_CONFIG3_APSS_PDXWRPNTRDELAY_SHFT                                               0x1e
#define HWIO_FEATURE_CONFIG3_RSVD0_BMSK                                                       0x3c000000
#define HWIO_FEATURE_CONFIG3_RSVD0_SHFT                                                             0x1a
#define HWIO_FEATURE_CONFIG3_MODEM_TCM_BOOT_DISABLE_BMSK                                       0x2000000
#define HWIO_FEATURE_CONFIG3_MODEM_TCM_BOOT_DISABLE_SHFT                                            0x19
#define HWIO_FEATURE_CONFIG3_NAV_DISABLE_BMSK                                                  0x1000000
#define HWIO_FEATURE_CONFIG3_NAV_DISABLE_SHFT                                                       0x18
#define HWIO_FEATURE_CONFIG3_MODEM_FEATURE_DISABLE_SOFT_BMSK                                    0xffffff
#define HWIO_FEATURE_CONFIG3_MODEM_FEATURE_DISABLE_SOFT_SHFT                                         0x0

#define HWIO_FEATURE_CONFIG4_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006014)
#define HWIO_FEATURE_CONFIG4_PHYS                                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006014)
#define HWIO_FEATURE_CONFIG4_RMSK                                                             0xffffffff
#define HWIO_FEATURE_CONFIG4_IN          \
        in_dword_masked(HWIO_FEATURE_CONFIG4_ADDR, HWIO_FEATURE_CONFIG4_RMSK)
#define HWIO_FEATURE_CONFIG4_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG4_ADDR, m)
#define HWIO_FEATURE_CONFIG4_TURING_Q6SS_PLL_L_MAX_9_0_BMSK                                   0xffc00000
#define HWIO_FEATURE_CONFIG4_TURING_Q6SS_PLL_L_MAX_9_0_SHFT                                         0x16
#define HWIO_FEATURE_CONFIG4_RSVD0_BMSK                                                         0x300000
#define HWIO_FEATURE_CONFIG4_RSVD0_SHFT                                                             0x14
#define HWIO_FEATURE_CONFIG4_QC_APPS_NIDEN_DISABLE_BMSK                                          0x80000
#define HWIO_FEATURE_CONFIG4_QC_APPS_NIDEN_DISABLE_SHFT                                             0x13
#define HWIO_FEATURE_CONFIG4_QC_APPS_DBGEN_DISABLE_BMSK                                          0x40000
#define HWIO_FEATURE_CONFIG4_QC_APPS_DBGEN_DISABLE_SHFT                                             0x12
#define HWIO_FEATURE_CONFIG4_QC_SHARED_NS_NIDEN_DISABLE_BMSK                                     0x20000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_NS_NIDEN_DISABLE_SHFT                                        0x11
#define HWIO_FEATURE_CONFIG4_QC_SHARED_NS_DBGEN_DISABLE_BMSK                                     0x10000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_NS_DBGEN_DISABLE_SHFT                                        0x10
#define HWIO_FEATURE_CONFIG4_QC_SHARED_CP_NIDEN_DISABLE_BMSK                                      0x8000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_CP_NIDEN_DISABLE_SHFT                                         0xf
#define HWIO_FEATURE_CONFIG4_QC_SHARED_CP_DBGEN_DISABLE_BMSK                                      0x4000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_CP_DBGEN_DISABLE_SHFT                                         0xe
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MSS_NIDEN_DISABLE_BMSK                                     0x2000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MSS_NIDEN_DISABLE_SHFT                                        0xd
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MSS_DBGEN_DISABLE_BMSK                                     0x1000
#define HWIO_FEATURE_CONFIG4_QC_SHARED_MSS_DBGEN_DISABLE_SHFT                                        0xc
#define HWIO_FEATURE_CONFIG4_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                                   0x800
#define HWIO_FEATURE_CONFIG4_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                                     0xb
#define HWIO_FEATURE_CONFIG4_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK                                    0x400
#define HWIO_FEATURE_CONFIG4_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT                                      0xa
#define HWIO_FEATURE_CONFIG4_PRIVATE_NS_NIDEN_DISABLE_BMSK                                         0x200
#define HWIO_FEATURE_CONFIG4_PRIVATE_NS_NIDEN_DISABLE_SHFT                                           0x9
#define HWIO_FEATURE_CONFIG4_PRIVATE_NS_DBGEN_DISABLE_BMSK                                         0x100
#define HWIO_FEATURE_CONFIG4_PRIVATE_NS_DBGEN_DISABLE_SHFT                                           0x8
#define HWIO_FEATURE_CONFIG4_PRIVATE_CP_NIDEN_DISABLE_BMSK                                          0x80
#define HWIO_FEATURE_CONFIG4_PRIVATE_CP_NIDEN_DISABLE_SHFT                                           0x7
#define HWIO_FEATURE_CONFIG4_PRIVATE_CP_DBGEN_DISABLE_BMSK                                          0x40
#define HWIO_FEATURE_CONFIG4_PRIVATE_CP_DBGEN_DISABLE_SHFT                                           0x6
#define HWIO_FEATURE_CONFIG4_PRIVATE_MSS_NIDEN_DISABLE_BMSK                                         0x20
#define HWIO_FEATURE_CONFIG4_PRIVATE_MSS_NIDEN_DISABLE_SHFT                                          0x5
#define HWIO_FEATURE_CONFIG4_PRIVATE_MSS_DBGEN_DISABLE_BMSK                                         0x10
#define HWIO_FEATURE_CONFIG4_PRIVATE_MSS_DBGEN_DISABLE_SHFT                                          0x4
#define HWIO_FEATURE_CONFIG4_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK                                       0x8
#define HWIO_FEATURE_CONFIG4_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT                                       0x3
#define HWIO_FEATURE_CONFIG4_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK                                        0x4
#define HWIO_FEATURE_CONFIG4_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT                                        0x2
#define HWIO_FEATURE_CONFIG4_SM_BIST_DISABLE_BMSK                                                    0x2
#define HWIO_FEATURE_CONFIG4_SM_BIST_DISABLE_SHFT                                                    0x1
#define HWIO_FEATURE_CONFIG4_TIC_DISABLE_BMSK                                                        0x1
#define HWIO_FEATURE_CONFIG4_TIC_DISABLE_SHFT                                                        0x0

#define HWIO_FEATURE_CONFIG5_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006018)
#define HWIO_FEATURE_CONFIG5_PHYS                                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006018)
#define HWIO_FEATURE_CONFIG5_RMSK                                                             0xffffffff
#define HWIO_FEATURE_CONFIG5_IN          \
        in_dword_masked(HWIO_FEATURE_CONFIG5_ADDR, HWIO_FEATURE_CONFIG5_RMSK)
#define HWIO_FEATURE_CONFIG5_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG5_ADDR, m)
#define HWIO_FEATURE_CONFIG5_OUT(v)      \
        out_dword(HWIO_FEATURE_CONFIG5_ADDR,v)
#define HWIO_FEATURE_CONFIG5_OUTM(m,v) \
        out_dword_masked_ns(HWIO_FEATURE_CONFIG5_ADDR,m,v,HWIO_FEATURE_CONFIG5_IN)
#define HWIO_FEATURE_CONFIG5_SYS_CFG_APC1PLL_LVAL_BMSK                                        0xff000000
#define HWIO_FEATURE_CONFIG5_SYS_CFG_APC1PLL_LVAL_SHFT                                              0x18
#define HWIO_FEATURE_CONFIG5_RSVD1_BMSK                                                         0x800000
#define HWIO_FEATURE_CONFIG5_RSVD1_SHFT                                                             0x17
#define HWIO_FEATURE_CONFIG5_SYS_CFG_L3_SIZE_RED_BMSK                                           0x400000
#define HWIO_FEATURE_CONFIG5_SYS_CFG_L3_SIZE_RED_SHFT                                               0x16
#define HWIO_FEATURE_CONFIG5_AUTO_CCI_RCG_CFG_DISABLE_BMSK                                      0x200000
#define HWIO_FEATURE_CONFIG5_AUTO_CCI_RCG_CFG_DISABLE_SHFT                                          0x15
#define HWIO_FEATURE_CONFIG5_APPS_BOOT_FSM_FUSE_BMSK                                            0x1f8000
#define HWIO_FEATURE_CONFIG5_APPS_BOOT_FSM_FUSE_SHFT                                                 0xf
#define HWIO_FEATURE_CONFIG5_SYS_APCSCFGAPMBOOTONMX_BMSK                                          0x4000
#define HWIO_FEATURE_CONFIG5_SYS_APCSCFGAPMBOOTONMX_SHFT                                             0xe
#define HWIO_FEATURE_CONFIG5_SYS_APCCCFGCPUPRESENT_N_BMSK                                         0x3fc0
#define HWIO_FEATURE_CONFIG5_SYS_APCCCFGCPUPRESENT_N_SHFT                                            0x6
#define HWIO_FEATURE_CONFIG5_TURING_Q6SS_PLL_L_MAX_15_10_BMSK                                       0x3f
#define HWIO_FEATURE_CONFIG5_TURING_Q6SS_PLL_L_MAX_15_10_SHFT                                        0x0

#define HWIO_FEATURE_CONFIG6_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000601c)
#define HWIO_FEATURE_CONFIG6_PHYS                                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000601c)
#define HWIO_FEATURE_CONFIG6_RMSK                                                             0xffffffff
#define HWIO_FEATURE_CONFIG6_IN          \
        in_dword_masked(HWIO_FEATURE_CONFIG6_ADDR, HWIO_FEATURE_CONFIG6_RMSK)
#define HWIO_FEATURE_CONFIG6_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG6_ADDR, m)
#define HWIO_FEATURE_CONFIG6_TAP_GEN_SPARE_INSTR_DISABLE_13_0_BMSK                            0xfffc0000
#define HWIO_FEATURE_CONFIG6_TAP_GEN_SPARE_INSTR_DISABLE_13_0_SHFT                                  0x12
#define HWIO_FEATURE_CONFIG6_TAP_INSTR_DISABLE_BMSK                                              0x3ffff
#define HWIO_FEATURE_CONFIG6_TAP_INSTR_DISABLE_SHFT                                                  0x0

#define HWIO_FEATURE_CONFIG7_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006020)
#define HWIO_FEATURE_CONFIG7_PHYS                                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006020)
#define HWIO_FEATURE_CONFIG7_RMSK                                                             0xffffffff
#define HWIO_FEATURE_CONFIG7_IN          \
        in_dword_masked(HWIO_FEATURE_CONFIG7_ADDR, HWIO_FEATURE_CONFIG7_RMSK)
#define HWIO_FEATURE_CONFIG7_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG7_ADDR, m)
#define HWIO_FEATURE_CONFIG7_SEC_TAP_ACCESS_DISABLE_BMSK                                      0xfffc0000
#define HWIO_FEATURE_CONFIG7_SEC_TAP_ACCESS_DISABLE_SHFT                                            0x12
#define HWIO_FEATURE_CONFIG7_TAP_GEN_SPARE_INSTR_DISABLE_31_14_BMSK                              0x3ffff
#define HWIO_FEATURE_CONFIG7_TAP_GEN_SPARE_INSTR_DISABLE_31_14_SHFT                                  0x0

#define HWIO_FEATURE_CONFIG8_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006024)
#define HWIO_FEATURE_CONFIG8_PHYS                                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006024)
#define HWIO_FEATURE_CONFIG8_RMSK                                                             0xffffffff
#define HWIO_FEATURE_CONFIG8_IN          \
        in_dword_masked(HWIO_FEATURE_CONFIG8_ADDR, HWIO_FEATURE_CONFIG8_RMSK)
#define HWIO_FEATURE_CONFIG8_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG8_ADDR, m)
#define HWIO_FEATURE_CONFIG8_MODEM_PBL_PATCH_VERSION_BMSK                                     0xfe000000
#define HWIO_FEATURE_CONFIG8_MODEM_PBL_PATCH_VERSION_SHFT                                           0x19
#define HWIO_FEATURE_CONFIG8_APPS_PBL_PATCH_VERSION_BMSK                                       0x1fc0000
#define HWIO_FEATURE_CONFIG8_APPS_PBL_PATCH_VERSION_SHFT                                            0x12
#define HWIO_FEATURE_CONFIG8_APPS_PBL_BOOT_SPEED_BMSK                                            0x30000
#define HWIO_FEATURE_CONFIG8_APPS_PBL_BOOT_SPEED_SHFT                                               0x10
#define HWIO_FEATURE_CONFIG8_MODEM_PBL_BOOT_BMSK                                                  0x8000
#define HWIO_FEATURE_CONFIG8_MODEM_PBL_BOOT_SHFT                                                     0xf
#define HWIO_FEATURE_CONFIG8_RSVD1_BMSK                                                           0x4000
#define HWIO_FEATURE_CONFIG8_RSVD1_SHFT                                                              0xe
#define HWIO_FEATURE_CONFIG8_APPS_BOOT_FROM_ROM_BMSK                                              0x2000
#define HWIO_FEATURE_CONFIG8_APPS_BOOT_FROM_ROM_SHFT                                                 0xd
#define HWIO_FEATURE_CONFIG8_RSVD0_BMSK                                                           0x1e00
#define HWIO_FEATURE_CONFIG8_RSVD0_SHFT                                                              0x9
#define HWIO_FEATURE_CONFIG8_ARM_CE_DISABLE_USAGE_BMSK                                             0x100
#define HWIO_FEATURE_CONFIG8_ARM_CE_DISABLE_USAGE_SHFT                                               0x8
#define HWIO_FEATURE_CONFIG8_BOOT_ROM_CFG_BMSK                                                      0xff
#define HWIO_FEATURE_CONFIG8_BOOT_ROM_CFG_SHFT                                                       0x0

#define HWIO_FEATURE_CONFIG9_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006028)
#define HWIO_FEATURE_CONFIG9_PHYS                                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006028)
#define HWIO_FEATURE_CONFIG9_RMSK                                                             0xffffffff
#define HWIO_FEATURE_CONFIG9_IN          \
        in_dword_masked(HWIO_FEATURE_CONFIG9_ADDR, HWIO_FEATURE_CONFIG9_RMSK)
#define HWIO_FEATURE_CONFIG9_INM(m)      \
        in_dword_masked(HWIO_FEATURE_CONFIG9_ADDR, m)
#define HWIO_FEATURE_CONFIG9_APPS_BOOT_TRIGGER_DISABLE_BMSK                                   0x80000000
#define HWIO_FEATURE_CONFIG9_APPS_BOOT_TRIGGER_DISABLE_SHFT                                         0x1f
#define HWIO_FEATURE_CONFIG9_PBL_QSEE_BOOT_FLOW_DISABLE_BMSK                                  0x40000000
#define HWIO_FEATURE_CONFIG9_PBL_QSEE_BOOT_FLOW_DISABLE_SHFT                                        0x1e
#define HWIO_FEATURE_CONFIG9_XBL_SEC_AUTH_DISABLE_BMSK                                        0x20000000
#define HWIO_FEATURE_CONFIG9_XBL_SEC_AUTH_DISABLE_SHFT                                              0x1d
#define HWIO_FEATURE_CONFIG9_MSM_PKG_TYPE_BMSK                                                0x10000000
#define HWIO_FEATURE_CONFIG9_MSM_PKG_TYPE_SHFT                                                      0x1c
#define HWIO_FEATURE_CONFIG9_LOAD_SPU_TEST_IMAGE_BMSK                                          0x8000000
#define HWIO_FEATURE_CONFIG9_LOAD_SPU_TEST_IMAGE_SHFT                                               0x1b
#define HWIO_FEATURE_CONFIG9_RSVD3_BMSK                                                        0x7f80000
#define HWIO_FEATURE_CONFIG9_RSVD3_SHFT                                                             0x13
#define HWIO_FEATURE_CONFIG9_FOUNDRY_ID_BMSK                                                     0x78000
#define HWIO_FEATURE_CONFIG9_FOUNDRY_ID_SHFT                                                         0xf
#define HWIO_FEATURE_CONFIG9_PLL_CFG_BMSK                                                         0x7ff0
#define HWIO_FEATURE_CONFIG9_PLL_CFG_SHFT                                                            0x4
#define HWIO_FEATURE_CONFIG9_APPS_PBL_PLL_CTRL_BMSK                                                  0xf
#define HWIO_FEATURE_CONFIG9_APPS_PBL_PLL_CTRL_SHFT                                                  0x0

#define HWIO_OEM_CONFIG0_ADDR                                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006040)
#define HWIO_OEM_CONFIG0_PHYS                                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006040)
#define HWIO_OEM_CONFIG0_RMSK                                                                 0xffffffff
#define HWIO_OEM_CONFIG0_IN          \
        in_dword_masked(HWIO_OEM_CONFIG0_ADDR, HWIO_OEM_CONFIG0_RMSK)
#define HWIO_OEM_CONFIG0_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG0_ADDR, m)
#define HWIO_OEM_CONFIG0_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                                     0x80000000
#define HWIO_OEM_CONFIG0_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                                           0x1f
#define HWIO_OEM_CONFIG0_SHARED_QSEE_SPIDEN_DISABLE_BMSK                                      0x40000000
#define HWIO_OEM_CONFIG0_SHARED_QSEE_SPIDEN_DISABLE_SHFT                                            0x1e
#define HWIO_OEM_CONFIG0_ALL_DEBUG_DISABLE_BMSK                                               0x20000000
#define HWIO_OEM_CONFIG0_ALL_DEBUG_DISABLE_SHFT                                                     0x1d
#define HWIO_OEM_CONFIG0_DEBUG_POLICY_DISABLE_BMSK                                            0x10000000
#define HWIO_OEM_CONFIG0_DEBUG_POLICY_DISABLE_SHFT                                                  0x1c
#define HWIO_OEM_CONFIG0_SP_DISABLE_BMSK                                                       0x8000000
#define HWIO_OEM_CONFIG0_SP_DISABLE_SHFT                                                            0x1b
#define HWIO_OEM_CONFIG0_UDK_DISABLE_BMSK                                                      0x4000000
#define HWIO_OEM_CONFIG0_UDK_DISABLE_SHFT                                                           0x1a
#define HWIO_OEM_CONFIG0_RSVD2_BMSK                                                            0x2000000
#define HWIO_OEM_CONFIG0_RSVD2_SHFT                                                                 0x19
#define HWIO_OEM_CONFIG0_MSS_HASH_INTEGRITY_CHECK_ENABLE_BMSK                                  0x1000000
#define HWIO_OEM_CONFIG0_MSS_HASH_INTEGRITY_CHECK_ENABLE_SHFT                                       0x18
#define HWIO_OEM_CONFIG0_APPS_HASH_INTEGRITY_CHECK_ENABLE_BMSK                                  0x800000
#define HWIO_OEM_CONFIG0_APPS_HASH_INTEGRITY_CHECK_ENABLE_SHFT                                      0x17
#define HWIO_OEM_CONFIG0_USB_SS_DISABLE_BMSK                                                    0x400000
#define HWIO_OEM_CONFIG0_USB_SS_DISABLE_SHFT                                                        0x16
#define HWIO_OEM_CONFIG0_SW_ROT_USE_SERIAL_NUM_BMSK                                             0x200000
#define HWIO_OEM_CONFIG0_SW_ROT_USE_SERIAL_NUM_SHFT                                                 0x15
#define HWIO_OEM_CONFIG0_DISABLE_ROT_TRANSFER_BMSK                                              0x100000
#define HWIO_OEM_CONFIG0_DISABLE_ROT_TRANSFER_SHFT                                                  0x14
#define HWIO_OEM_CONFIG0_IMAGE_ENCRYPTION_ENABLE_BMSK                                            0x80000
#define HWIO_OEM_CONFIG0_IMAGE_ENCRYPTION_ENABLE_SHFT                                               0x13
#define HWIO_OEM_CONFIG0_ROOT_CERT_TOTAL_NUM_BMSK                                                0x60000
#define HWIO_OEM_CONFIG0_ROOT_CERT_TOTAL_NUM_SHFT                                                   0x11
#define HWIO_OEM_CONFIG0_PBL_USB_TYPE_C_DISABLE_BMSK                                             0x10000
#define HWIO_OEM_CONFIG0_PBL_USB_TYPE_C_DISABLE_SHFT                                                0x10
#define HWIO_OEM_CONFIG0_PBL_LOG_DISABLE_BMSK                                                     0x8000
#define HWIO_OEM_CONFIG0_PBL_LOG_DISABLE_SHFT                                                        0xf
#define HWIO_OEM_CONFIG0_WDOG_EN_BMSK                                                             0x4000
#define HWIO_OEM_CONFIG0_WDOG_EN_SHFT                                                                0xe
#define HWIO_OEM_CONFIG0_RSVD1_BMSK                                                               0x2000
#define HWIO_OEM_CONFIG0_RSVD1_SHFT                                                                  0xd
#define HWIO_OEM_CONFIG0_SW_FUSE_PROG_DISABLE_BMSK                                                0x1000
#define HWIO_OEM_CONFIG0_SW_FUSE_PROG_DISABLE_SHFT                                                   0xc
#define HWIO_OEM_CONFIG0_RSVD0_BMSK                                                                0xc00
#define HWIO_OEM_CONFIG0_RSVD0_SHFT                                                                  0xa
#define HWIO_OEM_CONFIG0_FAST_BOOT_BMSK                                                            0x3e0
#define HWIO_OEM_CONFIG0_FAST_BOOT_SHFT                                                              0x5
#define HWIO_OEM_CONFIG0_SDCC_MCLK_BOOT_FREQ_BMSK                                                   0x10
#define HWIO_OEM_CONFIG0_SDCC_MCLK_BOOT_FREQ_SHFT                                                    0x4
#define HWIO_OEM_CONFIG0_FORCE_USB_BOOT_DISABLE_BMSK                                                 0x8
#define HWIO_OEM_CONFIG0_FORCE_USB_BOOT_DISABLE_SHFT                                                 0x3
#define HWIO_OEM_CONFIG0_FORCE_DLOAD_DISABLE_BMSK                                                    0x4
#define HWIO_OEM_CONFIG0_FORCE_DLOAD_DISABLE_SHFT                                                    0x2
#define HWIO_OEM_CONFIG0_ENUM_TIMEOUT_BMSK                                                           0x2
#define HWIO_OEM_CONFIG0_ENUM_TIMEOUT_SHFT                                                           0x1
#define HWIO_OEM_CONFIG0_E_DLOAD_DISABLE_BMSK                                                        0x1
#define HWIO_OEM_CONFIG0_E_DLOAD_DISABLE_SHFT                                                        0x0

#define HWIO_OEM_CONFIG1_ADDR                                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006044)
#define HWIO_OEM_CONFIG1_PHYS                                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006044)
#define HWIO_OEM_CONFIG1_RMSK                                                                 0xffffffff
#define HWIO_OEM_CONFIG1_IN          \
        in_dword_masked(HWIO_OEM_CONFIG1_ADDR, HWIO_OEM_CONFIG1_RMSK)
#define HWIO_OEM_CONFIG1_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG1_ADDR, m)
#define HWIO_OEM_CONFIG1_RSVD0_BMSK                                                           0xffffff00
#define HWIO_OEM_CONFIG1_RSVD0_SHFT                                                                  0x8
#define HWIO_OEM_CONFIG1_APPS_NIDEN_DISABLE_BMSK                                                    0x80
#define HWIO_OEM_CONFIG1_APPS_NIDEN_DISABLE_SHFT                                                     0x7
#define HWIO_OEM_CONFIG1_APPS_DBGEN_DISABLE_BMSK                                                    0x40
#define HWIO_OEM_CONFIG1_APPS_DBGEN_DISABLE_SHFT                                                     0x6
#define HWIO_OEM_CONFIG1_SHARED_NS_NIDEN_DISABLE_BMSK                                               0x20
#define HWIO_OEM_CONFIG1_SHARED_NS_NIDEN_DISABLE_SHFT                                                0x5
#define HWIO_OEM_CONFIG1_SHARED_NS_DBGEN_DISABLE_BMSK                                               0x10
#define HWIO_OEM_CONFIG1_SHARED_NS_DBGEN_DISABLE_SHFT                                                0x4
#define HWIO_OEM_CONFIG1_SHARED_CP_NIDEN_DISABLE_BMSK                                                0x8
#define HWIO_OEM_CONFIG1_SHARED_CP_NIDEN_DISABLE_SHFT                                                0x3
#define HWIO_OEM_CONFIG1_SHARED_CP_DBGEN_DISABLE_BMSK                                                0x4
#define HWIO_OEM_CONFIG1_SHARED_CP_DBGEN_DISABLE_SHFT                                                0x2
#define HWIO_OEM_CONFIG1_SHARED_MSS_NIDEN_DISABLE_BMSK                                               0x2
#define HWIO_OEM_CONFIG1_SHARED_MSS_NIDEN_DISABLE_SHFT                                               0x1
#define HWIO_OEM_CONFIG1_SHARED_MSS_DBGEN_DISABLE_BMSK                                               0x1
#define HWIO_OEM_CONFIG1_SHARED_MSS_DBGEN_DISABLE_SHFT                                               0x0

#define HWIO_OEM_CONFIG2_ADDR                                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006048)
#define HWIO_OEM_CONFIG2_PHYS                                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006048)
#define HWIO_OEM_CONFIG2_RMSK                                                                 0xffffffff
#define HWIO_OEM_CONFIG2_IN          \
        in_dword_masked(HWIO_OEM_CONFIG2_ADDR, HWIO_OEM_CONFIG2_RMSK)
#define HWIO_OEM_CONFIG2_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG2_ADDR, m)
#define HWIO_OEM_CONFIG2_RSVD1_BMSK                                                           0xffff8000
#define HWIO_OEM_CONFIG2_RSVD1_SHFT                                                                  0xf
#define HWIO_OEM_CONFIG2_OEM_SPARE_REG30_SECURE_BMSK                                              0x4000
#define HWIO_OEM_CONFIG2_OEM_SPARE_REG30_SECURE_SHFT                                                 0xe
#define HWIO_OEM_CONFIG2_OEM_SPARE_REG29_SECURE_BMSK                                              0x2000
#define HWIO_OEM_CONFIG2_OEM_SPARE_REG29_SECURE_SHFT                                                 0xd
#define HWIO_OEM_CONFIG2_OEM_SPARE_REG28_SECURE_BMSK                                              0x1000
#define HWIO_OEM_CONFIG2_OEM_SPARE_REG28_SECURE_SHFT                                                 0xc
#define HWIO_OEM_CONFIG2_OEM_SPARE_REG27_SECURE_BMSK                                               0x800
#define HWIO_OEM_CONFIG2_OEM_SPARE_REG27_SECURE_SHFT                                                 0xb
#define HWIO_OEM_CONFIG2_OEM_SPARE_REG26_SECURE_BMSK                                               0x400
#define HWIO_OEM_CONFIG2_OEM_SPARE_REG26_SECURE_SHFT                                                 0xa
#define HWIO_OEM_CONFIG2_RSVD0_BMSK                                                                0x3ff
#define HWIO_OEM_CONFIG2_RSVD0_SHFT                                                                  0x0

#define HWIO_OEM_CONFIG3_ADDR                                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000604c)
#define HWIO_OEM_CONFIG3_PHYS                                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000604c)
#define HWIO_OEM_CONFIG3_RMSK                                                                 0xffffffff
#define HWIO_OEM_CONFIG3_IN          \
        in_dword_masked(HWIO_OEM_CONFIG3_ADDR, HWIO_OEM_CONFIG3_RMSK)
#define HWIO_OEM_CONFIG3_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG3_ADDR, m)
#define HWIO_OEM_CONFIG3_OEM_PRODUCT_ID_BMSK                                                  0xffff0000
#define HWIO_OEM_CONFIG3_OEM_PRODUCT_ID_SHFT                                                        0x10
#define HWIO_OEM_CONFIG3_OEM_HW_ID_BMSK                                                           0xffff
#define HWIO_OEM_CONFIG3_OEM_HW_ID_SHFT                                                              0x0

#define HWIO_OEM_CONFIG4_ADDR                                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006050)
#define HWIO_OEM_CONFIG4_PHYS                                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006050)
#define HWIO_OEM_CONFIG4_RMSK                                                                 0xffffffff
#define HWIO_OEM_CONFIG4_IN          \
        in_dword_masked(HWIO_OEM_CONFIG4_ADDR, HWIO_OEM_CONFIG4_RMSK)
#define HWIO_OEM_CONFIG4_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG4_ADDR, m)
#define HWIO_OEM_CONFIG4_PERIPH_VID_BMSK                                                      0xffff0000
#define HWIO_OEM_CONFIG4_PERIPH_VID_SHFT                                                            0x10
#define HWIO_OEM_CONFIG4_PERIPH_PID_BMSK                                                          0xffff
#define HWIO_OEM_CONFIG4_PERIPH_PID_SHFT                                                             0x0

#define HWIO_OEM_CONFIG5_ADDR                                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006054)
#define HWIO_OEM_CONFIG5_PHYS                                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006054)
#define HWIO_OEM_CONFIG5_RMSK                                                                 0xffffffff
#define HWIO_OEM_CONFIG5_IN          \
        in_dword_masked(HWIO_OEM_CONFIG5_ADDR, HWIO_OEM_CONFIG5_RMSK)
#define HWIO_OEM_CONFIG5_INM(m)      \
        in_dword_masked(HWIO_OEM_CONFIG5_ADDR, m)
#define HWIO_OEM_CONFIG5_RSVD0_BMSK                                                           0xffffff00
#define HWIO_OEM_CONFIG5_RSVD0_SHFT                                                                  0x8
#define HWIO_OEM_CONFIG5_ANTI_ROLLBACK_FEATURE_EN_BMSK                                              0xff
#define HWIO_OEM_CONFIG5_ANTI_ROLLBACK_FEATURE_EN_SHFT                                               0x0

#define HWIO_BOOT_CONFIG_ADDR                                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006070)
#define HWIO_BOOT_CONFIG_PHYS                                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006070)
#define HWIO_BOOT_CONFIG_RMSK                                                                      0x1ff
#define HWIO_BOOT_CONFIG_IN          \
        in_dword_masked(HWIO_BOOT_CONFIG_ADDR, HWIO_BOOT_CONFIG_RMSK)
#define HWIO_BOOT_CONFIG_INM(m)      \
        in_dword_masked(HWIO_BOOT_CONFIG_ADDR, m)
#define HWIO_BOOT_CONFIG_APPS_PBL_BOOT_SPEED_BMSK                                                  0x180
#define HWIO_BOOT_CONFIG_APPS_PBL_BOOT_SPEED_SHFT                                                    0x7
#define HWIO_BOOT_CONFIG_APPS_BOOT_FROM_ROM_BMSK                                                    0x40
#define HWIO_BOOT_CONFIG_APPS_BOOT_FROM_ROM_SHFT                                                     0x6
#define HWIO_BOOT_CONFIG_FAST_BOOT_BMSK                                                             0x3e
#define HWIO_BOOT_CONFIG_FAST_BOOT_SHFT                                                              0x1
#define HWIO_BOOT_CONFIG_WDOG_EN_BMSK                                                                0x1
#define HWIO_BOOT_CONFIG_WDOG_EN_SHFT                                                                0x0

#define HWIO_SECURE_BOOTn_ADDR(n)                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006078 + 0x4 * (n))
#define HWIO_SECURE_BOOTn_PHYS(n)                                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006078 + 0x4 * (n))
#define HWIO_SECURE_BOOTn_RMSK                                                                     0x1ff
#define HWIO_SECURE_BOOTn_MAXn                                                                        14
#define HWIO_SECURE_BOOTn_INI(n)        \
        in_dword_masked(HWIO_SECURE_BOOTn_ADDR(n), HWIO_SECURE_BOOTn_RMSK)
#define HWIO_SECURE_BOOTn_INMI(n,mask)    \
        in_dword_masked(HWIO_SECURE_BOOTn_ADDR(n), mask)
#define HWIO_SECURE_BOOTn_FUSE_SRC_BMSK                                                            0x100
#define HWIO_SECURE_BOOTn_FUSE_SRC_SHFT                                                              0x8
#define HWIO_SECURE_BOOTn_RSVD_7_BMSK                                                               0x80
#define HWIO_SECURE_BOOTn_RSVD_7_SHFT                                                                0x7
#define HWIO_SECURE_BOOTn_USE_SERIAL_NUM_BMSK                                                       0x40
#define HWIO_SECURE_BOOTn_USE_SERIAL_NUM_SHFT                                                        0x6
#define HWIO_SECURE_BOOTn_AUTH_EN_BMSK                                                              0x20
#define HWIO_SECURE_BOOTn_AUTH_EN_SHFT                                                               0x5
#define HWIO_SECURE_BOOTn_PK_HASH_IN_FUSE_BMSK                                                      0x10
#define HWIO_SECURE_BOOTn_PK_HASH_IN_FUSE_SHFT                                                       0x4
#define HWIO_SECURE_BOOTn_ROM_PK_HASH_INDEX_BMSK                                                     0xf
#define HWIO_SECURE_BOOTn_ROM_PK_HASH_INDEX_SHFT                                                     0x0

#define HWIO_QSEE_INV_OVERRIDE_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060c0)
#define HWIO_QSEE_INV_OVERRIDE_PHYS                                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060c0)
#define HWIO_QSEE_INV_OVERRIDE_RMSK                                                           0xffffffff
#define HWIO_QSEE_INV_OVERRIDE_IN          \
        in_dword_masked(HWIO_QSEE_INV_OVERRIDE_ADDR, HWIO_QSEE_INV_OVERRIDE_RMSK)
#define HWIO_QSEE_INV_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_QSEE_INV_OVERRIDE_ADDR, m)
#define HWIO_QSEE_INV_OVERRIDE_OUT(v)      \
        out_dword(HWIO_QSEE_INV_OVERRIDE_ADDR,v)
#define HWIO_QSEE_INV_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QSEE_INV_OVERRIDE_ADDR,m,v,HWIO_QSEE_INV_OVERRIDE_IN)
#define HWIO_QSEE_INV_OVERRIDE_RSVD_31_1_BMSK                                                 0xfffffffe
#define HWIO_QSEE_INV_OVERRIDE_RSVD_31_1_SHFT                                                        0x1
#define HWIO_QSEE_INV_OVERRIDE_SHARED_QSEE_SPIDEN_DISABLE_BMSK                                       0x1
#define HWIO_QSEE_INV_OVERRIDE_SHARED_QSEE_SPIDEN_DISABLE_SHFT                                       0x0

#define HWIO_QSEE_NI_OVERRIDE_ADDR                                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060c4)
#define HWIO_QSEE_NI_OVERRIDE_PHYS                                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060c4)
#define HWIO_QSEE_NI_OVERRIDE_RMSK                                                            0xffffffff
#define HWIO_QSEE_NI_OVERRIDE_IN          \
        in_dword_masked(HWIO_QSEE_NI_OVERRIDE_ADDR, HWIO_QSEE_NI_OVERRIDE_RMSK)
#define HWIO_QSEE_NI_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_QSEE_NI_OVERRIDE_ADDR, m)
#define HWIO_QSEE_NI_OVERRIDE_OUT(v)      \
        out_dword(HWIO_QSEE_NI_OVERRIDE_ADDR,v)
#define HWIO_QSEE_NI_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QSEE_NI_OVERRIDE_ADDR,m,v,HWIO_QSEE_NI_OVERRIDE_IN)
#define HWIO_QSEE_NI_OVERRIDE_RSVD_31_1_BMSK                                                  0xfffffffe
#define HWIO_QSEE_NI_OVERRIDE_RSVD_31_1_SHFT                                                         0x1
#define HWIO_QSEE_NI_OVERRIDE_SHARED_QSEE_SPNIDEN_DISABLE_BMSK                                       0x1
#define HWIO_QSEE_NI_OVERRIDE_SHARED_QSEE_SPNIDEN_DISABLE_SHFT                                       0x0

#define HWIO_MSS_INV_OVERRIDE_ADDR                                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060c8)
#define HWIO_MSS_INV_OVERRIDE_PHYS                                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060c8)
#define HWIO_MSS_INV_OVERRIDE_RMSK                                                            0xffffffff
#define HWIO_MSS_INV_OVERRIDE_IN          \
        in_dword_masked(HWIO_MSS_INV_OVERRIDE_ADDR, HWIO_MSS_INV_OVERRIDE_RMSK)
#define HWIO_MSS_INV_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_MSS_INV_OVERRIDE_ADDR, m)
#define HWIO_MSS_INV_OVERRIDE_OUT(v)      \
        out_dword(HWIO_MSS_INV_OVERRIDE_ADDR,v)
#define HWIO_MSS_INV_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MSS_INV_OVERRIDE_ADDR,m,v,HWIO_MSS_INV_OVERRIDE_IN)
#define HWIO_MSS_INV_OVERRIDE_RSVD_31_1_BMSK                                                  0xfffffffe
#define HWIO_MSS_INV_OVERRIDE_RSVD_31_1_SHFT                                                         0x1
#define HWIO_MSS_INV_OVERRIDE_SHARED_MSS_DBGEN_DISABLE_BMSK                                          0x1
#define HWIO_MSS_INV_OVERRIDE_SHARED_MSS_DBGEN_DISABLE_SHFT                                          0x0

#define HWIO_MSS_NI_OVERRIDE_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060cc)
#define HWIO_MSS_NI_OVERRIDE_PHYS                                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060cc)
#define HWIO_MSS_NI_OVERRIDE_RMSK                                                             0xffffffff
#define HWIO_MSS_NI_OVERRIDE_IN          \
        in_dword_masked(HWIO_MSS_NI_OVERRIDE_ADDR, HWIO_MSS_NI_OVERRIDE_RMSK)
#define HWIO_MSS_NI_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_MSS_NI_OVERRIDE_ADDR, m)
#define HWIO_MSS_NI_OVERRIDE_OUT(v)      \
        out_dword(HWIO_MSS_NI_OVERRIDE_ADDR,v)
#define HWIO_MSS_NI_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MSS_NI_OVERRIDE_ADDR,m,v,HWIO_MSS_NI_OVERRIDE_IN)
#define HWIO_MSS_NI_OVERRIDE_RSVD_31_1_BMSK                                                   0xfffffffe
#define HWIO_MSS_NI_OVERRIDE_RSVD_31_1_SHFT                                                          0x1
#define HWIO_MSS_NI_OVERRIDE_SHARED_MSS_NIDEN_DISABLE_BMSK                                           0x1
#define HWIO_MSS_NI_OVERRIDE_SHARED_MSS_NIDEN_DISABLE_SHFT                                           0x0

#define HWIO_CP_INV_OVERRIDE_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060d0)
#define HWIO_CP_INV_OVERRIDE_PHYS                                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060d0)
#define HWIO_CP_INV_OVERRIDE_RMSK                                                             0xffffffff
#define HWIO_CP_INV_OVERRIDE_IN          \
        in_dword_masked(HWIO_CP_INV_OVERRIDE_ADDR, HWIO_CP_INV_OVERRIDE_RMSK)
#define HWIO_CP_INV_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_CP_INV_OVERRIDE_ADDR, m)
#define HWIO_CP_INV_OVERRIDE_OUT(v)      \
        out_dword(HWIO_CP_INV_OVERRIDE_ADDR,v)
#define HWIO_CP_INV_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CP_INV_OVERRIDE_ADDR,m,v,HWIO_CP_INV_OVERRIDE_IN)
#define HWIO_CP_INV_OVERRIDE_RSVD_31_1_BMSK                                                   0xfffffffe
#define HWIO_CP_INV_OVERRIDE_RSVD_31_1_SHFT                                                          0x1
#define HWIO_CP_INV_OVERRIDE_SHARED_CP_DBGEN_DISABLE_BMSK                                            0x1
#define HWIO_CP_INV_OVERRIDE_SHARED_CP_DBGEN_DISABLE_SHFT                                            0x0

#define HWIO_CP_NI_OVERRIDE_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060d4)
#define HWIO_CP_NI_OVERRIDE_PHYS                                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060d4)
#define HWIO_CP_NI_OVERRIDE_RMSK                                                              0xffffffff
#define HWIO_CP_NI_OVERRIDE_IN          \
        in_dword_masked(HWIO_CP_NI_OVERRIDE_ADDR, HWIO_CP_NI_OVERRIDE_RMSK)
#define HWIO_CP_NI_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_CP_NI_OVERRIDE_ADDR, m)
#define HWIO_CP_NI_OVERRIDE_OUT(v)      \
        out_dword(HWIO_CP_NI_OVERRIDE_ADDR,v)
#define HWIO_CP_NI_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CP_NI_OVERRIDE_ADDR,m,v,HWIO_CP_NI_OVERRIDE_IN)
#define HWIO_CP_NI_OVERRIDE_RSVD_31_1_BMSK                                                    0xfffffffe
#define HWIO_CP_NI_OVERRIDE_RSVD_31_1_SHFT                                                           0x1
#define HWIO_CP_NI_OVERRIDE_SHARED_CP_NIDEN_DISABLE_BMSK                                             0x1
#define HWIO_CP_NI_OVERRIDE_SHARED_CP_NIDEN_DISABLE_SHFT                                             0x0

#define HWIO_NS_INV_OVERRIDE_ADDR                                                             (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060d8)
#define HWIO_NS_INV_OVERRIDE_PHYS                                                             (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060d8)
#define HWIO_NS_INV_OVERRIDE_RMSK                                                             0xffffffff
#define HWIO_NS_INV_OVERRIDE_IN          \
        in_dword_masked(HWIO_NS_INV_OVERRIDE_ADDR, HWIO_NS_INV_OVERRIDE_RMSK)
#define HWIO_NS_INV_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_NS_INV_OVERRIDE_ADDR, m)
#define HWIO_NS_INV_OVERRIDE_OUT(v)      \
        out_dword(HWIO_NS_INV_OVERRIDE_ADDR,v)
#define HWIO_NS_INV_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_NS_INV_OVERRIDE_ADDR,m,v,HWIO_NS_INV_OVERRIDE_IN)
#define HWIO_NS_INV_OVERRIDE_RSVD_31_5_BMSK                                                   0xffffffe0
#define HWIO_NS_INV_OVERRIDE_RSVD_31_5_SHFT                                                          0x5
#define HWIO_NS_INV_OVERRIDE_APPS_DBGEN_DISABLE_BMSK                                                0x10
#define HWIO_NS_INV_OVERRIDE_APPS_DBGEN_DISABLE_SHFT                                                 0x4
#define HWIO_NS_INV_OVERRIDE_RSVD_3_1_BMSK                                                           0xe
#define HWIO_NS_INV_OVERRIDE_RSVD_3_1_SHFT                                                           0x1
#define HWIO_NS_INV_OVERRIDE_SHARED_NS_DBGEN_DISABLE_BMSK                                            0x1
#define HWIO_NS_INV_OVERRIDE_SHARED_NS_DBGEN_DISABLE_SHFT                                            0x0

#define HWIO_NS_NI_OVERRIDE_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x000060dc)
#define HWIO_NS_NI_OVERRIDE_PHYS                                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060dc)
#define HWIO_NS_NI_OVERRIDE_RMSK                                                              0xffffffff
#define HWIO_NS_NI_OVERRIDE_IN          \
        in_dword_masked(HWIO_NS_NI_OVERRIDE_ADDR, HWIO_NS_NI_OVERRIDE_RMSK)
#define HWIO_NS_NI_OVERRIDE_INM(m)      \
        in_dword_masked(HWIO_NS_NI_OVERRIDE_ADDR, m)
#define HWIO_NS_NI_OVERRIDE_OUT(v)      \
        out_dword(HWIO_NS_NI_OVERRIDE_ADDR,v)
#define HWIO_NS_NI_OVERRIDE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_NS_NI_OVERRIDE_ADDR,m,v,HWIO_NS_NI_OVERRIDE_IN)
#define HWIO_NS_NI_OVERRIDE_RSVD_31_5_BMSK                                                    0xffffffe0
#define HWIO_NS_NI_OVERRIDE_RSVD_31_5_SHFT                                                           0x5
#define HWIO_NS_NI_OVERRIDE_APPS_NIDEN_DISABLE_BMSK                                                 0x10
#define HWIO_NS_NI_OVERRIDE_APPS_NIDEN_DISABLE_SHFT                                                  0x4
#define HWIO_NS_NI_OVERRIDE_RSVD_3_1_BMSK                                                            0xe
#define HWIO_NS_NI_OVERRIDE_RSVD_3_1_SHFT                                                            0x1
#define HWIO_NS_NI_OVERRIDE_SHARED_NS_NIDEN_DISABLE_BMSK                                             0x1
#define HWIO_NS_NI_OVERRIDE_SHARED_NS_NIDEN_DISABLE_SHFT                                             0x0

#define HWIO_CAPT_SEC_GPIO_ADDR                                                               (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006100)
#define HWIO_CAPT_SEC_GPIO_PHYS                                                               (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006100)
#define HWIO_CAPT_SEC_GPIO_RMSK                                                                   0x1fff
#define HWIO_CAPT_SEC_GPIO_IN          \
        in_dword_masked(HWIO_CAPT_SEC_GPIO_ADDR, HWIO_CAPT_SEC_GPIO_RMSK)
#define HWIO_CAPT_SEC_GPIO_INM(m)      \
        in_dword_masked(HWIO_CAPT_SEC_GPIO_ADDR, m)
#define HWIO_CAPT_SEC_GPIO_OUT(v)      \
        out_dword(HWIO_CAPT_SEC_GPIO_ADDR,v)
#define HWIO_CAPT_SEC_GPIO_OUTM(m,v) \
        out_dword_masked_ns(HWIO_CAPT_SEC_GPIO_ADDR,m,v,HWIO_CAPT_SEC_GPIO_IN)
#define HWIO_CAPT_SEC_GPIO_FORCE_USB_BOOT_GPIO_BMSK                                               0x1000
#define HWIO_CAPT_SEC_GPIO_FORCE_USB_BOOT_GPIO_SHFT                                                  0xc
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_AP_AUTH_EN_BMSK                                        0x800
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_AP_AUTH_EN_SHFT                                          0xb
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_AP_PK_HASH_IN_FUSE_BMSK                                0x400
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_AP_PK_HASH_IN_FUSE_SHFT                                  0xa
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_ALL_USE_SERIAL_NUM_BMSK                                0x200
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_ALL_USE_SERIAL_NUM_SHFT                                  0x9
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_PK_HASH_INDEX_SRC_BMSK                                 0x100
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_PK_HASH_INDEX_SRC_SHFT                                   0x8
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_APPS_PBL_BOOT_SPEED_BMSK                                0xc0
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_APPS_PBL_BOOT_SPEED_SHFT                                 0x6
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_APPS_BOOT_FROM_ROM_BMSK                                 0x20
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_APPS_BOOT_FROM_ROM_SHFT                                  0x5
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_FAST_BOOT_BMSK                                          0x1e
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_FAST_BOOT_SHFT                                           0x1
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_WDOG_DISABLE_BMSK                                        0x1
#define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_WDOG_DISABLE_SHFT                                        0x0

#define HWIO_APP_PROC_CFG_ADDR                                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006110)
#define HWIO_APP_PROC_CFG_PHYS                                                                (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006110)
#define HWIO_APP_PROC_CFG_RMSK                                                                       0xf
#define HWIO_APP_PROC_CFG_IN          \
        in_dword_masked(HWIO_APP_PROC_CFG_ADDR, HWIO_APP_PROC_CFG_RMSK)
#define HWIO_APP_PROC_CFG_INM(m)      \
        in_dword_masked(HWIO_APP_PROC_CFG_ADDR, m)
#define HWIO_APP_PROC_CFG_OUT(v)      \
        out_dword(HWIO_APP_PROC_CFG_ADDR,v)
#define HWIO_APP_PROC_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_APP_PROC_CFG_ADDR,m,v,HWIO_APP_PROC_CFG_IN)
#define HWIO_APP_PROC_CFG_SHARED_QSEE_SPNIDEN_BMSK                                                   0x8
#define HWIO_APP_PROC_CFG_SHARED_QSEE_SPNIDEN_SHFT                                                   0x3
#define HWIO_APP_PROC_CFG_SHARED_CP_NIDEN_BMSK                                                       0x4
#define HWIO_APP_PROC_CFG_SHARED_CP_NIDEN_SHFT                                                       0x2
#define HWIO_APP_PROC_CFG_SHARED_NS_NIDEN_BMSK                                                       0x2
#define HWIO_APP_PROC_CFG_SHARED_NS_NIDEN_SHFT                                                       0x1
#define HWIO_APP_PROC_CFG_APPS_NIDEN_BMSK                                                            0x1
#define HWIO_APP_PROC_CFG_APPS_NIDEN_SHFT                                                            0x0

#define HWIO_MSS_PROC_CFG_ADDR                                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006114)
#define HWIO_MSS_PROC_CFG_PHYS                                                                (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006114)
#define HWIO_MSS_PROC_CFG_RMSK                                                                       0x1
#define HWIO_MSS_PROC_CFG_IN          \
        in_dword_masked(HWIO_MSS_PROC_CFG_ADDR, HWIO_MSS_PROC_CFG_RMSK)
#define HWIO_MSS_PROC_CFG_INM(m)      \
        in_dword_masked(HWIO_MSS_PROC_CFG_ADDR, m)
#define HWIO_MSS_PROC_CFG_OUT(v)      \
        out_dword(HWIO_MSS_PROC_CFG_ADDR,v)
#define HWIO_MSS_PROC_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_MSS_PROC_CFG_ADDR,m,v,HWIO_MSS_PROC_CFG_IN)
#define HWIO_MSS_PROC_CFG_SHARED_MSS_NIDEN_BMSK                                                      0x1
#define HWIO_MSS_PROC_CFG_SHARED_MSS_NIDEN_SHFT                                                      0x0

#define HWIO_QFPROM_CLK_CTL_ADDR                                                              (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006118)
#define HWIO_QFPROM_CLK_CTL_PHYS                                                              (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006118)
#define HWIO_QFPROM_CLK_CTL_RMSK                                                                     0x1
#define HWIO_QFPROM_CLK_CTL_IN          \
        in_dword_masked(HWIO_QFPROM_CLK_CTL_ADDR, HWIO_QFPROM_CLK_CTL_RMSK)
#define HWIO_QFPROM_CLK_CTL_INM(m)      \
        in_dword_masked(HWIO_QFPROM_CLK_CTL_ADDR, m)
#define HWIO_QFPROM_CLK_CTL_OUT(v)      \
        out_dword(HWIO_QFPROM_CLK_CTL_ADDR,v)
#define HWIO_QFPROM_CLK_CTL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_CLK_CTL_ADDR,m,v,HWIO_QFPROM_CLK_CTL_IN)
#define HWIO_QFPROM_CLK_CTL_CLK_HALT_BMSK                                                            0x1
#define HWIO_QFPROM_CLK_CTL_CLK_HALT_SHFT                                                            0x0

#define HWIO_JTAG_ID_ADDR                                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006130)
#define HWIO_JTAG_ID_PHYS                                                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006130)
#define HWIO_JTAG_ID_RMSK                                                                     0xffffffff
#define HWIO_JTAG_ID_IN          \
        in_dword_masked(HWIO_JTAG_ID_ADDR, HWIO_JTAG_ID_RMSK)
#define HWIO_JTAG_ID_INM(m)      \
        in_dword_masked(HWIO_JTAG_ID_ADDR, m)
#define HWIO_JTAG_ID_JTAG_ID_BMSK                                                             0xffffffff
#define HWIO_JTAG_ID_JTAG_ID_SHFT                                                                    0x0

#define HWIO_SERIAL_NUM_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006134)
#define HWIO_SERIAL_NUM_PHYS                                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006134)
#define HWIO_SERIAL_NUM_RMSK                                                                  0xffffffff
#define HWIO_SERIAL_NUM_IN          \
        in_dword_masked(HWIO_SERIAL_NUM_ADDR, HWIO_SERIAL_NUM_RMSK)
#define HWIO_SERIAL_NUM_INM(m)      \
        in_dword_masked(HWIO_SERIAL_NUM_ADDR, m)
#define HWIO_SERIAL_NUM_SERIAL_NUM_BMSK                                                       0xffffffff
#define HWIO_SERIAL_NUM_SERIAL_NUM_SHFT                                                              0x0

#define HWIO_OEM_ID_ADDR                                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006138)
#define HWIO_OEM_ID_PHYS                                                                      (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006138)
#define HWIO_OEM_ID_RMSK                                                                      0xffffffff
#define HWIO_OEM_ID_IN          \
        in_dword_masked(HWIO_OEM_ID_ADDR, HWIO_OEM_ID_RMSK)
#define HWIO_OEM_ID_INM(m)      \
        in_dword_masked(HWIO_OEM_ID_ADDR, m)
#define HWIO_OEM_ID_OEM_ID_BMSK                                                               0xffff0000
#define HWIO_OEM_ID_OEM_ID_SHFT                                                                     0x10
#define HWIO_OEM_ID_OEM_PRODUCT_ID_BMSK                                                           0xffff
#define HWIO_OEM_ID_OEM_PRODUCT_ID_SHFT                                                              0x0

#define HWIO_TEST_BUS_SEL_ADDR                                                                (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000613c)
#define HWIO_TEST_BUS_SEL_PHYS                                                                (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000613c)
#define HWIO_TEST_BUS_SEL_RMSK                                                                       0x7
#define HWIO_TEST_BUS_SEL_IN          \
        in_dword_masked(HWIO_TEST_BUS_SEL_ADDR, HWIO_TEST_BUS_SEL_RMSK)
#define HWIO_TEST_BUS_SEL_INM(m)      \
        in_dword_masked(HWIO_TEST_BUS_SEL_ADDR, m)
#define HWIO_TEST_BUS_SEL_OUT(v)      \
        out_dword(HWIO_TEST_BUS_SEL_ADDR,v)
#define HWIO_TEST_BUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TEST_BUS_SEL_ADDR,m,v,HWIO_TEST_BUS_SEL_IN)
#define HWIO_TEST_BUS_SEL_TEST_EN_BMSK                                                               0x4
#define HWIO_TEST_BUS_SEL_TEST_EN_SHFT                                                               0x2
#define HWIO_TEST_BUS_SEL_TEST_SELECT_BMSK                                                           0x3
#define HWIO_TEST_BUS_SEL_TEST_SELECT_SHFT                                                           0x0

#define HWIO_SPDM_DYN_SECURE_MODE_ADDR                                                        (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006140)
#define HWIO_SPDM_DYN_SECURE_MODE_PHYS                                                        (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006140)
#define HWIO_SPDM_DYN_SECURE_MODE_RMSK                                                               0x1
#define HWIO_SPDM_DYN_SECURE_MODE_IN          \
        in_dword_masked(HWIO_SPDM_DYN_SECURE_MODE_ADDR, HWIO_SPDM_DYN_SECURE_MODE_RMSK)
#define HWIO_SPDM_DYN_SECURE_MODE_INM(m)      \
        in_dword_masked(HWIO_SPDM_DYN_SECURE_MODE_ADDR, m)
#define HWIO_SPDM_DYN_SECURE_MODE_OUT(v)      \
        out_dword(HWIO_SPDM_DYN_SECURE_MODE_ADDR,v)
#define HWIO_SPDM_DYN_SECURE_MODE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_SPDM_DYN_SECURE_MODE_ADDR,m,v,HWIO_SPDM_DYN_SECURE_MODE_IN)
#define HWIO_SPDM_DYN_SECURE_MODE_SECURE_MODE_BMSK                                                   0x1
#define HWIO_SPDM_DYN_SECURE_MODE_SECURE_MODE_SHFT                                                   0x0

#define HWIO_CHIP_ID_ADDR                                                                     (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006144)
#define HWIO_CHIP_ID_PHYS                                                                     (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006144)
#define HWIO_CHIP_ID_RMSK                                                                         0xffff
#define HWIO_CHIP_ID_IN          \
        in_dword_masked(HWIO_CHIP_ID_ADDR, HWIO_CHIP_ID_RMSK)
#define HWIO_CHIP_ID_INM(m)      \
        in_dword_masked(HWIO_CHIP_ID_ADDR, m)
#define HWIO_CHIP_ID_CHIP_ID_BMSK                                                                 0xffff
#define HWIO_CHIP_ID_CHIP_ID_SHFT                                                                    0x0

#define HWIO_OEM_IMAGE_ENCR_KEYn_ADDR(n)                                                      (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006150 + 0x4 * (n))
#define HWIO_OEM_IMAGE_ENCR_KEYn_PHYS(n)                                                      (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006150 + 0x4 * (n))
#define HWIO_OEM_IMAGE_ENCR_KEYn_RMSK                                                         0xffffffff
#define HWIO_OEM_IMAGE_ENCR_KEYn_MAXn                                                                  3
#define HWIO_OEM_IMAGE_ENCR_KEYn_INI(n)        \
        in_dword_masked(HWIO_OEM_IMAGE_ENCR_KEYn_ADDR(n), HWIO_OEM_IMAGE_ENCR_KEYn_RMSK)
#define HWIO_OEM_IMAGE_ENCR_KEYn_INMI(n,mask)    \
        in_dword_masked(HWIO_OEM_IMAGE_ENCR_KEYn_ADDR(n), mask)
#define HWIO_OEM_IMAGE_ENCR_KEYn_KEY_DATA0_BMSK                                               0xffffffff
#define HWIO_OEM_IMAGE_ENCR_KEYn_KEY_DATA0_SHFT                                                      0x0

#define HWIO_IMAGE_ENCR_KEY1_0_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006160)
#define HWIO_IMAGE_ENCR_KEY1_0_PHYS                                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006160)
#define HWIO_IMAGE_ENCR_KEY1_0_RMSK                                                           0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_0_IN          \
        in_dword_masked(HWIO_IMAGE_ENCR_KEY1_0_ADDR, HWIO_IMAGE_ENCR_KEY1_0_RMSK)
#define HWIO_IMAGE_ENCR_KEY1_0_INM(m)      \
        in_dword_masked(HWIO_IMAGE_ENCR_KEY1_0_ADDR, m)
#define HWIO_IMAGE_ENCR_KEY1_0_KEY_DATA0_BMSK                                                 0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_0_KEY_DATA0_SHFT                                                        0x0

#define HWIO_IMAGE_ENCR_KEY1_1_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006164)
#define HWIO_IMAGE_ENCR_KEY1_1_PHYS                                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006164)
#define HWIO_IMAGE_ENCR_KEY1_1_RMSK                                                           0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_1_IN          \
        in_dword_masked(HWIO_IMAGE_ENCR_KEY1_1_ADDR, HWIO_IMAGE_ENCR_KEY1_1_RMSK)
#define HWIO_IMAGE_ENCR_KEY1_1_INM(m)      \
        in_dword_masked(HWIO_IMAGE_ENCR_KEY1_1_ADDR, m)
#define HWIO_IMAGE_ENCR_KEY1_1_KEY_DATA0_BMSK                                                 0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_1_KEY_DATA0_SHFT                                                        0x0

#define HWIO_IMAGE_ENCR_KEY1_2_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006168)
#define HWIO_IMAGE_ENCR_KEY1_2_PHYS                                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006168)
#define HWIO_IMAGE_ENCR_KEY1_2_RMSK                                                           0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_2_IN          \
        in_dword_masked(HWIO_IMAGE_ENCR_KEY1_2_ADDR, HWIO_IMAGE_ENCR_KEY1_2_RMSK)
#define HWIO_IMAGE_ENCR_KEY1_2_INM(m)      \
        in_dword_masked(HWIO_IMAGE_ENCR_KEY1_2_ADDR, m)
#define HWIO_IMAGE_ENCR_KEY1_2_KEY_DATA0_BMSK                                                 0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_2_KEY_DATA0_SHFT                                                        0x0

#define HWIO_IMAGE_ENCR_KEY1_3_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000616c)
#define HWIO_IMAGE_ENCR_KEY1_3_PHYS                                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000616c)
#define HWIO_IMAGE_ENCR_KEY1_3_RMSK                                                           0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_3_IN          \
        in_dword_masked(HWIO_IMAGE_ENCR_KEY1_3_ADDR, HWIO_IMAGE_ENCR_KEY1_3_RMSK)
#define HWIO_IMAGE_ENCR_KEY1_3_INM(m)      \
        in_dword_masked(HWIO_IMAGE_ENCR_KEY1_3_ADDR, m)
#define HWIO_IMAGE_ENCR_KEY1_3_KEY_DATA0_BMSK                                                 0xffffffff
#define HWIO_IMAGE_ENCR_KEY1_3_KEY_DATA0_SHFT                                                        0x0

#define HWIO_PK_HASH0_0_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006190)
#define HWIO_PK_HASH0_0_PHYS                                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006190)
#define HWIO_PK_HASH0_0_RMSK                                                                  0xffffffff
#define HWIO_PK_HASH0_0_IN          \
        in_dword_masked(HWIO_PK_HASH0_0_ADDR, HWIO_PK_HASH0_0_RMSK)
#define HWIO_PK_HASH0_0_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_0_ADDR, m)
#define HWIO_PK_HASH0_0_HASH_DATA0_BMSK                                                       0xffffffff
#define HWIO_PK_HASH0_0_HASH_DATA0_SHFT                                                              0x0

#define HWIO_PK_HASH0_1_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006194)
#define HWIO_PK_HASH0_1_PHYS                                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006194)
#define HWIO_PK_HASH0_1_RMSK                                                                  0xffffffff
#define HWIO_PK_HASH0_1_IN          \
        in_dword_masked(HWIO_PK_HASH0_1_ADDR, HWIO_PK_HASH0_1_RMSK)
#define HWIO_PK_HASH0_1_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_1_ADDR, m)
#define HWIO_PK_HASH0_1_HASH_DATA0_BMSK                                                       0xffffffff
#define HWIO_PK_HASH0_1_HASH_DATA0_SHFT                                                              0x0

#define HWIO_PK_HASH0_2_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006198)
#define HWIO_PK_HASH0_2_PHYS                                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006198)
#define HWIO_PK_HASH0_2_RMSK                                                                  0xffffffff
#define HWIO_PK_HASH0_2_IN          \
        in_dword_masked(HWIO_PK_HASH0_2_ADDR, HWIO_PK_HASH0_2_RMSK)
#define HWIO_PK_HASH0_2_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_2_ADDR, m)
#define HWIO_PK_HASH0_2_HASH_DATA0_BMSK                                                       0xffffffff
#define HWIO_PK_HASH0_2_HASH_DATA0_SHFT                                                              0x0

#define HWIO_PK_HASH0_3_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000619c)
#define HWIO_PK_HASH0_3_PHYS                                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000619c)
#define HWIO_PK_HASH0_3_RMSK                                                                  0xffffffff
#define HWIO_PK_HASH0_3_IN          \
        in_dword_masked(HWIO_PK_HASH0_3_ADDR, HWIO_PK_HASH0_3_RMSK)
#define HWIO_PK_HASH0_3_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_3_ADDR, m)
#define HWIO_PK_HASH0_3_HASH_DATA0_BMSK                                                       0xffffffff
#define HWIO_PK_HASH0_3_HASH_DATA0_SHFT                                                              0x0

#define HWIO_PK_HASH0_4_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061a0)
#define HWIO_PK_HASH0_4_PHYS                                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061a0)
#define HWIO_PK_HASH0_4_RMSK                                                                  0xffffffff
#define HWIO_PK_HASH0_4_IN          \
        in_dword_masked(HWIO_PK_HASH0_4_ADDR, HWIO_PK_HASH0_4_RMSK)
#define HWIO_PK_HASH0_4_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_4_ADDR, m)
#define HWIO_PK_HASH0_4_HASH_DATA0_BMSK                                                       0xffffffff
#define HWIO_PK_HASH0_4_HASH_DATA0_SHFT                                                              0x0

#define HWIO_PK_HASH0_5_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061a4)
#define HWIO_PK_HASH0_5_PHYS                                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061a4)
#define HWIO_PK_HASH0_5_RMSK                                                                  0xffffffff
#define HWIO_PK_HASH0_5_IN          \
        in_dword_masked(HWIO_PK_HASH0_5_ADDR, HWIO_PK_HASH0_5_RMSK)
#define HWIO_PK_HASH0_5_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_5_ADDR, m)
#define HWIO_PK_HASH0_5_HASH_DATA0_BMSK                                                       0xffffffff
#define HWIO_PK_HASH0_5_HASH_DATA0_SHFT                                                              0x0

#define HWIO_PK_HASH0_6_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061a8)
#define HWIO_PK_HASH0_6_PHYS                                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061a8)
#define HWIO_PK_HASH0_6_RMSK                                                                  0xffffffff
#define HWIO_PK_HASH0_6_IN          \
        in_dword_masked(HWIO_PK_HASH0_6_ADDR, HWIO_PK_HASH0_6_RMSK)
#define HWIO_PK_HASH0_6_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_6_ADDR, m)
#define HWIO_PK_HASH0_6_HASH_DATA0_BMSK                                                       0xffffffff
#define HWIO_PK_HASH0_6_HASH_DATA0_SHFT                                                              0x0

#define HWIO_PK_HASH0_7_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061ac)
#define HWIO_PK_HASH0_7_PHYS                                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061ac)
#define HWIO_PK_HASH0_7_RMSK                                                                  0xffffffff
#define HWIO_PK_HASH0_7_IN          \
        in_dword_masked(HWIO_PK_HASH0_7_ADDR, HWIO_PK_HASH0_7_RMSK)
#define HWIO_PK_HASH0_7_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_7_ADDR, m)
#define HWIO_PK_HASH0_7_HASH_DATA0_BMSK                                                       0xffffffff
#define HWIO_PK_HASH0_7_HASH_DATA0_SHFT                                                              0x0

#define HWIO_PK_HASH0_8_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061b0)
#define HWIO_PK_HASH0_8_PHYS                                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061b0)
#define HWIO_PK_HASH0_8_RMSK                                                                  0xffffffff
#define HWIO_PK_HASH0_8_IN          \
        in_dword_masked(HWIO_PK_HASH0_8_ADDR, HWIO_PK_HASH0_8_RMSK)
#define HWIO_PK_HASH0_8_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_8_ADDR, m)
#define HWIO_PK_HASH0_8_HASH_DATA0_BMSK                                                       0xffffffff
#define HWIO_PK_HASH0_8_HASH_DATA0_SHFT                                                              0x0

#define HWIO_PK_HASH0_9_ADDR                                                                  (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061b4)
#define HWIO_PK_HASH0_9_PHYS                                                                  (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061b4)
#define HWIO_PK_HASH0_9_RMSK                                                                  0xffffffff
#define HWIO_PK_HASH0_9_IN          \
        in_dword_masked(HWIO_PK_HASH0_9_ADDR, HWIO_PK_HASH0_9_RMSK)
#define HWIO_PK_HASH0_9_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_9_ADDR, m)
#define HWIO_PK_HASH0_9_HASH_DATA0_BMSK                                                       0xffffffff
#define HWIO_PK_HASH0_9_HASH_DATA0_SHFT                                                              0x0

#define HWIO_PK_HASH0_10_ADDR                                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061b8)
#define HWIO_PK_HASH0_10_PHYS                                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061b8)
#define HWIO_PK_HASH0_10_RMSK                                                                 0xffffffff
#define HWIO_PK_HASH0_10_IN          \
        in_dword_masked(HWIO_PK_HASH0_10_ADDR, HWIO_PK_HASH0_10_RMSK)
#define HWIO_PK_HASH0_10_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_10_ADDR, m)
#define HWIO_PK_HASH0_10_HASH_DATA0_BMSK                                                      0xffffffff
#define HWIO_PK_HASH0_10_HASH_DATA0_SHFT                                                             0x0

#define HWIO_PK_HASH0_11_ADDR                                                                 (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061bc)
#define HWIO_PK_HASH0_11_PHYS                                                                 (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061bc)
#define HWIO_PK_HASH0_11_RMSK                                                                 0xffffffff
#define HWIO_PK_HASH0_11_IN          \
        in_dword_masked(HWIO_PK_HASH0_11_ADDR, HWIO_PK_HASH0_11_RMSK)
#define HWIO_PK_HASH0_11_INM(m)      \
        in_dword_masked(HWIO_PK_HASH0_11_ADDR, m)
#define HWIO_PK_HASH0_11_HASH_DATA0_BMSK                                                      0xffffffff
#define HWIO_PK_HASH0_11_HASH_DATA0_SHFT                                                             0x0

#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061f0)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_PHYS                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061f0)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_RMSK                                            0xffffffff
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_IN          \
        in_dword_masked(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR, HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_RMSK)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_INM(m)      \
        in_dword_masked(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR, m)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_OUT(v)      \
        out_dword(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR,v)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR,m,v,HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_IN)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_RSVD0_BMSK                                      0x80000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_RSVD0_SHFT                                            0x1f
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION30_STICKY_BIT_BMSK                        0x40000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION30_STICKY_BIT_SHFT                              0x1e
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION29_STICKY_BIT_BMSK                        0x20000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION29_STICKY_BIT_SHFT                              0x1d
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION28_STICKY_BIT_BMSK                        0x10000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION28_STICKY_BIT_SHFT                              0x1c
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION27_STICKY_BIT_BMSK                         0x8000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION27_STICKY_BIT_SHFT                              0x1b
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION26_STICKY_BIT_BMSK                         0x4000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION26_STICKY_BIT_SHFT                              0x1a
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION25_STICKY_BIT_BMSK                         0x2000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION25_STICKY_BIT_SHFT                              0x19
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION24_STICKY_BIT_BMSK                         0x1000000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION24_STICKY_BIT_SHFT                              0x18
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION23_STICKY_BIT_BMSK                          0x800000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION23_STICKY_BIT_SHFT                              0x17
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION22_STICKY_BIT_BMSK                          0x400000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION22_STICKY_BIT_SHFT                              0x16
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION21_STICKY_BIT_BMSK                          0x200000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION21_STICKY_BIT_SHFT                              0x15
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION20_STICKY_BIT_BMSK                          0x100000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION20_STICKY_BIT_SHFT                              0x14
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION19_STICKY_BIT_BMSK                           0x80000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION19_STICKY_BIT_SHFT                              0x13
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION18_STICKY_BIT_BMSK                           0x40000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION18_STICKY_BIT_SHFT                              0x12
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION17_STICKY_BIT_BMSK                           0x20000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION17_STICKY_BIT_SHFT                              0x11
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION16_STICKY_BIT_BMSK                           0x10000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION16_STICKY_BIT_SHFT                              0x10
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION15_STICKY_BIT_BMSK                            0x8000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION15_STICKY_BIT_SHFT                               0xf
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION14_STICKY_BIT_BMSK                            0x4000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION14_STICKY_BIT_SHFT                               0xe
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION13_STICKY_BIT_BMSK                            0x2000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION13_STICKY_BIT_SHFT                               0xd
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION12_STICKY_BIT_BMSK                            0x1000
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION12_STICKY_BIT_SHFT                               0xc
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION11_STICKY_BIT_BMSK                             0x800
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION11_STICKY_BIT_SHFT                               0xb
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION10_STICKY_BIT_BMSK                             0x400
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION10_STICKY_BIT_SHFT                               0xa
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION9_STICKY_BIT_BMSK                              0x200
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION9_STICKY_BIT_SHFT                                0x9
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION8_STICKY_BIT_BMSK                              0x100
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION8_STICKY_BIT_SHFT                                0x8
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION7_STICKY_BIT_BMSK                               0x80
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION7_STICKY_BIT_SHFT                                0x7
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION6_STICKY_BIT_BMSK                               0x40
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION6_STICKY_BIT_SHFT                                0x6
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION5_STICKY_BIT_BMSK                               0x20
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION5_STICKY_BIT_SHFT                                0x5
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION4_STICKY_BIT_BMSK                               0x10
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION4_STICKY_BIT_SHFT                                0x4
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION3_STICKY_BIT_BMSK                                0x8
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION3_STICKY_BIT_SHFT                                0x3
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION2_STICKY_BIT_BMSK                                0x4
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION2_STICKY_BIT_SHFT                                0x2
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION1_STICKY_BIT_BMSK                                0x2
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION1_STICKY_BIT_SHFT                                0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION0_STICKY_BIT_BMSK                                0x1
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION0_STICKY_BIT_SHFT                                0x0

#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR                                            (SECURITY_CONTROL_CORE_REG_BASE      + 0x000061f4)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_PHYS                                            (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061f4)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_RMSK                                            0xffffffff
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_IN          \
        in_dword_masked(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR, HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_RMSK)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_INM(m)      \
        in_dword_masked(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR, m)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_OUT(v)      \
        out_dword(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR,v)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR,m,v,HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_IN)
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_RSVD0_BMSK                                      0xffffffff
#define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_RSVD0_SHFT                                             0x0

#define HWIO_ANTI_ROLLBACK_1_0_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006200)
#define HWIO_ANTI_ROLLBACK_1_0_PHYS                                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006200)
#define HWIO_ANTI_ROLLBACK_1_0_RMSK                                                           0xffffffff
#define HWIO_ANTI_ROLLBACK_1_0_IN          \
        in_dword_masked(HWIO_ANTI_ROLLBACK_1_0_ADDR, HWIO_ANTI_ROLLBACK_1_0_RMSK)
#define HWIO_ANTI_ROLLBACK_1_0_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_1_0_ADDR, m)
#define HWIO_ANTI_ROLLBACK_1_0_XBL0_BMSK                                                      0xffffffff
#define HWIO_ANTI_ROLLBACK_1_0_XBL0_SHFT                                                             0x0

#define HWIO_ANTI_ROLLBACK_1_1_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006204)
#define HWIO_ANTI_ROLLBACK_1_1_PHYS                                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006204)
#define HWIO_ANTI_ROLLBACK_1_1_RMSK                                                           0xffffffff
#define HWIO_ANTI_ROLLBACK_1_1_IN          \
        in_dword_masked(HWIO_ANTI_ROLLBACK_1_1_ADDR, HWIO_ANTI_ROLLBACK_1_1_RMSK)
#define HWIO_ANTI_ROLLBACK_1_1_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_1_1_ADDR, m)
#define HWIO_ANTI_ROLLBACK_1_1_XBL1_BMSK                                                      0xffffffff
#define HWIO_ANTI_ROLLBACK_1_1_XBL1_SHFT                                                             0x0

#define HWIO_ANTI_ROLLBACK_2_0_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006208)
#define HWIO_ANTI_ROLLBACK_2_0_PHYS                                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006208)
#define HWIO_ANTI_ROLLBACK_2_0_RMSK                                                           0xffffffff
#define HWIO_ANTI_ROLLBACK_2_0_IN          \
        in_dword_masked(HWIO_ANTI_ROLLBACK_2_0_ADDR, HWIO_ANTI_ROLLBACK_2_0_RMSK)
#define HWIO_ANTI_ROLLBACK_2_0_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_2_0_ADDR, m)
#define HWIO_ANTI_ROLLBACK_2_0_PIL_SUBSYSTEM_31_0_BMSK                                        0xffffffff
#define HWIO_ANTI_ROLLBACK_2_0_PIL_SUBSYSTEM_31_0_SHFT                                               0x0

#define HWIO_ANTI_ROLLBACK_2_1_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000620c)
#define HWIO_ANTI_ROLLBACK_2_1_PHYS                                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000620c)
#define HWIO_ANTI_ROLLBACK_2_1_RMSK                                                           0xffffffff
#define HWIO_ANTI_ROLLBACK_2_1_IN          \
        in_dword_masked(HWIO_ANTI_ROLLBACK_2_1_ADDR, HWIO_ANTI_ROLLBACK_2_1_RMSK)
#define HWIO_ANTI_ROLLBACK_2_1_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_2_1_ADDR, m)
#define HWIO_ANTI_ROLLBACK_2_1_XBL_SEC_BMSK                                                   0xfe000000
#define HWIO_ANTI_ROLLBACK_2_1_XBL_SEC_SHFT                                                         0x19
#define HWIO_ANTI_ROLLBACK_2_1_RPM_BMSK                                                        0x1fe0000
#define HWIO_ANTI_ROLLBACK_2_1_RPM_SHFT                                                             0x11
#define HWIO_ANTI_ROLLBACK_2_1_TZ_BMSK                                                           0x1ffff
#define HWIO_ANTI_ROLLBACK_2_1_TZ_SHFT                                                               0x0

#define HWIO_ANTI_ROLLBACK_3_0_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006210)
#define HWIO_ANTI_ROLLBACK_3_0_PHYS                                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006210)
#define HWIO_ANTI_ROLLBACK_3_0_RMSK                                                           0xffffffff
#define HWIO_ANTI_ROLLBACK_3_0_IN          \
        in_dword_masked(HWIO_ANTI_ROLLBACK_3_0_ADDR, HWIO_ANTI_ROLLBACK_3_0_RMSK)
#define HWIO_ANTI_ROLLBACK_3_0_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_3_0_ADDR, m)
#define HWIO_ANTI_ROLLBACK_3_0_RSVD1_BMSK                                                     0xc0000000
#define HWIO_ANTI_ROLLBACK_3_0_RSVD1_SHFT                                                           0x1e
#define HWIO_ANTI_ROLLBACK_3_0_TQS_HASH_ACTIVE_BMSK                                           0x3e000000
#define HWIO_ANTI_ROLLBACK_3_0_TQS_HASH_ACTIVE_SHFT                                                 0x19
#define HWIO_ANTI_ROLLBACK_3_0_RPMB_KEY_PROVISIONED_BMSK                                       0x1000000
#define HWIO_ANTI_ROLLBACK_3_0_RPMB_KEY_PROVISIONED_SHFT                                            0x18
#define HWIO_ANTI_ROLLBACK_3_0_PIL_SUBSYSTEM_47_32_BMSK                                         0xffff00
#define HWIO_ANTI_ROLLBACK_3_0_PIL_SUBSYSTEM_47_32_SHFT                                              0x8
#define HWIO_ANTI_ROLLBACK_3_0_SAFESWITCH_BMSK                                                      0xff
#define HWIO_ANTI_ROLLBACK_3_0_SAFESWITCH_SHFT                                                       0x0

#define HWIO_ANTI_ROLLBACK_3_1_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006214)
#define HWIO_ANTI_ROLLBACK_3_1_PHYS                                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006214)
#define HWIO_ANTI_ROLLBACK_3_1_RMSK                                                           0xffffffff
#define HWIO_ANTI_ROLLBACK_3_1_IN          \
        in_dword_masked(HWIO_ANTI_ROLLBACK_3_1_ADDR, HWIO_ANTI_ROLLBACK_3_1_RMSK)
#define HWIO_ANTI_ROLLBACK_3_1_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_3_1_ADDR, m)
#define HWIO_ANTI_ROLLBACK_3_1_RSVD1_BMSK                                                     0xf0000000
#define HWIO_ANTI_ROLLBACK_3_1_RSVD1_SHFT                                                           0x1c
#define HWIO_ANTI_ROLLBACK_3_1_DEVICE_CFG_BMSK                                                 0xffe0000
#define HWIO_ANTI_ROLLBACK_3_1_DEVICE_CFG_SHFT                                                      0x11
#define HWIO_ANTI_ROLLBACK_3_1_DEBUG_POLICY_BMSK                                                 0x1f000
#define HWIO_ANTI_ROLLBACK_3_1_DEBUG_POLICY_SHFT                                                     0xc
#define HWIO_ANTI_ROLLBACK_3_1_HYPERVISOR_BMSK                                                     0xfff
#define HWIO_ANTI_ROLLBACK_3_1_HYPERVISOR_SHFT                                                       0x0

#define HWIO_ANTI_ROLLBACK_4_0_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006218)
#define HWIO_ANTI_ROLLBACK_4_0_PHYS                                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006218)
#define HWIO_ANTI_ROLLBACK_4_0_RMSK                                                           0xffffffff
#define HWIO_ANTI_ROLLBACK_4_0_IN          \
        in_dword_masked(HWIO_ANTI_ROLLBACK_4_0_ADDR, HWIO_ANTI_ROLLBACK_4_0_RMSK)
#define HWIO_ANTI_ROLLBACK_4_0_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_4_0_ADDR, m)
#define HWIO_ANTI_ROLLBACK_4_0_MSS_BMSK                                                       0xffff0000
#define HWIO_ANTI_ROLLBACK_4_0_MSS_SHFT                                                             0x10
#define HWIO_ANTI_ROLLBACK_4_0_MBA_BMSK                                                           0xffff
#define HWIO_ANTI_ROLLBACK_4_0_MBA_SHFT                                                              0x0

#define HWIO_ANTI_ROLLBACK_4_1_ADDR                                                           (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000621c)
#define HWIO_ANTI_ROLLBACK_4_1_PHYS                                                           (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000621c)
#define HWIO_ANTI_ROLLBACK_4_1_RMSK                                                           0xffffffff
#define HWIO_ANTI_ROLLBACK_4_1_IN          \
        in_dword_masked(HWIO_ANTI_ROLLBACK_4_1_ADDR, HWIO_ANTI_ROLLBACK_4_1_RMSK)
#define HWIO_ANTI_ROLLBACK_4_1_INM(m)      \
        in_dword_masked(HWIO_ANTI_ROLLBACK_4_1_ADDR, m)
#define HWIO_ANTI_ROLLBACK_4_1_SIMLOCK_BMSK                                                   0x80000000
#define HWIO_ANTI_ROLLBACK_4_1_SIMLOCK_SHFT                                                         0x1f
#define HWIO_ANTI_ROLLBACK_4_1_RSVD0_BMSK                                                     0x7fffffff
#define HWIO_ANTI_ROLLBACK_4_1_RSVD0_SHFT                                                            0x0

#define HWIO_MRC_2_0_0_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006250)
#define HWIO_MRC_2_0_0_PHYS                                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006250)
#define HWIO_MRC_2_0_0_RMSK                                                                   0xffffffff
#define HWIO_MRC_2_0_0_IN          \
        in_dword_masked(HWIO_MRC_2_0_0_ADDR, HWIO_MRC_2_0_0_RMSK)
#define HWIO_MRC_2_0_0_INM(m)      \
        in_dword_masked(HWIO_MRC_2_0_0_ADDR, m)
#define HWIO_MRC_2_0_0_RSVD0_BMSK                                                             0xfffffff0
#define HWIO_MRC_2_0_0_RSVD0_SHFT                                                                    0x4
#define HWIO_MRC_2_0_0_ROOT_CERT_ACTIVATION_LIST_BMSK                                                0xf
#define HWIO_MRC_2_0_0_ROOT_CERT_ACTIVATION_LIST_SHFT                                                0x0

#define HWIO_MRC_2_0_1_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006254)
#define HWIO_MRC_2_0_1_PHYS                                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006254)
#define HWIO_MRC_2_0_1_RMSK                                                                   0xffffffff
#define HWIO_MRC_2_0_1_IN          \
        in_dword_masked(HWIO_MRC_2_0_1_ADDR, HWIO_MRC_2_0_1_RMSK)
#define HWIO_MRC_2_0_1_INM(m)      \
        in_dword_masked(HWIO_MRC_2_0_1_ADDR, m)
#define HWIO_MRC_2_0_1_RSVD1_BMSK                                                             0xfffffffe
#define HWIO_MRC_2_0_1_RSVD1_SHFT                                                                    0x1
#define HWIO_MRC_2_0_1_CURRENT_UIE_KEY_SEL_BMSK                                                      0x1
#define HWIO_MRC_2_0_1_CURRENT_UIE_KEY_SEL_SHFT                                                      0x0

#define HWIO_MRC_2_0_2_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006258)
#define HWIO_MRC_2_0_2_PHYS                                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006258)
#define HWIO_MRC_2_0_2_RMSK                                                                   0xffffffff
#define HWIO_MRC_2_0_2_IN          \
        in_dword_masked(HWIO_MRC_2_0_2_ADDR, HWIO_MRC_2_0_2_RMSK)
#define HWIO_MRC_2_0_2_INM(m)      \
        in_dword_masked(HWIO_MRC_2_0_2_ADDR, m)
#define HWIO_MRC_2_0_2_RSVD0_BMSK                                                             0xfffffff0
#define HWIO_MRC_2_0_2_RSVD0_SHFT                                                                    0x4
#define HWIO_MRC_2_0_2_ROOT_CERT_REVOCATION_LIST_BMSK                                                0xf
#define HWIO_MRC_2_0_2_ROOT_CERT_REVOCATION_LIST_SHFT                                                0x0

#define HWIO_MRC_2_0_3_ADDR                                                                   (SECURITY_CONTROL_CORE_REG_BASE      + 0x0000625c)
#define HWIO_MRC_2_0_3_PHYS                                                                   (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000625c)
#define HWIO_MRC_2_0_3_RMSK                                                                   0xffffffff
#define HWIO_MRC_2_0_3_IN          \
        in_dword_masked(HWIO_MRC_2_0_3_ADDR, HWIO_MRC_2_0_3_RMSK)
#define HWIO_MRC_2_0_3_INM(m)      \
        in_dword_masked(HWIO_MRC_2_0_3_ADDR, m)
#define HWIO_MRC_2_0_3_RSVD0_BMSK                                                             0xffffffff
#define HWIO_MRC_2_0_3_RSVD0_SHFT                                                                    0x0

#define HWIO_CRYPTO_LIB_VERSION_ADDR                                                          (SECURITY_CONTROL_CORE_REG_BASE      + 0x00006300)
#define HWIO_CRYPTO_LIB_VERSION_PHYS                                                          (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006300)
#define HWIO_CRYPTO_LIB_VERSION_RMSK                                                          0xffffffff
#define HWIO_CRYPTO_LIB_VERSION_IN          \
        in_dword_masked(HWIO_CRYPTO_LIB_VERSION_ADDR, HWIO_CRYPTO_LIB_VERSION_RMSK)
#define HWIO_CRYPTO_LIB_VERSION_INM(m)      \
        in_dword_masked(HWIO_CRYPTO_LIB_VERSION_ADDR, m)
#define HWIO_CRYPTO_LIB_VERSION_VERSION_BMSK                                                  0xffffffff
#define HWIO_CRYPTO_LIB_VERSION_VERSION_SHFT                                                         0x0

/*----------------------------------------------------------------------------
 * MODULE: TCSR_TCSR_REGS
 *--------------------------------------------------------------------------*/

#define TCSR_TCSR_REGS_REG_BASE                                                                                      (CORE_TOP_CSR_BASE      + 0x000c0000)
#define TCSR_TCSR_REGS_REG_BASE_PHYS                                                                                 (CORE_TOP_CSR_BASE_PHYS + 0x000c0000)

#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_ADDR                                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x0000d000)
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_PHYS                                                                       (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d000)
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_RMSK                                                                              0xf
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_ADDR, HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_RMSK)
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_ADDR, m)
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDMMCX_READ_BMSK                                                  0x8
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDMMCX_READ_SHFT                                                  0x3
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDGFX_READ_BMSK                                                   0x4
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDGFX_READ_SHFT                                                   0x2
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDMSS_READ_BMSK                                                   0x2
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDMSS_READ_SHFT                                                   0x1
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDCX_READ_BMSK                                                    0x1
#define HWIO_TCSR_AOSS_MEM_TURBO_READ_REG_AOSS_MEM_TURBO_VDDCX_READ_SHFT                                                    0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022010)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022010)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_RMSK                                                                 0xff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_7_BMSK                                 0xff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_7_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_7_SHFT                                  0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022014)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022014)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_RMSK                                                                 0xff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_6_BMSK                                 0xff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_6_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_6_SHFT                                  0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022018)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022018)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_RMSK                                                                 0xff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_5_BMSK                                 0xff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_5_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_5_SHFT                                  0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0002201c)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002201c)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_RMSK                                                                 0xff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_4_BMSK                                 0xff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_4_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_4_SHFT                                  0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022020)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022020)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_RMSK                                                                 0xff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_3_BMSK                                 0xff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_3_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_3_SHFT                                  0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022024)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022024)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_RMSK                                                                 0xff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_2_BMSK                                 0xff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_2_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_2_SHFT                                  0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00022028)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022028)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_RMSK                                                                 0xff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_1_BMSK                                 0xff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_1_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_1_SHFT                                  0x0

#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0002202c)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002202c)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_RMSK                                                                 0xff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_0_BMSK                                 0xff
#define HWIO_TCSR_DBGOVR_VALUE_COMPILER_MEM_ACC_0_REG_DBGOVR_VALUE_COMPILER_MEM_ACC_0_SHFT                                  0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00022030)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_PHYS                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022030)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_RMSK                                                               0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_BMSK                             0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE1_SHFT                              0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00022034)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_PHYS                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022034)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_RMSK                                                               0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_BMSK                             0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE2_SHFT                              0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00022038)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_PHYS                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022038)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_RMSK                                                               0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_BMSK                             0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE3_SHFT                              0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x0002203c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_PHYS                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002203c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_RMSK                                                               0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_BMSK                             0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE4_SHFT                              0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00022040)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_PHYS                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022040)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_RMSK                                                               0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_BMSK                             0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE5_SHFT                              0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00022044)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_PHYS                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022044)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_RMSK                                                               0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_BMSK                             0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE6_SHFT                              0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00022048)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_PHYS                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022048)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_RMSK                                                               0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_BMSK                             0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE7_SHFT                              0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x0002204c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_PHYS                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002204c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_RMSK                                                               0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_BMSK                             0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE8_SHFT                              0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00022050)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_PHYS                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022050)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_RMSK                                                               0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_BMSK                             0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE9_SHFT                              0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00022054)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022054)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE10_SHFT                            0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00022058)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022058)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE11_SHFT                            0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x0002205c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002205c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE12_SHFT                            0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00022060)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022060)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE13_SHFT                            0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00022064)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022064)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE14_SHFT                            0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00022068)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022068)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE15_SHFT                            0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x0002206c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002206c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE16_SHFT                            0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00022070)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022070)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE17_SHFT                            0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00022074)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022074)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE18_SHFT                            0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00022078)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022078)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE19_SHFT                            0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x0002207c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002207c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE20_SHFT                            0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00022080)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022080)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE21_SHFT                            0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00022084)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022084)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE22_SHFT                            0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00022088)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022088)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE23_SHFT                            0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x0002208c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002208c)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE24_SHFT                            0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00022090)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022090)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE25_SHFT                            0x0

#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00022094)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022094)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_RMSK                                                              0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_ADDR, HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_RMSK)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_ADDR, m)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_ADDR,v)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_ADDR,m,v,HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_IN)
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_BMSK                           0xff
#define HWIO_TCSR_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_REG_DBGOVR_VALUE_CUSTOM_MEM_ACC_TYPE26_SHFT                            0x0

#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d004)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d004)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_RMSK                                                              0xffffffff
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_ADDR, HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_FUSE_COMPILER_MEM_ACC_0_READ_BMSK                                 0xffffffff
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_0_READ_REG_FUSE_COMPILER_MEM_ACC_0_READ_SHFT                                        0x0

#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000d008)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d008)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_RMSK                                                              0xffffffff
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_ADDR, HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_FUSE_COMPILER_MEM_ACC_1_READ_BMSK                                 0xffffffff
#define HWIO_TCSR_FUSE_COMPILER_MEM_ACC_1_READ_REG_FUSE_COMPILER_MEM_ACC_1_READ_SHFT                                        0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0000d00c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_PHYS                                                            (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d00c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_RMSK                                                                  0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_BMSK                                   0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE1_READ_SHFT                                    0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0000d010)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_PHYS                                                            (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d010)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_RMSK                                                                  0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_BMSK                                   0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE2_READ_SHFT                                    0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0000d014)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_PHYS                                                            (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d014)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_RMSK                                                                  0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_BMSK                                   0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE3_READ_SHFT                                    0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0000d018)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_PHYS                                                            (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d018)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_RMSK                                                                  0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_BMSK                                   0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE4_READ_SHFT                                    0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0000d01c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_PHYS                                                            (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d01c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_RMSK                                                                  0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_BMSK                                   0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE5_READ_SHFT                                    0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0000d020)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_PHYS                                                            (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d020)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_RMSK                                                                  0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_BMSK                                   0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE6_READ_SHFT                                    0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0000d024)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_PHYS                                                            (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d024)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_RMSK                                                                  0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_BMSK                                   0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE7_READ_SHFT                                    0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0000d028)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_PHYS                                                            (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d028)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_RMSK                                                                  0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_BMSK                                   0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE8_READ_SHFT                                    0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_ADDR                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x0000d02c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_PHYS                                                            (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d02c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_RMSK                                                                  0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_BMSK                                   0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE9_READ_SHFT                                    0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d030)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d030)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE10_READ_SHFT                                  0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d034)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d034)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE11_READ_SHFT                                  0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d038)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d038)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE12_READ_SHFT                                  0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d03c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d03c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE13_READ_SHFT                                  0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d040)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d040)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE14_READ_SHFT                                  0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d044)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d044)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE15_READ_SHFT                                  0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d048)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d048)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE16_READ_SHFT                                  0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d04c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d04c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE17_READ_SHFT                                  0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d050)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d050)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE18_READ_SHFT                                  0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d054)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d054)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE19_READ_SHFT                                  0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d058)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d058)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE20_READ_SHFT                                  0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d05c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d05c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE21_READ_SHFT                                  0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d060)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d060)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE22_READ_SHFT                                  0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d064)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d064)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE23_READ_SHFT                                  0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d068)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d068)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE24_READ_SHFT                                  0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d06c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d06c)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE25_READ_SHFT                                  0x0

#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_ADDR                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0000d070)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_PHYS                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000d070)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_RMSK                                                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_IN          \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_ADDR, HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_RMSK)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_ADDR, m)
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_BMSK                                 0xff
#define HWIO_TCSR_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_REG_FUSE_CUSTOM_MEM_ACC_TYPE26_READ_SHFT                                  0x0

#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_ADDR                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x00022000)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_PHYS                                                                   (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022000)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_RMSK                                                                          0x1
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_ADDR, HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_RMSK)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_ADDR, m)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_ADDR,v)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_ADDR,m,v,HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_IN)
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_DBGOVR_COMPILER_MEM_ACC_SEL_BMSK                                              0x1
#define HWIO_TCSR_DBGOVR_COMPILER_MEM_ACC_SEL_DBGOVR_COMPILER_MEM_ACC_SEL_SHFT                                              0x0

#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_ADDR                                                                     (TCSR_TCSR_REGS_REG_BASE      + 0x00022004)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_PHYS                                                                     (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022004)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_RMSK                                                                            0x1
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_IN          \
        in_dword_masked(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_ADDR, HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_RMSK)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_ADDR, m)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_OUT(v)      \
        out_dword(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_ADDR,v)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_ADDR,m,v,HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_IN)
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_DBGOVR_CUSTOM_MEM_ACC_SEL_BMSK                                                  0x1
#define HWIO_TCSR_DBGOVR_CUSTOM_MEM_ACC_SEL_DBGOVR_CUSTOM_MEM_ACC_SEL_SHFT                                                  0x0

#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_ADDR                                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00022800)
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_PHYS                                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022800)
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_RMSK                                                                         0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_IN          \
        in_dword_masked(HWIO_TCSR_MBIST_DBG_STATUS0_REG_ADDR, HWIO_TCSR_MBIST_DBG_STATUS0_REG_RMSK)
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_MBIST_DBG_STATUS0_REG_ADDR, m)
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_MBIST_DBG_STATUS0_BMSK                                                       0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS0_REG_MBIST_DBG_STATUS0_SHFT                                                              0x0

#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_ADDR                                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00022804)
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_PHYS                                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022804)
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_RMSK                                                                         0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_IN          \
        in_dword_masked(HWIO_TCSR_MBIST_DBG_STATUS1_REG_ADDR, HWIO_TCSR_MBIST_DBG_STATUS1_REG_RMSK)
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_MBIST_DBG_STATUS1_REG_ADDR, m)
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_MBIST_DBG_STATUS1_BMSK                                                       0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS1_REG_MBIST_DBG_STATUS1_SHFT                                                              0x0

#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_ADDR                                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00022808)
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_PHYS                                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00022808)
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_RMSK                                                                         0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_IN          \
        in_dword_masked(HWIO_TCSR_MBIST_DBG_STATUS2_REG_ADDR, HWIO_TCSR_MBIST_DBG_STATUS2_REG_RMSK)
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_MBIST_DBG_STATUS2_REG_ADDR, m)
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_MBIST_DBG_STATUS2_BMSK                                                       0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS2_REG_MBIST_DBG_STATUS2_SHFT                                                              0x0

#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_ADDR                                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x0002280c)
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_PHYS                                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002280c)
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_RMSK                                                                         0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_IN          \
        in_dword_masked(HWIO_TCSR_MBIST_DBG_STATUS3_REG_ADDR, HWIO_TCSR_MBIST_DBG_STATUS3_REG_RMSK)
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_INM(m)      \
        in_dword_masked(HWIO_TCSR_MBIST_DBG_STATUS3_REG_ADDR, m)
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_MBIST_DBG_STATUS3_BMSK                                                       0xffffffff
#define HWIO_TCSR_MBIST_DBG_STATUS3_REG_MBIST_DBG_STATUS3_SHFT                                                              0x0

#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x00000800)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_PHYS                                                                          (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00000800)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_RMSK                                                                                 0x1
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_IN          \
        in_dword_masked(HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_ADDR, HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_RMSK)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_ADDR, m)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_OUT(v)      \
        out_dword(HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_ADDR,v)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_ADDR,m,v,HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_IN)
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_TIMEOUT_SLAVE_GLB_EN_BMSK                                                            0x1
#define HWIO_TCSR_TIMEOUT_SLAVE_GLB_EN_TIMEOUT_SLAVE_GLB_EN_SHFT                                                            0x0

#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x00002000)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_PHYS                                                                          (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00002000)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_RMSK                                                                          0xffffffff
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_IN          \
        in_dword_masked(HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ADDR, HWIO_TCSR_SS_XPU_NON_SEC_INTR0_RMSK)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ADDR, m)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR0_BMSK                        0x80000000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR0_SHFT                              0x1f
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_BOOT_ROM_XPU_NON_SEC_INTR0_BMSK                                               0x40000000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_BOOT_ROM_XPU_NON_SEC_INTR0_SHFT                                                     0x1e
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR0_BMSK                            0x20000000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR0_SHFT                                  0x1d
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_LLCC3_XPU_NON_SEC_INTR0_BMSK                                                  0x10000000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_LLCC3_XPU_NON_SEC_INTR0_SHFT                                                        0x1c
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_LLCC2_XPU_NON_SEC_INTR0_BMSK                                                   0x8000000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_LLCC2_XPU_NON_SEC_INTR0_SHFT                                                        0x1b
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_LLCC1_XPU_NON_SEC_INTR0_BMSK                                                   0x4000000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_LLCC1_XPU_NON_SEC_INTR0_SHFT                                                        0x1a
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_LLCC0_XPU_NON_SEC_INTR0_BMSK                                                   0x2000000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_LLCC0_XPU_NON_SEC_INTR0_SHFT                                                        0x19
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_UFS_XPU_NON_SEC_INTR0_BMSK                                                     0x1000000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_UFS_XPU_NON_SEC_INTR0_SHFT                                                          0x18
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_QXS_BOOT_IMEM_SS_MPU_XPU_NON_SEC_INTR0_BMSK                                     0x800000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_QXS_BOOT_IMEM_SS_MPU_XPU_NON_SEC_INTR0_SHFT                                         0x17
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_SSC_SDC_XPU_NON_SEC_INTR0_BMSK                                                  0x400000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_SSC_SDC_XPU_NON_SEC_INTR0_SHFT                                                      0x16
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_GCC_XPU_NON_SEC_INTR0_BMSK                                                      0x200000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_GCC_XPU_NON_SEC_INTR0_SHFT                                                          0x15
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_MEMNOC_XPU_NON_SEC_INTR0_BMSK                                                   0x100000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_MEMNOC_XPU_NON_SEC_INTR0_SHFT                                                       0x14
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_QM_XPU_NON_SEC_INTR0_BMSK                                                        0x80000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_QM_XPU_NON_SEC_INTR0_SHFT                                                           0x13
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_QNM_SNOC_XPU_NON_SEC_INTR0_BMSK                                                  0x40000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_QNM_SNOC_XPU_NON_SEC_INTR0_SHFT                                                     0x12
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_QHS_CNOC_XPU_NON_SEC_INTR0_BMSK                                                  0x20000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_QHS_CNOC_XPU_NON_SEC_INTR0_SHFT                                                     0x11
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_QHM_AOSS_XPU_NON_SEC_INTR0_BMSK                                                  0x10000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_QHM_AOSS_XPU_NON_SEC_INTR0_SHFT                                                     0x10
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_SP_XPU_NON_SEC_INTR0_BMSK                                                         0x8000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_SP_XPU_NON_SEC_INTR0_SHFT                                                            0xf
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_PIMEM_MPU_XPU_NON_SEC_INTR0_BMSK                                                  0x4000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_PIMEM_MPU_XPU_NON_SEC_INTR0_SHFT                                                     0xe
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_PIMEM_APU_XPU_NON_SEC_INTR0_BMSK                                                  0x2000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_PIMEM_APU_XPU_NON_SEC_INTR0_SHFT                                                     0xd
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_SSC_Q6_XPU_NON_SEC_INTR0_BMSK                                                     0x1000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_SSC_Q6_XPU_NON_SEC_INTR0_SHFT                                                        0xc
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_SSC_XPU_NON_SEC_INTR0_BMSK                                                         0x800
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_SSC_XPU_NON_SEC_INTR0_SHFT                                                           0xb
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_SSC_QUP_XPU_NON_SEC_INTR0_BMSK                                                     0x400
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_SSC_QUP_XPU_NON_SEC_INTR0_SHFT                                                       0xa
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_SEC_CTRL_XPU_NON_SEC_INTR0_BMSK                                                    0x200
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_SEC_CTRL_XPU_NON_SEC_INTR0_SHFT                                                      0x9
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_DCC_XPU_NON_SEC_INTR0_BMSK                                                         0x100
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_DCC_XPU_NON_SEC_INTR0_SHFT                                                           0x8
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_OCIMEM_RPU_XPU_NON_SEC_INTR0_BMSK                                                   0x80
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_OCIMEM_RPU_XPU_NON_SEC_INTR0_SHFT                                                    0x7
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_CRYPTO0_XPU_NON_SEC_INTR0_BMSK                                                      0x40
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_CRYPTO0_XPU_NON_SEC_INTR0_SHFT                                                       0x6
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_TCSR_MUTEX_XPU_NON_SEC_INTR0_BMSK                                                   0x20
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_TCSR_MUTEX_XPU_NON_SEC_INTR0_SHFT                                                    0x5
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_QUPV3_1_XPU_NON_SEC_INTR0_BMSK                                                      0x10
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_QUPV3_1_XPU_NON_SEC_INTR0_SHFT                                                       0x4
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_TCSR_REGS_XPU_NON_SEC_INTR0_BMSK                                                     0x8
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_TCSR_REGS_XPU_NON_SEC_INTR0_SHFT                                                     0x3
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_QUPV3_0_XPU_NON_SEC_INTR0_BMSK                                                       0x4
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_QUPV3_0_XPU_NON_SEC_INTR0_SHFT                                                       0x2
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_AOSS_MPU_XPU_NON_SEC_INTR0_BMSK                                                      0x2
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_AOSS_MPU_XPU_NON_SEC_INTR0_SHFT                                                      0x1
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_PMIC_ARB_XPU_NON_SEC_INTR0_BMSK                                                      0x1
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_PMIC_ARB_XPU_NON_SEC_INTR0_SHFT                                                      0x0

#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x00002004)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_PHYS                                                                          (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00002004)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_RMSK                                                                             0x7ffff
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_IN          \
        in_dword_masked(HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ADDR, HWIO_TCSR_SS_XPU_NON_SEC_INTR1_RMSK)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ADDR, m)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_RESERVE_50_BMSK                                                                  0x40000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_RESERVE_50_SHFT                                                                     0x12
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_RESERVE_49_BMSK                                                                  0x20000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_RESERVE_49_SHFT                                                                     0x11
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_RESERVE_48_BMSK                                                                  0x10000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_RESERVE_48_SHFT                                                                     0x10
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_TLMM_NORTH_XPU_NON_SEC_INTR1_BMSK                                                 0x8000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_TLMM_NORTH_XPU_NON_SEC_INTR1_SHFT                                                    0xf
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_RESERVE_46_BMSK                                                                   0x4000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_RESERVE_46_SHFT                                                                      0xe
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_RESERVE_45_BMSK                                                                   0x2000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_RESERVE_45_SHFT                                                                      0xd
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_QUPV3_2_XPU_NON_SEC_INTR1_BMSK                                                    0x1000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_QUPV3_2_XPU_NON_SEC_INTR1_SHFT                                                       0xc
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_IPA_XPU_NON_SEC_INTR1_BMSK                                                         0x800
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_IPA_XPU_NON_SEC_INTR1_SHFT                                                           0xb
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_TLMM_EAST_XPU_NON_SEC_INTR1_BMSK                                                   0x400
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_TLMM_EAST_XPU_NON_SEC_INTR1_SHFT                                                     0xa
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_TLMM_SOUTH_XPU_NON_SEC_INTR1_BMSK                                                  0x200
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_TLMM_SOUTH_XPU_NON_SEC_INTR1_SHFT                                                    0x9
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_TLMM_WEST_XPU_NON_SEC_INTR1_BMSK                                                   0x100
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_TLMM_WEST_XPU_NON_SEC_INTR1_SHFT                                                     0x8
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_MDSS_XPU_NON_SEC_INTR1_BMSK                                                         0x80
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_MDSS_XPU_NON_SEC_INTR1_SHFT                                                          0x7
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_UFS_CARD_ICE_XPU_NON_SEC_INTR1_BMSK                                                 0x40
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_UFS_CARD_ICE_XPU_NON_SEC_INTR1_SHFT                                                  0x6
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_TITAN_XPU_NON_SEC_INTR1_BMSK                                                        0x20
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_TITAN_XPU_NON_SEC_INTR1_SHFT                                                         0x5
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_SPDM_XPU_NON_SEC_INTR1_BMSK                                                         0x10
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_SPDM_XPU_NON_SEC_INTR1_SHFT                                                          0x4
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_QXM_MSS_NAV_XPU_NON_SEC_INTR1_BMSK                                                   0x8
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_QXM_MSS_NAV_XPU_NON_SEC_INTR1_SHFT                                                   0x3
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_QNM_AGGRE2_XPU_NON_SEC_INTR1_BMSK                                                    0x4
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_QNM_AGGRE2_XPU_NON_SEC_INTR1_SHFT                                                    0x2
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_QNM_AGGRE1_XPU_NON_SEC_INTR1_BMSK                                                    0x2
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_QNM_AGGRE1_XPU_NON_SEC_INTR1_SHFT                                                    0x1
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_OCIMEM_XPU3_XPU_NON_SEC_INTR1_BMSK                                                   0x1
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_OCIMEM_XPU3_XPU_NON_SEC_INTR1_SHFT                                                   0x0

#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_ADDR                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x00002040)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_PHYS                                                                   (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00002040)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_RMSK                                                                   0xffffffff
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_ADDR, HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_RMSK)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_ADDR, m)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_ADDR,v)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_ADDR,m,v,HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_IN)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR0_ENABLE_BMSK          0x80000000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR0_ENABLE_SHFT                0x1f
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_BOOT_ROM_XPU_NON_SEC_INTR0_ENABLE_BMSK                                 0x40000000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_BOOT_ROM_XPU_NON_SEC_INTR0_ENABLE_SHFT                                       0x1e
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_DTP_QHS_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR0_ENABLE_BMSK              0x20000000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_DTP_QHS_BROADCAST_MPU_MAINO_XPU_NON_SEC_INTR0_ENABLE_SHFT                    0x1d
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_LLCC3_XPU_NON_SEC_INTR0_ENABLE_BMSK                                    0x10000000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_LLCC3_XPU_NON_SEC_INTR0_ENABLE_SHFT                                          0x1c
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_LLCC2_XPU_NON_SEC_INTR0_ENABLE_BMSK                                     0x8000000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_LLCC2_XPU_NON_SEC_INTR0_ENABLE_SHFT                                          0x1b
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_LLCC1_XPU_NON_SEC_INTR0_ENABLE_BMSK                                     0x4000000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_LLCC1_XPU_NON_SEC_INTR0_ENABLE_SHFT                                          0x1a
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_LLCC0_XPU_NON_SEC_INTR0_ENABLE_BMSK                                     0x2000000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_LLCC0_XPU_NON_SEC_INTR0_ENABLE_SHFT                                          0x19
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_UFS_XPU_NON_SEC_INTR0_ENABLE_BMSK                                       0x1000000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_UFS_XPU_NON_SEC_INTR0_ENABLE_SHFT                                            0x18
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_QXS_BOOT_IMEM_SS_MPU_XPU_NON_SEC_INTR0_ENABLE_BMSK                       0x800000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_QXS_BOOT_IMEM_SS_MPU_XPU_NON_SEC_INTR0_ENABLE_SHFT                           0x17
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_SSC_SDC_XPU_NON_SEC_INTR0_ENABLE_BMSK                                    0x400000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_SSC_SDC_XPU_NON_SEC_INTR0_ENABLE_SHFT                                        0x16
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_GCC_XPU_NON_SEC_INTR0_ENABLE_BMSK                                        0x200000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_GCC_XPU_NON_SEC_INTR0_ENABLE_SHFT                                            0x15
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_MEMNOC_XPU_NON_SEC_INTR0_ENABLE_BMSK                                     0x100000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_MEMNOC_XPU_NON_SEC_INTR0_ENABLE_SHFT                                         0x14
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_QM_XPU_NON_SEC_INTR0_ENABLE_BMSK                                          0x80000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_QM_XPU_NON_SEC_INTR0_ENABLE_SHFT                                             0x13
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_QNM_SNOC_XPU_NON_SEC_INTR0_ENABLE_BMSK                                    0x40000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_QNM_SNOC_XPU_NON_SEC_INTR0_ENABLE_SHFT                                       0x12
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_QHS_CNOC_XPU_NON_SEC_INTR0_ENABLE_BMSK                                    0x20000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_QHS_CNOC_XPU_NON_SEC_INTR0_ENABLE_SHFT                                       0x11
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_QHM_AOSS_XPU_NON_SEC_INTR0_ENABLE_BMSK                                    0x10000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_QHM_AOSS_XPU_NON_SEC_INTR0_ENABLE_SHFT                                       0x10
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_SP_XPU_NON_SEC_INTR0_ENABLE_BMSK                                           0x8000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_SP_XPU_NON_SEC_INTR0_ENABLE_SHFT                                              0xf
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_PIMEM_MPU_XPU_NON_SEC_INTR0_ENABLE_BMSK                                    0x4000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_PIMEM_MPU_XPU_NON_SEC_INTR0_ENABLE_SHFT                                       0xe
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_PIMEM_APU_XPU_NON_SEC_INTR0_ENABLE_BMSK                                    0x2000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_PIMEM_APU_XPU_NON_SEC_INTR0_ENABLE_SHFT                                       0xd
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_SSC_Q6_XPU_NON_SEC_INTR0_ENABLE_BMSK                                       0x1000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_SSC_Q6_XPU_NON_SEC_INTR0_ENABLE_SHFT                                          0xc
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_SSC_XPU_NON_SEC_INTR0_ENABLE_BMSK                                           0x800
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_SSC_XPU_NON_SEC_INTR0_ENABLE_SHFT                                             0xb
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_SSC_QUP_XPU_NON_SEC_INTR0_ENABLE_BMSK                                       0x400
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_SSC_QUP_XPU_NON_SEC_INTR0_ENABLE_SHFT                                         0xa
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_SEC_CTRL_XPU_NON_SEC_INTR0_ENABLE_BMSK                                      0x200
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_SEC_CTRL_XPU_NON_SEC_INTR0_ENABLE_SHFT                                        0x9
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_DCC_XPU_NON_SEC_INTR0_ENABLE_BMSK                                           0x100
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_DCC_XPU_NON_SEC_INTR0_ENABLE_SHFT                                             0x8
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_OCIMEM_RPU_XPU_NON_SEC_INTR0_ENABLE_BMSK                                     0x80
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_OCIMEM_RPU_XPU_NON_SEC_INTR0_ENABLE_SHFT                                      0x7
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_CRYPTO0_XPU_NON_SEC_INTR0_ENABLE_BMSK                                        0x40
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_CRYPTO0_XPU_NON_SEC_INTR0_ENABLE_SHFT                                         0x6
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_TCSR_MUTEX_XPU_NON_SEC_INTR0_ENABLE_BMSK                                     0x20
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_TCSR_MUTEX_XPU_NON_SEC_INTR0_ENABLE_SHFT                                      0x5
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_QUPV3_1_XPU_NON_SEC_INTR0_ENABLE_BMSK                                        0x10
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_QUPV3_1_XPU_NON_SEC_INTR0_ENABLE_SHFT                                         0x4
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_TCSR_REGS_XPU_NON_SEC_INTR0_ENABLE_BMSK                                       0x8
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_TCSR_REGS_XPU_NON_SEC_INTR0_ENABLE_SHFT                                       0x3
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_QUPV3_0_XPU_NON_SEC_INTR0_ENABLE_BMSK                                         0x4
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_QUPV3_0_XPU_NON_SEC_INTR0_ENABLE_SHFT                                         0x2
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_AOSS_MPU_XPU_NON_SEC_INTR0_ENABLE_BMSK                                        0x2
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_AOSS_MPU_XPU_NON_SEC_INTR0_ENABLE_SHFT                                        0x1
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_PMIC_ARB_XPU_NON_SEC_INTR0_ENABLE_BMSK                                        0x1
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR0_ENABLE_PMIC_ARB_XPU_NON_SEC_INTR0_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_ADDR                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x00002044)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_PHYS                                                                   (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00002044)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_RMSK                                                                      0x7ffff
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_ADDR, HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_RMSK)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_ADDR, m)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_ADDR,v)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_ADDR,m,v,HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_IN)
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_RESERVE_50_BMSK                                                           0x40000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_RESERVE_50_SHFT                                                              0x12
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_RESERVE_49_BMSK                                                           0x20000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_RESERVE_49_SHFT                                                              0x11
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_RESERVE_48_BMSK                                                           0x10000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_RESERVE_48_SHFT                                                              0x10
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_TLMM_NORTH_XPU_NON_SEC_INTR1_ENABLE_BMSK                                   0x8000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_TLMM_NORTH_XPU_NON_SEC_INTR1_ENABLE_SHFT                                      0xf
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_RESERVE_46_BMSK                                                            0x4000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_RESERVE_46_SHFT                                                               0xe
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_RESERVE_45_BMSK                                                            0x2000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_RESERVE_45_SHFT                                                               0xd
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_QUPV3_2_XPU_NON_SEC_INTR1_ENABLE_BMSK                                      0x1000
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_QUPV3_2_XPU_NON_SEC_INTR1_ENABLE_SHFT                                         0xc
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_IPA_XPU_NON_SEC_INTR1_ENABLE_BMSK                                           0x800
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_IPA_XPU_NON_SEC_INTR1_ENABLE_SHFT                                             0xb
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_TLMM_EAST_XPU_NON_SEC_INTR1_ENABLE_BMSK                                     0x400
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_TLMM_EAST_XPU_NON_SEC_INTR1_ENABLE_SHFT                                       0xa
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_TLMM_SOUTH_XPU_NON_SEC_INTR1_ENABLE_BMSK                                    0x200
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_TLMM_SOUTH_XPU_NON_SEC_INTR1_ENABLE_SHFT                                      0x9
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_TLMM_WEST_XPU_NON_SEC_INTR1_ENABLE_BMSK                                     0x100
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_TLMM_WEST_XPU_NON_SEC_INTR1_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_MDSS_XPU_NON_SEC_INTR1_ENABLE_BMSK                                           0x80
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_MDSS_XPU_NON_SEC_INTR1_ENABLE_SHFT                                            0x7
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_UFS_CARD_ICE_XPU_NON_SEC_INTR1_ENABLE_BMSK                                   0x40
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_UFS_CARD_ICE_XPU_NON_SEC_INTR1_ENABLE_SHFT                                    0x6
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_TITAN_XPU_NON_SEC_INTR1_ENABLE_BMSK                                          0x20
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_TITAN_XPU_NON_SEC_INTR1_ENABLE_SHFT                                           0x5
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_SPDM_XPU_NON_SEC_INTR1_ENABLE_BMSK                                           0x10
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_SPDM_XPU_NON_SEC_INTR1_ENABLE_SHFT                                            0x4
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_QXM_MSS_NAV_XPU_NON_SEC_INTR1_ENABLE_BMSK                                     0x8
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_QXM_MSS_NAV_XPU_NON_SEC_INTR1_ENABLE_SHFT                                     0x3
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_QNM_AGGRE2_XPU_NON_SEC_INTR1_ENABLE_BMSK                                      0x4
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_QNM_AGGRE2_XPU_NON_SEC_INTR1_ENABLE_SHFT                                      0x2
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_QNM_AGGRE1_XPU_NON_SEC_INTR1_ENABLE_BMSK                                      0x2
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_QNM_AGGRE1_XPU_NON_SEC_INTR1_ENABLE_SHFT                                      0x1
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_OCIMEM_XPU3_XPU_NON_SEC_INTR1_ENABLE_BMSK                                     0x1
#define HWIO_TCSR_SS_XPU_NON_SEC_INTR1_ENABLE_OCIMEM_XPU3_XPU_NON_SEC_INTR1_ENABLE_SHFT                                     0x0

#define HWIO_TCSR_SS_XPU_SEC_INTR0_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00004000)
#define HWIO_TCSR_SS_XPU_SEC_INTR0_PHYS                                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00004000)
#define HWIO_TCSR_SS_XPU_SEC_INTR0_RMSK                                                                              0xffffffff
#define HWIO_TCSR_SS_XPU_SEC_INTR0_IN          \
        in_dword_masked(HWIO_TCSR_SS_XPU_SEC_INTR0_ADDR, HWIO_TCSR_SS_XPU_SEC_INTR0_RMSK)
#define HWIO_TCSR_SS_XPU_SEC_INTR0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_XPU_SEC_INTR0_ADDR, m)
#define HWIO_TCSR_SS_XPU_SEC_INTR0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SEC_INTR0_BMSK                                0x80000000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SEC_INTR0_SHFT                                      0x1f
#define HWIO_TCSR_SS_XPU_SEC_INTR0_BOOT_ROM_XPU_SEC_INTR0_BMSK                                                       0x40000000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_BOOT_ROM_XPU_SEC_INTR0_SHFT                                                             0x1e
#define HWIO_TCSR_SS_XPU_SEC_INTR0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SEC_INTR0_BMSK                                    0x20000000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SEC_INTR0_SHFT                                          0x1d
#define HWIO_TCSR_SS_XPU_SEC_INTR0_LLCC3_XPU_SEC_INTR0_BMSK                                                          0x10000000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_LLCC3_XPU_SEC_INTR0_SHFT                                                                0x1c
#define HWIO_TCSR_SS_XPU_SEC_INTR0_LLCC2_XPU_SEC_INTR0_BMSK                                                           0x8000000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_LLCC2_XPU_SEC_INTR0_SHFT                                                                0x1b
#define HWIO_TCSR_SS_XPU_SEC_INTR0_LLCC1_XPU_SEC_INTR0_BMSK                                                           0x4000000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_LLCC1_XPU_SEC_INTR0_SHFT                                                                0x1a
#define HWIO_TCSR_SS_XPU_SEC_INTR0_LLCC0_XPU_SEC_INTR0_BMSK                                                           0x2000000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_LLCC0_XPU_SEC_INTR0_SHFT                                                                0x19
#define HWIO_TCSR_SS_XPU_SEC_INTR0_UFS_XPU_SEC_INTR0_BMSK                                                             0x1000000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_UFS_XPU_SEC_INTR0_SHFT                                                                  0x18
#define HWIO_TCSR_SS_XPU_SEC_INTR0_QXS_BOOT_IMEM_SS_MPU_XPU_SEC_INTR0_BMSK                                             0x800000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_QXS_BOOT_IMEM_SS_MPU_XPU_SEC_INTR0_SHFT                                                 0x17
#define HWIO_TCSR_SS_XPU_SEC_INTR0_SSC_SDC_XPU_SEC_INTR0_BMSK                                                          0x400000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_SSC_SDC_XPU_SEC_INTR0_SHFT                                                              0x16
#define HWIO_TCSR_SS_XPU_SEC_INTR0_GCC_XPU_SEC_INTR0_BMSK                                                              0x200000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_GCC_XPU_SEC_INTR0_SHFT                                                                  0x15
#define HWIO_TCSR_SS_XPU_SEC_INTR0_MEMNOC_XPU_SEC_INTR0_BMSK                                                           0x100000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_MEMNOC_XPU_SEC_INTR0_SHFT                                                               0x14
#define HWIO_TCSR_SS_XPU_SEC_INTR0_QM_XPU_SEC_INTR0_BMSK                                                                0x80000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_QM_XPU_SEC_INTR0_SHFT                                                                   0x13
#define HWIO_TCSR_SS_XPU_SEC_INTR0_QNM_SNOC_XPU_SEC_INTR0_BMSK                                                          0x40000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_QNM_SNOC_XPU_SEC_INTR0_SHFT                                                             0x12
#define HWIO_TCSR_SS_XPU_SEC_INTR0_QHS_CNOC_XPU_SEC_INTR0_BMSK                                                          0x20000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_QHS_CNOC_XPU_SEC_INTR0_SHFT                                                             0x11
#define HWIO_TCSR_SS_XPU_SEC_INTR0_QHM_AOSS_XPU_SEC_INTR0_BMSK                                                          0x10000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_QHM_AOSS_XPU_SEC_INTR0_SHFT                                                             0x10
#define HWIO_TCSR_SS_XPU_SEC_INTR0_SP_XPU_SEC_INTR0_BMSK                                                                 0x8000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_SP_XPU_SEC_INTR0_SHFT                                                                    0xf
#define HWIO_TCSR_SS_XPU_SEC_INTR0_PIMEM_MPU_XPU_SEC_INTR0_BMSK                                                          0x4000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_PIMEM_MPU_XPU_SEC_INTR0_SHFT                                                             0xe
#define HWIO_TCSR_SS_XPU_SEC_INTR0_PIMEM_APU_XPU_SEC_INTR0_BMSK                                                          0x2000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_PIMEM_APU_XPU_SEC_INTR0_SHFT                                                             0xd
#define HWIO_TCSR_SS_XPU_SEC_INTR0_SSC_Q6_XPU_SEC_INTR0_BMSK                                                             0x1000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_SSC_Q6_XPU_SEC_INTR0_SHFT                                                                0xc
#define HWIO_TCSR_SS_XPU_SEC_INTR0_SSC_XPU_SEC_INTR0_BMSK                                                                 0x800
#define HWIO_TCSR_SS_XPU_SEC_INTR0_SSC_XPU_SEC_INTR0_SHFT                                                                   0xb
#define HWIO_TCSR_SS_XPU_SEC_INTR0_SSC_QUP_XPU_SEC_INTR0_BMSK                                                             0x400
#define HWIO_TCSR_SS_XPU_SEC_INTR0_SSC_QUP_XPU_SEC_INTR0_SHFT                                                               0xa
#define HWIO_TCSR_SS_XPU_SEC_INTR0_SEC_CTRL_XPU_SEC_INTR0_BMSK                                                            0x200
#define HWIO_TCSR_SS_XPU_SEC_INTR0_SEC_CTRL_XPU_SEC_INTR0_SHFT                                                              0x9
#define HWIO_TCSR_SS_XPU_SEC_INTR0_DCC_XPU_SEC_INTR0_BMSK                                                                 0x100
#define HWIO_TCSR_SS_XPU_SEC_INTR0_DCC_XPU_SEC_INTR0_SHFT                                                                   0x8
#define HWIO_TCSR_SS_XPU_SEC_INTR0_OCIMEM_RPU_XPU_SEC_INTR0_BMSK                                                           0x80
#define HWIO_TCSR_SS_XPU_SEC_INTR0_OCIMEM_RPU_XPU_SEC_INTR0_SHFT                                                            0x7
#define HWIO_TCSR_SS_XPU_SEC_INTR0_CRYPTO0_XPU_SEC_INTR0_BMSK                                                              0x40
#define HWIO_TCSR_SS_XPU_SEC_INTR0_CRYPTO0_XPU_SEC_INTR0_SHFT                                                               0x6
#define HWIO_TCSR_SS_XPU_SEC_INTR0_TCSR_MUTEX_XPU_SEC_INTR0_BMSK                                                           0x20
#define HWIO_TCSR_SS_XPU_SEC_INTR0_TCSR_MUTEX_XPU_SEC_INTR0_SHFT                                                            0x5
#define HWIO_TCSR_SS_XPU_SEC_INTR0_QUPV3_1_XPU_SEC_INTR0_BMSK                                                              0x10
#define HWIO_TCSR_SS_XPU_SEC_INTR0_QUPV3_1_XPU_SEC_INTR0_SHFT                                                               0x4
#define HWIO_TCSR_SS_XPU_SEC_INTR0_TCSR_REGS_XPU_SEC_INTR0_BMSK                                                             0x8
#define HWIO_TCSR_SS_XPU_SEC_INTR0_TCSR_REGS_XPU_SEC_INTR0_SHFT                                                             0x3
#define HWIO_TCSR_SS_XPU_SEC_INTR0_QUPV3_0_XPU_SEC_INTR0_BMSK                                                               0x4
#define HWIO_TCSR_SS_XPU_SEC_INTR0_QUPV3_0_XPU_SEC_INTR0_SHFT                                                               0x2
#define HWIO_TCSR_SS_XPU_SEC_INTR0_AOSS_MPU_XPU_SEC_INTR0_BMSK                                                              0x2
#define HWIO_TCSR_SS_XPU_SEC_INTR0_AOSS_MPU_XPU_SEC_INTR0_SHFT                                                              0x1
#define HWIO_TCSR_SS_XPU_SEC_INTR0_PMIC_ARB_XPU_SEC_INTR0_BMSK                                                              0x1
#define HWIO_TCSR_SS_XPU_SEC_INTR0_PMIC_ARB_XPU_SEC_INTR0_SHFT                                                              0x0

#define HWIO_TCSR_SS_XPU_SEC_INTR1_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00004004)
#define HWIO_TCSR_SS_XPU_SEC_INTR1_PHYS                                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00004004)
#define HWIO_TCSR_SS_XPU_SEC_INTR1_RMSK                                                                                 0x7ffff
#define HWIO_TCSR_SS_XPU_SEC_INTR1_IN          \
        in_dword_masked(HWIO_TCSR_SS_XPU_SEC_INTR1_ADDR, HWIO_TCSR_SS_XPU_SEC_INTR1_RMSK)
#define HWIO_TCSR_SS_XPU_SEC_INTR1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_XPU_SEC_INTR1_ADDR, m)
#define HWIO_TCSR_SS_XPU_SEC_INTR1_RESERVE_50_BMSK                                                                      0x40000
#define HWIO_TCSR_SS_XPU_SEC_INTR1_RESERVE_50_SHFT                                                                         0x12
#define HWIO_TCSR_SS_XPU_SEC_INTR1_RESERVE_49_BMSK                                                                      0x20000
#define HWIO_TCSR_SS_XPU_SEC_INTR1_RESERVE_49_SHFT                                                                         0x11
#define HWIO_TCSR_SS_XPU_SEC_INTR1_RESERVE_48_BMSK                                                                      0x10000
#define HWIO_TCSR_SS_XPU_SEC_INTR1_RESERVE_48_SHFT                                                                         0x10
#define HWIO_TCSR_SS_XPU_SEC_INTR1_TLMM_NORTH_XPU_SEC_INTR1_BMSK                                                         0x8000
#define HWIO_TCSR_SS_XPU_SEC_INTR1_TLMM_NORTH_XPU_SEC_INTR1_SHFT                                                            0xf
#define HWIO_TCSR_SS_XPU_SEC_INTR1_RESERVE_46_BMSK                                                                       0x4000
#define HWIO_TCSR_SS_XPU_SEC_INTR1_RESERVE_46_SHFT                                                                          0xe
#define HWIO_TCSR_SS_XPU_SEC_INTR1_RESERVE_45_BMSK                                                                       0x2000
#define HWIO_TCSR_SS_XPU_SEC_INTR1_RESERVE_45_SHFT                                                                          0xd
#define HWIO_TCSR_SS_XPU_SEC_INTR1_QUPV3_2_XPU_SEC_INTR1_BMSK                                                            0x1000
#define HWIO_TCSR_SS_XPU_SEC_INTR1_QUPV3_2_XPU_SEC_INTR1_SHFT                                                               0xc
#define HWIO_TCSR_SS_XPU_SEC_INTR1_IPA_XPU_SEC_INTR1_BMSK                                                                 0x800
#define HWIO_TCSR_SS_XPU_SEC_INTR1_IPA_XPU_SEC_INTR1_SHFT                                                                   0xb
#define HWIO_TCSR_SS_XPU_SEC_INTR1_TLMM_EAST_XPU_SEC_INTR1_BMSK                                                           0x400
#define HWIO_TCSR_SS_XPU_SEC_INTR1_TLMM_EAST_XPU_SEC_INTR1_SHFT                                                             0xa
#define HWIO_TCSR_SS_XPU_SEC_INTR1_TLMM_SOUTH_XPU_SEC_INTR1_BMSK                                                          0x200
#define HWIO_TCSR_SS_XPU_SEC_INTR1_TLMM_SOUTH_XPU_SEC_INTR1_SHFT                                                            0x9
#define HWIO_TCSR_SS_XPU_SEC_INTR1_TLMM_WEST_XPU_SEC_INTR1_BMSK                                                           0x100
#define HWIO_TCSR_SS_XPU_SEC_INTR1_TLMM_WEST_XPU_SEC_INTR1_SHFT                                                             0x8
#define HWIO_TCSR_SS_XPU_SEC_INTR1_MDSS_XPU_SEC_INTR1_BMSK                                                                 0x80
#define HWIO_TCSR_SS_XPU_SEC_INTR1_MDSS_XPU_SEC_INTR1_SHFT                                                                  0x7
#define HWIO_TCSR_SS_XPU_SEC_INTR1_UFS_CARD_ICE_XPU_SEC_INTR1_BMSK                                                         0x40
#define HWIO_TCSR_SS_XPU_SEC_INTR1_UFS_CARD_ICE_XPU_SEC_INTR1_SHFT                                                          0x6
#define HWIO_TCSR_SS_XPU_SEC_INTR1_TITAN_XPU_SEC_INTR1_BMSK                                                                0x20
#define HWIO_TCSR_SS_XPU_SEC_INTR1_TITAN_XPU_SEC_INTR1_SHFT                                                                 0x5
#define HWIO_TCSR_SS_XPU_SEC_INTR1_SPDM_XPU_SEC_INTR1_BMSK                                                                 0x10
#define HWIO_TCSR_SS_XPU_SEC_INTR1_SPDM_XPU_SEC_INTR1_SHFT                                                                  0x4
#define HWIO_TCSR_SS_XPU_SEC_INTR1_QXM_MSS_NAV_XPU_SEC_INTR1_BMSK                                                           0x8
#define HWIO_TCSR_SS_XPU_SEC_INTR1_QXM_MSS_NAV_XPU_SEC_INTR1_SHFT                                                           0x3
#define HWIO_TCSR_SS_XPU_SEC_INTR1_QNM_AGGRE2_XPU_SEC_INTR1_BMSK                                                            0x4
#define HWIO_TCSR_SS_XPU_SEC_INTR1_QNM_AGGRE2_XPU_SEC_INTR1_SHFT                                                            0x2
#define HWIO_TCSR_SS_XPU_SEC_INTR1_QNM_AGGRE1_XPU_SEC_INTR1_BMSK                                                            0x2
#define HWIO_TCSR_SS_XPU_SEC_INTR1_QNM_AGGRE1_XPU_SEC_INTR1_SHFT                                                            0x1
#define HWIO_TCSR_SS_XPU_SEC_INTR1_OCIMEM_XPU3_XPU_SEC_INTR1_BMSK                                                           0x1
#define HWIO_TCSR_SS_XPU_SEC_INTR1_OCIMEM_XPU3_XPU_SEC_INTR1_SHFT                                                           0x0

#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_ADDR                                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x00004040)
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_PHYS                                                                       (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00004040)
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_RMSK                                                                       0xffffffff
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_ADDR, HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_RMSK)
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_ADDR, m)
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_ADDR,v)
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_ADDR,m,v,HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_IN)
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SEC_INTR0_ENABLE_BMSK                  0x80000000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SEC_INTR0_ENABLE_SHFT                        0x1f
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_BOOT_ROM_XPU_SEC_INTR0_ENABLE_BMSK                                         0x40000000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_BOOT_ROM_XPU_SEC_INTR0_ENABLE_SHFT                                               0x1e
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SEC_INTR0_ENABLE_BMSK                      0x20000000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SEC_INTR0_ENABLE_SHFT                            0x1d
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_LLCC3_XPU_SEC_INTR0_ENABLE_BMSK                                            0x10000000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_LLCC3_XPU_SEC_INTR0_ENABLE_SHFT                                                  0x1c
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_LLCC2_XPU_SEC_INTR0_ENABLE_BMSK                                             0x8000000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_LLCC2_XPU_SEC_INTR0_ENABLE_SHFT                                                  0x1b
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_LLCC1_XPU_SEC_INTR0_ENABLE_BMSK                                             0x4000000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_LLCC1_XPU_SEC_INTR0_ENABLE_SHFT                                                  0x1a
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_LLCC0_XPU_SEC_INTR0_ENABLE_BMSK                                             0x2000000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_LLCC0_XPU_SEC_INTR0_ENABLE_SHFT                                                  0x19
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_UFS_XPU_SEC_INTR0_ENABLE_BMSK                                               0x1000000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_UFS_XPU_SEC_INTR0_ENABLE_SHFT                                                    0x18
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_QXS_BOOT_IMEM_SS_MPU_XPU_SEC_INTR0_ENABLE_BMSK                               0x800000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_QXS_BOOT_IMEM_SS_MPU_XPU_SEC_INTR0_ENABLE_SHFT                                   0x17
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_SSC_SDC_XPU_SEC_INTR0_ENABLE_BMSK                                            0x400000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_SSC_SDC_XPU_SEC_INTR0_ENABLE_SHFT                                                0x16
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_GCC_XPU_SEC_INTR0_ENABLE_BMSK                                                0x200000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_GCC_XPU_SEC_INTR0_ENABLE_SHFT                                                    0x15
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_MEMNOC_XPU_SEC_INTR0_ENABLE_BMSK                                             0x100000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_MEMNOC_XPU_SEC_INTR0_ENABLE_SHFT                                                 0x14
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_QM_XPU_SEC_INTR0_ENABLE_BMSK                                                  0x80000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_QM_XPU_SEC_INTR0_ENABLE_SHFT                                                     0x13
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_QNM_SNOC_XPU_SEC_INTR0_ENABLE_BMSK                                            0x40000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_QNM_SNOC_XPU_SEC_INTR0_ENABLE_SHFT                                               0x12
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_QHS_CNOC_XPU_SEC_INTR0_ENABLE_BMSK                                            0x20000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_QHS_CNOC_XPU_SEC_INTR0_ENABLE_SHFT                                               0x11
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_QHM_AOSS_XPU_SEC_INTR0_ENABLE_BMSK                                            0x10000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_QHM_AOSS_XPU_SEC_INTR0_ENABLE_SHFT                                               0x10
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_SP_XPU_SEC_INTR0_ENABLE_BMSK                                                   0x8000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_SP_XPU_SEC_INTR0_ENABLE_SHFT                                                      0xf
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_PIMEM_MPU_XPU_SEC_INTR0_ENABLE_BMSK                                            0x4000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_PIMEM_MPU_XPU_SEC_INTR0_ENABLE_SHFT                                               0xe
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_PIMEM_APU_XPU_SEC_INTR0_ENABLE_BMSK                                            0x2000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_PIMEM_APU_XPU_SEC_INTR0_ENABLE_SHFT                                               0xd
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_SSC_Q6_XPU_SEC_INTR0_ENABLE_BMSK                                               0x1000
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_SSC_Q6_XPU_SEC_INTR0_ENABLE_SHFT                                                  0xc
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_SSC_XPU_SEC_INTR0_ENABLE_BMSK                                                   0x800
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_SSC_XPU_SEC_INTR0_ENABLE_SHFT                                                     0xb
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_SSC_QUP_XPU_SEC_INTR0_ENABLE_BMSK                                               0x400
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_SSC_QUP_XPU_SEC_INTR0_ENABLE_SHFT                                                 0xa
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_SEC_CTRL_XPU_SEC_INTR0_ENABLE_BMSK                                              0x200
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_SEC_CTRL_XPU_SEC_INTR0_ENABLE_SHFT                                                0x9
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_DCC_XPU_SEC_INTR0_ENABLE_BMSK                                                   0x100
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_DCC_XPU_SEC_INTR0_ENABLE_SHFT                                                     0x8
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_OCIMEM_RPU_XPU_SEC_INTR0_ENABLE_BMSK                                             0x80
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_OCIMEM_RPU_XPU_SEC_INTR0_ENABLE_SHFT                                              0x7
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_CRYPTO0_XPU_SEC_INTR0_ENABLE_BMSK                                                0x40
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_CRYPTO0_XPU_SEC_INTR0_ENABLE_SHFT                                                 0x6
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_TCSR_MUTEX_XPU_SEC_INTR0_ENABLE_BMSK                                             0x20
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_TCSR_MUTEX_XPU_SEC_INTR0_ENABLE_SHFT                                              0x5
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_QUPV3_1_XPU_SEC_INTR0_ENABLE_BMSK                                                0x10
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_QUPV3_1_XPU_SEC_INTR0_ENABLE_SHFT                                                 0x4
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_TCSR_REGS_XPU_SEC_INTR0_ENABLE_BMSK                                               0x8
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_TCSR_REGS_XPU_SEC_INTR0_ENABLE_SHFT                                               0x3
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_QUPV3_0_XPU_SEC_INTR0_ENABLE_BMSK                                                 0x4
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_QUPV3_0_XPU_SEC_INTR0_ENABLE_SHFT                                                 0x2
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_AOSS_MPU_XPU_SEC_INTR0_ENABLE_BMSK                                                0x2
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_AOSS_MPU_XPU_SEC_INTR0_ENABLE_SHFT                                                0x1
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_PMIC_ARB_XPU_SEC_INTR0_ENABLE_BMSK                                                0x1
#define HWIO_TCSR_SS_XPU_SEC_INTR0_ENABLE_PMIC_ARB_XPU_SEC_INTR0_ENABLE_SHFT                                                0x0

#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_ADDR                                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x00004044)
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_PHYS                                                                       (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00004044)
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_RMSK                                                                          0x7ffff
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_ADDR, HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_RMSK)
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_ADDR, m)
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_ADDR,v)
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_ADDR,m,v,HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_IN)
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_RESERVE_50_BMSK                                                               0x40000
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_RESERVE_50_SHFT                                                                  0x12
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_RESERVE_49_BMSK                                                               0x20000
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_RESERVE_49_SHFT                                                                  0x11
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_RESERVE_48_BMSK                                                               0x10000
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_RESERVE_48_SHFT                                                                  0x10
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_TLMM_NORTH_XPU_SEC_INTR1_ENABLE_BMSK                                           0x8000
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_TLMM_NORTH_XPU_SEC_INTR1_ENABLE_SHFT                                              0xf
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_RESERVE_46_BMSK                                                                0x4000
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_RESERVE_46_SHFT                                                                   0xe
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_RESERVE_45_BMSK                                                                0x2000
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_RESERVE_45_SHFT                                                                   0xd
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_QUPV3_2_XPU_SEC_INTR1_ENABLE_BMSK                                              0x1000
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_QUPV3_2_XPU_SEC_INTR1_ENABLE_SHFT                                                 0xc
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_IPA_XPU_SEC_INTR1_ENABLE_BMSK                                                   0x800
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_IPA_XPU_SEC_INTR1_ENABLE_SHFT                                                     0xb
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_TLMM_EAST_XPU_SEC_INTR1_ENABLE_BMSK                                             0x400
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_TLMM_EAST_XPU_SEC_INTR1_ENABLE_SHFT                                               0xa
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_TLMM_SOUTH_XPU_SEC_INTR1_ENABLE_BMSK                                            0x200
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_TLMM_SOUTH_XPU_SEC_INTR1_ENABLE_SHFT                                              0x9
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_TLMM_WEST_XPU_SEC_INTR1_ENABLE_BMSK                                             0x100
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_TLMM_WEST_XPU_SEC_INTR1_ENABLE_SHFT                                               0x8
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_MDSS_XPU_SEC_INTR1_ENABLE_BMSK                                                   0x80
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_MDSS_XPU_SEC_INTR1_ENABLE_SHFT                                                    0x7
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_UFS_CARD_ICE_XPU_SEC_INTR1_ENABLE_BMSK                                           0x40
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_UFS_CARD_ICE_XPU_SEC_INTR1_ENABLE_SHFT                                            0x6
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_TITAN_XPU_SEC_INTR1_ENABLE_BMSK                                                  0x20
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_TITAN_XPU_SEC_INTR1_ENABLE_SHFT                                                   0x5
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_SPDM_XPU_SEC_INTR1_ENABLE_BMSK                                                   0x10
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_SPDM_XPU_SEC_INTR1_ENABLE_SHFT                                                    0x4
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_QXM_MSS_NAV_XPU_SEC_INTR1_ENABLE_BMSK                                             0x8
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_QXM_MSS_NAV_XPU_SEC_INTR1_ENABLE_SHFT                                             0x3
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_QNM_AGGRE2_XPU_SEC_INTR1_ENABLE_BMSK                                              0x4
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_QNM_AGGRE2_XPU_SEC_INTR1_ENABLE_SHFT                                              0x2
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_QNM_AGGRE1_XPU_SEC_INTR1_ENABLE_BMSK                                              0x2
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_QNM_AGGRE1_XPU_SEC_INTR1_ENABLE_SHFT                                              0x1
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_OCIMEM_XPU3_XPU_SEC_INTR1_ENABLE_BMSK                                             0x1
#define HWIO_TCSR_SS_XPU_SEC_INTR1_ENABLE_OCIMEM_XPU3_XPU_SEC_INTR1_ENABLE_SHFT                                             0x0

#define HWIO_TCSR_SS_XPU_MSA_INTR0_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00006000)
#define HWIO_TCSR_SS_XPU_MSA_INTR0_PHYS                                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00006000)
#define HWIO_TCSR_SS_XPU_MSA_INTR0_RMSK                                                                              0xffffffff
#define HWIO_TCSR_SS_XPU_MSA_INTR0_IN          \
        in_dword_masked(HWIO_TCSR_SS_XPU_MSA_INTR0_ADDR, HWIO_TCSR_SS_XPU_MSA_INTR0_RMSK)
#define HWIO_TCSR_SS_XPU_MSA_INTR0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_XPU_MSA_INTR0_ADDR, m)
#define HWIO_TCSR_SS_XPU_MSA_INTR0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_MSA_INTR0_BMSK                                0x80000000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_MSA_INTR0_SHFT                                      0x1f
#define HWIO_TCSR_SS_XPU_MSA_INTR0_BOOT_ROM_XPU_MSA_INTR0_BMSK                                                       0x40000000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_BOOT_ROM_XPU_MSA_INTR0_SHFT                                                             0x1e
#define HWIO_TCSR_SS_XPU_MSA_INTR0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_MSA_INTR0_BMSK                                    0x20000000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_MSA_INTR0_SHFT                                          0x1d
#define HWIO_TCSR_SS_XPU_MSA_INTR0_LLCC3_XPU_MSA_INTR0_BMSK                                                          0x10000000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_LLCC3_XPU_MSA_INTR0_SHFT                                                                0x1c
#define HWIO_TCSR_SS_XPU_MSA_INTR0_LLCC2_XPU_MSA_INTR0_BMSK                                                           0x8000000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_LLCC2_XPU_MSA_INTR0_SHFT                                                                0x1b
#define HWIO_TCSR_SS_XPU_MSA_INTR0_LLCC1_XPU_MSA_INTR0_BMSK                                                           0x4000000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_LLCC1_XPU_MSA_INTR0_SHFT                                                                0x1a
#define HWIO_TCSR_SS_XPU_MSA_INTR0_LLCC0_XPU_MSA_INTR0_BMSK                                                           0x2000000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_LLCC0_XPU_MSA_INTR0_SHFT                                                                0x19
#define HWIO_TCSR_SS_XPU_MSA_INTR0_UFS_XPU_MSA_INTR0_BMSK                                                             0x1000000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_UFS_XPU_MSA_INTR0_SHFT                                                                  0x18
#define HWIO_TCSR_SS_XPU_MSA_INTR0_QXS_BOOT_IMEM_SS_MPU_XPU_MSA_INTR0_BMSK                                             0x800000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_QXS_BOOT_IMEM_SS_MPU_XPU_MSA_INTR0_SHFT                                                 0x17
#define HWIO_TCSR_SS_XPU_MSA_INTR0_SSC_SDC_XPU_MSA_INTR0_BMSK                                                          0x400000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_SSC_SDC_XPU_MSA_INTR0_SHFT                                                              0x16
#define HWIO_TCSR_SS_XPU_MSA_INTR0_GCC_XPU_MSA_INTR0_BMSK                                                              0x200000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_GCC_XPU_MSA_INTR0_SHFT                                                                  0x15
#define HWIO_TCSR_SS_XPU_MSA_INTR0_MEMNOC_XPU_MSA_INTR0_BMSK                                                           0x100000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_MEMNOC_XPU_MSA_INTR0_SHFT                                                               0x14
#define HWIO_TCSR_SS_XPU_MSA_INTR0_QM_XPU_MSA_INTR0_BMSK                                                                0x80000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_QM_XPU_MSA_INTR0_SHFT                                                                   0x13
#define HWIO_TCSR_SS_XPU_MSA_INTR0_QNM_SNOC_XPU_MSA_INTR0_BMSK                                                          0x40000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_QNM_SNOC_XPU_MSA_INTR0_SHFT                                                             0x12
#define HWIO_TCSR_SS_XPU_MSA_INTR0_QHS_CNOC_XPU_MSA_INTR0_BMSK                                                          0x20000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_QHS_CNOC_XPU_MSA_INTR0_SHFT                                                             0x11
#define HWIO_TCSR_SS_XPU_MSA_INTR0_QHM_AOSS_XPU_MSA_INTR0_BMSK                                                          0x10000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_QHM_AOSS_XPU_MSA_INTR0_SHFT                                                             0x10
#define HWIO_TCSR_SS_XPU_MSA_INTR0_SP_XPU_MSA_INTR0_BMSK                                                                 0x8000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_SP_XPU_MSA_INTR0_SHFT                                                                    0xf
#define HWIO_TCSR_SS_XPU_MSA_INTR0_PIMEM_MPU_XPU_MSA_INTR0_BMSK                                                          0x4000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_PIMEM_MPU_XPU_MSA_INTR0_SHFT                                                             0xe
#define HWIO_TCSR_SS_XPU_MSA_INTR0_PIMEM_APU_XPU_MSA_INTR0_BMSK                                                          0x2000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_PIMEM_APU_XPU_MSA_INTR0_SHFT                                                             0xd
#define HWIO_TCSR_SS_XPU_MSA_INTR0_SSC_Q6_XPU_MSA_INTR0_BMSK                                                             0x1000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_SSC_Q6_XPU_MSA_INTR0_SHFT                                                                0xc
#define HWIO_TCSR_SS_XPU_MSA_INTR0_SSC_XPU_MSA_INTR0_BMSK                                                                 0x800
#define HWIO_TCSR_SS_XPU_MSA_INTR0_SSC_XPU_MSA_INTR0_SHFT                                                                   0xb
#define HWIO_TCSR_SS_XPU_MSA_INTR0_SSC_QUP_XPU_MSA_INTR0_BMSK                                                             0x400
#define HWIO_TCSR_SS_XPU_MSA_INTR0_SSC_QUP_XPU_MSA_INTR0_SHFT                                                               0xa
#define HWIO_TCSR_SS_XPU_MSA_INTR0_SEC_CTRL_XPU_MSA_INTR0_BMSK                                                            0x200
#define HWIO_TCSR_SS_XPU_MSA_INTR0_SEC_CTRL_XPU_MSA_INTR0_SHFT                                                              0x9
#define HWIO_TCSR_SS_XPU_MSA_INTR0_DCC_XPU_MSA_INTR0_BMSK                                                                 0x100
#define HWIO_TCSR_SS_XPU_MSA_INTR0_DCC_XPU_MSA_INTR0_SHFT                                                                   0x8
#define HWIO_TCSR_SS_XPU_MSA_INTR0_OCIMEM_RPU_XPU_MSA_INTR0_BMSK                                                           0x80
#define HWIO_TCSR_SS_XPU_MSA_INTR0_OCIMEM_RPU_XPU_MSA_INTR0_SHFT                                                            0x7
#define HWIO_TCSR_SS_XPU_MSA_INTR0_CRYPTO0_XPU_MSA_INTR0_BMSK                                                              0x40
#define HWIO_TCSR_SS_XPU_MSA_INTR0_CRYPTO0_XPU_MSA_INTR0_SHFT                                                               0x6
#define HWIO_TCSR_SS_XPU_MSA_INTR0_TCSR_MUTEX_XPU_MSA_INTR0_BMSK                                                           0x20
#define HWIO_TCSR_SS_XPU_MSA_INTR0_TCSR_MUTEX_XPU_MSA_INTR0_SHFT                                                            0x5
#define HWIO_TCSR_SS_XPU_MSA_INTR0_QUPV3_1_XPU_MSA_INTR0_BMSK                                                              0x10
#define HWIO_TCSR_SS_XPU_MSA_INTR0_QUPV3_1_XPU_MSA_INTR0_SHFT                                                               0x4
#define HWIO_TCSR_SS_XPU_MSA_INTR0_TCSR_REGS_XPU_MSA_INTR0_BMSK                                                             0x8
#define HWIO_TCSR_SS_XPU_MSA_INTR0_TCSR_REGS_XPU_MSA_INTR0_SHFT                                                             0x3
#define HWIO_TCSR_SS_XPU_MSA_INTR0_QUPV3_0_XPU_MSA_INTR0_BMSK                                                               0x4
#define HWIO_TCSR_SS_XPU_MSA_INTR0_QUPV3_0_XPU_MSA_INTR0_SHFT                                                               0x2
#define HWIO_TCSR_SS_XPU_MSA_INTR0_AOSS_MPU_XPU_MSA_INTR0_BMSK                                                              0x2
#define HWIO_TCSR_SS_XPU_MSA_INTR0_AOSS_MPU_XPU_MSA_INTR0_SHFT                                                              0x1
#define HWIO_TCSR_SS_XPU_MSA_INTR0_PMIC_ARB_XPU_MSA_INTR0_BMSK                                                              0x1
#define HWIO_TCSR_SS_XPU_MSA_INTR0_PMIC_ARB_XPU_MSA_INTR0_SHFT                                                              0x0

#define HWIO_TCSR_SS_XPU_MSA_INTR1_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00006004)
#define HWIO_TCSR_SS_XPU_MSA_INTR1_PHYS                                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00006004)
#define HWIO_TCSR_SS_XPU_MSA_INTR1_RMSK                                                                                 0x7ffff
#define HWIO_TCSR_SS_XPU_MSA_INTR1_IN          \
        in_dword_masked(HWIO_TCSR_SS_XPU_MSA_INTR1_ADDR, HWIO_TCSR_SS_XPU_MSA_INTR1_RMSK)
#define HWIO_TCSR_SS_XPU_MSA_INTR1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_XPU_MSA_INTR1_ADDR, m)
#define HWIO_TCSR_SS_XPU_MSA_INTR1_RESERVE_50_BMSK                                                                      0x40000
#define HWIO_TCSR_SS_XPU_MSA_INTR1_RESERVE_50_SHFT                                                                         0x12
#define HWIO_TCSR_SS_XPU_MSA_INTR1_RESERVE_49_BMSK                                                                      0x20000
#define HWIO_TCSR_SS_XPU_MSA_INTR1_RESERVE_49_SHFT                                                                         0x11
#define HWIO_TCSR_SS_XPU_MSA_INTR1_RESERVE_48_BMSK                                                                      0x10000
#define HWIO_TCSR_SS_XPU_MSA_INTR1_RESERVE_48_SHFT                                                                         0x10
#define HWIO_TCSR_SS_XPU_MSA_INTR1_TLMM_NORTH_XPU_MSA_INTR1_BMSK                                                         0x8000
#define HWIO_TCSR_SS_XPU_MSA_INTR1_TLMM_NORTH_XPU_MSA_INTR1_SHFT                                                            0xf
#define HWIO_TCSR_SS_XPU_MSA_INTR1_RESERVE_46_BMSK                                                                       0x4000
#define HWIO_TCSR_SS_XPU_MSA_INTR1_RESERVE_46_SHFT                                                                          0xe
#define HWIO_TCSR_SS_XPU_MSA_INTR1_RESERVE_45_BMSK                                                                       0x2000
#define HWIO_TCSR_SS_XPU_MSA_INTR1_RESERVE_45_SHFT                                                                          0xd
#define HWIO_TCSR_SS_XPU_MSA_INTR1_QUPV3_2_XPU_MSA_INTR1_BMSK                                                            0x1000
#define HWIO_TCSR_SS_XPU_MSA_INTR1_QUPV3_2_XPU_MSA_INTR1_SHFT                                                               0xc
#define HWIO_TCSR_SS_XPU_MSA_INTR1_IPA_XPU_MSA_INTR1_BMSK                                                                 0x800
#define HWIO_TCSR_SS_XPU_MSA_INTR1_IPA_XPU_MSA_INTR1_SHFT                                                                   0xb
#define HWIO_TCSR_SS_XPU_MSA_INTR1_TLMM_EAST_XPU_MSA_INTR1_BMSK                                                           0x400
#define HWIO_TCSR_SS_XPU_MSA_INTR1_TLMM_EAST_XPU_MSA_INTR1_SHFT                                                             0xa
#define HWIO_TCSR_SS_XPU_MSA_INTR1_TLMM_SOUTH_XPU_MSA_INTR1_BMSK                                                          0x200
#define HWIO_TCSR_SS_XPU_MSA_INTR1_TLMM_SOUTH_XPU_MSA_INTR1_SHFT                                                            0x9
#define HWIO_TCSR_SS_XPU_MSA_INTR1_TLMM_WEST_XPU_MSA_INTR1_BMSK                                                           0x100
#define HWIO_TCSR_SS_XPU_MSA_INTR1_TLMM_WEST_XPU_MSA_INTR1_SHFT                                                             0x8
#define HWIO_TCSR_SS_XPU_MSA_INTR1_MDSS_XPU_MSA_INTR1_BMSK                                                                 0x80
#define HWIO_TCSR_SS_XPU_MSA_INTR1_MDSS_XPU_MSA_INTR1_SHFT                                                                  0x7
#define HWIO_TCSR_SS_XPU_MSA_INTR1_UFS_CARD_ICE_XPU_MSA_INTR1_BMSK                                                         0x40
#define HWIO_TCSR_SS_XPU_MSA_INTR1_UFS_CARD_ICE_XPU_MSA_INTR1_SHFT                                                          0x6
#define HWIO_TCSR_SS_XPU_MSA_INTR1_TITAN_XPU_MSA_INTR1_BMSK                                                                0x20
#define HWIO_TCSR_SS_XPU_MSA_INTR1_TITAN_XPU_MSA_INTR1_SHFT                                                                 0x5
#define HWIO_TCSR_SS_XPU_MSA_INTR1_SPDM_XPU_MSA_INTR1_BMSK                                                                 0x10
#define HWIO_TCSR_SS_XPU_MSA_INTR1_SPDM_XPU_MSA_INTR1_SHFT                                                                  0x4
#define HWIO_TCSR_SS_XPU_MSA_INTR1_QXM_MSS_NAV_XPU_MSA_INTR1_BMSK                                                           0x8
#define HWIO_TCSR_SS_XPU_MSA_INTR1_QXM_MSS_NAV_XPU_MSA_INTR1_SHFT                                                           0x3
#define HWIO_TCSR_SS_XPU_MSA_INTR1_QNM_AGGRE2_XPU_MSA_INTR1_BMSK                                                            0x4
#define HWIO_TCSR_SS_XPU_MSA_INTR1_QNM_AGGRE2_XPU_MSA_INTR1_SHFT                                                            0x2
#define HWIO_TCSR_SS_XPU_MSA_INTR1_QNM_AGGRE1_XPU_MSA_INTR1_BMSK                                                            0x2
#define HWIO_TCSR_SS_XPU_MSA_INTR1_QNM_AGGRE1_XPU_MSA_INTR1_SHFT                                                            0x1
#define HWIO_TCSR_SS_XPU_MSA_INTR1_OCIMEM_XPU3_XPU_MSA_INTR1_BMSK                                                           0x1
#define HWIO_TCSR_SS_XPU_MSA_INTR1_OCIMEM_XPU3_XPU_MSA_INTR1_SHFT                                                           0x0

#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_ADDR                                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x00006040)
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_PHYS                                                                       (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00006040)
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_RMSK                                                                       0xffffffff
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_ADDR, HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_RMSK)
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_ADDR, m)
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_ADDR,v)
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_ADDR,m,v,HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_IN)
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_MSA_INTR0_ENABLE_BMSK                  0x80000000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_MSA_INTR0_ENABLE_SHFT                        0x1f
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_BOOT_ROM_XPU_MSA_INTR0_ENABLE_BMSK                                         0x40000000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_BOOT_ROM_XPU_MSA_INTR0_ENABLE_SHFT                                               0x1e
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_DTP_QHS_BROADCAST_MPU_MAINO_XPU_MSA_INTR0_ENABLE_BMSK                      0x20000000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_DTP_QHS_BROADCAST_MPU_MAINO_XPU_MSA_INTR0_ENABLE_SHFT                            0x1d
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_LLCC3_XPU_MSA_INTR0_ENABLE_BMSK                                            0x10000000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_LLCC3_XPU_MSA_INTR0_ENABLE_SHFT                                                  0x1c
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_LLCC2_XPU_MSA_INTR0_ENABLE_BMSK                                             0x8000000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_LLCC2_XPU_MSA_INTR0_ENABLE_SHFT                                                  0x1b
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_LLCC1_XPU_MSA_INTR0_ENABLE_BMSK                                             0x4000000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_LLCC1_XPU_MSA_INTR0_ENABLE_SHFT                                                  0x1a
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_LLCC0_XPU_MSA_INTR0_ENABLE_BMSK                                             0x2000000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_LLCC0_XPU_MSA_INTR0_ENABLE_SHFT                                                  0x19
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_UFS_XPU_MSA_INTR0_ENABLE_BMSK                                               0x1000000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_UFS_XPU_MSA_INTR0_ENABLE_SHFT                                                    0x18
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_QXS_BOOT_IMEM_SS_MPU_XPU_MSA_INTR0_ENABLE_BMSK                               0x800000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_QXS_BOOT_IMEM_SS_MPU_XPU_MSA_INTR0_ENABLE_SHFT                                   0x17
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_SSC_SDC_XPU_MSA_INTR0_ENABLE_BMSK                                            0x400000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_SSC_SDC_XPU_MSA_INTR0_ENABLE_SHFT                                                0x16
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_GCC_XPU_MSA_INTR0_ENABLE_BMSK                                                0x200000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_GCC_XPU_MSA_INTR0_ENABLE_SHFT                                                    0x15
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_MEMNOC_XPU_MSA_INTR0_ENABLE_BMSK                                             0x100000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_MEMNOC_XPU_MSA_INTR0_ENABLE_SHFT                                                 0x14
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_QM_XPU_MSA_INTR0_ENABLE_BMSK                                                  0x80000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_QM_XPU_MSA_INTR0_ENABLE_SHFT                                                     0x13
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_QNM_SNOC_XPU_MSA_INTR0_ENABLE_BMSK                                            0x40000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_QNM_SNOC_XPU_MSA_INTR0_ENABLE_SHFT                                               0x12
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_QHS_CNOC_XPU_MSA_INTR0_ENABLE_BMSK                                            0x20000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_QHS_CNOC_XPU_MSA_INTR0_ENABLE_SHFT                                               0x11
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_QHM_AOSS_XPU_MSA_INTR0_ENABLE_BMSK                                            0x10000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_QHM_AOSS_XPU_MSA_INTR0_ENABLE_SHFT                                               0x10
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_SP_XPU_MSA_INTR0_ENABLE_BMSK                                                   0x8000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_SP_XPU_MSA_INTR0_ENABLE_SHFT                                                      0xf
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_PIMEM_MPU_XPU_MSA_INTR0_ENABLE_BMSK                                            0x4000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_PIMEM_MPU_XPU_MSA_INTR0_ENABLE_SHFT                                               0xe
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_PIMEM_APU_XPU_MSA_INTR0_ENABLE_BMSK                                            0x2000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_PIMEM_APU_XPU_MSA_INTR0_ENABLE_SHFT                                               0xd
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_SSC_Q6_XPU_MSA_INTR0_ENABLE_BMSK                                               0x1000
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_SSC_Q6_XPU_MSA_INTR0_ENABLE_SHFT                                                  0xc
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_SSC_XPU_MSA_INTR0_ENABLE_BMSK                                                   0x800
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_SSC_XPU_MSA_INTR0_ENABLE_SHFT                                                     0xb
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_SSC_QUP_XPU_MSA_INTR0_ENABLE_BMSK                                               0x400
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_SSC_QUP_XPU_MSA_INTR0_ENABLE_SHFT                                                 0xa
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_SEC_CTRL_XPU_MSA_INTR0_ENABLE_BMSK                                              0x200
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_SEC_CTRL_XPU_MSA_INTR0_ENABLE_SHFT                                                0x9
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_DCC_XPU_MSA_INTR0_ENABLE_BMSK                                                   0x100
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_DCC_XPU_MSA_INTR0_ENABLE_SHFT                                                     0x8
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_OCIMEM_RPU_XPU_MSA_INTR0_ENABLE_BMSK                                             0x80
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_OCIMEM_RPU_XPU_MSA_INTR0_ENABLE_SHFT                                              0x7
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_CRYPTO0_XPU_MSA_INTR0_ENABLE_BMSK                                                0x40
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_CRYPTO0_XPU_MSA_INTR0_ENABLE_SHFT                                                 0x6
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_TCSR_MUTEX_XPU_MSA_INTR0_ENABLE_BMSK                                             0x20
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_TCSR_MUTEX_XPU_MSA_INTR0_ENABLE_SHFT                                              0x5
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_QUPV3_1_XPU_MSA_INTR0_ENABLE_BMSK                                                0x10
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_QUPV3_1_XPU_MSA_INTR0_ENABLE_SHFT                                                 0x4
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_TCSR_REGS_XPU_MSA_INTR0_ENABLE_BMSK                                               0x8
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_TCSR_REGS_XPU_MSA_INTR0_ENABLE_SHFT                                               0x3
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_QUPV3_0_XPU_MSA_INTR0_ENABLE_BMSK                                                 0x4
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_QUPV3_0_XPU_MSA_INTR0_ENABLE_SHFT                                                 0x2
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_AOSS_MPU_XPU_MSA_INTR0_ENABLE_BMSK                                                0x2
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_AOSS_MPU_XPU_MSA_INTR0_ENABLE_SHFT                                                0x1
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_PMIC_ARB_XPU_MSA_INTR0_ENABLE_BMSK                                                0x1
#define HWIO_TCSR_SS_XPU_MSA_INTR0_ENABLE_PMIC_ARB_XPU_MSA_INTR0_ENABLE_SHFT                                                0x0

#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_ADDR                                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x00006044)
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_PHYS                                                                       (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00006044)
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_RMSK                                                                          0x7ffff
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_ADDR, HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_RMSK)
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_ADDR, m)
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_ADDR,v)
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_ADDR,m,v,HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_IN)
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_RESERVE_50_BMSK                                                               0x40000
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_RESERVE_50_SHFT                                                                  0x12
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_RESERVE_49_BMSK                                                               0x20000
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_RESERVE_49_SHFT                                                                  0x11
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_RESERVE_48_BMSK                                                               0x10000
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_RESERVE_48_SHFT                                                                  0x10
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_TLMM_NORTH_XPU_MSA_INTR1_ENABLE_BMSK                                           0x8000
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_TLMM_NORTH_XPU_MSA_INTR1_ENABLE_SHFT                                              0xf
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_RESERVE_46_BMSK                                                                0x4000
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_RESERVE_46_SHFT                                                                   0xe
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_RESERVE_45_BMSK                                                                0x2000
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_RESERVE_45_SHFT                                                                   0xd
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_QUPV3_2_XPU_MSA_INTR1_ENABLE_BMSK                                              0x1000
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_QUPV3_2_XPU_MSA_INTR1_ENABLE_SHFT                                                 0xc
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_IPA_XPU_MSA_INTR1_ENABLE_BMSK                                                   0x800
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_IPA_XPU_MSA_INTR1_ENABLE_SHFT                                                     0xb
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_TLMM_EAST_XPU_MSA_INTR1_ENABLE_BMSK                                             0x400
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_TLMM_EAST_XPU_MSA_INTR1_ENABLE_SHFT                                               0xa
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_TLMM_SOUTH_XPU_MSA_INTR1_ENABLE_BMSK                                            0x200
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_TLMM_SOUTH_XPU_MSA_INTR1_ENABLE_SHFT                                              0x9
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_TLMM_WEST_XPU_MSA_INTR1_ENABLE_BMSK                                             0x100
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_TLMM_WEST_XPU_MSA_INTR1_ENABLE_SHFT                                               0x8
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_MDSS_XPU_MSA_INTR1_ENABLE_BMSK                                                   0x80
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_MDSS_XPU_MSA_INTR1_ENABLE_SHFT                                                    0x7
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_UFS_CARD_ICE_XPU_MSA_INTR1_ENABLE_BMSK                                           0x40
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_UFS_CARD_ICE_XPU_MSA_INTR1_ENABLE_SHFT                                            0x6
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_TITAN_XPU_MSA_INTR1_ENABLE_BMSK                                                  0x20
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_TITAN_XPU_MSA_INTR1_ENABLE_SHFT                                                   0x5
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_SPDM_XPU_MSA_INTR1_ENABLE_BMSK                                                   0x10
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_SPDM_XPU_MSA_INTR1_ENABLE_SHFT                                                    0x4
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_QXM_MSS_NAV_XPU_MSA_INTR1_ENABLE_BMSK                                             0x8
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_QXM_MSS_NAV_XPU_MSA_INTR1_ENABLE_SHFT                                             0x3
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_QNM_AGGRE2_XPU_MSA_INTR1_ENABLE_BMSK                                              0x4
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_QNM_AGGRE2_XPU_MSA_INTR1_ENABLE_SHFT                                              0x2
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_QNM_AGGRE1_XPU_MSA_INTR1_ENABLE_BMSK                                              0x2
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_QNM_AGGRE1_XPU_MSA_INTR1_ENABLE_SHFT                                              0x1
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_OCIMEM_XPU3_XPU_MSA_INTR1_ENABLE_BMSK                                             0x1
#define HWIO_TCSR_SS_XPU_MSA_INTR1_ENABLE_OCIMEM_XPU3_XPU_MSA_INTR1_ENABLE_SHFT                                             0x0

#define HWIO_TCSR_SS_XPU_SP_INTR0_ADDR                                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00021000)
#define HWIO_TCSR_SS_XPU_SP_INTR0_PHYS                                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00021000)
#define HWIO_TCSR_SS_XPU_SP_INTR0_RMSK                                                                               0xffffffff
#define HWIO_TCSR_SS_XPU_SP_INTR0_IN          \
        in_dword_masked(HWIO_TCSR_SS_XPU_SP_INTR0_ADDR, HWIO_TCSR_SS_XPU_SP_INTR0_RMSK)
#define HWIO_TCSR_SS_XPU_SP_INTR0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_XPU_SP_INTR0_ADDR, m)
#define HWIO_TCSR_SS_XPU_SP_INTR0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SP_INTR0_BMSK                                  0x80000000
#define HWIO_TCSR_SS_XPU_SP_INTR0_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SP_INTR0_SHFT                                        0x1f
#define HWIO_TCSR_SS_XPU_SP_INTR0_BOOT_ROM_XPU_SP_INTR0_BMSK                                                         0x40000000
#define HWIO_TCSR_SS_XPU_SP_INTR0_BOOT_ROM_XPU_SP_INTR0_SHFT                                                               0x1e
#define HWIO_TCSR_SS_XPU_SP_INTR0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SP_INTR0_BMSK                                      0x20000000
#define HWIO_TCSR_SS_XPU_SP_INTR0_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SP_INTR0_SHFT                                            0x1d
#define HWIO_TCSR_SS_XPU_SP_INTR0_LLCC3_XPU_SP_INTR0_BMSK                                                            0x10000000
#define HWIO_TCSR_SS_XPU_SP_INTR0_LLCC3_XPU_SP_INTR0_SHFT                                                                  0x1c
#define HWIO_TCSR_SS_XPU_SP_INTR0_LLCC2_XPU_SP_INTR0_BMSK                                                             0x8000000
#define HWIO_TCSR_SS_XPU_SP_INTR0_LLCC2_XPU_SP_INTR0_SHFT                                                                  0x1b
#define HWIO_TCSR_SS_XPU_SP_INTR0_LLCC1_XPU_SP_INTR0_BMSK                                                             0x4000000
#define HWIO_TCSR_SS_XPU_SP_INTR0_LLCC1_XPU_SP_INTR0_SHFT                                                                  0x1a
#define HWIO_TCSR_SS_XPU_SP_INTR0_LLCC0_XPU_SP_INTR0_BMSK                                                             0x2000000
#define HWIO_TCSR_SS_XPU_SP_INTR0_LLCC0_XPU_SP_INTR0_SHFT                                                                  0x19
#define HWIO_TCSR_SS_XPU_SP_INTR0_UFS_XPU_SP_INTR0_BMSK                                                               0x1000000
#define HWIO_TCSR_SS_XPU_SP_INTR0_UFS_XPU_SP_INTR0_SHFT                                                                    0x18
#define HWIO_TCSR_SS_XPU_SP_INTR0_QXS_BOOT_IMEM_SS_MPU_XPU_SP_INTR0_BMSK                                               0x800000
#define HWIO_TCSR_SS_XPU_SP_INTR0_QXS_BOOT_IMEM_SS_MPU_XPU_SP_INTR0_SHFT                                                   0x17
#define HWIO_TCSR_SS_XPU_SP_INTR0_SSC_SDC_XPU_SP_INTR0_BMSK                                                            0x400000
#define HWIO_TCSR_SS_XPU_SP_INTR0_SSC_SDC_XPU_SP_INTR0_SHFT                                                                0x16
#define HWIO_TCSR_SS_XPU_SP_INTR0_GCC_XPU_SP_INTR0_BMSK                                                                0x200000
#define HWIO_TCSR_SS_XPU_SP_INTR0_GCC_XPU_SP_INTR0_SHFT                                                                    0x15
#define HWIO_TCSR_SS_XPU_SP_INTR0_MEMNOC_XPU_SP_INTR0_BMSK                                                             0x100000
#define HWIO_TCSR_SS_XPU_SP_INTR0_MEMNOC_XPU_SP_INTR0_SHFT                                                                 0x14
#define HWIO_TCSR_SS_XPU_SP_INTR0_QM_XPU_SP_INTR0_BMSK                                                                  0x80000
#define HWIO_TCSR_SS_XPU_SP_INTR0_QM_XPU_SP_INTR0_SHFT                                                                     0x13
#define HWIO_TCSR_SS_XPU_SP_INTR0_QNM_SNOC_XPU_SP_INTR0_BMSK                                                            0x40000
#define HWIO_TCSR_SS_XPU_SP_INTR0_QNM_SNOC_XPU_SP_INTR0_SHFT                                                               0x12
#define HWIO_TCSR_SS_XPU_SP_INTR0_QHS_CNOC_XPU_SP_INTR0_BMSK                                                            0x20000
#define HWIO_TCSR_SS_XPU_SP_INTR0_QHS_CNOC_XPU_SP_INTR0_SHFT                                                               0x11
#define HWIO_TCSR_SS_XPU_SP_INTR0_QHM_AOSS_XPU_SP_INTR0_BMSK                                                            0x10000
#define HWIO_TCSR_SS_XPU_SP_INTR0_QHM_AOSS_XPU_SP_INTR0_SHFT                                                               0x10
#define HWIO_TCSR_SS_XPU_SP_INTR0_SP_XPU_SP_INTR0_BMSK                                                                   0x8000
#define HWIO_TCSR_SS_XPU_SP_INTR0_SP_XPU_SP_INTR0_SHFT                                                                      0xf
#define HWIO_TCSR_SS_XPU_SP_INTR0_PIMEM_MPU_XPU_SP_INTR0_BMSK                                                            0x4000
#define HWIO_TCSR_SS_XPU_SP_INTR0_PIMEM_MPU_XPU_SP_INTR0_SHFT                                                               0xe
#define HWIO_TCSR_SS_XPU_SP_INTR0_PIMEM_APU_XPU_SP_INTR0_BMSK                                                            0x2000
#define HWIO_TCSR_SS_XPU_SP_INTR0_PIMEM_APU_XPU_SP_INTR0_SHFT                                                               0xd
#define HWIO_TCSR_SS_XPU_SP_INTR0_SSC_Q6_XPU_SP_INTR0_BMSK                                                               0x1000
#define HWIO_TCSR_SS_XPU_SP_INTR0_SSC_Q6_XPU_SP_INTR0_SHFT                                                                  0xc
#define HWIO_TCSR_SS_XPU_SP_INTR0_SSC_XPU_SP_INTR0_BMSK                                                                   0x800
#define HWIO_TCSR_SS_XPU_SP_INTR0_SSC_XPU_SP_INTR0_SHFT                                                                     0xb
#define HWIO_TCSR_SS_XPU_SP_INTR0_SSC_QUP_XPU_SP_INTR0_BMSK                                                               0x400
#define HWIO_TCSR_SS_XPU_SP_INTR0_SSC_QUP_XPU_SP_INTR0_SHFT                                                                 0xa
#define HWIO_TCSR_SS_XPU_SP_INTR0_SEC_CTRL_XPU_SP_INTR0_BMSK                                                              0x200
#define HWIO_TCSR_SS_XPU_SP_INTR0_SEC_CTRL_XPU_SP_INTR0_SHFT                                                                0x9
#define HWIO_TCSR_SS_XPU_SP_INTR0_DCC_XPU_SP_INTR0_BMSK                                                                   0x100
#define HWIO_TCSR_SS_XPU_SP_INTR0_DCC_XPU_SP_INTR0_SHFT                                                                     0x8
#define HWIO_TCSR_SS_XPU_SP_INTR0_OCIMEM_RPU_XPU_SP_INTR0_BMSK                                                             0x80
#define HWIO_TCSR_SS_XPU_SP_INTR0_OCIMEM_RPU_XPU_SP_INTR0_SHFT                                                              0x7
#define HWIO_TCSR_SS_XPU_SP_INTR0_CRYPTO0_XPU_SP_INTR0_BMSK                                                                0x40
#define HWIO_TCSR_SS_XPU_SP_INTR0_CRYPTO0_XPU_SP_INTR0_SHFT                                                                 0x6
#define HWIO_TCSR_SS_XPU_SP_INTR0_TCSR_MUTEX_XPU_SP_INTR0_BMSK                                                             0x20
#define HWIO_TCSR_SS_XPU_SP_INTR0_TCSR_MUTEX_XPU_SP_INTR0_SHFT                                                              0x5
#define HWIO_TCSR_SS_XPU_SP_INTR0_QUPV3_1_XPU_SP_INTR0_BMSK                                                                0x10
#define HWIO_TCSR_SS_XPU_SP_INTR0_QUPV3_1_XPU_SP_INTR0_SHFT                                                                 0x4
#define HWIO_TCSR_SS_XPU_SP_INTR0_TCSR_REGS_XPU_SP_INTR0_BMSK                                                               0x8
#define HWIO_TCSR_SS_XPU_SP_INTR0_TCSR_REGS_XPU_SP_INTR0_SHFT                                                               0x3
#define HWIO_TCSR_SS_XPU_SP_INTR0_QUPV3_0_XPU_SP_INTR0_BMSK                                                                 0x4
#define HWIO_TCSR_SS_XPU_SP_INTR0_QUPV3_0_XPU_SP_INTR0_SHFT                                                                 0x2
#define HWIO_TCSR_SS_XPU_SP_INTR0_AOSS_MPU_XPU_SP_INTR0_BMSK                                                                0x2
#define HWIO_TCSR_SS_XPU_SP_INTR0_AOSS_MPU_XPU_SP_INTR0_SHFT                                                                0x1
#define HWIO_TCSR_SS_XPU_SP_INTR0_PMIC_ARB_XPU_SP_INTR0_BMSK                                                                0x1
#define HWIO_TCSR_SS_XPU_SP_INTR0_PMIC_ARB_XPU_SP_INTR0_SHFT                                                                0x0

#define HWIO_TCSR_SS_XPU_SP_INTR1_ADDR                                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00021004)
#define HWIO_TCSR_SS_XPU_SP_INTR1_PHYS                                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00021004)
#define HWIO_TCSR_SS_XPU_SP_INTR1_RMSK                                                                                  0x7ffff
#define HWIO_TCSR_SS_XPU_SP_INTR1_IN          \
        in_dword_masked(HWIO_TCSR_SS_XPU_SP_INTR1_ADDR, HWIO_TCSR_SS_XPU_SP_INTR1_RMSK)
#define HWIO_TCSR_SS_XPU_SP_INTR1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_XPU_SP_INTR1_ADDR, m)
#define HWIO_TCSR_SS_XPU_SP_INTR1_RESERVE_50_BMSK                                                                       0x40000
#define HWIO_TCSR_SS_XPU_SP_INTR1_RESERVE_50_SHFT                                                                          0x12
#define HWIO_TCSR_SS_XPU_SP_INTR1_RESERVE_49_BMSK                                                                       0x20000
#define HWIO_TCSR_SS_XPU_SP_INTR1_RESERVE_49_SHFT                                                                          0x11
#define HWIO_TCSR_SS_XPU_SP_INTR1_RESERVE_48_BMSK                                                                       0x10000
#define HWIO_TCSR_SS_XPU_SP_INTR1_RESERVE_48_SHFT                                                                          0x10
#define HWIO_TCSR_SS_XPU_SP_INTR1_TLMM_NORTH_XPU_SP_INTR1_BMSK                                                           0x8000
#define HWIO_TCSR_SS_XPU_SP_INTR1_TLMM_NORTH_XPU_SP_INTR1_SHFT                                                              0xf
#define HWIO_TCSR_SS_XPU_SP_INTR1_RESERVE_46_BMSK                                                                        0x4000
#define HWIO_TCSR_SS_XPU_SP_INTR1_RESERVE_46_SHFT                                                                           0xe
#define HWIO_TCSR_SS_XPU_SP_INTR1_RESERVE_45_BMSK                                                                        0x2000
#define HWIO_TCSR_SS_XPU_SP_INTR1_RESERVE_45_SHFT                                                                           0xd
#define HWIO_TCSR_SS_XPU_SP_INTR1_QUPV3_2_XPU_SP_INTR1_BMSK                                                              0x1000
#define HWIO_TCSR_SS_XPU_SP_INTR1_QUPV3_2_XPU_SP_INTR1_SHFT                                                                 0xc
#define HWIO_TCSR_SS_XPU_SP_INTR1_IPA_XPU_SP_INTR1_BMSK                                                                   0x800
#define HWIO_TCSR_SS_XPU_SP_INTR1_IPA_XPU_SP_INTR1_SHFT                                                                     0xb
#define HWIO_TCSR_SS_XPU_SP_INTR1_TLMM_EAST_XPU_SP_INTR1_BMSK                                                             0x400
#define HWIO_TCSR_SS_XPU_SP_INTR1_TLMM_EAST_XPU_SP_INTR1_SHFT                                                               0xa
#define HWIO_TCSR_SS_XPU_SP_INTR1_TLMM_SOUTH_XPU_SP_INTR1_BMSK                                                            0x200
#define HWIO_TCSR_SS_XPU_SP_INTR1_TLMM_SOUTH_XPU_SP_INTR1_SHFT                                                              0x9
#define HWIO_TCSR_SS_XPU_SP_INTR1_TLMM_WEST_XPU_SP_INTR1_BMSK                                                             0x100
#define HWIO_TCSR_SS_XPU_SP_INTR1_TLMM_WEST_XPU_SP_INTR1_SHFT                                                               0x8
#define HWIO_TCSR_SS_XPU_SP_INTR1_MDSS_XPU_SP_INTR1_BMSK                                                                   0x80
#define HWIO_TCSR_SS_XPU_SP_INTR1_MDSS_XPU_SP_INTR1_SHFT                                                                    0x7
#define HWIO_TCSR_SS_XPU_SP_INTR1_UFS_CARD_ICE_XPU_SP_INTR1_BMSK                                                           0x40
#define HWIO_TCSR_SS_XPU_SP_INTR1_UFS_CARD_ICE_XPU_SP_INTR1_SHFT                                                            0x6
#define HWIO_TCSR_SS_XPU_SP_INTR1_TITAN_XPU_SP_INTR1_BMSK                                                                  0x20
#define HWIO_TCSR_SS_XPU_SP_INTR1_TITAN_XPU_SP_INTR1_SHFT                                                                   0x5
#define HWIO_TCSR_SS_XPU_SP_INTR1_SPDM_XPU_SP_INTR1_BMSK                                                                   0x10
#define HWIO_TCSR_SS_XPU_SP_INTR1_SPDM_XPU_SP_INTR1_SHFT                                                                    0x4
#define HWIO_TCSR_SS_XPU_SP_INTR1_QXM_MSS_NAV_XPU_SP_INTR1_BMSK                                                             0x8
#define HWIO_TCSR_SS_XPU_SP_INTR1_QXM_MSS_NAV_XPU_SP_INTR1_SHFT                                                             0x3
#define HWIO_TCSR_SS_XPU_SP_INTR1_QNM_AGGRE2_XPU_SP_INTR1_BMSK                                                              0x4
#define HWIO_TCSR_SS_XPU_SP_INTR1_QNM_AGGRE2_XPU_SP_INTR1_SHFT                                                              0x2
#define HWIO_TCSR_SS_XPU_SP_INTR1_QNM_AGGRE1_XPU_SP_INTR1_BMSK                                                              0x2
#define HWIO_TCSR_SS_XPU_SP_INTR1_QNM_AGGRE1_XPU_SP_INTR1_SHFT                                                              0x1
#define HWIO_TCSR_SS_XPU_SP_INTR1_OCIMEM_XPU3_XPU_SP_INTR1_BMSK                                                             0x1
#define HWIO_TCSR_SS_XPU_SP_INTR1_OCIMEM_XPU3_XPU_SP_INTR1_SHFT                                                             0x0

#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00021008)
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_PHYS                                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00021008)
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_RMSK                                                                        0xffffffff
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_ADDR, HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_RMSK)
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_ADDR, m)
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_ADDR,v)
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_ADDR,m,v,HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_IN)
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SP_INTR0_ENABLE_BMSK                    0x80000000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_DTP_QHS_NON_BROADCAST_MPU_MAINO_XPU_SP_INTR0_ENABLE_SHFT                          0x1f
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_BOOT_ROM_XPU_SP_INTR0_ENABLE_BMSK                                           0x40000000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_BOOT_ROM_XPU_SP_INTR0_ENABLE_SHFT                                                 0x1e
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SP_INTR0_ENABLE_BMSK                        0x20000000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_DTP_QHS_BROADCAST_MPU_MAINO_XPU_SP_INTR0_ENABLE_SHFT                              0x1d
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_LLCC3_XPU_SP_INTR0_ENABLE_BMSK                                              0x10000000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_LLCC3_XPU_SP_INTR0_ENABLE_SHFT                                                    0x1c
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_LLCC2_XPU_SP_INTR0_ENABLE_BMSK                                               0x8000000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_LLCC2_XPU_SP_INTR0_ENABLE_SHFT                                                    0x1b
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_LLCC1_XPU_SP_INTR0_ENABLE_BMSK                                               0x4000000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_LLCC1_XPU_SP_INTR0_ENABLE_SHFT                                                    0x1a
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_LLCC0_XPU_SP_INTR0_ENABLE_BMSK                                               0x2000000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_LLCC0_XPU_SP_INTR0_ENABLE_SHFT                                                    0x19
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_UFS_XPU_SP_INTR0_ENABLE_BMSK                                                 0x1000000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_UFS_XPU_SP_INTR0_ENABLE_SHFT                                                      0x18
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_QXS_BOOT_IMEM_SS_MPU_XPU_SP_INTR0_ENABLE_BMSK                                 0x800000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_QXS_BOOT_IMEM_SS_MPU_XPU_SP_INTR0_ENABLE_SHFT                                     0x17
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_SSC_SDC_XPU_SP_INTR0_ENABLE_BMSK                                              0x400000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_SSC_SDC_XPU_SP_INTR0_ENABLE_SHFT                                                  0x16
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_GCC_XPU_SP_INTR0_ENABLE_BMSK                                                  0x200000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_GCC_XPU_SP_INTR0_ENABLE_SHFT                                                      0x15
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_MEMNOC_XPU_SP_INTR0_ENABLE_BMSK                                               0x100000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_MEMNOC_XPU_SP_INTR0_ENABLE_SHFT                                                   0x14
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_QM_XPU_SP_INTR0_ENABLE_BMSK                                                    0x80000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_QM_XPU_SP_INTR0_ENABLE_SHFT                                                       0x13
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_QNM_SNOC_XPU_SP_INTR0_ENABLE_BMSK                                              0x40000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_QNM_SNOC_XPU_SP_INTR0_ENABLE_SHFT                                                 0x12
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_QHS_CNOC_XPU_SP_INTR0_ENABLE_BMSK                                              0x20000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_QHS_CNOC_XPU_SP_INTR0_ENABLE_SHFT                                                 0x11
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_QHM_AOSS_XPU_SP_INTR0_ENABLE_BMSK                                              0x10000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_QHM_AOSS_XPU_SP_INTR0_ENABLE_SHFT                                                 0x10
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_SP_XPU_SP_INTR0_ENABLE_BMSK                                                     0x8000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_SP_XPU_SP_INTR0_ENABLE_SHFT                                                        0xf
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_PIMEM_MPU_XPU_SP_INTR0_ENABLE_BMSK                                              0x4000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_PIMEM_MPU_XPU_SP_INTR0_ENABLE_SHFT                                                 0xe
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_PIMEM_APU_XPU_SP_INTR0_ENABLE_BMSK                                              0x2000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_PIMEM_APU_XPU_SP_INTR0_ENABLE_SHFT                                                 0xd
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_SSC_Q6_XPU_SP_INTR0_ENABLE_BMSK                                                 0x1000
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_SSC_Q6_XPU_SP_INTR0_ENABLE_SHFT                                                    0xc
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_SSC_XPU_SP_INTR0_ENABLE_BMSK                                                     0x800
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_SSC_XPU_SP_INTR0_ENABLE_SHFT                                                       0xb
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_SSC_QUP_XPU_SP_INTR0_ENABLE_BMSK                                                 0x400
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_SSC_QUP_XPU_SP_INTR0_ENABLE_SHFT                                                   0xa
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_SEC_CTRL_XPU_SP_INTR0_ENABLE_BMSK                                                0x200
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_SEC_CTRL_XPU_SP_INTR0_ENABLE_SHFT                                                  0x9
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_DCC_XPU_SP_INTR0_ENABLE_BMSK                                                     0x100
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_DCC_XPU_SP_INTR0_ENABLE_SHFT                                                       0x8
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_OCIMEM_RPU_XPU_SP_INTR0_ENABLE_BMSK                                               0x80
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_OCIMEM_RPU_XPU_SP_INTR0_ENABLE_SHFT                                                0x7
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_CRYPTO0_XPU_SP_INTR0_ENABLE_BMSK                                                  0x40
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_CRYPTO0_XPU_SP_INTR0_ENABLE_SHFT                                                   0x6
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_TCSR_MUTEX_XPU_SP_INTR0_ENABLE_BMSK                                               0x20
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_TCSR_MUTEX_XPU_SP_INTR0_ENABLE_SHFT                                                0x5
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_QUPV3_1_XPU_SP_INTR0_ENABLE_BMSK                                                  0x10
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_QUPV3_1_XPU_SP_INTR0_ENABLE_SHFT                                                   0x4
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_TCSR_REGS_XPU_SP_INTR0_ENABLE_BMSK                                                 0x8
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_TCSR_REGS_XPU_SP_INTR0_ENABLE_SHFT                                                 0x3
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_QUPV3_0_XPU_SP_INTR0_ENABLE_BMSK                                                   0x4
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_QUPV3_0_XPU_SP_INTR0_ENABLE_SHFT                                                   0x2
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_AOSS_MPU_XPU_SP_INTR0_ENABLE_BMSK                                                  0x2
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_AOSS_MPU_XPU_SP_INTR0_ENABLE_SHFT                                                  0x1
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_PMIC_ARB_XPU_SP_INTR0_ENABLE_BMSK                                                  0x1
#define HWIO_TCSR_SS_XPU_SP_INTR0_ENABLE_PMIC_ARB_XPU_SP_INTR0_ENABLE_SHFT                                                  0x0

#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x0002100c)
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_PHYS                                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002100c)
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_RMSK                                                                           0x7ffff
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_ADDR, HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_RMSK)
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_ADDR, m)
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_ADDR,v)
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_ADDR,m,v,HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_IN)
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_RESERVE_50_BMSK                                                                0x40000
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_RESERVE_50_SHFT                                                                   0x12
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_RESERVE_49_BMSK                                                                0x20000
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_RESERVE_49_SHFT                                                                   0x11
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_RESERVE_48_BMSK                                                                0x10000
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_RESERVE_48_SHFT                                                                   0x10
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_TLMM_NORTH_XPU_SP_INTR1_ENABLE_BMSK                                             0x8000
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_TLMM_NORTH_XPU_SP_INTR1_ENABLE_SHFT                                                0xf
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_RESERVE_46_BMSK                                                                 0x4000
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_RESERVE_46_SHFT                                                                    0xe
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_RESERVE_45_BMSK                                                                 0x2000
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_RESERVE_45_SHFT                                                                    0xd
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_QUPV3_2_XPU_SP_INTR1_ENABLE_BMSK                                                0x1000
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_QUPV3_2_XPU_SP_INTR1_ENABLE_SHFT                                                   0xc
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_IPA_XPU_SP_INTR1_ENABLE_BMSK                                                     0x800
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_IPA_XPU_SP_INTR1_ENABLE_SHFT                                                       0xb
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_TLMM_EAST_XPU_SP_INTR1_ENABLE_BMSK                                               0x400
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_TLMM_EAST_XPU_SP_INTR1_ENABLE_SHFT                                                 0xa
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_TLMM_SOUTH_XPU_SP_INTR1_ENABLE_BMSK                                              0x200
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_TLMM_SOUTH_XPU_SP_INTR1_ENABLE_SHFT                                                0x9
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_TLMM_WEST_XPU_SP_INTR1_ENABLE_BMSK                                               0x100
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_TLMM_WEST_XPU_SP_INTR1_ENABLE_SHFT                                                 0x8
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_MDSS_XPU_SP_INTR1_ENABLE_BMSK                                                     0x80
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_MDSS_XPU_SP_INTR1_ENABLE_SHFT                                                      0x7
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_UFS_CARD_ICE_XPU_SP_INTR1_ENABLE_BMSK                                             0x40
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_UFS_CARD_ICE_XPU_SP_INTR1_ENABLE_SHFT                                              0x6
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_TITAN_XPU_SP_INTR1_ENABLE_BMSK                                                    0x20
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_TITAN_XPU_SP_INTR1_ENABLE_SHFT                                                     0x5
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_SPDM_XPU_SP_INTR1_ENABLE_BMSK                                                     0x10
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_SPDM_XPU_SP_INTR1_ENABLE_SHFT                                                      0x4
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_QXM_MSS_NAV_XPU_SP_INTR1_ENABLE_BMSK                                               0x8
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_QXM_MSS_NAV_XPU_SP_INTR1_ENABLE_SHFT                                               0x3
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_QNM_AGGRE2_XPU_SP_INTR1_ENABLE_BMSK                                                0x4
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_QNM_AGGRE2_XPU_SP_INTR1_ENABLE_SHFT                                                0x2
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_QNM_AGGRE1_XPU_SP_INTR1_ENABLE_BMSK                                                0x2
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_QNM_AGGRE1_XPU_SP_INTR1_ENABLE_SHFT                                                0x1
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_OCIMEM_XPU3_XPU_SP_INTR1_ENABLE_BMSK                                               0x1
#define HWIO_TCSR_SS_XPU_SP_INTR1_ENABLE_OCIMEM_XPU3_XPU_SP_INTR1_ENABLE_SHFT                                               0x0

#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x00002010)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_PHYS                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00002010)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RMSK                                                                    0x3ffff
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_IN          \
        in_dword_masked(HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ADDR, HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RMSK)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ADDR, m)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RESERVE_17_VMIDMT_NSGIRPT_BMSK                                          0x20000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RESERVE_17_VMIDMT_NSGIRPT_SHFT                                             0x11
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RESERVE_16_VMIDMT_NSGIRPT_BMSK                                          0x10000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RESERVE_16_VMIDMT_NSGIRPT_SHFT                                             0x10
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RESERVE_15_VMIDMT_NSGIRPT_BMSK                                           0x8000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RESERVE_15_VMIDMT_NSGIRPT_SHFT                                              0xf
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RESERVE_14_VMIDMT_NSGIRPT_BMSK                                           0x4000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RESERVE_14_VMIDMT_NSGIRPT_SHFT                                              0xe
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RESERVE_13_VMIDMT_NSGIRPT_BMSK                                           0x2000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RESERVE_13_VMIDMT_NSGIRPT_SHFT                                              0xd
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RESERVE_12_VMIDMT_NSGIRPT_BMSK                                           0x1000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RESERVE_12_VMIDMT_NSGIRPT_SHFT                                              0xc
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_QDSS_DAP_VMIDMT_NSGIRPT_BMSK                                              0x800
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_QDSS_DAP_VMIDMT_NSGIRPT_SHFT                                                0xb
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_QDSS_TRACE_VMIDMT_NSGIRPT_BMSK                                            0x400
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_QDSS_TRACE_VMIDMT_NSGIRPT_SHFT                                              0xa
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_IPA_VMIDMT_NSGIRPT_BMSK                                                   0x200
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_IPA_VMIDMT_NSGIRPT_SHFT                                                     0x9
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RESERVE_8_VMIDMT_NSGIRPT_BMSK                                             0x100
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RESERVE_8_VMIDMT_NSGIRPT_SHFT                                               0x8
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RESERVE_7_VMIDMT_NSGIRPT_BMSK                                              0x80
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_RESERVE_7_VMIDMT_NSGIRPT_SHFT                                               0x7
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_SSC_VMIDMT_NSGIRPT_BMSK                                                    0x40
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_SSC_VMIDMT_NSGIRPT_SHFT                                                     0x6
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_QUPV3_2_VMIDMT_NSGIRPT_BMSK                                                0x20
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_QUPV3_2_VMIDMT_NSGIRPT_SHFT                                                 0x5
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_QUPV3_1_VMIDMT_NSGIRPT_BMSK                                                0x10
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_QUPV3_1_VMIDMT_NSGIRPT_SHFT                                                 0x4
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_SSC_SDC_VMIDMT_NSGIRPT_BMSK                                                 0x8
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_SSC_SDC_VMIDMT_NSGIRPT_SHFT                                                 0x3
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_QUPV3_0_VMIDMT_NSGIRPT_BMSK                                                 0x4
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_QUPV3_0_VMIDMT_NSGIRPT_SHFT                                                 0x2
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_AOP_VMIDMT_NSGIRPT_BMSK                                                     0x2
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_AOP_VMIDMT_NSGIRPT_SHFT                                                     0x1
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_CRYPTO0_VMIDMT_NSGIRPT_BMSK                                                 0x1
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_CRYPTO0_VMIDMT_NSGIRPT_SHFT                                                 0x0

#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_ADDR                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x00002050)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_PHYS                                                          (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00002050)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RMSK                                                             0x3ffff
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_ADDR, HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RMSK)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_ADDR, m)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_ADDR,v)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_ADDR,m,v,HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_IN)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RESERVE_17_VMIDMT_NSGIRPT_ENABLE_BMSK                            0x20000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RESERVE_17_VMIDMT_NSGIRPT_ENABLE_SHFT                               0x11
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RESERVE_16_VMIDMT_NSGIRPT_ENABLE_BMSK                            0x10000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RESERVE_16_VMIDMT_NSGIRPT_ENABLE_SHFT                               0x10
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RESERVE_15_VMIDMT_NSGIRPT_ENABLE_BMSK                             0x8000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RESERVE_15_VMIDMT_NSGIRPT_ENABLE_SHFT                                0xf
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RESERVE_14_VMIDMT_NSGIRPT_ENABLE_BMSK                             0x4000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RESERVE_14_VMIDMT_NSGIRPT_ENABLE_SHFT                                0xe
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RESERVE_13_VMIDMT_NSGIRPT_ENABLE_BMSK                             0x2000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RESERVE_13_VMIDMT_NSGIRPT_ENABLE_SHFT                                0xd
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RESERVE_12_VMIDMT_NSGIRPT_ENABLE_BMSK                             0x1000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RESERVE_12_VMIDMT_NSGIRPT_ENABLE_SHFT                                0xc
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_QDSS_DAP_VMIDMT_NSGIRPT_ENABLE_BMSK                                0x800
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_QDSS_DAP_VMIDMT_NSGIRPT_ENABLE_SHFT                                  0xb
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_QDSS_TRACE_VMIDMT_NSGIRPT_ENABLE_BMSK                              0x400
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_QDSS_TRACE_VMIDMT_NSGIRPT_ENABLE_SHFT                                0xa
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_IPA_VMIDMT_NSGIRPT_ENABLE_BMSK                                     0x200
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_IPA_VMIDMT_NSGIRPT_ENABLE_SHFT                                       0x9
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RESERVE_8_VMIDMT_NSGIRPT_ENABLE_BMSK                               0x100
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RESERVE_8_VMIDMT_NSGIRPT_ENABLE_SHFT                                 0x8
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RESERVE_7_VMIDMT_NSGIRPT_ENABLE_BMSK                                0x80
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_RESERVE_7_VMIDMT_NSGIRPT_ENABLE_SHFT                                 0x7
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_SSC_VMIDMT_NSGIRPT_ENABLE_BMSK                                      0x40
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_SSC_VMIDMT_NSGIRPT_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_QUPV3_2_VMIDMT_NSGIRPT_ENABLE_BMSK                                  0x20
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_QUPV3_2_VMIDMT_NSGIRPT_ENABLE_SHFT                                   0x5
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_QUPV3_1_VMIDMT_NSGIRPT_ENABLE_BMSK                                  0x10
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_QUPV3_1_VMIDMT_NSGIRPT_ENABLE_SHFT                                   0x4
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_SSC_SDC_VMIDMT_NSGIRPT_ENABLE_BMSK                                   0x8
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_SSC_SDC_VMIDMT_NSGIRPT_ENABLE_SHFT                                   0x3
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_QUPV3_0_VMIDMT_NSGIRPT_ENABLE_BMSK                                   0x4
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_QUPV3_0_VMIDMT_NSGIRPT_ENABLE_SHFT                                   0x2
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_AOP_VMIDMT_NSGIRPT_ENABLE_BMSK                                       0x2
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_AOP_VMIDMT_NSGIRPT_ENABLE_SHFT                                       0x1
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_CRYPTO0_VMIDMT_NSGIRPT_ENABLE_BMSK                                   0x1
#define HWIO_TCSR_SS_VMIDMT_CLIENT_NON_SEC_INTR_ENABLE_CRYPTO0_VMIDMT_NSGIRPT_ENABLE_SHFT                                   0x0

#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ADDR                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x00003000)
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_PHYS                                                                    (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00003000)
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RMSK                                                                       0x3ffff
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_IN          \
        in_dword_masked(HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ADDR, HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RMSK)
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ADDR, m)
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RESERVE_17_VMIDMT_NSGCFGIRPT_BMSK                                          0x20000
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RESERVE_17_VMIDMT_NSGCFGIRPT_SHFT                                             0x11
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RESERVE_16_VMIDMT_NSGCFGIRPT_BMSK                                          0x10000
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RESERVE_16_VMIDMT_NSGCFGIRPT_SHFT                                             0x10
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RESERVE_15_VMIDMT_NSGCFGIRPT_BMSK                                           0x8000
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RESERVE_15_VMIDMT_NSGCFGIRPT_SHFT                                              0xf
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RESERVE_14_VMIDMT_NSGCFGIRPT_BMSK                                           0x4000
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RESERVE_14_VMIDMT_NSGCFGIRPT_SHFT                                              0xe
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RESERVE_13_VMIDMT_NSGCFGIRPT_BMSK                                           0x2000
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RESERVE_13_VMIDMT_NSGCFGIRPT_SHFT                                              0xd
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RESERVE_12_VMIDMT_NSGCFGIRPT_BMSK                                           0x1000
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RESERVE_12_VMIDMT_NSGCFGIRPT_SHFT                                              0xc
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_QDSS_DAP_VMIDMT_NSGCFGIRPT_BMSK                                              0x800
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_QDSS_DAP_VMIDMT_NSGCFGIRPT_SHFT                                                0xb
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_QDSS_TRACE_VMIDMT_NSGCFGIRPT_BMSK                                            0x400
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_QDSS_TRACE_VMIDMT_NSGCFGIRPT_SHFT                                              0xa
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_IPA_VMIDMT_NSGCFGIRPT_BMSK                                                   0x200
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_IPA_VMIDMT_NSGCFGIRPT_SHFT                                                     0x9
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RESERVE_8_VMIDMT_NSGCFGIRPT_BMSK                                             0x100
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RESERVE_8_VMIDMT_NSGCFGIRPT_SHFT                                               0x8
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RESERVE_7_VMIDMT_NSGCFGIRPT_BMSK                                              0x80
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_RESERVE_7_VMIDMT_NSGCFGIRPT_SHFT                                               0x7
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_SSC_VMIDMT_NSGCFGIRPT_BMSK                                                    0x40
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_SSC_VMIDMT_NSGCFGIRPT_SHFT                                                     0x6
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_QUPV3_2_VMIDMT_NSGCFGIRPT_BMSK                                                0x20
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_QUPV3_2_VMIDMT_NSGCFGIRPT_SHFT                                                 0x5
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_QUPV3_1_VMIDMT_NSGCFGIRPT_BMSK                                                0x10
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_QUPV3_1_VMIDMT_NSGCFGIRPT_SHFT                                                 0x4
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_SSC_SDC_VMIDMT_NSGCFGIRPT_BMSK                                                 0x8
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_SSC_SDC_VMIDMT_NSGCFGIRPT_SHFT                                                 0x3
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_QUPV3_0_VMIDMT_NSGCFGIRPT_BMSK                                                 0x4
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_QUPV3_0_VMIDMT_NSGCFGIRPT_SHFT                                                 0x2
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_AOP_VMIDMT_NSGCFGIRPT_BMSK                                                     0x2
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_AOP_VMIDMT_NSGCFGIRPT_SHFT                                                     0x1
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_CRYPTO0_VMIDMT_NSGCFGIRPT_BMSK                                                 0x1
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_CRYPTO0_VMIDMT_NSGCFGIRPT_SHFT                                                 0x0

#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_ADDR                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x00003040)
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_PHYS                                                             (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00003040)
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RMSK                                                                0x3ffff
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_ADDR, HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RMSK)
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_ADDR, m)
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_ADDR,v)
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_ADDR,m,v,HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_IN)
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RESERVE_17_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                            0x20000
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RESERVE_17_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                               0x11
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RESERVE_16_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                            0x10000
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RESERVE_16_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                               0x10
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RESERVE_15_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                             0x8000
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RESERVE_15_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                0xf
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RESERVE_14_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                             0x4000
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RESERVE_14_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                0xe
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RESERVE_13_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                             0x2000
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RESERVE_13_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                0xd
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RESERVE_12_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                             0x1000
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RESERVE_12_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                0xc
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_QDSS_DAP_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                0x800
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_QDSS_DAP_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                  0xb
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_QDSS_TRACE_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                              0x400
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_QDSS_TRACE_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                0xa
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_IPA_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                     0x200
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_IPA_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                       0x9
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RESERVE_8_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                               0x100
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RESERVE_8_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                 0x8
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RESERVE_7_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                0x80
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_RESERVE_7_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                 0x7
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_SSC_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                      0x40
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_SSC_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                       0x6
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_QUPV3_2_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                  0x20
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_QUPV3_2_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                   0x5
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_QUPV3_1_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                  0x10
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_QUPV3_1_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                   0x4
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_SSC_SDC_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                   0x8
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_SSC_SDC_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                   0x3
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_QUPV3_0_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                   0x4
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_QUPV3_0_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                   0x2
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_AOP_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                       0x2
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_AOP_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                       0x1
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_CRYPTO0_VMIDMT_NSGCFGIRPT_ENABLE_BMSK                                   0x1
#define HWIO_TCSR_SS_VMIDMT_CFG_NON_SEC_INTR_ENABLE_CRYPTO0_VMIDMT_NSGCFGIRPT_ENABLE_SHFT                                   0x0

#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ADDR                                                                     (TCSR_TCSR_REGS_REG_BASE      + 0x00004010)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_PHYS                                                                     (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00004010)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RMSK                                                                        0x3ffff
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_IN          \
        in_dword_masked(HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ADDR, HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RMSK)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ADDR, m)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RESERVE_17_VMIDMT_GIRPT_BMSK                                                0x20000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RESERVE_17_VMIDMT_GIRPT_SHFT                                                   0x11
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RESERVE_16_VMIDMT_GIRPT_BMSK                                                0x10000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RESERVE_16_VMIDMT_GIRPT_SHFT                                                   0x10
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RESERVE_15_VMIDMT_GIRPT_BMSK                                                 0x8000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RESERVE_15_VMIDMT_GIRPT_SHFT                                                    0xf
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RESERVE_14_VMIDMT_GIRPT_BMSK                                                 0x4000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RESERVE_14_VMIDMT_GIRPT_SHFT                                                    0xe
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RESERVE_13_VMIDMT_GIRPT_BMSK                                                 0x2000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RESERVE_13_VMIDMT_GIRPT_SHFT                                                    0xd
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RESERVE_12_VMIDMT_GIRPT_BMSK                                                 0x1000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RESERVE_12_VMIDMT_GIRPT_SHFT                                                    0xc
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_QDSS_DAP_VMIDMT_GIRPT_BMSK                                                    0x800
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_QDSS_DAP_VMIDMT_GIRPT_SHFT                                                      0xb
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_QDSS_TRACE_VMIDMT_GIRPT_BMSK                                                  0x400
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_QDSS_TRACE_VMIDMT_GIRPT_SHFT                                                    0xa
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_IPA_VMIDMT_GIRPT_BMSK                                                         0x200
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_IPA_VMIDMT_GIRPT_SHFT                                                           0x9
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RESERVE_8_VMIDMT_GIRPT_BMSK                                                   0x100
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RESERVE_8_VMIDMT_GIRPT_SHFT                                                     0x8
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RESERVE_7_VMIDMT_GIRPT_BMSK                                                    0x80
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_RESERVE_7_VMIDMT_GIRPT_SHFT                                                     0x7
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_SSC_VMIDMT_GIRPT_BMSK                                                          0x40
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_SSC_VMIDMT_GIRPT_SHFT                                                           0x6
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_QUPV3_2_VMIDMT_GIRPT_BMSK                                                      0x20
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_QUPV3_2_VMIDMT_GIRPT_SHFT                                                       0x5
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_QUPV3_1_VMIDMT_GIRPT_BMSK                                                      0x10
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_QUPV3_1_VMIDMT_GIRPT_SHFT                                                       0x4
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_SSC_SDC_VMIDMT_GIRPT_BMSK                                                       0x8
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_SSC_SDC_VMIDMT_GIRPT_SHFT                                                       0x3
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_QUPV3_0_VMIDMT_GIRPT_BMSK                                                       0x4
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_QUPV3_0_VMIDMT_GIRPT_SHFT                                                       0x2
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_AOP_VMIDMT_GIRPT_BMSK                                                           0x2
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_AOP_VMIDMT_GIRPT_SHFT                                                           0x1
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_CRYPTO0_VMIDMT_GIRPT_BMSK                                                       0x1
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_CRYPTO0_VMIDMT_GIRPT_SHFT                                                       0x0

#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00004050)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00004050)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RMSK                                                                 0x3ffff
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_ADDR, HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RMSK)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_ADDR, m)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_ADDR,v)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_ADDR,m,v,HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_IN)
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RESERVE_17_VMIDMT_GIRPT_ENABLE_BMSK                                  0x20000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RESERVE_17_VMIDMT_GIRPT_ENABLE_SHFT                                     0x11
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RESERVE_16_VMIDMT_GIRPT_ENABLE_BMSK                                  0x10000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RESERVE_16_VMIDMT_GIRPT_ENABLE_SHFT                                     0x10
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RESERVE_15_VMIDMT_GIRPT_ENABLE_BMSK                                   0x8000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RESERVE_15_VMIDMT_GIRPT_ENABLE_SHFT                                      0xf
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RESERVE_14_VMIDMT_GIRPT_ENABLE_BMSK                                   0x4000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RESERVE_14_VMIDMT_GIRPT_ENABLE_SHFT                                      0xe
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RESERVE_13_VMIDMT_GIRPT_ENABLE_BMSK                                   0x2000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RESERVE_13_VMIDMT_GIRPT_ENABLE_SHFT                                      0xd
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RESERVE_12_VMIDMT_GIRPT_ENABLE_BMSK                                   0x1000
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RESERVE_12_VMIDMT_GIRPT_ENABLE_SHFT                                      0xc
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_QDSS_DAP_VMIDMT_GIRPT_ENABLE_BMSK                                      0x800
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_QDSS_DAP_VMIDMT_GIRPT_ENABLE_SHFT                                        0xb
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_QDSS_TRACE_VMIDMT_GIRPT_ENABLE_BMSK                                    0x400
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_QDSS_TRACE_VMIDMT_GIRPT_ENABLE_SHFT                                      0xa
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_IPA_VMIDMT_GIRPT_ENABLE_BMSK                                           0x200
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_IPA_VMIDMT_GIRPT_ENABLE_SHFT                                             0x9
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RESERVE_8_VMIDMT_GIRPT_ENABLE_BMSK                                     0x100
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RESERVE_8_VMIDMT_GIRPT_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RESERVE_7_VMIDMT_GIRPT_ENABLE_BMSK                                      0x80
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_RESERVE_7_VMIDMT_GIRPT_ENABLE_SHFT                                       0x7
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_SSC_VMIDMT_GIRPT_ENABLE_BMSK                                            0x40
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_SSC_VMIDMT_GIRPT_ENABLE_SHFT                                             0x6
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_QUPV3_2_VMIDMT_GIRPT_ENABLE_BMSK                                        0x20
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_QUPV3_2_VMIDMT_GIRPT_ENABLE_SHFT                                         0x5
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_QUPV3_1_VMIDMT_GIRPT_ENABLE_BMSK                                        0x10
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_QUPV3_1_VMIDMT_GIRPT_ENABLE_SHFT                                         0x4
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_SSC_SDC_VMIDMT_GIRPT_ENABLE_BMSK                                         0x8
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_SSC_SDC_VMIDMT_GIRPT_ENABLE_SHFT                                         0x3
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_QUPV3_0_VMIDMT_GIRPT_ENABLE_BMSK                                         0x4
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_QUPV3_0_VMIDMT_GIRPT_ENABLE_SHFT                                         0x2
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_AOP_VMIDMT_GIRPT_ENABLE_BMSK                                             0x2
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_AOP_VMIDMT_GIRPT_ENABLE_SHFT                                             0x1
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_CRYPTO0_VMIDMT_GIRPT_ENABLE_BMSK                                         0x1
#define HWIO_TCSR_SS_VMIDMT_CLIENT_SEC_INTR_ENABLE_CRYPTO0_VMIDMT_GIRPT_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00005000)
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_PHYS                                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00005000)
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RMSK                                                                           0x3ffff
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_IN          \
        in_dword_masked(HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ADDR, HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RMSK)
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ADDR, m)
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RESERVE_17_VMIDMT_GCFGIRPT_BMSK                                                0x20000
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RESERVE_17_VMIDMT_GCFGIRPT_SHFT                                                   0x11
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RESERVE_16_VMIDMT_GCFGIRPT_BMSK                                                0x10000
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RESERVE_16_VMIDMT_GCFGIRPT_SHFT                                                   0x10
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RESERVE_15_VMIDMT_GCFGIRPT_BMSK                                                 0x8000
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RESERVE_15_VMIDMT_GCFGIRPT_SHFT                                                    0xf
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RESERVE_14_VMIDMT_GCFGIRPT_BMSK                                                 0x4000
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RESERVE_14_VMIDMT_GCFGIRPT_SHFT                                                    0xe
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RESERVE_13_VMIDMT_GCFGIRPT_BMSK                                                 0x2000
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RESERVE_13_VMIDMT_GCFGIRPT_SHFT                                                    0xd
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RESERVE_12_VMIDMT_GCFGIRPT_BMSK                                                 0x1000
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RESERVE_12_VMIDMT_GCFGIRPT_SHFT                                                    0xc
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_QDSS_DAP_VMIDMT_GCFGIRPT_BMSK                                                    0x800
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_QDSS_DAP_VMIDMT_GCFGIRPT_SHFT                                                      0xb
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_QDSS_TRACE_VMIDMT_GCFGIRPT_BMSK                                                  0x400
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_QDSS_TRACE_VMIDMT_GCFGIRPT_SHFT                                                    0xa
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_IPA_VMIDMT_GCFGIRPT_BMSK                                                         0x200
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_IPA_VMIDMT_GCFGIRPT_SHFT                                                           0x9
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RESERVE_8_VMIDMT_GCFGIRPT_BMSK                                                   0x100
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RESERVE_8_VMIDMT_GCFGIRPT_SHFT                                                     0x8
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RESERVE_7_VMIDMT_GCFGIRPT_BMSK                                                    0x80
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_RESERVE_7_VMIDMT_GCFGIRPT_SHFT                                                     0x7
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_SSC_VMIDMT_GCFGIRPT_BMSK                                                          0x40
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_SSC_VMIDMT_GCFGIRPT_SHFT                                                           0x6
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_QUPV3_2_VMIDMT_GCFGIRPT_BMSK                                                      0x20
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_QUPV3_2_VMIDMT_GCFGIRPT_SHFT                                                       0x5
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_QUPV3_1_VMIDMT_GCFGIRPT_BMSK                                                      0x10
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_QUPV3_1_VMIDMT_GCFGIRPT_SHFT                                                       0x4
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_SSC_SDC_VMIDMT_GCFGIRPT_BMSK                                                       0x8
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_SSC_SDC_VMIDMT_GCFGIRPT_SHFT                                                       0x3
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_QUPV3_0_VMIDMT_GCFGIRPT_BMSK                                                       0x4
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_QUPV3_0_VMIDMT_GCFGIRPT_SHFT                                                       0x2
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_AOP_VMIDMT_GCFGIRPT_BMSK                                                           0x2
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_AOP_VMIDMT_GCFGIRPT_SHFT                                                           0x1
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_CRYPTO0_VMIDMT_GCFGIRPT_BMSK                                                       0x1
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_CRYPTO0_VMIDMT_GCFGIRPT_SHFT                                                       0x0

#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x00005040)
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_PHYS                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00005040)
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RMSK                                                                    0x3ffff
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_ADDR, HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RMSK)
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_ADDR, m)
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_ADDR,v)
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_ADDR,m,v,HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_IN)
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RESERVE_17_VMIDMT_GCFGIRPT_ENABLE_BMSK                                  0x20000
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RESERVE_17_VMIDMT_GCFGIRPT_ENABLE_SHFT                                     0x11
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RESERVE_16_VMIDMT_GCFGIRPT_ENABLE_BMSK                                  0x10000
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RESERVE_16_VMIDMT_GCFGIRPT_ENABLE_SHFT                                     0x10
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RESERVE_15_VMIDMT_GCFGIRPT_ENABLE_BMSK                                   0x8000
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RESERVE_15_VMIDMT_GCFGIRPT_ENABLE_SHFT                                      0xf
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RESERVE_14_VMIDMT_GCFGIRPT_ENABLE_BMSK                                   0x4000
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RESERVE_14_VMIDMT_GCFGIRPT_ENABLE_SHFT                                      0xe
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RESERVE_13_VMIDMT_GCFGIRPT_ENABLE_BMSK                                   0x2000
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RESERVE_13_VMIDMT_GCFGIRPT_ENABLE_SHFT                                      0xd
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RESERVE_12_VMIDMT_GCFGIRPT_ENABLE_BMSK                                   0x1000
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RESERVE_12_VMIDMT_GCFGIRPT_ENABLE_SHFT                                      0xc
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_QDSS_DAP_VMIDMT_GCFGIRPT_ENABLE_BMSK                                      0x800
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_QDSS_DAP_VMIDMT_GCFGIRPT_ENABLE_SHFT                                        0xb
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_QDSS_TRACE_VMIDMT_GCFGIRPT_ENABLE_BMSK                                    0x400
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_QDSS_TRACE_VMIDMT_GCFGIRPT_ENABLE_SHFT                                      0xa
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_IPA_VMIDMT_GCFGIRPT_ENABLE_BMSK                                           0x200
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_IPA_VMIDMT_GCFGIRPT_ENABLE_SHFT                                             0x9
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RESERVE_8_VMIDMT_GCFGIRPT_ENABLE_BMSK                                     0x100
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RESERVE_8_VMIDMT_GCFGIRPT_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RESERVE_7_VMIDMT_GCFGIRPT_ENABLE_BMSK                                      0x80
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_RESERVE_7_VMIDMT_GCFGIRPT_ENABLE_SHFT                                       0x7
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_SSC_VMIDMT_GCFGIRPT_ENABLE_BMSK                                            0x40
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_SSC_VMIDMT_GCFGIRPT_ENABLE_SHFT                                             0x6
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_QUPV3_2_VMIDMT_GCFGIRPT_ENABLE_BMSK                                        0x20
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_QUPV3_2_VMIDMT_GCFGIRPT_ENABLE_SHFT                                         0x5
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_QUPV3_1_VMIDMT_GCFGIRPT_ENABLE_BMSK                                        0x10
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_QUPV3_1_VMIDMT_GCFGIRPT_ENABLE_SHFT                                         0x4
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_SSC_SDC_VMIDMT_GCFGIRPT_ENABLE_BMSK                                         0x8
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_SSC_SDC_VMIDMT_GCFGIRPT_ENABLE_SHFT                                         0x3
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_QUPV3_0_VMIDMT_GCFGIRPT_ENABLE_BMSK                                         0x4
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_QUPV3_0_VMIDMT_GCFGIRPT_ENABLE_SHFT                                         0x2
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_AOP_VMIDMT_GCFGIRPT_ENABLE_BMSK                                             0x2
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_AOP_VMIDMT_GCFGIRPT_ENABLE_SHFT                                             0x1
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_CRYPTO0_VMIDMT_GCFGIRPT_ENABLE_BMSK                                         0x1
#define HWIO_TCSR_SS_VMIDMT_CFG_SEC_INTR_ENABLE_CRYPTO0_VMIDMT_GCFGIRPT_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_ADDR                                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x00007000)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_PHYS                                                                             (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00007000)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_RMSK                                                                                 0xffff
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_IN          \
        in_dword_masked(HWIO_TCSR_SPDM_CNT_CLK_CTRL_ADDR, HWIO_TCSR_SPDM_CNT_CLK_CTRL_RMSK)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPDM_CNT_CLK_CTRL_ADDR, m)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_OUT(v)      \
        out_dword(HWIO_TCSR_SPDM_CNT_CLK_CTRL_ADDR,v)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPDM_CNT_CLK_CTRL_ADDR,m,v,HWIO_TCSR_SPDM_CNT_CLK_CTRL_IN)
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_SPDM_CNT_CLK_MUX_SEL_BMSK                                                            0xffff
#define HWIO_TCSR_SPDM_CNT_CLK_CTRL_SPDM_CNT_CLK_MUX_SEL_SHFT                                                               0x0

#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_ADDR                                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x0000705c)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_PHYS                                                                             (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000705c)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_RMSK                                                                             0xffffffff
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_IN          \
        in_dword_masked(HWIO_TCSR_SPDM_WRP_CTI_CTL0_ADDR, HWIO_TCSR_SPDM_WRP_CTI_CTL0_RMSK)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPDM_WRP_CTI_CTL0_ADDR, m)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_OUT(v)      \
        out_dword(HWIO_TCSR_SPDM_WRP_CTI_CTL0_ADDR,v)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPDM_WRP_CTI_CTL0_ADDR,m,v,HWIO_TCSR_SPDM_WRP_CTI_CTL0_IN)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_SPDM_WRP_CTI_CTL0_BMSK                                                           0xffffffff
#define HWIO_TCSR_SPDM_WRP_CTI_CTL0_SPDM_WRP_CTI_CTL0_SHFT                                                                  0x0

#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_ADDR                                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x00007060)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_PHYS                                                                             (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00007060)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_RMSK                                                                             0xffffffff
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_IN          \
        in_dword_masked(HWIO_TCSR_SPDM_WRP_CTI_CTL1_ADDR, HWIO_TCSR_SPDM_WRP_CTI_CTL1_RMSK)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPDM_WRP_CTI_CTL1_ADDR, m)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_OUT(v)      \
        out_dword(HWIO_TCSR_SPDM_WRP_CTI_CTL1_ADDR,v)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPDM_WRP_CTI_CTL1_ADDR,m,v,HWIO_TCSR_SPDM_WRP_CTI_CTL1_IN)
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_SPDM_WRP_CTI_CTL1_BMSK                                                           0xffffffff
#define HWIO_TCSR_SPDM_WRP_CTI_CTL1_SPDM_WRP_CTI_CTL1_SHFT                                                                  0x0

#define HWIO_TCSR_SOC_HW_VERSION_ADDR                                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x00008000)
#define HWIO_TCSR_SOC_HW_VERSION_PHYS                                                                                (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00008000)
#define HWIO_TCSR_SOC_HW_VERSION_RMSK                                                                                0xffffffff
#define HWIO_TCSR_SOC_HW_VERSION_IN          \
        in_dword_masked(HWIO_TCSR_SOC_HW_VERSION_ADDR, HWIO_TCSR_SOC_HW_VERSION_RMSK)
#define HWIO_TCSR_SOC_HW_VERSION_INM(m)      \
        in_dword_masked(HWIO_TCSR_SOC_HW_VERSION_ADDR, m)
#define HWIO_TCSR_SOC_HW_VERSION_FAMILY_NUMBER_BMSK                                                                  0xf0000000
#define HWIO_TCSR_SOC_HW_VERSION_FAMILY_NUMBER_SHFT                                                                        0x1c
#define HWIO_TCSR_SOC_HW_VERSION_DEVICE_NUMBER_BMSK                                                                   0xfff0000
#define HWIO_TCSR_SOC_HW_VERSION_DEVICE_NUMBER_SHFT                                                                        0x10
#define HWIO_TCSR_SOC_HW_VERSION_MAJOR_VERSION_BMSK                                                                      0xff00
#define HWIO_TCSR_SOC_HW_VERSION_MAJOR_VERSION_SHFT                                                                         0x8
#define HWIO_TCSR_SOC_HW_VERSION_MINOR_VERSION_BMSK                                                                        0xff
#define HWIO_TCSR_SOC_HW_VERSION_MINOR_VERSION_SHFT                                                                         0x0

#define HWIO_TCSR_SOC_EMULATION_TYPE_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00008004)
#define HWIO_TCSR_SOC_EMULATION_TYPE_PHYS                                                                            (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00008004)
#define HWIO_TCSR_SOC_EMULATION_TYPE_RMSK                                                                                   0x3
#define HWIO_TCSR_SOC_EMULATION_TYPE_IN          \
        in_dword_masked(HWIO_TCSR_SOC_EMULATION_TYPE_ADDR, HWIO_TCSR_SOC_EMULATION_TYPE_RMSK)
#define HWIO_TCSR_SOC_EMULATION_TYPE_INM(m)      \
        in_dword_masked(HWIO_TCSR_SOC_EMULATION_TYPE_ADDR, m)
#define HWIO_TCSR_SOC_EMULATION_TYPE_SOC_EMULATION_TYPE_BMSK                                                                0x3
#define HWIO_TCSR_SOC_EMULATION_TYPE_SOC_EMULATION_TYPE_SHFT                                                                0x0

#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_ADDR                                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x00008008)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_PHYS                                                                       (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00008008)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_RMSK                                                                       0xffffffff
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_IN          \
        in_dword_masked(HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_ADDR, HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_RMSK)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_INM(m)      \
        in_dword_masked(HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_ADDR, m)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_OUT(v)      \
        out_dword(HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_ADDR,v)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_ADDR,m,v,HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_IN)
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_FAMILY_NUMBER_BMSK                                                0xf0000000
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_FAMILY_NUMBER_SHFT                                                      0x1c
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_DEVICE_NUMBER_BMSK                                                 0xfff0000
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_DEVICE_NUMBER_SHFT                                                      0x10
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_MAJOR_VERSION_BMSK                                                    0xff00
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_MAJOR_VERSION_SHFT                                                       0x8
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_MINOR_VERSION_BMSK                                                      0xff
#define HWIO_TCSR_SW_WONCE_SOC_HW_VERSION_SW_WONCE_MINOR_VERSION_SHFT                                                       0x0

#define HWIO_TCSR_TIMEOUT_INTR_STATUS_ADDR                                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00008020)
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_PHYS                                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00008020)
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RMSK                                                                           0xffffffff
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_IN          \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_STATUS_ADDR, HWIO_TCSR_TIMEOUT_INTR_STATUS_RMSK)
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_STATUS_ADDR, m)
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_31_TIMEOUT_SLAVE_INTR_BMSK                                             0x80000000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_31_TIMEOUT_SLAVE_INTR_SHFT                                                   0x1f
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_30_TIMEOUT_SLAVE_INTR_BMSK                                             0x40000000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_30_TIMEOUT_SLAVE_INTR_SHFT                                                   0x1e
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_29_TIMEOUT_SLAVE_INTR_BMSK                                             0x20000000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_29_TIMEOUT_SLAVE_INTR_SHFT                                                   0x1d
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_28_TIMEOUT_SLAVE_INTR_BMSK                                             0x10000000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_28_TIMEOUT_SLAVE_INTR_SHFT                                                   0x1c
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_27_TIMEOUT_SLAVE_INTR_BMSK                                              0x8000000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_27_TIMEOUT_SLAVE_INTR_SHFT                                                   0x1b
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_26_TIMEOUT_SLAVE_INTR_BMSK                                              0x4000000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_26_TIMEOUT_SLAVE_INTR_SHFT                                                   0x1a
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_25_TIMEOUT_SLAVE_INTR_BMSK                                              0x2000000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_25_TIMEOUT_SLAVE_INTR_SHFT                                                   0x19
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_WCSS_ECAHB_TSLV_INTR_BMSK                                                       0x1000000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_WCSS_ECAHB_TSLV_INTR_SHFT                                                            0x18
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_LPASS_IRQ_OUT_AHB_TIMEOUT2_BMSK                                                  0x800000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_LPASS_IRQ_OUT_AHB_TIMEOUT2_SHFT                                                      0x17
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_LPASS_IRQ_OUT_AHB_TIMEOUT1_BMSK                                                  0x400000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_LPASS_IRQ_OUT_AHB_TIMEOUT1_SHFT                                                      0x16
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_LPASS_IRQ_OUT_AHB_TIMEOUT0_BMSK                                                  0x200000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_LPASS_IRQ_OUT_AHB_TIMEOUT0_SHFT                                                      0x15
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_WCSS_TCSR_WAHB_TSLV_INTR_BMSK                                                    0x100000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_WCSS_TCSR_WAHB_TSLV_INTR_SHFT                                                        0x14
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_19_TIMEOUT_SLAVE_INTR_BMSK                                                0x80000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_19_TIMEOUT_SLAVE_INTR_SHFT                                                   0x13
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_TURING_IRQ_OUT_AHB_TIMEOUT0_BMSK                                                  0x40000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_TURING_IRQ_OUT_AHB_TIMEOUT0_SHFT                                                     0x12
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_17_TIMEOUT_SLAVE_INTR_BMSK                                                0x20000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_17_TIMEOUT_SLAVE_INTR_SHFT                                                   0x11
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_16_TIMEOUT_SLAVE_INTR_BMSK                                                0x10000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_16_TIMEOUT_SLAVE_INTR_SHFT                                                   0x10
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_15_TIMEOUT_SLAVE_INTR_BMSK                                                 0x8000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_15_TIMEOUT_SLAVE_INTR_SHFT                                                    0xf
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_14_TIMEOUT_SLAVE_INTR_BMSK                                                 0x4000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_14_TIMEOUT_SLAVE_INTR_SHFT                                                    0xe
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_13_TIMEOUT_SLAVE_INTR_BMSK                                                 0x2000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_13_TIMEOUT_SLAVE_INTR_SHFT                                                    0xd
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_12_TIMEOUT_SLAVE_INTR_BMSK                                                 0x1000
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_12_TIMEOUT_SLAVE_INTR_SHFT                                                    0xc
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_WCSS_TCSR_WAPB_TSLV_IRQ_BMSK                                                        0x800
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_WCSS_TCSR_WAPB_TSLV_IRQ_SHFT                                                          0xb
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_MSS_CONFIG_TIMEOUT_SLAVE_IRQ_BMSK                                                   0x400
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_MSS_CONFIG_TIMEOUT_SLAVE_IRQ_SHFT                                                     0xa
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_9_TIMEOUT_SLAVE_INTR_BMSK                                                   0x200
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_9_TIMEOUT_SLAVE_INTR_SHFT                                                     0x9
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_8_TIMEOUT_SLAVE_INTR_BMSK                                                   0x100
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_8_TIMEOUT_SLAVE_INTR_SHFT                                                     0x8
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_7_TIMEOUT_SLAVE_INTR_BMSK                                                    0x80
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_7_TIMEOUT_SLAVE_INTR_SHFT                                                     0x7
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_WCSS_TCSR_NOC_INTR_BMSK                                                              0x40
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_WCSS_TCSR_NOC_INTR_SHFT                                                               0x6
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_5_TIMEOUT_SLAVE_INTR_BMSK                                                    0x20
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_5_TIMEOUT_SLAVE_INTR_SHFT                                                     0x5
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_4_TIMEOUT_SLAVE_INTR_BMSK                                                    0x10
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_4_TIMEOUT_SLAVE_INTR_SHFT                                                     0x4
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_3_TIMEOUT_SLAVE_INTR_BMSK                                                     0x8
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_3_TIMEOUT_SLAVE_INTR_SHFT                                                     0x3
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_2_TIMEOUT_SLAVE_INTR_BMSK                                                     0x4
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_2_TIMEOUT_SLAVE_INTR_SHFT                                                     0x2
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_1_TIMEOUT_SLAVE_INTR_BMSK                                                     0x2
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_1_TIMEOUT_SLAVE_INTR_SHFT                                                     0x1
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_0_TIMEOUT_SLAVE_INTR_BMSK                                                     0x1
#define HWIO_TCSR_TIMEOUT_INTR_STATUS_RESERVE_0_TIMEOUT_SLAVE_INTR_SHFT                                                     0x0

#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_ADDR                                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x00027000)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_PHYS                                                                       (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00027000)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RMSK                                                                       0xffffffff
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_ADDR, HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RMSK)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_ADDR, m)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_ADDR,v)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_ADDR,m,v,HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_IN)
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                  0x80000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x1f
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                  0x40000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x1e
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                  0x20000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x1d
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                  0x10000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x1c
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                   0x8000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x1b
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                   0x4000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x1a
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                   0x2000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x19
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_WCSS_ECAHB_TSLV_INTR_ENABLE_BMSK                                            0x1000000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_WCSS_ECAHB_TSLV_INTR_ENABLE_SHFT                                                 0x18
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_BMSK                                       0x800000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_SHFT                                           0x17
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                                       0x400000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                                           0x16
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                       0x200000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                           0x15
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_WCSS_TCSR_WAHB_TSLV_INTR_ENABLE_BMSK                                         0x100000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_WCSS_TCSR_WAHB_TSLV_INTR_ENABLE_SHFT                                             0x14
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_19_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                     0x80000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_19_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x13
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                       0x40000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                          0x12
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                     0x20000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x11
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                     0x10000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x10
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                      0x8000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0xf
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                      0x4000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0xe
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                      0x2000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0xd
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                      0x1000
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0xc
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_WCSS_TCSR_WAPB_TSLV_IRQ_ENABLE_BMSK                                             0x800
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_WCSS_TCSR_WAPB_TSLV_IRQ_ENABLE_SHFT                                               0xb
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_MSS_CONFIG_TIMEOUT_SLAVE_IRQ_ENABLE_BMSK                                        0x400
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_MSS_CONFIG_TIMEOUT_SLAVE_IRQ_ENABLE_SHFT                                          0xa
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                        0x200
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x9
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                        0x100
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x8
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                         0x80
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x7
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_WCSS_TCSR_NOC_INTR_ENABLE_BMSK                                                   0x40
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_WCSS_TCSR_NOC_INTR_ENABLE_SHFT                                                    0x6
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                         0x20
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x5
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                         0x10
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x4
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                          0x8
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x3
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_2_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                          0x4
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_2_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x2
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_1_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                          0x2
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_1_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x1
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_0_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                          0x1
#define HWIO_TCSR_TIMEOUT_INTR_RPM_ENABLE_RESERVE_0_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x0

#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_ADDR                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x00028000)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_PHYS                                                                      (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00028000)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RMSK                                                                      0xffffffff
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_ADDR, HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RMSK)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_ADDR, m)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_ADDR,v)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_ADDR,m,v,HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_IN)
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                 0x80000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x1f
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                 0x40000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x1e
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                 0x20000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x1d
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                 0x10000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x1c
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                  0x8000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x1b
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                  0x4000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x1a
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                  0x2000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x19
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_WCSS_ECAHB_TSLV_INTR_ENABLE_BMSK                                           0x1000000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_WCSS_ECAHB_TSLV_INTR_ENABLE_SHFT                                                0x18
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_BMSK                                      0x800000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_SHFT                                          0x17
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                                      0x400000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                                          0x16
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                      0x200000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                          0x15
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_WCSS_TCSR_WAHB_TSLV_INTR_ENABLE_BMSK                                        0x100000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_WCSS_TCSR_WAHB_TSLV_INTR_ENABLE_SHFT                                            0x14
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_19_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                    0x80000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_19_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x13
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                      0x40000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                         0x12
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                    0x20000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x11
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                    0x10000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x10
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                     0x8000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0xf
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                     0x4000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0xe
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                     0x2000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0xd
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                     0x1000
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0xc
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_WCSS_TCSR_WAPB_TSLV_IRQ_ENABLE_BMSK                                            0x800
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_WCSS_TCSR_WAPB_TSLV_IRQ_ENABLE_SHFT                                              0xb
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_MSS_CONFIG_TIMEOUT_SLAVE_IRQ_ENABLE_BMSK                                       0x400
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_MSS_CONFIG_TIMEOUT_SLAVE_IRQ_ENABLE_SHFT                                         0xa
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                       0x200
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0x9
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                       0x100
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0x8
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                        0x80
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0x7
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_WCSS_TCSR_NOC_INTR_ENABLE_BMSK                                                  0x40
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_WCSS_TCSR_NOC_INTR_ENABLE_SHFT                                                   0x6
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                        0x20
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0x5
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                        0x10
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0x4
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                         0x8
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0x3
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_2_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                         0x4
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_2_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0x2
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_1_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                         0x2
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_1_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0x1
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_0_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                         0x1
#define HWIO_TCSR_TIMEOUT_INTR_HMSS_ENABLE_RESERVE_0_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0x0

#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_ADDR                                                                     (TCSR_TCSR_REGS_REG_BASE      + 0x00029000)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_PHYS                                                                     (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029000)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RMSK                                                                     0xffffffff
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_ADDR, HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RMSK)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_ADDR, m)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_ADDR,v)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_ADDR,m,v,HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_IN)
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x80000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                      0x1f
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x40000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                      0x1e
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x20000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                      0x1d
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x10000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                      0x1c
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                 0x8000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                      0x1b
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                 0x4000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                      0x1a
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                 0x2000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                      0x19
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_WCSS_ECAHB_TSLV_INTR_ENABLE_BMSK                                          0x1000000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_WCSS_ECAHB_TSLV_INTR_ENABLE_SHFT                                               0x18
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_BMSK                                     0x800000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_SHFT                                         0x17
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                                     0x400000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                                         0x16
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                     0x200000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                         0x15
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_WCSS_TCSR_WAHB_TSLV_INTR_ENABLE_BMSK                                       0x100000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_WCSS_TCSR_WAHB_TSLV_INTR_ENABLE_SHFT                                           0x14
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_19_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                   0x80000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_19_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                      0x13
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                     0x40000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                        0x12
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                   0x20000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                      0x11
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                   0x10000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                      0x10
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                    0x8000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0xf
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                    0x4000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0xe
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                    0x2000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0xd
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                    0x1000
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0xc
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_WCSS_TCSR_WAPB_TSLV_IRQ_ENABLE_BMSK                                           0x800
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_WCSS_TCSR_WAPB_TSLV_IRQ_ENABLE_SHFT                                             0xb
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_MSS_CONFIG_TIMEOUT_SLAVE_IRQ_ENABLE_BMSK                                      0x400
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_MSS_CONFIG_TIMEOUT_SLAVE_IRQ_ENABLE_SHFT                                        0xa
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                      0x200
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x9
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                      0x100
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x8
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                       0x80
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x7
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_WCSS_TCSR_NOC_INTR_ENABLE_BMSK                                                 0x40
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_WCSS_TCSR_NOC_INTR_ENABLE_SHFT                                                  0x6
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                       0x20
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x5
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                       0x10
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x4
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                        0x8
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x3
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_2_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                        0x4
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_2_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x2
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_1_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                        0x2
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_1_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x1
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_0_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                        0x1
#define HWIO_TCSR_TIMEOUT_INTR_LPASS_ENABLE_RESERVE_0_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x0

#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_ADDR                                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x0002a000)
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_PHYS                                                                       (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002a000)
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RMSK                                                                       0xffffffff
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_ADDR, HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RMSK)
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_ADDR, m)
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_ADDR,v)
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_ADDR,m,v,HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_IN)
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                  0x80000000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x1f
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                  0x40000000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x1e
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                  0x20000000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x1d
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                  0x10000000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x1c
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                   0x8000000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x1b
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                   0x4000000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x1a
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                   0x2000000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x19
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_WCSS_ECAHB_TSLV_INTR_ENABLE_BMSK                                            0x1000000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_WCSS_ECAHB_TSLV_INTR_ENABLE_SHFT                                                 0x18
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_BMSK                                       0x800000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_SHFT                                           0x17
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                                       0x400000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                                           0x16
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                       0x200000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                           0x15
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_WCSS_TCSR_WAHB_TSLV_INTR_ENABLE_BMSK                                         0x100000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_WCSS_TCSR_WAHB_TSLV_INTR_ENABLE_SHFT                                             0x14
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_19_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                     0x80000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_19_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x13
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                       0x40000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                          0x12
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                     0x20000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x11
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                     0x10000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                        0x10
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                      0x8000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0xf
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                      0x4000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0xe
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                      0x2000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0xd
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                      0x1000
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                         0xc
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_WCSS_TCSR_WAPB_TSLV_IRQ_ENABLE_BMSK                                             0x800
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_WCSS_TCSR_WAPB_TSLV_IRQ_ENABLE_SHFT                                               0xb
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_MSS_CONFIG_TIMEOUT_SLAVE_IRQ_ENABLE_BMSK                                        0x400
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_MSS_CONFIG_TIMEOUT_SLAVE_IRQ_ENABLE_SHFT                                          0xa
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                        0x200
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x9
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                        0x100
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x8
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                         0x80
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x7
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_WCSS_TCSR_NOC_INTR_ENABLE_BMSK                                                   0x40
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_WCSS_TCSR_NOC_INTR_ENABLE_SHFT                                                    0x6
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                         0x20
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x5
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                         0x10
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x4
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                          0x8
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x3
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_2_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                          0x4
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_2_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x2
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_1_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                          0x2
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_1_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x1
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_0_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                          0x1
#define HWIO_TCSR_TIMEOUT_INTR_MSS_ENABLE_RESERVE_0_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                          0x0

#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_ADDR                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x0002b000)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_PHYS                                                                    (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b000)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RMSK                                                                    0xffffffff
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_ADDR, HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RMSK)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_ADDR, m)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_ADDR,v)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_ADDR,m,v,HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_IN)
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x80000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_31_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                     0x1f
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x40000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_30_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                     0x1e
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x20000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_29_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                     0x1d
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                               0x10000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_28_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                     0x1c
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x8000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_27_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                     0x1b
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x4000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_26_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                     0x1a
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                0x2000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_25_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                     0x19
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_WCSS_ECAHB_TSLV_INTR_ENABLE_BMSK                                         0x1000000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_WCSS_ECAHB_TSLV_INTR_ENABLE_SHFT                                              0x18
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_BMSK                                    0x800000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT2_ENABLE_SHFT                                        0x17
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_BMSK                                    0x400000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT1_ENABLE_SHFT                                        0x16
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                    0x200000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_LPASS_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                        0x15
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_WCSS_TCSR_WAHB_TSLV_INTR_ENABLE_BMSK                                      0x100000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_WCSS_TCSR_WAHB_TSLV_INTR_ENABLE_SHFT                                          0x14
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_19_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                  0x80000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_19_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                     0x13
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_BMSK                                    0x40000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_TURING_IRQ_OUT_AHB_TIMEOUT0_ENABLE_SHFT                                       0x12
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                  0x20000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_17_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                     0x11
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                  0x10000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_16_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                     0x10
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                   0x8000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_15_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                      0xf
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                   0x4000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_14_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                      0xe
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                   0x2000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_13_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                      0xd
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                   0x1000
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_12_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                      0xc
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_WCSS_TCSR_WAPB_TSLV_IRQ_ENABLE_BMSK                                          0x800
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_WCSS_TCSR_WAPB_TSLV_IRQ_ENABLE_SHFT                                            0xb
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_MSS_CONFIG_TIMEOUT_SLAVE_IRQ_ENABLE_BMSK                                     0x400
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_MSS_CONFIG_TIMEOUT_SLAVE_IRQ_ENABLE_SHFT                                       0xa
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                     0x200
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_9_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x9
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                     0x100
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_8_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x8
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                      0x80
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_7_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x7
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_WCSS_TCSR_NOC_INTR_ENABLE_BMSK                                                0x40
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_WCSS_TCSR_NOC_INTR_ENABLE_SHFT                                                 0x6
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                      0x20
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_5_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x5
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                      0x10
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_4_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x4
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                       0x8
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_3_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x3
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_2_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                       0x4
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_2_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x2
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_1_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                       0x2
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_1_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x1
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_0_TIMEOUT_SLAVE_INTR_ENABLE_BMSK                                       0x1
#define HWIO_TCSR_TIMEOUT_INTR_TURING_ENABLE_RESERVE_0_TIMEOUT_SLAVE_INTR_ENABLE_SHFT                                       0x0

#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_ADDR                                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x00008070)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_PHYS                                                                       (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00008070)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_RMSK                                                                              0x1
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_IN          \
        in_dword_masked(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_ADDR, HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_RMSK)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_INM(m)      \
        in_dword_masked(HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_ADDR, m)
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_SRAM_REDUNDANCY_CRC_ERR_BMSK                                                      0x1
#define HWIO_TCSR_SRAM_REDUNDANCY_CRC_ERR_SRAM_REDUNDANCY_CRC_ERR_SHFT                                                      0x0

#define HWIO_TCSR_TCSR_CLK_EN_ADDR                                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0000907c)
#define HWIO_TCSR_TCSR_CLK_EN_PHYS                                                                                   (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000907c)
#define HWIO_TCSR_TCSR_CLK_EN_RMSK                                                                                          0x1
#define HWIO_TCSR_TCSR_CLK_EN_IN          \
        in_dword_masked(HWIO_TCSR_TCSR_CLK_EN_ADDR, HWIO_TCSR_TCSR_CLK_EN_RMSK)
#define HWIO_TCSR_TCSR_CLK_EN_INM(m)      \
        in_dword_masked(HWIO_TCSR_TCSR_CLK_EN_ADDR, m)
#define HWIO_TCSR_TCSR_CLK_EN_OUT(v)      \
        out_dword(HWIO_TCSR_TCSR_CLK_EN_ADDR,v)
#define HWIO_TCSR_TCSR_CLK_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TCSR_CLK_EN_ADDR,m,v,HWIO_TCSR_TCSR_CLK_EN_IN)
#define HWIO_TCSR_TCSR_CLK_EN_TCSR_CLK_EN_BMSK                                                                              0x1
#define HWIO_TCSR_TCSR_CLK_EN_TCSR_CLK_EN_SHFT                                                                              0x0

#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x0000a100)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_PHYS                                                                          (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000a100)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_RMSK                                                                                 0x1
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_IN          \
        in_dword_masked(HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_ADDR, HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_RMSK)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_INM(m)      \
        in_dword_masked(HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_ADDR, m)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_OUT(v)      \
        out_dword(HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_ADDR,v)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_ADDR,m,v,HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_IN)
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_TCSR_IPA_WARMBOOT_EN_BMSK                                                            0x1
#define HWIO_TCSR_TCSR_IPA_WARMBOOT_EN_TCSR_IPA_WARMBOOT_EN_SHFT                                                            0x0

#define HWIO_TCSR_SYS_POWER_CTRL_ADDR                                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x0000a000)
#define HWIO_TCSR_SYS_POWER_CTRL_PHYS                                                                                (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000a000)
#define HWIO_TCSR_SYS_POWER_CTRL_RMSK                                                                                    0xffff
#define HWIO_TCSR_SYS_POWER_CTRL_IN          \
        in_dword_masked(HWIO_TCSR_SYS_POWER_CTRL_ADDR, HWIO_TCSR_SYS_POWER_CTRL_RMSK)
#define HWIO_TCSR_SYS_POWER_CTRL_INM(m)      \
        in_dword_masked(HWIO_TCSR_SYS_POWER_CTRL_ADDR, m)
#define HWIO_TCSR_SYS_POWER_CTRL_OUT(v)      \
        out_dword(HWIO_TCSR_SYS_POWER_CTRL_ADDR,v)
#define HWIO_TCSR_SYS_POWER_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SYS_POWER_CTRL_ADDR,m,v,HWIO_TCSR_SYS_POWER_CTRL_IN)
#define HWIO_TCSR_SYS_POWER_CTRL_SYS_POWER_CTRL_BMSK                                                                     0xffff
#define HWIO_TCSR_SYS_POWER_CTRL_SYS_POWER_CTRL_SHFT                                                                        0x0

#define HWIO_TCSR_USB_CORE_ID_ADDR                                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0000a004)
#define HWIO_TCSR_USB_CORE_ID_PHYS                                                                                   (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000a004)
#define HWIO_TCSR_USB_CORE_ID_RMSK                                                                                          0x3
#define HWIO_TCSR_USB_CORE_ID_IN          \
        in_dword_masked(HWIO_TCSR_USB_CORE_ID_ADDR, HWIO_TCSR_USB_CORE_ID_RMSK)
#define HWIO_TCSR_USB_CORE_ID_INM(m)      \
        in_dword_masked(HWIO_TCSR_USB_CORE_ID_ADDR, m)
#define HWIO_TCSR_USB_CORE_ID_OUT(v)      \
        out_dword(HWIO_TCSR_USB_CORE_ID_ADDR,v)
#define HWIO_TCSR_USB_CORE_ID_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_USB_CORE_ID_ADDR,m,v,HWIO_TCSR_USB_CORE_ID_IN)
#define HWIO_TCSR_USB_CORE_ID_USB_CORE_ID_BMSK                                                                              0x3
#define HWIO_TCSR_USB_CORE_ID_USB_CORE_ID_SHFT                                                                              0x0

#define HWIO_TCSR_SPARE_REG0_ADDR                                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x0000a044)
#define HWIO_TCSR_SPARE_REG0_PHYS                                                                                    (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000a044)
#define HWIO_TCSR_SPARE_REG0_RMSK                                                                                    0xffffffff
#define HWIO_TCSR_SPARE_REG0_IN          \
        in_dword_masked(HWIO_TCSR_SPARE_REG0_ADDR, HWIO_TCSR_SPARE_REG0_RMSK)
#define HWIO_TCSR_SPARE_REG0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPARE_REG0_ADDR, m)
#define HWIO_TCSR_SPARE_REG0_OUT(v)      \
        out_dword(HWIO_TCSR_SPARE_REG0_ADDR,v)
#define HWIO_TCSR_SPARE_REG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPARE_REG0_ADDR,m,v,HWIO_TCSR_SPARE_REG0_IN)
#define HWIO_TCSR_SPARE_REG0_SPARE_REG0_BMSK                                                                         0xffffffff
#define HWIO_TCSR_SPARE_REG0_SPARE_REG0_SHFT                                                                                0x0

#define HWIO_TCSR_SPARE_REG1_ADDR                                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x0000a048)
#define HWIO_TCSR_SPARE_REG1_PHYS                                                                                    (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000a048)
#define HWIO_TCSR_SPARE_REG1_RMSK                                                                                    0xffffffff
#define HWIO_TCSR_SPARE_REG1_IN          \
        in_dword_masked(HWIO_TCSR_SPARE_REG1_ADDR, HWIO_TCSR_SPARE_REG1_RMSK)
#define HWIO_TCSR_SPARE_REG1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPARE_REG1_ADDR, m)
#define HWIO_TCSR_SPARE_REG1_OUT(v)      \
        out_dword(HWIO_TCSR_SPARE_REG1_ADDR,v)
#define HWIO_TCSR_SPARE_REG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPARE_REG1_ADDR,m,v,HWIO_TCSR_SPARE_REG1_IN)
#define HWIO_TCSR_SPARE_REG1_SPARE_REG1_BMSK                                                                         0xffffffff
#define HWIO_TCSR_SPARE_REG1_SPARE_REG1_SHFT                                                                                0x0

#define HWIO_TCSR_SPARE_REG2_ADDR                                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x0000a04c)
#define HWIO_TCSR_SPARE_REG2_PHYS                                                                                    (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000a04c)
#define HWIO_TCSR_SPARE_REG2_RMSK                                                                                          0xff
#define HWIO_TCSR_SPARE_REG2_IN          \
        in_dword_masked(HWIO_TCSR_SPARE_REG2_ADDR, HWIO_TCSR_SPARE_REG2_RMSK)
#define HWIO_TCSR_SPARE_REG2_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPARE_REG2_ADDR, m)
#define HWIO_TCSR_SPARE_REG2_OUT(v)      \
        out_dword(HWIO_TCSR_SPARE_REG2_ADDR,v)
#define HWIO_TCSR_SPARE_REG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPARE_REG2_ADDR,m,v,HWIO_TCSR_SPARE_REG2_IN)
#define HWIO_TCSR_SPARE_REG2_SPARE_REG2_BMSK                                                                               0xff
#define HWIO_TCSR_SPARE_REG2_SPARE_REG2_SHFT                                                                                0x0

#define HWIO_TCSR_SPARE_REG3_ADDR                                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x0000a050)
#define HWIO_TCSR_SPARE_REG3_PHYS                                                                                    (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000a050)
#define HWIO_TCSR_SPARE_REG3_RMSK                                                                                          0xff
#define HWIO_TCSR_SPARE_REG3_IN          \
        in_dword_masked(HWIO_TCSR_SPARE_REG3_ADDR, HWIO_TCSR_SPARE_REG3_RMSK)
#define HWIO_TCSR_SPARE_REG3_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPARE_REG3_ADDR, m)
#define HWIO_TCSR_SPARE_REG3_OUT(v)      \
        out_dword(HWIO_TCSR_SPARE_REG3_ADDR,v)
#define HWIO_TCSR_SPARE_REG3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPARE_REG3_ADDR,m,v,HWIO_TCSR_SPARE_REG3_IN)
#define HWIO_TCSR_SPARE_REG3_SPARE_REG3_BMSK                                                                               0xff
#define HWIO_TCSR_SPARE_REG3_SPARE_REG3_SHFT                                                                                0x0

#define HWIO_TCSR_SPARE_REG4_ADDR                                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x0000a054)
#define HWIO_TCSR_SPARE_REG4_PHYS                                                                                    (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000a054)
#define HWIO_TCSR_SPARE_REG4_RMSK                                                                                          0xff
#define HWIO_TCSR_SPARE_REG4_IN          \
        in_dword_masked(HWIO_TCSR_SPARE_REG4_ADDR, HWIO_TCSR_SPARE_REG4_RMSK)
#define HWIO_TCSR_SPARE_REG4_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPARE_REG4_ADDR, m)
#define HWIO_TCSR_SPARE_REG4_OUT(v)      \
        out_dword(HWIO_TCSR_SPARE_REG4_ADDR,v)
#define HWIO_TCSR_SPARE_REG4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPARE_REG4_ADDR,m,v,HWIO_TCSR_SPARE_REG4_IN)
#define HWIO_TCSR_SPARE_REG4_SPARE_REG4_BMSK                                                                               0xff
#define HWIO_TCSR_SPARE_REG4_SPARE_REG4_SHFT                                                                                0x0

#define HWIO_TCSR_SPARE_REG5_ADDR                                                                                    (TCSR_TCSR_REGS_REG_BASE      + 0x0000a058)
#define HWIO_TCSR_SPARE_REG5_PHYS                                                                                    (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000a058)
#define HWIO_TCSR_SPARE_REG5_RMSK                                                                                          0xff
#define HWIO_TCSR_SPARE_REG5_IN          \
        in_dword_masked(HWIO_TCSR_SPARE_REG5_ADDR, HWIO_TCSR_SPARE_REG5_RMSK)
#define HWIO_TCSR_SPARE_REG5_INM(m)      \
        in_dword_masked(HWIO_TCSR_SPARE_REG5_ADDR, m)
#define HWIO_TCSR_SPARE_REG5_OUT(v)      \
        out_dword(HWIO_TCSR_SPARE_REG5_ADDR,v)
#define HWIO_TCSR_SPARE_REG5_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SPARE_REG5_ADDR,m,v,HWIO_TCSR_SPARE_REG5_IN)
#define HWIO_TCSR_SPARE_REG5_SPARE_REG5_BMSK                                                                               0xff
#define HWIO_TCSR_SPARE_REG5_SPARE_REG5_SHFT                                                                                0x0

#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00021014)
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_PHYS                                                                  (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00021014)
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_RMSK                                                                    0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_ADDR, HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_TOP_QUPV3_0_GSI_SP_INT_SEL_OUT_0_BMSK                                   0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_TOP_QUPV3_0_GSI_SP_INT_SEL_OUT_0_SHFT                                        0x8
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_TOP_QUPV3_0_SE_SP_INT_SEL_OUT_0_BMSK                                        0xff
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_0_TOP_QUPV3_0_SE_SP_INT_SEL_OUT_0_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00021010)
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_PHYS                                                                  (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00021010)
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_RMSK                                                                     0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_ADDR, HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_TOP_QUPV3_1_GSI_SP_INT_SEL_OUT_0_BMSK                                    0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_TOP_QUPV3_1_GSI_SP_INT_SEL_OUT_0_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_TOP_QUPV3_1_SE_SP_INT_SEL_OUT_0_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_0_TOP_QUPV3_1_SE_SP_INT_SEL_OUT_0_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00021020)
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_PHYS                                                                  (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00021020)
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_RMSK                                                                     0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_ADDR, HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_TOP_QUPV3_2_GSI_SP_INT_SEL_OUT_0_BMSK                                    0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_TOP_QUPV3_2_GSI_SP_INT_SEL_OUT_0_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_TOP_QUPV3_2_SE_SP_INT_SEL_OUT_0_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_0_TOP_QUPV3_2_SE_SP_INT_SEL_OUT_0_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x0002101c)
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_PHYS                                                                  (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002101c)
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_RMSK                                                                    0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_ADDR, HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_TOP_QUPV3_0_GSI_SP_INT_SEL_OUT_1_BMSK                                   0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_TOP_QUPV3_0_GSI_SP_INT_SEL_OUT_1_SHFT                                        0x8
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_TOP_QUPV3_0_SE_SP_INT_SEL_OUT_1_BMSK                                        0xff
#define HWIO_TCSR_TOP_QUPV3_0_SP_INT_SEL_OUT_1_TOP_QUPV3_0_SE_SP_INT_SEL_OUT_1_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00021018)
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_PHYS                                                                  (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00021018)
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_RMSK                                                                     0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_ADDR, HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_TOP_QUPV3_1_GSI_SP_INT_SEL_OUT_1_BMSK                                    0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_TOP_QUPV3_1_GSI_SP_INT_SEL_OUT_1_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_TOP_QUPV3_1_SE_SP_INT_SEL_OUT_1_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_1_SP_INT_SEL_OUT_1_TOP_QUPV3_1_SE_SP_INT_SEL_OUT_1_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00021024)
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_PHYS                                                                  (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00021024)
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_RMSK                                                                     0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_ADDR, HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_TOP_QUPV3_2_GSI_SP_INT_SEL_OUT_1_BMSK                                    0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_TOP_QUPV3_2_GSI_SP_INT_SEL_OUT_1_SHFT                                        0x6
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_TOP_QUPV3_2_SE_SP_INT_SEL_OUT_1_BMSK                                        0x3f
#define HWIO_TCSR_TOP_QUPV3_2_SP_INT_SEL_OUT_1_TOP_QUPV3_2_SE_SP_INT_SEL_OUT_1_SHFT                                         0x0

#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b000)
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_PHYS                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000b000)
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_RMSK                                                                   0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_ADDR, HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_TOP_QUPV3_0_GSI_SSC_INT_SEL_OUT_0_BMSK                                 0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_TOP_QUPV3_0_GSI_SSC_INT_SEL_OUT_0_SHFT                                      0x8
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_TOP_QUPV3_0_SE_SSC_INT_SEL_OUT_0_BMSK                                      0xff
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_0_TOP_QUPV3_0_SE_SSC_INT_SEL_OUT_0_SHFT                                       0x0

#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b004)
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_PHYS                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000b004)
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_RMSK                                                                    0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_ADDR, HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_TOP_QUPV3_1_GSI_SSC_INT_SEL_OUT_0_BMSK                                  0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_TOP_QUPV3_1_GSI_SSC_INT_SEL_OUT_0_SHFT                                      0x6
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_TOP_QUPV3_1_SE_SSC_INT_SEL_OUT_0_BMSK                                      0x3f
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_0_TOP_QUPV3_1_SE_SSC_INT_SEL_OUT_0_SHFT                                       0x0

#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b008)
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_PHYS                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000b008)
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_RMSK                                                                    0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_ADDR, HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_TOP_QUPV3_2_GSI_SSC_INT_SEL_OUT_0_BMSK                                  0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_TOP_QUPV3_2_GSI_SSC_INT_SEL_OUT_0_SHFT                                      0x6
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_TOP_QUPV3_2_SE_SSC_INT_SEL_OUT_0_BMSK                                      0x3f
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_0_TOP_QUPV3_2_SE_SSC_INT_SEL_OUT_0_SHFT                                       0x0

#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b010)
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_PHYS                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000b010)
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_RMSK                                                                   0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_ADDR, HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_TOP_QUPV3_0_GSI_SSC_INT_SEL_OUT_1_BMSK                                 0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_TOP_QUPV3_0_GSI_SSC_INT_SEL_OUT_1_SHFT                                      0x8
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_TOP_QUPV3_0_SE_SSC_INT_SEL_OUT_1_BMSK                                      0xff
#define HWIO_TCSR_TOP_QUPV3_0_SSC_INT_SEL_OUT_1_TOP_QUPV3_0_SE_SSC_INT_SEL_OUT_1_SHFT                                       0x0

#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b014)
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_PHYS                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000b014)
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_RMSK                                                                    0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_ADDR, HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_TOP_QUPV3_1_GSI_SSC_INT_SEL_OUT_1_BMSK                                  0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_TOP_QUPV3_1_GSI_SSC_INT_SEL_OUT_1_SHFT                                      0x6
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_TOP_QUPV3_1_SE_SSC_INT_SEL_OUT_1_BMSK                                      0x3f
#define HWIO_TCSR_TOP_QUPV3_1_SSC_INT_SEL_OUT_1_TOP_QUPV3_1_SE_SSC_INT_SEL_OUT_1_SHFT                                       0x0

#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000b018)
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_PHYS                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000b018)
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_RMSK                                                                    0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_ADDR, HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_TOP_QUPV3_2_GSI_SSC_INT_SEL_OUT_1_BMSK                                  0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_TOP_QUPV3_2_GSI_SSC_INT_SEL_OUT_1_SHFT                                      0x6
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_TOP_QUPV3_2_SE_SSC_INT_SEL_OUT_1_BMSK                                      0x3f
#define HWIO_TCSR_TOP_QUPV3_2_SSC_INT_SEL_OUT_1_TOP_QUPV3_2_SE_SSC_INT_SEL_OUT_1_SHFT                                       0x0

#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0002a004)
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_PHYS                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002a004)
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_RMSK                                                                   0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_ADDR, HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_TOP_QUPV3_0_GSI_MSS_INT_SEL_OUT_0_BMSK                                 0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_TOP_QUPV3_0_GSI_MSS_INT_SEL_OUT_0_SHFT                                      0x8
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_TOP_QUPV3_0_SE_MSS_INT_SEL_OUT_0_BMSK                                      0xff
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_0_TOP_QUPV3_0_SE_MSS_INT_SEL_OUT_0_SHFT                                       0x0

#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0002a008)
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_PHYS                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002a008)
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_RMSK                                                                    0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_ADDR, HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_TOP_QUPV3_1_GSI_MSS_INT_SEL_OUT_0_BMSK                                  0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_TOP_QUPV3_1_GSI_MSS_INT_SEL_OUT_0_SHFT                                      0x6
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_TOP_QUPV3_1_SE_MSS_INT_SEL_OUT_0_BMSK                                      0x3f
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_0_TOP_QUPV3_1_SE_MSS_INT_SEL_OUT_0_SHFT                                       0x0

#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0002a00c)
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_PHYS                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002a00c)
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_RMSK                                                                    0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_ADDR, HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_TOP_QUPV3_2_GSI_MSS_INT_SEL_OUT_0_BMSK                                  0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_TOP_QUPV3_2_GSI_MSS_INT_SEL_OUT_0_SHFT                                      0x6
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_TOP_QUPV3_2_SE_MSS_INT_SEL_OUT_0_BMSK                                      0x3f
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_0_TOP_QUPV3_2_SE_MSS_INT_SEL_OUT_0_SHFT                                       0x0

#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0002a010)
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_PHYS                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002a010)
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_RMSK                                                                   0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_ADDR, HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_TOP_QUPV3_0_GSI_MSS_INT_SEL_OUT_1_BMSK                                 0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_TOP_QUPV3_0_GSI_MSS_INT_SEL_OUT_1_SHFT                                      0x8
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_TOP_QUPV3_0_SE_MSS_INT_SEL_OUT_1_BMSK                                      0xff
#define HWIO_TCSR_TOP_QUPV3_0_MSS_INT_SEL_OUT_1_TOP_QUPV3_0_SE_MSS_INT_SEL_OUT_1_SHFT                                       0x0

#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0002a014)
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_PHYS                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002a014)
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_RMSK                                                                    0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_ADDR, HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_TOP_QUPV3_1_GSI_MSS_INT_SEL_OUT_1_BMSK                                  0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_TOP_QUPV3_1_GSI_MSS_INT_SEL_OUT_1_SHFT                                      0x6
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_TOP_QUPV3_1_SE_MSS_INT_SEL_OUT_1_BMSK                                      0x3f
#define HWIO_TCSR_TOP_QUPV3_1_MSS_INT_SEL_OUT_1_TOP_QUPV3_1_SE_MSS_INT_SEL_OUT_1_SHFT                                       0x0

#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0002a018)
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_PHYS                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002a018)
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_RMSK                                                                    0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_ADDR, HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_TOP_QUPV3_2_GSI_MSS_INT_SEL_OUT_1_BMSK                                  0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_TOP_QUPV3_2_GSI_MSS_INT_SEL_OUT_1_SHFT                                      0x6
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_TOP_QUPV3_2_SE_MSS_INT_SEL_OUT_1_BMSK                                      0x3f
#define HWIO_TCSR_TOP_QUPV3_2_MSS_INT_SEL_OUT_1_TOP_QUPV3_2_SE_MSS_INT_SEL_OUT_1_SHFT                                       0x0

#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0002a0c0)
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_PHYS                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002a0c0)
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_RMSK                                                                    0x7ffff
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_ADDR, HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_SSC_QUPV3_0_GSI_MSS_INT_SEL_OUT_0_BMSK                                  0x7ffc0
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_SSC_QUPV3_0_GSI_MSS_INT_SEL_OUT_0_SHFT                                      0x6
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_SSC_QUPV3_0_SE_MSS_INT_SEL_OUT_0_BMSK                                      0x3f
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_0_SSC_QUPV3_0_SE_MSS_INT_SEL_OUT_0_SHFT                                       0x0

#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_ADDR                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0002a0c4)
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_PHYS                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002a0c4)
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_RMSK                                                                    0x7ffff
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_ADDR, HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_SSC_QUPV3_0_GSI_MSS_INT_SEL_OUT_1_BMSK                                  0x7ffc0
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_SSC_QUPV3_0_GSI_MSS_INT_SEL_OUT_1_SHFT                                      0x6
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_SSC_QUPV3_0_SE_MSS_INT_SEL_OUT_1_BMSK                                      0x3f
#define HWIO_TCSR_SSC_QUPV3_0_MSS_INT_SEL_OUT_1_SSC_QUPV3_0_SE_MSS_INT_SEL_OUT_1_SHFT                                       0x0

#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029004)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029004)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_RMSK                                                                 0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_ADDR, HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_TOP_QUPV3_0_GSI_LPASS_INT_SEL_OUT_0_BMSK                             0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_TOP_QUPV3_0_GSI_LPASS_INT_SEL_OUT_0_SHFT                                  0x8
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_TOP_QUPV3_0_SE_LPASS_INT_SEL_OUT_0_BMSK                                  0xff
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_0_TOP_QUPV3_0_SE_LPASS_INT_SEL_OUT_0_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029008)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029008)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_RMSK                                                                  0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_ADDR, HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_TOP_QUPV3_1_GSI_LPASS_INT_SEL_OUT_0_BMSK                              0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_TOP_QUPV3_1_GSI_LPASS_INT_SEL_OUT_0_SHFT                                  0x6
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_TOP_QUPV3_1_SE_LPASS_INT_SEL_OUT_0_BMSK                                  0x3f
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_0_TOP_QUPV3_1_SE_LPASS_INT_SEL_OUT_0_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0002900c)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002900c)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_RMSK                                                                  0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_ADDR, HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_TOP_QUPV3_2_GSI_LPASS_INT_SEL_OUT_0_BMSK                              0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_TOP_QUPV3_2_GSI_LPASS_INT_SEL_OUT_0_SHFT                                  0x6
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_TOP_QUPV3_2_SE_LPASS_INT_SEL_OUT_0_BMSK                                  0x3f
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_0_TOP_QUPV3_2_SE_LPASS_INT_SEL_OUT_0_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029010)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029010)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_RMSK                                                                 0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_ADDR, HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_TOP_QUPV3_0_GSI_LPASS_INT_SEL_OUT_1_BMSK                             0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_TOP_QUPV3_0_GSI_LPASS_INT_SEL_OUT_1_SHFT                                  0x8
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_TOP_QUPV3_0_SE_LPASS_INT_SEL_OUT_1_BMSK                                  0xff
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_1_TOP_QUPV3_0_SE_LPASS_INT_SEL_OUT_1_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029014)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029014)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_RMSK                                                                  0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_ADDR, HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_TOP_QUPV3_1_GSI_LPASS_INT_SEL_OUT_1_BMSK                              0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_TOP_QUPV3_1_GSI_LPASS_INT_SEL_OUT_1_SHFT                                  0x6
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_TOP_QUPV3_1_SE_LPASS_INT_SEL_OUT_1_BMSK                                  0x3f
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_1_TOP_QUPV3_1_SE_LPASS_INT_SEL_OUT_1_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029018)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029018)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_RMSK                                                                  0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_ADDR, HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_TOP_QUPV3_2_GSI_LPASS_INT_SEL_OUT_1_BMSK                              0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_TOP_QUPV3_2_GSI_LPASS_INT_SEL_OUT_1_SHFT                                  0x6
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_TOP_QUPV3_2_SE_LPASS_INT_SEL_OUT_1_BMSK                                  0x3f
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_1_TOP_QUPV3_2_SE_LPASS_INT_SEL_OUT_1_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0002901c)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002901c)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_RMSK                                                                 0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_ADDR, HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_IN)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_TOP_QUPV3_0_GSI_LPASS_INT_SEL_OUT_2_BMSK                             0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_TOP_QUPV3_0_GSI_LPASS_INT_SEL_OUT_2_SHFT                                  0x8
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_TOP_QUPV3_0_SE_LPASS_INT_SEL_OUT_2_BMSK                                  0xff
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_2_TOP_QUPV3_0_SE_LPASS_INT_SEL_OUT_2_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029020)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029020)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_RMSK                                                                  0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_ADDR, HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_IN)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_TOP_QUPV3_1_GSI_LPASS_INT_SEL_OUT_2_BMSK                              0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_TOP_QUPV3_1_GSI_LPASS_INT_SEL_OUT_2_SHFT                                  0x6
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_TOP_QUPV3_1_SE_LPASS_INT_SEL_OUT_2_BMSK                                  0x3f
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_2_TOP_QUPV3_1_SE_LPASS_INT_SEL_OUT_2_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029024)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029024)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_RMSK                                                                  0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_ADDR, HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_IN)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_TOP_QUPV3_2_GSI_LPASS_INT_SEL_OUT_2_BMSK                              0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_TOP_QUPV3_2_GSI_LPASS_INT_SEL_OUT_2_SHFT                                  0x6
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_TOP_QUPV3_2_SE_LPASS_INT_SEL_OUT_2_BMSK                                  0x3f
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_2_TOP_QUPV3_2_SE_LPASS_INT_SEL_OUT_2_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029028)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029028)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_RMSK                                                                 0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_ADDR, HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_IN)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_TOP_QUPV3_0_GSI_LPASS_INT_SEL_OUT_3_BMSK                             0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_TOP_QUPV3_0_GSI_LPASS_INT_SEL_OUT_3_SHFT                                  0x8
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_TOP_QUPV3_0_SE_LPASS_INT_SEL_OUT_3_BMSK                                  0xff
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_3_TOP_QUPV3_0_SE_LPASS_INT_SEL_OUT_3_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0002902c)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002902c)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_RMSK                                                                  0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_ADDR, HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_IN)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_TOP_QUPV3_1_GSI_LPASS_INT_SEL_OUT_3_BMSK                              0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_TOP_QUPV3_1_GSI_LPASS_INT_SEL_OUT_3_SHFT                                  0x6
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_TOP_QUPV3_1_SE_LPASS_INT_SEL_OUT_3_BMSK                                  0x3f
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_3_TOP_QUPV3_1_SE_LPASS_INT_SEL_OUT_3_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029030)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029030)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_RMSK                                                                  0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_ADDR, HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_IN)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_TOP_QUPV3_2_GSI_LPASS_INT_SEL_OUT_3_BMSK                              0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_TOP_QUPV3_2_GSI_LPASS_INT_SEL_OUT_3_SHFT                                  0x6
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_TOP_QUPV3_2_SE_LPASS_INT_SEL_OUT_3_BMSK                                  0x3f
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_3_TOP_QUPV3_2_SE_LPASS_INT_SEL_OUT_3_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029034)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029034)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_RMSK                                                                 0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_ADDR, HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_IN)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_TOP_QUPV3_0_GSI_LPASS_INT_SEL_OUT_4_BMSK                             0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_TOP_QUPV3_0_GSI_LPASS_INT_SEL_OUT_4_SHFT                                  0x8
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_TOP_QUPV3_0_SE_LPASS_INT_SEL_OUT_4_BMSK                                  0xff
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_4_TOP_QUPV3_0_SE_LPASS_INT_SEL_OUT_4_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029038)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029038)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_RMSK                                                                  0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_ADDR, HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_IN)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_TOP_QUPV3_1_GSI_LPASS_INT_SEL_OUT_4_BMSK                              0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_TOP_QUPV3_1_GSI_LPASS_INT_SEL_OUT_4_SHFT                                  0x6
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_TOP_QUPV3_1_SE_LPASS_INT_SEL_OUT_4_BMSK                                  0x3f
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_4_TOP_QUPV3_1_SE_LPASS_INT_SEL_OUT_4_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0002903c)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002903c)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_RMSK                                                                  0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_ADDR, HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_IN)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_TOP_QUPV3_2_GSI_LPASS_INT_SEL_OUT_4_BMSK                              0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_TOP_QUPV3_2_GSI_LPASS_INT_SEL_OUT_4_SHFT                                  0x6
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_TOP_QUPV3_2_SE_LPASS_INT_SEL_OUT_4_BMSK                                  0x3f
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_4_TOP_QUPV3_2_SE_LPASS_INT_SEL_OUT_4_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029040)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029040)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_RMSK                                                                 0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_ADDR, HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_IN)
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_TOP_QUPV3_0_GSI_LPASS_INT_SEL_OUT_5_BMSK                             0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_TOP_QUPV3_0_GSI_LPASS_INT_SEL_OUT_5_SHFT                                  0x8
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_TOP_QUPV3_0_SE_LPASS_INT_SEL_OUT_5_BMSK                                  0xff
#define HWIO_TCSR_TOP_QUPV3_0_LPASS_INT_SEL_OUT_5_TOP_QUPV3_0_SE_LPASS_INT_SEL_OUT_5_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029044)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029044)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_RMSK                                                                  0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_ADDR, HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_IN)
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_TOP_QUPV3_1_GSI_LPASS_INT_SEL_OUT_5_BMSK                              0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_TOP_QUPV3_1_GSI_LPASS_INT_SEL_OUT_5_SHFT                                  0x6
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_TOP_QUPV3_1_SE_LPASS_INT_SEL_OUT_5_BMSK                                  0x3f
#define HWIO_TCSR_TOP_QUPV3_1_LPASS_INT_SEL_OUT_5_TOP_QUPV3_1_SE_LPASS_INT_SEL_OUT_5_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029048)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029048)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_RMSK                                                                  0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_ADDR, HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_IN)
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_TOP_QUPV3_2_GSI_LPASS_INT_SEL_OUT_5_BMSK                              0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_TOP_QUPV3_2_GSI_LPASS_INT_SEL_OUT_5_SHFT                                  0x6
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_TOP_QUPV3_2_SE_LPASS_INT_SEL_OUT_5_BMSK                                  0x3f
#define HWIO_TCSR_TOP_QUPV3_2_LPASS_INT_SEL_OUT_5_TOP_QUPV3_2_SE_LPASS_INT_SEL_OUT_5_SHFT                                   0x0

#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029060)
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029060)
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_RMSK                                                                  0x7ffff
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_ADDR, HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_SSC_QUPV3_0_GSI_LPASS_INT_SEL_OUT_0_BMSK                              0x7ffc0
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_SSC_QUPV3_0_GSI_LPASS_INT_SEL_OUT_0_SHFT                                  0x6
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_SSC_QUPV3_0_SE_LPASS_INT_SEL_OUT_0_BMSK                                  0x3f
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_0_SSC_QUPV3_0_SE_LPASS_INT_SEL_OUT_0_SHFT                                   0x0

#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00029064)
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00029064)
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_RMSK                                                                  0x7ffff
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_ADDR, HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_SSC_QUPV3_0_GSI_LPASS_INT_SEL_OUT_1_BMSK                              0x7ffc0
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_SSC_QUPV3_0_GSI_LPASS_INT_SEL_OUT_1_SHFT                                  0x6
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_SSC_QUPV3_0_SE_LPASS_INT_SEL_OUT_1_BMSK                                  0x3f
#define HWIO_TCSR_SSC_QUPV3_0_LPASS_INT_SEL_OUT_1_SSC_QUPV3_0_SE_LPASS_INT_SEL_OUT_1_SHFT                                   0x0

#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b004)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b004)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_RMSK                                                                0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_ADDR, HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_TOP_QUPV3_0_GSI_TURING_INT_SEL_OUT_0_BMSK                           0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_TOP_QUPV3_0_GSI_TURING_INT_SEL_OUT_0_SHFT                                0x8
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_TOP_QUPV3_0_SE_TURING_INT_SEL_OUT_0_BMSK                                0xff
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_0_TOP_QUPV3_0_SE_TURING_INT_SEL_OUT_0_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b008)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b008)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_RMSK                                                                 0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_ADDR, HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_TOP_QUPV3_1_GSI_TURING_INT_SEL_OUT_0_BMSK                            0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_TOP_QUPV3_1_GSI_TURING_INT_SEL_OUT_0_SHFT                                0x6
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_TOP_QUPV3_1_SE_TURING_INT_SEL_OUT_0_BMSK                                0x3f
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_0_TOP_QUPV3_1_SE_TURING_INT_SEL_OUT_0_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b00c)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b00c)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_RMSK                                                                 0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_ADDR, HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_TOP_QUPV3_2_GSI_TURING_INT_SEL_OUT_0_BMSK                            0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_TOP_QUPV3_2_GSI_TURING_INT_SEL_OUT_0_SHFT                                0x6
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_TOP_QUPV3_2_SE_TURING_INT_SEL_OUT_0_BMSK                                0x3f
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_0_TOP_QUPV3_2_SE_TURING_INT_SEL_OUT_0_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b010)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b010)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_RMSK                                                                0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_ADDR, HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_TOP_QUPV3_0_GSI_TURING_INT_SEL_OUT_1_BMSK                           0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_TOP_QUPV3_0_GSI_TURING_INT_SEL_OUT_1_SHFT                                0x8
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_TOP_QUPV3_0_SE_TURING_INT_SEL_OUT_1_BMSK                                0xff
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_1_TOP_QUPV3_0_SE_TURING_INT_SEL_OUT_1_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b014)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b014)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_RMSK                                                                 0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_ADDR, HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_TOP_QUPV3_1_GSI_TURING_INT_SEL_OUT_1_BMSK                            0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_TOP_QUPV3_1_GSI_TURING_INT_SEL_OUT_1_SHFT                                0x6
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_TOP_QUPV3_1_SE_TURING_INT_SEL_OUT_1_BMSK                                0x3f
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_1_TOP_QUPV3_1_SE_TURING_INT_SEL_OUT_1_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b018)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b018)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_RMSK                                                                 0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_ADDR, HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_TOP_QUPV3_2_GSI_TURING_INT_SEL_OUT_1_BMSK                            0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_TOP_QUPV3_2_GSI_TURING_INT_SEL_OUT_1_SHFT                                0x6
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_TOP_QUPV3_2_SE_TURING_INT_SEL_OUT_1_BMSK                                0x3f
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_1_TOP_QUPV3_2_SE_TURING_INT_SEL_OUT_1_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b01c)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b01c)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_RMSK                                                                0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_ADDR, HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_IN)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_TOP_QUPV3_0_GSI_TURING_INT_SEL_OUT_2_BMSK                           0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_TOP_QUPV3_0_GSI_TURING_INT_SEL_OUT_2_SHFT                                0x8
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_TOP_QUPV3_0_SE_TURING_INT_SEL_OUT_2_BMSK                                0xff
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_2_TOP_QUPV3_0_SE_TURING_INT_SEL_OUT_2_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b020)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b020)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_RMSK                                                                 0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_ADDR, HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_IN)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_TOP_QUPV3_1_GSI_TURING_INT_SEL_OUT_2_BMSK                            0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_TOP_QUPV3_1_GSI_TURING_INT_SEL_OUT_2_SHFT                                0x6
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_TOP_QUPV3_1_SE_TURING_INT_SEL_OUT_2_BMSK                                0x3f
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_2_TOP_QUPV3_1_SE_TURING_INT_SEL_OUT_2_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b024)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b024)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_RMSK                                                                 0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_ADDR, HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_IN)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_TOP_QUPV3_2_GSI_TURING_INT_SEL_OUT_2_BMSK                            0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_TOP_QUPV3_2_GSI_TURING_INT_SEL_OUT_2_SHFT                                0x6
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_TOP_QUPV3_2_SE_TURING_INT_SEL_OUT_2_BMSK                                0x3f
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_2_TOP_QUPV3_2_SE_TURING_INT_SEL_OUT_2_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b028)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b028)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_RMSK                                                                0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_ADDR, HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_IN)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_TOP_QUPV3_0_GSI_TURING_INT_SEL_OUT_3_BMSK                           0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_TOP_QUPV3_0_GSI_TURING_INT_SEL_OUT_3_SHFT                                0x8
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_TOP_QUPV3_0_SE_TURING_INT_SEL_OUT_3_BMSK                                0xff
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_3_TOP_QUPV3_0_SE_TURING_INT_SEL_OUT_3_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b02c)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b02c)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_RMSK                                                                 0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_ADDR, HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_IN)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_TOP_QUPV3_1_GSI_TURING_INT_SEL_OUT_3_BMSK                            0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_TOP_QUPV3_1_GSI_TURING_INT_SEL_OUT_3_SHFT                                0x6
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_TOP_QUPV3_1_SE_TURING_INT_SEL_OUT_3_BMSK                                0x3f
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_3_TOP_QUPV3_1_SE_TURING_INT_SEL_OUT_3_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b030)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b030)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_RMSK                                                                 0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_ADDR, HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_IN)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_TOP_QUPV3_2_GSI_TURING_INT_SEL_OUT_3_BMSK                            0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_TOP_QUPV3_2_GSI_TURING_INT_SEL_OUT_3_SHFT                                0x6
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_TOP_QUPV3_2_SE_TURING_INT_SEL_OUT_3_BMSK                                0x3f
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_3_TOP_QUPV3_2_SE_TURING_INT_SEL_OUT_3_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b034)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b034)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_RMSK                                                                0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_ADDR, HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_IN)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_TOP_QUPV3_0_GSI_TURING_INT_SEL_OUT_4_BMSK                           0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_TOP_QUPV3_0_GSI_TURING_INT_SEL_OUT_4_SHFT                                0x8
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_TOP_QUPV3_0_SE_TURING_INT_SEL_OUT_4_BMSK                                0xff
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_4_TOP_QUPV3_0_SE_TURING_INT_SEL_OUT_4_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b038)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b038)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_RMSK                                                                 0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_ADDR, HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_IN)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_TOP_QUPV3_1_GSI_TURING_INT_SEL_OUT_4_BMSK                            0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_TOP_QUPV3_1_GSI_TURING_INT_SEL_OUT_4_SHFT                                0x6
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_TOP_QUPV3_1_SE_TURING_INT_SEL_OUT_4_BMSK                                0x3f
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_4_TOP_QUPV3_1_SE_TURING_INT_SEL_OUT_4_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b03c)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b03c)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_RMSK                                                                 0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_ADDR, HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_IN)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_TOP_QUPV3_2_GSI_TURING_INT_SEL_OUT_4_BMSK                            0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_TOP_QUPV3_2_GSI_TURING_INT_SEL_OUT_4_SHFT                                0x6
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_TOP_QUPV3_2_SE_TURING_INT_SEL_OUT_4_BMSK                                0x3f
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_4_TOP_QUPV3_2_SE_TURING_INT_SEL_OUT_4_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b040)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b040)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_RMSK                                                                0x1fffff
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_ADDR, HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_RMSK)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_IN)
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_TOP_QUPV3_0_GSI_TURING_INT_SEL_OUT_5_BMSK                           0x1fff00
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_TOP_QUPV3_0_GSI_TURING_INT_SEL_OUT_5_SHFT                                0x8
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_TOP_QUPV3_0_SE_TURING_INT_SEL_OUT_5_BMSK                                0xff
#define HWIO_TCSR_TOP_QUPV3_0_TURING_INT_SEL_OUT_5_TOP_QUPV3_0_SE_TURING_INT_SEL_OUT_5_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b044)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b044)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_RMSK                                                                 0x7ffff
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_ADDR, HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_RMSK)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_IN)
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_TOP_QUPV3_1_GSI_TURING_INT_SEL_OUT_5_BMSK                            0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_TOP_QUPV3_1_GSI_TURING_INT_SEL_OUT_5_SHFT                                0x6
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_TOP_QUPV3_1_SE_TURING_INT_SEL_OUT_5_BMSK                                0x3f
#define HWIO_TCSR_TOP_QUPV3_1_TURING_INT_SEL_OUT_5_TOP_QUPV3_1_SE_TURING_INT_SEL_OUT_5_SHFT                                 0x0

#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b048)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b048)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_RMSK                                                                 0x7ffff
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_IN          \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_ADDR, HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_RMSK)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_INM(m)      \
        in_dword_masked(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_ADDR, m)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_OUT(v)      \
        out_dword(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_ADDR,v)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_ADDR,m,v,HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_IN)
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_TOP_QUPV3_2_GSI_TURING_INT_SEL_OUT_5_BMSK                            0x7ffc0
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_TOP_QUPV3_2_GSI_TURING_INT_SEL_OUT_5_SHFT                                0x6
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_TOP_QUPV3_2_SE_TURING_INT_SEL_OUT_5_BMSK                                0x3f
#define HWIO_TCSR_TOP_QUPV3_2_TURING_INT_SEL_OUT_5_TOP_QUPV3_2_SE_TURING_INT_SEL_OUT_5_SHFT                                 0x0

#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b060)
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b060)
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_RMSK                                                                 0x7ffff
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_IN          \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_ADDR, HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_RMSK)
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_OUT(v)      \
        out_dword(HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_ADDR,v)
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_ADDR,m,v,HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_IN)
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_SSC_QUPV3_0_GSI_TURING_INT_SEL_OUT_0_BMSK                            0x7ffc0
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_SSC_QUPV3_0_GSI_TURING_INT_SEL_OUT_0_SHFT                                0x6
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_SSC_QUPV3_0_SE_TURING_INT_SEL_OUT_0_BMSK                                0x3f
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_0_SSC_QUPV3_0_SE_TURING_INT_SEL_OUT_0_SHFT                                 0x0

#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_ADDR                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0002b064)
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_PHYS                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002b064)
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_RMSK                                                                 0x7ffff
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_IN          \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_ADDR, HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_RMSK)
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_ADDR, m)
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_OUT(v)      \
        out_dword(HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_ADDR,v)
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_ADDR,m,v,HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_IN)
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_SSC_QUPV3_0_GSI_TURING_INT_SEL_OUT_1_BMSK                            0x7ffc0
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_SSC_QUPV3_0_GSI_TURING_INT_SEL_OUT_1_SHFT                                0x6
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_SSC_QUPV3_0_SE_TURING_INT_SEL_OUT_1_BMSK                                0x3f
#define HWIO_TCSR_SSC_QUPV3_0_TURING_INT_SEL_OUT_1_SSC_QUPV3_0_SE_TURING_INT_SEL_OUT_1_SHFT                                 0x0

#define HWIO_TCSR_QPDI_DISABLE_CFG_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00001000)
#define HWIO_TCSR_QPDI_DISABLE_CFG_PHYS                                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00001000)
#define HWIO_TCSR_QPDI_DISABLE_CFG_RMSK                                                                                   0x303
#define HWIO_TCSR_QPDI_DISABLE_CFG_IN          \
        in_dword_masked(HWIO_TCSR_QPDI_DISABLE_CFG_ADDR, HWIO_TCSR_QPDI_DISABLE_CFG_RMSK)
#define HWIO_TCSR_QPDI_DISABLE_CFG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QPDI_DISABLE_CFG_ADDR, m)
#define HWIO_TCSR_QPDI_DISABLE_CFG_OUT(v)      \
        out_dword(HWIO_TCSR_QPDI_DISABLE_CFG_ADDR,v)
#define HWIO_TCSR_QPDI_DISABLE_CFG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QPDI_DISABLE_CFG_ADDR,m,v,HWIO_TCSR_QPDI_DISABLE_CFG_IN)
#define HWIO_TCSR_QPDI_DISABLE_CFG_QPDI_SPMI_DBG_ACK_BMSK                                                                 0x200
#define HWIO_TCSR_QPDI_DISABLE_CFG_QPDI_SPMI_DBG_ACK_SHFT                                                                   0x9
#define HWIO_TCSR_QPDI_DISABLE_CFG_QPDI_SPMI_DBG_REQ_BMSK                                                                 0x100
#define HWIO_TCSR_QPDI_DISABLE_CFG_QPDI_SPMI_DBG_REQ_SHFT                                                                   0x8
#define HWIO_TCSR_QPDI_DISABLE_CFG_SPMI_HANDSHAKE_DISABLE_BMSK                                                              0x2
#define HWIO_TCSR_QPDI_DISABLE_CFG_SPMI_HANDSHAKE_DISABLE_SHFT                                                              0x1
#define HWIO_TCSR_QPDI_DISABLE_CFG_QPDI_DISABLE_CFG_BMSK                                                                    0x1
#define HWIO_TCSR_QPDI_DISABLE_CFG_QPDI_DISABLE_CFG_SHFT                                                                    0x0

#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_ADDR                                                                     (TCSR_TCSR_REGS_REG_BASE      + 0x00016000)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_PHYS                                                                     (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00016000)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_RMSK                                                                            0x3
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_IN          \
        in_dword_masked(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_ADDR, HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_RMSK)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_ADDR, m)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_OUT(v)      \
        out_dword(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_ADDR,v)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_ADDR,m,v,HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_IN)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_TEST_EN_1_BMSK                                                                  0x2
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_TEST_EN_1_SHFT                                                                  0x1
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_TEST_DATA_1_BMSK                                                                0x1
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_1_TEST_DATA_1_SHFT                                                                0x0

#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_ADDR                                                                     (TCSR_TCSR_REGS_REG_BASE      + 0x00016004)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_PHYS                                                                     (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00016004)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_RMSK                                                                            0x3
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_IN          \
        in_dword_masked(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_ADDR, HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_RMSK)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_ADDR, m)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_OUT(v)      \
        out_dword(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_ADDR,v)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_ADDR,m,v,HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_IN)
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_TEST_EN_0_BMSK                                                                  0x2
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_TEST_EN_0_SHFT                                                                  0x1
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_TEST_DATA_0_BMSK                                                                0x1
#define HWIO_TCSR_DIFFERENTIAL_TEST_CLOCK_0_TEST_DATA_0_SHFT                                                                0x0

#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_ADDR                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x00017000)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_PHYS                                                                   (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00017000)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_RMSK                                                                          0x3
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_IN          \
        in_dword_masked(HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_ADDR, HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_RMSK)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_INM(m)      \
        in_dword_masked(HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_ADDR, m)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_OUT(v)      \
        out_dword(HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_ADDR,v)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_ADDR,m,v,HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_IN)
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_QDSS_NS_ENABLE_BACKPRESSURE_BMSK                                              0x2
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_QDSS_NS_ENABLE_BACKPRESSURE_SHFT                                              0x1
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_QDSS_NS_ENABLE_EVENT_IFACE_BMSK                                               0x1
#define HWIO_TCSR_QDSS_NS_STM_ENABLE_SWEVENTS_QDSS_NS_ENABLE_EVENT_IFACE_SHFT                                               0x0

#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00017004)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_PHYS                                                                  (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00017004)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_RMSK                                                                         0x3
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_IN          \
        in_dword_masked(HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_ADDR, HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_RMSK)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_INM(m)      \
        in_dword_masked(HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_ADDR, m)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_OUT(v)      \
        out_dword(HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_ADDR,v)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_ADDR,m,v,HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_IN)
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_QDSS_SEC_ENABLE_BACKPRESSURE_BMSK                                            0x2
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_QDSS_SEC_ENABLE_BACKPRESSURE_SHFT                                            0x1
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_QDSS_SEC_ENABLE_EVENT_IFACE_BMSK                                             0x1
#define HWIO_TCSR_QDSS_SEC_STM_ENABLE_SWEVENTS_QDSS_SEC_ENABLE_EVENT_IFACE_SHFT                                             0x0

#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_ADDR                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x00017008)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_PHYS                                                                      (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00017008)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_RMSK                                                                             0x1
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_IN          \
        in_dword_masked(HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_ADDR, HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_RMSK)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_INM(m)      \
        in_dword_masked(HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_ADDR, m)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_OUT(v)      \
        out_dword(HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_ADDR,v)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_ADDR,m,v,HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_IN)
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_QDSS_NS_ETR_TRACE_BMSK                                                           0x1
#define HWIO_TCSR_QDSS_NS_ETR_ENABLE_TRACE_QDSS_NS_ETR_TRACE_SHFT                                                           0x0

#define HWIO_TCSR_MEM_ARRY_STBY_ADDR                                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x0000c000)
#define HWIO_TCSR_MEM_ARRY_STBY_PHYS                                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000c000)
#define HWIO_TCSR_MEM_ARRY_STBY_RMSK                                                                                        0x1
#define HWIO_TCSR_MEM_ARRY_STBY_IN          \
        in_dword_masked(HWIO_TCSR_MEM_ARRY_STBY_ADDR, HWIO_TCSR_MEM_ARRY_STBY_RMSK)
#define HWIO_TCSR_MEM_ARRY_STBY_INM(m)      \
        in_dword_masked(HWIO_TCSR_MEM_ARRY_STBY_ADDR, m)
#define HWIO_TCSR_MEM_ARRY_STBY_OUT(v)      \
        out_dword(HWIO_TCSR_MEM_ARRY_STBY_ADDR,v)
#define HWIO_TCSR_MEM_ARRY_STBY_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_MEM_ARRY_STBY_ADDR,m,v,HWIO_TCSR_MEM_ARRY_STBY_IN)
#define HWIO_TCSR_MEM_ARRY_STBY_MEM_ARRY_STBY_N_BMSK                                                                        0x1
#define HWIO_TCSR_MEM_ARRY_STBY_MEM_ARRY_STBY_N_SHFT                                                                        0x0

#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_ADDR                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x00011000)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_PHYS                                                             (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00011000)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_RMSK                                                                    0x1
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_IN          \
        in_dword_masked(HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_ADDR, HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_RMSK)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_INM(m)      \
        in_dword_masked(HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_ADDR, m)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_OUT(v)      \
        out_dword(HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_ADDR,v)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_ADDR,m,v,HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_IN)
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_VSENSE_CONTROLLER_ENABLE_REGISTER_BMSK                                  0x1
#define HWIO_TCSR_VSENSE_CONTROLLER_ENABLE_REGISTER_VSENSE_CONTROLLER_ENABLE_REGISTER_SHFT                                  0x0

#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_ADDR                                                                     (TCSR_TCSR_REGS_REG_BASE      + 0x00012000)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_PHYS                                                                     (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00012000)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_RMSK                                                                     0xffffffff
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_IN          \
        in_dword_masked(HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_ADDR, HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_RMSK)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_INM(m)      \
        in_dword_masked(HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_ADDR, m)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_OUT(v)      \
        out_dword(HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_ADDR,v)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_ADDR,m,v,HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_IN)
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_TCSR_RESET_DEBUG_SW_ENTRY_BMSK                                           0xffffffff
#define HWIO_TCSR_TCSR_RESET_DEBUG_SW_ENTRY_TCSR_RESET_DEBUG_SW_ENTRY_SHFT                                                  0x0

#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_ADDR                                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00013000)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_PHYS                                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00013000)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_RMSK                                                                         0xffffffff
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_IN          \
        in_dword_masked(HWIO_TCSR_TCSR_BOOT_MISC_DETECT_ADDR, HWIO_TCSR_TCSR_BOOT_MISC_DETECT_RMSK)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_INM(m)      \
        in_dword_masked(HWIO_TCSR_TCSR_BOOT_MISC_DETECT_ADDR, m)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_OUT(v)      \
        out_dword(HWIO_TCSR_TCSR_BOOT_MISC_DETECT_ADDR,v)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TCSR_BOOT_MISC_DETECT_ADDR,m,v,HWIO_TCSR_TCSR_BOOT_MISC_DETECT_IN)
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_TCSR_BOOT_MISC_DETECT_BMSK                                                   0xffffffff
#define HWIO_TCSR_TCSR_BOOT_MISC_DETECT_TCSR_BOOT_MISC_DETECT_SHFT                                                          0x0

#define HWIO_TCSR_TZ_WONCE_n_ADDR(n)                                                                                 (TCSR_TCSR_REGS_REG_BASE      + 0x00014000 + 0x4 * (n))
#define HWIO_TCSR_TZ_WONCE_n_PHYS(n)                                                                                 (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00014000 + 0x4 * (n))
#define HWIO_TCSR_TZ_WONCE_n_RMSK                                                                                    0xffffffff
#define HWIO_TCSR_TZ_WONCE_n_MAXn                                                                                            15
#define HWIO_TCSR_TZ_WONCE_n_INI(n)        \
        in_dword_masked(HWIO_TCSR_TZ_WONCE_n_ADDR(n), HWIO_TCSR_TZ_WONCE_n_RMSK)
#define HWIO_TCSR_TZ_WONCE_n_INMI(n,mask)    \
        in_dword_masked(HWIO_TCSR_TZ_WONCE_n_ADDR(n), mask)
#define HWIO_TCSR_TZ_WONCE_n_OUTI(n,val)    \
        out_dword(HWIO_TCSR_TZ_WONCE_n_ADDR(n),val)
#define HWIO_TCSR_TZ_WONCE_n_OUTMI(n,mask,val) \
        out_dword_masked_ns(HWIO_TCSR_TZ_WONCE_n_ADDR(n),mask,val,HWIO_TCSR_TZ_WONCE_n_INI(n))
#define HWIO_TCSR_TZ_WONCE_n_TZ_WONCE_ADDRESS_BMSK                                                                   0xffffffff
#define HWIO_TCSR_TZ_WONCE_n_TZ_WONCE_ADDRESS_SHFT                                                                          0x0

#define HWIO_TCSR_QREFS_RPT_CONFIG_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00015000)
#define HWIO_TCSR_QREFS_RPT_CONFIG_PHYS                                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00015000)
#define HWIO_TCSR_QREFS_RPT_CONFIG_RMSK                                                                                  0xffff
#define HWIO_TCSR_QREFS_RPT_CONFIG_IN          \
        in_dword_masked(HWIO_TCSR_QREFS_RPT_CONFIG_ADDR, HWIO_TCSR_QREFS_RPT_CONFIG_RMSK)
#define HWIO_TCSR_QREFS_RPT_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_RPT_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_RPT_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_RPT_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_RPT_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_RPT_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_RPT_CONFIG_IN)
#define HWIO_TCSR_QREFS_RPT_CONFIG_QREFS_RPT_CONFIG_BUS_SELECT_BMSK                                                      0xffff
#define HWIO_TCSR_QREFS_RPT_CONFIG_QREFS_RPT_CONFIG_BUS_SELECT_SHFT                                                         0x0

#define HWIO_TCSR_QREFS_TXVBG_CONFIG_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00015004)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_PHYS                                                                            (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00015004)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_RMSK                                                                                0xffff
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_IN          \
        in_dword_masked(HWIO_TCSR_QREFS_TXVBG_CONFIG_ADDR, HWIO_TCSR_QREFS_TXVBG_CONFIG_RMSK)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_TXVBG_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_TXVBG_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_TXVBG_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_TXVBG_CONFIG_IN)
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_QREFS_TXVBG_CONFIG_BMSK                                                             0xffff
#define HWIO_TCSR_QREFS_TXVBG_CONFIG_QREFS_TXVBG_CONFIG_SHFT                                                                0x0

#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x00015008)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_PHYS                                                                          (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00015008)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_RMSK                                                                                0xff
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_IN          \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RX3_CONFIG_ADDR, HWIO_TCSR_QREFS_CXO_RX3_CONFIG_RMSK)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RX3_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO_RX3_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO_RX3_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO_RX3_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_QREFS_CXO_RX3_CONFIG_BMSK                                                           0xff
#define HWIO_TCSR_QREFS_CXO_RX3_CONFIG_QREFS_CXO_RX3_CONFIG_SHFT                                                            0x0

#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x0001500c)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_PHYS                                                                          (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001500c)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_RMSK                                                                                0xff
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_IN          \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RX2_CONFIG_ADDR, HWIO_TCSR_QREFS_CXO_RX2_CONFIG_RMSK)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RX2_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO_RX2_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO_RX2_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO_RX2_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_QREFS_CXO_RX2_CONFIG_BMSK                                                           0xff
#define HWIO_TCSR_QREFS_CXO_RX2_CONFIG_QREFS_CXO_RX2_CONFIG_SHFT                                                            0x0

#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_ADDR                                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00015010)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_PHYS                                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00015010)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_RMSK                                                                               0xff
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_IN          \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_ADDR, HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_RMSK)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_QREFS_CXO_RPT2_CONFIG_BMSK                                                         0xff
#define HWIO_TCSR_QREFS_CXO_RPT2_CONFIG_QREFS_CXO_RPT2_CONFIG_SHFT                                                          0x0

#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_ADDR                                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x00015018)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_PHYS                                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00015018)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_RMSK                                                                               0xff
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_IN          \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_ADDR, HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_RMSK)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_QREFS_CXO2_RX0_CONFIG_BMSK                                                         0xff
#define HWIO_TCSR_QREFS_CXO2_RX0_CONFIG_QREFS_CXO2_RX0_CONFIG_SHFT                                                          0x0

#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x0001501c)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_PHYS                                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001501c)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_RMSK                                                                              0xff
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_IN          \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_ADDR, HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_RMSK)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_QREFS_CXO2_RPT1_CONFIG_BMSK                                                       0xff
#define HWIO_TCSR_QREFS_CXO2_RPT1_CONFIG_QREFS_CXO2_RPT1_CONFIG_SHFT                                                        0x0

#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00015020)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_PHYS                                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00015020)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_RMSK                                                                              0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_IN          \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_ADDR, HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_RMSK)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_QREFS_CXO2_RPT0_CONFIG_BMSK                                                       0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0_CONFIG_QREFS_CXO2_RPT0_CONFIG_SHFT                                                        0x0

#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_ADDR                                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x00015024)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_PHYS                                                                      (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00015024)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_RMSK                                                                          0xffff
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_IN          \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_ADDR, HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_RMSK)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_QREFS_CXO2_TXVBG0_CONFIG_BMSK                                                 0xffff
#define HWIO_TCSR_QREFS_CXO2_TXVBG0_CONFIG_QREFS_CXO2_TXVBG0_CONFIG_SHFT                                                    0x0

#define HWIO_TCSR_QZIP_CTL_ST_ADDR                                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x00015028)
#define HWIO_TCSR_QZIP_CTL_ST_PHYS                                                                                   (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00015028)
#define HWIO_TCSR_QZIP_CTL_ST_RMSK                                                                                         0xff
#define HWIO_TCSR_QZIP_CTL_ST_IN          \
        in_dword_masked(HWIO_TCSR_QZIP_CTL_ST_ADDR, HWIO_TCSR_QZIP_CTL_ST_RMSK)
#define HWIO_TCSR_QZIP_CTL_ST_INM(m)      \
        in_dword_masked(HWIO_TCSR_QZIP_CTL_ST_ADDR, m)
#define HWIO_TCSR_QZIP_CTL_ST_OUT(v)      \
        out_dword(HWIO_TCSR_QZIP_CTL_ST_ADDR,v)
#define HWIO_TCSR_QZIP_CTL_ST_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QZIP_CTL_ST_ADDR,m,v,HWIO_TCSR_QZIP_CTL_ST_IN)
#define HWIO_TCSR_QZIP_CTL_ST_QZIP_CTL_ST_BMSK                                                                             0xff
#define HWIO_TCSR_QZIP_CTL_ST_QZIP_CTL_ST_SHFT                                                                              0x0

#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_ADDR                                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x0001502c)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_PHYS                                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001502c)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_RMSK                                                                               0xff
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_IN          \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_ADDR, HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_RMSK)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_QREFS_CXO_RPT3_CONFIG_BMSK                                                         0xff
#define HWIO_TCSR_QREFS_CXO_RPT3_CONFIG_QREFS_CXO_RPT3_CONFIG_SHFT                                                          0x0

#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_ADDR                                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x00015030)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_PHYS                                                                       (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00015030)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_RMSK                                                                             0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_IN          \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_ADDR, HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_RMSK)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_QREFS_CXO2_RPT0A_CONFIG_BMSK                                                     0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0A_CONFIG_QREFS_CXO2_RPT0A_CONFIG_SHFT                                                      0x0

#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_ADDR                                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x00015034)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_PHYS                                                                       (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00015034)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_RMSK                                                                             0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_IN          \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_ADDR, HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_RMSK)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_QREFS_CXO2_RPT0B_CONFIG_BMSK                                                     0xff
#define HWIO_TCSR_QREFS_CXO2_RPT0B_CONFIG_QREFS_CXO2_RPT0B_CONFIG_SHFT                                                      0x0

#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_ADDR                                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x00015038)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_PHYS                                                                          (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00015038)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_RMSK                                                                                0xff
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_IN          \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RX1_CONFIG_ADDR, HWIO_TCSR_QREFS_CXO_RX1_CONFIG_RMSK)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_INM(m)      \
        in_dword_masked(HWIO_TCSR_QREFS_CXO_RX1_CONFIG_ADDR, m)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_OUT(v)      \
        out_dword(HWIO_TCSR_QREFS_CXO_RX1_CONFIG_ADDR,v)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_QREFS_CXO_RX1_CONFIG_ADDR,m,v,HWIO_TCSR_QREFS_CXO_RX1_CONFIG_IN)
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_QREFS_CXO_RX1_CONFIG_BMSK                                                           0xff
#define HWIO_TCSR_QREFS_CXO_RX1_CONFIG_QREFS_CXO_RX1_CONFIG_SHFT                                                            0x0

#define HWIO_TCSR_TIC_CNOC_NS_ADDR                                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0000c004)
#define HWIO_TCSR_TIC_CNOC_NS_PHYS                                                                                   (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000c004)
#define HWIO_TCSR_TIC_CNOC_NS_RMSK                                                                                          0x1
#define HWIO_TCSR_TIC_CNOC_NS_IN          \
        in_dword_masked(HWIO_TCSR_TIC_CNOC_NS_ADDR, HWIO_TCSR_TIC_CNOC_NS_RMSK)
#define HWIO_TCSR_TIC_CNOC_NS_INM(m)      \
        in_dword_masked(HWIO_TCSR_TIC_CNOC_NS_ADDR, m)
#define HWIO_TCSR_TIC_CNOC_NS_OUT(v)      \
        out_dword(HWIO_TCSR_TIC_CNOC_NS_ADDR,v)
#define HWIO_TCSR_TIC_CNOC_NS_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_TIC_CNOC_NS_ADDR,m,v,HWIO_TCSR_TIC_CNOC_NS_IN)
#define HWIO_TCSR_TIC_CNOC_NS_TIC_CNOC_NS_BMSK                                                                              0x1
#define HWIO_TCSR_TIC_CNOC_NS_TIC_CNOC_NS_SHFT                                                                              0x0

#define HWIO_TCSR_CONN_BOX_SPARE_0_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000e000)
#define HWIO_TCSR_CONN_BOX_SPARE_0_PHYS                                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000e000)
#define HWIO_TCSR_CONN_BOX_SPARE_0_RMSK                                                                              0xffffffff
#define HWIO_TCSR_CONN_BOX_SPARE_0_IN          \
        in_dword_masked(HWIO_TCSR_CONN_BOX_SPARE_0_ADDR, HWIO_TCSR_CONN_BOX_SPARE_0_RMSK)
#define HWIO_TCSR_CONN_BOX_SPARE_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_CONN_BOX_SPARE_0_ADDR, m)
#define HWIO_TCSR_CONN_BOX_SPARE_0_OUT(v)      \
        out_dword(HWIO_TCSR_CONN_BOX_SPARE_0_ADDR,v)
#define HWIO_TCSR_CONN_BOX_SPARE_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_CONN_BOX_SPARE_0_ADDR,m,v,HWIO_TCSR_CONN_BOX_SPARE_0_IN)
#define HWIO_TCSR_CONN_BOX_SPARE_0_CONN_BOX_SPARE_0_BMSK                                                             0xffffffff
#define HWIO_TCSR_CONN_BOX_SPARE_0_CONN_BOX_SPARE_0_SHFT                                                                    0x0

#define HWIO_TCSR_CONN_BOX_SPARE_1_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x0000f000)
#define HWIO_TCSR_CONN_BOX_SPARE_1_PHYS                                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000f000)
#define HWIO_TCSR_CONN_BOX_SPARE_1_RMSK                                                                              0xffffffff
#define HWIO_TCSR_CONN_BOX_SPARE_1_IN          \
        in_dword_masked(HWIO_TCSR_CONN_BOX_SPARE_1_ADDR, HWIO_TCSR_CONN_BOX_SPARE_1_RMSK)
#define HWIO_TCSR_CONN_BOX_SPARE_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_CONN_BOX_SPARE_1_ADDR, m)
#define HWIO_TCSR_CONN_BOX_SPARE_1_OUT(v)      \
        out_dword(HWIO_TCSR_CONN_BOX_SPARE_1_ADDR,v)
#define HWIO_TCSR_CONN_BOX_SPARE_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_CONN_BOX_SPARE_1_ADDR,m,v,HWIO_TCSR_CONN_BOX_SPARE_1_IN)
#define HWIO_TCSR_CONN_BOX_SPARE_1_CONN_BOX_SPARE_1_BMSK                                                             0xffffffff
#define HWIO_TCSR_CONN_BOX_SPARE_1_CONN_BOX_SPARE_1_SHFT                                                                    0x0

#define HWIO_TCSR_CONN_BOX_SPARE_2_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00010000)
#define HWIO_TCSR_CONN_BOX_SPARE_2_PHYS                                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00010000)
#define HWIO_TCSR_CONN_BOX_SPARE_2_RMSK                                                                              0xffffffff
#define HWIO_TCSR_CONN_BOX_SPARE_2_IN          \
        in_dword_masked(HWIO_TCSR_CONN_BOX_SPARE_2_ADDR, HWIO_TCSR_CONN_BOX_SPARE_2_RMSK)
#define HWIO_TCSR_CONN_BOX_SPARE_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_CONN_BOX_SPARE_2_ADDR, m)
#define HWIO_TCSR_CONN_BOX_SPARE_2_OUT(v)      \
        out_dword(HWIO_TCSR_CONN_BOX_SPARE_2_ADDR,v)
#define HWIO_TCSR_CONN_BOX_SPARE_2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_CONN_BOX_SPARE_2_ADDR,m,v,HWIO_TCSR_CONN_BOX_SPARE_2_IN)
#define HWIO_TCSR_CONN_BOX_SPARE_2_CONN_BOX_SPARE_2_BMSK                                                             0xffffffff
#define HWIO_TCSR_CONN_BOX_SPARE_2_CONN_BOX_SPARE_2_SHFT                                                                    0x0

#define HWIO_TCSR_Q6SS_COREPWR_ON_ADDR                                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0000c008)
#define HWIO_TCSR_Q6SS_COREPWR_ON_PHYS                                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0000c008)
#define HWIO_TCSR_Q6SS_COREPWR_ON_RMSK                                                                                      0x1
#define HWIO_TCSR_Q6SS_COREPWR_ON_IN          \
        in_dword_masked(HWIO_TCSR_Q6SS_COREPWR_ON_ADDR, HWIO_TCSR_Q6SS_COREPWR_ON_RMSK)
#define HWIO_TCSR_Q6SS_COREPWR_ON_INM(m)      \
        in_dword_masked(HWIO_TCSR_Q6SS_COREPWR_ON_ADDR, m)
#define HWIO_TCSR_Q6SS_COREPWR_ON_MSS_Q6_PWR_ON_BMSK                                                                        0x1
#define HWIO_TCSR_Q6SS_COREPWR_ON_MSS_Q6_PWR_ON_SHFT                                                                        0x0

#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_ADDR                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00018000)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_PHYS                                                                  (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00018000)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_RMSK                                                                  0xffffffff
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_IN          \
        in_dword_masked(HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_ADDR, HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_RMSK)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_INM(m)      \
        in_dword_masked(HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_ADDR, m)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_OUT(v)      \
        out_dword(HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_ADDR,v)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_ADDR,m,v,HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_IN)
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_CFG_BITS_SHFT_BMSK                                                    0xffffffff
#define HWIO_TCSR_MASTER_CFG_COMPUTE_SIGNALING_CFG_BITS_SHFT_SHFT                                                           0x0

#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00019000)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00019000)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_RMSK                                                               0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_IN          \
        in_dword_masked(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_ADDR, HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_RMSK)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_ADDR, m)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_OUT(v)      \
        out_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_ADDR,v)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_ADDR,m,v,HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_IN)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_USER_COMPUTE_SIGNALING_WRITE_STATUS_BMSK                           0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_0_USER_COMPUTE_SIGNALING_WRITE_STATUS_SHFT                                  0x0

#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_ADDR                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00019004)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_PHYS                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00019004)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_RMSK                                                               0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_IN          \
        in_dword_masked(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_ADDR, HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_RMSK)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_ADDR, m)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_OUT(v)      \
        out_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_ADDR,v)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_ADDR,m,v,HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_IN)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_USER_COMPUTE_SIGNALING_WRITE_STATUS_BMSK                           0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_USER_1_USER_COMPUTE_SIGNALING_WRITE_STATUS_SHFT                                  0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x0001a000)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001a000)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_RMSK                                                        0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_IN          \
        in_dword_masked(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_ADDR, HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_RMSK)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_0_STATUS_USER_BMSK                                0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_0_STATUS_USER_SHFT                                       0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x0001a400)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_PHYS                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001a400)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_RMSK                                                         0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_0_CLEAR_USER_BMSK                                  0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_0_CLEAR_USER_SHFT                                         0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_ADDR                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x0001a800)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_PHYS                                                          (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001a800)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_RMSK                                                          0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_IN          \
        in_dword_masked(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_ADDR, HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_RMSK)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_ADDR,m,v,HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_IN)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_0_MASK_USER_BMSK                                    0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_0_MASK_USER_SHFT                                           0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x0001b000)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001b000)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_RMSK                                                        0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_IN          \
        in_dword_masked(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_ADDR, HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_RMSK)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_1_STATUS_USER_BMSK                                0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_1_STATUS_USER_SHFT                                       0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x0001b400)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_PHYS                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001b400)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_RMSK                                                         0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_1_CLEAR_USER_BMSK                                  0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_1_CLEAR_USER_SHFT                                         0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_ADDR                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x0001b800)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_PHYS                                                          (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001b800)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_RMSK                                                          0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_IN          \
        in_dword_masked(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_ADDR, HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_RMSK)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_ADDR,m,v,HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_IN)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_1_MASK_USER_BMSK                                    0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_1_MASK_USER_SHFT                                           0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x0001c000)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001c000)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_RMSK                                                        0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_IN          \
        in_dword_masked(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_ADDR, HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_RMSK)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_2_STATUS_USER_BMSK                                0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_USER_PROCESSOR_2_STATUS_USER_SHFT                                       0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_ADDR                                                         (TCSR_TCSR_REGS_REG_BASE      + 0x0001c400)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_PHYS                                                         (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001c400)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_RMSK                                                         0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_2_CLEAR_USER_BMSK                                  0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_USER_PROCESSOR_2_CLEAR_USER_SHFT                                         0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_ADDR                                                          (TCSR_TCSR_REGS_REG_BASE      + 0x0001c800)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_PHYS                                                          (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001c800)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_RMSK                                                          0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_IN          \
        in_dword_masked(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_ADDR, HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_RMSK)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_ADDR, m)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_ADDR,v)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_ADDR,m,v,HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_IN)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_2_MASK_USER_BMSK                                    0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_USER_PROCESSOR_2_MASK_USER_SHFT                                           0x0

#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_ADDR                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x0001d000)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_PHYS                                                             (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001d000)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_RMSK                                                             0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_IN          \
        in_dword_masked(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_ADDR, HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_RMSK)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_ADDR, m)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_OUT(v)      \
        out_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_ADDR,v)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_ADDR,m,v,HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_IN)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_KERNEL_COMPUTE_SIGNALING_WRITE_STATUS_BMSK                       0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_0_KERNEL_COMPUTE_SIGNALING_WRITE_STATUS_SHFT                              0x0

#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_ADDR                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x0001d004)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_PHYS                                                             (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001d004)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_RMSK                                                             0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_IN          \
        in_dword_masked(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_ADDR, HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_RMSK)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_ADDR, m)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_OUT(v)      \
        out_dword(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_ADDR,v)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_ADDR,m,v,HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_IN)
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_KERNEL_COMPUTE_SIGNALING_WRITE_STATUS_BMSK                       0xffffffff
#define HWIO_TCSR_MASTER_COMPUTE_SIGNALING_KERNEL_1_KERNEL_COMPUTE_SIGNALING_WRITE_STATUS_SHFT                              0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0001e000)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_PHYS                                                      (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001e000)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_RMSK                                                      0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_IN          \
        in_dword_masked(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR, HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_RMSK)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_0_STATUS_KERNEL_BMSK                            0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_0_STATUS_KERNEL_SHFT                                   0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x0001e400)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_PHYS                                                       (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001e400)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_RMSK                                                       0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_0_CLEAR_KERNEL_BMSK                              0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_0_CLEAR_KERNEL_SHFT                                     0x0

#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x0001e800)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001e800)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_RMSK                                                        0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_IN          \
        in_dword_masked(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_ADDR, HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_RMSK)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,m,v,HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_IN)
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_0_MASK_KERNEL_BMSK                                0xffffffff
#define HWIO_TCSR_PROCESSOR_0_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_0_MASK_KERNEL_SHFT                                       0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x0001f000)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_PHYS                                                      (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001f000)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_RMSK                                                      0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_IN          \
        in_dword_masked(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR, HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_RMSK)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_1_STATUS_KERNEL_BMSK                            0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_1_STATUS_KERNEL_SHFT                                   0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x0001f400)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_PHYS                                                       (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001f400)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_RMSK                                                       0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_1_CLEAR_KERNEL_BMSK                              0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_1_CLEAR_KERNEL_SHFT                                     0x0

#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x0001f800)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0001f800)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_RMSK                                                        0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_IN          \
        in_dword_masked(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_ADDR, HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_RMSK)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,m,v,HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_IN)
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_1_MASK_KERNEL_BMSK                                0xffffffff
#define HWIO_TCSR_PROCESSOR_1_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_1_MASK_KERNEL_SHFT                                       0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR                                                      (TCSR_TCSR_REGS_REG_BASE      + 0x00020000)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_PHYS                                                      (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00020000)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_RMSK                                                      0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_IN          \
        in_dword_masked(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR, HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_RMSK)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_2_STATUS_KERNEL_BMSK                            0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_STATUS_KERNEL_PROCESSOR_2_STATUS_KERNEL_SHFT                                   0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x00020400)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_PHYS                                                       (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00020400)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_RMSK                                                       0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_2_CLEAR_KERNEL_BMSK                              0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_CLEAR_KERNEL_PROCESSOR_2_CLEAR_KERNEL_SHFT                                     0x0

#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_ADDR                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00020800)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_PHYS                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00020800)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_RMSK                                                        0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_IN          \
        in_dword_masked(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_ADDR, HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_RMSK)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_ADDR, m)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_OUT(v)      \
        out_dword(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,v)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_ADDR,m,v,HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_IN)
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_2_MASK_KERNEL_BMSK                                0xffffffff
#define HWIO_TCSR_PROCESSOR_2_COMPUTE_SIGNAL_MASK_KERNEL_PROCESSOR_2_MASK_KERNEL_SHFT                                       0x0

#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00023000)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_PHYS                                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00023000)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_RMSK                                                                               0x3
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_IN          \
        in_dword_masked(HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_ADDR, HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_RMSK)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_INM(m)      \
        in_dword_masked(HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_ADDR, m)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_OUT(v)      \
        out_dword(HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_ADDR,v)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_ADDR,m,v,HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_IN)
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_A1NOC_SP_BYPASS_CHECK_TYPE_BMSK                                                    0x2
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_A1NOC_SP_BYPASS_CHECK_TYPE_SHFT                                                    0x1
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_A1NOC_MSA_BYPASS_CHECK_TYPE_BMSK                                                   0x1
#define HWIO_TCSR_A1NOC_BYPASS_CHECKTYPE_A1NOC_MSA_BYPASS_CHECK_TYPE_SHFT                                                   0x0

#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_ADDR                                                                        (TCSR_TCSR_REGS_REG_BASE      + 0x00023004)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_PHYS                                                                        (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00023004)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_RMSK                                                                               0x3
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_IN          \
        in_dword_masked(HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_ADDR, HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_RMSK)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_INM(m)      \
        in_dword_masked(HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_ADDR, m)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_OUT(v)      \
        out_dword(HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_ADDR,v)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_ADDR,m,v,HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_IN)
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_A2NOC_SP_BYPASS_CHECK_TYPE_BMSK                                                    0x2
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_A2NOC_SP_BYPASS_CHECK_TYPE_SHFT                                                    0x1
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_A2NOC_MSA_BYPASS_CHECK_TYPE_BMSK                                                   0x1
#define HWIO_TCSR_A2NOC_BYPASS_CHECKTYPE_A2NOC_MSA_BYPASS_CHECK_TYPE_SHFT                                                   0x0

#define HWIO_TCSR_WCSS_TESTBUS_SEL_ADDR                                                                              (TCSR_TCSR_REGS_REG_BASE      + 0x00024000)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_PHYS                                                                              (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00024000)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_RMSK                                                                                    0xff
#define HWIO_TCSR_WCSS_TESTBUS_SEL_IN          \
        in_dword_masked(HWIO_TCSR_WCSS_TESTBUS_SEL_ADDR, HWIO_TCSR_WCSS_TESTBUS_SEL_RMSK)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_WCSS_TESTBUS_SEL_ADDR, m)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_OUT(v)      \
        out_dword(HWIO_TCSR_WCSS_TESTBUS_SEL_ADDR,v)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_WCSS_TESTBUS_SEL_ADDR,m,v,HWIO_TCSR_WCSS_TESTBUS_SEL_IN)
#define HWIO_TCSR_WCSS_TESTBUS_SEL_WCSS_TESTBUS_SEL_BMSK                                                                   0xff
#define HWIO_TCSR_WCSS_TESTBUS_SEL_WCSS_TESTBUS_SEL_SHFT                                                                    0x0

#define HWIO_TCSR_WCSS_AHBBM_CTRL_ADDR                                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00024004)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_PHYS                                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00024004)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_RMSK                                                                                      0x7
#define HWIO_TCSR_WCSS_AHBBM_CTRL_IN          \
        in_dword_masked(HWIO_TCSR_WCSS_AHBBM_CTRL_ADDR, HWIO_TCSR_WCSS_AHBBM_CTRL_RMSK)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_INM(m)      \
        in_dword_masked(HWIO_TCSR_WCSS_AHBBM_CTRL_ADDR, m)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_OUT(v)      \
        out_dword(HWIO_TCSR_WCSS_AHBBM_CTRL_ADDR,v)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_WCSS_AHBBM_CTRL_ADDR,m,v,HWIO_TCSR_WCSS_AHBBM_CTRL_IN)
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_SOFT_RESET_BMSK                                                                     0x4
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_SOFT_RESET_SHFT                                                                     0x2
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_CLKGATE_DISABLE_BMSK                                                                0x2
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_CLKGATE_DISABLE_SHFT                                                                0x1
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_ROOT_CLK_ENABLE_BMSK                                                                0x1
#define HWIO_TCSR_WCSS_AHBBM_CTRL_AHBBM_ROOT_CLK_ENABLE_SHFT                                                                0x0

#define HWIO_TCSR_KRYO_MUX_SEL_ADDR                                                                                  (TCSR_TCSR_REGS_REG_BASE      + 0x00025008)
#define HWIO_TCSR_KRYO_MUX_SEL_PHYS                                                                                  (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00025008)
#define HWIO_TCSR_KRYO_MUX_SEL_RMSK                                                                                         0x3
#define HWIO_TCSR_KRYO_MUX_SEL_IN          \
        in_dword_masked(HWIO_TCSR_KRYO_MUX_SEL_ADDR, HWIO_TCSR_KRYO_MUX_SEL_RMSK)
#define HWIO_TCSR_KRYO_MUX_SEL_INM(m)      \
        in_dword_masked(HWIO_TCSR_KRYO_MUX_SEL_ADDR, m)
#define HWIO_TCSR_KRYO_MUX_SEL_OUT(v)      \
        out_dword(HWIO_TCSR_KRYO_MUX_SEL_ADDR,v)
#define HWIO_TCSR_KRYO_MUX_SEL_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_KRYO_MUX_SEL_ADDR,m,v,HWIO_TCSR_KRYO_MUX_SEL_IN)
#define HWIO_TCSR_KRYO_MUX_SEL_KRYO_MUX_SEL_BMSK                                                                            0x3
#define HWIO_TCSR_KRYO_MUX_SEL_KRYO_MUX_SEL_SHFT                                                                            0x0

#define HWIO_TCSR_APSS_BHS_EN_ADDR                                                                                   (TCSR_TCSR_REGS_REG_BASE      + 0x0002500c)
#define HWIO_TCSR_APSS_BHS_EN_PHYS                                                                                   (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002500c)
#define HWIO_TCSR_APSS_BHS_EN_RMSK                                                                                         0xff
#define HWIO_TCSR_APSS_BHS_EN_IN          \
        in_dword_masked(HWIO_TCSR_APSS_BHS_EN_ADDR, HWIO_TCSR_APSS_BHS_EN_RMSK)
#define HWIO_TCSR_APSS_BHS_EN_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_BHS_EN_ADDR, m)
#define HWIO_TCSR_APSS_BHS_EN_OUT(v)      \
        out_dword(HWIO_TCSR_APSS_BHS_EN_ADDR,v)
#define HWIO_TCSR_APSS_BHS_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_APSS_BHS_EN_ADDR,m,v,HWIO_TCSR_APSS_BHS_EN_IN)
#define HWIO_TCSR_APSS_BHS_EN_APSS_BHS_EN_BMSK                                                                             0xff
#define HWIO_TCSR_APSS_BHS_EN_APSS_BHS_EN_SHFT                                                                              0x0

#define HWIO_TCSR_APSS_BHS_EN_STATUS_ADDR                                                                            (TCSR_TCSR_REGS_REG_BASE      + 0x00025010)
#define HWIO_TCSR_APSS_BHS_EN_STATUS_PHYS                                                                            (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00025010)
#define HWIO_TCSR_APSS_BHS_EN_STATUS_RMSK                                                                                  0xff
#define HWIO_TCSR_APSS_BHS_EN_STATUS_IN          \
        in_dword_masked(HWIO_TCSR_APSS_BHS_EN_STATUS_ADDR, HWIO_TCSR_APSS_BHS_EN_STATUS_RMSK)
#define HWIO_TCSR_APSS_BHS_EN_STATUS_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_BHS_EN_STATUS_ADDR, m)
#define HWIO_TCSR_APSS_BHS_EN_STATUS_APSS_BHS_EN_STATUS_BMSK                                                               0xff
#define HWIO_TCSR_APSS_BHS_EN_STATUS_APSS_BHS_EN_STATUS_SHFT                                                                0x0

#define HWIO_TCSR_APSS_SPARE_REG0_ADDR                                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00025014)
#define HWIO_TCSR_APSS_SPARE_REG0_PHYS                                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00025014)
#define HWIO_TCSR_APSS_SPARE_REG0_RMSK                                                                               0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG0_IN          \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG0_ADDR, HWIO_TCSR_APSS_SPARE_REG0_RMSK)
#define HWIO_TCSR_APSS_SPARE_REG0_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG0_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG0_OUT(v)      \
        out_dword(HWIO_TCSR_APSS_SPARE_REG0_ADDR,v)
#define HWIO_TCSR_APSS_SPARE_REG0_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_APSS_SPARE_REG0_ADDR,m,v,HWIO_TCSR_APSS_SPARE_REG0_IN)
#define HWIO_TCSR_APSS_SPARE_REG0_SPARE_REG0_BMSK                                                                    0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG0_SPARE_REG0_SHFT                                                                           0x0

#define HWIO_TCSR_APSS_SPARE_REG1_ADDR                                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00025018)
#define HWIO_TCSR_APSS_SPARE_REG1_PHYS                                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00025018)
#define HWIO_TCSR_APSS_SPARE_REG1_RMSK                                                                               0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG1_IN          \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG1_ADDR, HWIO_TCSR_APSS_SPARE_REG1_RMSK)
#define HWIO_TCSR_APSS_SPARE_REG1_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG1_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG1_OUT(v)      \
        out_dword(HWIO_TCSR_APSS_SPARE_REG1_ADDR,v)
#define HWIO_TCSR_APSS_SPARE_REG1_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_APSS_SPARE_REG1_ADDR,m,v,HWIO_TCSR_APSS_SPARE_REG1_IN)
#define HWIO_TCSR_APSS_SPARE_REG1_SPARE_REG1_BMSK                                                                    0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG1_SPARE_REG1_SHFT                                                                           0x0

#define HWIO_TCSR_APSS_SPARE_REG2_ADDR                                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x0002501c)
#define HWIO_TCSR_APSS_SPARE_REG2_PHYS                                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002501c)
#define HWIO_TCSR_APSS_SPARE_REG2_RMSK                                                                               0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG2_IN          \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG2_ADDR, HWIO_TCSR_APSS_SPARE_REG2_RMSK)
#define HWIO_TCSR_APSS_SPARE_REG2_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG2_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG2_OUT(v)      \
        out_dword(HWIO_TCSR_APSS_SPARE_REG2_ADDR,v)
#define HWIO_TCSR_APSS_SPARE_REG2_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_APSS_SPARE_REG2_ADDR,m,v,HWIO_TCSR_APSS_SPARE_REG2_IN)
#define HWIO_TCSR_APSS_SPARE_REG2_SPARE_REG2_BMSK                                                                    0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG2_SPARE_REG2_SHFT                                                                           0x0

#define HWIO_TCSR_APSS_SPARE_REG3_ADDR                                                                               (TCSR_TCSR_REGS_REG_BASE      + 0x00025020)
#define HWIO_TCSR_APSS_SPARE_REG3_PHYS                                                                               (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00025020)
#define HWIO_TCSR_APSS_SPARE_REG3_RMSK                                                                               0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG3_IN          \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG3_ADDR, HWIO_TCSR_APSS_SPARE_REG3_RMSK)
#define HWIO_TCSR_APSS_SPARE_REG3_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG3_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG3_OUT(v)      \
        out_dword(HWIO_TCSR_APSS_SPARE_REG3_ADDR,v)
#define HWIO_TCSR_APSS_SPARE_REG3_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_APSS_SPARE_REG3_ADDR,m,v,HWIO_TCSR_APSS_SPARE_REG3_IN)
#define HWIO_TCSR_APSS_SPARE_REG3_SPARE_REG3_BMSK                                                                    0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG3_SPARE_REG3_SHFT                                                                           0x0

#define HWIO_TCSR_APSS_SPARE_REG_RD_0_ADDR                                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00025024)
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_PHYS                                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00025024)
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_RMSK                                                                           0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_IN          \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG_RD_0_ADDR, HWIO_TCSR_APSS_SPARE_REG_RD_0_RMSK)
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG_RD_0_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_SPARE_REG_RD_0_BMSK                                                            0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_0_SPARE_REG_RD_0_SHFT                                                                   0x0

#define HWIO_TCSR_APSS_SPARE_REG_RD_1_ADDR                                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00025028)
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_PHYS                                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00025028)
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_RMSK                                                                           0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_IN          \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG_RD_1_ADDR, HWIO_TCSR_APSS_SPARE_REG_RD_1_RMSK)
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG_RD_1_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_SPARE_REG_RD_1_BMSK                                                            0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_1_SPARE_REG_RD_1_SHFT                                                                   0x0

#define HWIO_TCSR_APSS_SPARE_REG_RD_2_ADDR                                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0002502c)
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_PHYS                                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002502c)
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_RMSK                                                                           0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_IN          \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG_RD_2_ADDR, HWIO_TCSR_APSS_SPARE_REG_RD_2_RMSK)
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG_RD_2_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_SPARE_REG_RD_2_BMSK                                                            0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_2_SPARE_REG_RD_2_SHFT                                                                   0x0

#define HWIO_TCSR_APSS_SPARE_REG_RD_3_ADDR                                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x00025030)
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_PHYS                                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00025030)
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_RMSK                                                                           0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_IN          \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG_RD_3_ADDR, HWIO_TCSR_APSS_SPARE_REG_RD_3_RMSK)
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_INM(m)      \
        in_dword_masked(HWIO_TCSR_APSS_SPARE_REG_RD_3_ADDR, m)
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_SPARE_REG_RD_3_BMSK                                                            0xffffffff
#define HWIO_TCSR_APSS_SPARE_REG_RD_3_SPARE_REG_RD_3_SHFT                                                                   0x0

#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_ADDR                                                                       (TCSR_TCSR_REGS_REG_BASE      + 0x00013100)
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_PHYS                                                                       (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00013100)
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_RMSK                                                                       0xffffffff
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_IN          \
        in_dword_masked(HWIO_TCSR_BOOT_IMEM_START_ADDRESS_ADDR, HWIO_TCSR_BOOT_IMEM_START_ADDRESS_RMSK)
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_INM(m)      \
        in_dword_masked(HWIO_TCSR_BOOT_IMEM_START_ADDRESS_ADDR, m)
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_BOOT_IMEM_START_ADDRESS_BMSK                                               0xffffffff
#define HWIO_TCSR_BOOT_IMEM_START_ADDRESS_BOOT_IMEM_START_ADDRESS_SHFT                                                      0x0

#define HWIO_TCSR_BOOT_IMEM_SIZE_ADDR                                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x00013200)
#define HWIO_TCSR_BOOT_IMEM_SIZE_PHYS                                                                                (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00013200)
#define HWIO_TCSR_BOOT_IMEM_SIZE_RMSK                                                                                0xffffffff
#define HWIO_TCSR_BOOT_IMEM_SIZE_IN          \
        in_dword_masked(HWIO_TCSR_BOOT_IMEM_SIZE_ADDR, HWIO_TCSR_BOOT_IMEM_SIZE_RMSK)
#define HWIO_TCSR_BOOT_IMEM_SIZE_INM(m)      \
        in_dword_masked(HWIO_TCSR_BOOT_IMEM_SIZE_ADDR, m)
#define HWIO_TCSR_BOOT_IMEM_SIZE_BOOT_IMEM_SIZE_BMSK                                                                 0xffffffff
#define HWIO_TCSR_BOOT_IMEM_SIZE_BOOT_IMEM_SIZE_SHFT                                                                        0x0

#define HWIO_TCSR_BOOT_IMEM_DISABLE_ADDR                                                                             (TCSR_TCSR_REGS_REG_BASE      + 0x00013300)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_PHYS                                                                             (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00013300)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_RMSK                                                                                    0x1
#define HWIO_TCSR_BOOT_IMEM_DISABLE_IN          \
        in_dword_masked(HWIO_TCSR_BOOT_IMEM_DISABLE_ADDR, HWIO_TCSR_BOOT_IMEM_DISABLE_RMSK)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_BOOT_IMEM_DISABLE_ADDR, m)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_OUT(v)      \
        out_dword(HWIO_TCSR_BOOT_IMEM_DISABLE_ADDR,v)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_BOOT_IMEM_DISABLE_ADDR,m,v,HWIO_TCSR_BOOT_IMEM_DISABLE_IN)
#define HWIO_TCSR_BOOT_IMEM_DISABLE_BOOT_IMEM_DISABLE_BMSK                                                                  0x1
#define HWIO_TCSR_BOOT_IMEM_DISABLE_BOOT_IMEM_DISABLE_SHFT                                                                  0x0

#define HWIO_TCSR_BIAS_REF_LS_EN_ADDR                                                                                (TCSR_TCSR_REGS_REG_BASE      + 0x00026000)
#define HWIO_TCSR_BIAS_REF_LS_EN_PHYS                                                                                (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x00026000)
#define HWIO_TCSR_BIAS_REF_LS_EN_RMSK                                                                                      0x3f
#define HWIO_TCSR_BIAS_REF_LS_EN_IN          \
        in_dword_masked(HWIO_TCSR_BIAS_REF_LS_EN_ADDR, HWIO_TCSR_BIAS_REF_LS_EN_RMSK)
#define HWIO_TCSR_BIAS_REF_LS_EN_INM(m)      \
        in_dword_masked(HWIO_TCSR_BIAS_REF_LS_EN_ADDR, m)
#define HWIO_TCSR_BIAS_REF_LS_EN_OUT(v)      \
        out_dword(HWIO_TCSR_BIAS_REF_LS_EN_ADDR,v)
#define HWIO_TCSR_BIAS_REF_LS_EN_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_BIAS_REF_LS_EN_ADDR,m,v,HWIO_TCSR_BIAS_REF_LS_EN_IN)
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_3_AUXBUF_EN_BMSK                                                              0x20
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_3_AUXBUF_EN_SHFT                                                               0x5
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_3_ATEST_EN_BMSK                                                               0x10
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_3_ATEST_EN_SHFT                                                                0x4
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_2_AUXBUF_EN_BMSK                                                               0x8
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_2_AUXBUF_EN_SHFT                                                               0x3
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_2_ATEST_EN_BMSK                                                                0x4
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_2_ATEST_EN_SHFT                                                                0x2
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_1_AUXBUF_EN_BMSK                                                               0x2
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_1_AUXBUF_EN_SHFT                                                               0x1
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_1_ATEST_EN_BMSK                                                                0x1
#define HWIO_TCSR_BIAS_REF_LS_EN_BIAS_REF_LS_1_ATEST_EN_SHFT                                                                0x0

#define HWIO_TCSR_REFGEN_QLINK_ENABLE_ADDR                                                                           (TCSR_TCSR_REGS_REG_BASE      + 0x0002c000)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_PHYS                                                                           (TCSR_TCSR_REGS_REG_BASE_PHYS + 0x0002c000)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_RMSK                                                                                  0x1
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_IN          \
        in_dword_masked(HWIO_TCSR_REFGEN_QLINK_ENABLE_ADDR, HWIO_TCSR_REFGEN_QLINK_ENABLE_RMSK)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_INM(m)      \
        in_dword_masked(HWIO_TCSR_REFGEN_QLINK_ENABLE_ADDR, m)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_OUT(v)      \
        out_dword(HWIO_TCSR_REFGEN_QLINK_ENABLE_ADDR,v)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_OUTM(m,v) \
        out_dword_masked_ns(HWIO_TCSR_REFGEN_QLINK_ENABLE_ADDR,m,v,HWIO_TCSR_REFGEN_QLINK_ENABLE_IN)
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_REFGEN_QLINK_ENABLE_BMSK                                                              0x1
#define HWIO_TCSR_REFGEN_QLINK_ENABLE_REFGEN_QLINK_ENABLE_SHFT                                                              0x0


#endif /* __SECBOOT_HWIO_H__ */
